Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.58 97.84 93.79 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2858
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T270 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4284520855 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:53 PM PDT 24 44348425 ps
T280 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.576811614 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 43282527 ps
T245 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1005360400 Jul 18 05:35:38 PM PDT 24 Jul 18 05:35:40 PM PDT 24 65551193 ps
T2770 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2644967470 Jul 18 05:35:51 PM PDT 24 Jul 18 05:35:56 PM PDT 24 47449429 ps
T243 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2971739811 Jul 18 05:35:18 PM PDT 24 Jul 18 05:35:27 PM PDT 24 122009948 ps
T2771 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1956369643 Jul 18 05:35:19 PM PDT 24 Jul 18 05:35:28 PM PDT 24 451692781 ps
T287 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.435430929 Jul 18 05:35:16 PM PDT 24 Jul 18 05:35:25 PM PDT 24 576022637 ps
T281 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3381045878 Jul 18 05:35:24 PM PDT 24 Jul 18 05:35:31 PM PDT 24 62045838 ps
T286 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1764822914 Jul 18 05:35:43 PM PDT 24 Jul 18 05:35:48 PM PDT 24 496992419 ps
T2772 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.656223707 Jul 18 05:35:46 PM PDT 24 Jul 18 05:35:50 PM PDT 24 124322096 ps
T2773 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2439079212 Jul 18 05:35:45 PM PDT 24 Jul 18 05:35:51 PM PDT 24 1288396940 ps
T274 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1215550289 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:00 PM PDT 24 44892345 ps
T2774 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.146530018 Jul 18 05:35:53 PM PDT 24 Jul 18 05:36:00 PM PDT 24 104995502 ps
T244 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4177564776 Jul 18 05:35:26 PM PDT 24 Jul 18 05:35:35 PM PDT 24 369031646 ps
T2775 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1338256051 Jul 18 05:35:30 PM PDT 24 Jul 18 05:35:34 PM PDT 24 89170535 ps
T2776 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1121222933 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:58 PM PDT 24 157267607 ps
T268 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4197927991 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 68666117 ps
T246 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.406481789 Jul 18 05:35:47 PM PDT 24 Jul 18 05:35:50 PM PDT 24 174043696 ps
T2777 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4033807561 Jul 18 05:35:50 PM PDT 24 Jul 18 05:35:55 PM PDT 24 43187545 ps
T2778 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2513097095 Jul 18 05:35:34 PM PDT 24 Jul 18 05:35:37 PM PDT 24 71625767 ps
T2779 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1754582947 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:55 PM PDT 24 251733916 ps
T2780 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3362252189 Jul 18 05:35:24 PM PDT 24 Jul 18 05:35:31 PM PDT 24 100751447 ps
T289 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4091068487 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:58 PM PDT 24 678739187 ps
T2781 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.637635647 Jul 18 05:35:48 PM PDT 24 Jul 18 05:35:52 PM PDT 24 44075147 ps
T288 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1637203934 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:58 PM PDT 24 1056997321 ps
T2782 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4011336443 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:53 PM PDT 24 40022791 ps
T2783 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3533553841 Jul 18 05:35:44 PM PDT 24 Jul 18 05:35:47 PM PDT 24 122986945 ps
T2784 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3042759966 Jul 18 05:35:24 PM PDT 24 Jul 18 05:35:31 PM PDT 24 115681530 ps
T2785 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1806117134 Jul 18 05:35:25 PM PDT 24 Jul 18 05:35:32 PM PDT 24 86978570 ps
T2786 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1464371127 Jul 18 05:35:48 PM PDT 24 Jul 18 05:35:57 PM PDT 24 1387422445 ps
T2787 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1496316916 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:03 PM PDT 24 147179468 ps
T278 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.727264 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:00 PM PDT 24 83826370 ps
T2788 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3736765754 Jul 18 05:35:40 PM PDT 24 Jul 18 05:35:42 PM PDT 24 107525119 ps
T2789 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1019550011 Jul 18 05:35:53 PM PDT 24 Jul 18 05:35:59 PM PDT 24 52916991 ps
T284 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2407417282 Jul 18 05:35:35 PM PDT 24 Jul 18 05:35:42 PM PDT 24 1141683131 ps
T2790 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2346381833 Jul 18 05:35:46 PM PDT 24 Jul 18 05:35:49 PM PDT 24 119383176 ps
T2791 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.508436703 Jul 18 05:35:47 PM PDT 24 Jul 18 05:35:50 PM PDT 24 123023796 ps
T2792 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1972754101 Jul 18 05:35:25 PM PDT 24 Jul 18 05:35:33 PM PDT 24 99459481 ps
T276 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.519656557 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 39714666 ps
T2793 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.489426351 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:53 PM PDT 24 39294717 ps
T2794 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2446166518 Jul 18 05:35:32 PM PDT 24 Jul 18 05:35:35 PM PDT 24 98934702 ps
T2795 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1447760447 Jul 18 05:35:24 PM PDT 24 Jul 18 05:35:33 PM PDT 24 350316976 ps
T2796 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.315351031 Jul 18 05:35:46 PM PDT 24 Jul 18 05:35:49 PM PDT 24 310376946 ps
T2797 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4233823486 Jul 18 05:35:27 PM PDT 24 Jul 18 05:35:33 PM PDT 24 42426068 ps
T2798 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.465020045 Jul 18 05:35:53 PM PDT 24 Jul 18 05:36:00 PM PDT 24 79152969 ps
T2799 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2147936087 Jul 18 05:35:25 PM PDT 24 Jul 18 05:35:34 PM PDT 24 131305702 ps
T2800 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2786491285 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:00 PM PDT 24 51854569 ps
T2801 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1608333939 Jul 18 05:35:23 PM PDT 24 Jul 18 05:35:33 PM PDT 24 718223810 ps
T2802 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3370882933 Jul 18 05:35:51 PM PDT 24 Jul 18 05:35:59 PM PDT 24 127274201 ps
T2803 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1003827066 Jul 18 05:35:53 PM PDT 24 Jul 18 05:36:00 PM PDT 24 31938251 ps
T2804 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.824733586 Jul 18 05:35:53 PM PDT 24 Jul 18 05:36:00 PM PDT 24 73178181 ps
T2805 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.895432022 Jul 18 05:36:00 PM PDT 24 Jul 18 05:36:05 PM PDT 24 119310656 ps
T2806 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.727904353 Jul 18 05:35:35 PM PDT 24 Jul 18 05:35:37 PM PDT 24 75472086 ps
T2807 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1544889289 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:02 PM PDT 24 65257789 ps
T2808 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2970086089 Jul 18 05:35:25 PM PDT 24 Jul 18 05:35:37 PM PDT 24 503294293 ps
T2809 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.633155871 Jul 18 05:36:00 PM PDT 24 Jul 18 05:36:04 PM PDT 24 115262146 ps
T282 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2268390480 Jul 18 05:35:23 PM PDT 24 Jul 18 05:35:34 PM PDT 24 1116131646 ps
T2810 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4217477359 Jul 18 05:35:26 PM PDT 24 Jul 18 05:35:33 PM PDT 24 169472488 ps
T2811 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.17093920 Jul 18 05:35:41 PM PDT 24 Jul 18 05:35:43 PM PDT 24 66312135 ps
T2812 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3779792660 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 141014485 ps
T2813 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2611863930 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:59 PM PDT 24 111232607 ps
T2814 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.523144169 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:00 PM PDT 24 78632282 ps
T2815 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2359237651 Jul 18 05:35:23 PM PDT 24 Jul 18 05:35:31 PM PDT 24 185654901 ps
T2816 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3967174230 Jul 18 05:35:20 PM PDT 24 Jul 18 05:35:31 PM PDT 24 713061295 ps
T2817 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3930744473 Jul 18 05:35:49 PM PDT 24 Jul 18 05:35:53 PM PDT 24 103072640 ps
T2818 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3357154944 Jul 18 05:35:32 PM PDT 24 Jul 18 05:35:36 PM PDT 24 94544394 ps
T2819 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3909796592 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:58 PM PDT 24 32631497 ps
T2820 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1522528563 Jul 18 05:35:26 PM PDT 24 Jul 18 05:35:35 PM PDT 24 313534773 ps
T2821 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1752222187 Jul 18 05:35:21 PM PDT 24 Jul 18 05:35:27 PM PDT 24 66475083 ps
T2822 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.844660465 Jul 18 05:35:40 PM PDT 24 Jul 18 05:35:41 PM PDT 24 42717308 ps
T2823 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.606990772 Jul 18 05:35:19 PM PDT 24 Jul 18 05:35:31 PM PDT 24 1004248682 ps
T2824 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3010137007 Jul 18 05:36:00 PM PDT 24 Jul 18 05:36:04 PM PDT 24 95512818 ps
T2825 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2589706864 Jul 18 05:35:30 PM PDT 24 Jul 18 05:35:35 PM PDT 24 84994522 ps
T2826 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.175203502 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 62749089 ps
T2827 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.925173614 Jul 18 05:35:48 PM PDT 24 Jul 18 05:35:52 PM PDT 24 78733572 ps
T2828 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2164970927 Jul 18 05:35:55 PM PDT 24 Jul 18 05:36:02 PM PDT 24 39865109 ps
T2829 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2468860070 Jul 18 05:35:18 PM PDT 24 Jul 18 05:35:26 PM PDT 24 83566218 ps
T2830 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1612281958 Jul 18 05:35:59 PM PDT 24 Jul 18 05:36:03 PM PDT 24 66115651 ps
T2831 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2328643589 Jul 18 05:35:47 PM PDT 24 Jul 18 05:35:52 PM PDT 24 91448667 ps
T2832 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1192753266 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:58 PM PDT 24 39386573 ps
T2833 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.640482069 Jul 18 05:35:53 PM PDT 24 Jul 18 05:35:59 PM PDT 24 33366372 ps
T2834 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3829149981 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:59 PM PDT 24 187750737 ps
T2835 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3321362513 Jul 18 05:35:43 PM PDT 24 Jul 18 05:35:45 PM PDT 24 39398223 ps
T2836 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.993659014 Jul 18 05:35:26 PM PDT 24 Jul 18 05:35:33 PM PDT 24 86949505 ps
T2837 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2848961508 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:57 PM PDT 24 35732033 ps
T2838 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.757048263 Jul 18 05:35:47 PM PDT 24 Jul 18 05:35:50 PM PDT 24 94958274 ps
T2839 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2716967873 Jul 18 05:35:53 PM PDT 24 Jul 18 05:36:00 PM PDT 24 474248269 ps
T2840 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.658264827 Jul 18 05:35:20 PM PDT 24 Jul 18 05:35:27 PM PDT 24 74438746 ps
T2841 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4235504962 Jul 18 05:35:43 PM PDT 24 Jul 18 05:35:45 PM PDT 24 161307057 ps
T2842 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.671328201 Jul 18 05:35:47 PM PDT 24 Jul 18 05:35:50 PM PDT 24 44313677 ps
T2843 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2168595630 Jul 18 05:35:18 PM PDT 24 Jul 18 05:35:30 PM PDT 24 61915710 ps
T2844 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2220228393 Jul 18 05:35:48 PM PDT 24 Jul 18 05:35:54 PM PDT 24 243075826 ps
T2845 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2913898417 Jul 18 05:35:25 PM PDT 24 Jul 18 05:35:31 PM PDT 24 56134961 ps
T2846 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1678082047 Jul 18 05:35:21 PM PDT 24 Jul 18 05:35:28 PM PDT 24 52643347 ps
T2847 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1262965885 Jul 18 05:35:26 PM PDT 24 Jul 18 05:35:34 PM PDT 24 178379964 ps
T2848 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.754247719 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 193306559 ps
T2849 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.148016248 Jul 18 05:35:25 PM PDT 24 Jul 18 05:35:32 PM PDT 24 88195873 ps
T2850 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.501663183 Jul 18 05:35:31 PM PDT 24 Jul 18 05:35:36 PM PDT 24 196521261 ps
T2851 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.175319482 Jul 18 05:35:25 PM PDT 24 Jul 18 05:35:32 PM PDT 24 236722828 ps
T283 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3850460853 Jul 18 05:35:39 PM PDT 24 Jul 18 05:35:45 PM PDT 24 1134926757 ps
T2852 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1846098285 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:01 PM PDT 24 38519584 ps
T2853 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1346932302 Jul 18 05:35:38 PM PDT 24 Jul 18 05:35:39 PM PDT 24 38423344 ps
T2854 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.883550480 Jul 18 05:35:20 PM PDT 24 Jul 18 05:35:28 PM PDT 24 178190487 ps
T2855 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.665902270 Jul 18 05:35:20 PM PDT 24 Jul 18 05:35:35 PM PDT 24 1908958261 ps
T285 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1242080374 Jul 18 05:35:52 PM PDT 24 Jul 18 05:35:59 PM PDT 24 347098605 ps
T2856 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.32554817 Jul 18 05:35:46 PM PDT 24 Jul 18 05:35:48 PM PDT 24 69990303 ps
T2857 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.660180746 Jul 18 05:35:14 PM PDT 24 Jul 18 05:35:23 PM PDT 24 437096361 ps
T2858 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3203229898 Jul 18 05:35:54 PM PDT 24 Jul 18 05:36:02 PM PDT 24 128323694 ps

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.3107280403
Short name T3
Test name
Test status
Simulation time 852584877 ps
CPU time 1.91 seconds
Started Jul 18 05:44:11 PM PDT 24
Finished Jul 18 05:44:18 PM PDT 24
Peak memory 206736 kb
Host smart-e0c40662-11c0-410f-9908-ce4e3f570bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31072
80403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.3107280403
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1872524654
Short name T85
Test name
Test status
Simulation time 9006266036 ps
CPU time 61.64 seconds
Started Jul 18 05:47:32 PM PDT 24
Finished Jul 18 05:48:48 PM PDT 24
Peak memory 206896 kb
Host smart-d02eccf4-6c56-4d50-b78c-cfc2989bdde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18725
24654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1872524654
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1659134622
Short name T199
Test name
Test status
Simulation time 48499693 ps
CPU time 0.69 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 206280 kb
Host smart-fff84bac-e166-4e55-b14b-df77f51f350e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1659134622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1659134622
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1892993187
Short name T1
Test name
Test status
Simulation time 13372473642 ps
CPU time 14.02 seconds
Started Jul 18 05:45:39 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206900 kb
Host smart-5009c0f2-3502-412b-8220-b0d849037fe1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1892993187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1892993187
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4109071073
Short name T190
Test name
Test status
Simulation time 1182793578 ps
CPU time 5.62 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 206444 kb
Host smart-f01aeefc-e4f1-4041-bee5-adf1a25e0aaf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4109071073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4109071073
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1604675662
Short name T38
Test name
Test status
Simulation time 9894669632 ps
CPU time 58.37 seconds
Started Jul 18 05:43:16 PM PDT 24
Finished Jul 18 05:44:31 PM PDT 24
Peak memory 206952 kb
Host smart-cabf2b37-2537-4b7f-af5a-9feca93dc742
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1604675662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1604675662
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2298098874
Short name T20
Test name
Test status
Simulation time 366884957 ps
CPU time 1.1 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:57 PM PDT 24
Peak memory 206640 kb
Host smart-70df1fff-3f24-49f7-8b2a-e22edcde5cf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22980
98874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2298098874
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1122099013
Short name T99
Test name
Test status
Simulation time 208992348 ps
CPU time 0.9 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206624 kb
Host smart-7d746c3a-3606-4390-9e52-75902a369c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
99013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1122099013
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2267572748
Short name T197
Test name
Test status
Simulation time 58583920 ps
CPU time 0.7 seconds
Started Jul 18 05:35:50 PM PDT 24
Finished Jul 18 05:35:54 PM PDT 24
Peak memory 206244 kb
Host smart-352c6a19-f49d-4f47-bb93-8f76aa8dc30a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2267572748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2267572748
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.2471320043
Short name T88
Test name
Test status
Simulation time 11628192477 ps
CPU time 41.95 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206888 kb
Host smart-d4bf1a1e-128f-41fe-a961-da28f8740f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24713
20043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.2471320043
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.3821303308
Short name T94
Test name
Test status
Simulation time 142799492 ps
CPU time 0.79 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206656 kb
Host smart-9b2a5e91-b27e-4958-956a-bfbf5c39cbde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38213
03308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.3821303308
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3372757919
Short name T214
Test name
Test status
Simulation time 106835508 ps
CPU time 2.97 seconds
Started Jul 18 05:35:17 PM PDT 24
Finished Jul 18 05:35:26 PM PDT 24
Peak memory 214804 kb
Host smart-fb61c45f-ad9e-4764-8c4a-163436bbb76c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3372757919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3372757919
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.664410733
Short name T186
Test name
Test status
Simulation time 1195644500 ps
CPU time 2.07 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:21 PM PDT 24
Peak memory 225548 kb
Host smart-16c5d1cc-c640-4ead-82bd-577cb3d78337
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=664410733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.664410733
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2897440312
Short name T104
Test name
Test status
Simulation time 204683885 ps
CPU time 0.83 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:57 PM PDT 24
Peak memory 206660 kb
Host smart-68f71af4-c7ea-43ec-87bb-e943443c88bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
40312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2897440312
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.2047305059
Short name T24
Test name
Test status
Simulation time 79042168 ps
CPU time 0.76 seconds
Started Jul 18 05:47:02 PM PDT 24
Finished Jul 18 05:47:17 PM PDT 24
Peak memory 206628 kb
Host smart-90600c88-dacb-43c0-9b16-62580561ac50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20473
05059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.2047305059
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1036782633
Short name T92
Test name
Test status
Simulation time 171535976 ps
CPU time 0.83 seconds
Started Jul 18 05:49:22 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206620 kb
Host smart-5b4a66a3-0979-4617-913b-bb0374b107d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10367
82633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1036782633
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.3952312129
Short name T78
Test name
Test status
Simulation time 363349081 ps
CPU time 1 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:34 PM PDT 24
Peak memory 206648 kb
Host smart-c183802a-643a-43b3-a4fd-0c24ae20a723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39523
12129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.3952312129
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.224691474
Short name T43
Test name
Test status
Simulation time 20154727572 ps
CPU time 191.97 seconds
Started Jul 18 05:43:35 PM PDT 24
Finished Jul 18 05:47:02 PM PDT 24
Peak memory 207008 kb
Host smart-05173267-e8e5-4da8-91b8-67100b1ea7b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=224691474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.224691474
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.1119870752
Short name T45
Test name
Test status
Simulation time 20179959162 ps
CPU time 21.01 seconds
Started Jul 18 05:43:31 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206744 kb
Host smart-6214ad13-c4b7-498b-803c-c9a8b398eb03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11198
70752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1119870752
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.2844688497
Short name T918
Test name
Test status
Simulation time 351547572 ps
CPU time 1.17 seconds
Started Jul 18 05:45:20 PM PDT 24
Finished Jul 18 05:45:39 PM PDT 24
Peak memory 206636 kb
Host smart-04dfdbb7-ef58-4599-bb52-4a6cfeb08450
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28446
88497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.2844688497
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.2786491285
Short name T2800
Test name
Test status
Simulation time 51854569 ps
CPU time 0.7 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206292 kb
Host smart-b4fb0ab7-a637-498d-accf-9aed7d714744
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2786491285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.2786491285
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.300432448
Short name T238
Test name
Test status
Simulation time 48026193 ps
CPU time 0.88 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:51 PM PDT 24
Peak memory 206272 kb
Host smart-1b962869-e6ca-415b-84de-0fc74e23a184
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=300432448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.300432448
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.466286494
Short name T271
Test name
Test status
Simulation time 179093052 ps
CPU time 0.79 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206656 kb
Host smart-90503db6-f9fc-4561-af64-e115ed710384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46628
6494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.466286494
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.1764822914
Short name T286
Test name
Test status
Simulation time 496992419 ps
CPU time 4.33 seconds
Started Jul 18 05:35:43 PM PDT 24
Finished Jul 18 05:35:48 PM PDT 24
Peak memory 206556 kb
Host smart-bc10a669-1c95-4c89-a97d-240ed7228bff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1764822914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.1764822914
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2306611956
Short name T200
Test name
Test status
Simulation time 76962678 ps
CPU time 0.73 seconds
Started Jul 18 05:35:40 PM PDT 24
Finished Jul 18 05:35:42 PM PDT 24
Peak memory 206272 kb
Host smart-b03e7540-dd65-4df4-b09d-0bb32ea84cab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306611956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2306611956
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.3162087407
Short name T73
Test name
Test status
Simulation time 222954641 ps
CPU time 0.9 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206660 kb
Host smart-c7a94b9b-1b9d-4483-bba5-68ffc80830c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31620
87407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.3162087407
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_device_address.809960414
Short name T98
Test name
Test status
Simulation time 18764316166 ps
CPU time 35.26 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:49:22 PM PDT 24
Peak memory 206828 kb
Host smart-159fa683-b7ba-4f42-a79c-7c3d14822db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80996
0414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.809960414
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.563470867
Short name T66
Test name
Test status
Simulation time 473711605 ps
CPU time 1.33 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 206636 kb
Host smart-97cbb71e-05c5-49f5-8a10-a44bd6a737c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56347
0867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.563470867
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.898265647
Short name T266
Test name
Test status
Simulation time 53984906 ps
CPU time 0.72 seconds
Started Jul 18 05:35:32 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206084 kb
Host smart-b73e6bc7-d0fd-45f1-955f-4439a570d4f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=898265647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.898265647
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3850460853
Short name T283
Test name
Test status
Simulation time 1134926757 ps
CPU time 5.33 seconds
Started Jul 18 05:35:39 PM PDT 24
Finished Jul 18 05:35:45 PM PDT 24
Peak memory 206476 kb
Host smart-1382885c-8fd7-45dd-bb42-2d695b8ca7ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3850460853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3850460853
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.2167649115
Short name T599
Test name
Test status
Simulation time 82527077 ps
CPU time 0.74 seconds
Started Jul 18 05:45:44 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 206708 kb
Host smart-e2c961dd-af3e-4e05-a31f-52daf15bfc68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2167649115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.2167649115
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.3346259682
Short name T152
Test name
Test status
Simulation time 10189253970 ps
CPU time 55.45 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 206936 kb
Host smart-45e3e438-6984-4a1c-9b27-2770a15e7fd1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3346259682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.3346259682
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.878180493
Short name T589
Test name
Test status
Simulation time 4353088161 ps
CPU time 5 seconds
Started Jul 18 05:45:40 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206752 kb
Host smart-67d1a9f9-d496-4a31-acf8-ef408cd320c3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=878180493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.878180493
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.4150443700
Short name T74
Test name
Test status
Simulation time 7156878136 ps
CPU time 204.05 seconds
Started Jul 18 05:45:48 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206832 kb
Host smart-7d7c4941-bee3-4ff6-a7e8-107ef44d13b8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4150443700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.4150443700
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2603572706
Short name T56
Test name
Test status
Simulation time 255023051 ps
CPU time 0.94 seconds
Started Jul 18 05:43:24 PM PDT 24
Finished Jul 18 05:43:40 PM PDT 24
Peak memory 206664 kb
Host smart-be0baa03-19f5-405a-8bbe-6a4518e943dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26035
72706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2603572706
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1182289801
Short name T87
Test name
Test status
Simulation time 147096006 ps
CPU time 0.77 seconds
Started Jul 18 05:43:07 PM PDT 24
Finished Jul 18 05:43:25 PM PDT 24
Peak memory 206632 kb
Host smart-9ef7da76-6911-4415-8215-fbf580c53230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11822
89801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1182289801
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.1242080374
Short name T285
Test name
Test status
Simulation time 347098605 ps
CPU time 2.37 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 206500 kb
Host smart-86b9093b-3f1e-4cfa-b002-d49e4355a74d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1242080374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.1242080374
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.241278237
Short name T5
Test name
Test status
Simulation time 5863005223 ps
CPU time 55.74 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:51:25 PM PDT 24
Peak memory 206844 kb
Host smart-55ca2f52-7bde-4814-b03e-cb78c24d3172
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=241278237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.241278237
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2287287611
Short name T209
Test name
Test status
Simulation time 139372048 ps
CPU time 1.75 seconds
Started Jul 18 05:35:20 PM PDT 24
Finished Jul 18 05:35:28 PM PDT 24
Peak memory 222288 kb
Host smart-cb9255b7-fe6b-4191-aae0-a550701c2aed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2287287611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2287287611
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_device_address.3728972705
Short name T95
Test name
Test status
Simulation time 11073689597 ps
CPU time 19.91 seconds
Started Jul 18 05:43:22 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 206904 kb
Host smart-32c16e49-9a79-45f2-b8f4-7b765a3acec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37289
72705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.3728972705
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.4115655990
Short name T156
Test name
Test status
Simulation time 9792336232 ps
CPU time 175.64 seconds
Started Jul 18 05:43:18 PM PDT 24
Finished Jul 18 05:46:31 PM PDT 24
Peak memory 206956 kb
Host smart-bfdff667-51aa-4613-86fb-ddc489adb1be
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4115655990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.4115655990
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2682482710
Short name T77
Test name
Test status
Simulation time 148714903 ps
CPU time 0.82 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:58 PM PDT 24
Peak memory 206620 kb
Host smart-eb04bdbe-aae1-49cf-9530-d65acbca3260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26824
82710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2682482710
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.3393706804
Short name T858
Test name
Test status
Simulation time 33911299 ps
CPU time 0.64 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206636 kb
Host smart-5287cac1-5625-4360-8c00-dd726de57d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33937
06804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.3393706804
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1803122194
Short name T679
Test name
Test status
Simulation time 149457283 ps
CPU time 0.86 seconds
Started Jul 18 05:45:55 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206628 kb
Host smart-6d6e9064-5df4-4183-913e-7f2e612572e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18031
22194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1803122194
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.2836948009
Short name T1854
Test name
Test status
Simulation time 23371515227 ps
CPU time 27.52 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:29 PM PDT 24
Peak memory 206852 kb
Host smart-cb1443af-f857-4a1b-8794-0010d0cdab85
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2836948009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.2836948009
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1888748520
Short name T516
Test name
Test status
Simulation time 339887688 ps
CPU time 2.04 seconds
Started Jul 18 05:45:26 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206724 kb
Host smart-fdbcd3ec-8d2e-4a87-8f17-867642eb4afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18887
48520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1888748520
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.755318950
Short name T47
Test name
Test status
Simulation time 147096749 ps
CPU time 0.78 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:43:52 PM PDT 24
Peak memory 206652 kb
Host smart-f92bd3a7-922e-4dcb-8665-03f86a4bba77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75531
8950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.755318950
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3812681933
Short name T51
Test name
Test status
Simulation time 180562998 ps
CPU time 0.87 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:18 PM PDT 24
Peak memory 206672 kb
Host smart-6f3ed220-4af5-4067-a54c-9987934180c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38126
81933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3812681933
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1599859636
Short name T64
Test name
Test status
Simulation time 4181435599 ps
CPU time 9.49 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:26 PM PDT 24
Peak memory 206916 kb
Host smart-f596c646-9d95-401a-be75-5e091753444d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15998
59636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1599859636
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.3146556794
Short name T65
Test name
Test status
Simulation time 173497429 ps
CPU time 0.84 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:15 PM PDT 24
Peak memory 206652 kb
Host smart-36308731-d0e8-40ee-9798-79309f4d0a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31465
56794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.3146556794
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.1849905142
Short name T4
Test name
Test status
Simulation time 5752023453 ps
CPU time 157.45 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206860 kb
Host smart-07644ea4-887e-40e0-8335-756324a83cbf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1849905142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.1849905142
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.4245794245
Short name T58
Test name
Test status
Simulation time 179582755 ps
CPU time 0.85 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:58 PM PDT 24
Peak memory 206620 kb
Host smart-3602cea6-06ed-4c70-a229-2853d412e6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42457
94245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.4245794245
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.276471239
Short name T129
Test name
Test status
Simulation time 186531370 ps
CPU time 0.82 seconds
Started Jul 18 05:43:31 PM PDT 24
Finished Jul 18 05:43:47 PM PDT 24
Peak memory 206624 kb
Host smart-2fce4a67-f084-4416-a637-9761f8699c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27647
1239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.276471239
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.2020432922
Short name T2558
Test name
Test status
Simulation time 433036334 ps
CPU time 1.4 seconds
Started Jul 18 05:43:20 PM PDT 24
Finished Jul 18 05:43:38 PM PDT 24
Peak memory 206640 kb
Host smart-6da1dbe1-ed29-4176-9fa1-999a4d082814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20204
32922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.2020432922
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.1960522597
Short name T140
Test name
Test status
Simulation time 203615426 ps
CPU time 0.84 seconds
Started Jul 18 05:43:41 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 206644 kb
Host smart-658366dc-81d9-44ff-a0d3-c9015bf02866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19605
22597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.1960522597
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.4154111517
Short name T117
Test name
Test status
Simulation time 208093852 ps
CPU time 0.85 seconds
Started Jul 18 05:45:23 PM PDT 24
Finished Jul 18 05:45:41 PM PDT 24
Peak memory 206632 kb
Host smart-21f5fe9a-591a-4512-8e04-a8730a75114c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41541
11517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.4154111517
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.982291788
Short name T137
Test name
Test status
Simulation time 200962144 ps
CPU time 0.85 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206616 kb
Host smart-1bda80a7-cdbf-485f-991f-463c4f7ace5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98229
1788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.982291788
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.3989375390
Short name T119
Test name
Test status
Simulation time 215193676 ps
CPU time 0.88 seconds
Started Jul 18 05:45:40 PM PDT 24
Finished Jul 18 05:45:56 PM PDT 24
Peak memory 206636 kb
Host smart-ce92bc3f-2504-4261-8866-a930afe514d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39893
75390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.3989375390
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.182917770
Short name T136
Test name
Test status
Simulation time 191382574 ps
CPU time 0.87 seconds
Started Jul 18 05:46:00 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206648 kb
Host smart-c54ffb16-b888-4586-9fc6-0e814a8f6126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18291
7770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.182917770
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.1877619065
Short name T123
Test name
Test status
Simulation time 229130669 ps
CPU time 0.87 seconds
Started Jul 18 05:46:14 PM PDT 24
Finished Jul 18 05:46:19 PM PDT 24
Peak memory 206648 kb
Host smart-b5db3707-0830-46d1-83d1-b5f038cd7ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18776
19065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.1877619065
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.82902092
Short name T125
Test name
Test status
Simulation time 178801084 ps
CPU time 0.89 seconds
Started Jul 18 05:43:55 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 206616 kb
Host smart-4de70dd2-541d-4102-a090-96bae2459761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82902
092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.82902092
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3463599114
Short name T130
Test name
Test status
Simulation time 244530955 ps
CPU time 0.94 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:44:22 PM PDT 24
Peak memory 206640 kb
Host smart-d0e52133-ca59-4341-8c58-fb46d6552f62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34635
99114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3463599114
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.2826727221
Short name T143
Test name
Test status
Simulation time 265703946 ps
CPU time 0.94 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:54 PM PDT 24
Peak memory 206660 kb
Host smart-f8abc084-7070-433b-8cf8-14084c262398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28267
27221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.2826727221
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2430862788
Short name T144
Test name
Test status
Simulation time 236600751 ps
CPU time 0.9 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:10 PM PDT 24
Peak memory 206640 kb
Host smart-ebe72bc0-89a5-4859-ade2-d0d3d2743a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24308
62788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2430862788
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.4177564776
Short name T244
Test name
Test status
Simulation time 369031646 ps
CPU time 3.7 seconds
Started Jul 18 05:35:26 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206316 kb
Host smart-fd13fdf7-4522-4051-8e66-6cf7f0eb5bd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4177564776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.4177564776
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.665902270
Short name T2855
Test name
Test status
Simulation time 1908958261 ps
CPU time 8.94 seconds
Started Jul 18 05:35:20 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206548 kb
Host smart-c2441438-8822-4254-8ccb-48c6712cbbab
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=665902270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.665902270
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1752222187
Short name T2821
Test name
Test status
Simulation time 66475083 ps
CPU time 0.81 seconds
Started Jul 18 05:35:21 PM PDT 24
Finished Jul 18 05:35:27 PM PDT 24
Peak memory 206264 kb
Host smart-36045eee-a8ec-4291-8600-c7190bd0d883
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1752222187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1752222187
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3368194111
Short name T2763
Test name
Test status
Simulation time 123004546 ps
CPU time 1.26 seconds
Started Jul 18 05:35:32 PM PDT 24
Finished Jul 18 05:35:36 PM PDT 24
Peak memory 214684 kb
Host smart-d4dfdce2-e71b-4470-ad35-4b47b080eaa9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368194111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3368194111
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1678082047
Short name T2846
Test name
Test status
Simulation time 52643347 ps
CPU time 1 seconds
Started Jul 18 05:35:21 PM PDT 24
Finished Jul 18 05:35:28 PM PDT 24
Peak memory 206384 kb
Host smart-70505edf-e366-4be2-8bee-6f36b0e1899f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1678082047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1678082047
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4233823486
Short name T2797
Test name
Test status
Simulation time 42426068 ps
CPU time 0.68 seconds
Started Jul 18 05:35:27 PM PDT 24
Finished Jul 18 05:35:33 PM PDT 24
Peak memory 206228 kb
Host smart-412f7e27-4fc6-4083-85dc-55a92a1b3ed9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4233823486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4233823486
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.1262965885
Short name T2847
Test name
Test status
Simulation time 178379964 ps
CPU time 2.44 seconds
Started Jul 18 05:35:26 PM PDT 24
Finished Jul 18 05:35:34 PM PDT 24
Peak memory 214692 kb
Host smart-beec93fc-c027-41f8-aa1d-03305f50c607
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1262965885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.1262965885
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.993738005
Short name T2761
Test name
Test status
Simulation time 154955640 ps
CPU time 4.13 seconds
Started Jul 18 05:35:29 PM PDT 24
Finished Jul 18 05:35:37 PM PDT 24
Peak memory 206308 kb
Host smart-4e3fdf17-c484-4441-bafc-bb29cca3ea70
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=993738005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.993738005
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.3042759966
Short name T2784
Test name
Test status
Simulation time 115681530 ps
CPU time 1.56 seconds
Started Jul 18 05:35:24 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 206504 kb
Host smart-da7b9c1b-be96-4a01-af56-b7aaa33676f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3042759966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.3042759966
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.1141633551
Short name T192
Test name
Test status
Simulation time 409636002 ps
CPU time 2.77 seconds
Started Jul 18 05:35:21 PM PDT 24
Finished Jul 18 05:35:30 PM PDT 24
Peak memory 206512 kb
Host smart-0b8ae37b-8280-42e7-ae5f-6d21af3efda0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1141633551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.1141633551
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3981778362
Short name T241
Test name
Test status
Simulation time 146099994 ps
CPU time 3.22 seconds
Started Jul 18 05:35:26 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206408 kb
Host smart-cab0adae-7a7d-4c6a-b9a7-df660a15c016
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3981778362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3981778362
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1416233799
Short name T236
Test name
Test status
Simulation time 166601108 ps
CPU time 3.86 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206288 kb
Host smart-96389945-4be9-46c4-978e-24ceadc6a23d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1416233799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1416233799
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.455722598
Short name T2755
Test name
Test status
Simulation time 128783792 ps
CPU time 0.84 seconds
Started Jul 18 05:35:24 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 206276 kb
Host smart-f5728570-fb92-45c7-b704-1ed8cde0259a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=455722598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.455722598
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.993659014
Short name T2836
Test name
Test status
Simulation time 86949505 ps
CPU time 1.91 seconds
Started Jul 18 05:35:26 PM PDT 24
Finished Jul 18 05:35:33 PM PDT 24
Peak memory 214560 kb
Host smart-95b986fa-76f8-4922-bf45-67cc4db05a89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=993659014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.993659014
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2446166518
Short name T2794
Test name
Test status
Simulation time 98934702 ps
CPU time 0.87 seconds
Started Jul 18 05:35:32 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206224 kb
Host smart-45b1ea0f-0ec7-4fb4-b273-58df759b5a04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2446166518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2446166518
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.727904353
Short name T2806
Test name
Test status
Simulation time 75472086 ps
CPU time 0.72 seconds
Started Jul 18 05:35:35 PM PDT 24
Finished Jul 18 05:35:37 PM PDT 24
Peak memory 206200 kb
Host smart-1c3eda55-387f-4792-b413-6eaf7d69951d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=727904353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.727904353
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.175319482
Short name T2851
Test name
Test status
Simulation time 236722828 ps
CPU time 2.42 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:32 PM PDT 24
Peak memory 214636 kb
Host smart-42509b08-8c26-4403-8b4c-51e765c50749
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=175319482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.175319482
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.3193794735
Short name T2757
Test name
Test status
Simulation time 103932638 ps
CPU time 2.6 seconds
Started Jul 18 05:35:29 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206308 kb
Host smart-6a3369c9-a6bb-49e9-a2c6-d29598e72ada
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3193794735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.3193794735
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.239095738
Short name T2766
Test name
Test status
Simulation time 172555510 ps
CPU time 1.6 seconds
Started Jul 18 05:35:16 PM PDT 24
Finished Jul 18 05:35:23 PM PDT 24
Peak memory 206524 kb
Host smart-b2f2e257-3eb0-402c-bdff-478b5520454c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=239095738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.239095738
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.1522528563
Short name T2820
Test name
Test status
Simulation time 313534773 ps
CPU time 3.37 seconds
Started Jul 18 05:35:26 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 222164 kb
Host smart-32e61dc6-76f2-4d02-91d5-932a03e48d2d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1522528563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.1522528563
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.660180746
Short name T2857
Test name
Test status
Simulation time 437096361 ps
CPU time 2.59 seconds
Started Jul 18 05:35:14 PM PDT 24
Finished Jul 18 05:35:23 PM PDT 24
Peak memory 206552 kb
Host smart-37b3ca9f-5e71-4922-ab86-7c53af0621e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=660180746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.660180746
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.2328643589
Short name T2831
Test name
Test status
Simulation time 91448667 ps
CPU time 1.95 seconds
Started Jul 18 05:35:47 PM PDT 24
Finished Jul 18 05:35:52 PM PDT 24
Peak memory 214696 kb
Host smart-98a6e213-c027-4d72-95d6-57fa3618c84d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328643589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.2328643589
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.637635647
Short name T2781
Test name
Test status
Simulation time 44075147 ps
CPU time 0.69 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:52 PM PDT 24
Peak memory 206248 kb
Host smart-8182b2e9-5118-4e0a-83c8-67537e6c7914
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=637635647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.637635647
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.4033485259
Short name T247
Test name
Test status
Simulation time 64681395 ps
CPU time 1.06 seconds
Started Jul 18 05:35:39 PM PDT 24
Finished Jul 18 05:35:41 PM PDT 24
Peak memory 206528 kb
Host smart-55e819b1-8e09-42f3-bc58-0f1e7b09c01b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4033485259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.4033485259
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3934600852
Short name T218
Test name
Test status
Simulation time 107508693 ps
CPU time 2.96 seconds
Started Jul 18 05:35:36 PM PDT 24
Finished Jul 18 05:35:40 PM PDT 24
Peak memory 214788 kb
Host smart-db9a51e1-e47c-428e-ae1b-29fbf592eb78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3934600852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3934600852
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.17093920
Short name T2811
Test name
Test status
Simulation time 66312135 ps
CPU time 1.17 seconds
Started Jul 18 05:35:41 PM PDT 24
Finished Jul 18 05:35:43 PM PDT 24
Peak memory 214688 kb
Host smart-91bf6025-56e0-4e24-b66b-3595614f459e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev
_csr_mem_rw_with_rand_reset.17093920
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.473444215
Short name T242
Test name
Test status
Simulation time 76337507 ps
CPU time 0.83 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206328 kb
Host smart-0b5cf243-c624-4770-b38e-6e9765387c31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=473444215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.473444215
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3736765754
Short name T2788
Test name
Test status
Simulation time 107525119 ps
CPU time 0.77 seconds
Started Jul 18 05:35:40 PM PDT 24
Finished Jul 18 05:35:42 PM PDT 24
Peak memory 206280 kb
Host smart-8238c6ae-0565-45fd-9562-80a6f1e420cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3736765754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3736765754
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3203229898
Short name T2858
Test name
Test status
Simulation time 128323694 ps
CPU time 1.22 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 206552 kb
Host smart-3efdfdfd-1612-4763-8b8a-150eb96af595
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3203229898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3203229898
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.895432022
Short name T2805
Test name
Test status
Simulation time 119310656 ps
CPU time 1.5 seconds
Started Jul 18 05:36:00 PM PDT 24
Finished Jul 18 05:36:05 PM PDT 24
Peak memory 206760 kb
Host smart-3ec3dd6b-b804-4dbf-a7a2-f83876a6c8bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=895432022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.895432022
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1725536256
Short name T261
Test name
Test status
Simulation time 393728993 ps
CPU time 2.83 seconds
Started Jul 18 05:35:38 PM PDT 24
Finished Jul 18 05:35:41 PM PDT 24
Peak memory 206480 kb
Host smart-05bb4cbb-bd05-4b30-92fc-faf233f58658
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1725536256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1725536256
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.570836126
Short name T215
Test name
Test status
Simulation time 220416253 ps
CPU time 1.97 seconds
Started Jul 18 05:35:44 PM PDT 24
Finished Jul 18 05:35:47 PM PDT 24
Peak memory 214680 kb
Host smart-b4f848e8-6547-40c7-a811-aa088e4bb43e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570836126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.570836126
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.523144169
Short name T2814
Test name
Test status
Simulation time 78632282 ps
CPU time 0.88 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206340 kb
Host smart-7a21994d-913e-4dac-82f0-70bc11be6e97
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=523144169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.523144169
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.2192225397
Short name T279
Test name
Test status
Simulation time 51014211 ps
CPU time 0.72 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 206296 kb
Host smart-1a136901-2767-45c8-bcc7-a2b14e2b1e7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2192225397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.2192225397
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1121222933
Short name T2776
Test name
Test status
Simulation time 157267607 ps
CPU time 1.24 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 206648 kb
Host smart-21ca9275-b65f-4bf8-8c66-f69949390eb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1121222933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1121222933
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2745276640
Short name T217
Test name
Test status
Simulation time 300232877 ps
CPU time 3.47 seconds
Started Jul 18 05:35:51 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 214720 kb
Host smart-470b7249-09d3-46e3-8b3b-5037e9652925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2745276640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2745276640
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1464371127
Short name T2786
Test name
Test status
Simulation time 1387422445 ps
CPU time 5.66 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 206524 kb
Host smart-1d6825ea-7236-4f2c-b255-10954c94d356
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1464371127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1464371127
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1347607005
Short name T2767
Test name
Test status
Simulation time 152212696 ps
CPU time 1.88 seconds
Started Jul 18 05:35:39 PM PDT 24
Finished Jul 18 05:35:41 PM PDT 24
Peak memory 214716 kb
Host smart-cf666826-4e7c-4fa9-b953-d31683e22b6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347607005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1347607005
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.925173614
Short name T2827
Test name
Test status
Simulation time 78733572 ps
CPU time 1.06 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:52 PM PDT 24
Peak memory 205692 kb
Host smart-ab62c247-bd3a-4180-8a87-81e1458e8e90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=925173614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.925173614
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.824733586
Short name T2804
Test name
Test status
Simulation time 73178181 ps
CPU time 0.7 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206240 kb
Host smart-8532670b-de4d-4001-8b6c-b6e6aa2977ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=824733586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.824733586
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2346381833
Short name T2790
Test name
Test status
Simulation time 119383176 ps
CPU time 1.27 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:49 PM PDT 24
Peak memory 206576 kb
Host smart-e5431357-863b-4f02-b617-d918484e213d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2346381833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2346381833
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3779792660
Short name T2812
Test name
Test status
Simulation time 141014485 ps
CPU time 1.66 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 222336 kb
Host smart-06ad24bc-79fb-41aa-8aab-b32e8425c87e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3779792660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3779792660
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1938420633
Short name T2759
Test name
Test status
Simulation time 77434222 ps
CPU time 1.16 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 216248 kb
Host smart-7f391b5a-ba6b-43cc-a6a6-9aee15e2eaa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938420633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1938420633
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1005360400
Short name T245
Test name
Test status
Simulation time 65551193 ps
CPU time 1.02 seconds
Started Jul 18 05:35:38 PM PDT 24
Finished Jul 18 05:35:40 PM PDT 24
Peak memory 206512 kb
Host smart-b0e035ba-6477-4c16-beb3-9ba600ac4527
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1005360400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1005360400
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.844660465
Short name T2822
Test name
Test status
Simulation time 42717308 ps
CPU time 0.66 seconds
Started Jul 18 05:35:40 PM PDT 24
Finished Jul 18 05:35:41 PM PDT 24
Peak memory 206240 kb
Host smart-70dd638e-f7a6-498f-adef-2b47cacf527f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=844660465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.844660465
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.3829149981
Short name T2834
Test name
Test status
Simulation time 187750737 ps
CPU time 1.63 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 206516 kb
Host smart-18108203-582b-4f87-bade-e03990c3f868
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3829149981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.3829149981
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3209721499
Short name T220
Test name
Test status
Simulation time 76509233 ps
CPU time 1.76 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:49 PM PDT 24
Peak memory 206568 kb
Host smart-22c18f00-123d-4908-a4c2-854ad059c1da
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3209721499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3209721499
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1315323043
Short name T260
Test name
Test status
Simulation time 698194098 ps
CPU time 3.02 seconds
Started Jul 18 05:35:45 PM PDT 24
Finished Jul 18 05:35:49 PM PDT 24
Peak memory 206512 kb
Host smart-6efe1cd4-8b42-4cf1-8c1e-c9e5815b9fe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1315323043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1315323043
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.13955294
Short name T263
Test name
Test status
Simulation time 151685152 ps
CPU time 1.26 seconds
Started Jul 18 05:35:45 PM PDT 24
Finished Jul 18 05:35:47 PM PDT 24
Peak memory 214732 kb
Host smart-d9b20590-0194-4730-a065-6ca0d37c0ca9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13955294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev
_csr_mem_rw_with_rand_reset.13955294
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.3722223436
Short name T253
Test name
Test status
Simulation time 50915442 ps
CPU time 1 seconds
Started Jul 18 05:35:43 PM PDT 24
Finished Jul 18 05:35:45 PM PDT 24
Peak memory 206412 kb
Host smart-f2006048-5ecf-44f6-943b-730e1ce234f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3722223436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.3722223436
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2220228393
Short name T2844
Test name
Test status
Simulation time 243075826 ps
CPU time 1.69 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:54 PM PDT 24
Peak memory 206472 kb
Host smart-4e71fd86-13e6-46c0-9620-797096a45876
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2220228393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2220228393
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.3370882933
Short name T2802
Test name
Test status
Simulation time 127274201 ps
CPU time 3.85 seconds
Started Jul 18 05:35:51 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 222860 kb
Host smart-dcbebcaf-f36f-4eb3-8bb7-fc27a6584fc7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3370882933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.3370882933
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2516171468
Short name T259
Test name
Test status
Simulation time 497718056 ps
CPU time 3.06 seconds
Started Jul 18 05:35:47 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 206492 kb
Host smart-c734f1c9-94e8-4b85-aabd-49809eea2a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2516171468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2516171468
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3533553841
Short name T2783
Test name
Test status
Simulation time 122986945 ps
CPU time 2.52 seconds
Started Jul 18 05:35:44 PM PDT 24
Finished Jul 18 05:35:47 PM PDT 24
Peak memory 214736 kb
Host smart-d5513f2f-70d3-4d6d-8e62-5708c553744b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533553841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3533553841
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.3974727376
Short name T250
Test name
Test status
Simulation time 74380756 ps
CPU time 1 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:52 PM PDT 24
Peak memory 206428 kb
Host smart-9fb38a3d-49d9-4427-a355-a6f328f007a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3974727376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.3974727376
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1346932302
Short name T2853
Test name
Test status
Simulation time 38423344 ps
CPU time 0.68 seconds
Started Jul 18 05:35:38 PM PDT 24
Finished Jul 18 05:35:39 PM PDT 24
Peak memory 206328 kb
Host smart-cccaaf0d-dcd7-4593-98f6-88f24ecc2e54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1346932302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1346932302
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.675599278
Short name T248
Test name
Test status
Simulation time 101239290 ps
CPU time 1.52 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 206524 kb
Host smart-83930f7c-4919-4301-9152-baa0f929a179
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=675599278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.675599278
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2295276448
Short name T2769
Test name
Test status
Simulation time 216059006 ps
CPU time 2.44 seconds
Started Jul 18 05:36:04 PM PDT 24
Finished Jul 18 05:36:09 PM PDT 24
Peak memory 214688 kb
Host smart-26f32771-ddc8-4837-bdc0-4890640c2a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2295276448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2295276448
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.1637203934
Short name T288
Test name
Test status
Simulation time 1056997321 ps
CPU time 5.56 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 206508 kb
Host smart-fcc6dc2a-9414-4c8a-af98-7514e4ff0ce6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1637203934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.1637203934
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.1147850923
Short name T191
Test name
Test status
Simulation time 67778219 ps
CPU time 1.17 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 214720 kb
Host smart-05cf4f5d-5f3b-4754-99cf-80d06a47aa6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147850923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.1147850923
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.32554817
Short name T2856
Test name
Test status
Simulation time 69990303 ps
CPU time 0.84 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:48 PM PDT 24
Peak memory 206264 kb
Host smart-8bd16550-ede9-4121-b3c2-ccaf6545c785
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=32554817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.32554817
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.3362559962
Short name T265
Test name
Test status
Simulation time 57060597 ps
CPU time 0.7 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:52 PM PDT 24
Peak memory 206300 kb
Host smart-ae1086b5-9966-4616-b5a6-942dc8acafaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3362559962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.3362559962
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2716967873
Short name T2839
Test name
Test status
Simulation time 474248269 ps
CPU time 2.45 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206476 kb
Host smart-b462311c-d2b4-471b-9307-1479692127a1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2716967873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2716967873
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.754247719
Short name T2848
Test name
Test status
Simulation time 193306559 ps
CPU time 2.07 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206360 kb
Host smart-9bac1301-47ce-45fd-94ee-54b02a1d64d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=754247719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.754247719
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.2611863930
Short name T2813
Test name
Test status
Simulation time 111232607 ps
CPU time 1.31 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 214664 kb
Host smart-e834b400-69e9-4235-b96f-7d6b3cb91cde
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611863930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.2611863930
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.406481789
Short name T246
Test name
Test status
Simulation time 174043696 ps
CPU time 1.13 seconds
Started Jul 18 05:35:47 PM PDT 24
Finished Jul 18 05:35:50 PM PDT 24
Peak memory 206360 kb
Host smart-c6ab5237-b7b7-4e72-bbfc-fc398f883221
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=406481789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.406481789
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1386698176
Short name T264
Test name
Test status
Simulation time 42507673 ps
CPU time 0.68 seconds
Started Jul 18 05:36:02 PM PDT 24
Finished Jul 18 05:36:04 PM PDT 24
Peak memory 206300 kb
Host smart-492b9398-cb8a-41d9-bf59-c5a62c916f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1386698176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1386698176
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3148391908
Short name T249
Test name
Test status
Simulation time 207770210 ps
CPU time 1.69 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:49 PM PDT 24
Peak memory 206484 kb
Host smart-9d313ffe-c6d7-4c49-b0f2-6f268c8e5f10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3148391908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3148391908
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1754582947
Short name T2779
Test name
Test status
Simulation time 251733916 ps
CPU time 2.74 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:55 PM PDT 24
Peak memory 222160 kb
Host smart-d018068d-a219-49ab-bfe4-ddaad98e4e9f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1754582947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1754582947
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2011264694
Short name T226
Test name
Test status
Simulation time 906036633 ps
CPU time 4.83 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:51 PM PDT 24
Peak memory 206532 kb
Host smart-11a3e070-5eec-4a67-b1a8-2fef3623c7ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2011264694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2011264694
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1496316916
Short name T2787
Test name
Test status
Simulation time 147179468 ps
CPU time 2.87 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:03 PM PDT 24
Peak memory 214800 kb
Host smart-d4e6e80c-893b-478f-ac54-1edcd6cce8d4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496316916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1496316916
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3930744473
Short name T2817
Test name
Test status
Simulation time 103072640 ps
CPU time 1.01 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 206476 kb
Host smart-efa3e4d5-d230-47da-9ae8-9279b8a00da8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3930744473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3930744473
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2164970927
Short name T2828
Test name
Test status
Simulation time 39865109 ps
CPU time 0.7 seconds
Started Jul 18 05:35:55 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 206284 kb
Host smart-e5112ead-e124-4745-96fb-17dc8b612fb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2164970927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2164970927
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2557984862
Short name T2768
Test name
Test status
Simulation time 154352221 ps
CPU time 1.57 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206196 kb
Host smart-2a531240-e68a-46ca-84ba-e712b1aee2b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2557984862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2557984862
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.4056676521
Short name T222
Test name
Test status
Simulation time 229900023 ps
CPU time 3.27 seconds
Started Jul 18 05:35:50 PM PDT 24
Finished Jul 18 05:35:56 PM PDT 24
Peak memory 222112 kb
Host smart-c14e1dc9-783c-4ca5-9d62-462c96de0a9a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4056676521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.4056676521
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4091068487
Short name T289
Test name
Test status
Simulation time 678739187 ps
CPU time 5.02 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 206548 kb
Host smart-d36c7b8b-eb7e-4493-947d-5ad2a6aec165
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4091068487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4091068487
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2971739811
Short name T243
Test name
Test status
Simulation time 122009948 ps
CPU time 3.3 seconds
Started Jul 18 05:35:18 PM PDT 24
Finished Jul 18 05:35:27 PM PDT 24
Peak memory 206392 kb
Host smart-4376a55c-d227-4c58-9084-633ab82ae462
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2971739811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2971739811
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.606990772
Short name T2823
Test name
Test status
Simulation time 1004248682 ps
CPU time 5.45 seconds
Started Jul 18 05:35:19 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 206420 kb
Host smart-cf3537bc-3972-489e-8c54-3546d72ba794
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=606990772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.606990772
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2468860070
Short name T2829
Test name
Test status
Simulation time 83566218 ps
CPU time 0.9 seconds
Started Jul 18 05:35:18 PM PDT 24
Finished Jul 18 05:35:26 PM PDT 24
Peak memory 206316 kb
Host smart-5ca3b034-4cae-4a11-9640-f8bc5475cd92
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2468860070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2468860070
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2513097095
Short name T2778
Test name
Test status
Simulation time 71625767 ps
CPU time 1.24 seconds
Started Jul 18 05:35:34 PM PDT 24
Finished Jul 18 05:35:37 PM PDT 24
Peak memory 214804 kb
Host smart-5e32bda8-03ee-4543-a627-e29a8643bf8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513097095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2513097095
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.2168595630
Short name T2843
Test name
Test status
Simulation time 61915710 ps
CPU time 0.82 seconds
Started Jul 18 05:35:18 PM PDT 24
Finished Jul 18 05:35:30 PM PDT 24
Peak memory 206444 kb
Host smart-79fe6124-ae68-435e-a46c-0edb2be076fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2168595630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.2168595630
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2608981943
Short name T275
Test name
Test status
Simulation time 77340299 ps
CPU time 0.75 seconds
Started Jul 18 05:35:23 PM PDT 24
Finished Jul 18 05:35:30 PM PDT 24
Peak memory 206244 kb
Host smart-c3f409cf-f6c7-4815-b8fc-63a41002423b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2608981943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2608981943
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2594697930
Short name T235
Test name
Test status
Simulation time 203178738 ps
CPU time 2.53 seconds
Started Jul 18 05:35:18 PM PDT 24
Finished Jul 18 05:35:27 PM PDT 24
Peak memory 214692 kb
Host smart-00afcee5-e7f0-41e0-801c-cd884ff57e48
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2594697930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2594697930
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3967174230
Short name T2816
Test name
Test status
Simulation time 713061295 ps
CPU time 5.03 seconds
Started Jul 18 05:35:20 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 206328 kb
Host smart-d1704d7d-251a-4b09-8503-ade469862d6c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3967174230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3967174230
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.3643061837
Short name T254
Test name
Test status
Simulation time 183826241 ps
CPU time 1.71 seconds
Started Jul 18 05:35:21 PM PDT 24
Finished Jul 18 05:35:29 PM PDT 24
Peak memory 206568 kb
Host smart-b4ec1b60-450a-4a30-9626-b8258292cb80
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3643061837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.3643061837
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2359237651
Short name T2815
Test name
Test status
Simulation time 185654901 ps
CPU time 2.39 seconds
Started Jul 18 05:35:23 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 222448 kb
Host smart-d9afdab7-2186-47d6-846a-38fd4357aec1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2359237651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2359237651
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2268390480
Short name T282
Test name
Test status
Simulation time 1116131646 ps
CPU time 4.92 seconds
Started Jul 18 05:35:23 PM PDT 24
Finished Jul 18 05:35:34 PM PDT 24
Peak memory 206424 kb
Host smart-cff8ec30-6d9f-4664-a5ab-25ac1bd2db87
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2268390480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2268390480
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.576811614
Short name T280
Test name
Test status
Simulation time 43282527 ps
CPU time 0.69 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206300 kb
Host smart-0f564089-e1a4-402b-ab1b-db0a89b2d9a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=576811614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.576811614
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.172477800
Short name T267
Test name
Test status
Simulation time 45793285 ps
CPU time 0.77 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:52 PM PDT 24
Peak memory 206244 kb
Host smart-c71c3f51-0c46-4706-b364-154d5c74ea8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=172477800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.172477800
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1846098285
Short name T2852
Test name
Test status
Simulation time 38519584 ps
CPU time 0.7 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206288 kb
Host smart-61bc359b-435d-4f84-9c02-fc5078b97efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1846098285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1846098285
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.519656557
Short name T276
Test name
Test status
Simulation time 39714666 ps
CPU time 0.71 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206284 kb
Host smart-636b415c-e2eb-409c-950d-1bce87486aef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=519656557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.519656557
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.489426351
Short name T2793
Test name
Test status
Simulation time 39294717 ps
CPU time 0.67 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 206284 kb
Host smart-7103ea5c-0a75-41ef-a684-136dcb0bb9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=489426351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.489426351
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.4011336443
Short name T2782
Test name
Test status
Simulation time 40022791 ps
CPU time 0.73 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 206312 kb
Host smart-e0009928-5556-4772-9f95-365c25ebad2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4011336443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.4011336443
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.508436703
Short name T2791
Test name
Test status
Simulation time 123023796 ps
CPU time 0.76 seconds
Started Jul 18 05:35:47 PM PDT 24
Finished Jul 18 05:35:50 PM PDT 24
Peak memory 206436 kb
Host smart-e6d7975a-c9d2-442c-8202-e811f23ceff2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=508436703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.508436703
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.671328201
Short name T2842
Test name
Test status
Simulation time 44313677 ps
CPU time 0.69 seconds
Started Jul 18 05:35:47 PM PDT 24
Finished Jul 18 05:35:50 PM PDT 24
Peak memory 206444 kb
Host smart-49d52c1d-9c67-4a55-bc38-599d6390838c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=671328201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.671328201
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.3010137007
Short name T2824
Test name
Test status
Simulation time 95512818 ps
CPU time 0.74 seconds
Started Jul 18 05:36:00 PM PDT 24
Finished Jul 18 05:36:04 PM PDT 24
Peak memory 206472 kb
Host smart-be10f845-8bdb-4946-bb4f-0acf71570828
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3010137007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.3010137007
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.4217477359
Short name T2810
Test name
Test status
Simulation time 169472488 ps
CPU time 2.08 seconds
Started Jul 18 05:35:26 PM PDT 24
Finished Jul 18 05:35:33 PM PDT 24
Peak memory 206404 kb
Host smart-3210873b-9509-4a98-8374-9a500846b1a0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4217477359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.4217477359
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1608333939
Short name T2801
Test name
Test status
Simulation time 718223810 ps
CPU time 4.49 seconds
Started Jul 18 05:35:23 PM PDT 24
Finished Jul 18 05:35:33 PM PDT 24
Peak memory 206364 kb
Host smart-9b20cefd-6088-4c69-b193-519653b0b307
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1608333939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1608333939
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2700594784
Short name T237
Test name
Test status
Simulation time 243351781 ps
CPU time 1.1 seconds
Started Jul 18 05:35:33 PM PDT 24
Finished Jul 18 05:35:37 PM PDT 24
Peak memory 206344 kb
Host smart-fc99c452-9c2e-4535-9bc7-0b4a719ad5bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2700594784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2700594784
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2589706864
Short name T2825
Test name
Test status
Simulation time 84994522 ps
CPU time 1.29 seconds
Started Jul 18 05:35:30 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 216512 kb
Host smart-8b9583ec-3a78-45d6-8cdd-54770ff5b3ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589706864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2589706864
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1338256051
Short name T2775
Test name
Test status
Simulation time 89170535 ps
CPU time 0.9 seconds
Started Jul 18 05:35:30 PM PDT 24
Finished Jul 18 05:35:34 PM PDT 24
Peak memory 205796 kb
Host smart-ebc96265-dae1-4cb4-86ab-4cd1726e074f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1338256051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1338256051
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.148016248
Short name T2849
Test name
Test status
Simulation time 88195873 ps
CPU time 0.76 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:32 PM PDT 24
Peak memory 206240 kb
Host smart-10d875f5-8d6c-47ee-a279-a4efaa902948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=148016248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.148016248
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.883550480
Short name T2854
Test name
Test status
Simulation time 178190487 ps
CPU time 2.38 seconds
Started Jul 18 05:35:20 PM PDT 24
Finished Jul 18 05:35:28 PM PDT 24
Peak memory 214656 kb
Host smart-033f5e38-d110-4999-9f4d-db821c3ec344
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=883550480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.883550480
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.14094070
Short name T2758
Test name
Test status
Simulation time 380455543 ps
CPU time 2.76 seconds
Started Jul 18 05:35:27 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206324 kb
Host smart-fcbefb43-8da0-4f65-83c1-83a08d4bc24b
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=14094070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.14094070
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1424318260
Short name T252
Test name
Test status
Simulation time 114621397 ps
CPU time 1.6 seconds
Started Jul 18 05:35:23 PM PDT 24
Finished Jul 18 05:35:30 PM PDT 24
Peak memory 206500 kb
Host smart-7dcabf30-0c97-4b9c-803a-1cfe5541d7eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1424318260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1424318260
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1956369643
Short name T2771
Test name
Test status
Simulation time 451692781 ps
CPU time 2.81 seconds
Started Jul 18 05:35:19 PM PDT 24
Finished Jul 18 05:35:28 PM PDT 24
Peak memory 206500 kb
Host smart-67c96b1b-2cef-4351-be15-0f1a0b4703de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1956369643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1956369643
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.633155871
Short name T2809
Test name
Test status
Simulation time 115262146 ps
CPU time 0.78 seconds
Started Jul 18 05:36:00 PM PDT 24
Finished Jul 18 05:36:04 PM PDT 24
Peak memory 206440 kb
Host smart-8d7152fd-233a-49f9-ad15-e3b692b0a466
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=633155871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.633155871
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.757048263
Short name T2838
Test name
Test status
Simulation time 94958274 ps
CPU time 0.74 seconds
Started Jul 18 05:35:47 PM PDT 24
Finished Jul 18 05:35:50 PM PDT 24
Peak memory 206440 kb
Host smart-1278d5c5-4eca-4b22-9d3f-37cffa87cd3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=757048263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.757048263
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.4197927991
Short name T268
Test name
Test status
Simulation time 68666117 ps
CPU time 0.74 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206284 kb
Host smart-dd632d64-f561-4807-a378-e78de5e84adc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4197927991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.4197927991
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.1544889289
Short name T2807
Test name
Test status
Simulation time 65257789 ps
CPU time 0.72 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:02 PM PDT 24
Peak memory 206244 kb
Host smart-e7aed096-1d3a-430b-a457-1fd2f7972eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1544889289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.1544889289
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.4033807561
Short name T2777
Test name
Test status
Simulation time 43187545 ps
CPU time 0.67 seconds
Started Jul 18 05:35:50 PM PDT 24
Finished Jul 18 05:35:55 PM PDT 24
Peak memory 206244 kb
Host smart-43a32453-9233-4b2b-8a0e-fe8c95673bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4033807561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.4033807561
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2323611526
Short name T201
Test name
Test status
Simulation time 46078598 ps
CPU time 0.69 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206232 kb
Host smart-6bbb0bb7-7224-42dc-93d3-e4742074f2b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2323611526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2323611526
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1019550011
Short name T2789
Test name
Test status
Simulation time 52916991 ps
CPU time 0.63 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 206284 kb
Host smart-9342d730-e042-4410-8201-5192ff11d501
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019550011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1019550011
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.1003827066
Short name T2803
Test name
Test status
Simulation time 31938251 ps
CPU time 0.64 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206308 kb
Host smart-725e3ac9-06f8-4391-b6fb-8e942ed47bee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1003827066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.1003827066
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3909796592
Short name T2819
Test name
Test status
Simulation time 32631497 ps
CPU time 0.69 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 206248 kb
Host smart-12a894b9-302d-44bd-ad0e-a5fe1b11828f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3909796592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3909796592
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2147936087
Short name T2799
Test name
Test status
Simulation time 131305702 ps
CPU time 3.27 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:34 PM PDT 24
Peak memory 206332 kb
Host smart-7f04c54e-08f3-4151-8b26-a61db461313c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2147936087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2147936087
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2970086089
Short name T2808
Test name
Test status
Simulation time 503294293 ps
CPU time 6.84 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:37 PM PDT 24
Peak memory 206364 kb
Host smart-1bb469fc-7f7f-42f2-9196-23cc03f83cfd
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2970086089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2970086089
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.658264827
Short name T2840
Test name
Test status
Simulation time 74438746 ps
CPU time 0.85 seconds
Started Jul 18 05:35:20 PM PDT 24
Finished Jul 18 05:35:27 PM PDT 24
Peak memory 206276 kb
Host smart-0041d89a-824c-486b-8113-956f96a5a1bb
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=658264827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.658264827
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3362252189
Short name T2780
Test name
Test status
Simulation time 100751447 ps
CPU time 1.31 seconds
Started Jul 18 05:35:24 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 214728 kb
Host smart-0714cd51-0e97-45c7-9774-9c0819fe0cb8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362252189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3362252189
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.2913898417
Short name T2845
Test name
Test status
Simulation time 56134961 ps
CPU time 0.88 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 206272 kb
Host smart-28a92635-0f75-42a3-a5d9-81da2f735c26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2913898417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.2913898417
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.4124055336
Short name T277
Test name
Test status
Simulation time 38660788 ps
CPU time 0.68 seconds
Started Jul 18 05:35:30 PM PDT 24
Finished Jul 18 05:35:34 PM PDT 24
Peak memory 205720 kb
Host smart-c59addfe-44af-4c90-a391-b92e3c6d3ef3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4124055336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.4124055336
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3565531049
Short name T240
Test name
Test status
Simulation time 94144796 ps
CPU time 1.45 seconds
Started Jul 18 05:35:36 PM PDT 24
Finished Jul 18 05:35:39 PM PDT 24
Peak memory 214728 kb
Host smart-b38e2e42-a33e-41da-a797-867cc24892c3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3565531049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3565531049
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3351261459
Short name T2756
Test name
Test status
Simulation time 439875961 ps
CPU time 2.74 seconds
Started Jul 18 05:35:27 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206308 kb
Host smart-9e07fb2c-da82-4f6d-8c8e-39912abf8f8e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3351261459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3351261459
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.550053874
Short name T251
Test name
Test status
Simulation time 62933330 ps
CPU time 1.09 seconds
Started Jul 18 05:35:19 PM PDT 24
Finished Jul 18 05:35:26 PM PDT 24
Peak memory 206632 kb
Host smart-78e273cf-2f86-4561-b233-60a71100c988
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=550053874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.550053874
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1972754101
Short name T2792
Test name
Test status
Simulation time 99459481 ps
CPU time 2.5 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:33 PM PDT 24
Peak memory 214724 kb
Host smart-d1066b48-a0f4-4864-9dcb-68c46ee6e45e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1972754101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1972754101
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.435430929
Short name T287
Test name
Test status
Simulation time 576022637 ps
CPU time 2.61 seconds
Started Jul 18 05:35:16 PM PDT 24
Finished Jul 18 05:35:25 PM PDT 24
Peak memory 206460 kb
Host smart-0be8c5d2-4cb6-4de9-8e6e-40b6968ff094
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=435430929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.435430929
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.146530018
Short name T2774
Test name
Test status
Simulation time 104995502 ps
CPU time 0.79 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206232 kb
Host smart-de469df0-6fc8-4a1c-9ed1-2c0b2b3c22c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=146530018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.146530018
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1612281958
Short name T2830
Test name
Test status
Simulation time 66115651 ps
CPU time 0.72 seconds
Started Jul 18 05:35:59 PM PDT 24
Finished Jul 18 05:36:03 PM PDT 24
Peak memory 206272 kb
Host smart-59b07ee2-3fa5-4521-b03e-92a8f0b77e37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1612281958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1612281958
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1684343615
Short name T198
Test name
Test status
Simulation time 53507801 ps
CPU time 0.68 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 206244 kb
Host smart-ae7a9f9b-56bb-4b37-9deb-79be07c3ce9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1684343615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1684343615
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.640482069
Short name T2833
Test name
Test status
Simulation time 33366372 ps
CPU time 0.68 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 206240 kb
Host smart-4bdc47e4-55f2-490c-9b2f-936bf941ec1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=640482069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.640482069
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3321362513
Short name T2835
Test name
Test status
Simulation time 39398223 ps
CPU time 0.68 seconds
Started Jul 18 05:35:43 PM PDT 24
Finished Jul 18 05:35:45 PM PDT 24
Peak memory 206260 kb
Host smart-1bbd3bab-4a87-4e0a-8ef1-3f53d0ae73ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3321362513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3321362513
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.727264
Short name T278
Test name
Test status
Simulation time 83826370 ps
CPU time 0.74 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206280 kb
Host smart-a416ec81-6c50-4675-a198-d7f849d7925a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=727264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.727264
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1510741016
Short name T269
Test name
Test status
Simulation time 39590538 ps
CPU time 0.7 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 205892 kb
Host smart-f3411619-7142-42cf-8be8-7fc697517e2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1510741016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1510741016
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2848961508
Short name T2837
Test name
Test status
Simulation time 35732033 ps
CPU time 0.67 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:57 PM PDT 24
Peak memory 206248 kb
Host smart-a68b3608-e83d-401c-8ed7-90541f97c948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2848961508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2848961508
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1192753266
Short name T2832
Test name
Test status
Simulation time 39386573 ps
CPU time 0.72 seconds
Started Jul 18 05:35:52 PM PDT 24
Finished Jul 18 05:35:58 PM PDT 24
Peak memory 205928 kb
Host smart-e5ef34bd-98dc-46c5-9dae-a51785246af0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1192753266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1192753266
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1651208616
Short name T258
Test name
Test status
Simulation time 92188437 ps
CPU time 1.26 seconds
Started Jul 18 05:35:30 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 216976 kb
Host smart-990e2147-9b0b-4aa1-b1b8-6a292ebe1b08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651208616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1651208616
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1806117134
Short name T2785
Test name
Test status
Simulation time 86978570 ps
CPU time 1.04 seconds
Started Jul 18 05:35:25 PM PDT 24
Finished Jul 18 05:35:32 PM PDT 24
Peak memory 206336 kb
Host smart-7a429c8d-f2a1-486c-87cf-9f76ec544d55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1806117134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1806117134
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.3381045878
Short name T281
Test name
Test status
Simulation time 62045838 ps
CPU time 0.72 seconds
Started Jul 18 05:35:24 PM PDT 24
Finished Jul 18 05:35:31 PM PDT 24
Peak memory 206220 kb
Host smart-1249d907-61f8-4927-a357-8fcffce56c84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3381045878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.3381045878
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.501663183
Short name T2850
Test name
Test status
Simulation time 196521261 ps
CPU time 1.72 seconds
Started Jul 18 05:35:31 PM PDT 24
Finished Jul 18 05:35:36 PM PDT 24
Peak memory 206376 kb
Host smart-6784b2b7-8215-4ee7-aabb-1952422819e2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=501663183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.501663183
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1447760447
Short name T2795
Test name
Test status
Simulation time 350316976 ps
CPU time 3.43 seconds
Started Jul 18 05:35:24 PM PDT 24
Finished Jul 18 05:35:33 PM PDT 24
Peak memory 214728 kb
Host smart-433185a9-8b9e-4fb5-8f48-d3ca197bd2d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1447760447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1447760447
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1534631076
Short name T2760
Test name
Test status
Simulation time 1402739995 ps
CPU time 6.19 seconds
Started Jul 18 05:35:24 PM PDT 24
Finished Jul 18 05:35:36 PM PDT 24
Peak memory 206452 kb
Host smart-be35d4eb-618b-46e0-aac8-bce13c1117c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1534631076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1534631076
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.4259830638
Short name T227
Test name
Test status
Simulation time 157540912 ps
CPU time 1.91 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 222068 kb
Host smart-0d3d4772-9af3-4d49-9b42-97178617702a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259830638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.4259830638
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.2253231665
Short name T239
Test name
Test status
Simulation time 87587246 ps
CPU time 0.86 seconds
Started Jul 18 05:35:32 PM PDT 24
Finished Jul 18 05:35:35 PM PDT 24
Peak memory 206256 kb
Host smart-74094c9e-52a9-44dd-b4cd-412d7d3e4cb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2253231665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.2253231665
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3357154944
Short name T2818
Test name
Test status
Simulation time 94544394 ps
CPU time 1.06 seconds
Started Jul 18 05:35:32 PM PDT 24
Finished Jul 18 05:35:36 PM PDT 24
Peak memory 206332 kb
Host smart-68e75f55-d134-4d1e-b422-fa18db13108d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3357154944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3357154944
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1325793031
Short name T219
Test name
Test status
Simulation time 117991607 ps
CPU time 3.34 seconds
Started Jul 18 05:35:31 PM PDT 24
Finished Jul 18 05:35:38 PM PDT 24
Peak memory 214728 kb
Host smart-d7ffc4bc-c5e2-415e-81c2-b45d28e5767d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1325793031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1325793031
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2407417282
Short name T284
Test name
Test status
Simulation time 1141683131 ps
CPU time 5.76 seconds
Started Jul 18 05:35:35 PM PDT 24
Finished Jul 18 05:35:42 PM PDT 24
Peak memory 206408 kb
Host smart-5a8b2975-2d25-47e4-a116-84a566f462d5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2407417282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2407417282
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2789881698
Short name T2764
Test name
Test status
Simulation time 81014029 ps
CPU time 1.26 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:35:59 PM PDT 24
Peak memory 214704 kb
Host smart-04a09020-47bb-4197-8529-3403188319a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789881698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2789881698
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.465020045
Short name T2798
Test name
Test status
Simulation time 79152969 ps
CPU time 1.04 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206436 kb
Host smart-0c5741cc-4554-41cc-85e0-8eef5a434060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=465020045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.465020045
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2644967470
Short name T2770
Test name
Test status
Simulation time 47449429 ps
CPU time 0.73 seconds
Started Jul 18 05:35:51 PM PDT 24
Finished Jul 18 05:35:56 PM PDT 24
Peak memory 206308 kb
Host smart-6901f1bb-4080-477a-ab01-3d66a41fc567
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2644967470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2644967470
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.315351031
Short name T2796
Test name
Test status
Simulation time 310376946 ps
CPU time 2.08 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:49 PM PDT 24
Peak memory 206440 kb
Host smart-ed714b1e-8683-49fd-adbc-55d962b50caa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=315351031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.315351031
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.656223707
Short name T2772
Test name
Test status
Simulation time 124322096 ps
CPU time 2.07 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:50 PM PDT 24
Peak memory 206596 kb
Host smart-0e1ef994-3051-41b9-907c-6eaadabc80bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=656223707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.656223707
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.92918662
Short name T189
Test name
Test status
Simulation time 120759302 ps
CPU time 1.81 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 214684 kb
Host smart-b48777e4-f322-40ce-ab10-9263ffa5872d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92918662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u
sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_
csr_mem_rw_with_rand_reset.92918662
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2966509698
Short name T210
Test name
Test status
Simulation time 45374919 ps
CPU time 0.91 seconds
Started Jul 18 05:36:02 PM PDT 24
Finished Jul 18 05:36:05 PM PDT 24
Peak memory 206416 kb
Host smart-3cc918d0-1c15-4de4-a327-dbc6044e69eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2966509698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2966509698
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.4284520855
Short name T270
Test name
Test status
Simulation time 44348425 ps
CPU time 0.7 seconds
Started Jul 18 05:35:49 PM PDT 24
Finished Jul 18 05:35:53 PM PDT 24
Peak memory 206228 kb
Host smart-9fb350e0-1702-4d16-8fcd-f836bbe66149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4284520855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.4284520855
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.4235504962
Short name T2841
Test name
Test status
Simulation time 161307057 ps
CPU time 1.18 seconds
Started Jul 18 05:35:43 PM PDT 24
Finished Jul 18 05:35:45 PM PDT 24
Peak memory 206456 kb
Host smart-5e5a90a9-f7e2-451a-9c33-80dadc180305
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4235504962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.4235504962
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2910057430
Short name T221
Test name
Test status
Simulation time 366443764 ps
CPU time 3.83 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:56 PM PDT 24
Peak memory 214808 kb
Host smart-ac74bbda-5973-41e6-bead-c3720362ae01
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2910057430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2910057430
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.140193322
Short name T213
Test name
Test status
Simulation time 1047564373 ps
CPU time 5.83 seconds
Started Jul 18 05:35:48 PM PDT 24
Finished Jul 18 05:35:56 PM PDT 24
Peak memory 206444 kb
Host smart-5a28fe7d-0d7a-4dfa-bf64-563feef1c7c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=140193322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.140193322
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3070373317
Short name T2765
Test name
Test status
Simulation time 86404415 ps
CPU time 2.14 seconds
Started Jul 18 05:35:46 PM PDT 24
Finished Jul 18 05:35:49 PM PDT 24
Peak memory 214824 kb
Host smart-1c5c478b-283e-4564-9cda-30e2ca32a10d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070373317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3070373317
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.175203502
Short name T2826
Test name
Test status
Simulation time 62749089 ps
CPU time 0.83 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:01 PM PDT 24
Peak memory 206328 kb
Host smart-79be41af-d79d-4834-85c0-e88e846ec339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=175203502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.175203502
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.1215550289
Short name T274
Test name
Test status
Simulation time 44892345 ps
CPU time 0.69 seconds
Started Jul 18 05:35:54 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206296 kb
Host smart-a5ae94d7-3025-4fe4-b3b8-04e0353c1340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1215550289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.1215550289
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2395733812
Short name T262
Test name
Test status
Simulation time 212355519 ps
CPU time 1.71 seconds
Started Jul 18 05:35:53 PM PDT 24
Finished Jul 18 05:36:00 PM PDT 24
Peak memory 206388 kb
Host smart-a6a0cc7f-dec1-4055-bbf4-1b6e09df882f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2395733812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2395733812
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2499235696
Short name T2762
Test name
Test status
Simulation time 137756004 ps
CPU time 1.95 seconds
Started Jul 18 05:35:50 PM PDT 24
Finished Jul 18 05:35:56 PM PDT 24
Peak memory 214740 kb
Host smart-88f44bab-97b0-444a-b5e4-30973b66def3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2499235696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2499235696
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.2439079212
Short name T2773
Test name
Test status
Simulation time 1288396940 ps
CPU time 5.02 seconds
Started Jul 18 05:35:45 PM PDT 24
Finished Jul 18 05:35:51 PM PDT 24
Peak memory 206416 kb
Host smart-c9ecb4af-6554-47a1-b822-8f059d68a75c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2439079212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.2439079212
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2276031353
Short name T1250
Test name
Test status
Simulation time 50163250 ps
CPU time 0.72 seconds
Started Jul 18 05:43:16 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 206688 kb
Host smart-3573effe-a351-443f-876c-9dd8a50ab225
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2276031353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2276031353
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.487504850
Short name T1578
Test name
Test status
Simulation time 4258442367 ps
CPU time 4.86 seconds
Started Jul 18 05:43:07 PM PDT 24
Finished Jul 18 05:43:30 PM PDT 24
Peak memory 206676 kb
Host smart-2d37ddab-df1f-4a5c-a23e-1d88cadbfcea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=487504850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.487504850
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.290865526
Short name T1708
Test name
Test status
Simulation time 13448113544 ps
CPU time 16.59 seconds
Started Jul 18 05:43:07 PM PDT 24
Finished Jul 18 05:43:41 PM PDT 24
Peak memory 206736 kb
Host smart-3c237d6f-1355-41e9-a9ec-6e10f99240f5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=290865526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.290865526
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1896053165
Short name T355
Test name
Test status
Simulation time 23392659266 ps
CPU time 21.73 seconds
Started Jul 18 05:43:07 PM PDT 24
Finished Jul 18 05:43:46 PM PDT 24
Peak memory 206908 kb
Host smart-870e6b77-5b47-4a26-9d15-032e8994e900
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1896053165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.1896053165
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1120370854
Short name T2391
Test name
Test status
Simulation time 172712659 ps
CPU time 0.92 seconds
Started Jul 18 05:43:02 PM PDT 24
Finished Jul 18 05:43:20 PM PDT 24
Peak memory 206672 kb
Host smart-31e9e8a6-d074-45cf-866f-65bb262b6489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11203
70854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1120370854
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.1661439270
Short name T1147
Test name
Test status
Simulation time 173274591 ps
CPU time 0.78 seconds
Started Jul 18 05:43:07 PM PDT 24
Finished Jul 18 05:43:31 PM PDT 24
Peak memory 206644 kb
Host smart-f1769794-d3d6-4bc8-910f-2c86a9539afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16614
39270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.1661439270
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.3774277469
Short name T1505
Test name
Test status
Simulation time 482258990 ps
CPU time 1.37 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:43:25 PM PDT 24
Peak memory 206736 kb
Host smart-c684ff49-5538-4415-aff0-41f8371dc189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37742
77469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.3774277469
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.702562329
Short name T321
Test name
Test status
Simulation time 1066291400 ps
CPU time 2.45 seconds
Started Jul 18 05:43:07 PM PDT 24
Finished Jul 18 05:43:26 PM PDT 24
Peak memory 206776 kb
Host smart-551821d7-1f42-4b32-84c9-17bcf5833a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70256
2329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.702562329
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3176969101
Short name T1469
Test name
Test status
Simulation time 5946638678 ps
CPU time 11.26 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:26 PM PDT 24
Peak memory 206904 kb
Host smart-e0dae3fa-93dc-4542-95ea-85a05209d2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
69101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3176969101
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.4228165691
Short name T2579
Test name
Test status
Simulation time 479532412 ps
CPU time 1.39 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 206628 kb
Host smart-ff2acc18-0b67-4ed4-a8d7-030d7a3d979b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42281
65691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.4228165691
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.955090706
Short name T1042
Test name
Test status
Simulation time 152591209 ps
CPU time 0.76 seconds
Started Jul 18 05:42:57 PM PDT 24
Finished Jul 18 05:43:13 PM PDT 24
Peak memory 206644 kb
Host smart-acd29520-cd5f-4642-a319-100750e367e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95509
0706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.955090706
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.3382339100
Short name T1720
Test name
Test status
Simulation time 5105617798 ps
CPU time 44.47 seconds
Started Jul 18 05:43:04 PM PDT 24
Finished Jul 18 05:44:05 PM PDT 24
Peak memory 206856 kb
Host smart-1a8e89e2-21d1-4fdd-a805-6bd432517576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33823
39100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.3382339100
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.312987473
Short name T1813
Test name
Test status
Simulation time 123566693 ps
CPU time 0.72 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:15 PM PDT 24
Peak memory 206624 kb
Host smart-f6811fd7-8910-42cc-8fb5-e4d8939e96fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
7473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.312987473
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1166453189
Short name T2623
Test name
Test status
Simulation time 813962041 ps
CPU time 1.86 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:17 PM PDT 24
Peak memory 206760 kb
Host smart-38a4a336-32b2-41b8-b652-b69eb9eaf270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11664
53189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1166453189
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.4045034872
Short name T1500
Test name
Test status
Simulation time 260554110 ps
CPU time 1.87 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:19 PM PDT 24
Peak memory 206764 kb
Host smart-56ff5352-bf33-405d-a4c7-2427f58a64e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40450
34872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.4045034872
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.1658143422
Short name T2043
Test name
Test status
Simulation time 118189216450 ps
CPU time 158.77 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:45:55 PM PDT 24
Peak memory 206848 kb
Host smart-eb0a25fb-dbe5-4ff7-a572-742706eddcf5
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1658143422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.1658143422
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.3215025625
Short name T1576
Test name
Test status
Simulation time 121228448054 ps
CPU time 170.37 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206856 kb
Host smart-121e0e8d-8476-405c-b7de-1dbd8c72fe3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215025625 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.3215025625
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3163561737
Short name T1248
Test name
Test status
Simulation time 115104913005 ps
CPU time 160.96 seconds
Started Jul 18 05:43:03 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206868 kb
Host smart-d6bc04d9-1663-41eb-831a-0af0de74e481
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3163561737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3163561737
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3043137274
Short name T1909
Test name
Test status
Simulation time 120072155586 ps
CPU time 162.34 seconds
Started Jul 18 05:43:05 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206860 kb
Host smart-348e9d65-c897-4b2f-b9f5-58772d3aac76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043137274 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3043137274
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.1216406522
Short name T807
Test name
Test status
Simulation time 95117572675 ps
CPU time 120.81 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:45:17 PM PDT 24
Peak memory 206900 kb
Host smart-08998e7a-ef08-4aab-b09a-e791f4337869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12164
06522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.1216406522
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2804931448
Short name T1017
Test name
Test status
Simulation time 194567288 ps
CPU time 0.91 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:18 PM PDT 24
Peak memory 206648 kb
Host smart-70d76317-926c-4301-ba10-6cbb6bcaa131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28049
31448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2804931448
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.996978858
Short name T2321
Test name
Test status
Simulation time 176351035 ps
CPU time 0.85 seconds
Started Jul 18 05:43:01 PM PDT 24
Finished Jul 18 05:43:18 PM PDT 24
Peak memory 206652 kb
Host smart-7ef1d028-0542-4d0d-8b61-6245dc9549b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99697
8858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.996978858
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.802091500
Short name T1235
Test name
Test status
Simulation time 195905704 ps
CPU time 0.87 seconds
Started Jul 18 05:43:05 PM PDT 24
Finished Jul 18 05:43:22 PM PDT 24
Peak memory 206648 kb
Host smart-bc3d9926-6983-4869-818d-d42f3102eaa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80209
1500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.802091500
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.386450041
Short name T971
Test name
Test status
Simulation time 4092233366 ps
CPU time 12.82 seconds
Started Jul 18 05:43:05 PM PDT 24
Finished Jul 18 05:43:34 PM PDT 24
Peak memory 206848 kb
Host smart-39e8928b-ac7e-4998-8def-9efa90d5a8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38645
0041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.386450041
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.1139789743
Short name T2535
Test name
Test status
Simulation time 172702849 ps
CPU time 0.77 seconds
Started Jul 18 05:43:04 PM PDT 24
Finished Jul 18 05:43:22 PM PDT 24
Peak memory 206636 kb
Host smart-46fc6b68-1c38-4cee-a613-145c35d73cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11397
89743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.1139789743
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.2097878161
Short name T68
Test name
Test status
Simulation time 475185909 ps
CPU time 1.32 seconds
Started Jul 18 05:43:05 PM PDT 24
Finished Jul 18 05:43:23 PM PDT 24
Peak memory 206652 kb
Host smart-0487b330-4874-4170-abfc-70bd50b12c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20978
78161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.2097878161
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1052526233
Short name T481
Test name
Test status
Simulation time 23325819393 ps
CPU time 24.8 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:43:47 PM PDT 24
Peak memory 206728 kb
Host smart-3beb7c7b-cdfb-473e-94a7-d9a4bafc1d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10525
26233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1052526233
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3433411501
Short name T2402
Test name
Test status
Simulation time 3283472412 ps
CPU time 4.48 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:43:27 PM PDT 24
Peak memory 206684 kb
Host smart-8d5eda0d-ad9e-41a2-a3c6-0bd07e60cd89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34334
11501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3433411501
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3467488986
Short name T554
Test name
Test status
Simulation time 10443353463 ps
CPU time 71.01 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:44:26 PM PDT 24
Peak memory 206924 kb
Host smart-04a7f6de-25b5-4a47-9cbf-5c3abbee43e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34674
88986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3467488986
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.3721728048
Short name T622
Test name
Test status
Simulation time 5002339394 ps
CPU time 140.4 seconds
Started Jul 18 05:43:00 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206844 kb
Host smart-557ea1a9-4d7a-4bb6-9a78-2085a4b55a34
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3721728048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.3721728048
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.1780342322
Short name T825
Test name
Test status
Simulation time 325823196 ps
CPU time 1.05 seconds
Started Jul 18 05:42:59 PM PDT 24
Finished Jul 18 05:43:16 PM PDT 24
Peak memory 206652 kb
Host smart-ff0aae92-811e-454c-8668-d06b972bbf47
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1780342322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.1780342322
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.1769461065
Short name T1538
Test name
Test status
Simulation time 218438604 ps
CPU time 0.85 seconds
Started Jul 18 05:43:06 PM PDT 24
Finished Jul 18 05:43:23 PM PDT 24
Peak memory 206620 kb
Host smart-5704dbb1-d943-445c-85de-2a91913a8680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17694
61065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.1769461065
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2826602924
Short name T2552
Test name
Test status
Simulation time 5962970821 ps
CPU time 168.99 seconds
Started Jul 18 05:43:08 PM PDT 24
Finished Jul 18 05:46:14 PM PDT 24
Peak memory 206868 kb
Host smart-9e0791db-0b35-44bc-9d4c-3eed5f3bcd00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28266
02924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2826602924
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3591169317
Short name T1828
Test name
Test status
Simulation time 2811636889 ps
CPU time 24.99 seconds
Started Jul 18 05:43:03 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 206848 kb
Host smart-7d683904-a93c-4af9-8a94-384893f34f11
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3591169317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3591169317
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.24413876
Short name T348
Test name
Test status
Simulation time 197524317 ps
CPU time 0.84 seconds
Started Jul 18 05:43:27 PM PDT 24
Finished Jul 18 05:43:43 PM PDT 24
Peak memory 206608 kb
Host smart-aa18584e-de61-4625-a548-26baa7c35cfa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=24413876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.24413876
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.586522953
Short name T628
Test name
Test status
Simulation time 152745794 ps
CPU time 0.79 seconds
Started Jul 18 05:43:29 PM PDT 24
Finished Jul 18 05:43:44 PM PDT 24
Peak memory 206596 kb
Host smart-bc149777-2a49-48da-b302-15fd56d5584c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58652
2953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.586522953
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.660194115
Short name T67
Test name
Test status
Simulation time 462962834 ps
CPU time 1.39 seconds
Started Jul 18 05:43:24 PM PDT 24
Finished Jul 18 05:43:40 PM PDT 24
Peak memory 206636 kb
Host smart-13f49f9a-22b9-49e1-90e2-920640719d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66019
4115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.660194115
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.1542592553
Short name T733
Test name
Test status
Simulation time 155328612 ps
CPU time 0.86 seconds
Started Jul 18 05:43:20 PM PDT 24
Finished Jul 18 05:43:37 PM PDT 24
Peak memory 206636 kb
Host smart-3db014d0-b990-49be-bd5c-2466076b9269
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15425
92553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.1542592553
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.481780280
Short name T1365
Test name
Test status
Simulation time 164166979 ps
CPU time 0.8 seconds
Started Jul 18 05:43:16 PM PDT 24
Finished Jul 18 05:43:34 PM PDT 24
Peak memory 206632 kb
Host smart-cef5c1c9-059e-45cb-af4a-1e1354f99e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48178
0280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.481780280
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.568408145
Short name T1173
Test name
Test status
Simulation time 175815683 ps
CPU time 0.82 seconds
Started Jul 18 05:43:14 PM PDT 24
Finished Jul 18 05:43:32 PM PDT 24
Peak memory 206660 kb
Host smart-d9f51f9c-1251-4836-b618-e0e11c1dc176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56840
8145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.568408145
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.2376486821
Short name T1799
Test name
Test status
Simulation time 145587459 ps
CPU time 0.83 seconds
Started Jul 18 05:43:29 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 206652 kb
Host smart-e3ca9b84-068c-4c80-a302-db5470cf7335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23764
86821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.2376486821
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.815677816
Short name T1528
Test name
Test status
Simulation time 144604561 ps
CPU time 0.77 seconds
Started Jul 18 05:43:21 PM PDT 24
Finished Jul 18 05:43:38 PM PDT 24
Peak memory 206636 kb
Host smart-fe93232b-931b-48f6-aa38-3b9a5ba96b5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81567
7816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.815677816
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.3339381302
Short name T46
Test name
Test status
Simulation time 179979025 ps
CPU time 0.88 seconds
Started Jul 18 05:43:15 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 206640 kb
Host smart-0eda4d69-e808-4ffb-8c8f-39193fdbc3de
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3339381302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.3339381302
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1688863407
Short name T195
Test name
Test status
Simulation time 216896467 ps
CPU time 0.93 seconds
Started Jul 18 05:43:23 PM PDT 24
Finished Jul 18 05:43:39 PM PDT 24
Peak memory 206620 kb
Host smart-c44c8495-1b4a-4ab8-bf2b-206adba6232e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16888
63407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1688863407
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.1861846153
Short name T160
Test name
Test status
Simulation time 221441419 ps
CPU time 0.87 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 206656 kb
Host smart-23bc6875-b95f-476b-baf4-0cbe044c7f83
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1861846153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.1861846153
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2380507232
Short name T193
Test name
Test status
Simulation time 229972790 ps
CPU time 0.94 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 206568 kb
Host smart-9a2e3956-e345-4cf9-8bba-0ed18bdd4871
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2380507232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2380507232
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3876385111
Short name T1930
Test name
Test status
Simulation time 142928012 ps
CPU time 0.75 seconds
Started Jul 18 05:43:24 PM PDT 24
Finished Jul 18 05:43:40 PM PDT 24
Peak memory 206644 kb
Host smart-6f3e94c9-8770-436b-97e6-dfa541734d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38763
85111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3876385111
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.4039923940
Short name T681
Test name
Test status
Simulation time 74417373 ps
CPU time 0.69 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:36 PM PDT 24
Peak memory 206584 kb
Host smart-b198f632-ce0c-40f8-9ece-3d08d0cbf965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40399
23940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.4039923940
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3378526233
Short name T1402
Test name
Test status
Simulation time 19056073097 ps
CPU time 42.42 seconds
Started Jul 18 05:43:30 PM PDT 24
Finished Jul 18 05:44:27 PM PDT 24
Peak memory 206956 kb
Host smart-bce3c3d6-8300-42aa-8b07-409895ca2821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33785
26233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3378526233
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.912871651
Short name T464
Test name
Test status
Simulation time 150531848 ps
CPU time 0.77 seconds
Started Jul 18 05:43:29 PM PDT 24
Finished Jul 18 05:43:44 PM PDT 24
Peak memory 206612 kb
Host smart-aa11d2c6-6350-493a-bdf1-476157039909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91287
1651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.912871651
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.560646837
Short name T1959
Test name
Test status
Simulation time 206611211 ps
CPU time 0.9 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 206632 kb
Host smart-7a4f89f7-1a8f-475a-b943-1f6266dd5c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56064
6837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.560646837
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1942433608
Short name T2059
Test name
Test status
Simulation time 15131944449 ps
CPU time 113.01 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:45:26 PM PDT 24
Peak memory 206968 kb
Host smart-87c9b6b3-c6dd-4d08-8a21-829d9f55f1a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1942433608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1942433608
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3128384965
Short name T1183
Test name
Test status
Simulation time 254294308 ps
CPU time 0.93 seconds
Started Jul 18 05:43:29 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 206608 kb
Host smart-b0ef1241-270d-46f2-b927-0dff3972bf1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31283
84965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3128384965
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3112481817
Short name T1052
Test name
Test status
Simulation time 234072358 ps
CPU time 0.91 seconds
Started Jul 18 05:43:18 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 206648 kb
Host smart-bfb07828-d775-45ac-a05a-587a8f8faca2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31124
81817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3112481817
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.1272610360
Short name T2390
Test name
Test status
Simulation time 181169791 ps
CPU time 0.79 seconds
Started Jul 18 05:43:14 PM PDT 24
Finished Jul 18 05:43:32 PM PDT 24
Peak memory 206636 kb
Host smart-e58896c9-6d3e-4a1a-8e46-e72ecf2e2ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
10360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.1272610360
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2377228914
Short name T75
Test name
Test status
Simulation time 187225049 ps
CPU time 0.83 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 206620 kb
Host smart-104417ed-c70f-4088-899d-f4ef54a05e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23772
28914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2377228914
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.3435580861
Short name T187
Test name
Test status
Simulation time 261351481 ps
CPU time 1.07 seconds
Started Jul 18 05:43:19 PM PDT 24
Finished Jul 18 05:43:37 PM PDT 24
Peak memory 224440 kb
Host smart-99f9fa89-2907-47a1-ac48-fe68d60f9436
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3435580861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.3435580861
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.1971132639
Short name T2047
Test name
Test status
Simulation time 301189884 ps
CPU time 0.96 seconds
Started Jul 18 05:43:24 PM PDT 24
Finished Jul 18 05:43:41 PM PDT 24
Peak memory 206672 kb
Host smart-b0847690-86eb-4972-ab76-6dbcb64d1589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19711
32639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.1971132639
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2131344519
Short name T2069
Test name
Test status
Simulation time 150639701 ps
CPU time 0.76 seconds
Started Jul 18 05:43:22 PM PDT 24
Finished Jul 18 05:43:38 PM PDT 24
Peak memory 206648 kb
Host smart-a22617df-29f4-4518-be3b-2c33bbfabff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21313
44519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2131344519
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.3315975295
Short name T1282
Test name
Test status
Simulation time 199188187 ps
CPU time 0.83 seconds
Started Jul 18 05:43:20 PM PDT 24
Finished Jul 18 05:43:37 PM PDT 24
Peak memory 206620 kb
Host smart-328726a2-acc3-445a-a6ca-a8a75ed1a375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33159
75295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.3315975295
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1181627444
Short name T1602
Test name
Test status
Simulation time 211928018 ps
CPU time 0.92 seconds
Started Jul 18 05:43:20 PM PDT 24
Finished Jul 18 05:43:37 PM PDT 24
Peak memory 206628 kb
Host smart-d7416dc0-2d86-40d5-90dc-27679bc5b07e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11816
27444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1181627444
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.980753632
Short name T1657
Test name
Test status
Simulation time 5681350775 ps
CPU time 144.92 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:45:58 PM PDT 24
Peak memory 206868 kb
Host smart-5a3579b7-2ffb-49af-8c0d-3eb79bee394a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=980753632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.980753632
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.471733850
Short name T451
Test name
Test status
Simulation time 186168005 ps
CPU time 0.82 seconds
Started Jul 18 05:43:15 PM PDT 24
Finished Jul 18 05:43:33 PM PDT 24
Peak memory 206652 kb
Host smart-a62a1628-94c5-49d3-9b40-d991deea7b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47173
3850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.471733850
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.331017173
Short name T1428
Test name
Test status
Simulation time 203235657 ps
CPU time 0.76 seconds
Started Jul 18 05:43:26 PM PDT 24
Finished Jul 18 05:43:42 PM PDT 24
Peak memory 206648 kb
Host smart-a74a6e22-2eb3-409b-88aa-242365632849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33101
7173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.331017173
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.320620454
Short name T2127
Test name
Test status
Simulation time 466350687 ps
CPU time 1.32 seconds
Started Jul 18 05:43:22 PM PDT 24
Finished Jul 18 05:43:38 PM PDT 24
Peak memory 206636 kb
Host smart-578e04a9-5ef9-4843-b878-9652c5b86c27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32062
0454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.320620454
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.2403799908
Short name T1614
Test name
Test status
Simulation time 5407805025 ps
CPU time 151.2 seconds
Started Jul 18 05:43:21 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206848 kb
Host smart-eb4c5ebe-6700-491c-baac-95c0058648ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24037
99908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.2403799908
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3008018518
Short name T163
Test name
Test status
Simulation time 10119788582 ps
CPU time 165.11 seconds
Started Jul 18 05:43:19 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 206992 kb
Host smart-f5dc6e4f-fa11-4d7c-bffb-cefa3249fdf6
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3008018518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3008018518
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1681098859
Short name T2314
Test name
Test status
Simulation time 59847467 ps
CPU time 0.65 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:58 PM PDT 24
Peak memory 206692 kb
Host smart-6f914eac-9154-4595-9325-061f322cee0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1681098859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1681098859
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1821754606
Short name T1724
Test name
Test status
Simulation time 4035518812 ps
CPU time 4.69 seconds
Started Jul 18 05:43:24 PM PDT 24
Finished Jul 18 05:43:44 PM PDT 24
Peak memory 206820 kb
Host smart-ccdc7155-b4d3-4067-9b95-2be13b156207
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1821754606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1821754606
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1897696485
Short name T1711
Test name
Test status
Simulation time 13348103548 ps
CPU time 12.36 seconds
Started Jul 18 05:43:27 PM PDT 24
Finished Jul 18 05:43:54 PM PDT 24
Peak memory 206736 kb
Host smart-f581fe41-7e46-47bb-b376-28116825cbab
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1897696485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1897696485
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.698891335
Short name T835
Test name
Test status
Simulation time 23353560101 ps
CPU time 22.43 seconds
Started Jul 18 05:43:23 PM PDT 24
Finished Jul 18 05:44:01 PM PDT 24
Peak memory 206712 kb
Host smart-6716da95-7699-46d4-b54a-0d83eb79b47c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=698891335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.698891335
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.3871197386
Short name T1792
Test name
Test status
Simulation time 222586623 ps
CPU time 0.85 seconds
Started Jul 18 05:43:25 PM PDT 24
Finished Jul 18 05:43:41 PM PDT 24
Peak memory 206644 kb
Host smart-9a3d19a1-17a1-4645-a9a4-e4c379aa3a3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38711
97386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.3871197386
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.2853306420
Short name T52
Test name
Test status
Simulation time 160986235 ps
CPU time 0.8 seconds
Started Jul 18 05:43:21 PM PDT 24
Finished Jul 18 05:43:37 PM PDT 24
Peak memory 206656 kb
Host smart-05624845-2f05-46bc-ad7e-2926aec9d543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28533
06420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.2853306420
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.1135280491
Short name T63
Test name
Test status
Simulation time 143709955 ps
CPU time 0.77 seconds
Started Jul 18 05:43:24 PM PDT 24
Finished Jul 18 05:43:40 PM PDT 24
Peak memory 206648 kb
Host smart-104a0bf0-600a-4620-9b15-508b6236049b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11352
80491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.1135280491
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2802761654
Short name T2328
Test name
Test status
Simulation time 148138988 ps
CPU time 0.76 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 206632 kb
Host smart-1544d9d0-3d02-4feb-99b0-5c074e2839eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28027
61654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2802761654
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.2809315510
Short name T1995
Test name
Test status
Simulation time 432112512 ps
CPU time 1.35 seconds
Started Jul 18 05:43:17 PM PDT 24
Finished Jul 18 05:43:35 PM PDT 24
Peak memory 206652 kb
Host smart-d7a81a3d-451f-44d3-b1b0-a0e7d60ba154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28093
15510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.2809315510
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.156444997
Short name T686
Test name
Test status
Simulation time 565396147 ps
CPU time 1.47 seconds
Started Jul 18 05:43:16 PM PDT 24
Finished Jul 18 05:43:34 PM PDT 24
Peak memory 206616 kb
Host smart-71d6fb4c-71b1-4d01-9097-09f905d9c178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15644
4997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.156444997
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2584187580
Short name T2199
Test name
Test status
Simulation time 426355540 ps
CPU time 1.43 seconds
Started Jul 18 05:43:19 PM PDT 24
Finished Jul 18 05:43:37 PM PDT 24
Peak memory 206644 kb
Host smart-96da0591-1dea-452a-8583-392648892e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25841
87580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2584187580
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.1147779745
Short name T544
Test name
Test status
Simulation time 145646567 ps
CPU time 0.75 seconds
Started Jul 18 05:43:18 PM PDT 24
Finished Jul 18 05:43:36 PM PDT 24
Peak memory 206648 kb
Host smart-a982249e-a2a4-421d-bf04-47677431d244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11477
79745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.1147779745
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.536284126
Short name T1386
Test name
Test status
Simulation time 30305050 ps
CPU time 0.65 seconds
Started Jul 18 05:43:30 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 206616 kb
Host smart-61168cb7-4174-4b61-aeca-03a95c441310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53628
4126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.536284126
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.2952338736
Short name T1435
Test name
Test status
Simulation time 921894045 ps
CPU time 2.14 seconds
Started Jul 18 05:43:25 PM PDT 24
Finished Jul 18 05:43:43 PM PDT 24
Peak memory 206712 kb
Host smart-62ef63f1-c01b-4af8-b2cf-73cc87262752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
38736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.2952338736
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.494016973
Short name T2158
Test name
Test status
Simulation time 405200921 ps
CPU time 2.39 seconds
Started Jul 18 05:43:20 PM PDT 24
Finished Jul 18 05:43:39 PM PDT 24
Peak memory 206716 kb
Host smart-df2376b7-2a78-4572-a2ed-bead9ef1b72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49401
6973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.494016973
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3662639824
Short name T1551
Test name
Test status
Simulation time 98229574618 ps
CPU time 138.22 seconds
Started Jul 18 05:43:19 PM PDT 24
Finished Jul 18 05:45:54 PM PDT 24
Peak memory 206864 kb
Host smart-4a4cdfb6-ae86-48c8-b148-7c37e4803181
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3662639824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3662639824
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.1631141686
Short name T2101
Test name
Test status
Simulation time 96054121477 ps
CPU time 135.36 seconds
Started Jul 18 05:43:34 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206836 kb
Host smart-2250ce7f-d1cb-479f-bdaf-0a06a075aae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631141686 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.1631141686
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.438635177
Short name T2491
Test name
Test status
Simulation time 86162362065 ps
CPU time 121.35 seconds
Started Jul 18 05:43:31 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206872 kb
Host smart-ffeb74ab-fe3f-4032-bafe-80a34b404f07
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=438635177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.438635177
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.2125737002
Short name T2155
Test name
Test status
Simulation time 120143719875 ps
CPU time 156.08 seconds
Started Jul 18 05:43:20 PM PDT 24
Finished Jul 18 05:46:13 PM PDT 24
Peak memory 206928 kb
Host smart-d05bbd9d-7554-4deb-97ee-110f23ce122e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125737002 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.2125737002
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.3646735200
Short name T2021
Test name
Test status
Simulation time 88154880399 ps
CPU time 117.21 seconds
Started Jul 18 05:43:14 PM PDT 24
Finished Jul 18 05:45:29 PM PDT 24
Peak memory 206868 kb
Host smart-36ba90a0-1ed5-4458-a95b-d2ef1f7da023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36467
35200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.3646735200
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.812823178
Short name T1811
Test name
Test status
Simulation time 212691205 ps
CPU time 0.94 seconds
Started Jul 18 05:43:25 PM PDT 24
Finished Jul 18 05:43:41 PM PDT 24
Peak memory 206616 kb
Host smart-8400dcac-7dab-4d3e-ad4a-c5a4c193cc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81282
3178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.812823178
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3648225460
Short name T400
Test name
Test status
Simulation time 152083099 ps
CPU time 0.77 seconds
Started Jul 18 05:43:31 PM PDT 24
Finished Jul 18 05:43:47 PM PDT 24
Peak memory 206648 kb
Host smart-1c134689-6732-46f6-b898-7d1ae442afbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36482
25460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3648225460
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.3378381079
Short name T1967
Test name
Test status
Simulation time 274192359 ps
CPU time 0.94 seconds
Started Jul 18 05:43:26 PM PDT 24
Finished Jul 18 05:43:42 PM PDT 24
Peak memory 206640 kb
Host smart-7d4d7cc9-d23c-40b4-a41b-5ee40ac84a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33783
81079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.3378381079
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.970675968
Short name T207
Test name
Test status
Simulation time 8436207587 ps
CPU time 78.51 seconds
Started Jul 18 05:43:31 PM PDT 24
Finished Jul 18 05:45:05 PM PDT 24
Peak memory 206912 kb
Host smart-e6b05930-fe9c-4c79-9334-5d510b2c57e4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=970675968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.970675968
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3105315485
Short name T1843
Test name
Test status
Simulation time 4872932365 ps
CPU time 16.24 seconds
Started Jul 18 05:43:21 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 206864 kb
Host smart-34408a72-d72e-4981-93a7-dc6f85f26528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31053
15485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3105315485
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3454393955
Short name T1656
Test name
Test status
Simulation time 200032019 ps
CPU time 0.85 seconds
Started Jul 18 05:43:30 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 206648 kb
Host smart-442e91c3-27a7-47ff-82c9-e93c9e9cf35e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34543
93955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3454393955
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.4179127835
Short name T1075
Test name
Test status
Simulation time 23317714558 ps
CPU time 23.08 seconds
Started Jul 18 05:43:18 PM PDT 24
Finished Jul 18 05:43:58 PM PDT 24
Peak memory 206760 kb
Host smart-aee82d78-b9fe-48ba-a606-07289031d39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41791
27835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.4179127835
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.8484112
Short name T2442
Test name
Test status
Simulation time 3339618462 ps
CPU time 3.97 seconds
Started Jul 18 05:43:26 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 206712 kb
Host smart-562931b3-ba85-4453-adb1-7451f2c10ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84841
12 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.8484112
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1882925324
Short name T1081
Test name
Test status
Simulation time 11712353631 ps
CPU time 81.27 seconds
Started Jul 18 05:43:24 PM PDT 24
Finished Jul 18 05:45:00 PM PDT 24
Peak memory 206916 kb
Host smart-d604e901-621c-46ff-aed7-7d9dbc24a9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18829
25324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1882925324
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2141545657
Short name T2738
Test name
Test status
Simulation time 5153739496 ps
CPU time 34.72 seconds
Started Jul 18 05:43:20 PM PDT 24
Finished Jul 18 05:44:11 PM PDT 24
Peak memory 206848 kb
Host smart-29db3b0e-8593-4924-acaa-ebaa8087e72e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2141545657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2141545657
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.229373626
Short name T1130
Test name
Test status
Simulation time 246220150 ps
CPU time 0.94 seconds
Started Jul 18 05:43:30 PM PDT 24
Finished Jul 18 05:43:45 PM PDT 24
Peak memory 206648 kb
Host smart-0d3443ec-3a1f-4769-8579-790e15644f99
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=229373626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.229373626
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4231724164
Short name T378
Test name
Test status
Simulation time 186367705 ps
CPU time 0.97 seconds
Started Jul 18 05:43:27 PM PDT 24
Finished Jul 18 05:43:43 PM PDT 24
Peak memory 206652 kb
Host smart-74c90b1d-301b-4e26-98b4-db16acd55da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
24164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4231724164
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.4012856298
Short name T1280
Test name
Test status
Simulation time 3673547398 ps
CPU time 101.22 seconds
Started Jul 18 05:43:30 PM PDT 24
Finished Jul 18 05:45:26 PM PDT 24
Peak memory 206840 kb
Host smart-a6c71dc4-caa0-4966-9fbb-de54cecec941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40128
56298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.4012856298
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3924127823
Short name T2541
Test name
Test status
Simulation time 3950024018 ps
CPU time 107.32 seconds
Started Jul 18 05:43:18 PM PDT 24
Finished Jul 18 05:45:22 PM PDT 24
Peak memory 206856 kb
Host smart-1e93c2ea-1a43-4a43-ad1a-145d668875d9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3924127823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3924127823
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.2152726513
Short name T783
Test name
Test status
Simulation time 188326223 ps
CPU time 0.82 seconds
Started Jul 18 05:43:22 PM PDT 24
Finished Jul 18 05:43:38 PM PDT 24
Peak memory 206620 kb
Host smart-bcded239-791b-49a1-9661-cc6b8b3b3742
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2152726513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.2152726513
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1146571003
Short name T2070
Test name
Test status
Simulation time 171588740 ps
CPU time 0.78 seconds
Started Jul 18 05:43:34 PM PDT 24
Finished Jul 18 05:43:50 PM PDT 24
Peak memory 206648 kb
Host smart-1c3d0c47-3b63-42d0-9093-0f96a5df8c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465
71003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1146571003
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3713726627
Short name T861
Test name
Test status
Simulation time 161134640 ps
CPU time 0.8 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:44:00 PM PDT 24
Peak memory 206616 kb
Host smart-265ce3a2-5b76-4bed-a2a0-a85a679425e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37137
26627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3713726627
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.850368967
Short name T2303
Test name
Test status
Simulation time 195490372 ps
CPU time 0.8 seconds
Started Jul 18 05:43:41 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 206640 kb
Host smart-234274ab-52ab-4e1f-8c04-710be8ae52c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85036
8967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.850368967
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.253847756
Short name T547
Test name
Test status
Simulation time 164007098 ps
CPU time 0.84 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 206640 kb
Host smart-ebbd4680-664d-4653-9a5a-912276bb1297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25384
7756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.253847756
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.620834144
Short name T1115
Test name
Test status
Simulation time 155296278 ps
CPU time 0.79 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 206620 kb
Host smart-a803e755-7b14-47e8-a9a7-067dd2f7f357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62083
4144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.620834144
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.740227336
Short name T1079
Test name
Test status
Simulation time 269724760 ps
CPU time 0.97 seconds
Started Jul 18 05:43:32 PM PDT 24
Finished Jul 18 05:43:48 PM PDT 24
Peak memory 206656 kb
Host smart-998cb9ba-6083-4b15-978a-dbad33fd2e60
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=740227336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.740227336
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.289273307
Short name T194
Test name
Test status
Simulation time 266527234 ps
CPU time 0.95 seconds
Started Jul 18 05:43:33 PM PDT 24
Finished Jul 18 05:43:49 PM PDT 24
Peak memory 206632 kb
Host smart-ca7297bf-74dd-4525-80e3-4047978bbfc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28927
3307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.289273307
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1775121434
Short name T2161
Test name
Test status
Simulation time 164159818 ps
CPU time 0.83 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 206632 kb
Host smart-8e986a50-211d-4566-83de-6348a887320c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17751
21434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1775121434
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.274356834
Short name T1883
Test name
Test status
Simulation time 45114758 ps
CPU time 0.7 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 206600 kb
Host smart-ba6a1d14-f06b-43a9-b19a-f20e75c54645
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27435
6834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.274356834
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1168945358
Short name T1710
Test name
Test status
Simulation time 17295972180 ps
CPU time 40.07 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:44:32 PM PDT 24
Peak memory 206960 kb
Host smart-3abcbf95-8340-464f-85fa-5ea22313a72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11689
45358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1168945358
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3867272189
Short name T1232
Test name
Test status
Simulation time 190582226 ps
CPU time 0.87 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:43:54 PM PDT 24
Peak memory 206628 kb
Host smart-1e266024-2b59-43fb-8a94-a84198af7cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38672
72189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3867272189
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1647476387
Short name T1439
Test name
Test status
Simulation time 289036620 ps
CPU time 0.96 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 206632 kb
Host smart-3ba27bbf-f5f0-4ca1-9b47-e144091632e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16474
76387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1647476387
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3566526955
Short name T165
Test name
Test status
Simulation time 7790683804 ps
CPU time 48.38 seconds
Started Jul 18 05:43:41 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206924 kb
Host smart-59856509-8d3e-4bb7-8009-9a083de2fda7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3566526955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3566526955
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.4035192969
Short name T814
Test name
Test status
Simulation time 16856101243 ps
CPU time 123.58 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206948 kb
Host smart-a812e04b-54cf-4b8c-a515-0b24cca46436
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4035192969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.4035192969
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.4066401304
Short name T155
Test name
Test status
Simulation time 11575002715 ps
CPU time 63.3 seconds
Started Jul 18 05:43:35 PM PDT 24
Finished Jul 18 05:44:53 PM PDT 24
Peak memory 206924 kb
Host smart-757d5968-2d87-42fc-a4f2-b22ca51676fd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4066401304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.4066401304
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.1888871864
Short name T769
Test name
Test status
Simulation time 222726822 ps
CPU time 0.88 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 206620 kb
Host smart-5a26ffd7-ae68-4cdc-8591-cf5ad59b4cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18888
71864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.1888871864
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.954621961
Short name T1594
Test name
Test status
Simulation time 157012427 ps
CPU time 0.78 seconds
Started Jul 18 05:43:35 PM PDT 24
Finished Jul 18 05:43:51 PM PDT 24
Peak memory 206632 kb
Host smart-da74ccee-2a8a-44f0-9dc6-14b10da03be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95462
1961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.954621961
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.326808183
Short name T1253
Test name
Test status
Simulation time 141270070 ps
CPU time 0.77 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:43:52 PM PDT 24
Peak memory 206644 kb
Host smart-8fc70630-8576-4208-9366-9680277284d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32680
8183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.326808183
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.670555829
Short name T188
Test name
Test status
Simulation time 580898419 ps
CPU time 1.38 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 224648 kb
Host smart-de1de145-880f-4f7b-8e1c-1f3ca4e5766e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=670555829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.670555829
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.271908391
Short name T57
Test name
Test status
Simulation time 400320866 ps
CPU time 1.24 seconds
Started Jul 18 05:43:33 PM PDT 24
Finished Jul 18 05:43:49 PM PDT 24
Peak memory 206656 kb
Host smart-c990e046-0504-40cc-a0bb-8583b479117f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27190
8391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.271908391
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1247944656
Short name T2057
Test name
Test status
Simulation time 206703794 ps
CPU time 0.91 seconds
Started Jul 18 05:43:32 PM PDT 24
Finished Jul 18 05:43:48 PM PDT 24
Peak memory 206616 kb
Host smart-5eac03a6-8acb-4e66-aed5-a80ac6437028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12479
44656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1247944656
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1469214705
Short name T2677
Test name
Test status
Simulation time 153400540 ps
CPU time 0.82 seconds
Started Jul 18 05:43:34 PM PDT 24
Finished Jul 18 05:43:49 PM PDT 24
Peak memory 206640 kb
Host smart-31c6cc0f-ebb3-45ec-9e4d-50024f80e11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14692
14705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1469214705
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.3790900739
Short name T1767
Test name
Test status
Simulation time 181069409 ps
CPU time 0.82 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 206640 kb
Host smart-31e1f67a-f8ae-47e2-97d4-8d983768b4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37909
00739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.3790900739
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.785132311
Short name T490
Test name
Test status
Simulation time 199715070 ps
CPU time 0.89 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 206660 kb
Host smart-0476bf8e-a9c1-4155-8e77-6ebd673df4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78513
2311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.785132311
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.3229776836
Short name T1817
Test name
Test status
Simulation time 6483085446 ps
CPU time 61.43 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:44:58 PM PDT 24
Peak memory 206864 kb
Host smart-f57f9426-925f-44bb-a1e2-35e761a15563
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3229776836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.3229776836
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.3132959982
Short name T2081
Test name
Test status
Simulation time 173665619 ps
CPU time 0.79 seconds
Started Jul 18 05:43:41 PM PDT 24
Finished Jul 18 05:43:58 PM PDT 24
Peak memory 206616 kb
Host smart-7ae674b8-6b16-489d-83d7-b256cf0ae452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31329
59982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.3132959982
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.214694101
Short name T2323
Test name
Test status
Simulation time 172469460 ps
CPU time 0.8 seconds
Started Jul 18 05:43:41 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 206620 kb
Host smart-eaddf763-c9c3-4253-a4f1-593145efbdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21469
4101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.214694101
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.1691088433
Short name T334
Test name
Test status
Simulation time 268420721 ps
CPU time 1.06 seconds
Started Jul 18 05:43:35 PM PDT 24
Finished Jul 18 05:43:51 PM PDT 24
Peak memory 206672 kb
Host smart-ce4453ac-ae00-4206-b6c1-8cfb0c60d162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
88433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.1691088433
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.370488430
Short name T1949
Test name
Test status
Simulation time 3357254277 ps
CPU time 23.44 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:44:16 PM PDT 24
Peak memory 206848 kb
Host smart-c8082432-5668-41a0-bef4-9fa44c2f3639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37048
8430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.370488430
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2373556845
Short name T857
Test name
Test status
Simulation time 62641689 ps
CPU time 0.69 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:43 PM PDT 24
Peak memory 206704 kb
Host smart-9366ef0a-edf5-425d-a59b-ac1c61c4bc2d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2373556845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2373556845
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1832142002
Short name T764
Test name
Test status
Simulation time 3915251532 ps
CPU time 4.61 seconds
Started Jul 18 05:45:13 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206716 kb
Host smart-efa0f85b-8a01-40da-acc0-e96f7891cd88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1832142002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1832142002
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.3291535069
Short name T1241
Test name
Test status
Simulation time 13333075545 ps
CPU time 15.24 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:52 PM PDT 24
Peak memory 206868 kb
Host smart-6c46f8c9-bfa4-48e9-a12d-8f737bdceb2b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3291535069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.3291535069
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1667720461
Short name T643
Test name
Test status
Simulation time 23384417307 ps
CPU time 24.53 seconds
Started Jul 18 05:45:22 PM PDT 24
Finished Jul 18 05:46:03 PM PDT 24
Peak memory 206920 kb
Host smart-f33a8b3a-0e6f-4b25-9bcd-0582de1f6a68
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1667720461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1667720461
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.4065452408
Short name T1761
Test name
Test status
Simulation time 239519228 ps
CPU time 0.93 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206656 kb
Host smart-1b15faae-0d79-49c4-8021-aedc87f0acc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40654
52408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.4065452408
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.332158312
Short name T2206
Test name
Test status
Simulation time 140129553 ps
CPU time 0.73 seconds
Started Jul 18 05:45:18 PM PDT 24
Finished Jul 18 05:45:36 PM PDT 24
Peak memory 206656 kb
Host smart-f4b2d022-d604-4753-9576-58f3097e5dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33215
8312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.332158312
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.1525516422
Short name T1983
Test name
Test status
Simulation time 838985781 ps
CPU time 2.08 seconds
Started Jul 18 05:45:21 PM PDT 24
Finished Jul 18 05:45:40 PM PDT 24
Peak memory 206796 kb
Host smart-e4a392b7-26a4-4a66-bf9b-281a7e705c75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15255
16422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.1525516422
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1109948151
Short name T727
Test name
Test status
Simulation time 6265087303 ps
CPU time 11.27 seconds
Started Jul 18 05:45:21 PM PDT 24
Finished Jul 18 05:45:49 PM PDT 24
Peak memory 206908 kb
Host smart-430a2368-9a07-4594-9346-dfb26505f80c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11099
48151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1109948151
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3677363644
Short name T2093
Test name
Test status
Simulation time 555470329 ps
CPU time 1.56 seconds
Started Jul 18 05:45:22 PM PDT 24
Finished Jul 18 05:45:40 PM PDT 24
Peak memory 206648 kb
Host smart-f125630f-b96e-4750-854d-e19f19919486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36773
63644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3677363644
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3098044704
Short name T914
Test name
Test status
Simulation time 147599972 ps
CPU time 0.72 seconds
Started Jul 18 05:45:20 PM PDT 24
Finished Jul 18 05:45:38 PM PDT 24
Peak memory 206532 kb
Host smart-aae0dbe4-8cc3-4c71-be0a-1a4a7e1e0e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30980
44704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3098044704
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.3287963189
Short name T2693
Test name
Test status
Simulation time 100585819 ps
CPU time 0.7 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:42 PM PDT 24
Peak memory 206628 kb
Host smart-b8347545-3de7-41b9-8191-629bd25cd28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32879
63189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.3287963189
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2345923827
Short name T974
Test name
Test status
Simulation time 812922227 ps
CPU time 2.09 seconds
Started Jul 18 05:45:21 PM PDT 24
Finished Jul 18 05:45:40 PM PDT 24
Peak memory 206792 kb
Host smart-0ecca031-98eb-4f47-95d0-5ae1626db246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23459
23827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2345923827
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.2172260133
Short name T1663
Test name
Test status
Simulation time 191374866 ps
CPU time 2.28 seconds
Started Jul 18 05:45:23 PM PDT 24
Finished Jul 18 05:45:42 PM PDT 24
Peak memory 206788 kb
Host smart-16c89ad4-50c4-4ac2-a167-3c583bad2c0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21722
60133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.2172260133
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.4119992230
Short name T904
Test name
Test status
Simulation time 227127358 ps
CPU time 0.85 seconds
Started Jul 18 05:45:21 PM PDT 24
Finished Jul 18 05:45:39 PM PDT 24
Peak memory 206644 kb
Host smart-c60b9443-c13c-4242-8046-6fe20d531531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41199
92230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.4119992230
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.540535612
Short name T2613
Test name
Test status
Simulation time 137247409 ps
CPU time 0.73 seconds
Started Jul 18 05:45:20 PM PDT 24
Finished Jul 18 05:45:38 PM PDT 24
Peak memory 206644 kb
Host smart-0ca988c4-1e3f-4507-b0ee-7579306c2dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54053
5612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.540535612
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.1572963375
Short name T864
Test name
Test status
Simulation time 258616992 ps
CPU time 0.9 seconds
Started Jul 18 05:45:13 PM PDT 24
Finished Jul 18 05:45:28 PM PDT 24
Peak memory 206660 kb
Host smart-ec24bb32-719e-454a-8eaf-d50202a0ab5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15729
63375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.1572963375
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.3264591556
Short name T1139
Test name
Test status
Simulation time 6712648986 ps
CPU time 58.72 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:46:35 PM PDT 24
Peak memory 206904 kb
Host smart-ec8677b5-1cbe-4cbb-924f-a0ee2579377a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32645
91556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.3264591556
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.4026306767
Short name T2214
Test name
Test status
Simulation time 217896143 ps
CPU time 0.92 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:42 PM PDT 24
Peak memory 205984 kb
Host smart-cb6f9fd6-0c80-45bb-b511-daed8b1f6280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40263
06767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.4026306767
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.2864637875
Short name T853
Test name
Test status
Simulation time 23306874318 ps
CPU time 20.82 seconds
Started Jul 18 05:45:13 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206776 kb
Host smart-843b3251-b0a5-43a3-bafa-c13cf2bb92de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
37875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.2864637875
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1054450306
Short name T2602
Test name
Test status
Simulation time 3311436727 ps
CPU time 3.55 seconds
Started Jul 18 05:45:22 PM PDT 24
Finished Jul 18 05:45:43 PM PDT 24
Peak memory 206588 kb
Host smart-168be79e-48e7-4239-9b8c-2e0e94ccda54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544
50306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1054450306
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2788748217
Short name T2133
Test name
Test status
Simulation time 8415781136 ps
CPU time 230.05 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:49:31 PM PDT 24
Peak memory 206288 kb
Host smart-ba9de156-f4b7-413e-a03d-cc701166a534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27887
48217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2788748217
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.1825380098
Short name T1380
Test name
Test status
Simulation time 7942390993 ps
CPU time 204.14 seconds
Started Jul 18 05:45:22 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206696 kb
Host smart-7d66ce59-ad87-4d50-993c-ac64ed19f8ce
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1825380098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.1825380098
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.4237445493
Short name T829
Test name
Test status
Simulation time 266267489 ps
CPU time 0.91 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:42 PM PDT 24
Peak memory 206632 kb
Host smart-c01b6403-14e2-4d8e-8ccc-e989cbe44c91
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4237445493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.4237445493
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.897819514
Short name T666
Test name
Test status
Simulation time 202935807 ps
CPU time 0.86 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206636 kb
Host smart-4fb25e28-f26d-42a1-a9e8-c1a399421fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89781
9514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.897819514
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.4280451704
Short name T2664
Test name
Test status
Simulation time 4412230734 ps
CPU time 30.68 seconds
Started Jul 18 05:45:20 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206744 kb
Host smart-9ed5099a-2fc0-4c32-b6bf-f1bc356ab0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42804
51704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.4280451704
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.243049353
Short name T863
Test name
Test status
Simulation time 3473215925 ps
CPU time 95.04 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:47:01 PM PDT 24
Peak memory 206836 kb
Host smart-b7af560e-8498-4a94-b361-f4c0124161fc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=243049353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.243049353
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.2409334633
Short name T2278
Test name
Test status
Simulation time 149435457 ps
CPU time 0.83 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:45:27 PM PDT 24
Peak memory 206636 kb
Host smart-eba85141-4d67-4176-b643-6e545ae6419a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2409334633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.2409334633
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.153177244
Short name T2742
Test name
Test status
Simulation time 157598149 ps
CPU time 0.82 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206648 kb
Host smart-79598d05-e4c2-4f4c-8932-1c684c209e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15317
7244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.153177244
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1731348352
Short name T650
Test name
Test status
Simulation time 168501832 ps
CPU time 0.84 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206620 kb
Host smart-fc45820b-d260-48fd-9910-794705d52d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17313
48352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1731348352
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2222654145
Short name T652
Test name
Test status
Simulation time 150215661 ps
CPU time 0.77 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206816 kb
Host smart-8cb7ae33-3071-452d-800d-54708e517de5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
54145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2222654145
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1244194222
Short name T1047
Test name
Test status
Simulation time 175421594 ps
CPU time 0.83 seconds
Started Jul 18 05:45:14 PM PDT 24
Finished Jul 18 05:45:29 PM PDT 24
Peak memory 206676 kb
Host smart-f43d7dd1-170f-4985-a926-066bca00afd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12441
94222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1244194222
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.4219480916
Short name T954
Test name
Test status
Simulation time 157922660 ps
CPU time 0.79 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:45:33 PM PDT 24
Peak memory 206620 kb
Host smart-b1b42c9c-a3f0-403e-a447-27699720405a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42194
80916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.4219480916
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.245047688
Short name T1270
Test name
Test status
Simulation time 210890424 ps
CPU time 0.97 seconds
Started Jul 18 05:45:11 PM PDT 24
Finished Jul 18 05:45:25 PM PDT 24
Peak memory 206652 kb
Host smart-d9a80565-2d34-461c-a4db-024440a5ddbf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=245047688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.245047688
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.1640585182
Short name T2501
Test name
Test status
Simulation time 145997858 ps
CPU time 0.75 seconds
Started Jul 18 05:45:11 PM PDT 24
Finished Jul 18 05:45:25 PM PDT 24
Peak memory 206636 kb
Host smart-1dbc60d7-73ef-4a3d-b575-41fe5c013de4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16405
85182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.1640585182
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3255485171
Short name T1547
Test name
Test status
Simulation time 32023158 ps
CPU time 0.67 seconds
Started Jul 18 05:45:13 PM PDT 24
Finished Jul 18 05:45:28 PM PDT 24
Peak memory 206664 kb
Host smart-dd57fa50-9da3-4eae-a38b-6dcd75dd6567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32554
85171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3255485171
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.3470938350
Short name T1352
Test name
Test status
Simulation time 17291831519 ps
CPU time 35.76 seconds
Started Jul 18 05:45:20 PM PDT 24
Finished Jul 18 05:46:13 PM PDT 24
Peak memory 206932 kb
Host smart-ab7bf9dd-6a7a-43c3-bb57-bff389fa060f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34709
38350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.3470938350
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.446071864
Short name T2730
Test name
Test status
Simulation time 176134480 ps
CPU time 0.87 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206656 kb
Host smart-e5bd099b-b544-4fe7-baee-18b5630f96d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44607
1864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.446071864
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2576144188
Short name T1556
Test name
Test status
Simulation time 195379087 ps
CPU time 0.9 seconds
Started Jul 18 05:45:20 PM PDT 24
Finished Jul 18 05:45:38 PM PDT 24
Peak memory 206612 kb
Host smart-433a098a-a4c1-4fd1-a3f2-0e64b89ca94b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25761
44188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2576144188
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3591720245
Short name T932
Test name
Test status
Simulation time 224611099 ps
CPU time 0.85 seconds
Started Jul 18 05:45:21 PM PDT 24
Finished Jul 18 05:45:39 PM PDT 24
Peak memory 206636 kb
Host smart-620171f8-023d-4f76-a7eb-f5f859b1346e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
20245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3591720245
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.1740619329
Short name T1859
Test name
Test status
Simulation time 170555510 ps
CPU time 0.76 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206492 kb
Host smart-a8426739-d55a-4790-8074-cf10087cefa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17406
19329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.1740619329
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.4196833899
Short name T1068
Test name
Test status
Simulation time 200301657 ps
CPU time 0.86 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206636 kb
Host smart-1aeeef3b-2519-4525-8856-6aa689000ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41968
33899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.4196833899
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.4172025527
Short name T1064
Test name
Test status
Simulation time 156973685 ps
CPU time 0.77 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206632 kb
Host smart-0be31a6a-6c01-46da-a833-9493baa974e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
25527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.4172025527
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.187610773
Short name T2017
Test name
Test status
Simulation time 197099142 ps
CPU time 0.79 seconds
Started Jul 18 05:45:31 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206620 kb
Host smart-7a5a1311-7e89-4ced-a3c6-b83237b1f6a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18761
0773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.187610773
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1177199722
Short name T515
Test name
Test status
Simulation time 208745094 ps
CPU time 0.89 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206636 kb
Host smart-87c769a7-73fa-4e60-9ff9-e81954b57bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11771
99722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1177199722
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2929822180
Short name T1053
Test name
Test status
Simulation time 5992233603 ps
CPU time 169.63 seconds
Started Jul 18 05:45:29 PM PDT 24
Finished Jul 18 05:48:36 PM PDT 24
Peak memory 206884 kb
Host smart-dd0c0129-c1b1-48ed-ba13-8653392ddbd2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2929822180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2929822180
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2444816550
Short name T797
Test name
Test status
Simulation time 176821836 ps
CPU time 0.83 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:42 PM PDT 24
Peak memory 206612 kb
Host smart-47acee6d-132e-47d1-a8a8-eeb81baf0792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24448
16550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2444816550
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.4166653971
Short name T1815
Test name
Test status
Simulation time 151516972 ps
CPU time 0.83 seconds
Started Jul 18 05:45:29 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206628 kb
Host smart-a7a42ae1-5aec-47d8-a628-034ede0d8ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666
53971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.4166653971
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.4094866248
Short name T2352
Test name
Test status
Simulation time 693505347 ps
CPU time 1.88 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206784 kb
Host smart-a0027c8b-f923-457a-a2e3-826762907c71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40948
66248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.4094866248
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.2465981948
Short name T314
Test name
Test status
Simulation time 3267382741 ps
CPU time 91.79 seconds
Started Jul 18 05:45:26 PM PDT 24
Finished Jul 18 05:47:15 PM PDT 24
Peak memory 206848 kb
Host smart-f98390c8-0cbb-4ad6-a135-adba289980a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24659
81948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.2465981948
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3005382860
Short name T850
Test name
Test status
Simulation time 4113050743 ps
CPU time 4.81 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:46 PM PDT 24
Peak memory 206788 kb
Host smart-9e15077f-9153-4665-9764-c7b5746c8a82
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3005382860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3005382860
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.251286019
Short name T487
Test name
Test status
Simulation time 13311344144 ps
CPU time 12.82 seconds
Started Jul 18 05:45:32 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206776 kb
Host smart-877e1742-ece4-431b-bde4-bc42a136cfb8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=251286019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.251286019
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.784777910
Short name T1689
Test name
Test status
Simulation time 23413966212 ps
CPU time 24.71 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206928 kb
Host smart-856dc7ec-4a5f-4cce-a696-7a059d9b28b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=784777910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.784777910
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.2847484696
Short name T687
Test name
Test status
Simulation time 181403978 ps
CPU time 0.91 seconds
Started Jul 18 05:45:31 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206624 kb
Host smart-143148c4-d370-4342-a1e4-ec3d93c6108f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28474
84696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.2847484696
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.4027691796
Short name T1448
Test name
Test status
Simulation time 147632312 ps
CPU time 0.77 seconds
Started Jul 18 05:45:28 PM PDT 24
Finished Jul 18 05:45:46 PM PDT 24
Peak memory 206644 kb
Host smart-2522091e-e051-41ae-8e15-b6a26eb0a26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40276
91796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.4027691796
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3838847128
Short name T735
Test name
Test status
Simulation time 506634975 ps
CPU time 1.66 seconds
Started Jul 18 05:45:31 PM PDT 24
Finished Jul 18 05:45:49 PM PDT 24
Peak memory 206608 kb
Host smart-71f2a343-ebf3-4b3d-a44a-984446f65146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38388
47128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3838847128
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.3671049263
Short name T1227
Test name
Test status
Simulation time 658210038 ps
CPU time 1.75 seconds
Started Jul 18 05:53:26 PM PDT 24
Finished Jul 18 05:53:34 PM PDT 24
Peak memory 206736 kb
Host smart-3fb4666a-1065-4657-9e91-c171836b7dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36710
49263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.3671049263
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2446504639
Short name T2656
Test name
Test status
Simulation time 12398888080 ps
CPU time 23.14 seconds
Started Jul 18 05:45:29 PM PDT 24
Finished Jul 18 05:46:09 PM PDT 24
Peak memory 206832 kb
Host smart-53d0fd5a-2052-4dfe-9c98-dab3e7714ad5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24465
04639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2446504639
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1686999860
Short name T86
Test name
Test status
Simulation time 441029788 ps
CPU time 1.38 seconds
Started Jul 18 05:45:28 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206640 kb
Host smart-5a2bb50b-9a3f-4d8b-8501-4ed01deb9814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16869
99860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1686999860
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1488206002
Short name T1361
Test name
Test status
Simulation time 141111347 ps
CPU time 0.75 seconds
Started Jul 18 05:45:24 PM PDT 24
Finished Jul 18 05:45:41 PM PDT 24
Peak memory 206632 kb
Host smart-7aa8d60b-3a8a-4885-94bb-fde12f8bc5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14882
06002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1488206002
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3263846385
Short name T1369
Test name
Test status
Simulation time 95217723 ps
CPU time 0.76 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206632 kb
Host smart-3903188a-5e36-4f21-84ff-e87be2079005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32638
46385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3263846385
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.2349326647
Short name T607
Test name
Test status
Simulation time 876072620 ps
CPU time 2.05 seconds
Started Jul 18 05:45:28 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206780 kb
Host smart-3b6eb356-cb15-4078-8dc6-2a1485123bfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23493
26647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.2349326647
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.2393156389
Short name T1678
Test name
Test status
Simulation time 204342688 ps
CPU time 0.88 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:44 PM PDT 24
Peak memory 206612 kb
Host smart-4bc8af5e-ca33-4fc8-afa2-966ebf101315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23931
56389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.2393156389
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.3477659143
Short name T493
Test name
Test status
Simulation time 143552030 ps
CPU time 0.75 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206644 kb
Host smart-719c3601-10e9-4940-8422-2b2543efe957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34776
59143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.3477659143
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.1737803025
Short name T1401
Test name
Test status
Simulation time 214324702 ps
CPU time 0.91 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:43 PM PDT 24
Peak memory 206660 kb
Host smart-cdf0e056-2141-4209-9724-2a2b29a7d9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17378
03025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.1737803025
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.391451004
Short name T2618
Test name
Test status
Simulation time 13473522606 ps
CPU time 103.18 seconds
Started Jul 18 05:45:28 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206856 kb
Host smart-51f12c9f-c1d9-4221-a1d3-c4c1083589ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39145
1004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.391451004
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.1506663429
Short name T913
Test name
Test status
Simulation time 232443040 ps
CPU time 0.93 seconds
Started Jul 18 05:45:29 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206652 kb
Host smart-2a0fc42f-f9e4-467f-801f-e9be60516469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15066
63429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.1506663429
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.2523788404
Short name T1655
Test name
Test status
Simulation time 23375861738 ps
CPU time 24.52 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:46:09 PM PDT 24
Peak memory 206744 kb
Host smart-2ace8301-4019-4cb3-b97c-6224795063db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25237
88404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.2523788404
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.801133897
Short name T1639
Test name
Test status
Simulation time 3276843008 ps
CPU time 4.19 seconds
Started Jul 18 05:45:32 PM PDT 24
Finished Jul 18 05:45:52 PM PDT 24
Peak memory 206700 kb
Host smart-b57e6266-4b45-4d49-988f-b531eacc3490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80113
3897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.801133897
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.2086127012
Short name T2728
Test name
Test status
Simulation time 8114225368 ps
CPU time 227.63 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:49:32 PM PDT 24
Peak memory 206944 kb
Host smart-c8e6b9bd-90fc-48f1-885c-4625c8c4c5dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20861
27012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.2086127012
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3256612302
Short name T393
Test name
Test status
Simulation time 5375524538 ps
CPU time 38.02 seconds
Started Jul 18 05:45:24 PM PDT 24
Finished Jul 18 05:46:19 PM PDT 24
Peak memory 206848 kb
Host smart-fc078433-a784-4a6a-8608-36601386ddc5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3256612302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3256612302
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1850946524
Short name T1018
Test name
Test status
Simulation time 252215792 ps
CPU time 0.91 seconds
Started Jul 18 05:45:31 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206624 kb
Host smart-7dcfabb8-a727-4b73-9eb2-956f07b0b193
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1850946524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1850946524
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1878093476
Short name T1706
Test name
Test status
Simulation time 192621712 ps
CPU time 0.9 seconds
Started Jul 18 05:45:26 PM PDT 24
Finished Jul 18 05:45:43 PM PDT 24
Peak memory 206648 kb
Host smart-6b8d7aa5-300a-43bf-a2fc-4f0a7577b40d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18780
93476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1878093476
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2728514178
Short name T2519
Test name
Test status
Simulation time 4779360300 ps
CPU time 133.78 seconds
Started Jul 18 05:45:29 PM PDT 24
Finished Jul 18 05:48:00 PM PDT 24
Peak memory 206880 kb
Host smart-53c06d66-35a4-45a4-b0ac-b5f2cafd2503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27285
14178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2728514178
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.2975841232
Short name T1339
Test name
Test status
Simulation time 5549166966 ps
CPU time 155.71 seconds
Started Jul 18 05:45:32 PM PDT 24
Finished Jul 18 05:48:24 PM PDT 24
Peak memory 206836 kb
Host smart-ff4ad9ce-430c-4e90-86ca-6b64eb53bd4f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2975841232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.2975841232
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.2419346291
Short name T2060
Test name
Test status
Simulation time 170429827 ps
CPU time 0.88 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:44 PM PDT 24
Peak memory 206648 kb
Host smart-8eae5482-2074-4fdf-92a4-1de9dbadae16
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2419346291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.2419346291
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2554517353
Short name T2389
Test name
Test status
Simulation time 198306605 ps
CPU time 0.78 seconds
Started Jul 18 05:45:29 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206628 kb
Host smart-44392f46-fb18-4556-b326-b9fec9484e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25545
17353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2554517353
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3670535381
Short name T2295
Test name
Test status
Simulation time 224240451 ps
CPU time 0.83 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:44 PM PDT 24
Peak memory 206632 kb
Host smart-145279e3-d61f-4511-a5eb-06549056dbef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36705
35381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3670535381
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1663211092
Short name T1363
Test name
Test status
Simulation time 194180329 ps
CPU time 0.84 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:44 PM PDT 24
Peak memory 206672 kb
Host smart-83092361-1596-4a1b-8fe9-715540378b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16632
11092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1663211092
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3230502196
Short name T2723
Test name
Test status
Simulation time 191790370 ps
CPU time 0.9 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:46 PM PDT 24
Peak memory 206820 kb
Host smart-0abe91fa-42b9-4ec7-8a53-0155f3f052db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32305
02196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3230502196
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2094108674
Short name T470
Test name
Test status
Simulation time 176091692 ps
CPU time 0.86 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:43 PM PDT 24
Peak memory 206656 kb
Host smart-c4c7f54e-5087-491d-9b03-4c2bb6905bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20941
08674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2094108674
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.1397038892
Short name T2573
Test name
Test status
Simulation time 174514966 ps
CPU time 0.86 seconds
Started Jul 18 05:45:25 PM PDT 24
Finished Jul 18 05:45:43 PM PDT 24
Peak memory 206628 kb
Host smart-9b315d0a-6b3a-4780-86ba-ecbd32873d73
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1397038892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.1397038892
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.2962286947
Short name T1801
Test name
Test status
Simulation time 137998965 ps
CPU time 0.76 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206648 kb
Host smart-d7aa100e-dc26-4c11-9dc0-1f335f313876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29622
86947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.2962286947
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.2334931499
Short name T896
Test name
Test status
Simulation time 40559864 ps
CPU time 0.68 seconds
Started Jul 18 05:45:26 PM PDT 24
Finished Jul 18 05:45:44 PM PDT 24
Peak memory 206652 kb
Host smart-cc8d9d6f-d440-4ba5-be0d-60cb6d304727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23349
31499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.2334931499
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.1006964796
Short name T1582
Test name
Test status
Simulation time 23925939393 ps
CPU time 52.35 seconds
Started Jul 18 05:45:31 PM PDT 24
Finished Jul 18 05:46:40 PM PDT 24
Peak memory 206904 kb
Host smart-b181f971-74d9-44ae-be00-1beecc975e95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10069
64796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.1006964796
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.3841705442
Short name T2570
Test name
Test status
Simulation time 177185698 ps
CPU time 0.9 seconds
Started Jul 18 05:45:27 PM PDT 24
Finished Jul 18 05:45:46 PM PDT 24
Peak memory 206652 kb
Host smart-0da9cbda-7f04-4898-95b6-ae06527cdc17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38417
05442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.3841705442
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.1750270006
Short name T1405
Test name
Test status
Simulation time 200467183 ps
CPU time 0.85 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206616 kb
Host smart-f118b1d8-adb4-42d0-84cd-a82d0fbbc0f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17502
70006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.1750270006
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2215649195
Short name T1103
Test name
Test status
Simulation time 192044511 ps
CPU time 0.82 seconds
Started Jul 18 05:45:42 PM PDT 24
Finished Jul 18 05:45:58 PM PDT 24
Peak memory 206624 kb
Host smart-cbeba132-7f0e-4f6f-bfb1-e2b65a43ed29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22156
49195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2215649195
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.260726579
Short name T581
Test name
Test status
Simulation time 165626466 ps
CPU time 0.78 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206616 kb
Host smart-69aeb523-9443-4bf1-8e2c-1451de9b3ccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26072
6579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.260726579
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.3985379168
Short name T2708
Test name
Test status
Simulation time 138864065 ps
CPU time 0.78 seconds
Started Jul 18 05:45:40 PM PDT 24
Finished Jul 18 05:45:56 PM PDT 24
Peak memory 206624 kb
Host smart-2fa1c7f9-6639-409e-bf1c-0dca10e88c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39853
79168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.3985379168
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.922711862
Short name T938
Test name
Test status
Simulation time 166139294 ps
CPU time 0.79 seconds
Started Jul 18 05:45:51 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206664 kb
Host smart-c3e2275c-298d-4bf1-868b-63a744125e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92271
1862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.922711862
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.3182209931
Short name T1308
Test name
Test status
Simulation time 172714912 ps
CPU time 0.85 seconds
Started Jul 18 05:45:44 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 206616 kb
Host smart-c9c2b45b-c4d9-49d9-b0d9-5f38f449e0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31822
09931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.3182209931
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.4251649831
Short name T1372
Test name
Test status
Simulation time 229201136 ps
CPU time 0.92 seconds
Started Jul 18 05:45:45 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206628 kb
Host smart-367c84e7-00cf-48ef-87ca-c48cf15be220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42516
49831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.4251649831
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.3492075018
Short name T2202
Test name
Test status
Simulation time 5392778154 ps
CPU time 39.89 seconds
Started Jul 18 05:45:46 PM PDT 24
Finished Jul 18 05:46:40 PM PDT 24
Peak memory 206848 kb
Host smart-42113e58-9929-4ede-ace4-ed83fce5123e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3492075018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.3492075018
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.756067596
Short name T1682
Test name
Test status
Simulation time 182982069 ps
CPU time 0.83 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206644 kb
Host smart-05f3e126-29df-464b-8bcd-f90714b65559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75606
7596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.756067596
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.130507311
Short name T1681
Test name
Test status
Simulation time 172006907 ps
CPU time 0.8 seconds
Started Jul 18 05:45:39 PM PDT 24
Finished Jul 18 05:45:55 PM PDT 24
Peak memory 206636 kb
Host smart-e0587bb9-55db-4b2f-b863-b6271c825bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13050
7311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.130507311
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.4097875513
Short name T1481
Test name
Test status
Simulation time 646253437 ps
CPU time 1.58 seconds
Started Jul 18 05:45:38 PM PDT 24
Finished Jul 18 05:45:55 PM PDT 24
Peak memory 206640 kb
Host smart-549bf08e-554c-4d5b-abb1-29a6cf1ed326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40978
75513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.4097875513
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3281750635
Short name T2079
Test name
Test status
Simulation time 5207862011 ps
CPU time 36.68 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:46:32 PM PDT 24
Peak memory 206888 kb
Host smart-15c9a4ee-f901-4a5c-af3b-f72ed6b7b33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32817
50635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3281750635
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.1643750723
Short name T1855
Test name
Test status
Simulation time 55099153 ps
CPU time 0.71 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206692 kb
Host smart-7dbfce6a-9cdf-469e-b987-252869c72416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1643750723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.1643750723
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.165488441
Short name T11
Test name
Test status
Simulation time 23366082515 ps
CPU time 22.21 seconds
Started Jul 18 05:45:43 PM PDT 24
Finished Jul 18 05:46:20 PM PDT 24
Peak memory 206928 kb
Host smart-eabee468-ce27-4c9d-a14b-914044258a15
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=165488441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.165488441
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2073430115
Short name T2635
Test name
Test status
Simulation time 157114657 ps
CPU time 0.77 seconds
Started Jul 18 05:45:40 PM PDT 24
Finished Jul 18 05:45:56 PM PDT 24
Peak memory 206668 kb
Host smart-033f77b4-461b-49b8-ab95-0fad27935518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20734
30115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2073430115
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.325695035
Short name T1288
Test name
Test status
Simulation time 145155183 ps
CPU time 0.81 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206640 kb
Host smart-6d57f0a5-94bd-423e-ae67-24c3a5252dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32569
5035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.325695035
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2506590745
Short name T821
Test name
Test status
Simulation time 383556473 ps
CPU time 1.24 seconds
Started Jul 18 05:45:38 PM PDT 24
Finished Jul 18 05:45:55 PM PDT 24
Peak memory 206612 kb
Host smart-e95b4f5f-c7ef-4305-b5fc-c02315b72026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25065
90745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2506590745
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.624437982
Short name T1963
Test name
Test status
Simulation time 349367451 ps
CPU time 1.06 seconds
Started Jul 18 05:45:39 PM PDT 24
Finished Jul 18 05:45:55 PM PDT 24
Peak memory 206652 kb
Host smart-0f2dacb7-1a3e-428c-8b62-4dfaeed7277a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62443
7982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.624437982
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.1097534449
Short name T526
Test name
Test status
Simulation time 9690972871 ps
CPU time 19.52 seconds
Started Jul 18 05:45:43 PM PDT 24
Finished Jul 18 05:46:17 PM PDT 24
Peak memory 206848 kb
Host smart-c95c63b3-59e3-4af7-b472-5779ff5a5c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10975
34449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.1097534449
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.4278275250
Short name T893
Test name
Test status
Simulation time 382969520 ps
CPU time 1.22 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206328 kb
Host smart-df881bce-5a0a-423e-a392-e398600097b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42782
75250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.4278275250
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.990963267
Short name T998
Test name
Test status
Simulation time 142873265 ps
CPU time 0.79 seconds
Started Jul 18 05:45:46 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206672 kb
Host smart-50d7f07c-86fe-4531-a092-049403ce8615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99096
3267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.990963267
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3075235169
Short name T859
Test name
Test status
Simulation time 109024591 ps
CPU time 0.77 seconds
Started Jul 18 05:45:45 PM PDT 24
Finished Jul 18 05:46:00 PM PDT 24
Peak memory 206628 kb
Host smart-dc84e403-7bab-4623-99d1-0f0e4ff9d1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30752
35169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3075235169
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2247752826
Short name T2463
Test name
Test status
Simulation time 1031480167 ps
CPU time 2.37 seconds
Started Jul 18 05:45:43 PM PDT 24
Finished Jul 18 05:46:00 PM PDT 24
Peak memory 206756 kb
Host smart-bdb125b8-0b24-4154-97e8-ccbf552e2a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22477
52826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2247752826
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2314339192
Short name T1158
Test name
Test status
Simulation time 269619689 ps
CPU time 1.89 seconds
Started Jul 18 05:45:39 PM PDT 24
Finished Jul 18 05:45:56 PM PDT 24
Peak memory 206788 kb
Host smart-7612e012-a255-43e7-a1ac-76256b98e561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23143
39192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2314339192
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.4145637860
Short name T1375
Test name
Test status
Simulation time 220116354 ps
CPU time 0.88 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206664 kb
Host smart-1620b540-a764-4887-a14a-2c11e7a42a61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41456
37860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.4145637860
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4236994693
Short name T2413
Test name
Test status
Simulation time 143110707 ps
CPU time 0.8 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206644 kb
Host smart-ad395c71-e502-4852-9671-030e28255bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42369
94693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4236994693
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.2956012542
Short name T2509
Test name
Test status
Simulation time 203120346 ps
CPU time 0.85 seconds
Started Jul 18 05:45:51 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206640 kb
Host smart-1279fc79-eee1-47cb-8b13-2aa19ece7444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
12542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.2956012542
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.570111445
Short name T101
Test name
Test status
Simulation time 5058166208 ps
CPU time 48.9 seconds
Started Jul 18 05:45:38 PM PDT 24
Finished Jul 18 05:46:43 PM PDT 24
Peak memory 206920 kb
Host smart-cd8eacec-6f4b-460c-bbad-7aa0433bae5b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=570111445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.570111445
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2354479688
Short name T319
Test name
Test status
Simulation time 7025786140 ps
CPU time 29.05 seconds
Started Jul 18 05:46:12 PM PDT 24
Finished Jul 18 05:46:46 PM PDT 24
Peak memory 206832 kb
Host smart-e72afc0c-f050-4815-9f69-dfc0c9241a38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23544
79688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2354479688
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.4146360694
Short name T2195
Test name
Test status
Simulation time 188489726 ps
CPU time 0.84 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206624 kb
Host smart-c360b9cc-f20b-410f-be91-19b6ca7ce796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
60694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.4146360694
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.1121729640
Short name T1149
Test name
Test status
Simulation time 23293117532 ps
CPU time 22.21 seconds
Started Jul 18 05:45:48 PM PDT 24
Finished Jul 18 05:46:24 PM PDT 24
Peak memory 206776 kb
Host smart-7f535a52-46fd-4a90-b7e1-a64ce34bf763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
29640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.1121729640
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.1990463466
Short name T810
Test name
Test status
Simulation time 3364634570 ps
CPU time 4.05 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206676 kb
Host smart-5b7dc1f0-2189-47d6-a5d6-c6304ec7baf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19904
63466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.1990463466
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3219141392
Short name T1640
Test name
Test status
Simulation time 6009455759 ps
CPU time 39.4 seconds
Started Jul 18 05:45:37 PM PDT 24
Finished Jul 18 05:46:32 PM PDT 24
Peak memory 206908 kb
Host smart-03b11357-8c46-4bc2-92e1-61980dc11b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32191
41392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3219141392
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.157491233
Short name T394
Test name
Test status
Simulation time 3650256653 ps
CPU time 35.49 seconds
Started Jul 18 05:45:44 PM PDT 24
Finished Jul 18 05:46:35 PM PDT 24
Peak memory 206856 kb
Host smart-cdf41e3a-f1e6-4182-83bd-0c01ecdba9ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=157491233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.157491233
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.982255645
Short name T1254
Test name
Test status
Simulation time 240781520 ps
CPU time 0.99 seconds
Started Jul 18 05:45:42 PM PDT 24
Finished Jul 18 05:45:58 PM PDT 24
Peak memory 206600 kb
Host smart-fd1b9689-82c7-4109-b6c7-7f7da2d8cc19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=982255645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.982255645
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1705173406
Short name T384
Test name
Test status
Simulation time 190368061 ps
CPU time 0.88 seconds
Started Jul 18 05:45:42 PM PDT 24
Finished Jul 18 05:45:58 PM PDT 24
Peak memory 206592 kb
Host smart-ca9a1479-b1a1-41e2-8dea-9ed4b57f9012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17051
73406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1705173406
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.2681776700
Short name T1589
Test name
Test status
Simulation time 3550990762 ps
CPU time 26.7 seconds
Started Jul 18 05:45:39 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 206884 kb
Host smart-c819e1c7-293f-4af1-ae20-4220d45e9313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26817
76700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.2681776700
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.538055681
Short name T2330
Test name
Test status
Simulation time 6871973982 ps
CPU time 196.25 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:49:17 PM PDT 24
Peak memory 206872 kb
Host smart-32e782fd-5706-4048-9886-fa674078c6dc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=538055681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.538055681
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.523082902
Short name T458
Test name
Test status
Simulation time 158113558 ps
CPU time 0.8 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206640 kb
Host smart-0738904a-b791-4e77-b193-32704fc9d9c5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=523082902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.523082902
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2632483387
Short name T993
Test name
Test status
Simulation time 150764955 ps
CPU time 0.8 seconds
Started Jul 18 05:45:45 PM PDT 24
Finished Jul 18 05:46:00 PM PDT 24
Peak memory 206624 kb
Host smart-a6cf1f56-0d1a-4ecd-a087-9d394da363e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26324
83387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2632483387
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3603347089
Short name T659
Test name
Test status
Simulation time 157218586 ps
CPU time 0.8 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206616 kb
Host smart-31921014-4fa6-4448-b27e-20d5782d6beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36033
47089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3603347089
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.1691999943
Short name T518
Test name
Test status
Simulation time 156312173 ps
CPU time 0.8 seconds
Started Jul 18 05:45:40 PM PDT 24
Finished Jul 18 05:45:56 PM PDT 24
Peak memory 206640 kb
Host smart-20b33e7b-34ee-4cc3-b12a-574cd79d159a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16919
99943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.1691999943
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.1998036076
Short name T1581
Test name
Test status
Simulation time 183932827 ps
CPU time 0.8 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206204 kb
Host smart-12804c76-f8bd-4a77-96a6-a383b41768ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19980
36076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.1998036076
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2409986308
Short name T976
Test name
Test status
Simulation time 146106396 ps
CPU time 0.82 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206668 kb
Host smart-5812bb01-8825-49f7-97b2-8d842cfc4923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24099
86308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2409986308
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.4229706799
Short name T1617
Test name
Test status
Simulation time 264070828 ps
CPU time 0.91 seconds
Started Jul 18 05:45:38 PM PDT 24
Finished Jul 18 05:45:54 PM PDT 24
Peak memory 206612 kb
Host smart-17def4fe-e81a-469e-9951-6d320a2bc2ff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4229706799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.4229706799
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.1248596660
Short name T1450
Test name
Test status
Simulation time 150962063 ps
CPU time 0.77 seconds
Started Jul 18 05:45:44 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 206628 kb
Host smart-7bc2a3b0-e21d-4230-b6e9-389f181f27a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12485
96660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.1248596660
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.1806716536
Short name T2521
Test name
Test status
Simulation time 64408672 ps
CPU time 0.73 seconds
Started Jul 18 05:45:44 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 206600 kb
Host smart-7ec99d14-0f1e-46dd-b0ea-20d2f9152176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18067
16536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.1806716536
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.622024359
Short name T231
Test name
Test status
Simulation time 10919552815 ps
CPU time 22.49 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:46:18 PM PDT 24
Peak memory 206812 kb
Host smart-4d14058d-6886-4c96-b087-9db4e5d181a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62202
4359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.622024359
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1719943121
Short name T1154
Test name
Test status
Simulation time 171707306 ps
CPU time 0.83 seconds
Started Jul 18 05:45:48 PM PDT 24
Finished Jul 18 05:46:03 PM PDT 24
Peak memory 206620 kb
Host smart-0bc43ffa-a499-4646-8f94-c41b0f8bad3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17199
43121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1719943121
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2449159506
Short name T627
Test name
Test status
Simulation time 183891485 ps
CPU time 0.86 seconds
Started Jul 18 05:45:39 PM PDT 24
Finished Jul 18 05:45:55 PM PDT 24
Peak memory 206648 kb
Host smart-c6ec1715-92ee-4012-9613-98d6711b7290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24491
59506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2449159506
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1446443933
Short name T2752
Test name
Test status
Simulation time 285366121 ps
CPU time 1 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206636 kb
Host smart-892a737b-68d7-4cf3-870d-4fa0e08a7754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464
43933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1446443933
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.3726819877
Short name T899
Test name
Test status
Simulation time 161529337 ps
CPU time 0.82 seconds
Started Jul 18 05:45:46 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206620 kb
Host smart-7c72c2cd-f276-4c6f-97be-68c9126a1587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37268
19877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.3726819877
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.930948920
Short name T2049
Test name
Test status
Simulation time 144360509 ps
CPU time 0.82 seconds
Started Jul 18 05:45:44 PM PDT 24
Finished Jul 18 05:46:00 PM PDT 24
Peak memory 206616 kb
Host smart-04eb10c4-1811-410b-8b69-ca321906d105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93094
8920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.930948920
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.3355408296
Short name T1026
Test name
Test status
Simulation time 153324574 ps
CPU time 0.82 seconds
Started Jul 18 05:45:43 PM PDT 24
Finished Jul 18 05:45:58 PM PDT 24
Peak memory 206632 kb
Host smart-06447034-1577-456a-87b4-d9f6fdac9c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33554
08296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.3355408296
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.716762545
Short name T1540
Test name
Test status
Simulation time 181915575 ps
CPU time 0.8 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:57 PM PDT 24
Peak memory 206612 kb
Host smart-0269be05-2a83-465b-9ccf-f4ef97027fe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71676
2545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.716762545
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.3189689186
Short name T1823
Test name
Test status
Simulation time 234809418 ps
CPU time 0.98 seconds
Started Jul 18 05:45:51 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206660 kb
Host smart-d5ce8475-e378-40ec-ba14-de4c44642a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31896
89186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.3189689186
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.1878729657
Short name T466
Test name
Test status
Simulation time 4198780884 ps
CPU time 39.51 seconds
Started Jul 18 05:45:42 PM PDT 24
Finished Jul 18 05:46:37 PM PDT 24
Peak memory 206780 kb
Host smart-9ce00ff3-2225-448b-8b73-ed2b1e9202c8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1878729657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.1878729657
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.3030502634
Short name T2319
Test name
Test status
Simulation time 182285688 ps
CPU time 0.87 seconds
Started Jul 18 05:45:43 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 206636 kb
Host smart-29fd3aae-a8c4-45e5-8eb3-cd5355e9f00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30305
02634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.3030502634
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1576312887
Short name T587
Test name
Test status
Simulation time 166027364 ps
CPU time 0.78 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206668 kb
Host smart-6817cb27-5eb6-415a-9fd2-051bc8cb9b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15763
12887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1576312887
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.2676632103
Short name T529
Test name
Test status
Simulation time 1208785140 ps
CPU time 2.51 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206740 kb
Host smart-e2564874-6358-472a-afe3-65798fb6def8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26766
32103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.2676632103
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.843382268
Short name T617
Test name
Test status
Simulation time 5612620102 ps
CPU time 153.31 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:48:34 PM PDT 24
Peak memory 206832 kb
Host smart-45deae04-8748-4233-8473-0b589e71a791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84338
2268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.843382268
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1778443821
Short name T888
Test name
Test status
Simulation time 45546242 ps
CPU time 0.69 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206692 kb
Host smart-7b0f9f9a-d5ca-4686-8925-a4d48db730a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1778443821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1778443821
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.3335701997
Short name T196
Test name
Test status
Simulation time 4296118730 ps
CPU time 4.6 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:14 PM PDT 24
Peak memory 206908 kb
Host smart-b97c790f-71ff-4a24-9a71-47874bd443af
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3335701997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.3335701997
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.258042774
Short name T2537
Test name
Test status
Simulation time 13493089646 ps
CPU time 12.61 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:22 PM PDT 24
Peak memory 206912 kb
Host smart-99f3a437-0222-4195-82bb-0dda42f9055f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=258042774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.258042774
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3449542631
Short name T739
Test name
Test status
Simulation time 23333248081 ps
CPU time 23.1 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:32 PM PDT 24
Peak memory 206848 kb
Host smart-820729de-172c-4ae2-884c-e1c6060e737b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3449542631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3449542631
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.433807376
Short name T293
Test name
Test status
Simulation time 170996006 ps
CPU time 0.88 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206648 kb
Host smart-39f88fd1-2361-4da9-b60b-2a88e75f8bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43380
7376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.433807376
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.2945583852
Short name T1172
Test name
Test status
Simulation time 147714314 ps
CPU time 0.85 seconds
Started Jul 18 05:45:46 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206652 kb
Host smart-65245207-208e-4c1c-9a35-0d67386b9a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29455
83852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.2945583852
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.3652219967
Short name T1014
Test name
Test status
Simulation time 395061396 ps
CPU time 1.37 seconds
Started Jul 18 05:45:51 PM PDT 24
Finished Jul 18 05:46:06 PM PDT 24
Peak memory 206620 kb
Host smart-1e690ed0-c5e7-4a9a-a3af-a6252e34f57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36522
19967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.3652219967
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.2379218000
Short name T2359
Test name
Test status
Simulation time 776057594 ps
CPU time 2.06 seconds
Started Jul 18 05:45:50 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206796 kb
Host smart-e92224ba-7549-492c-aaf3-4ce21efbb0aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23792
18000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.2379218000
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.2489986799
Short name T107
Test name
Test status
Simulation time 16222363097 ps
CPU time 30.36 seconds
Started Jul 18 05:45:55 PM PDT 24
Finished Jul 18 05:46:38 PM PDT 24
Peak memory 206924 kb
Host smart-838893df-637d-463d-8394-1b403db6f06e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24899
86799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.2489986799
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.3833124477
Short name T2035
Test name
Test status
Simulation time 294929286 ps
CPU time 1.04 seconds
Started Jul 18 05:45:51 PM PDT 24
Finished Jul 18 05:46:05 PM PDT 24
Peak memory 206652 kb
Host smart-e30bddda-832a-46d1-94c0-82ba7b3750cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38331
24477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.3833124477
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.253000574
Short name T2494
Test name
Test status
Simulation time 130618164 ps
CPU time 0.74 seconds
Started Jul 18 05:45:40 PM PDT 24
Finished Jul 18 05:45:56 PM PDT 24
Peak memory 206656 kb
Host smart-6217a783-c2ff-47fc-b268-7bbbf3f97f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25300
0574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.253000574
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.4199080779
Short name T947
Test name
Test status
Simulation time 101282862 ps
CPU time 0.76 seconds
Started Jul 18 05:45:53 PM PDT 24
Finished Jul 18 05:46:07 PM PDT 24
Peak memory 206644 kb
Host smart-db2e0c0b-1421-468c-9ec7-113da684e7e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41990
80779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.4199080779
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2169277356
Short name T2029
Test name
Test status
Simulation time 881242904 ps
CPU time 2.05 seconds
Started Jul 18 05:45:48 PM PDT 24
Finished Jul 18 05:46:04 PM PDT 24
Peak memory 206788 kb
Host smart-1d31789f-8e16-436d-9dff-ea160a7a62b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21692
77356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2169277356
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.588141975
Short name T1059
Test name
Test status
Simulation time 169216819 ps
CPU time 1.61 seconds
Started Jul 18 05:45:41 PM PDT 24
Finished Jul 18 05:45:58 PM PDT 24
Peak memory 206800 kb
Host smart-cf477b8d-b34d-4eda-96fe-cab695f7b40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58814
1975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.588141975
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1294128132
Short name T1865
Test name
Test status
Simulation time 224515563 ps
CPU time 0.97 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206620 kb
Host smart-8689c068-7d60-4f31-a9db-27aa8155f73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12941
28132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1294128132
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.257871379
Short name T2614
Test name
Test status
Simulation time 162660834 ps
CPU time 0.82 seconds
Started Jul 18 05:45:47 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206640 kb
Host smart-fb953e90-b330-4d39-8b62-28d581856003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25787
1379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.257871379
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1812236299
Short name T1041
Test name
Test status
Simulation time 222923475 ps
CPU time 0.87 seconds
Started Jul 18 05:45:39 PM PDT 24
Finished Jul 18 05:45:55 PM PDT 24
Peak memory 206656 kb
Host smart-bd416026-caec-497e-afa9-30d94a3182d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18122
36299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1812236299
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.3427252592
Short name T594
Test name
Test status
Simulation time 9735000265 ps
CPU time 86.16 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206872 kb
Host smart-542cde28-8306-4a54-8caa-d876a0cc7195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34272
52592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.3427252592
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.656880413
Short name T1917
Test name
Test status
Simulation time 175078109 ps
CPU time 0.84 seconds
Started Jul 18 05:46:01 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206612 kb
Host smart-0a19e2d6-1011-4f4b-b324-b83832c9d176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65688
0413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.656880413
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3035733195
Short name T364
Test name
Test status
Simulation time 23271357579 ps
CPU time 28.19 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:38 PM PDT 24
Peak memory 206772 kb
Host smart-986b2010-6f0d-4226-8253-add50c4fc110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30357
33195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3035733195
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2262697042
Short name T1833
Test name
Test status
Simulation time 3336308124 ps
CPU time 3.88 seconds
Started Jul 18 05:46:02 PM PDT 24
Finished Jul 18 05:46:16 PM PDT 24
Peak memory 206712 kb
Host smart-69015845-13da-48f3-88e0-f43cec1d05a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22626
97042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2262697042
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.3273965042
Short name T852
Test name
Test status
Simulation time 13786036688 ps
CPU time 394.51 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:52:44 PM PDT 24
Peak memory 206960 kb
Host smart-c94453e9-4b33-415d-adbf-a1204ec998e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32739
65042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.3273965042
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.1828852813
Short name T307
Test name
Test status
Simulation time 5247981312 ps
CPU time 150.95 seconds
Started Jul 18 05:46:00 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206812 kb
Host smart-44422d4e-dfce-4d11-b7a7-70b1ef4ebb9b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1828852813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.1828852813
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.3219164501
Short name T2740
Test name
Test status
Simulation time 251324102 ps
CPU time 0.93 seconds
Started Jul 18 05:46:00 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206648 kb
Host smart-aed1155a-7421-430c-bc72-cdc3a30b6e2e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3219164501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.3219164501
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.2255569289
Short name T2092
Test name
Test status
Simulation time 193941889 ps
CPU time 0.86 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206616 kb
Host smart-7c7801f8-db7d-41e6-bb9b-88b2601b6bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22555
69289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.2255569289
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2567675263
Short name T2578
Test name
Test status
Simulation time 6007268967 ps
CPU time 41.13 seconds
Started Jul 18 05:45:54 PM PDT 24
Finished Jul 18 05:46:48 PM PDT 24
Peak memory 206920 kb
Host smart-3596f7cc-916e-41c9-9fc7-51d316aec302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25676
75263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2567675263
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.3924166186
Short name T774
Test name
Test status
Simulation time 4311196781 ps
CPU time 33.47 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:46:43 PM PDT 24
Peak memory 206832 kb
Host smart-09e59501-84e9-4ce1-8241-f81d83ea7310
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3924166186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.3924166186
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3867636829
Short name T1719
Test name
Test status
Simulation time 158342047 ps
CPU time 0.81 seconds
Started Jul 18 05:46:00 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206640 kb
Host smart-8a669ae0-c371-4630-a4ca-52903a2ef93f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3867636829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3867636829
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3241222947
Short name T491
Test name
Test status
Simulation time 141495999 ps
CPU time 0.86 seconds
Started Jul 18 05:46:00 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206664 kb
Host smart-132f281e-57ef-426f-8e3d-b2d3d3541511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32412
22947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3241222947
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3111417088
Short name T1661
Test name
Test status
Simulation time 174106469 ps
CPU time 0.84 seconds
Started Jul 18 05:46:02 PM PDT 24
Finished Jul 18 05:46:14 PM PDT 24
Peak memory 206620 kb
Host smart-870fad80-45d8-4767-9444-f001ddf9ac03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114
17088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3111417088
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.550712146
Short name T2569
Test name
Test status
Simulation time 163957055 ps
CPU time 0.77 seconds
Started Jul 18 05:45:56 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206820 kb
Host smart-af9ef5fb-5991-4227-b1aa-c311e752bcf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55071
2146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.550712146
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2051116439
Short name T2533
Test name
Test status
Simulation time 173384938 ps
CPU time 0.82 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206636 kb
Host smart-97ce69e6-aa63-4725-8832-4851290a980d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20511
16439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2051116439
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.790211671
Short name T987
Test name
Test status
Simulation time 161334605 ps
CPU time 0.76 seconds
Started Jul 18 05:46:04 PM PDT 24
Finished Jul 18 05:46:15 PM PDT 24
Peak memory 206640 kb
Host smart-2adea480-b647-48f6-9679-8b7a02c469b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79021
1671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.790211671
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.2861508271
Short name T2485
Test name
Test status
Simulation time 243026170 ps
CPU time 0.98 seconds
Started Jul 18 05:46:02 PM PDT 24
Finished Jul 18 05:46:14 PM PDT 24
Peak memory 206620 kb
Host smart-cc4a68e8-9957-4cbc-9404-0f480b99873e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2861508271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.2861508271
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.2115662623
Short name T2482
Test name
Test status
Simulation time 38965651 ps
CPU time 0.66 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206616 kb
Host smart-21b9083d-2bad-420d-a9a7-b0b29d38d133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21156
62623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.2115662623
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.1850171154
Short name T2134
Test name
Test status
Simulation time 17594826735 ps
CPU time 37.52 seconds
Started Jul 18 05:45:52 PM PDT 24
Finished Jul 18 05:46:42 PM PDT 24
Peak memory 206864 kb
Host smart-fa97a38a-8db2-4d2a-82e9-0fd7a5bc5978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
71154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.1850171154
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.1840657055
Short name T1367
Test name
Test status
Simulation time 185400238 ps
CPU time 0.82 seconds
Started Jul 18 05:45:53 PM PDT 24
Finished Jul 18 05:46:06 PM PDT 24
Peak memory 206660 kb
Host smart-e1f2a1af-79d4-4e7c-8b26-4a20b25765f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18406
57055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.1840657055
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2399242579
Short name T2662
Test name
Test status
Simulation time 216727956 ps
CPU time 0.92 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206660 kb
Host smart-f64f2f44-ee59-44d0-b89e-d770d451ab79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23992
42579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2399242579
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1187354767
Short name T1810
Test name
Test status
Simulation time 200788456 ps
CPU time 0.85 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206652 kb
Host smart-5daf2cdd-2b9e-4bd0-a83d-da6d39b91b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11873
54767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1187354767
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1864967545
Short name T2270
Test name
Test status
Simulation time 216334943 ps
CPU time 0.86 seconds
Started Jul 18 05:46:02 PM PDT 24
Finished Jul 18 05:46:14 PM PDT 24
Peak memory 206600 kb
Host smart-ffcba45c-23ce-41dd-bc90-5fd9afdf9240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18649
67545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1864967545
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2053744350
Short name T1649
Test name
Test status
Simulation time 206129000 ps
CPU time 0.84 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206580 kb
Host smart-6f07991e-113e-44fc-89c4-d71b730134ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20537
44350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2053744350
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.344547558
Short name T113
Test name
Test status
Simulation time 156205195 ps
CPU time 0.76 seconds
Started Jul 18 05:45:55 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206632 kb
Host smart-3128f2b9-727f-49c6-a30c-fa8b88057f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34454
7558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.344547558
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4039135330
Short name T2437
Test name
Test status
Simulation time 157200900 ps
CPU time 0.79 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206640 kb
Host smart-3b5b7704-027c-4229-93c7-e4de37e6411f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40391
35330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4039135330
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.3278267006
Short name T402
Test name
Test status
Simulation time 245568484 ps
CPU time 0.95 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206588 kb
Host smart-14b4b070-2727-4f40-8cb4-4b660cf099f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32782
67006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.3278267006
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.3634388573
Short name T820
Test name
Test status
Simulation time 3397160084 ps
CPU time 96.01 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206864 kb
Host smart-7bf3815b-402d-422e-b567-7fd6d20d2d6c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3634388573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.3634388573
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1276867801
Short name T26
Test name
Test status
Simulation time 142335521 ps
CPU time 0.77 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206648 kb
Host smart-30664632-11ba-402c-bb85-e13d4cb1e45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12768
67801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1276867801
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.868710888
Short name T2638
Test name
Test status
Simulation time 172442083 ps
CPU time 0.83 seconds
Started Jul 18 05:46:02 PM PDT 24
Finished Jul 18 05:46:13 PM PDT 24
Peak memory 206644 kb
Host smart-3eb46937-514b-4550-abc4-0b48ac2edb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86871
0888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.868710888
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.1427725214
Short name T29
Test name
Test status
Simulation time 1243816418 ps
CPU time 2.7 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206764 kb
Host smart-43b03087-6173-4ebd-b475-afc62f8cda1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14277
25214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.1427725214
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.1985570550
Short name T1357
Test name
Test status
Simulation time 5901718854 ps
CPU time 58.04 seconds
Started Jul 18 05:45:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206916 kb
Host smart-61213822-98b4-4a03-bd80-7b83f66731e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19855
70550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.1985570550
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1108650537
Short name T619
Test name
Test status
Simulation time 45330614 ps
CPU time 0.67 seconds
Started Jul 18 05:46:21 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 206656 kb
Host smart-125328db-abfa-431c-b68f-2265eb91008b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1108650537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1108650537
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.2132743156
Short name T1937
Test name
Test status
Simulation time 3655140845 ps
CPU time 5.34 seconds
Started Jul 18 05:45:55 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206720 kb
Host smart-5b02d871-654d-4825-af9e-9d2d1b8c0901
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2132743156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.2132743156
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.3539401348
Short name T1167
Test name
Test status
Simulation time 13425004578 ps
CPU time 12.96 seconds
Started Jul 18 05:45:56 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 206780 kb
Host smart-6157b52b-317a-4341-9b43-a2c661e89f28
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3539401348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.3539401348
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.2261412004
Short name T1929
Test name
Test status
Simulation time 23362131133 ps
CPU time 24.1 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:34 PM PDT 24
Peak memory 206920 kb
Host smart-7901729e-be60-497a-8580-6b69618183b5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2261412004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.2261412004
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.920179906
Short name T1580
Test name
Test status
Simulation time 187794551 ps
CPU time 0.85 seconds
Started Jul 18 05:45:54 PM PDT 24
Finished Jul 18 05:46:07 PM PDT 24
Peak memory 206652 kb
Host smart-87247e0a-1822-4c82-aef0-125553bf01b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92017
9906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.920179906
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.119378027
Short name T1322
Test name
Test status
Simulation time 196002758 ps
CPU time 0.84 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206632 kb
Host smart-e1fd0725-30e1-49a7-9d9d-b52cd76b018b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11937
8027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.119378027
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.232185818
Short name T2300
Test name
Test status
Simulation time 531130848 ps
CPU time 1.53 seconds
Started Jul 18 05:45:58 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206656 kb
Host smart-31207968-5005-4eb0-8060-67740154e79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23218
5818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.232185818
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.1602138182
Short name T1251
Test name
Test status
Simulation time 1431853668 ps
CPU time 3.16 seconds
Started Jul 18 05:45:55 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206788 kb
Host smart-bd6c50de-fee9-4c27-a8d5-1135bc6ba323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16021
38182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.1602138182
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.604732484
Short name T173
Test name
Test status
Simulation time 17733424988 ps
CPU time 34.69 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:45 PM PDT 24
Peak memory 206836 kb
Host smart-a033c3cf-859e-4f72-b726-e8d44e5027ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60473
2484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.604732484
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.910061424
Short name T1379
Test name
Test status
Simulation time 298613961 ps
CPU time 1.07 seconds
Started Jul 18 05:45:55 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206640 kb
Host smart-68097419-cd18-4897-9115-65ecafa41d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91006
1424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.910061424
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.2681833841
Short name T1846
Test name
Test status
Simulation time 143246615 ps
CPU time 0.77 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206652 kb
Host smart-8e8883aa-6386-4565-96ee-ab7d5fce27ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26818
33841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.2681833841
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3002270556
Short name T417
Test name
Test status
Simulation time 46558246 ps
CPU time 0.68 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206648 kb
Host smart-f8042ee9-47ee-494d-b0bd-65bec85a1001
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30022
70556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3002270556
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.3217749028
Short name T803
Test name
Test status
Simulation time 843609967 ps
CPU time 2.04 seconds
Started Jul 18 05:46:02 PM PDT 24
Finished Jul 18 05:46:14 PM PDT 24
Peak memory 206788 kb
Host smart-38c32400-58ca-499f-8d75-0d1570fc26e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32177
49028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.3217749028
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.3601737043
Short name T1725
Test name
Test status
Simulation time 212954471 ps
CPU time 1.78 seconds
Started Jul 18 05:45:59 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206732 kb
Host smart-99a02240-4e8e-4661-af50-b8b4b61cd285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36017
37043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.3601737043
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.2198673298
Short name T2720
Test name
Test status
Simulation time 173396840 ps
CPU time 0.83 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206648 kb
Host smart-39bf58de-b330-494d-b9fd-c6bf89b6dc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21986
73298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.2198673298
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.1730823537
Short name T1668
Test name
Test status
Simulation time 141028507 ps
CPU time 0.74 seconds
Started Jul 18 05:45:57 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206660 kb
Host smart-8d16392a-cdd5-4b1f-9061-9e91b013578f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17308
23537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.1730823537
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3514150712
Short name T1265
Test name
Test status
Simulation time 220102335 ps
CPU time 0.97 seconds
Started Jul 18 05:46:00 PM PDT 24
Finished Jul 18 05:46:12 PM PDT 24
Peak memory 206636 kb
Host smart-f8ea1a74-6f6f-4e83-88e8-a59654ce7a28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35141
50712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3514150712
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.4023969719
Short name T224
Test name
Test status
Simulation time 6072493830 ps
CPU time 57.28 seconds
Started Jul 18 05:46:02 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206808 kb
Host smart-23be2ffb-a577-4184-aa8e-55129e40ccd1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4023969719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.4023969719
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.1546236303
Short name T611
Test name
Test status
Simulation time 167157957 ps
CPU time 0.88 seconds
Started Jul 18 05:46:11 PM PDT 24
Finished Jul 18 05:46:17 PM PDT 24
Peak memory 206640 kb
Host smart-803fdbf6-6209-47c4-a6aa-bbc0c256aa0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15462
36303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.1546236303
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.768646648
Short name T2727
Test name
Test status
Simulation time 23324318647 ps
CPU time 24.67 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:46 PM PDT 24
Peak memory 206760 kb
Host smart-562cd201-9e77-42c9-923e-14ff6d379494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76864
6648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.768646648
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.315887097
Short name T2086
Test name
Test status
Simulation time 3312420536 ps
CPU time 4.27 seconds
Started Jul 18 05:46:13 PM PDT 24
Finished Jul 18 05:46:22 PM PDT 24
Peak memory 206720 kb
Host smart-9c565b6f-133d-4f1f-926d-49297a78381e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31588
7097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.315887097
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.4242964505
Short name T423
Test name
Test status
Simulation time 10928124065 ps
CPU time 320.04 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:51:42 PM PDT 24
Peak memory 206904 kb
Host smart-6343822a-ac60-48a6-9813-3cce59e43710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42429
64505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.4242964505
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1749439169
Short name T1652
Test name
Test status
Simulation time 5408604597 ps
CPU time 49.75 seconds
Started Jul 18 05:46:09 PM PDT 24
Finished Jul 18 05:47:05 PM PDT 24
Peak memory 206832 kb
Host smart-4cc5c089-9894-4f5a-8cc5-6ee05dd6b374
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1749439169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1749439169
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.1792751101
Short name T2139
Test name
Test status
Simulation time 242151942 ps
CPU time 0.88 seconds
Started Jul 18 05:46:12 PM PDT 24
Finished Jul 18 05:46:18 PM PDT 24
Peak memory 206628 kb
Host smart-6c867de4-0ae1-412a-8af9-7a31b31a6837
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1792751101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.1792751101
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.4034044431
Short name T1567
Test name
Test status
Simulation time 195695326 ps
CPU time 0.88 seconds
Started Jul 18 05:46:13 PM PDT 24
Finished Jul 18 05:46:18 PM PDT 24
Peak memory 206612 kb
Host smart-265294d2-d706-429e-84d6-c7787fb8b610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40340
44431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.4034044431
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.915499028
Short name T684
Test name
Test status
Simulation time 5337053057 ps
CPU time 51.49 seconds
Started Jul 18 05:46:11 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206852 kb
Host smart-6a3c40a1-4611-4726-a47b-4434cd95785e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91549
9028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.915499028
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.576185315
Short name T365
Test name
Test status
Simulation time 5124330340 ps
CPU time 39.67 seconds
Started Jul 18 05:46:12 PM PDT 24
Finished Jul 18 05:46:57 PM PDT 24
Peak memory 206892 kb
Host smart-3144e3c8-96bc-4383-8fdb-5aefb797275d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=576185315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.576185315
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.2503825466
Short name T2628
Test name
Test status
Simulation time 161758958 ps
CPU time 0.84 seconds
Started Jul 18 05:46:12 PM PDT 24
Finished Jul 18 05:46:18 PM PDT 24
Peak memory 206616 kb
Host smart-d62c399d-cfad-48d0-b7e3-1e14b451c33e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2503825466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.2503825466
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.2686291199
Short name T1440
Test name
Test status
Simulation time 145085744 ps
CPU time 0.76 seconds
Started Jul 18 05:46:13 PM PDT 24
Finished Jul 18 05:46:18 PM PDT 24
Peak memory 206648 kb
Host smart-526c4544-2e7e-4f91-a85a-3385384a5019
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26862
91199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.2686291199
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.2214198001
Short name T848
Test name
Test status
Simulation time 151948247 ps
CPU time 0.8 seconds
Started Jul 18 05:46:12 PM PDT 24
Finished Jul 18 05:46:17 PM PDT 24
Peak memory 206648 kb
Host smart-cc4d84fa-dec0-4fc6-9295-3cf7b75c80be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22141
98001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.2214198001
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.145642543
Short name T2397
Test name
Test status
Simulation time 212708273 ps
CPU time 0.9 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 206640 kb
Host smart-207a58ba-7dc5-4aca-9cc8-0b9bf32f9953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14564
2543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.145642543
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.543130617
Short name T705
Test name
Test status
Simulation time 146709069 ps
CPU time 0.78 seconds
Started Jul 18 05:46:12 PM PDT 24
Finished Jul 18 05:46:18 PM PDT 24
Peak memory 206628 kb
Host smart-0ace5ee2-f87c-4a32-84c2-005ab7007030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54313
0617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.543130617
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.958057369
Short name T2654
Test name
Test status
Simulation time 151173539 ps
CPU time 0.82 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:20 PM PDT 24
Peak memory 206628 kb
Host smart-303db461-b2a8-493f-8f89-b5803d9238de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95805
7369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.958057369
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1543764411
Short name T2020
Test name
Test status
Simulation time 200027921 ps
CPU time 0.91 seconds
Started Jul 18 05:46:14 PM PDT 24
Finished Jul 18 05:46:19 PM PDT 24
Peak memory 206648 kb
Host smart-76d35452-a7d4-41c3-b57c-cbbca4172b29
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1543764411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1543764411
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.480406018
Short name T430
Test name
Test status
Simulation time 148309010 ps
CPU time 0.79 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 206664 kb
Host smart-790068ea-3f0e-4c20-9b12-76d915fc7dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48040
6018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.480406018
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.1378716570
Short name T1195
Test name
Test status
Simulation time 30209797 ps
CPU time 0.66 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:46:23 PM PDT 24
Peak memory 206632 kb
Host smart-1ae2ccde-fe97-485c-83ea-199f79fdc2d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13787
16570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.1378716570
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.2210343958
Short name T1772
Test name
Test status
Simulation time 16691529207 ps
CPU time 37.79 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:47:02 PM PDT 24
Peak memory 206852 kb
Host smart-108d92fa-ea71-4ef0-953f-3a7063209a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22103
43958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.2210343958
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.789443364
Short name T2461
Test name
Test status
Simulation time 154889112 ps
CPU time 0.81 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:46:23 PM PDT 24
Peak memory 206624 kb
Host smart-80bc4ef0-e30f-4054-836f-c25f3b9c9ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78944
3364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.789443364
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.3978545064
Short name T1775
Test name
Test status
Simulation time 209409814 ps
CPU time 0.88 seconds
Started Jul 18 05:46:13 PM PDT 24
Finished Jul 18 05:46:18 PM PDT 24
Peak memory 206808 kb
Host smart-f6b50b19-2ab0-497a-8075-9440db2fe021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39785
45064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.3978545064
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.3103095941
Short name T891
Test name
Test status
Simulation time 157651960 ps
CPU time 0.83 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:24 PM PDT 24
Peak memory 206616 kb
Host smart-f72d367e-47d3-477d-add3-25faf6b872b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030
95941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.3103095941
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2903050686
Short name T1176
Test name
Test status
Simulation time 196262512 ps
CPU time 0.87 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206600 kb
Host smart-8f6c98bf-ec6f-4585-b0bc-1f048506f6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29030
50686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2903050686
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.2259548601
Short name T2660
Test name
Test status
Simulation time 176321440 ps
CPU time 0.8 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:20 PM PDT 24
Peak memory 206664 kb
Host smart-3316be5c-439a-4ff8-a392-d285d8c9d2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22595
48601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.2259548601
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3019573002
Short name T433
Test name
Test status
Simulation time 153429271 ps
CPU time 0.8 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206644 kb
Host smart-edbdbcbb-094b-4222-930a-42209b0cadc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30195
73002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3019573002
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1861179903
Short name T2168
Test name
Test status
Simulation time 151859948 ps
CPU time 0.84 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:24 PM PDT 24
Peak memory 206620 kb
Host smart-03fc1a37-ebd9-4fb7-98ac-80f338c7ca88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18611
79903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1861179903
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.4060652184
Short name T790
Test name
Test status
Simulation time 243196103 ps
CPU time 0.96 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206624 kb
Host smart-d50a9e70-6c0e-4bf7-8a14-29862d79886f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40606
52184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.4060652184
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.3408506374
Short name T2611
Test name
Test status
Simulation time 4664966060 ps
CPU time 46.96 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206880 kb
Host smart-a36ffea9-df73-41dd-8077-44babe63a9ef
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3408506374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.3408506374
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.2087659740
Short name T1978
Test name
Test status
Simulation time 167869483 ps
CPU time 0.84 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206668 kb
Host smart-51add974-0c74-44a7-b354-0385efc6c5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20876
59740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.2087659740
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.3762497248
Short name T1752
Test name
Test status
Simulation time 192682229 ps
CPU time 0.86 seconds
Started Jul 18 05:46:21 PM PDT 24
Finished Jul 18 05:46:29 PM PDT 24
Peak memory 206632 kb
Host smart-f1edf870-f473-4fbd-baa7-20b8b4a992db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37624
97248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.3762497248
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2155201609
Short name T1356
Test name
Test status
Simulation time 1108937845 ps
CPU time 2.31 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:26 PM PDT 24
Peak memory 206772 kb
Host smart-dc08b0b6-fcb3-41ce-ad87-1e1c9e9547a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21552
01609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2155201609
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.3518808508
Short name T1563
Test name
Test status
Simulation time 5511502273 ps
CPU time 38.05 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:47:04 PM PDT 24
Peak memory 206864 kb
Host smart-29495204-a210-4605-89bf-d5555627988c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35188
08508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.3518808508
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.864872702
Short name T1483
Test name
Test status
Simulation time 102036346 ps
CPU time 0.7 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:39 PM PDT 24
Peak memory 206708 kb
Host smart-c292cd41-e198-4ba3-91ba-42471f048f90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=864872702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.864872702
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.1872658647
Short name T2663
Test name
Test status
Simulation time 3382502661 ps
CPU time 3.95 seconds
Started Jul 18 05:46:23 PM PDT 24
Finished Jul 18 05:46:33 PM PDT 24
Peak memory 206712 kb
Host smart-786b1065-3435-45a2-b198-8b628c5e28cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1872658647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.1872658647
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.333957600
Short name T2177
Test name
Test status
Simulation time 13390559234 ps
CPU time 12.8 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:33 PM PDT 24
Peak memory 206780 kb
Host smart-4f33a488-d62e-4a43-a395-1b7e10059250
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=333957600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.333957600
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.1630841074
Short name T1667
Test name
Test status
Simulation time 23380312962 ps
CPU time 28.68 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:54 PM PDT 24
Peak memory 206688 kb
Host smart-e1cc34a9-fcbb-4876-ba04-e8e427e546f7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1630841074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.1630841074
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1438339620
Short name T663
Test name
Test status
Simulation time 179507485 ps
CPU time 0.85 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206584 kb
Host smart-47cb8d32-7575-4953-bb9a-f40e48c76b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14383
39620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1438339620
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.616757680
Short name T2042
Test name
Test status
Simulation time 152630690 ps
CPU time 0.79 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206652 kb
Host smart-df69a97d-c35a-484c-bca5-269b5bff4c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61675
7680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.616757680
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.3431852038
Short name T560
Test name
Test status
Simulation time 491052779 ps
CPU time 1.44 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 206636 kb
Host smart-0ad1f65b-e738-46d7-a080-ec33dbe74481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34318
52038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.3431852038
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2373333521
Short name T2477
Test name
Test status
Simulation time 640499596 ps
CPU time 1.56 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206620 kb
Host smart-b96398ea-192a-4e51-abbf-592fff16a46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23733
33521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2373333521
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.75710190
Short name T1484
Test name
Test status
Simulation time 6600305502 ps
CPU time 11.87 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:38 PM PDT 24
Peak memory 206772 kb
Host smart-85e2deb5-01d2-4449-befe-7e37584671d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75710
190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.75710190
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_device_timeout.1612810203
Short name T827
Test name
Test status
Simulation time 168219676 ps
CPU time 0.81 seconds
Started Jul 18 05:46:23 PM PDT 24
Finished Jul 18 05:46:30 PM PDT 24
Peak memory 206632 kb
Host smart-3071aaff-2f41-4244-bccc-0d3ee5e9f406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128
10203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_timeout.1612810203
Directory /workspace/15.usbdev_device_timeout/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.2615476293
Short name T747
Test name
Test status
Simulation time 419194209 ps
CPU time 1.41 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:22 PM PDT 24
Peak memory 206636 kb
Host smart-dc9ae5b0-0510-4cd8-819f-070fd1e30126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26154
76293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.2615476293
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.267728380
Short name T1313
Test name
Test status
Simulation time 156642025 ps
CPU time 0.8 seconds
Started Jul 18 05:46:23 PM PDT 24
Finished Jul 18 05:46:30 PM PDT 24
Peak memory 206652 kb
Host smart-302471d6-77f7-4544-bb0c-773bca6c151f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26772
8380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.267728380
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.3908001041
Short name T1030
Test name
Test status
Simulation time 41331744 ps
CPU time 0.7 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 206644 kb
Host smart-ef4b5d18-d070-4e43-9dd6-98bb7b43a42b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39080
01041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.3908001041
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.429825232
Short name T1504
Test name
Test status
Simulation time 907827447 ps
CPU time 2.09 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:46:29 PM PDT 24
Peak memory 206740 kb
Host smart-42cb2b7e-3cc4-48df-a5fc-4d4cb0adc66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42982
5232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.429825232
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.3913941658
Short name T1467
Test name
Test status
Simulation time 299387071 ps
CPU time 2.1 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:24 PM PDT 24
Peak memory 206800 kb
Host smart-310b2351-ca5f-4423-b8ca-b532f722b109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39139
41658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.3913941658
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2462949081
Short name T555
Test name
Test status
Simulation time 219051347 ps
CPU time 0.89 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:46:24 PM PDT 24
Peak memory 206628 kb
Host smart-39995f9e-cc0e-4339-b5b1-3105f7c9e0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24629
49081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2462949081
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2723880060
Short name T623
Test name
Test status
Simulation time 190463766 ps
CPU time 0.79 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:46:23 PM PDT 24
Peak memory 206640 kb
Host smart-e94220f1-56d4-4770-b8dd-e0f56262504e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27238
80060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2723880060
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.1307260752
Short name T2655
Test name
Test status
Simulation time 243051800 ps
CPU time 0.88 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:23 PM PDT 24
Peak memory 206640 kb
Host smart-dec34892-7c29-485a-a44b-b5504091bd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13072
60752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.1307260752
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.2566074781
Short name T2458
Test name
Test status
Simulation time 8798922990 ps
CPU time 250.19 seconds
Started Jul 18 05:46:13 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 207036 kb
Host smart-ad80bdf8-032b-43a4-88af-fc906ba461fe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2566074781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2566074781
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.2683686166
Short name T1848
Test name
Test status
Simulation time 8881402549 ps
CPU time 34.54 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206908 kb
Host smart-c516d2ed-4fa9-4d44-88e2-404189157ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836
86166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.2683686166
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.1816091099
Short name T784
Test name
Test status
Simulation time 203777775 ps
CPU time 0.94 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:21 PM PDT 24
Peak memory 206668 kb
Host smart-58cef780-d310-4d6f-9add-69f589d993e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18160
91099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.1816091099
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.2200354712
Short name T416
Test name
Test status
Simulation time 23345114840 ps
CPU time 23.27 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:43 PM PDT 24
Peak memory 206776 kb
Host smart-e59565a3-6393-4e43-9615-275ec8cc75ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22003
54712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.2200354712
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.3378108704
Short name T1403
Test name
Test status
Simulation time 3320818851 ps
CPU time 3.72 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:23 PM PDT 24
Peak memory 206736 kb
Host smart-cb7ba5f5-1baf-4568-8cff-d46e7b06655c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33781
08704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.3378108704
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.675651009
Short name T1654
Test name
Test status
Simulation time 7196848896 ps
CPU time 66.73 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206948 kb
Host smart-e76316ec-f197-4533-9cf5-d44af00496fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67565
1009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.675651009
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2518220358
Short name T1759
Test name
Test status
Simulation time 6624582261 ps
CPU time 189.37 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:49:32 PM PDT 24
Peak memory 206844 kb
Host smart-e99cc9aa-0932-48b9-a5ba-f8b5f3735ed8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2518220358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2518220358
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.2024596402
Short name T2414
Test name
Test status
Simulation time 264271440 ps
CPU time 0.98 seconds
Started Jul 18 05:46:15 PM PDT 24
Finished Jul 18 05:46:22 PM PDT 24
Peak memory 206652 kb
Host smart-625690c0-fc1d-4d62-a73b-aedefdfd6e19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2024596402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.2024596402
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.1060914367
Short name T1436
Test name
Test status
Simulation time 202777317 ps
CPU time 0.87 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206644 kb
Host smart-b9fd607c-82de-4bb5-b39e-da80174be68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10609
14367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.1060914367
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.1051587238
Short name T2354
Test name
Test status
Simulation time 4302950055 ps
CPU time 118.6 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206876 kb
Host smart-d071f822-76bc-4685-bed1-47ee18be3967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10515
87238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.1051587238
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.501185444
Short name T1774
Test name
Test status
Simulation time 2839753478 ps
CPU time 76.31 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:47:39 PM PDT 24
Peak memory 206840 kb
Host smart-d89aa376-0c27-4166-9a6c-caad17ddf219
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=501185444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.501185444
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.2084245514
Short name T609
Test name
Test status
Simulation time 158131953 ps
CPU time 0.78 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:22 PM PDT 24
Peak memory 206656 kb
Host smart-8e2188cd-acc8-4685-8580-a57526ed15ac
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2084245514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.2084245514
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.1542660801
Short name T1417
Test name
Test status
Simulation time 158332058 ps
CPU time 0.8 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:23 PM PDT 24
Peak memory 206624 kb
Host smart-a4b1beae-093c-4cf4-a31b-dbaa2a5bef6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15426
60801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.1542660801
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1541599950
Short name T2167
Test name
Test status
Simulation time 221743383 ps
CPU time 0.89 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206672 kb
Host smart-5cf2dcea-2911-4e9c-883a-7c41dce4129b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15415
99950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1541599950
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.3378670989
Short name T694
Test name
Test status
Simulation time 158527757 ps
CPU time 0.84 seconds
Started Jul 18 05:46:17 PM PDT 24
Finished Jul 18 05:46:24 PM PDT 24
Peak memory 206628 kb
Host smart-2d608864-782b-455a-9ab1-7c3b757cc5d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33786
70989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.3378670989
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1194523713
Short name T1482
Test name
Test status
Simulation time 177982953 ps
CPU time 0.84 seconds
Started Jul 18 05:46:18 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206612 kb
Host smart-a77fa101-647c-4870-8271-aedfb47b4156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11945
23713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1194523713
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3842968490
Short name T771
Test name
Test status
Simulation time 211143707 ps
CPU time 0.88 seconds
Started Jul 18 05:46:21 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 206612 kb
Host smart-e18e0061-b6f0-49eb-bf2d-374f5b8baebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
68490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3842968490
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.3659132604
Short name T1438
Test name
Test status
Simulation time 152046205 ps
CPU time 0.78 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206652 kb
Host smart-48e7796d-2e76-4908-9fe9-7d8b05bd1d80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36591
32604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.3659132604
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.659708516
Short name T2553
Test name
Test status
Simulation time 203215656 ps
CPU time 0.9 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206624 kb
Host smart-470c7acd-67cc-48ae-82f8-f3aa6e5751e2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=659708516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.659708516
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.284017581
Short name T1613
Test name
Test status
Simulation time 136744636 ps
CPU time 0.77 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206652 kb
Host smart-1f114d96-47a1-4c15-966e-a9210ac364bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28401
7581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.284017581
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.232870883
Short name T34
Test name
Test status
Simulation time 46985228 ps
CPU time 0.67 seconds
Started Jul 18 05:46:24 PM PDT 24
Finished Jul 18 05:46:30 PM PDT 24
Peak memory 206628 kb
Host smart-e63a7376-f1c2-440c-9819-ae395cb4d5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23287
0883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.232870883
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.705903266
Short name T1442
Test name
Test status
Simulation time 14103595053 ps
CPU time 30.46 seconds
Started Jul 18 05:46:21 PM PDT 24
Finished Jul 18 05:46:58 PM PDT 24
Peak memory 206864 kb
Host smart-5d1bc553-542d-4be0-80cb-21e59a1eb78f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70590
3266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.705903266
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3612957281
Short name T779
Test name
Test status
Simulation time 164968942 ps
CPU time 0.88 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206640 kb
Host smart-83c40ccc-5ee3-4ce7-8f99-99443ec85826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36129
57281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3612957281
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.33318401
Short name T1918
Test name
Test status
Simulation time 237264039 ps
CPU time 0.96 seconds
Started Jul 18 05:46:21 PM PDT 24
Finished Jul 18 05:46:29 PM PDT 24
Peak memory 206636 kb
Host smart-ae07bd08-957b-489f-ad6c-4b88eb3796ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.33318401
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.1510691665
Short name T2643
Test name
Test status
Simulation time 207844237 ps
CPU time 0.82 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206648 kb
Host smart-4c933eae-d95d-49a3-a6bc-1098b9464a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15106
91665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.1510691665
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2148891039
Short name T2312
Test name
Test status
Simulation time 165239753 ps
CPU time 0.83 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 206632 kb
Host smart-383c66f0-e5c6-4bd6-b8e2-a3bfa106da6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21488
91039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2148891039
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3912752165
Short name T1240
Test name
Test status
Simulation time 149613853 ps
CPU time 0.78 seconds
Started Jul 18 05:46:22 PM PDT 24
Finished Jul 18 05:46:29 PM PDT 24
Peak memory 206620 kb
Host smart-2e1ea747-d16d-43c9-8542-2530c97cbfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39127
52165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3912752165
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1481806177
Short name T2074
Test name
Test status
Simulation time 148192732 ps
CPU time 0.82 seconds
Started Jul 18 05:46:21 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 206632 kb
Host smart-2575ea9a-a8bc-4f46-bd57-e50cc8cfa2b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14818
06177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1481806177
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2115157781
Short name T1161
Test name
Test status
Simulation time 170236153 ps
CPU time 0.82 seconds
Started Jul 18 05:46:16 PM PDT 24
Finished Jul 18 05:46:22 PM PDT 24
Peak memory 206668 kb
Host smart-6d444113-86af-4ec6-b1fc-e107149f3c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21151
57781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2115157781
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.2269041010
Short name T908
Test name
Test status
Simulation time 264715765 ps
CPU time 1.06 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:46:28 PM PDT 24
Peak memory 206640 kb
Host smart-7b7f9693-6bc2-49ef-a4c7-9ccb15e0f743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22690
41010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.2269041010
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.770302106
Short name T1187
Test name
Test status
Simulation time 3660441456 ps
CPU time 27.89 seconds
Started Jul 18 05:46:20 PM PDT 24
Finished Jul 18 05:46:55 PM PDT 24
Peak memory 206836 kb
Host smart-92ca6307-03cd-4220-ad14-b45016792f96
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=770302106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.770302106
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.1560996474
Short name T752
Test name
Test status
Simulation time 142031145 ps
CPU time 0.78 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:39 PM PDT 24
Peak memory 206632 kb
Host smart-54a519d6-184d-4795-9891-2e5e228c2ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15609
96474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.1560996474
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.3798106587
Short name T2164
Test name
Test status
Simulation time 156270749 ps
CPU time 0.82 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:45 PM PDT 24
Peak memory 206648 kb
Host smart-07e6faac-3a30-46dd-b9c7-b9735c2aeea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37981
06587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.3798106587
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.1705512595
Short name T1061
Test name
Test status
Simulation time 895413345 ps
CPU time 1.96 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:42 PM PDT 24
Peak memory 206748 kb
Host smart-0628e4c8-e3b3-4bd4-9dd3-c2bebf08a058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17055
12595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.1705512595
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3481936801
Short name T2377
Test name
Test status
Simulation time 3647509158 ps
CPU time 33.96 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206880 kb
Host smart-09842fa0-4528-47fb-ad1b-279491ec0142
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34819
36801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3481936801
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_timeout_missing_host_handshake.3908138556
Short name T1089
Test name
Test status
Simulation time 160470562 ps
CPU time 0.9 seconds
Started Jul 18 05:46:19 PM PDT 24
Finished Jul 18 05:46:26 PM PDT 24
Peak memory 206804 kb
Host smart-016dd2d6-6d13-4ee4-8560-3f09c20e8624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39081
38556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_timeout_missing_host_handshake.3908138556
Directory /workspace/15.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3571221783
Short name T724
Test name
Test status
Simulation time 36157437 ps
CPU time 0.66 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:47 PM PDT 24
Peak memory 206712 kb
Host smart-d34798b2-eeb3-4d9a-b24e-74f78afa7cdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3571221783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3571221783
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2694201632
Short name T1768
Test name
Test status
Simulation time 4260285269 ps
CPU time 5.17 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206712 kb
Host smart-d1608abf-68ea-4640-a3d0-2f33e5cf00e0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2694201632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2694201632
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.268895125
Short name T12
Test name
Test status
Simulation time 13303779696 ps
CPU time 13.78 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:47:00 PM PDT 24
Peak memory 206916 kb
Host smart-f13c5398-bef7-4cf0-b298-6bf4625a2235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=268895125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.268895125
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.2557927024
Short name T337
Test name
Test status
Simulation time 23405480269 ps
CPU time 22.91 seconds
Started Jul 18 05:46:34 PM PDT 24
Finished Jul 18 05:46:58 PM PDT 24
Peak memory 206848 kb
Host smart-047d9ef8-c25c-482f-813d-15e8c705b485
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2557927024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.2557927024
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1068109288
Short name T1872
Test name
Test status
Simulation time 148304880 ps
CPU time 0.82 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:41 PM PDT 24
Peak memory 206656 kb
Host smart-3c4eac72-5753-4f4d-8124-5e2bcb000265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10681
09288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1068109288
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1442619853
Short name T1665
Test name
Test status
Simulation time 148047036 ps
CPU time 0.82 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:41 PM PDT 24
Peak memory 206652 kb
Host smart-53553a0e-61df-4fc0-a105-e78c94678f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14426
19853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1442619853
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.1011967665
Short name T525
Test name
Test status
Simulation time 214269076 ps
CPU time 0.99 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:45 PM PDT 24
Peak memory 206620 kb
Host smart-ad3ab7b7-d4c5-4578-983a-2b4b3fb34ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
67665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.1011967665
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1302648289
Short name T109
Test name
Test status
Simulation time 1174455915 ps
CPU time 2.61 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:46 PM PDT 24
Peak memory 206792 kb
Host smart-048b0a59-c165-46c4-851e-0b6a01858d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13026
48289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1302648289
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.3481796718
Short name T97
Test name
Test status
Simulation time 11628159679 ps
CPU time 22.03 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:47:07 PM PDT 24
Peak memory 206852 kb
Host smart-77c02288-791b-4184-bf4c-df2ddd50fb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34817
96718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.3481796718
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.2632741377
Short name T2084
Test name
Test status
Simulation time 344233906 ps
CPU time 1.25 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:40 PM PDT 24
Peak memory 206628 kb
Host smart-7600fe16-ce88-4bf8-baa9-af0dd7b376bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26327
41377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.2632741377
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.4229666913
Short name T2335
Test name
Test status
Simulation time 164244351 ps
CPU time 0.81 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:45 PM PDT 24
Peak memory 206656 kb
Host smart-05078d8c-d5ee-4846-b6c8-9d001b836903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42296
66913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.4229666913
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3678795520
Short name T305
Test name
Test status
Simulation time 37397602 ps
CPU time 0.68 seconds
Started Jul 18 05:46:40 PM PDT 24
Finished Jul 18 05:46:50 PM PDT 24
Peak memory 206612 kb
Host smart-9b7ebb3e-5dae-456f-a5a3-9e29961e9094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36787
95520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3678795520
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1033044929
Short name T562
Test name
Test status
Simulation time 933263191 ps
CPU time 2.08 seconds
Started Jul 18 05:46:35 PM PDT 24
Finished Jul 18 05:46:40 PM PDT 24
Peak memory 206740 kb
Host smart-a17e7693-599d-4bc9-b0f1-90503ab9700a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330
44929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1033044929
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.4238489773
Short name T1213
Test name
Test status
Simulation time 248186432 ps
CPU time 1.79 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:46:50 PM PDT 24
Peak memory 206796 kb
Host smart-f23c77c3-2417-497b-9f24-6d818af36a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42384
89773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.4238489773
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1585219512
Short name T2431
Test name
Test status
Simulation time 184958154 ps
CPU time 0.87 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:45 PM PDT 24
Peak memory 206644 kb
Host smart-cac40e2f-2ae7-4978-83de-ffef635dbc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15852
19512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1585219512
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1638614695
Short name T2695
Test name
Test status
Simulation time 145882642 ps
CPU time 0.78 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:45 PM PDT 24
Peak memory 206612 kb
Host smart-e57e0caa-57c5-4b02-a183-53ea56b97bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16386
14695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1638614695
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.1159679714
Short name T309
Test name
Test status
Simulation time 231046341 ps
CPU time 0.93 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:47 PM PDT 24
Peak memory 206640 kb
Host smart-1d4eebaf-7abe-4f0e-ab9a-6252e93d0ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11596
79714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.1159679714
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.1318517379
Short name T2361
Test name
Test status
Simulation time 5841300443 ps
CPU time 164.37 seconds
Started Jul 18 05:46:35 PM PDT 24
Finished Jul 18 05:49:21 PM PDT 24
Peak memory 206864 kb
Host smart-546806db-3cba-4353-b82e-2ae0c046669f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1318517379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1318517379
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.2086635253
Short name T1537
Test name
Test status
Simulation time 7592790101 ps
CPU time 61.1 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:47:42 PM PDT 24
Peak memory 206904 kb
Host smart-1984a335-e3c5-48fd-b3b5-4cdd619c8a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20866
35253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.2086635253
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.211917156
Short name T782
Test name
Test status
Simulation time 207825630 ps
CPU time 0.85 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:44 PM PDT 24
Peak memory 206636 kb
Host smart-33bc76af-ad32-4290-badb-bd262de01895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
7156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.211917156
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.4132557914
Short name T359
Test name
Test status
Simulation time 23360166500 ps
CPU time 24.22 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206744 kb
Host smart-fe7efc59-a640-472b-9757-3e6d52ff6c7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41325
57914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.4132557914
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.1037198851
Short name T2754
Test name
Test status
Simulation time 3360174869 ps
CPU time 4.69 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:43 PM PDT 24
Peak memory 206724 kb
Host smart-0b5b51c0-d7b1-48dc-93d8-cc1d7dfa0e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10371
98851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.1037198851
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.2949228269
Short name T412
Test name
Test status
Simulation time 10611637734 ps
CPU time 304.1 seconds
Started Jul 18 05:46:42 PM PDT 24
Finished Jul 18 05:51:56 PM PDT 24
Peak memory 206928 kb
Host smart-6dd0574c-9c7b-42c5-9ce9-61d4e228faf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29492
28269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.2949228269
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.1698584523
Short name T1031
Test name
Test status
Simulation time 3475857582 ps
CPU time 97.88 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:48:24 PM PDT 24
Peak memory 206812 kb
Host smart-52942bdd-98d0-43b3-a2cc-2a7b78cf7ceb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1698584523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.1698584523
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.532401515
Short name T2121
Test name
Test status
Simulation time 237102039 ps
CPU time 0.89 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206636 kb
Host smart-d5ff2289-8103-45ac-97f2-86c3059341b6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=532401515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.532401515
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.72824023
Short name T1944
Test name
Test status
Simulation time 197888209 ps
CPU time 0.9 seconds
Started Jul 18 05:46:40 PM PDT 24
Finished Jul 18 05:46:50 PM PDT 24
Peak memory 206600 kb
Host smart-19211ea9-0ecf-412d-bf9f-563e491c8611
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72824
023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.72824023
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.1862980588
Short name T1707
Test name
Test status
Simulation time 4962987757 ps
CPU time 46.91 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:47:32 PM PDT 24
Peak memory 206892 kb
Host smart-316134c2-a159-4630-a5dc-9b696e8c7a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18629
80588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.1862980588
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.1543213774
Short name T2542
Test name
Test status
Simulation time 3324491316 ps
CPU time 33.45 seconds
Started Jul 18 05:46:40 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206816 kb
Host smart-038de217-02f0-4f7b-9820-935f0c2201ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1543213774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.1543213774
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.3933616247
Short name T356
Test name
Test status
Simulation time 152773891 ps
CPU time 0.79 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:46:48 PM PDT 24
Peak memory 206628 kb
Host smart-182d3d93-30e1-4872-bd51-a332249cf4fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3933616247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.3933616247
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.2114548033
Short name T2701
Test name
Test status
Simulation time 151483591 ps
CPU time 0.79 seconds
Started Jul 18 05:46:40 PM PDT 24
Finished Jul 18 05:46:50 PM PDT 24
Peak memory 206804 kb
Host smart-51f396cd-7fe3-47fd-b44a-a7d257d033aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21145
48033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.2114548033
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.608537932
Short name T1152
Test name
Test status
Simulation time 209853888 ps
CPU time 0.96 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:47 PM PDT 24
Peak memory 206640 kb
Host smart-a419df10-b4dc-4871-927a-96e3b8662e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60853
7932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.608537932
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.2168743327
Short name T605
Test name
Test status
Simulation time 206831278 ps
CPU time 0.85 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206648 kb
Host smart-c36ffb99-c090-4e94-ae2a-ef9b0be104b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21687
43327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.2168743327
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2753922507
Short name T574
Test name
Test status
Simulation time 168839460 ps
CPU time 0.85 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206608 kb
Host smart-7ec5dacb-3817-459d-9c76-4bfef1342f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27539
22507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2753922507
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1215101084
Short name T2705
Test name
Test status
Simulation time 223009893 ps
CPU time 0.83 seconds
Started Jul 18 05:46:42 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206648 kb
Host smart-fd247c03-e2ab-407b-8a6c-8911a813f968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12151
01084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1215101084
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.1040829041
Short name T2308
Test name
Test status
Simulation time 162995811 ps
CPU time 0.83 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206484 kb
Host smart-dd2050b6-3100-429d-8375-4d0155f19e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10408
29041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.1040829041
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.4171673454
Short name T1264
Test name
Test status
Simulation time 227800927 ps
CPU time 0.94 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:44 PM PDT 24
Peak memory 206656 kb
Host smart-0c2fe144-07ab-44cf-8cb2-2217e5d832fc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4171673454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.4171673454
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.1598270060
Short name T93
Test name
Test status
Simulation time 168711638 ps
CPU time 0.88 seconds
Started Jul 18 05:46:42 PM PDT 24
Finished Jul 18 05:46:52 PM PDT 24
Peak memory 206624 kb
Host smart-e99c3127-45c7-4563-9315-5ffb71a840a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15982
70060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.1598270060
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.4093535326
Short name T2421
Test name
Test status
Simulation time 41552565 ps
CPU time 0.71 seconds
Started Jul 18 05:46:45 PM PDT 24
Finished Jul 18 05:46:53 PM PDT 24
Peak memory 206600 kb
Host smart-7df445c9-c5a1-471f-9ed6-40d078385671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40935
35326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.4093535326
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.1810145600
Short name T1923
Test name
Test status
Simulation time 6580929330 ps
CPU time 14.93 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:47:05 PM PDT 24
Peak memory 206872 kb
Host smart-37f3eaed-278d-4ecf-8c1e-e23787d5d334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18101
45600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.1810145600
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.3095529399
Short name T453
Test name
Test status
Simulation time 192901318 ps
CPU time 0.87 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:46:49 PM PDT 24
Peak memory 206656 kb
Host smart-85e97408-797b-45c7-9a33-5e8bc36ded79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30955
29399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.3095529399
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.804002603
Short name T323
Test name
Test status
Simulation time 304978926 ps
CPU time 1.02 seconds
Started Jul 18 05:46:42 PM PDT 24
Finished Jul 18 05:46:52 PM PDT 24
Peak memory 206624 kb
Host smart-9372539c-5edd-4e88-89a2-82d8ef0ee5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80400
2603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.804002603
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.4162848426
Short name T39
Test name
Test status
Simulation time 162371603 ps
CPU time 0.82 seconds
Started Jul 18 05:46:42 PM PDT 24
Finished Jul 18 05:46:52 PM PDT 24
Peak memory 206624 kb
Host smart-e23f4484-26d1-4a25-a8df-077b12484b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41628
48426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.4162848426
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1260889082
Short name T1328
Test name
Test status
Simulation time 243867769 ps
CPU time 0.92 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:46 PM PDT 24
Peak memory 206636 kb
Host smart-c2757b36-ffe0-4639-9a13-c27d57521c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12608
89082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1260889082
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.1863478799
Short name T512
Test name
Test status
Simulation time 193849915 ps
CPU time 0.87 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206624 kb
Host smart-a4488830-b384-4914-b009-470b7faf0ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18634
78799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.1863478799
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3424210962
Short name T1225
Test name
Test status
Simulation time 159906244 ps
CPU time 0.81 seconds
Started Jul 18 05:46:40 PM PDT 24
Finished Jul 18 05:46:50 PM PDT 24
Peak memory 206640 kb
Host smart-fc20dbe5-4965-4af9-af2d-8624a4a69a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34242
10962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3424210962
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.158998972
Short name T1360
Test name
Test status
Simulation time 151360373 ps
CPU time 0.8 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:47 PM PDT 24
Peak memory 206624 kb
Host smart-9e1e5b76-e5fe-4d52-b37c-550a8f1c0baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15899
8972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.158998972
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1631531769
Short name T566
Test name
Test status
Simulation time 262218498 ps
CPU time 1.02 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:39 PM PDT 24
Peak memory 206660 kb
Host smart-9af884e4-3ce1-4333-be6c-2c0ee6da7681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16315
31769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1631531769
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3678675086
Short name T347
Test name
Test status
Simulation time 197663663 ps
CPU time 0.79 seconds
Started Jul 18 05:46:35 PM PDT 24
Finished Jul 18 05:46:37 PM PDT 24
Peak memory 206640 kb
Host smart-2560e4db-2c3a-442b-bd96-a246f3ba9650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36786
75086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3678675086
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2004159472
Short name T1680
Test name
Test status
Simulation time 168118525 ps
CPU time 0.8 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:39 PM PDT 24
Peak memory 206636 kb
Host smart-90f15dba-9499-432c-840d-19e7d04a4904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20041
59472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2004159472
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3875852592
Short name T2538
Test name
Test status
Simulation time 1015823154 ps
CPU time 2.39 seconds
Started Jul 18 05:46:35 PM PDT 24
Finished Jul 18 05:46:40 PM PDT 24
Peak memory 206784 kb
Host smart-2648867f-b75c-49b4-be55-9886fe512460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38758
52592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3875852592
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2256192166
Short name T780
Test name
Test status
Simulation time 4274949318 ps
CPU time 120.22 seconds
Started Jul 18 05:46:40 PM PDT 24
Finished Jul 18 05:48:49 PM PDT 24
Peak memory 206824 kb
Host smart-b0375802-d8e8-40c8-ac4e-bf53c8c14bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22561
92166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2256192166
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.2114885436
Short name T907
Test name
Test status
Simulation time 37101356 ps
CPU time 0.68 seconds
Started Jul 18 05:46:55 PM PDT 24
Finished Jul 18 05:47:04 PM PDT 24
Peak memory 206608 kb
Host smart-bcd232ce-6d6f-4e90-90a4-50adf7ab3cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2114885436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.2114885436
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1885245194
Short name T2468
Test name
Test status
Simulation time 3488336122 ps
CPU time 4.45 seconds
Started Jul 18 05:46:34 PM PDT 24
Finished Jul 18 05:46:40 PM PDT 24
Peak memory 206716 kb
Host smart-ed434ad4-8d87-4a30-99c4-d01799c2031e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1885245194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1885245194
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.1091436899
Short name T719
Test name
Test status
Simulation time 13349232076 ps
CPU time 13.18 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:47:00 PM PDT 24
Peak memory 206900 kb
Host smart-58f4f4f0-2ff6-4704-a130-0d38503176c9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1091436899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.1091436899
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.1497876519
Short name T2624
Test name
Test status
Simulation time 23320042374 ps
CPU time 24.51 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:47:09 PM PDT 24
Peak memory 206768 kb
Host smart-b96f6c92-691d-4326-9f7d-dc220d74ee73
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1497876519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.1497876519
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.1256240299
Short name T2215
Test name
Test status
Simulation time 147942050 ps
CPU time 0.78 seconds
Started Jul 18 05:46:35 PM PDT 24
Finished Jul 18 05:46:39 PM PDT 24
Peak memory 206616 kb
Host smart-c98e14db-2c36-4396-bc5f-2b893fff2dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
40299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.1256240299
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.3485940082
Short name T59
Test name
Test status
Simulation time 190968628 ps
CPU time 0.89 seconds
Started Jul 18 05:46:38 PM PDT 24
Finished Jul 18 05:46:47 PM PDT 24
Peak memory 206648 kb
Host smart-76a1e353-165a-41a7-967f-26ccc47935ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34859
40082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.3485940082
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1084714714
Short name T1809
Test name
Test status
Simulation time 232166461 ps
CPU time 0.96 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:43 PM PDT 24
Peak memory 206628 kb
Host smart-90b3737b-2f93-4c7a-8771-2f556ef7d105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10847
14714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1084714714
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.2440745755
Short name T711
Test name
Test status
Simulation time 1274144813 ps
CPU time 2.76 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:44 PM PDT 24
Peak memory 206420 kb
Host smart-6b8bb5bf-ef22-4b26-aa8f-9a67985b7a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24407
45755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.2440745755
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1262135531
Short name T169
Test name
Test status
Simulation time 15394425612 ps
CPU time 28.09 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206880 kb
Host smart-b2b9b0bf-1b68-4ff6-b269-73708bebe42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
35531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1262135531
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.194677783
Short name T2123
Test name
Test status
Simulation time 401003294 ps
CPU time 1.22 seconds
Started Jul 18 05:46:40 PM PDT 24
Finished Jul 18 05:46:49 PM PDT 24
Peak memory 206656 kb
Host smart-52a54e19-5f86-46a2-a130-eab2f3068b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19467
7783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.194677783
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1284407309
Short name T2710
Test name
Test status
Simulation time 183018662 ps
CPU time 0.8 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:41 PM PDT 24
Peak memory 206648 kb
Host smart-4782bf1d-34ff-4ead-8aab-b9315c92ffcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844
07309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1284407309
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.88257266
Short name T2005
Test name
Test status
Simulation time 39098814 ps
CPU time 0.67 seconds
Started Jul 18 05:46:36 PM PDT 24
Finished Jul 18 05:46:40 PM PDT 24
Peak memory 206608 kb
Host smart-412d4f99-a79c-4c15-b34d-9af7125cf1cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88257
266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.88257266
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2818601822
Short name T2262
Test name
Test status
Simulation time 863553521 ps
CPU time 2.02 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:46 PM PDT 24
Peak memory 206760 kb
Host smart-6ed98368-128b-4dc8-ab17-5f07e35709dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
01822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2818601822
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.703786526
Short name T2037
Test name
Test status
Simulation time 287810564 ps
CPU time 1.41 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:46:45 PM PDT 24
Peak memory 206700 kb
Host smart-076aecf3-4d01-4fdd-97f7-bb0599096958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70378
6526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.703786526
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1673439202
Short name T1476
Test name
Test status
Simulation time 236031257 ps
CPU time 1.01 seconds
Started Jul 18 05:46:42 PM PDT 24
Finished Jul 18 05:46:52 PM PDT 24
Peak memory 206636 kb
Host smart-ebc1c65f-f62c-43ca-9e94-562fafcaf222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
39202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1673439202
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.1937508403
Short name T1521
Test name
Test status
Simulation time 150023642 ps
CPU time 0.76 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:46:48 PM PDT 24
Peak memory 206636 kb
Host smart-07be6c67-edea-4d92-9052-9e2494810059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19375
08403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.1937508403
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.3241032303
Short name T1050
Test name
Test status
Simulation time 183598684 ps
CPU time 0.85 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206644 kb
Host smart-eacb61e5-ea3a-4e82-85e9-20e16e93434c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32410
32303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.3241032303
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3240472593
Short name T2231
Test name
Test status
Simulation time 8371710054 ps
CPU time 241.07 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206848 kb
Host smart-ac9a221a-b6e2-4b9f-be05-b0ca319e344b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3240472593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3240472593
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.947907228
Short name T2082
Test name
Test status
Simulation time 10735734910 ps
CPU time 38.79 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:47:26 PM PDT 24
Peak memory 206876 kb
Host smart-be0aeabd-563c-4036-b6e2-fa54a249545e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94790
7228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.947907228
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2160927994
Short name T504
Test name
Test status
Simulation time 231353027 ps
CPU time 0.92 seconds
Started Jul 18 05:46:52 PM PDT 24
Finished Jul 18 05:46:57 PM PDT 24
Peak memory 206648 kb
Host smart-2f8af9f3-3f70-451c-bc38-aeaf1824cb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
27994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2160927994
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.997374758
Short name T1936
Test name
Test status
Simulation time 23331107252 ps
CPU time 25.83 seconds
Started Jul 18 05:46:37 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206772 kb
Host smart-e19ec3d5-67c4-4517-84c2-629cc137627c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99737
4758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.997374758
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1225003736
Short name T2622
Test name
Test status
Simulation time 3338490761 ps
CPU time 3.77 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206688 kb
Host smart-cd34433d-3fc1-453b-bc50-6ae618d0ab07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12250
03736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1225003736
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.393155703
Short name T2385
Test name
Test status
Simulation time 11638250987 ps
CPU time 333.68 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:52:24 PM PDT 24
Peak memory 207112 kb
Host smart-7fe4c7ed-0cb8-4660-a622-626d129b7730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39315
5703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.393155703
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2242197618
Short name T722
Test name
Test status
Simulation time 4735262769 ps
CPU time 128.36 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:48:59 PM PDT 24
Peak memory 207000 kb
Host smart-044d471a-fac5-4223-a696-2b4bd5ae7ba8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2242197618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2242197618
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.2844734313
Short name T1610
Test name
Test status
Simulation time 245051915 ps
CPU time 0.92 seconds
Started Jul 18 05:46:39 PM PDT 24
Finished Jul 18 05:46:48 PM PDT 24
Peak memory 206616 kb
Host smart-03e81a6d-bf48-4bf0-a8a6-0483dea64674
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2844734313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.2844734313
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1476964640
Short name T2369
Test name
Test status
Simulation time 191079633 ps
CPU time 0.85 seconds
Started Jul 18 05:54:36 PM PDT 24
Finished Jul 18 05:54:40 PM PDT 24
Peak memory 206628 kb
Host smart-ecea597e-6490-4a2a-9927-a9b478fc01d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14769
64640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1476964640
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.1169555031
Short name T614
Test name
Test status
Simulation time 4836633343 ps
CPU time 47.11 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:47:37 PM PDT 24
Peak memory 206772 kb
Host smart-b3549a05-88e8-460a-965b-0c0bda8beb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11695
55031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.1169555031
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2980442602
Short name T1662
Test name
Test status
Simulation time 3990545522 ps
CPU time 28.25 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:47:18 PM PDT 24
Peak memory 206904 kb
Host smart-e9389d96-0c61-473b-8efc-803fc657dffe
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2980442602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2980442602
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.2984443501
Short name T967
Test name
Test status
Simulation time 216881369 ps
CPU time 0.85 seconds
Started Jul 18 05:46:41 PM PDT 24
Finished Jul 18 05:46:51 PM PDT 24
Peak memory 206648 kb
Host smart-416664f8-2600-4324-b910-8cd8d264fe5d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2984443501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.2984443501
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.2644124064
Short name T1534
Test name
Test status
Simulation time 149005054 ps
CPU time 0.76 seconds
Started Jul 18 05:46:52 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206608 kb
Host smart-c2fc2859-f244-44f9-84b1-a1b82a942659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26441
24064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.2644124064
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1673197423
Short name T139
Test name
Test status
Simulation time 263658050 ps
CPU time 0.93 seconds
Started Jul 18 05:46:54 PM PDT 24
Finished Jul 18 05:47:02 PM PDT 24
Peak memory 206612 kb
Host smart-57cd5f90-cd14-4f7f-a283-eb75b84fd85e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16731
97423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1673197423
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.778566807
Short name T1051
Test name
Test status
Simulation time 228791721 ps
CPU time 0.86 seconds
Started Jul 18 05:46:53 PM PDT 24
Finished Jul 18 05:46:58 PM PDT 24
Peak memory 206636 kb
Host smart-cb9b9523-7fc6-47a4-a692-04dc0d3a3ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77856
6807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.778566807
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2562302842
Short name T1925
Test name
Test status
Simulation time 197306217 ps
CPU time 0.89 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206668 kb
Host smart-2ecb2d92-b1be-4326-b72b-ac22ac56d41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
02842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2562302842
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.2872533590
Short name T701
Test name
Test status
Simulation time 161903433 ps
CPU time 0.77 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206648 kb
Host smart-1817e4e5-f643-43e9-b96d-29d002f2b65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
33590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.2872533590
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.1466389618
Short name T775
Test name
Test status
Simulation time 203398449 ps
CPU time 0.88 seconds
Started Jul 18 05:46:52 PM PDT 24
Finished Jul 18 05:46:57 PM PDT 24
Peak memory 206620 kb
Host smart-cc1c8bb6-9eb3-4582-b07e-1e5026a4be7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14663
89618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.1466389618
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1209903289
Short name T2367
Test name
Test status
Simulation time 226583531 ps
CPU time 0.93 seconds
Started Jul 18 05:46:50 PM PDT 24
Finished Jul 18 05:46:55 PM PDT 24
Peak memory 206632 kb
Host smart-f8ca9032-45a7-4d30-83d5-7218628e9adf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1209903289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1209903289
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.4209622628
Short name T608
Test name
Test status
Simulation time 193991250 ps
CPU time 0.81 seconds
Started Jul 18 05:46:52 PM PDT 24
Finished Jul 18 05:46:57 PM PDT 24
Peak memory 206644 kb
Host smart-b5cefbed-7384-4762-8226-fa9dd1f803f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42096
22628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.4209622628
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.3083340286
Short name T89
Test name
Test status
Simulation time 9563984429 ps
CPU time 19.91 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:47:15 PM PDT 24
Peak memory 206928 kb
Host smart-b0ac29a3-5f35-4582-a92d-7c35f3e85990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30833
40286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.3083340286
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.2388068179
Short name T2388
Test name
Test status
Simulation time 172230163 ps
CPU time 0.83 seconds
Started Jul 18 05:46:55 PM PDT 24
Finished Jul 18 05:47:03 PM PDT 24
Peak memory 206628 kb
Host smart-143ab4cf-7041-472f-8051-69e870561cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23880
68179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.2388068179
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1189665881
Short name T1499
Test name
Test status
Simulation time 177385936 ps
CPU time 0.81 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206648 kb
Host smart-58de8837-a8f8-445d-b30e-5f27eae8e2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11896
65881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1189665881
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2288822030
Short name T2524
Test name
Test status
Simulation time 214279191 ps
CPU time 0.86 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:46:55 PM PDT 24
Peak memory 206648 kb
Host smart-6f2b1ffb-54df-4793-978d-0643e71e50cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22888
22030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2288822030
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.101522337
Short name T1994
Test name
Test status
Simulation time 212631100 ps
CPU time 0.89 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206592 kb
Host smart-8fbb1e2c-477d-4f07-acde-e191c106f3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10152
2337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.101522337
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.3143639198
Short name T1728
Test name
Test status
Simulation time 197477987 ps
CPU time 0.9 seconds
Started Jul 18 05:46:53 PM PDT 24
Finished Jul 18 05:46:57 PM PDT 24
Peak memory 206616 kb
Host smart-e54a7e69-461b-4bab-bdbd-de044016da53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31436
39198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.3143639198
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.1792236884
Short name T901
Test name
Test status
Simulation time 150059353 ps
CPU time 0.78 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206644 kb
Host smart-c09b9bd7-0784-4eea-bca6-10d9ee063b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17922
36884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.1792236884
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.2445020217
Short name T1231
Test name
Test status
Simulation time 184133254 ps
CPU time 0.84 seconds
Started Jul 18 05:46:53 PM PDT 24
Finished Jul 18 05:46:59 PM PDT 24
Peak memory 206620 kb
Host smart-20e43453-be17-43dd-88e4-653845ad7088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24450
20217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.2445020217
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.84559732
Short name T2050
Test name
Test status
Simulation time 218121285 ps
CPU time 0.92 seconds
Started Jul 18 05:46:54 PM PDT 24
Finished Jul 18 05:47:02 PM PDT 24
Peak memory 206652 kb
Host smart-2b2e8e39-ea7e-4d15-87cd-9da62abbbffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84559
732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.84559732
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2161710541
Short name T386
Test name
Test status
Simulation time 4627665138 ps
CPU time 32.37 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:47:27 PM PDT 24
Peak memory 206832 kb
Host smart-7c538683-d310-418f-9669-97fd2fe946b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2161710541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2161710541
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2737787356
Short name T624
Test name
Test status
Simulation time 171289380 ps
CPU time 0.81 seconds
Started Jul 18 05:46:53 PM PDT 24
Finished Jul 18 05:47:00 PM PDT 24
Peak memory 206620 kb
Host smart-22d5b874-054a-4ee5-8da6-0a1683fa1ced
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27377
87356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2737787356
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.2601843962
Short name T2396
Test name
Test status
Simulation time 259473193 ps
CPU time 0.93 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206636 kb
Host smart-684cdff3-44dd-45fa-b2ca-6758274d743d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26018
43962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.2601843962
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3129850686
Short name T2243
Test name
Test status
Simulation time 971293795 ps
CPU time 2.32 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206764 kb
Host smart-b88e14af-cbea-4c1e-b93a-998d07e29027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31298
50686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3129850686
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.971002529
Short name T2375
Test name
Test status
Simulation time 4671827203 ps
CPU time 34.08 seconds
Started Jul 18 05:46:54 PM PDT 24
Finished Jul 18 05:47:34 PM PDT 24
Peak memory 206904 kb
Host smart-b8a4604e-2c54-47e8-8fc5-6be67a196aca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97100
2529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.971002529
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1757904925
Short name T2531
Test name
Test status
Simulation time 37285889 ps
CPU time 0.68 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206540 kb
Host smart-bd9c921f-d5db-410d-96e5-96e675390d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1757904925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1757904925
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2618955196
Short name T1744
Test name
Test status
Simulation time 4078511146 ps
CPU time 4.83 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206468 kb
Host smart-a0ba8f1b-bc49-4030-962e-6b8d4f7211db
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2618955196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2618955196
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1229750177
Short name T2472
Test name
Test status
Simulation time 13415274353 ps
CPU time 11.9 seconds
Started Jul 18 05:46:53 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206888 kb
Host smart-4c092b74-485a-4b13-b877-f2f519d2f12a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1229750177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1229750177
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.3911336217
Short name T2061
Test name
Test status
Simulation time 23346715907 ps
CPU time 27.18 seconds
Started Jul 18 05:46:52 PM PDT 24
Finished Jul 18 05:47:22 PM PDT 24
Peak memory 206752 kb
Host smart-537625c8-b1cf-4f25-b3e2-e9b2b887710e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3911336217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.3911336217
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.3757787355
Short name T2450
Test name
Test status
Simulation time 146561134 ps
CPU time 0.83 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206080 kb
Host smart-09bbe13f-702d-4df2-8fd2-b1c81f8c9d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37577
87355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.3757787355
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.959196739
Short name T800
Test name
Test status
Simulation time 153178604 ps
CPU time 0.81 seconds
Started Jul 18 05:46:52 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206656 kb
Host smart-cbb08db6-7210-4011-802b-1bd529ff8d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95919
6739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.959196739
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.703533461
Short name T1078
Test name
Test status
Simulation time 220348267 ps
CPU time 0.93 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206656 kb
Host smart-1baa8eb5-498a-4647-9d9b-091b41d9c5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70353
3461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.703533461
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1678131126
Short name T551
Test name
Test status
Simulation time 1360021371 ps
CPU time 2.99 seconds
Started Jul 18 05:46:54 PM PDT 24
Finished Jul 18 05:47:03 PM PDT 24
Peak memory 206804 kb
Host smart-a439e76a-28b6-4a98-8840-739fa52adf79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16781
31126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1678131126
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.890886416
Short name T2600
Test name
Test status
Simulation time 10948741681 ps
CPU time 19.12 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206836 kb
Host smart-2bc8ff91-ff48-4175-804b-dc983a9fab8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89088
6416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.890886416
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1228718334
Short name T2718
Test name
Test status
Simulation time 479178564 ps
CPU time 1.37 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 205548 kb
Host smart-153d922e-2929-4215-9657-4b7d993e89a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12287
18334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1228718334
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.947104429
Short name T2751
Test name
Test status
Simulation time 163979313 ps
CPU time 0.78 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206648 kb
Host smart-ca2b1e0c-1501-4b25-8a57-807ef01c2a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94710
4429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.947104429
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.2133640922
Short name T1095
Test name
Test status
Simulation time 79349217 ps
CPU time 0.71 seconds
Started Jul 18 05:46:50 PM PDT 24
Finished Jul 18 05:46:55 PM PDT 24
Peak memory 206648 kb
Host smart-69910ea9-884a-4792-aa09-9e2e02340f29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21336
40922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.2133640922
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3274096224
Short name T353
Test name
Test status
Simulation time 890102644 ps
CPU time 2.12 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206712 kb
Host smart-1937aee4-89b1-48e9-8db6-0d6d3e16dfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32740
96224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3274096224
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3587428215
Short name T2087
Test name
Test status
Simulation time 207146072 ps
CPU time 1.42 seconds
Started Jul 18 05:46:54 PM PDT 24
Finished Jul 18 05:47:02 PM PDT 24
Peak memory 206796 kb
Host smart-f6d91412-2308-4be7-bf86-44714822c58e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35874
28215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3587428215
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.162601601
Short name T2596
Test name
Test status
Simulation time 244904541 ps
CPU time 1.02 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206644 kb
Host smart-c59202a8-f8b8-4d2d-b88e-1e7723d5834c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16260
1601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.162601601
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2292832301
Short name T375
Test name
Test status
Simulation time 151297425 ps
CPU time 0.81 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:05 PM PDT 24
Peak memory 205504 kb
Host smart-ef85b900-c409-43a6-8f54-70841a268bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
32301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2292832301
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.1914995729
Short name T2200
Test name
Test status
Simulation time 301972351 ps
CPU time 0.97 seconds
Started Jul 18 05:46:55 PM PDT 24
Finished Jul 18 05:47:04 PM PDT 24
Peak memory 206616 kb
Host smart-d4a36462-659d-416f-af96-8e5ac7f1257f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19149
95729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.1914995729
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2757686183
Short name T2631
Test name
Test status
Simulation time 5696489529 ps
CPU time 53.34 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:57 PM PDT 24
Peak memory 206852 kb
Host smart-bba72cd2-5919-4f84-8e0b-e4b1808f7b93
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2757686183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2757686183
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.110127499
Short name T796
Test name
Test status
Simulation time 11840248688 ps
CPU time 38.87 seconds
Started Jul 18 05:46:52 PM PDT 24
Finished Jul 18 05:47:35 PM PDT 24
Peak memory 206824 kb
Host smart-ff8a78f6-b32e-48ff-ad23-6b5b40f477e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11012
7499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.110127499
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2762651892
Short name T2625
Test name
Test status
Simulation time 190377038 ps
CPU time 0.82 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206644 kb
Host smart-d55a3c6d-87a5-41fb-9753-bee3250c9d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27626
51892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2762651892
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.4233211848
Short name T492
Test name
Test status
Simulation time 23354878100 ps
CPU time 24.1 seconds
Started Jul 18 05:46:51 PM PDT 24
Finished Jul 18 05:47:19 PM PDT 24
Peak memory 206744 kb
Host smart-66ca832f-2bcb-4b68-bb1d-1d93530c2845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42332
11848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.4233211848
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2071786989
Short name T1000
Test name
Test status
Simulation time 3398623543 ps
CPU time 4.48 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:11 PM PDT 24
Peak memory 206716 kb
Host smart-07e94027-c03f-45f1-b9a4-149487787fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20717
86989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2071786989
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.2456516191
Short name T2527
Test name
Test status
Simulation time 11332789311 ps
CPU time 107.49 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:48:55 PM PDT 24
Peak memory 206920 kb
Host smart-7f15f7ff-5505-48e3-8fed-8cc7419f06e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24565
16191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.2456516191
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1327774838
Short name T424
Test name
Test status
Simulation time 5587132888 ps
CPU time 41.32 seconds
Started Jul 18 05:48:41 PM PDT 24
Finished Jul 18 05:49:30 PM PDT 24
Peak memory 206904 kb
Host smart-8b0e1361-b616-44f2-bc7d-aafc6572a488
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1327774838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1327774838
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.628124333
Short name T717
Test name
Test status
Simulation time 259895954 ps
CPU time 0.96 seconds
Started Jul 18 05:47:09 PM PDT 24
Finished Jul 18 05:47:24 PM PDT 24
Peak memory 206668 kb
Host smart-a4b41e9d-3146-43ef-a302-e2e047f41139
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=628124333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.628124333
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.2847956863
Short name T2277
Test name
Test status
Simulation time 198244743 ps
CPU time 0.92 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206124 kb
Host smart-4fb846c2-07e3-435a-941d-931975a5653e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
56863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.2847956863
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.1316469593
Short name T1038
Test name
Test status
Simulation time 6154131561 ps
CPU time 44.25 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:53 PM PDT 24
Peak memory 206852 kb
Host smart-c23aed03-0438-4cec-a314-7348bd623f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13164
69593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.1316469593
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1054801372
Short name T934
Test name
Test status
Simulation time 4195689322 ps
CPU time 29.28 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:35 PM PDT 24
Peak memory 206804 kb
Host smart-3a2eb5e4-fa19-4acc-966d-288f9908f5c2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1054801372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1054801372
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.773301652
Short name T2609
Test name
Test status
Simulation time 155601136 ps
CPU time 0.76 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206668 kb
Host smart-0ff00abf-b5da-44f4-ba68-cc1d8926a1fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=773301652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.773301652
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2594428552
Short name T2309
Test name
Test status
Simulation time 142592141 ps
CPU time 0.75 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206232 kb
Host smart-46e50933-b8a1-416b-ad1b-8993d9670d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25944
28552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2594428552
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.695031737
Short name T2549
Test name
Test status
Simulation time 231314307 ps
CPU time 0.97 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206256 kb
Host smart-5eaa512c-a70f-4fdb-9fb3-1764b1a7caf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69503
1737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.695031737
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.2597206742
Short name T1461
Test name
Test status
Simulation time 197646047 ps
CPU time 0.9 seconds
Started Jul 18 05:46:55 PM PDT 24
Finished Jul 18 05:47:03 PM PDT 24
Peak memory 206616 kb
Host smart-e1bc9923-134d-437b-8507-58589d0c6b21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25972
06742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.2597206742
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.3535592581
Short name T2550
Test name
Test status
Simulation time 175117829 ps
CPU time 0.81 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206656 kb
Host smart-0fa79d23-c468-4462-a315-fa5cbe314c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35355
92581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.3535592581
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.200934828
Short name T105
Test name
Test status
Simulation time 182011205 ps
CPU time 0.81 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206604 kb
Host smart-77fb4c9e-c062-4cad-8542-a0c75afa2464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20093
4828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.200934828
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.4027279154
Short name T1285
Test name
Test status
Simulation time 160848738 ps
CPU time 0.77 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:07 PM PDT 24
Peak memory 206648 kb
Host smart-5719968b-73d5-468c-a57f-af00349c9dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40272
79154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.4027279154
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3349883034
Short name T1753
Test name
Test status
Simulation time 229494896 ps
CPU time 0.96 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206636 kb
Host smart-5dc8d48d-4874-4f30-a189-83b0b4e5798f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3349883034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3349883034
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4240374528
Short name T2306
Test name
Test status
Simulation time 144087508 ps
CPU time 0.86 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206608 kb
Host smart-6bd8defa-bd79-4182-87c6-acd13ce1adbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42403
74528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4240374528
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.837974585
Short name T564
Test name
Test status
Simulation time 89611050 ps
CPU time 0.76 seconds
Started Jul 18 05:46:55 PM PDT 24
Finished Jul 18 05:47:03 PM PDT 24
Peak memory 206652 kb
Host smart-3d5d24ac-5cad-4527-94cd-d193ee61f668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83797
4585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.837974585
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.932724015
Short name T2649
Test name
Test status
Simulation time 13094864888 ps
CPU time 27.42 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206896 kb
Host smart-d8427142-5004-429a-ad3a-bac2795a8190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93272
4015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.932724015
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.2469743169
Short name T1371
Test name
Test status
Simulation time 174517301 ps
CPU time 0.84 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:09 PM PDT 24
Peak memory 206652 kb
Host smart-8f406748-0033-458f-8f8d-33542f3e137f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24697
43169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.2469743169
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.2646912710
Short name T2088
Test name
Test status
Simulation time 182929637 ps
CPU time 0.85 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:15 PM PDT 24
Peak memory 206624 kb
Host smart-9ab618cd-1bfd-4e7b-8e11-a304381553ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26469
12710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.2646912710
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.4015135412
Short name T501
Test name
Test status
Simulation time 274445673 ps
CPU time 0.95 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206644 kb
Host smart-da0ca5c1-2511-4e50-82b8-fd5f4e415fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40151
35412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.4015135412
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3442681706
Short name T302
Test name
Test status
Simulation time 161837411 ps
CPU time 0.81 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206624 kb
Host smart-bfcedf54-a3bd-4221-b23a-55c75e08a2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34426
81706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3442681706
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.734388239
Short name T1486
Test name
Test status
Simulation time 163280383 ps
CPU time 0.81 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:12 PM PDT 24
Peak memory 206652 kb
Host smart-a98069d1-ccd8-418d-81cc-f2435892522f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73438
8239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.734388239
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2856786204
Short name T1307
Test name
Test status
Simulation time 151797061 ps
CPU time 0.78 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206636 kb
Host smart-ca593307-ca96-4085-9f6e-20c4d151b3b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28567
86204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2856786204
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3118246453
Short name T1958
Test name
Test status
Simulation time 230795436 ps
CPU time 0.85 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206648 kb
Host smart-762af3c3-ef0c-4f4c-a783-feffa8811fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31182
46453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3118246453
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.686117981
Short name T661
Test name
Test status
Simulation time 208432578 ps
CPU time 0.99 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206640 kb
Host smart-4c3adb7c-342f-4ae2-a1f8-cc10a14562ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68611
7981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.686117981
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.3738274261
Short name T950
Test name
Test status
Simulation time 4684395911 ps
CPU time 124.96 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:49:14 PM PDT 24
Peak memory 206844 kb
Host smart-6b0bd387-00a4-4608-beb2-47b5e17eaf0a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3738274261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.3738274261
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.3091891252
Short name T1960
Test name
Test status
Simulation time 189959531 ps
CPU time 0.83 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206620 kb
Host smart-2809df84-69fe-4584-9efe-bb4b1f383cca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30918
91252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.3091891252
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3690839922
Short name T751
Test name
Test status
Simulation time 173426407 ps
CPU time 0.78 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206648 kb
Host smart-d2889937-b194-4690-ae60-e5b66d6dd4de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36908
39922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3690839922
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3656000079
Short name T2606
Test name
Test status
Simulation time 667697765 ps
CPU time 1.76 seconds
Started Jul 18 05:47:04 PM PDT 24
Finished Jul 18 05:47:20 PM PDT 24
Peak memory 206756 kb
Host smart-8afdbc94-2ee2-4e50-89d0-fc08bcb82fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36560
00079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3656000079
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.4098061500
Short name T1755
Test name
Test status
Simulation time 7058102040 ps
CPU time 205.35 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:50:37 PM PDT 24
Peak memory 206864 kb
Host smart-cf32a373-db00-4c6d-a8f5-d5fd53ddddb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40980
61500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.4098061500
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.3314094113
Short name T179
Test name
Test status
Simulation time 39206749 ps
CPU time 0.68 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206668 kb
Host smart-f3f6ea2a-1c56-4907-8123-5e9f0de60ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3314094113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.3314094113
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.1160018929
Short name T1723
Test name
Test status
Simulation time 3620878079 ps
CPU time 4.4 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206732 kb
Host smart-d8360c61-629b-43fe-9b3a-166ec9601ef6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1160018929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.1160018929
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1615243621
Short name T1825
Test name
Test status
Simulation time 13521897741 ps
CPU time 12.78 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206944 kb
Host smart-013d32ea-f498-4150-b62f-bf1331b0a3c7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1615243621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1615243621
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1264376447
Short name T816
Test name
Test status
Simulation time 23323989303 ps
CPU time 24.9 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:30 PM PDT 24
Peak memory 206760 kb
Host smart-307e99a2-5401-440e-bac4-2463e17e64e7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1264376447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1264376447
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.358931744
Short name T1666
Test name
Test status
Simulation time 162888114 ps
CPU time 0.8 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:09 PM PDT 24
Peak memory 206660 kb
Host smart-56f04f13-afc4-4710-9ec4-83aaa8a78b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35893
1744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.358931744
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1749816257
Short name T2691
Test name
Test status
Simulation time 175528244 ps
CPU time 0.86 seconds
Started Jul 18 05:46:54 PM PDT 24
Finished Jul 18 05:47:02 PM PDT 24
Peak memory 206656 kb
Host smart-4fa147bf-a635-4205-b645-2d81168a2811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17498
16257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1749816257
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.936586878
Short name T2170
Test name
Test status
Simulation time 320838439 ps
CPU time 1.19 seconds
Started Jul 18 05:46:55 PM PDT 24
Finished Jul 18 05:47:03 PM PDT 24
Peak memory 206644 kb
Host smart-098efc9d-63cd-43fe-ba70-d55cee2cd75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93658
6878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.936586878
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.60568711
Short name T689
Test name
Test status
Simulation time 892407604 ps
CPU time 2.05 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:12 PM PDT 24
Peak memory 206704 kb
Host smart-03f00682-a14c-4eb6-815b-4688bb98f870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60568
711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.60568711
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2460595824
Short name T773
Test name
Test status
Simulation time 7660126798 ps
CPU time 16.46 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:24 PM PDT 24
Peak memory 206940 kb
Host smart-3f6740a2-8d91-414c-895d-a1c5ad599690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24605
95824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2460595824
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.1284094774
Short name T1272
Test name
Test status
Simulation time 414391035 ps
CPU time 1.28 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:16 PM PDT 24
Peak memory 206620 kb
Host smart-a70fc685-5876-42b6-bbae-ad4fbc0edf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12840
94774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.1284094774
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.1429728739
Short name T1062
Test name
Test status
Simulation time 141859183 ps
CPU time 0.77 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206652 kb
Host smart-e4e92101-aa65-4a1f-98f8-c7e971fd4ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14297
28739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.1429728739
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.322691435
Short name T223
Test name
Test status
Simulation time 46857468 ps
CPU time 0.68 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:12 PM PDT 24
Peak memory 206640 kb
Host smart-05e8f4e6-bee1-4fc9-a330-3bf8917d855d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32269
1435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.322691435
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.365915658
Short name T1779
Test name
Test status
Simulation time 1032651791 ps
CPU time 2.42 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206744 kb
Host smart-c1bc8908-4264-4d2f-95d4-cca7778eee26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36591
5658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.365915658
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.838669231
Short name T1199
Test name
Test status
Simulation time 301137566 ps
CPU time 1.59 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206720 kb
Host smart-046a2733-95f9-456b-b9d2-9f681a1f2963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83866
9231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.838669231
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.795096478
Short name T361
Test name
Test status
Simulation time 261164581 ps
CPU time 0.94 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:12 PM PDT 24
Peak memory 206644 kb
Host smart-b1d7e676-7a97-454f-a6b8-3a5de44a70eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79509
6478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.795096478
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2417348362
Short name T1063
Test name
Test status
Simulation time 179475919 ps
CPU time 0.9 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206636 kb
Host smart-a9f51a4b-db04-4694-b1ab-9270f4f5567e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24173
48362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2417348362
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.4259967079
Short name T935
Test name
Test status
Simulation time 168769061 ps
CPU time 0.79 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206640 kb
Host smart-ac0c2a39-1bfe-4853-9062-37737fb75e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42599
67079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.4259967079
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.280127253
Short name T1647
Test name
Test status
Simulation time 7758824064 ps
CPU time 56.84 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:48:08 PM PDT 24
Peak memory 206900 kb
Host smart-79629e5f-f6ce-4dd9-9781-bcb5cb1c0dbc
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=280127253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.280127253
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3036139767
Short name T826
Test name
Test status
Simulation time 7797664782 ps
CPU time 71.63 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:48:24 PM PDT 24
Peak memory 206836 kb
Host smart-233a4473-31dc-4999-8115-b9d606a71dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30361
39767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3036139767
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1226084811
Short name T892
Test name
Test status
Simulation time 208710887 ps
CPU time 0.99 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206636 kb
Host smart-b3ffdd67-b1c0-4e75-bcd1-ab461871da9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12260
84811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1226084811
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1787890106
Short name T440
Test name
Test status
Simulation time 23303755355 ps
CPU time 23.66 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206756 kb
Host smart-d3381b45-c552-4057-ae04-10bba2ac61ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17878
90106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1787890106
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.92352325
Short name T1236
Test name
Test status
Simulation time 3339365676 ps
CPU time 3.78 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:18 PM PDT 24
Peak memory 206708 kb
Host smart-a5bb895a-4690-407c-a0e7-18a04f3608c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92352
325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.92352325
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.2918924531
Short name T1849
Test name
Test status
Simulation time 10241814021 ps
CPU time 93.14 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206912 kb
Host smart-58f908b1-6dbd-49a4-926e-58a607ff9ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
24531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.2918924531
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2573702600
Short name T537
Test name
Test status
Simulation time 7517176676 ps
CPU time 76.72 seconds
Started Jul 18 05:47:04 PM PDT 24
Finished Jul 18 05:48:35 PM PDT 24
Peak memory 206888 kb
Host smart-9a95a5f9-5a10-48b1-b181-1146b68387e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2573702600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2573702600
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2308050705
Short name T1827
Test name
Test status
Simulation time 247739978 ps
CPU time 1.12 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:05 PM PDT 24
Peak memory 206640 kb
Host smart-02091c04-da0a-411d-bcbe-c39f6507db3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2308050705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2308050705
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2697066826
Short name T2089
Test name
Test status
Simulation time 215032570 ps
CPU time 0.91 seconds
Started Jul 18 05:47:04 PM PDT 24
Finished Jul 18 05:47:19 PM PDT 24
Peak memory 206632 kb
Host smart-a9a8992e-8e06-4514-b622-8b08d304fcdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26970
66826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2697066826
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.3139454588
Short name T1182
Test name
Test status
Simulation time 3409828270 ps
CPU time 33.37 seconds
Started Jul 18 05:47:04 PM PDT 24
Finished Jul 18 05:47:52 PM PDT 24
Peak memory 206880 kb
Host smart-0c93a2aa-d994-4b69-87ae-d1d181b87a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31394
54588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.3139454588
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3263481558
Short name T1326
Test name
Test status
Simulation time 5097078750 ps
CPU time 143.76 seconds
Started Jul 18 05:47:04 PM PDT 24
Finished Jul 18 05:49:42 PM PDT 24
Peak memory 206828 kb
Host smart-cc02b756-bb53-4d27-b488-4d03ce975ad0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3263481558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3263481558
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.3649568678
Short name T2233
Test name
Test status
Simulation time 156435409 ps
CPU time 0.76 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206636 kb
Host smart-892a5885-3919-4ba8-8ea0-2591649a12df
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3649568678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.3649568678
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1433114468
Short name T494
Test name
Test status
Simulation time 147309372 ps
CPU time 0.77 seconds
Started Jul 18 05:47:04 PM PDT 24
Finished Jul 18 05:47:19 PM PDT 24
Peak memory 206624 kb
Host smart-f5881dec-dbff-41e3-981c-8feb3a14714f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14331
14468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1433114468
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.1687319924
Short name T122
Test name
Test status
Simulation time 214217416 ps
CPU time 0.9 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:15 PM PDT 24
Peak memory 206636 kb
Host smart-5ebe9a27-bb5d-4a07-a4d4-4656b1dfa03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16873
19924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.1687319924
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2781429775
Short name T2229
Test name
Test status
Simulation time 171343283 ps
CPU time 0.81 seconds
Started Jul 18 05:47:03 PM PDT 24
Finished Jul 18 05:47:19 PM PDT 24
Peak memory 206632 kb
Host smart-093ce9c5-d487-4fe9-afaa-7e3f871f81ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27814
29775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2781429775
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1381920829
Short name T295
Test name
Test status
Simulation time 184368136 ps
CPU time 0.82 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206652 kb
Host smart-81a06d6b-2f67-49d9-88eb-e33a1f640799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13819
20829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1381920829
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.1308373498
Short name T2249
Test name
Test status
Simulation time 170182838 ps
CPU time 0.76 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:15 PM PDT 24
Peak memory 206636 kb
Host smart-1d4c7ab6-2988-42f2-9c85-aff114a4a2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
73498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.1308373498
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.526799858
Short name T166
Test name
Test status
Simulation time 164612386 ps
CPU time 0.77 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:07 PM PDT 24
Peak memory 206652 kb
Host smart-3c94618c-aa42-47e4-a3b0-e44e0626f800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52679
9858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.526799858
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2012032431
Short name T2488
Test name
Test status
Simulation time 223717967 ps
CPU time 0.91 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206636 kb
Host smart-224f8a26-45c9-478a-be74-fee1bafdd5d2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2012032431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2012032431
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1256944406
Short name T374
Test name
Test status
Simulation time 158262516 ps
CPU time 0.82 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206628 kb
Host smart-631d6aaa-27ad-4930-bf75-3bdec97509e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12569
44406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1256944406
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.430180581
Short name T1211
Test name
Test status
Simulation time 19617282169 ps
CPU time 42.62 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 215080 kb
Host smart-9bbae89f-1138-42b8-9e45-757d2ee7c16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43018
0581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.430180581
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.2008197468
Short name T1452
Test name
Test status
Simulation time 185288728 ps
CPU time 0.86 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:13 PM PDT 24
Peak memory 206660 kb
Host smart-31a66367-521d-4e8a-8d51-b2f2709963df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20081
97468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.2008197468
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2491030579
Short name T1870
Test name
Test status
Simulation time 293327954 ps
CPU time 0.97 seconds
Started Jul 18 05:46:57 PM PDT 24
Finished Jul 18 05:47:07 PM PDT 24
Peak memory 206616 kb
Host smart-1ae4e5d9-643e-446d-9d41-e0ecdc419c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
30579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2491030579
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.714630937
Short name T676
Test name
Test status
Simulation time 226416084 ps
CPU time 1 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206656 kb
Host smart-c992966a-9ab1-4b28-8e65-90f89b1eba2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71463
0937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.714630937
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.958641803
Short name T2232
Test name
Test status
Simulation time 171442886 ps
CPU time 0.84 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:14 PM PDT 24
Peak memory 206636 kb
Host smart-b6686bdf-7544-42af-80a5-3f199a27bb35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95864
1803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.958641803
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.2625068857
Short name T1262
Test name
Test status
Simulation time 133427958 ps
CPU time 0.74 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:15 PM PDT 24
Peak memory 206632 kb
Host smart-db8180a1-de0c-429a-9fae-2fc368410716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26250
68857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.2625068857
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.735819090
Short name T450
Test name
Test status
Simulation time 146535589 ps
CPU time 0.76 seconds
Started Jul 18 05:47:07 PM PDT 24
Finished Jul 18 05:47:21 PM PDT 24
Peak memory 206620 kb
Host smart-cde926f4-9010-4df4-836d-312cc80a799d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73581
9090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.735819090
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3256600332
Short name T1475
Test name
Test status
Simulation time 159928384 ps
CPU time 0.78 seconds
Started Jul 18 05:47:07 PM PDT 24
Finished Jul 18 05:47:21 PM PDT 24
Peak memory 206644 kb
Host smart-2b099e41-248b-4a09-b514-2d047df7acdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32566
00332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3256600332
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3811995075
Short name T1771
Test name
Test status
Simulation time 231670072 ps
CPU time 0.9 seconds
Started Jul 18 05:47:07 PM PDT 24
Finished Jul 18 05:47:21 PM PDT 24
Peak memory 206636 kb
Host smart-6583e32e-aaec-454e-b48f-b75f3baa38e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38119
95075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3811995075
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3611281284
Short name T1485
Test name
Test status
Simulation time 4666990510 ps
CPU time 132 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:49:21 PM PDT 24
Peak memory 206864 kb
Host smart-83f26ad1-3a93-4b1f-9af3-5cdb5b6f29db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3611281284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3611281284
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3299883394
Short name T366
Test name
Test status
Simulation time 156698289 ps
CPU time 0.75 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:06 PM PDT 24
Peak memory 206632 kb
Host smart-261402b9-795f-457d-9524-552f0c50d763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32998
83394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3299883394
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1208984637
Short name T2097
Test name
Test status
Simulation time 243763897 ps
CPU time 0.84 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:05 PM PDT 24
Peak memory 206652 kb
Host smart-7903532c-20a0-4b6d-bcaa-2295f0763b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12089
84637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1208984637
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.3611655811
Short name T1524
Test name
Test status
Simulation time 1273677984 ps
CPU time 2.67 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:15 PM PDT 24
Peak memory 206684 kb
Host smart-b9e8864b-e306-4a70-9411-c4088bc638b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36116
55811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3611655811
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.3972689688
Short name T1203
Test name
Test status
Simulation time 6237345691 ps
CPU time 45.75 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:54 PM PDT 24
Peak memory 206868 kb
Host smart-88f4db0e-0f86-4baf-a4e5-9bbeb94faae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39726
89688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.3972689688
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.2671382158
Short name T2339
Test name
Test status
Simulation time 86440238 ps
CPU time 0.7 seconds
Started Jul 18 05:43:52 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206708 kb
Host smart-61732a23-d0ff-4d64-aef0-36cf084abf5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2671382158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.2671382158
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1451456272
Short name T915
Test name
Test status
Simulation time 3835607190 ps
CPU time 5.04 seconds
Started Jul 18 05:44:30 PM PDT 24
Finished Jul 18 05:44:36 PM PDT 24
Peak memory 206788 kb
Host smart-af51dcca-f187-4170-8cb2-98a9e5df06d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1451456272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1451456272
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.1431791926
Short name T880
Test name
Test status
Simulation time 13498126854 ps
CPU time 13.32 seconds
Started Jul 18 05:43:38 PM PDT 24
Finished Jul 18 05:44:06 PM PDT 24
Peak memory 206888 kb
Host smart-22703e9c-6679-4a0b-ba11-11f0465b948f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1431791926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.1431791926
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3228766181
Short name T911
Test name
Test status
Simulation time 23356705055 ps
CPU time 30.23 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:44:22 PM PDT 24
Peak memory 206780 kb
Host smart-ec81649c-3bdc-4d5a-a299-f14ba97dbaee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3228766181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.3228766181
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.4159848500
Short name T1675
Test name
Test status
Simulation time 153494548 ps
CPU time 0.8 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 206624 kb
Host smart-5615abaf-ab64-4508-9541-c401ea146836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41598
48500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.4159848500
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.623992872
Short name T644
Test name
Test status
Simulation time 140090761 ps
CPU time 0.8 seconds
Started Jul 18 05:43:34 PM PDT 24
Finished Jul 18 05:43:50 PM PDT 24
Peak memory 206656 kb
Host smart-55cc0961-e71b-4f46-837a-494c1fa698ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62399
2872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.623992872
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2136349004
Short name T1600
Test name
Test status
Simulation time 343920386 ps
CPU time 1.21 seconds
Started Jul 18 05:43:35 PM PDT 24
Finished Jul 18 05:43:52 PM PDT 24
Peak memory 206640 kb
Host smart-422d2fc2-10a1-4edc-8112-5c1591535b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21363
49004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2136349004
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.642219986
Short name T1531
Test name
Test status
Simulation time 650758251 ps
CPU time 1.57 seconds
Started Jul 18 05:43:38 PM PDT 24
Finished Jul 18 05:43:55 PM PDT 24
Peak memory 206692 kb
Host smart-baf5eee0-8381-4dc6-833b-3fe0d324d73a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64221
9986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.642219986
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.1131021441
Short name T1853
Test name
Test status
Simulation time 23085507176 ps
CPU time 41.4 seconds
Started Jul 18 05:43:47 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206892 kb
Host smart-a2e4089c-e3cf-450a-83cd-22d361844d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11310
21441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.1131021441
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.2027626659
Short name T1727
Test name
Test status
Simulation time 443840161 ps
CPU time 1.32 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:43:54 PM PDT 24
Peak memory 206620 kb
Host smart-0fa0700f-a86a-4cf5-94a5-4ea2a9cd8127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20276
26659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.2027626659
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2508050030
Short name T1258
Test name
Test status
Simulation time 134407493 ps
CPU time 0.74 seconds
Started Jul 18 05:43:35 PM PDT 24
Finished Jul 18 05:43:51 PM PDT 24
Peak memory 206728 kb
Host smart-11dbc8a4-3349-434f-8e0b-9ec9d3e11a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25080
50030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2508050030
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.3130011215
Short name T1411
Test name
Test status
Simulation time 53331935 ps
CPU time 0.69 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 206648 kb
Host smart-54bc99c1-b810-4843-b81f-607ce7f10f39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31300
11215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.3130011215
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3092237321
Short name T2298
Test name
Test status
Simulation time 979962975 ps
CPU time 2.3 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:43:55 PM PDT 24
Peak memory 206736 kb
Host smart-89fa0e1f-19d8-40e4-8bbe-ff81963d47eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30922
37321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3092237321
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.1408876795
Short name T1291
Test name
Test status
Simulation time 192045611 ps
CPU time 2.27 seconds
Started Jul 18 05:43:43 PM PDT 24
Finished Jul 18 05:44:02 PM PDT 24
Peak memory 206704 kb
Host smart-88c69891-74d0-4d3f-94a0-e233f5ea3c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14088
76795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.1408876795
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.3506809349
Short name T1426
Test name
Test status
Simulation time 109201620870 ps
CPU time 148.93 seconds
Started Jul 18 05:43:33 PM PDT 24
Finished Jul 18 05:46:17 PM PDT 24
Peak memory 206872 kb
Host smart-e8c838d5-5f76-489d-a2ce-d07cc28fdbf9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3506809349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.3506809349
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.471503964
Short name T792
Test name
Test status
Simulation time 113054309791 ps
CPU time 149.89 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:46:22 PM PDT 24
Peak memory 206864 kb
Host smart-33d8a2db-9d43-4cdc-aaf9-2034548639c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471503964 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.471503964
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.1899710256
Short name T1390
Test name
Test status
Simulation time 114148662419 ps
CPU time 184.96 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:47:04 PM PDT 24
Peak memory 206860 kb
Host smart-b1bc4b4e-d57d-4090-bebc-62a3c845b0ed
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1899710256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.1899710256
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.3867192891
Short name T1454
Test name
Test status
Simulation time 83186747332 ps
CPU time 111.9 seconds
Started Jul 18 05:43:39 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206888 kb
Host smart-8ffa4444-b1d6-41bb-99be-752b12cf6b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867192891 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.3867192891
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3146539625
Short name T2336
Test name
Test status
Simulation time 108129316455 ps
CPU time 148.19 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:46:20 PM PDT 24
Peak memory 206836 kb
Host smart-95c200d9-b770-4825-8245-9baf947110b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31465
39625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3146539625
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3204162903
Short name T2062
Test name
Test status
Simulation time 154887810 ps
CPU time 0.82 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:43:52 PM PDT 24
Peak memory 206612 kb
Host smart-f80b2b34-c262-4caa-8e0f-4b43556a39fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32041
62903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3204162903
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2564318719
Short name T1714
Test name
Test status
Simulation time 153026920 ps
CPU time 0.8 seconds
Started Jul 18 05:43:45 PM PDT 24
Finished Jul 18 05:44:03 PM PDT 24
Peak memory 206596 kb
Host smart-edaf98a4-1929-4cba-8d94-050f740489d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25643
18719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2564318719
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1853558672
Short name T1188
Test name
Test status
Simulation time 187211031 ps
CPU time 0.85 seconds
Started Jul 18 05:43:36 PM PDT 24
Finished Jul 18 05:43:52 PM PDT 24
Peak memory 206728 kb
Host smart-588082bc-e363-4f0b-b3cd-7644e56d2cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18535
58672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1853558672
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.2505322487
Short name T1587
Test name
Test status
Simulation time 5281603640 ps
CPU time 47.98 seconds
Started Jul 18 05:43:34 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 206936 kb
Host smart-e99e566d-78ac-4545-b152-b0c8dd249282
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2505322487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.2505322487
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3162439750
Short name T2234
Test name
Test status
Simulation time 4674347637 ps
CPU time 39.69 seconds
Started Jul 18 05:43:39 PM PDT 24
Finished Jul 18 05:44:34 PM PDT 24
Peak memory 206940 kb
Host smart-f585c6d8-76c9-47c4-a5d9-4f8079a33f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624
39750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3162439750
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3797050670
Short name T2603
Test name
Test status
Simulation time 232465117 ps
CPU time 0.86 seconds
Started Jul 18 05:43:47 PM PDT 24
Finished Jul 18 05:44:04 PM PDT 24
Peak memory 206620 kb
Host smart-16f24ac0-ce7d-4d6f-bed5-f2c01c68bad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37970
50670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3797050670
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.19573326
Short name T2039
Test name
Test status
Simulation time 23281528462 ps
CPU time 21.73 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:44:20 PM PDT 24
Peak memory 206776 kb
Host smart-0359d74d-1127-4311-b57e-82736974cdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19573
326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.19573326
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.3477361879
Short name T1287
Test name
Test status
Simulation time 3273978056 ps
CPU time 4.47 seconds
Started Jul 18 05:43:47 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206700 kb
Host smart-a7fa80fe-e60b-4a6e-8dce-b2c7e20edd2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34773
61879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.3477361879
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2902207754
Short name T2343
Test name
Test status
Simulation time 7556553772 ps
CPU time 213.12 seconds
Started Jul 18 05:43:47 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206940 kb
Host smart-3d57f459-063b-47e6-a48e-bef024e88ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29022
07754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2902207754
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3243618563
Short name T2743
Test name
Test status
Simulation time 6294280936 ps
CPU time 172.52 seconds
Started Jul 18 05:43:48 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206840 kb
Host smart-5e1904c8-5313-4701-b4e4-eacb55031b6b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3243618563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3243618563
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1674077222
Short name T1749
Test name
Test status
Simulation time 250796638 ps
CPU time 0.92 seconds
Started Jul 18 05:43:44 PM PDT 24
Finished Jul 18 05:44:02 PM PDT 24
Peak memory 206648 kb
Host smart-eb82a9d5-2c68-4d85-b0a2-3c6ad7286823
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1674077222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1674077222
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.2489754855
Short name T476
Test name
Test status
Simulation time 199585667 ps
CPU time 0.84 seconds
Started Jul 18 05:43:47 PM PDT 24
Finished Jul 18 05:44:04 PM PDT 24
Peak memory 206616 kb
Host smart-1f687d2d-93cf-41c0-b530-2e7436e4289d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24897
54855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.2489754855
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1342418993
Short name T1228
Test name
Test status
Simulation time 3791694170 ps
CPU time 26.42 seconds
Started Jul 18 05:43:44 PM PDT 24
Finished Jul 18 05:44:28 PM PDT 24
Peak memory 206924 kb
Host smart-c5c599ea-9a77-4420-8c94-c0665cdd77fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13424
18993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1342418993
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.72724804
Short name T1449
Test name
Test status
Simulation time 5099644323 ps
CPU time 47.97 seconds
Started Jul 18 05:43:48 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206900 kb
Host smart-bf1027c4-3cf7-4894-a7eb-8d2bdeeb5ef4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=72724804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.72724804
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.1570298491
Short name T1679
Test name
Test status
Simulation time 205450021 ps
CPU time 0.81 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 206648 kb
Host smart-097f0376-a064-42ee-a7a2-15fc9c46fb7b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1570298491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.1570298491
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1615223784
Short name T563
Test name
Test status
Simulation time 177139764 ps
CPU time 0.84 seconds
Started Jul 18 05:43:48 PM PDT 24
Finished Jul 18 05:44:05 PM PDT 24
Peak memory 206628 kb
Host smart-397413a5-1313-4587-a2b7-d800a7b9c1d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16152
23784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1615223784
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3001626773
Short name T1927
Test name
Test status
Simulation time 196581180 ps
CPU time 0.88 seconds
Started Jul 18 05:43:38 PM PDT 24
Finished Jul 18 05:43:54 PM PDT 24
Peak memory 206656 kb
Host smart-b0ad6d22-d5c6-41a5-84c4-d4395b4bccd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30016
26773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3001626773
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3569934120
Short name T677
Test name
Test status
Simulation time 157082883 ps
CPU time 0.81 seconds
Started Jul 18 05:43:47 PM PDT 24
Finished Jul 18 05:44:04 PM PDT 24
Peak memory 206628 kb
Host smart-f2db12e3-c1e0-451c-a4aa-040f31f7c66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
34120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3569934120
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1950020307
Short name T18
Test name
Test status
Simulation time 165089984 ps
CPU time 0.84 seconds
Started Jul 18 05:43:48 PM PDT 24
Finished Jul 18 05:44:05 PM PDT 24
Peak memory 206640 kb
Host smart-6bee4702-a5be-4502-b49c-8de17fd664fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19500
20307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1950020307
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.1657216271
Short name T648
Test name
Test status
Simulation time 162813365 ps
CPU time 0.77 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:43:59 PM PDT 24
Peak memory 206648 kb
Host smart-b269ae0a-3232-4697-89a8-0052136b0fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16572
16271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.1657216271
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.3941211756
Short name T2580
Test name
Test status
Simulation time 162216545 ps
CPU time 0.79 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:43:53 PM PDT 24
Peak memory 206656 kb
Host smart-8d78d419-24e9-4483-b4f0-eaa8a9b862a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39412
11756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.3941211756
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.3288273437
Short name T2143
Test name
Test status
Simulation time 193388859 ps
CPU time 0.87 seconds
Started Jul 18 05:43:42 PM PDT 24
Finished Jul 18 05:44:00 PM PDT 24
Peak memory 206652 kb
Host smart-a34210b2-6b54-424f-afc6-538ea46f5f8d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3288273437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.3288273437
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1256417527
Short name T2034
Test name
Test status
Simulation time 186781147 ps
CPU time 0.8 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 206596 kb
Host smart-7f226a87-c16e-4f8a-a07f-f79f50c05479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12564
17527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1256417527
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1494702566
Short name T1608
Test name
Test status
Simulation time 151651574 ps
CPU time 0.71 seconds
Started Jul 18 05:43:39 PM PDT 24
Finished Jul 18 05:43:55 PM PDT 24
Peak memory 206604 kb
Host smart-a1c6d0d9-cd3a-4273-98c3-16565b4c6479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14947
02566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1494702566
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.639473879
Short name T1457
Test name
Test status
Simulation time 72429302 ps
CPU time 0.69 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 206648 kb
Host smart-aff8d29d-77aa-43ac-a8e1-fb63edf1f953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63947
3879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.639473879
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.3059435973
Short name T257
Test name
Test status
Simulation time 21095940920 ps
CPU time 47.82 seconds
Started Jul 18 05:43:43 PM PDT 24
Finished Jul 18 05:44:48 PM PDT 24
Peak memory 206944 kb
Host smart-771892f5-6f7f-423c-9d2c-f0690de56168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30594
35973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.3059435973
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3571815169
Short name T2422
Test name
Test status
Simulation time 198633845 ps
CPU time 0.86 seconds
Started Jul 18 05:43:39 PM PDT 24
Finished Jul 18 05:43:55 PM PDT 24
Peak memory 206652 kb
Host smart-da530e3d-360c-4483-8524-dc4011dc513c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35718
15169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3571815169
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1236130468
Short name T146
Test name
Test status
Simulation time 179124875 ps
CPU time 0.8 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:58 PM PDT 24
Peak memory 206644 kb
Host smart-3a285ef6-2db7-4935-acc2-30f994d2c8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12361
30468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1236130468
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.3393327186
Short name T1137
Test name
Test status
Simulation time 4992704045 ps
CPU time 33.75 seconds
Started Jul 18 05:43:37 PM PDT 24
Finished Jul 18 05:44:26 PM PDT 24
Peak memory 206940 kb
Host smart-30f03ba1-139e-453a-acfb-80013edd7cbc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3393327186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.3393327186
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2109268974
Short name T1880
Test name
Test status
Simulation time 14925912505 ps
CPU time 82.77 seconds
Started Jul 18 05:43:38 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206884 kb
Host smart-0f696de0-129b-4963-93a3-b811f9ed89dc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2109268974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2109268974
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.837212737
Short name T2465
Test name
Test status
Simulation time 11138799627 ps
CPU time 51.86 seconds
Started Jul 18 05:43:39 PM PDT 24
Finished Jul 18 05:44:46 PM PDT 24
Peak memory 206880 kb
Host smart-4dcdc6b2-ed78-4a54-a68a-7018096b25d0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=837212737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.837212737
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3786889792
Short name T2528
Test name
Test status
Simulation time 163817413 ps
CPU time 0.73 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:56 PM PDT 24
Peak memory 206612 kb
Host smart-8bd4338d-c83a-4acf-ab64-7de9b1dd0c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37868
89792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3786889792
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.1353923939
Short name T2257
Test name
Test status
Simulation time 177675759 ps
CPU time 0.77 seconds
Started Jul 18 05:43:39 PM PDT 24
Finished Jul 18 05:43:55 PM PDT 24
Peak memory 206592 kb
Host smart-ce94a380-0513-4987-8576-5e8b08b25154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13539
23939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.1353923939
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3818831572
Short name T1266
Test name
Test status
Simulation time 211593119 ps
CPU time 0.75 seconds
Started Jul 18 05:43:40 PM PDT 24
Finished Jul 18 05:43:57 PM PDT 24
Peak memory 206592 kb
Host smart-750930c7-6dd4-4fc8-aae6-7c6fdb58c587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38188
31572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3818831572
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.1483893966
Short name T2023
Test name
Test status
Simulation time 207033937 ps
CPU time 0.79 seconds
Started Jul 18 05:43:38 PM PDT 24
Finished Jul 18 05:43:54 PM PDT 24
Peak memory 206636 kb
Host smart-2b4e2d99-3a6d-4c10-b831-ca3946302efc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14838
93966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.1483893966
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.1200842230
Short name T202
Test name
Test status
Simulation time 292443635 ps
CPU time 1.19 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 224480 kb
Host smart-8f977e72-8a54-4033-aa4e-aebcd11be930
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1200842230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.1200842230
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.769624141
Short name T2497
Test name
Test status
Simulation time 444184591 ps
CPU time 1.27 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206632 kb
Host smart-9aff1c76-2b3a-49cb-ab79-708570ec393e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76962
4141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.769624141
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3982988037
Short name T995
Test name
Test status
Simulation time 296219663 ps
CPU time 1.06 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206652 kb
Host smart-afce9cce-da6c-4e63-a097-f01152af938b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39829
88037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3982988037
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1827272034
Short name T897
Test name
Test status
Simulation time 154906684 ps
CPU time 0.76 seconds
Started Jul 18 05:43:56 PM PDT 24
Finished Jul 18 05:44:10 PM PDT 24
Peak memory 206644 kb
Host smart-51e76314-b579-46a8-ba73-a48b367bf0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18272
72034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1827272034
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.144883958
Short name T2090
Test name
Test status
Simulation time 153417045 ps
CPU time 0.75 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:06 PM PDT 24
Peak memory 206616 kb
Host smart-b3f7daa4-24b1-46a7-a739-c413263be5f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14488
3958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.144883958
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2756856987
Short name T973
Test name
Test status
Simulation time 195665397 ps
CPU time 0.87 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206612 kb
Host smart-111f69f7-0cf9-4919-a6af-be7077ffa3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27568
56987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2756856987
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.2733182696
Short name T2499
Test name
Test status
Simulation time 6419039034 ps
CPU time 177.98 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:47:03 PM PDT 24
Peak memory 206824 kb
Host smart-399fc002-772c-4e7f-9eb6-6af6201bbfea
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2733182696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.2733182696
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1262325186
Short name T1957
Test name
Test status
Simulation time 164771509 ps
CPU time 0.86 seconds
Started Jul 18 05:43:59 PM PDT 24
Finished Jul 18 05:44:11 PM PDT 24
Peak memory 206820 kb
Host smart-c36c7949-84f9-47de-b63e-56825a399f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12623
25186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1262325186
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.587363350
Short name T2178
Test name
Test status
Simulation time 198585953 ps
CPU time 0.85 seconds
Started Jul 18 05:43:59 PM PDT 24
Finished Jul 18 05:44:11 PM PDT 24
Peak memory 206824 kb
Host smart-fadfffd6-862c-42d0-9b3e-8daef0a6e61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58736
3350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.587363350
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.2325357393
Short name T662
Test name
Test status
Simulation time 1033887654 ps
CPU time 2.16 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 206748 kb
Host smart-6dba98f4-f519-47a7-b3da-09365cef64ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23253
57393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.2325357393
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2414857011
Short name T2378
Test name
Test status
Simulation time 7765767386 ps
CPU time 230.07 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206844 kb
Host smart-623cd708-a7af-49d6-87aa-9bf30738b1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24148
57011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2414857011
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.1738746451
Short name T168
Test name
Test status
Simulation time 16975933396 ps
CPU time 365.88 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:50:11 PM PDT 24
Peak memory 207004 kb
Host smart-3106e837-063d-4412-b496-481fe44f675d
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1738746451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.1738746451
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.494514417
Short name T1509
Test name
Test status
Simulation time 34560511 ps
CPU time 0.72 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206688 kb
Host smart-dc689c1c-7f25-4e83-b1e3-2dcf999de8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=494514417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.494514417
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.649320980
Short name T2717
Test name
Test status
Simulation time 3801096855 ps
CPU time 5.56 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:11 PM PDT 24
Peak memory 206796 kb
Host smart-50893010-acad-4840-a215-4ff71137b49e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=649320980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.649320980
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.171506181
Short name T2010
Test name
Test status
Simulation time 13370790375 ps
CPU time 14.62 seconds
Started Jul 18 05:46:59 PM PDT 24
Finished Jul 18 05:47:26 PM PDT 24
Peak memory 206728 kb
Host smart-524051ae-9c5b-4a80-bf0f-68afef96a0b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=171506181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.171506181
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.995889712
Short name T922
Test name
Test status
Simulation time 23359328755 ps
CPU time 23.81 seconds
Started Jul 18 05:46:56 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206784 kb
Host smart-d6a43d53-1713-48c4-92e5-5ed211588ad9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=995889712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.995889712
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.100583249
Short name T1202
Test name
Test status
Simulation time 222368648 ps
CPU time 0.88 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:16 PM PDT 24
Peak memory 206620 kb
Host smart-e60dafe7-e759-4000-80a7-4b1a185283f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10058
3249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.100583249
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1678196756
Short name T2080
Test name
Test status
Simulation time 155478000 ps
CPU time 0.76 seconds
Started Jul 18 05:47:01 PM PDT 24
Finished Jul 18 05:47:16 PM PDT 24
Peak memory 206620 kb
Host smart-7f94076d-19af-4ca0-a956-40c54cc2ce7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16781
96756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1678196756
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3015697365
Short name T1230
Test name
Test status
Simulation time 219784906 ps
CPU time 0.91 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:10 PM PDT 24
Peak memory 206624 kb
Host smart-b232dfab-98b2-4b20-ac30-5a945befec81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30156
97365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3015697365
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.1747693402
Short name T749
Test name
Test status
Simulation time 589594731 ps
CPU time 1.54 seconds
Started Jul 18 05:46:58 PM PDT 24
Finished Jul 18 05:47:09 PM PDT 24
Peak memory 206648 kb
Host smart-76a297ab-2bc7-4eeb-a6da-38d5fd9a3128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17476
93402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.1747693402
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3527104654
Short name T1756
Test name
Test status
Simulation time 22723450827 ps
CPU time 46.22 seconds
Started Jul 18 05:47:00 PM PDT 24
Finished Jul 18 05:47:58 PM PDT 24
Peak memory 206836 kb
Host smart-788d6fc6-273a-4927-9395-4b36f448746b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35271
04654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3527104654
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.492393424
Short name T2204
Test name
Test status
Simulation time 404596526 ps
CPU time 1.22 seconds
Started Jul 18 05:47:08 PM PDT 24
Finished Jul 18 05:47:22 PM PDT 24
Peak memory 206804 kb
Host smart-9eeec791-564f-4d0e-b3e7-c71f35d9e2a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49239
3424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.492393424
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2905535615
Short name T1385
Test name
Test status
Simulation time 148105140 ps
CPU time 0.76 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206612 kb
Host smart-ea4a0621-82ca-4d48-b5cc-65e1d9de0b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29055
35615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2905535615
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1133409344
Short name T939
Test name
Test status
Simulation time 42524252 ps
CPU time 0.66 seconds
Started Jul 18 05:47:14 PM PDT 24
Finished Jul 18 05:47:32 PM PDT 24
Peak memory 206648 kb
Host smart-512977fe-5bf0-45a5-92c6-3f0a84bb6f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11334
09344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1133409344
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.530021386
Short name T1245
Test name
Test status
Simulation time 872239013 ps
CPU time 2.43 seconds
Started Jul 18 05:47:07 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206724 kb
Host smart-50948a61-5d1a-4a00-8e42-d88b153fd12a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53002
1386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.530021386
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1759654261
Short name T2065
Test name
Test status
Simulation time 177491484 ps
CPU time 1.72 seconds
Started Jul 18 05:47:08 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206792 kb
Host smart-94d49258-683d-4290-99eb-e8859b67f2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17596
54261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1759654261
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.2333722869
Short name T1320
Test name
Test status
Simulation time 198349227 ps
CPU time 0.87 seconds
Started Jul 18 05:47:14 PM PDT 24
Finished Jul 18 05:47:31 PM PDT 24
Peak memory 206644 kb
Host smart-c9e414da-8aa3-4ed4-8a49-e4a836392e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23337
22869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.2333722869
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.840024332
Short name T2750
Test name
Test status
Simulation time 145523383 ps
CPU time 0.76 seconds
Started Jul 18 05:47:13 PM PDT 24
Finished Jul 18 05:47:30 PM PDT 24
Peak memory 206552 kb
Host smart-33afb30c-490e-4abd-8caf-06407e67fd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84002
4332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.840024332
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.1219188640
Short name T1099
Test name
Test status
Simulation time 173283540 ps
CPU time 0.9 seconds
Started Jul 18 05:47:08 PM PDT 24
Finished Jul 18 05:47:22 PM PDT 24
Peak memory 206656 kb
Host smart-0916e813-c95e-4f13-b279-f5e87ee18f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
88640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.1219188640
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.802280772
Short name T1906
Test name
Test status
Simulation time 9562988713 ps
CPU time 80.79 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:48:48 PM PDT 24
Peak memory 206832 kb
Host smart-4723d7ce-9cba-4704-a2ad-08ac3e012942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80228
0772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.802280772
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.317105002
Short name T1992
Test name
Test status
Simulation time 214086808 ps
CPU time 0.85 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206172 kb
Host smart-4d47cb2b-6865-49f9-97db-e58322af28b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31710
5002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.317105002
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.1827959012
Short name T738
Test name
Test status
Simulation time 23339998355 ps
CPU time 23.29 seconds
Started Jul 18 05:47:14 PM PDT 24
Finished Jul 18 05:47:54 PM PDT 24
Peak memory 206776 kb
Host smart-0f2b1afc-4486-4088-ab3e-783ccef0a9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18279
59012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.1827959012
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1719534612
Short name T716
Test name
Test status
Simulation time 3327580523 ps
CPU time 4.45 seconds
Started Jul 18 05:47:06 PM PDT 24
Finished Jul 18 05:47:25 PM PDT 24
Peak memory 206720 kb
Host smart-18d83860-cda0-44fc-8f1c-2e45c1d864e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17195
34612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1719534612
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.3684081082
Short name T2238
Test name
Test status
Simulation time 11558446498 ps
CPU time 114.51 seconds
Started Jul 18 05:47:13 PM PDT 24
Finished Jul 18 05:49:24 PM PDT 24
Peak memory 206884 kb
Host smart-3e8f2f27-6bb7-4f51-87de-35813e5c2d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36840
81082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.3684081082
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.247160806
Short name T2054
Test name
Test status
Simulation time 5167405804 ps
CPU time 37.29 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206844 kb
Host smart-ea12c374-03fa-4c7c-a3a7-9394cee7e680
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=247160806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.247160806
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.2957218204
Short name T1185
Test name
Test status
Simulation time 251127593 ps
CPU time 0.98 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206620 kb
Host smart-12992223-7e7f-4354-8c64-320dba7eb301
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2957218204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.2957218204
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.819399957
Short name T921
Test name
Test status
Simulation time 228075117 ps
CPU time 0.91 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 205952 kb
Host smart-ea739c11-8691-4938-a6b9-451aca010c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81939
9957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.819399957
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.379443428
Short name T1048
Test name
Test status
Simulation time 4080512038 ps
CPU time 40.2 seconds
Started Jul 18 05:47:13 PM PDT 24
Finished Jul 18 05:48:10 PM PDT 24
Peak memory 206868 kb
Host smart-e636c5ff-01f2-42e4-bf57-3bfa30310747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37944
3428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.379443428
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1936625973
Short name T1555
Test name
Test status
Simulation time 6138364254 ps
CPU time 55.85 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:48:23 PM PDT 24
Peak memory 206724 kb
Host smart-c03912db-f219-4672-938d-05b5de007db9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1936625973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1936625973
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1853398957
Short name T1040
Test name
Test status
Simulation time 203822972 ps
CPU time 0.88 seconds
Started Jul 18 05:47:14 PM PDT 24
Finished Jul 18 05:47:32 PM PDT 24
Peak memory 206656 kb
Host smart-7b31ed42-8fe9-48bb-81d1-aa6a25922635
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1853398957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1853398957
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.548536587
Short name T1606
Test name
Test status
Simulation time 141449019 ps
CPU time 0.81 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:27 PM PDT 24
Peak memory 206616 kb
Host smart-d827e00c-4344-4ce3-8fa3-992ba60170cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54853
6587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.548536587
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2342792164
Short name T128
Test name
Test status
Simulation time 181512220 ps
CPU time 0.86 seconds
Started Jul 18 05:47:07 PM PDT 24
Finished Jul 18 05:47:22 PM PDT 24
Peak memory 206632 kb
Host smart-fb243f55-6fcd-4910-8dbc-eec807e182d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23427
92164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2342792164
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.2241517969
Short name T1070
Test name
Test status
Simulation time 176558492 ps
CPU time 0.83 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:26 PM PDT 24
Peak memory 206520 kb
Host smart-4fe13a4f-b146-437f-80e0-200806f05f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22415
17969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.2241517969
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4056735976
Short name T778
Test name
Test status
Simulation time 161399499 ps
CPU time 0.84 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:24 PM PDT 24
Peak memory 206616 kb
Host smart-ce2eb782-487d-489c-889c-44848071cfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40567
35976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4056735976
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.2717870531
Short name T1824
Test name
Test status
Simulation time 152113581 ps
CPU time 0.77 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:27 PM PDT 24
Peak memory 206624 kb
Host smart-56a309da-9227-46d0-a87e-0aeb6054c2c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27178
70531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.2717870531
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3664825090
Short name T549
Test name
Test status
Simulation time 152484969 ps
CPU time 0.82 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206504 kb
Host smart-a0bc0495-f2e1-497e-a69a-2611386bf094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36648
25090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3664825090
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.525351096
Short name T2476
Test name
Test status
Simulation time 243664315 ps
CPU time 1.08 seconds
Started Jul 18 05:47:08 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206652 kb
Host smart-d721f2df-93c9-403f-8065-c5b60cf74d8b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=525351096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.525351096
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.4062015796
Short name T1022
Test name
Test status
Simulation time 162685480 ps
CPU time 0.81 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:27 PM PDT 24
Peak memory 206648 kb
Host smart-b4926d27-e46b-4d48-a1f3-891494bf87aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40620
15796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.4062015796
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.3216158032
Short name T1598
Test name
Test status
Simulation time 88785942 ps
CPU time 0.68 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206648 kb
Host smart-52b2bb94-b9d3-435a-8cd6-ffc8b592d33a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32161
58032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.3216158032
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3402117789
Short name T1591
Test name
Test status
Simulation time 10486843716 ps
CPU time 26.82 seconds
Started Jul 18 05:47:09 PM PDT 24
Finished Jul 18 05:47:49 PM PDT 24
Peak memory 207112 kb
Host smart-b0aa4bae-1200-4452-b8a3-cb576203e6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34021
17789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3402117789
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.2537047186
Short name T1191
Test name
Test status
Simulation time 190033842 ps
CPU time 0.85 seconds
Started Jul 18 05:47:13 PM PDT 24
Finished Jul 18 05:47:30 PM PDT 24
Peak memory 206616 kb
Host smart-662228ab-55b8-466d-9761-ed6ce1123579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25370
47186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.2537047186
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3505781133
Short name T1496
Test name
Test status
Simulation time 233374573 ps
CPU time 0.89 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206660 kb
Host smart-deb3b478-bc24-4970-973c-e98c543130df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35057
81133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3505781133
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3514935210
Short name T2357
Test name
Test status
Simulation time 259162190 ps
CPU time 0.94 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206016 kb
Host smart-6ec83112-adf2-44d1-b902-0176c20f8e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35149
35210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3514935210
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2622525611
Short name T1991
Test name
Test status
Simulation time 166576598 ps
CPU time 0.86 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:26 PM PDT 24
Peak memory 206576 kb
Host smart-fe028832-94c4-4350-b03f-3344ff77b751
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26225
25611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2622525611
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.2058918376
Short name T2085
Test name
Test status
Simulation time 221856737 ps
CPU time 0.83 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:26 PM PDT 24
Peak memory 206604 kb
Host smart-127a8156-abda-44fc-86f3-976b579036e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20589
18376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.2058918376
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2021205544
Short name T1908
Test name
Test status
Simulation time 146026520 ps
CPU time 0.76 seconds
Started Jul 18 05:47:17 PM PDT 24
Finished Jul 18 05:47:35 PM PDT 24
Peak memory 206420 kb
Host smart-1efefbfd-bb88-4394-91cd-03f5027b09d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20212
05544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2021205544
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.2374644325
Short name T809
Test name
Test status
Simulation time 154664091 ps
CPU time 0.81 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:25 PM PDT 24
Peak memory 206616 kb
Host smart-6fd39ffd-090a-413d-9cac-d320128cef73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23746
44325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.2374644325
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.365412397
Short name T1812
Test name
Test status
Simulation time 239828653 ps
CPU time 1.01 seconds
Started Jul 18 05:47:13 PM PDT 24
Finished Jul 18 05:47:30 PM PDT 24
Peak memory 206556 kb
Host smart-972bc5a1-64b6-4a7b-ab00-db62024bbdb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36541
2397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.365412397
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.876983498
Short name T1829
Test name
Test status
Simulation time 5899120358 ps
CPU time 162.59 seconds
Started Jul 18 05:47:16 PM PDT 24
Finished Jul 18 05:50:16 PM PDT 24
Peak memory 206824 kb
Host smart-4829518b-062b-48c4-b884-e17acb361e8a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=876983498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.876983498
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.4110633431
Short name T1550
Test name
Test status
Simulation time 218891199 ps
CPU time 0.82 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:26 PM PDT 24
Peak memory 206648 kb
Host smart-0d7261f7-0c3e-4c81-8c08-7d1a02b8e53a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41106
33431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.4110633431
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.3923711571
Short name T1382
Test name
Test status
Simulation time 149953251 ps
CPU time 0.76 seconds
Started Jul 18 05:47:17 PM PDT 24
Finished Jul 18 05:47:35 PM PDT 24
Peak memory 206396 kb
Host smart-f63738b3-bc84-4e45-8ebb-2f8a4b91d9d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39237
11571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.3923711571
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.3155419265
Short name T1463
Test name
Test status
Simulation time 454838554 ps
CPU time 1.21 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206372 kb
Host smart-6e484912-a622-4e06-ace0-2d6b7623456c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31554
19265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.3155419265
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.2765117024
Short name T1292
Test name
Test status
Simulation time 3615339598 ps
CPU time 24.63 seconds
Started Jul 18 05:47:13 PM PDT 24
Finished Jul 18 05:47:54 PM PDT 24
Peak memory 206880 kb
Host smart-8327ca96-a8f0-44e4-90a5-dd467b242dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27651
17024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.2765117024
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.2786789980
Short name T1277
Test name
Test status
Simulation time 35410144 ps
CPU time 0.68 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206672 kb
Host smart-b8ad4773-d5a0-4b9a-848c-c82da4351e3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2786789980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.2786789980
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2618935630
Short name T802
Test name
Test status
Simulation time 4310323092 ps
CPU time 4.67 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206892 kb
Host smart-eb905e6b-f671-4578-8f55-aa1de00e6d41
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2618935630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2618935630
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.214717910
Short name T2636
Test name
Test status
Simulation time 13316931773 ps
CPU time 12.48 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:39 PM PDT 24
Peak memory 206888 kb
Host smart-4b347c3f-06d6-46a9-a28e-ade6c791d245
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=214717910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.214717910
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.4153777924
Short name T890
Test name
Test status
Simulation time 23333519790 ps
CPU time 22.04 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:48 PM PDT 24
Peak memory 206864 kb
Host smart-89035903-ad86-4bef-8f98-f28444296a1f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4153777924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.4153777924
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.760129983
Short name T1868
Test name
Test status
Simulation time 162699256 ps
CPU time 0.8 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206644 kb
Host smart-6dc7f9ad-1f11-4b64-b8e3-6c1e7003e942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76012
9983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.760129983
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2812111878
Short name T728
Test name
Test status
Simulation time 180904323 ps
CPU time 0.81 seconds
Started Jul 18 05:47:14 PM PDT 24
Finished Jul 18 05:47:32 PM PDT 24
Peak memory 206668 kb
Host smart-f6905be6-f8ae-4831-86ef-043ab849abf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28121
11878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2812111878
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.1782487146
Short name T1368
Test name
Test status
Simulation time 431836784 ps
CPU time 1.34 seconds
Started Jul 18 05:47:17 PM PDT 24
Finished Jul 18 05:47:35 PM PDT 24
Peak memory 206500 kb
Host smart-2d38649b-362c-47f5-845a-332e7eb11cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17824
87146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.1782487146
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3371503501
Short name T1383
Test name
Test status
Simulation time 784748685 ps
CPU time 1.85 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:27 PM PDT 24
Peak memory 206796 kb
Host smart-3112e1f3-b1ee-4f8b-b3ac-de37e689b9d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33715
03501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3371503501
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.2678789166
Short name T1604
Test name
Test status
Simulation time 16829059178 ps
CPU time 32.97 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:58 PM PDT 24
Peak memory 206880 kb
Host smart-2bd87d8a-2e1f-496a-996b-c6489be7fc7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26787
89166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.2678789166
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.2311556361
Short name T2374
Test name
Test status
Simulation time 443938813 ps
CPU time 1.4 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206652 kb
Host smart-4d76906c-5c91-4619-9c04-914017c1a9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23115
56361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.2311556361
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.1493117396
Short name T1924
Test name
Test status
Simulation time 179498370 ps
CPU time 0.79 seconds
Started Jul 18 05:47:16 PM PDT 24
Finished Jul 18 05:47:34 PM PDT 24
Peak memory 206660 kb
Host smart-5523e957-b7c4-4cab-9e50-831a1a70fc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931
17396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.1493117396
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2608532298
Short name T2258
Test name
Test status
Simulation time 40074312 ps
CPU time 0.65 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:27 PM PDT 24
Peak memory 206644 kb
Host smart-67b2bd02-311e-402d-91f5-f3803406b2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26085
32298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2608532298
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.1257477096
Short name T2356
Test name
Test status
Simulation time 1041115290 ps
CPU time 2.31 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:30 PM PDT 24
Peak memory 206772 kb
Host smart-4bbe6e7d-c58e-44fd-a533-c71b0ee25816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12574
77096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.1257477096
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3499748952
Short name T2670
Test name
Test status
Simulation time 180633154 ps
CPU time 1.63 seconds
Started Jul 18 05:47:14 PM PDT 24
Finished Jul 18 05:47:33 PM PDT 24
Peak memory 206800 kb
Host smart-94276375-e43b-4c46-8224-4f73b5e3fcba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34997
48952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3499748952
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.1054249604
Short name T205
Test name
Test status
Simulation time 215424174 ps
CPU time 0.93 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206288 kb
Host smart-a3595c76-7b4f-48b0-b121-4169baafab9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10542
49604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.1054249604
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.708278111
Short name T1141
Test name
Test status
Simulation time 164237837 ps
CPU time 0.78 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206632 kb
Host smart-b4096aa1-bf24-40e4-8edc-24cd71bbc029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70827
8111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.708278111
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1277747071
Short name T1032
Test name
Test status
Simulation time 172802313 ps
CPU time 0.87 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206412 kb
Host smart-d7cd4abd-bcf4-4c7a-93a5-28349b4bfc1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12777
47071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1277747071
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.1181037121
Short name T2674
Test name
Test status
Simulation time 4961017028 ps
CPU time 19 seconds
Started Jul 18 05:47:28 PM PDT 24
Finished Jul 18 05:48:03 PM PDT 24
Peak memory 206896 kb
Host smart-73fab772-f400-45c0-b23f-79b4365c1664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11810
37121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.1181037121
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3750756310
Short name T1358
Test name
Test status
Simulation time 162085359 ps
CPU time 0.78 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206636 kb
Host smart-86985b41-2145-49b0-982d-1afd6233d056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37507
56310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3750756310
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.3044160508
Short name T2203
Test name
Test status
Simulation time 23336639243 ps
CPU time 23.21 seconds
Started Jul 18 05:47:21 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206772 kb
Host smart-b94e43a4-274a-421c-80a9-7e1e02d5ddc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30441
60508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.3044160508
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1238104785
Short name T1086
Test name
Test status
Simulation time 3277633623 ps
CPU time 4.49 seconds
Started Jul 18 05:47:22 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206716 kb
Host smart-1f7fbc18-aa3a-44aa-9bf5-a424945b1ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12381
04785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1238104785
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1525961107
Short name T2571
Test name
Test status
Simulation time 7156605875 ps
CPU time 199.05 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:50:57 PM PDT 24
Peak memory 206892 kb
Host smart-bf7f7b08-5107-4c6b-a773-94f05b349ae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15259
61107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1525961107
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.2461883400
Short name T1416
Test name
Test status
Simulation time 4025947728 ps
CPU time 112.13 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:49:29 PM PDT 24
Peak memory 206808 kb
Host smart-f1750b37-d72b-4d46-bf31-c9d7fd911d0d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2461883400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.2461883400
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3833022851
Short name T1532
Test name
Test status
Simulation time 268005559 ps
CPU time 0.96 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:47:38 PM PDT 24
Peak memory 206616 kb
Host smart-5f680f1a-bd27-4bc8-8489-63d434d8ca98
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3833022851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3833022851
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.2315621702
Short name T2109
Test name
Test status
Simulation time 256569752 ps
CPU time 0.94 seconds
Started Jul 18 05:47:20 PM PDT 24
Finished Jul 18 05:47:39 PM PDT 24
Peak memory 206612 kb
Host smart-614b4c29-03b6-4a6c-96dd-c5243860e9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23156
21702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.2315621702
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.1166511911
Short name T403
Test name
Test status
Simulation time 6725394943 ps
CPU time 49.45 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:48:25 PM PDT 24
Peak memory 206848 kb
Host smart-5a42d183-16c5-453d-b584-d098d2139992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11665
11911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.1166511911
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.2976147029
Short name T1274
Test name
Test status
Simulation time 3714430224 ps
CPU time 36.16 seconds
Started Jul 18 05:47:22 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206844 kb
Host smart-ec54b1a5-89e7-4c70-b34b-0e24f2f4d1ad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2976147029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.2976147029
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3491305909
Short name T510
Test name
Test status
Simulation time 153495004 ps
CPU time 0.81 seconds
Started Jul 18 05:47:21 PM PDT 24
Finished Jul 18 05:47:41 PM PDT 24
Peak memory 206640 kb
Host smart-a2cda8b6-efdd-427b-a349-76909905ef2d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3491305909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3491305909
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.3278611697
Short name T2083
Test name
Test status
Simulation time 143832791 ps
CPU time 0.79 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:47:37 PM PDT 24
Peak memory 206640 kb
Host smart-2f46609d-6d16-4cbf-8612-2d98835048a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32786
11697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.3278611697
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.3811542662
Short name T1359
Test name
Test status
Simulation time 191447412 ps
CPU time 0.82 seconds
Started Jul 18 05:47:09 PM PDT 24
Finished Jul 18 05:47:24 PM PDT 24
Peak memory 206620 kb
Host smart-371eed76-a893-4bd3-8c04-637d16b011bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38115
42662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.3811542662
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2906394888
Short name T2732
Test name
Test status
Simulation time 149338931 ps
CPU time 0.84 seconds
Started Jul 18 05:47:23 PM PDT 24
Finished Jul 18 05:47:43 PM PDT 24
Peak memory 206644 kb
Host smart-8dac8323-a7a3-4f58-ad82-34f1f7b0b064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29063
94888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2906394888
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1486211907
Short name T2237
Test name
Test status
Simulation time 200272067 ps
CPU time 0.77 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:47:37 PM PDT 24
Peak memory 206636 kb
Host smart-b791ab46-0cfc-45da-bba8-e236fcf863e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14862
11907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1486211907
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1851483423
Short name T1289
Test name
Test status
Simulation time 196487780 ps
CPU time 0.78 seconds
Started Jul 18 05:47:09 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206632 kb
Host smart-c04a0475-248a-44a2-8406-c9748f929e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18514
83423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1851483423
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2866014586
Short name T448
Test name
Test status
Simulation time 168960246 ps
CPU time 0.83 seconds
Started Jul 18 05:47:20 PM PDT 24
Finished Jul 18 05:47:39 PM PDT 24
Peak memory 206616 kb
Host smart-18f3603d-ff55-4b60-9dc3-4fbc771f17e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28660
14586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2866014586
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.4213356032
Short name T1558
Test name
Test status
Simulation time 283317612 ps
CPU time 1.01 seconds
Started Jul 18 05:47:23 PM PDT 24
Finished Jul 18 05:47:43 PM PDT 24
Peak memory 206640 kb
Host smart-a94267a2-a1fd-4ee6-ae94-8fae3ac53344
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4213356032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.4213356032
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.525238138
Short name T1787
Test name
Test status
Simulation time 137523392 ps
CPU time 0.8 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:25 PM PDT 24
Peak memory 206644 kb
Host smart-8e37474a-be84-4cbd-95b4-c54f4f479a7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52523
8138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.525238138
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.598292140
Short name T845
Test name
Test status
Simulation time 41046254 ps
CPU time 0.67 seconds
Started Jul 18 05:47:20 PM PDT 24
Finished Jul 18 05:47:39 PM PDT 24
Peak memory 206492 kb
Host smart-ec9cc9c8-e42f-4d6f-a507-70dfa6d39ec4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59829
2140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.598292140
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2472201654
Short name T2290
Test name
Test status
Simulation time 12632590462 ps
CPU time 29.14 seconds
Started Jul 18 05:47:20 PM PDT 24
Finished Jul 18 05:48:07 PM PDT 24
Peak memory 206936 kb
Host smart-a200d30b-af24-4f3b-97dd-9b48edc0b9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24722
01654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2472201654
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.3019424707
Short name T1344
Test name
Test status
Simulation time 187403394 ps
CPU time 0.88 seconds
Started Jul 18 05:47:21 PM PDT 24
Finished Jul 18 05:47:41 PM PDT 24
Peak memory 206652 kb
Host smart-c58223d3-d35a-465f-a16e-49f214900ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30194
24707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.3019424707
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1411038692
Short name T985
Test name
Test status
Simulation time 167735120 ps
CPU time 0.82 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:37 PM PDT 24
Peak memory 206636 kb
Host smart-d6ec648a-9f3f-4ce6-bf43-5d0dfaaddece
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14110
38692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1411038692
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.143116105
Short name T2741
Test name
Test status
Simulation time 235868497 ps
CPU time 0.89 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206652 kb
Host smart-745cdc6d-b6c7-44cd-94ba-83b80bab220d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14311
6105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.143116105
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3524887732
Short name T1572
Test name
Test status
Simulation time 188952921 ps
CPU time 0.81 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206636 kb
Host smart-19cd056f-2848-441e-b78d-c718fc756ba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35248
87732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3524887732
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1106414293
Short name T2513
Test name
Test status
Simulation time 200247095 ps
CPU time 0.81 seconds
Started Jul 18 05:47:09 PM PDT 24
Finished Jul 18 05:47:23 PM PDT 24
Peak memory 206632 kb
Host smart-d421b0ee-18cd-493b-895b-bc9f026fd724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11064
14293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1106414293
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2825917033
Short name T2254
Test name
Test status
Simulation time 152949052 ps
CPU time 0.77 seconds
Started Jul 18 05:47:16 PM PDT 24
Finished Jul 18 05:47:34 PM PDT 24
Peak memory 206476 kb
Host smart-0a515226-835c-42d8-8e68-aa3898d1d121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28259
17033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2825917033
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.3419969438
Short name T1494
Test name
Test status
Simulation time 154030276 ps
CPU time 0.77 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:47:37 PM PDT 24
Peak memory 206640 kb
Host smart-a87228b5-cce0-4188-8e56-21a165ee42e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34199
69438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.3419969438
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1009119884
Short name T2507
Test name
Test status
Simulation time 292057660 ps
CPU time 1.01 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:47:38 PM PDT 24
Peak memory 206640 kb
Host smart-d53aa443-8bb1-40b6-8419-4e72149ce121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10091
19884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1009119884
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3570987834
Short name T1741
Test name
Test status
Simulation time 5716774715 ps
CPU time 152.96 seconds
Started Jul 18 05:47:17 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206844 kb
Host smart-fb557596-d507-4962-83f8-b992f4091a47
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3570987834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3570987834
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.392503041
Short name T2423
Test name
Test status
Simulation time 166295426 ps
CPU time 0.79 seconds
Started Jul 18 05:47:13 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206644 kb
Host smart-d6c86581-db9a-41cb-9bed-93196c842afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39250
3041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.392503041
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.243481626
Short name T399
Test name
Test status
Simulation time 159285891 ps
CPU time 0.78 seconds
Started Jul 18 05:47:20 PM PDT 24
Finished Jul 18 05:47:39 PM PDT 24
Peak memory 206488 kb
Host smart-c9d84298-fade-46c2-9dc7-c59eea62dba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24348
1626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.243481626
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3812051669
Short name T545
Test name
Test status
Simulation time 748456540 ps
CPU time 1.89 seconds
Started Jul 18 05:47:20 PM PDT 24
Finished Jul 18 05:47:40 PM PDT 24
Peak memory 206772 kb
Host smart-36c1617d-9384-40ec-ade5-e78802800c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38120
51669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3812051669
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.344451291
Short name T84
Test name
Test status
Simulation time 3891312060 ps
CPU time 108.48 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:49:15 PM PDT 24
Peak memory 206880 kb
Host smart-781da6a5-bc1e-4b4b-b1d4-08d793b1adda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34445
1291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.344451291
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.2697670372
Short name T2046
Test name
Test status
Simulation time 63294174 ps
CPU time 0.65 seconds
Started Jul 18 05:47:44 PM PDT 24
Finished Jul 18 05:47:51 PM PDT 24
Peak memory 206644 kb
Host smart-88c5dfe2-cd3c-4104-baf1-f9d01042df3a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2697670372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.2697670372
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.676988142
Short name T2696
Test name
Test status
Simulation time 3453330615 ps
CPU time 4.55 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206656 kb
Host smart-ab2877e6-20b9-4d51-8e40-8bda4cade6f6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=676988142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.676988142
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.4277719822
Short name T1911
Test name
Test status
Simulation time 13455728593 ps
CPU time 15.03 seconds
Started Jul 18 05:47:16 PM PDT 24
Finished Jul 18 05:47:49 PM PDT 24
Peak memory 206924 kb
Host smart-0874a85d-325f-40c8-8d0d-b05f5b7f0359
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4277719822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.4277719822
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.342538193
Short name T585
Test name
Test status
Simulation time 23422707008 ps
CPU time 23.37 seconds
Started Jul 18 05:47:15 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206892 kb
Host smart-97187ddc-6b8c-434f-9d07-260db4b74202
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=342538193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.342538193
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.805188302
Short name T667
Test name
Test status
Simulation time 158054033 ps
CPU time 0.79 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:25 PM PDT 24
Peak memory 206668 kb
Host smart-1ab06309-1467-4b7c-adc0-a2523b4dab43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80518
8302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.805188302
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.2126166919
Short name T61
Test name
Test status
Simulation time 142966308 ps
CPU time 0.78 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206632 kb
Host smart-a0802219-cfb0-421c-9f09-2d25e530d7ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21261
66919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.2126166919
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.859564460
Short name T112
Test name
Test status
Simulation time 345884020 ps
CPU time 1.43 seconds
Started Jul 18 05:47:10 PM PDT 24
Finished Jul 18 05:47:25 PM PDT 24
Peak memory 206668 kb
Host smart-bd38ea5a-f087-41af-b8f3-fc91c329fe38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85956
4460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.859564460
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1251146656
Short name T2147
Test name
Test status
Simulation time 643239018 ps
CPU time 1.55 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206660 kb
Host smart-25d1fae3-d8d8-42a9-a5fb-85438c96b328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12511
46656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1251146656
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2164877074
Short name T980
Test name
Test status
Simulation time 6170576226 ps
CPU time 11.47 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:39 PM PDT 24
Peak memory 206844 kb
Host smart-d8e9510f-15c3-40b9-8e0e-859728446eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21648
77074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2164877074
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.1348364376
Short name T2028
Test name
Test status
Simulation time 448413333 ps
CPU time 1.28 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206652 kb
Host smart-56845e02-34bb-4440-97e7-5136b809e905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13483
64376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.1348364376
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.2990149353
Short name T2480
Test name
Test status
Simulation time 138652580 ps
CPU time 0.78 seconds
Started Jul 18 05:47:16 PM PDT 24
Finished Jul 18 05:47:34 PM PDT 24
Peak memory 206640 kb
Host smart-ae01fd82-3206-489d-8ad1-33780f40f028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29901
49353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.2990149353
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.1670736684
Short name T2030
Test name
Test status
Simulation time 30855747 ps
CPU time 0.64 seconds
Started Jul 18 05:47:12 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206624 kb
Host smart-8a70a5e2-94ac-4d46-b7f3-fe956c85e696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16707
36684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.1670736684
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3580990035
Short name T1298
Test name
Test status
Simulation time 1072486317 ps
CPU time 2.31 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:29 PM PDT 24
Peak memory 206760 kb
Host smart-64979151-936a-42ce-b4c6-27f4c3952b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
90035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3580990035
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.3427944706
Short name T460
Test name
Test status
Simulation time 228475749 ps
CPU time 1.38 seconds
Started Jul 18 05:47:11 PM PDT 24
Finished Jul 18 05:47:28 PM PDT 24
Peak memory 206724 kb
Host smart-dc5d74d2-96c1-49e4-999f-3cc4f59266de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34279
44706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.3427944706
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2976422316
Short name T776
Test name
Test status
Simulation time 196470493 ps
CPU time 0.87 seconds
Started Jul 18 05:47:18 PM PDT 24
Finished Jul 18 05:47:36 PM PDT 24
Peak memory 206640 kb
Host smart-12a0a57a-f50e-4b4a-a724-70f5b90ee775
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29764
22316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2976422316
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2005472006
Short name T2478
Test name
Test status
Simulation time 144563828 ps
CPU time 0.81 seconds
Started Jul 18 05:47:19 PM PDT 24
Finished Jul 18 05:47:38 PM PDT 24
Peak memory 206612 kb
Host smart-8cfc5208-5b97-4f3e-a0c3-53bf114a49fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20054
72006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2005472006
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.2225963883
Short name T1180
Test name
Test status
Simulation time 177911500 ps
CPU time 0.83 seconds
Started Jul 18 05:47:21 PM PDT 24
Finished Jul 18 05:47:41 PM PDT 24
Peak memory 206652 kb
Host smart-e62f734a-0a7c-4ebe-b1c0-d6e0cd6c271c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22259
63883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.2225963883
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.242586891
Short name T2490
Test name
Test status
Simulation time 4710887539 ps
CPU time 124.59 seconds
Started Jul 18 05:47:21 PM PDT 24
Finished Jul 18 05:49:45 PM PDT 24
Peak memory 206892 kb
Host smart-51d479d4-83e9-4370-9d75-e5d917651942
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=242586891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.242586891
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.572420274
Short name T1421
Test name
Test status
Simulation time 13532684861 ps
CPU time 112.1 seconds
Started Jul 18 05:47:31 PM PDT 24
Finished Jul 18 05:49:38 PM PDT 24
Peak memory 206840 kb
Host smart-419a3184-026c-4caf-8b1e-6df709f08e3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57242
0274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.572420274
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3491801966
Short name T1177
Test name
Test status
Simulation time 206198090 ps
CPU time 0.87 seconds
Started Jul 18 05:47:29 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206472 kb
Host smart-f356029d-2fc7-40af-8efd-951647136b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34918
01966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3491801966
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3332054761
Short name T1200
Test name
Test status
Simulation time 23338194912 ps
CPU time 22.78 seconds
Started Jul 18 05:47:34 PM PDT 24
Finished Jul 18 05:48:10 PM PDT 24
Peak memory 206760 kb
Host smart-adc23bb3-5807-4586-90ad-84f2bb5cdde7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33320
54761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3332054761
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.4293642090
Short name T2690
Test name
Test status
Simulation time 3279976771 ps
CPU time 4.17 seconds
Started Jul 18 05:47:24 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206716 kb
Host smart-659ddc35-f785-47bd-8e32-2f80aaf35cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
42090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.4293642090
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.2455713251
Short name T675
Test name
Test status
Simulation time 5348895911 ps
CPU time 149.11 seconds
Started Jul 18 05:47:28 PM PDT 24
Finished Jul 18 05:50:14 PM PDT 24
Peak memory 206840 kb
Host smart-92d73106-c43f-4723-9176-debd3dcfaca0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2455713251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.2455713251
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2615042967
Short name T2294
Test name
Test status
Simulation time 235755347 ps
CPU time 0.89 seconds
Started Jul 18 05:47:24 PM PDT 24
Finished Jul 18 05:47:43 PM PDT 24
Peak memory 206652 kb
Host smart-c45346e0-1b52-4eae-b3e0-d2fa058f7786
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2615042967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2615042967
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.925158135
Short name T2156
Test name
Test status
Simulation time 218202387 ps
CPU time 0.93 seconds
Started Jul 18 05:47:28 PM PDT 24
Finished Jul 18 05:47:45 PM PDT 24
Peak memory 206648 kb
Host smart-7bdd2f93-19ab-42be-a63f-689b3eb369ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92515
8135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.925158135
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2793576002
Short name T1376
Test name
Test status
Simulation time 3404598599 ps
CPU time 97.82 seconds
Started Jul 18 05:47:32 PM PDT 24
Finished Jul 18 05:49:24 PM PDT 24
Peak memory 206892 kb
Host smart-50e62203-76b0-48a2-bab2-c85566da1b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27935
76002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2793576002
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1951909460
Short name T2251
Test name
Test status
Simulation time 7560750880 ps
CPU time 208.12 seconds
Started Jul 18 05:47:25 PM PDT 24
Finished Jul 18 05:51:11 PM PDT 24
Peak memory 206848 kb
Host smart-b5abe0a6-f5bf-4ceb-9465-d5d55977e718
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1951909460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1951909460
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1696716108
Short name T805
Test name
Test status
Simulation time 156444785 ps
CPU time 0.84 seconds
Started Jul 18 05:47:29 PM PDT 24
Finished Jul 18 05:47:45 PM PDT 24
Peak memory 206660 kb
Host smart-2ea14032-6189-4855-bb22-2c17c5a5549d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1696716108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1696716108
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2437909304
Short name T228
Test name
Test status
Simulation time 136304085 ps
CPU time 0.81 seconds
Started Jul 18 05:47:27 PM PDT 24
Finished Jul 18 05:47:44 PM PDT 24
Peak memory 206624 kb
Host smart-a1276d75-ad91-4964-bdaf-5a9fe6a9a6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24379
09304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2437909304
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.145278718
Short name T2142
Test name
Test status
Simulation time 226604973 ps
CPU time 0.88 seconds
Started Jul 18 05:47:27 PM PDT 24
Finished Jul 18 05:47:44 PM PDT 24
Peak memory 206628 kb
Host smart-8739bbcc-4afa-45e9-8f25-0da6f79a7135
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14527
8718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.145278718
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.2707734996
Short name T637
Test name
Test status
Simulation time 184504752 ps
CPU time 0.84 seconds
Started Jul 18 05:47:31 PM PDT 24
Finished Jul 18 05:47:47 PM PDT 24
Peak memory 206620 kb
Host smart-f830ec2d-c3a8-4d62-9421-a71159764c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077
34996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.2707734996
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2914864361
Short name T484
Test name
Test status
Simulation time 185669594 ps
CPU time 0.82 seconds
Started Jul 18 05:47:33 PM PDT 24
Finished Jul 18 05:47:47 PM PDT 24
Peak memory 206644 kb
Host smart-1294b263-d125-48b6-be45-e5421c19ebae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29148
64361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2914864361
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.818419042
Short name T1943
Test name
Test status
Simulation time 204555180 ps
CPU time 0.88 seconds
Started Jul 18 05:47:27 PM PDT 24
Finished Jul 18 05:47:45 PM PDT 24
Peak memory 206620 kb
Host smart-dd93f4e2-1c05-41a4-aae7-b9979bf1fc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81841
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.818419042
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.1450928505
Short name T1072
Test name
Test status
Simulation time 182622230 ps
CPU time 0.88 seconds
Started Jul 18 05:47:24 PM PDT 24
Finished Jul 18 05:47:43 PM PDT 24
Peak memory 206652 kb
Host smart-e4f7ec56-20f1-4704-86a2-c3e6dba4569d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14509
28505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.1450928505
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.283894980
Short name T1841
Test name
Test status
Simulation time 261531751 ps
CPU time 0.99 seconds
Started Jul 18 05:47:29 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206640 kb
Host smart-850b1071-9b7a-4cc3-957d-6a489a4ca103
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=283894980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.283894980
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.228831874
Short name T2228
Test name
Test status
Simulation time 170399989 ps
CPU time 0.79 seconds
Started Jul 18 05:47:30 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206632 kb
Host smart-46fcf822-d135-4b01-9a80-a72433753629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22883
1874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.228831874
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3269705926
Short name T744
Test name
Test status
Simulation time 82617366 ps
CPU time 0.73 seconds
Started Jul 18 05:47:30 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206636 kb
Host smart-c84adde4-a889-4115-940b-070d4f434099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32697
05926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3269705926
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.2641997838
Short name T255
Test name
Test status
Simulation time 13204977715 ps
CPU time 31.79 seconds
Started Jul 18 05:47:27 PM PDT 24
Finished Jul 18 05:48:15 PM PDT 24
Peak memory 206924 kb
Host smart-a4128623-c381-4093-baca-dccc472aee1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26419
97838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.2641997838
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.205347878
Short name T740
Test name
Test status
Simulation time 143984992 ps
CPU time 0.78 seconds
Started Jul 18 05:47:29 PM PDT 24
Finished Jul 18 05:47:45 PM PDT 24
Peak memory 206672 kb
Host smart-55a79059-0ffe-4eba-81a6-378caeea44d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20534
7878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.205347878
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.3039965498
Short name T1110
Test name
Test status
Simulation time 235398051 ps
CPU time 0.87 seconds
Started Jul 18 05:47:25 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206668 kb
Host smart-aa10b7ee-ddd3-43c3-b42a-62911af787a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30399
65498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.3039965498
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.529141218
Short name T2748
Test name
Test status
Simulation time 181042266 ps
CPU time 0.89 seconds
Started Jul 18 05:47:27 PM PDT 24
Finished Jul 18 05:47:44 PM PDT 24
Peak memory 206636 kb
Host smart-2d226ff7-f773-4cfb-8b00-db5baa34d845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52914
1218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.529141218
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2678966251
Short name T1628
Test name
Test status
Simulation time 235465305 ps
CPU time 0.87 seconds
Started Jul 18 05:47:30 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206636 kb
Host smart-b2e0a752-5835-4b7a-90ff-af667e63ef43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26789
66251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2678966251
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.346946364
Short name T1214
Test name
Test status
Simulation time 223513143 ps
CPU time 0.86 seconds
Started Jul 18 05:47:26 PM PDT 24
Finished Jul 18 05:47:44 PM PDT 24
Peak memory 206656 kb
Host smart-605ed3c7-59be-40fd-ae90-e4b44645cc0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34694
6364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.346946364
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.506160630
Short name T616
Test name
Test status
Simulation time 161686213 ps
CPU time 0.78 seconds
Started Jul 18 05:47:29 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206472 kb
Host smart-2561d223-2295-429f-a2ad-c3920d8a0a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50616
0630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.506160630
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.4278692018
Short name T2669
Test name
Test status
Simulation time 204415546 ps
CPU time 0.87 seconds
Started Jul 18 05:47:24 PM PDT 24
Finished Jul 18 05:47:43 PM PDT 24
Peak memory 206616 kb
Host smart-733a63b2-0ee2-4ac9-9b2e-248538619895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42786
92018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.4278692018
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.791648062
Short name T2182
Test name
Test status
Simulation time 229029777 ps
CPU time 0.96 seconds
Started Jul 18 05:47:28 PM PDT 24
Finished Jul 18 05:47:45 PM PDT 24
Peak memory 206644 kb
Host smart-e6b20447-40f7-423c-a404-ea9bb2410088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79164
8062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.791648062
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.1392048974
Short name T151
Test name
Test status
Simulation time 4290683113 ps
CPU time 33.7 seconds
Started Jul 18 05:47:29 PM PDT 24
Finished Jul 18 05:48:19 PM PDT 24
Peak memory 206812 kb
Host smart-8fcd6d23-90ef-488b-af69-44c5c255f9c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1392048974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.1392048974
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.2411124464
Short name T958
Test name
Test status
Simulation time 173319289 ps
CPU time 0.84 seconds
Started Jul 18 05:47:29 PM PDT 24
Finished Jul 18 05:47:46 PM PDT 24
Peak memory 206648 kb
Host smart-8baf3629-9814-487e-abc9-908ccb2a29a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24111
24464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.2411124464
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1153117901
Short name T2459
Test name
Test status
Simulation time 167253652 ps
CPU time 0.83 seconds
Started Jul 18 05:47:24 PM PDT 24
Finished Jul 18 05:47:43 PM PDT 24
Peak memory 206656 kb
Host smart-32c78f83-e6f7-40f9-9a66-723529b414e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11531
17901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1153117901
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.1725189025
Short name T1691
Test name
Test status
Simulation time 1075053429 ps
CPU time 2.19 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206760 kb
Host smart-353acb0d-3e86-4a4f-9376-ec653d9a9c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17251
89025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.1725189025
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.3488222847
Short name T2114
Test name
Test status
Simulation time 4211816068 ps
CPU time 31.47 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:48:23 PM PDT 24
Peak memory 206856 kb
Host smart-5a1f7462-6b07-4240-96b2-b905d9f0a023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34882
22847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.3488222847
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1093329263
Short name T2448
Test name
Test status
Simulation time 53647176 ps
CPU time 0.69 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:02 PM PDT 24
Peak memory 206700 kb
Host smart-30fcbf70-94ae-43a2-be6f-6b6249b2f719
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1093329263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1093329263
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1693965596
Short name T961
Test name
Test status
Simulation time 3693302264 ps
CPU time 5.53 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:48:00 PM PDT 24
Peak memory 206684 kb
Host smart-d7c6090f-aefc-49c4-ac5b-1491a9f89797
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1693965596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1693965596
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2002622836
Short name T1973
Test name
Test status
Simulation time 13386327865 ps
CPU time 14.47 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:13 PM PDT 24
Peak memory 206868 kb
Host smart-04cbd99b-84a7-4880-a2c6-98762581aefb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2002622836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2002622836
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.3102773934
Short name T552
Test name
Test status
Simulation time 23361638871 ps
CPU time 22.24 seconds
Started Jul 18 05:47:46 PM PDT 24
Finished Jul 18 05:48:13 PM PDT 24
Peak memory 206864 kb
Host smart-e1c83a29-0ecd-4557-8cab-65d5864a38c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3102773934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.3102773934
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3790736263
Short name T2502
Test name
Test status
Simulation time 172573851 ps
CPU time 0.82 seconds
Started Jul 18 05:47:46 PM PDT 24
Finished Jul 18 05:47:51 PM PDT 24
Peak memory 206656 kb
Host smart-ececb840-eb02-4efa-ba3c-284d9e71e7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37907
36263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3790736263
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.680329570
Short name T2048
Test name
Test status
Simulation time 153551640 ps
CPU time 0.86 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:47:53 PM PDT 24
Peak memory 206620 kb
Host smart-dc674a9d-ede5-45b3-b60b-960ba5cdce1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68032
9570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.680329570
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.3771440078
Short name T2334
Test name
Test status
Simulation time 558783454 ps
CPU time 1.59 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206732 kb
Host smart-b001d64d-9a86-4ae9-bc48-00fca0db970e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37714
40078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.3771440078
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2596831193
Short name T2735
Test name
Test status
Simulation time 427165252 ps
CPU time 1.19 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:00 PM PDT 24
Peak memory 206652 kb
Host smart-599999ab-d4e8-47fe-9f60-76601fda78fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25968
31193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2596831193
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.808097572
Short name T1223
Test name
Test status
Simulation time 17169686275 ps
CPU time 31.72 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:48:26 PM PDT 24
Peak memory 206912 kb
Host smart-31609d15-0441-4c68-a4cf-9dae1783fe2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80809
7572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.808097572
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.2064015996
Short name T1624
Test name
Test status
Simulation time 314009629 ps
CPU time 1.21 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:47:53 PM PDT 24
Peak memory 206616 kb
Host smart-fcb2b19a-5b16-4d4e-96b1-dc347b9adcbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20640
15996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.2064015996
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_enable.1743048883
Short name T535
Test name
Test status
Simulation time 35089979 ps
CPU time 0.72 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:54 PM PDT 24
Peak memory 206608 kb
Host smart-0d6fa280-7f6a-45ad-bd77-ededd8cd7e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17430
48883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.1743048883
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.110634540
Short name T1619
Test name
Test status
Simulation time 878790950 ps
CPU time 2.21 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:48:00 PM PDT 24
Peak memory 206728 kb
Host smart-421ec507-9a2a-4f44-8adc-cc20ecb0ccd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11063
4540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.110634540
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2875154051
Short name T1836
Test name
Test status
Simulation time 183247052 ps
CPU time 1.96 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206672 kb
Host smart-3ccfbc3e-947f-47dd-8f6a-38206c7b5c91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28751
54051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2875154051
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.818842975
Short name T2604
Test name
Test status
Simulation time 262897129 ps
CPU time 0.93 seconds
Started Jul 18 05:47:43 PM PDT 24
Finished Jul 18 05:47:50 PM PDT 24
Peak memory 206628 kb
Host smart-533a597e-fcc5-4652-9e5d-de41e29f5d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81884
2975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.818842975
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3272691128
Short name T1190
Test name
Test status
Simulation time 142905339 ps
CPU time 0.86 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:47:59 PM PDT 24
Peak memory 206612 kb
Host smart-ffa5748f-668f-48fa-8d21-f9d7a8525241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32726
91128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3272691128
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.929168528
Short name T2351
Test name
Test status
Simulation time 155275075 ps
CPU time 0.78 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:47:59 PM PDT 24
Peak memory 206656 kb
Host smart-85368eb7-c5b8-4a77-a184-a16120ae8592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92916
8528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.929168528
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.1296896922
Short name T2000
Test name
Test status
Simulation time 6658973973 ps
CPU time 62.55 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206896 kb
Host smart-735cb2cc-dfd6-4e58-a5b8-441f7d059771
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1296896922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.1296896922
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.35425940
Short name T1760
Test name
Test status
Simulation time 8091390639 ps
CPU time 24.67 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206908 kb
Host smart-8fe145f3-868f-4a2c-925e-d4e5cedc0ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35425
940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.35425940
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2249052981
Short name T743
Test name
Test status
Simulation time 237592349 ps
CPU time 0.88 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:47:58 PM PDT 24
Peak memory 206612 kb
Host smart-1fb8dd7b-36f1-4a4e-8a96-245a6d7caf1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22490
52981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2249052981
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2536924657
Short name T1988
Test name
Test status
Simulation time 23285034971 ps
CPU time 23.08 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:48:19 PM PDT 24
Peak memory 206764 kb
Host smart-2c81f839-4661-4c36-977f-71d1143792a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25369
24657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2536924657
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.4227698993
Short name T750
Test name
Test status
Simulation time 3336880515 ps
CPU time 4.05 seconds
Started Jul 18 05:47:53 PM PDT 24
Finished Jul 18 05:48:06 PM PDT 24
Peak memory 206708 kb
Host smart-7162b77b-78d5-4b82-8935-127941109b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42276
98993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.4227698993
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.108521160
Short name T2327
Test name
Test status
Simulation time 10949759208 ps
CPU time 308.66 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:53:04 PM PDT 24
Peak memory 206904 kb
Host smart-39b33527-b5fb-47ac-b072-ba751fb74d05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10852
1160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.108521160
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1266820682
Short name T2523
Test name
Test status
Simulation time 3508392412 ps
CPU time 95.8 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206836 kb
Host smart-6007370d-3d5e-4330-a2e4-75d2ce79f006
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1266820682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1266820682
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.1618181382
Short name T2044
Test name
Test status
Simulation time 246466602 ps
CPU time 0.92 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:47:53 PM PDT 24
Peak memory 206652 kb
Host smart-61cb36ca-e7b2-4853-8266-05d13260d16f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1618181382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.1618181382
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.122569118
Short name T2189
Test name
Test status
Simulation time 190993892 ps
CPU time 0.92 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:56 PM PDT 24
Peak memory 206640 kb
Host smart-2117c368-a498-49ca-980d-77160319a178
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12256
9118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.122569118
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.3955392537
Short name T503
Test name
Test status
Simulation time 4642155395 ps
CPU time 45.09 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:48:40 PM PDT 24
Peak memory 206892 kb
Host smart-83746377-6009-4c58-aecc-fb5d14949ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
92537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.3955392537
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.903409147
Short name T1845
Test name
Test status
Simulation time 6257587543 ps
CPU time 177.76 seconds
Started Jul 18 05:47:46 PM PDT 24
Finished Jul 18 05:50:49 PM PDT 24
Peak memory 206884 kb
Host smart-44d54538-53d7-46ec-8587-43335b182383
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=903409147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.903409147
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2974982208
Short name T942
Test name
Test status
Simulation time 165988096 ps
CPU time 0.78 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:58 PM PDT 24
Peak memory 206660 kb
Host smart-700a831f-913f-4980-86e6-2dea84fdff53
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2974982208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2974982208
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.1162092664
Short name T926
Test name
Test status
Simulation time 175581848 ps
CPU time 0.81 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:56 PM PDT 24
Peak memory 206616 kb
Host smart-952fa3ee-e34f-4e7d-94ae-4a5c8e765cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11620
92664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.1162092664
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.3106159465
Short name T142
Test name
Test status
Simulation time 226009639 ps
CPU time 0.93 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206640 kb
Host smart-ac95efbd-9a69-41e5-ba60-3dd8d88b2ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31061
59465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.3106159465
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.2577744064
Short name T804
Test name
Test status
Simulation time 160490632 ps
CPU time 0.79 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206640 kb
Host smart-7e8ddfc3-095e-4f13-8109-dd1c60a4ed19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25777
44064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.2577744064
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1114108284
Short name T455
Test name
Test status
Simulation time 201190555 ps
CPU time 0.83 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:54 PM PDT 24
Peak memory 206612 kb
Host smart-4c2dfae4-c86d-44e4-99ac-989a2e5d4788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11141
08284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1114108284
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.773102017
Short name T1795
Test name
Test status
Simulation time 179752322 ps
CPU time 0.78 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:58 PM PDT 24
Peak memory 206652 kb
Host smart-2035b2a5-eace-4b78-993e-5289f2c79add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77310
2017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.773102017
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2134724880
Short name T1953
Test name
Test status
Simulation time 161543445 ps
CPU time 0.9 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:53 PM PDT 24
Peak memory 206632 kb
Host smart-59f0df44-12d0-440b-a8b9-19e718e2ec5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21347
24880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2134724880
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3987199192
Short name T357
Test name
Test status
Simulation time 267233329 ps
CPU time 1.11 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:47:59 PM PDT 24
Peak memory 206636 kb
Host smart-38847c82-a073-44e9-9a35-813a3197df6a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3987199192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3987199192
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3206654323
Short name T351
Test name
Test status
Simulation time 188340347 ps
CPU time 0.81 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:47:53 PM PDT 24
Peak memory 206644 kb
Host smart-0b8a806a-c8b1-462c-bf22-e920c1dcf625
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
54323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3206654323
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2424995800
Short name T1653
Test name
Test status
Simulation time 37373683 ps
CPU time 0.7 seconds
Started Jul 18 05:47:54 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206616 kb
Host smart-e08afeac-9fc9-4e51-8557-b7e999e471b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24249
95800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2424995800
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2511586804
Short name T256
Test name
Test status
Simulation time 19220132977 ps
CPU time 42.47 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:48:39 PM PDT 24
Peak memory 206924 kb
Host smart-40c25b32-ad26-4e90-a3aa-9a554b453d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25115
86804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2511586804
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.482308130
Short name T927
Test name
Test status
Simulation time 170518852 ps
CPU time 0.84 seconds
Started Jul 18 05:47:45 PM PDT 24
Finished Jul 18 05:47:51 PM PDT 24
Peak memory 206652 kb
Host smart-9f01cf85-42a8-4947-8450-22f80d8d0572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48230
8130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.482308130
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.1850127937
Short name T362
Test name
Test status
Simulation time 234760784 ps
CPU time 0.95 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:02 PM PDT 24
Peak memory 206624 kb
Host smart-a4aee1d4-4d39-4888-8f77-d30f99af8949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18501
27937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.1850127937
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.526831358
Short name T2404
Test name
Test status
Simulation time 206772036 ps
CPU time 0.91 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206636 kb
Host smart-0575fa5a-5057-466e-b3e6-d97f1c557a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52683
1358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.526831358
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2786267977
Short name T1334
Test name
Test status
Simulation time 215677817 ps
CPU time 0.9 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:58 PM PDT 24
Peak memory 206632 kb
Host smart-61d00df0-1596-4955-8784-e8f337d7fc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27862
67977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2786267977
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3780582992
Short name T519
Test name
Test status
Simulation time 187195318 ps
CPU time 0.85 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:47:52 PM PDT 24
Peak memory 206612 kb
Host smart-1085201e-3e0c-47ae-82ca-d41b5c3a1220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37805
82992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3780582992
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1076414451
Short name T1807
Test name
Test status
Simulation time 174523005 ps
CPU time 0.78 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206632 kb
Host smart-8c60ee9c-144b-49d8-9542-fde33e7eaff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10764
14451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1076414451
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1268895887
Short name T895
Test name
Test status
Simulation time 166570123 ps
CPU time 0.79 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:56 PM PDT 24
Peak memory 206652 kb
Host smart-f139a63f-8170-4678-be4a-be30df8b28ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12688
95887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1268895887
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.4085363447
Short name T634
Test name
Test status
Simulation time 235513891 ps
CPU time 0.93 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206648 kb
Host smart-9bffa1d2-76e1-4744-a19f-e4babf723b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40853
63447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.4085363447
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.3302001296
Short name T1196
Test name
Test status
Simulation time 4874310204 ps
CPU time 137.6 seconds
Started Jul 18 05:47:46 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206804 kb
Host smart-85fd2d66-f16c-4d51-960c-ab3b7f6e5171
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3302001296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.3302001296
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.3234874100
Short name T2568
Test name
Test status
Simulation time 196166596 ps
CPU time 0.82 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:03 PM PDT 24
Peak memory 206616 kb
Host smart-a9761322-7d46-4467-bd06-407f10e4852d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32348
74100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.3234874100
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.1440948383
Short name T795
Test name
Test status
Simulation time 181944655 ps
CPU time 0.83 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206612 kb
Host smart-18c55c01-b4e0-4ad7-a082-490f61f70445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14409
48383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.1440948383
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1696098682
Short name T2425
Test name
Test status
Simulation time 778906451 ps
CPU time 1.89 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:03 PM PDT 24
Peak memory 206764 kb
Host smart-6fc24f4b-6e0d-4f49-ab0e-10501ba85ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16960
98682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1696098682
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.1928988026
Short name T1216
Test name
Test status
Simulation time 3754661283 ps
CPU time 34.95 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:48:33 PM PDT 24
Peak memory 206860 kb
Host smart-eaa70646-338b-48c1-90e1-7ad70363d9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19289
88026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.1928988026
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2323716734
Short name T1941
Test name
Test status
Simulation time 48885816 ps
CPU time 0.71 seconds
Started Jul 18 05:48:05 PM PDT 24
Finished Jul 18 05:48:09 PM PDT 24
Peak memory 206688 kb
Host smart-cbc602b4-86ed-4a96-a32b-80394219f7f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2323716734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2323716734
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.4256545367
Short name T2675
Test name
Test status
Simulation time 3871097059 ps
CPU time 5.47 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206868 kb
Host smart-790a8f22-1dd9-47b6-a5de-3fd35f10b184
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4256545367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.4256545367
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.3212072886
Short name T2282
Test name
Test status
Simulation time 13335202537 ps
CPU time 16.66 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206724 kb
Host smart-9ea31c6b-ae59-49f3-96fc-de7f4d0ef146
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3212072886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.3212072886
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3141430067
Short name T1729
Test name
Test status
Simulation time 147373385 ps
CPU time 0.79 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:55 PM PDT 24
Peak memory 206656 kb
Host smart-3e3d8542-b87f-4482-9edb-56686be1a3b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31414
30067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3141430067
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.2771233226
Short name T680
Test name
Test status
Simulation time 157872231 ps
CPU time 0.77 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:02 PM PDT 24
Peak memory 206652 kb
Host smart-30a797c4-fc99-4372-87eb-6f2e8a9f2690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27712
33226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.2771233226
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3745980251
Short name T2417
Test name
Test status
Simulation time 428979638 ps
CPU time 1.35 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:47:59 PM PDT 24
Peak memory 206644 kb
Host smart-8607b3a9-c26e-41ab-a068-04403662d81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37459
80251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3745980251
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.794544488
Short name T1348
Test name
Test status
Simulation time 475729464 ps
CPU time 1.34 seconds
Started Jul 18 05:47:48 PM PDT 24
Finished Jul 18 05:47:56 PM PDT 24
Peak memory 206644 kb
Host smart-6c15b1e6-1de1-4d04-a3a1-2aa511ed7244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79454
4488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.794544488
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.423225560
Short name T592
Test name
Test status
Simulation time 16813111306 ps
CPU time 37.7 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:38 PM PDT 24
Peak memory 206888 kb
Host smart-e5cd2db9-2cea-4442-a87e-382c3d0f4b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42322
5560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.423225560
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.1054410077
Short name T437
Test name
Test status
Simulation time 421578287 ps
CPU time 1.35 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:02 PM PDT 24
Peak memory 206636 kb
Host smart-b9f1a093-5ba6-4029-8e32-89c917d1c4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10544
10077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.1054410077
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.2960798919
Short name T527
Test name
Test status
Simulation time 139717161 ps
CPU time 0.8 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206656 kb
Host smart-f6bf88b7-0c9f-4968-8615-3dd336d24524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29607
98919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.2960798919
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.2702388172
Short name T572
Test name
Test status
Simulation time 85002872 ps
CPU time 0.74 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:02 PM PDT 24
Peak memory 206624 kb
Host smart-66ab1e6f-873a-4175-afd6-3b43347c7a1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27023
88172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.2702388172
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.3439049972
Short name T2124
Test name
Test status
Simulation time 880493705 ps
CPU time 2.19 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:59 PM PDT 24
Peak memory 206784 kb
Host smart-c3c978d5-2fea-4697-82b2-9e8737d06003
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34390
49972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.3439049972
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.2494044369
Short name T2617
Test name
Test status
Simulation time 375586962 ps
CPU time 2.19 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206724 kb
Host smart-8167d8e8-d317-473a-aa39-d9fde5150ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24940
44369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.2494044369
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.2104310308
Short name T1102
Test name
Test status
Simulation time 203577323 ps
CPU time 0.9 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206652 kb
Host smart-272619d7-d93b-4482-b9d2-b364c39dd79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
10308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.2104310308
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.246764806
Short name T1108
Test name
Test status
Simulation time 169255082 ps
CPU time 0.82 seconds
Started Jul 18 05:47:53 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206624 kb
Host smart-e0f74b0e-71d1-406e-a8ea-58dd8bfb55b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24676
4806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.246764806
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.3554243803
Short name T401
Test name
Test status
Simulation time 202403002 ps
CPU time 0.83 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206640 kb
Host smart-9ff71060-a6ff-4cbf-9758-364921304744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35542
43803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.3554243803
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.2557156131
Short name T208
Test name
Test status
Simulation time 7112070690 ps
CPU time 55.02 seconds
Started Jul 18 05:47:50 PM PDT 24
Finished Jul 18 05:48:53 PM PDT 24
Peak memory 206880 kb
Host smart-a3c64f4e-134a-48a4-b115-2eb06fe63ef0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2557156131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.2557156131
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.1935713569
Short name T996
Test name
Test status
Simulation time 12576713920 ps
CPU time 38.46 seconds
Started Jul 18 05:47:56 PM PDT 24
Finished Jul 18 05:48:43 PM PDT 24
Peak memory 206888 kb
Host smart-57bde107-2e5b-496c-bae2-9d5effd70aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19357
13569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.1935713569
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.2581728264
Short name T586
Test name
Test status
Simulation time 221230757 ps
CPU time 0.92 seconds
Started Jul 18 05:47:54 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206636 kb
Host smart-5ac8580f-7f1e-42b3-a758-9e4ea6494452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25817
28264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.2581728264
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.4207209867
Short name T2746
Test name
Test status
Simulation time 23327070138 ps
CPU time 22.69 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:23 PM PDT 24
Peak memory 206748 kb
Host smart-70dcf212-f3f1-4ce2-aacb-f285b0e99082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
09867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.4207209867
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.1257366166
Short name T2019
Test name
Test status
Simulation time 3350948310 ps
CPU time 3.88 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:06 PM PDT 24
Peak memory 206704 kb
Host smart-6b4cfa47-f04c-46a0-b7f5-178e251bfaf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12573
66166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.1257366166
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.1112413653
Short name T1879
Test name
Test status
Simulation time 11586509522 ps
CPU time 332.73 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:53:33 PM PDT 24
Peak memory 206912 kb
Host smart-bc9dbad1-409f-4829-92ab-43667af2ddb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11124
13653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.1112413653
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.3951241155
Short name T1490
Test name
Test status
Simulation time 4100756125 ps
CPU time 38.67 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:38 PM PDT 24
Peak memory 206908 kb
Host smart-66e36faa-87c1-42b7-953c-f568ce157b8b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3951241155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.3951241155
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.3084764315
Short name T799
Test name
Test status
Simulation time 237301124 ps
CPU time 0.91 seconds
Started Jul 18 05:47:55 PM PDT 24
Finished Jul 18 05:48:05 PM PDT 24
Peak memory 206648 kb
Host smart-32e2ea65-607d-4fe3-99d3-783ae1d26922
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3084764315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.3084764315
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.691503914
Short name T2395
Test name
Test status
Simulation time 190179374 ps
CPU time 0.96 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:58 PM PDT 24
Peak memory 206664 kb
Host smart-e7130efe-ed7b-44fc-bd16-7f329aaaaa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69150
3914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.691503914
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2712514570
Short name T1972
Test name
Test status
Simulation time 4659207130 ps
CPU time 130.49 seconds
Started Jul 18 05:47:53 PM PDT 24
Finished Jul 18 05:50:13 PM PDT 24
Peak memory 206860 kb
Host smart-0ab45156-c3f3-4dc2-8401-12a16a925576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27125
14570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2712514570
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.4031323707
Short name T688
Test name
Test status
Simulation time 5209716923 ps
CPU time 45.47 seconds
Started Jul 18 05:47:55 PM PDT 24
Finished Jul 18 05:48:49 PM PDT 24
Peak memory 206844 kb
Host smart-911ec000-2cce-4269-bd30-821a6f0f882f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4031323707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.4031323707
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.2579300128
Short name T1170
Test name
Test status
Simulation time 181873910 ps
CPU time 0.78 seconds
Started Jul 18 05:47:54 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206648 kb
Host smart-25defca3-6274-4974-8d04-920b9cede3c9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2579300128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.2579300128
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2768721110
Short name T2704
Test name
Test status
Simulation time 213601183 ps
CPU time 0.83 seconds
Started Jul 18 05:47:55 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206644 kb
Host smart-d1282257-0280-4226-a1eb-f16ef0bbef5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27687
21110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2768721110
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.474399419
Short name T1693
Test name
Test status
Simulation time 223291886 ps
CPU time 0.89 seconds
Started Jul 18 05:47:47 PM PDT 24
Finished Jul 18 05:47:53 PM PDT 24
Peak memory 206648 kb
Host smart-70280f4f-1961-449b-9be2-18e5dfe95460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47439
9419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.474399419
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1935957102
Short name T2246
Test name
Test status
Simulation time 177906925 ps
CPU time 0.84 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206652 kb
Host smart-925788e3-10e7-4337-9c2d-df68db5da7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19359
57102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1935957102
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1863605517
Short name T1914
Test name
Test status
Simulation time 195207025 ps
CPU time 0.85 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206656 kb
Host smart-afb54068-53c1-4f0a-8cd7-6e60e538544d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18636
05517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1863605517
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2679804126
Short name T1012
Test name
Test status
Simulation time 169290728 ps
CPU time 0.85 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206656 kb
Host smart-53e7e909-1558-46ef-8a11-edea7bd6aebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26798
04126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2679804126
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.3481754645
Short name T2003
Test name
Test status
Simulation time 150842887 ps
CPU time 0.78 seconds
Started Jul 18 05:48:05 PM PDT 24
Finished Jul 18 05:48:10 PM PDT 24
Peak memory 206656 kb
Host smart-bc9a69ff-e058-4feb-af20-437d4c1849e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34817
54645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.3481754645
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.503065141
Short name T1345
Test name
Test status
Simulation time 199182339 ps
CPU time 0.9 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206640 kb
Host smart-89631813-d405-4113-a076-b470e7bb9998
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=503065141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.503065141
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.2703987846
Short name T2698
Test name
Test status
Simulation time 146296475 ps
CPU time 0.8 seconds
Started Jul 18 05:47:49 PM PDT 24
Finished Jul 18 05:47:56 PM PDT 24
Peak memory 206632 kb
Host smart-9e6b834e-a4e7-4ab2-afbd-e34d4718677d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27039
87846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.2703987846
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2918526844
Short name T1295
Test name
Test status
Simulation time 52795675 ps
CPU time 0.68 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206648 kb
Host smart-e6032f5b-65dd-4f2e-8792-8ef5ec2ebdd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29185
26844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2918526844
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1272049546
Short name T229
Test name
Test status
Simulation time 8124642396 ps
CPU time 19.42 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:19 PM PDT 24
Peak memory 206928 kb
Host smart-3f7ea8f1-d19a-47ba-9b65-c61bc1bb9839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12720
49546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1272049546
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.2360770220
Short name T1636
Test name
Test status
Simulation time 168823615 ps
CPU time 0.82 seconds
Started Jul 18 05:47:51 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206652 kb
Host smart-eba38556-fc95-43b1-990b-2b5d1464cad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23607
70220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.2360770220
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.1252180261
Short name T2216
Test name
Test status
Simulation time 200279073 ps
CPU time 0.87 seconds
Started Jul 18 05:47:53 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206520 kb
Host smart-69e8037c-bca3-454f-801c-fa56f2805c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12521
80261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.1252180261
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.1226224520
Short name T1415
Test name
Test status
Simulation time 197854891 ps
CPU time 0.87 seconds
Started Jul 18 05:47:54 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206652 kb
Host smart-28acf17c-4046-4f94-bb83-c9691c442afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12262
24520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.1226224520
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3892178442
Short name T1337
Test name
Test status
Simulation time 164582132 ps
CPU time 0.77 seconds
Started Jul 18 05:47:55 PM PDT 24
Finished Jul 18 05:48:05 PM PDT 24
Peak memory 206652 kb
Host smart-3f57b76e-5b9e-4a97-8c33-eefc661d51c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38921
78442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3892178442
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1141621091
Short name T2191
Test name
Test status
Simulation time 152338601 ps
CPU time 0.83 seconds
Started Jul 18 05:47:53 PM PDT 24
Finished Jul 18 05:48:03 PM PDT 24
Peak memory 206640 kb
Host smart-70ea7b15-5fa3-4300-bdb3-1a17fed2ee44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11416
21091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1141621091
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.401227165
Short name T1905
Test name
Test status
Simulation time 143619641 ps
CPU time 0.81 seconds
Started Jul 18 05:47:52 PM PDT 24
Finished Jul 18 05:48:01 PM PDT 24
Peak memory 206636 kb
Host smart-cd1a0618-fe73-4c3f-9254-d17781c01c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40122
7165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.401227165
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3706082812
Short name T2572
Test name
Test status
Simulation time 146568652 ps
CPU time 0.85 seconds
Started Jul 18 05:47:53 PM PDT 24
Finished Jul 18 05:48:04 PM PDT 24
Peak memory 206448 kb
Host smart-3a210be2-ca18-4949-a32c-6f05e9e8c9c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37060
82812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3706082812
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.676907173
Short name T1726
Test name
Test status
Simulation time 250900744 ps
CPU time 1.09 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:12 PM PDT 24
Peak memory 206632 kb
Host smart-72e2e47d-f1d2-44f4-87ca-ff9249ced8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67690
7173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.676907173
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3849125131
Short name T540
Test name
Test status
Simulation time 6045830449 ps
CPU time 172.68 seconds
Started Jul 18 05:48:09 PM PDT 24
Finished Jul 18 05:51:06 PM PDT 24
Peak memory 206844 kb
Host smart-afe9d7e7-193c-4ecb-b5da-9b75c6d69eae
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3849125131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3849125131
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2612141710
Short name T1122
Test name
Test status
Simulation time 170673161 ps
CPU time 0.85 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206628 kb
Host smart-ad3ce048-6baf-4aaf-9f49-6eb54a3cec56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
41710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2612141710
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.67694920
Short name T2444
Test name
Test status
Simulation time 191426448 ps
CPU time 0.84 seconds
Started Jul 18 05:48:06 PM PDT 24
Finished Jul 18 05:48:11 PM PDT 24
Peak memory 206628 kb
Host smart-abd58ad4-e93a-4ae1-9d50-76c08d917f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67694
920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.67694920
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1567730991
Short name T1544
Test name
Test status
Simulation time 1318780182 ps
CPU time 2.52 seconds
Started Jul 18 05:48:06 PM PDT 24
Finished Jul 18 05:48:12 PM PDT 24
Peak memory 206800 kb
Host smart-4e2495ee-1cdb-4962-a705-d0bdc10a6fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15677
30991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1567730991
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.4098540240
Short name T1314
Test name
Test status
Simulation time 4024298047 ps
CPU time 39.24 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:50 PM PDT 24
Peak memory 206924 kb
Host smart-04eb94ea-3e2a-4ff3-9f87-7d0eaad43208
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985
40240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.4098540240
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.124797244
Short name T409
Test name
Test status
Simulation time 57787168 ps
CPU time 0.72 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206652 kb
Host smart-9dbf4602-337d-44fc-a837-6b7efe46675f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=124797244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.124797244
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.822773952
Short name T1506
Test name
Test status
Simulation time 3689853885 ps
CPU time 4.33 seconds
Started Jul 18 05:48:08 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206724 kb
Host smart-a6add888-4a33-45ea-b807-7bfa8440a912
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=822773952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.822773952
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1367895574
Short name T1892
Test name
Test status
Simulation time 13360952514 ps
CPU time 13.1 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:32 PM PDT 24
Peak memory 206868 kb
Host smart-e09234ca-7c74-411f-b4c6-794dc87f7333
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1367895574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1367895574
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2625691897
Short name T2103
Test name
Test status
Simulation time 23380763158 ps
CPU time 21.57 seconds
Started Jul 18 05:48:15 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206716 kb
Host smart-c4f39cc1-0108-4262-bc9c-45cecc758137
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2625691897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2625691897
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.2192284448
Short name T2244
Test name
Test status
Simulation time 197760249 ps
CPU time 0.95 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:12 PM PDT 24
Peak memory 206636 kb
Host smart-4bb35927-6903-42c9-845f-347c6e7250ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21922
84448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.2192284448
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.4153120651
Short name T2724
Test name
Test status
Simulation time 199639498 ps
CPU time 0.85 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206632 kb
Host smart-563c26f1-1e07-44a6-a88f-2616316b9cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41531
20651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.4153120651
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.741677214
Short name T759
Test name
Test status
Simulation time 462418328 ps
CPU time 1.42 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:19 PM PDT 24
Peak memory 206624 kb
Host smart-39ecefd7-a37f-4739-88db-dec49987f568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74167
7214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.741677214
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2121032388
Short name T732
Test name
Test status
Simulation time 983172547 ps
CPU time 2.33 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:13 PM PDT 24
Peak memory 206796 kb
Host smart-6e0d6499-2655-46bb-997d-f6f28029c655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21210
32388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2121032388
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.1955375960
Short name T2322
Test name
Test status
Simulation time 8788439724 ps
CPU time 16.68 seconds
Started Jul 18 05:48:08 PM PDT 24
Finished Jul 18 05:48:29 PM PDT 24
Peak memory 206880 kb
Host smart-17769051-4c0c-4bc7-8d61-c79d3fb954f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19553
75960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.1955375960
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.2149446588
Short name T2671
Test name
Test status
Simulation time 371166657 ps
CPU time 1.28 seconds
Started Jul 18 05:48:08 PM PDT 24
Finished Jul 18 05:48:13 PM PDT 24
Peak memory 206648 kb
Host smart-f7b5d5d4-f727-4cc8-b892-d5db460c127c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21494
46588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.2149446588
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1860775770
Short name T1641
Test name
Test status
Simulation time 150786388 ps
CPU time 0.79 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206620 kb
Host smart-46d33f43-5b21-46f6-b1a9-7f71f40dfba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18607
75770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1860775770
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.372329716
Short name T1353
Test name
Test status
Simulation time 81502555 ps
CPU time 0.72 seconds
Started Jul 18 05:48:09 PM PDT 24
Finished Jul 18 05:48:14 PM PDT 24
Peak memory 206624 kb
Host smart-1fc0333e-0da3-4486-b950-01a2bd8a53b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37232
9716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.372329716
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.1422815083
Short name T2605
Test name
Test status
Simulation time 924448877 ps
CPU time 2.11 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206772 kb
Host smart-d605ddee-fbc0-4241-801d-716de2c21dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14228
15083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.1422815083
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.1427941458
Short name T1071
Test name
Test status
Simulation time 364473757 ps
CPU time 2.32 seconds
Started Jul 18 05:48:06 PM PDT 24
Finished Jul 18 05:48:12 PM PDT 24
Peak memory 206800 kb
Host smart-80ce4d46-848e-4aa1-9503-ebfe86745f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14279
41458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.1427941458
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.4035696836
Short name T1424
Test name
Test status
Simulation time 239315741 ps
CPU time 0.92 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:12 PM PDT 24
Peak memory 206608 kb
Host smart-9f11cfc7-1fd9-45fc-b058-b4dfc1616fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40356
96836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.4035696836
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1107910921
Short name T1002
Test name
Test status
Simulation time 165519977 ps
CPU time 0.79 seconds
Started Jul 18 05:48:06 PM PDT 24
Finished Jul 18 05:48:11 PM PDT 24
Peak memory 206648 kb
Host smart-236de5d8-b73d-4b7c-93c8-516d1344dada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11079
10921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1107910921
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2633017695
Short name T2518
Test name
Test status
Simulation time 152177710 ps
CPU time 0.84 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206632 kb
Host smart-722c7c19-3994-4d86-b34d-a9479a430e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26330
17695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2633017695
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.1210597025
Short name T951
Test name
Test status
Simulation time 5802025356 ps
CPU time 54.72 seconds
Started Jul 18 05:48:05 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 207004 kb
Host smart-4fe22062-3918-4895-b1d2-7007ccfb6be6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1210597025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.1210597025
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.3388534565
Short name T2172
Test name
Test status
Simulation time 10019614012 ps
CPU time 30.83 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206868 kb
Host smart-df5ab640-2a10-492e-a09e-19eb71ffe004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33885
34565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.3388534565
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1440708282
Short name T1574
Test name
Test status
Simulation time 166788177 ps
CPU time 0.78 seconds
Started Jul 18 05:48:06 PM PDT 24
Finished Jul 18 05:48:10 PM PDT 24
Peak memory 206648 kb
Host smart-5eecb2c4-54ab-4284-b4a3-77fddd540e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14407
08282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1440708282
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.100177597
Short name T2445
Test name
Test status
Simulation time 23357063454 ps
CPU time 25.56 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:43 PM PDT 24
Peak memory 206744 kb
Host smart-04060b1f-edfa-4ef9-9328-b6c19ef37343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10017
7597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.100177597
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1331003051
Short name T485
Test name
Test status
Simulation time 3331642612 ps
CPU time 3.82 seconds
Started Jul 18 05:48:09 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206704 kb
Host smart-4c9e92eb-ef4e-4a2a-b830-755141e1ca16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13310
03051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1331003051
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.797686073
Short name T536
Test name
Test status
Simulation time 5313773476 ps
CPU time 145.47 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:50:41 PM PDT 24
Peak memory 206928 kb
Host smart-f105761f-3fde-40d2-bbe3-05528700c4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79768
6073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.797686073
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.1656157592
Short name T2313
Test name
Test status
Simulation time 5488264090 ps
CPU time 40.92 seconds
Started Jul 18 05:48:05 PM PDT 24
Finished Jul 18 05:48:50 PM PDT 24
Peak memory 206904 kb
Host smart-28809da7-f482-4fd8-809f-3c93c80c887d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1656157592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.1656157592
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2752413393
Short name T1324
Test name
Test status
Simulation time 231615552 ps
CPU time 0.96 seconds
Started Jul 18 05:48:05 PM PDT 24
Finished Jul 18 05:48:09 PM PDT 24
Peak memory 206616 kb
Host smart-abbebb5c-7f01-4465-b81c-25f9c0aff474
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2752413393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2752413393
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1906652271
Short name T2051
Test name
Test status
Simulation time 226375227 ps
CPU time 0.87 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206620 kb
Host smart-c95a620d-7eca-45be-a1bb-366d2cd3a09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19066
52271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1906652271
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.1294478836
Short name T1765
Test name
Test status
Simulation time 5304980597 ps
CPU time 48.75 seconds
Started Jul 18 05:48:24 PM PDT 24
Finished Jul 18 05:49:18 PM PDT 24
Peak memory 206848 kb
Host smart-3f7cb329-b5b2-408d-8e83-629c8b30ef83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12944
78836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.1294478836
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.4093492764
Short name T2226
Test name
Test status
Simulation time 5980757081 ps
CPU time 43.22 seconds
Started Jul 18 05:48:05 PM PDT 24
Finished Jul 18 05:48:52 PM PDT 24
Peak memory 206892 kb
Host smart-43a3e5f5-6ef4-463b-8029-3b4c9230ee48
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4093492764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.4093492764
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3876464615
Short name T1839
Test name
Test status
Simulation time 169403330 ps
CPU time 0.83 seconds
Started Jul 18 05:48:15 PM PDT 24
Finished Jul 18 05:48:24 PM PDT 24
Peak memory 206456 kb
Host smart-3fd8744c-0ec6-4e94-900a-2a326381cb0e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3876464615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3876464615
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.3918805613
Short name T871
Test name
Test status
Simulation time 202662013 ps
CPU time 0.8 seconds
Started Jul 18 05:48:05 PM PDT 24
Finished Jul 18 05:48:10 PM PDT 24
Peak memory 206648 kb
Host smart-856a7f03-1d41-461e-b7bf-3420f2bcfa09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39188
05613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.3918805613
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.3914972535
Short name T132
Test name
Test status
Simulation time 195929849 ps
CPU time 0.84 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206656 kb
Host smart-cccb7235-cb48-402c-ad53-55d3c6cbae66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39149
72535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.3914972535
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1024911292
Short name T2585
Test name
Test status
Simulation time 152428317 ps
CPU time 0.82 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206640 kb
Host smart-5e2ad17f-70ae-49ac-8fd4-b6419ab0722c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10249
11292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1024911292
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.4092673527
Short name T1627
Test name
Test status
Simulation time 206338113 ps
CPU time 0.85 seconds
Started Jul 18 05:48:04 PM PDT 24
Finished Jul 18 05:48:09 PM PDT 24
Peak memory 206640 kb
Host smart-62226784-8d76-4eaa-8c99-c554041bbdbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40926
73527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.4092673527
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.417031731
Short name T1466
Test name
Test status
Simulation time 185611440 ps
CPU time 0.81 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206648 kb
Host smart-1df89087-29c2-4534-be95-608b766b0bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41703
1731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.417031731
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3803524435
Short name T1863
Test name
Test status
Simulation time 160295807 ps
CPU time 0.8 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:11 PM PDT 24
Peak memory 206656 kb
Host smart-2963cc36-5198-4c91-adb8-41300063dc03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38035
24435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3803524435
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.1858474547
Short name T447
Test name
Test status
Simulation time 223411706 ps
CPU time 0.97 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206624 kb
Host smart-4e20fc61-d61e-474a-bf3a-e1e5dcb036e0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1858474547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.1858474547
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.760073710
Short name T1162
Test name
Test status
Simulation time 164972580 ps
CPU time 0.78 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206624 kb
Host smart-e35aa4a6-32cf-4ea5-af7e-297155656cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76007
3710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.760073710
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2418780236
Short name T1642
Test name
Test status
Simulation time 37922055 ps
CPU time 0.66 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206648 kb
Host smart-1b39e375-d207-4a7f-b5eb-b990d547cd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24187
80236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2418780236
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.257153287
Short name T925
Test name
Test status
Simulation time 16375476245 ps
CPU time 35.01 seconds
Started Jul 18 05:48:09 PM PDT 24
Finished Jul 18 05:48:50 PM PDT 24
Peak memory 206940 kb
Host smart-9b90c7b5-636e-4ea1-9ba1-548c2d643dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25715
3287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.257153287
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.3167327137
Short name T1331
Test name
Test status
Simulation time 199464942 ps
CPU time 0.83 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:18 PM PDT 24
Peak memory 206672 kb
Host smart-86820030-7f3e-443a-989c-f41eecd50e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31673
27137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.3167327137
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.1583545342
Short name T1743
Test name
Test status
Simulation time 244210581 ps
CPU time 0.92 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:26 PM PDT 24
Peak memory 206632 kb
Host smart-c9a989c5-e7b2-4118-8ad5-03190bbd22b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15835
45342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.1583545342
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3405200266
Short name T2250
Test name
Test status
Simulation time 233563691 ps
CPU time 0.91 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206660 kb
Host smart-0bc4ffd0-27ed-467a-b6a3-cfade4b00a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34052
00266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3405200266
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.3627780748
Short name T1090
Test name
Test status
Simulation time 213982401 ps
CPU time 0.83 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206644 kb
Host smart-6056543f-ae9a-487c-9ce8-6be87556070c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277
80748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.3627780748
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.1159967299
Short name T2495
Test name
Test status
Simulation time 159692989 ps
CPU time 0.78 seconds
Started Jul 18 05:48:08 PM PDT 24
Finished Jul 18 05:48:13 PM PDT 24
Peak memory 206648 kb
Host smart-52f4d4b1-24b1-4961-87f7-3ce69e40d757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11599
67299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.1159967299
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1725249740
Short name T1019
Test name
Test status
Simulation time 150130711 ps
CPU time 0.77 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:21 PM PDT 24
Peak memory 206580 kb
Host smart-596e08c0-bd19-476a-9fb9-37ac470c6ad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17252
49740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1725249740
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.4148952044
Short name T1055
Test name
Test status
Simulation time 151440880 ps
CPU time 0.77 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:18 PM PDT 24
Peak memory 206672 kb
Host smart-1098bc72-2c5b-46d6-8da5-034155430e79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41489
52044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.4148952044
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3294634865
Short name T1160
Test name
Test status
Simulation time 224342812 ps
CPU time 0.93 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206620 kb
Host smart-07c3b72a-4125-4165-8e8f-81bdb97e00de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32946
34865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3294634865
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.4248583781
Short name T1648
Test name
Test status
Simulation time 4666306049 ps
CPU time 42.93 seconds
Started Jul 18 05:48:15 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206908 kb
Host smart-b1303998-f536-4e98-8d3f-39963822a54c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4248583781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.4248583781
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3330110553
Short name T1542
Test name
Test status
Simulation time 168676845 ps
CPU time 0.86 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:18 PM PDT 24
Peak memory 206624 kb
Host smart-0b92e9ea-6f02-411a-9e3e-9721d12f7373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33301
10553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3330110553
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.3009383366
Short name T1965
Test name
Test status
Simulation time 189067512 ps
CPU time 0.81 seconds
Started Jul 18 05:48:09 PM PDT 24
Finished Jul 18 05:48:14 PM PDT 24
Peak memory 206640 kb
Host smart-0d5c134a-4770-42fc-bb5a-3a577dc15561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30093
83366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.3009383366
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1513704848
Short name T2592
Test name
Test status
Simulation time 684579994 ps
CPU time 1.71 seconds
Started Jul 18 05:48:09 PM PDT 24
Finished Jul 18 05:48:15 PM PDT 24
Peak memory 206948 kb
Host smart-49575edf-d701-4ed6-9710-3fbcfa6c66ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137
04848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1513704848
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.763795746
Short name T2372
Test name
Test status
Simulation time 5381695974 ps
CPU time 143.84 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:50:41 PM PDT 24
Peak memory 206860 kb
Host smart-6e2038be-8325-4dd2-8797-e87b16ac6b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76379
5746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.763795746
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2107511055
Short name T2608
Test name
Test status
Simulation time 50806894 ps
CPU time 0.69 seconds
Started Jul 18 05:48:15 PM PDT 24
Finished Jul 18 05:48:24 PM PDT 24
Peak memory 206688 kb
Host smart-b1110af9-bb32-445e-8df1-0c8a3cec86ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2107511055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2107511055
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.1649113217
Short name T439
Test name
Test status
Simulation time 3887238292 ps
CPU time 4.33 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:21 PM PDT 24
Peak memory 206784 kb
Host smart-c048345e-a7ff-4134-8de3-eb3bbcfb0949
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1649113217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.1649113217
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1482481650
Short name T44
Test name
Test status
Simulation time 13346238399 ps
CPU time 12.81 seconds
Started Jul 18 05:48:21 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 206748 kb
Host smart-e15767e6-9216-41f0-b279-0bfdd45b7a8e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1482481650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1482481650
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3220250593
Short name T606
Test name
Test status
Simulation time 23317283442 ps
CPU time 26.07 seconds
Started Jul 18 05:48:21 PM PDT 24
Finished Jul 18 05:48:54 PM PDT 24
Peak memory 206716 kb
Host smart-c6cbac69-f421-4af9-9a0a-6e6740a97d96
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3220250593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3220250593
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.2699594108
Short name T538
Test name
Test status
Simulation time 193374592 ps
CPU time 0.87 seconds
Started Jul 18 05:48:15 PM PDT 24
Finished Jul 18 05:48:24 PM PDT 24
Peak memory 206652 kb
Host smart-e67b915e-bc88-4da2-9222-689722a640cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26995
94108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.2699594108
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1685568567
Short name T457
Test name
Test status
Simulation time 156181367 ps
CPU time 0.76 seconds
Started Jul 18 05:48:22 PM PDT 24
Finished Jul 18 05:48:29 PM PDT 24
Peak memory 206516 kb
Host smart-15e0e51f-6ba5-49d3-a62d-73cfe5f9b891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16855
68567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1685568567
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.2616668606
Short name T1305
Test name
Test status
Simulation time 178001238 ps
CPU time 0.85 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:12 PM PDT 24
Peak memory 206608 kb
Host smart-2a0938a0-6b35-430b-b32f-eb52cedd8c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26166
68606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.2616668606
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.4240855441
Short name T16
Test name
Test status
Simulation time 1374947533 ps
CPU time 3.01 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:28 PM PDT 24
Peak memory 206724 kb
Host smart-9d57ced5-1cde-47e6-8921-eb8c829f496b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42408
55441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.4240855441
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1426165184
Short name T2373
Test name
Test status
Simulation time 12595832693 ps
CPU time 23.79 seconds
Started Jul 18 05:48:18 PM PDT 24
Finished Jul 18 05:48:49 PM PDT 24
Peak memory 206892 kb
Host smart-f9dd6cbe-2877-40b5-9005-f0cb9c2cfc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14261
65184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1426165184
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1968149377
Short name T818
Test name
Test status
Simulation time 420379435 ps
CPU time 1.5 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:18 PM PDT 24
Peak memory 206616 kb
Host smart-e0632c5b-2f63-455f-91f2-57965ecc1f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19681
49377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1968149377
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3694837291
Short name T2115
Test name
Test status
Simulation time 143522347 ps
CPU time 0.75 seconds
Started Jul 18 05:48:16 PM PDT 24
Finished Jul 18 05:48:25 PM PDT 24
Peak memory 206660 kb
Host smart-57c6cfa2-0f73-4d1e-bc37-fa1be9e66785
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
37291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3694837291
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.2137620688
Short name T1219
Test name
Test status
Simulation time 35022446 ps
CPU time 0.74 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:16 PM PDT 24
Peak memory 206644 kb
Host smart-28eee271-e17c-4953-adca-1749a6f9eeb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21376
20688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.2137620688
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.502036628
Short name T1362
Test name
Test status
Simulation time 764368978 ps
CPU time 1.88 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:22 PM PDT 24
Peak memory 206740 kb
Host smart-18463ff9-96ac-491c-89c3-84f48ea1ae74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50203
6628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.502036628
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.3917989039
Short name T1234
Test name
Test status
Simulation time 178784540 ps
CPU time 1.56 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:21 PM PDT 24
Peak memory 206732 kb
Host smart-eadb5a9a-552a-4192-9597-dea3e3dce4b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39179
89039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.3917989039
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.114711070
Short name T1010
Test name
Test status
Simulation time 240055983 ps
CPU time 0.88 seconds
Started Jul 18 05:48:07 PM PDT 24
Finished Jul 18 05:48:12 PM PDT 24
Peak memory 206644 kb
Host smart-597ac874-752a-4c11-9ff0-52f15af3d4ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11471
1070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.114711070
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1419948251
Short name T1009
Test name
Test status
Simulation time 134827172 ps
CPU time 0.76 seconds
Started Jul 18 05:48:08 PM PDT 24
Finished Jul 18 05:48:14 PM PDT 24
Peak memory 206640 kb
Host smart-eb306372-3e93-4def-9309-054d081f193d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14199
48251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1419948251
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1465800069
Short name T813
Test name
Test status
Simulation time 171070734 ps
CPU time 0.84 seconds
Started Jul 18 05:48:14 PM PDT 24
Finished Jul 18 05:48:22 PM PDT 24
Peak memory 206620 kb
Host smart-02bf936b-a8b4-485c-a21e-98534c443e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14658
00069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1465800069
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.3434935250
Short name T655
Test name
Test status
Simulation time 7986252478 ps
CPU time 70.82 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206928 kb
Host smart-d7113c91-37e0-46ef-ae9c-5658c0823de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34349
35250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.3434935250
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1742751023
Short name T2125
Test name
Test status
Simulation time 216228922 ps
CPU time 0.83 seconds
Started Jul 18 05:48:16 PM PDT 24
Finished Jul 18 05:48:24 PM PDT 24
Peak memory 206656 kb
Host smart-34d4567b-4a38-4178-bddc-c828770ced5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17427
51023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1742751023
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.4260433272
Short name T1985
Test name
Test status
Simulation time 23342538505 ps
CPU time 29.85 seconds
Started Jul 18 05:48:08 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206768 kb
Host smart-7d090e19-9c6b-4e02-a972-56ab839512d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42604
33272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.4260433272
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2187788208
Short name T2481
Test name
Test status
Simulation time 3356251467 ps
CPU time 3.5 seconds
Started Jul 18 05:48:15 PM PDT 24
Finished Jul 18 05:48:26 PM PDT 24
Peak memory 206724 kb
Host smart-f3110ae8-14dc-4f4a-b0a6-8ee93ac68d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21877
88208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2187788208
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.579996774
Short name T2239
Test name
Test status
Simulation time 6737775334 ps
CPU time 48.53 seconds
Started Jul 18 05:48:14 PM PDT 24
Finished Jul 18 05:49:10 PM PDT 24
Peak memory 206908 kb
Host smart-2a0622c9-9127-4df6-bffd-5bef5abef1c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57999
6774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.579996774
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3247876294
Short name T352
Test name
Test status
Simulation time 4132628204 ps
CPU time 29.61 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:54 PM PDT 24
Peak memory 206892 kb
Host smart-88646db3-98cd-441b-a74b-5f36dfb58cb5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3247876294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3247876294
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.4057506969
Short name T391
Test name
Test status
Simulation time 239285660 ps
CPU time 0.86 seconds
Started Jul 18 05:48:16 PM PDT 24
Finished Jul 18 05:48:25 PM PDT 24
Peak memory 206656 kb
Host smart-9e88ec49-4228-41a3-bab2-ce512d516bf4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4057506969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.4057506969
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3209267757
Short name T1951
Test name
Test status
Simulation time 197281793 ps
CPU time 0.87 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206648 kb
Host smart-ae0e9047-8d39-47e9-b795-77330724a9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32092
67757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3209267757
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.3426570931
Short name T936
Test name
Test status
Simulation time 3992379836 ps
CPU time 111.02 seconds
Started Jul 18 05:48:14 PM PDT 24
Finished Jul 18 05:50:12 PM PDT 24
Peak memory 206844 kb
Host smart-cb858fe6-e60f-49b2-997f-4818a9045d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34265
70931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.3426570931
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1649983946
Short name T1284
Test name
Test status
Simulation time 4548531204 ps
CPU time 128.52 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:50:33 PM PDT 24
Peak memory 206832 kb
Host smart-5718218a-ae04-4df2-a44c-b05f8e60d7f6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1649983946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1649983946
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.982829777
Short name T1333
Test name
Test status
Simulation time 146551710 ps
CPU time 0.77 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:25 PM PDT 24
Peak memory 206632 kb
Host smart-7d52004e-ef08-4b5f-a6eb-10ac2bdbc337
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=982829777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.982829777
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3300879935
Short name T2403
Test name
Test status
Simulation time 154509620 ps
CPU time 0.76 seconds
Started Jul 18 05:48:14 PM PDT 24
Finished Jul 18 05:48:22 PM PDT 24
Peak memory 206624 kb
Host smart-3dbc7b6e-346b-4d60-88e4-9e8c433c8748
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33008
79935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3300879935
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3693862234
Short name T1764
Test name
Test status
Simulation time 238809193 ps
CPU time 0.92 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:25 PM PDT 24
Peak memory 206640 kb
Host smart-d4e5938d-2a7b-4e9b-9b2f-b2d1d72e76c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36938
62234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3693862234
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.4198929079
Short name T1434
Test name
Test status
Simulation time 160401517 ps
CPU time 0.83 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:26 PM PDT 24
Peak memory 206636 kb
Host smart-9e4670f9-75f9-499a-b094-fdff06bf0f4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41989
29079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.4198929079
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.4150495327
Short name T2197
Test name
Test status
Simulation time 180836537 ps
CPU time 0.85 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206652 kb
Host smart-1b272dad-15c4-4a82-9519-1b83ec520831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41504
95327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.4150495327
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.3889336167
Short name T1392
Test name
Test status
Simulation time 157605900 ps
CPU time 0.79 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:22 PM PDT 24
Peak memory 206640 kb
Host smart-b8252a5b-5074-4190-824a-4f10ee8d66e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38893
36167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.3889336167
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1951025508
Short name T1982
Test name
Test status
Simulation time 233813612 ps
CPU time 0.86 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206668 kb
Host smart-31d905f6-7d6e-48e8-9695-0bc2f58aa81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19510
25508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1951025508
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1526643110
Short name T647
Test name
Test status
Simulation time 237740156 ps
CPU time 1.01 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206672 kb
Host smart-3264d082-b4a1-4492-8262-55afe9e7d042
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1526643110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1526643110
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2014187164
Short name T1625
Test name
Test status
Simulation time 173781559 ps
CPU time 0.82 seconds
Started Jul 18 05:48:11 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206640 kb
Host smart-66cc2498-ed28-4db6-b9c3-f51b72371974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20141
87164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2014187164
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.1045249092
Short name T1577
Test name
Test status
Simulation time 52701067 ps
CPU time 0.71 seconds
Started Jul 18 05:48:19 PM PDT 24
Finished Jul 18 05:48:27 PM PDT 24
Peak memory 206648 kb
Host smart-57d590fc-d922-4b41-919f-2559dcdbf6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10452
49092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.1045249092
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.4014767488
Short name T1049
Test name
Test status
Simulation time 7046566837 ps
CPU time 17.43 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:38 PM PDT 24
Peak memory 206684 kb
Host smart-603529c7-cefb-4572-9ce0-5a16155d4e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40147
67488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.4014767488
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.3919107526
Short name T1634
Test name
Test status
Simulation time 178926894 ps
CPU time 0.81 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:21 PM PDT 24
Peak memory 206304 kb
Host smart-098f1ba5-7f20-40cc-ae67-afa36cfd6bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39191
07526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.3919107526
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.1684790019
Short name T2015
Test name
Test status
Simulation time 200348965 ps
CPU time 0.87 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206668 kb
Host smart-80880b99-6c7a-4684-bffd-241af2cdfe34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16847
90019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.1684790019
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.1058969710
Short name T407
Test name
Test status
Simulation time 198045266 ps
CPU time 0.91 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:22 PM PDT 24
Peak memory 206072 kb
Host smart-c1f1c174-1837-4527-9bcb-d4cf919a07dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10589
69710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.1058969710
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.4203472513
Short name T2370
Test name
Test status
Simulation time 243858161 ps
CPU time 1 seconds
Started Jul 18 05:48:12 PM PDT 24
Finished Jul 18 05:48:20 PM PDT 24
Peak memory 206616 kb
Host smart-db816589-f4bb-4c8f-8d8a-8fb10a2779f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42034
72513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.4203472513
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.1463006774
Short name T2646
Test name
Test status
Simulation time 150969370 ps
CPU time 0.78 seconds
Started Jul 18 05:48:06 PM PDT 24
Finished Jul 18 05:48:11 PM PDT 24
Peak memory 206640 kb
Host smart-eea66c70-188a-45d9-8795-d53287dacb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14630
06774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.1463006774
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.3181506330
Short name T1218
Test name
Test status
Simulation time 184691975 ps
CPU time 0.88 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:26 PM PDT 24
Peak memory 206608 kb
Host smart-0ed1f6aa-0ed0-4638-a5bf-79ba68149f79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31815
06330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.3181506330
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3898876727
Short name T387
Test name
Test status
Simulation time 163499385 ps
CPU time 0.85 seconds
Started Jul 18 05:48:10 PM PDT 24
Finished Jul 18 05:48:17 PM PDT 24
Peak memory 206632 kb
Host smart-57df5441-e007-433e-8e1e-cf384dede8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38988
76727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3898876727
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.999070624
Short name T1702
Test name
Test status
Simulation time 238183717 ps
CPU time 0.98 seconds
Started Jul 18 05:48:22 PM PDT 24
Finished Jul 18 05:48:29 PM PDT 24
Peak memory 206612 kb
Host smart-cb1052ea-dc56-480d-adf8-41d9f63a54a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99907
0624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.999070624
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.930873637
Short name T2753
Test name
Test status
Simulation time 6625921227 ps
CPU time 50.37 seconds
Started Jul 18 05:48:06 PM PDT 24
Finished Jul 18 05:48:59 PM PDT 24
Peak memory 206892 kb
Host smart-71d1b995-145c-4c1b-8ba5-9fafc9279571
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=930873637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.930873637
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1098249194
Short name T1229
Test name
Test status
Simulation time 153801004 ps
CPU time 0.81 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:22 PM PDT 24
Peak memory 206632 kb
Host smart-4c988693-9136-44f2-93c2-55318f357306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10982
49194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1098249194
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3592748389
Short name T1355
Test name
Test status
Simulation time 190822743 ps
CPU time 0.84 seconds
Started Jul 18 05:48:18 PM PDT 24
Finished Jul 18 05:48:26 PM PDT 24
Peak memory 206636 kb
Host smart-45065d01-8020-4167-b36e-d76ef43a08a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35927
48389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3592748389
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3668250536
Short name T2407
Test name
Test status
Simulation time 1326916433 ps
CPU time 2.54 seconds
Started Jul 18 05:48:22 PM PDT 24
Finished Jul 18 05:48:30 PM PDT 24
Peak memory 206672 kb
Host smart-f40adf8d-8c62-4d98-885c-f8a40c417c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36682
50536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3668250536
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.2330612194
Short name T1541
Test name
Test status
Simulation time 5315568983 ps
CPU time 38.39 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:58 PM PDT 24
Peak memory 206920 kb
Host smart-d18e965c-32c2-49d2-a58d-d414df53cd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23306
12194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.2330612194
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3487320001
Short name T2075
Test name
Test status
Simulation time 39443261 ps
CPU time 0.69 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206696 kb
Host smart-cdc733d6-9d0d-4174-bb12-4a547f3de82a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3487320001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3487320001
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.3829403062
Short name T960
Test name
Test status
Simulation time 3905569708 ps
CPU time 4.67 seconds
Started Jul 18 05:48:18 PM PDT 24
Finished Jul 18 05:48:30 PM PDT 24
Peak memory 206700 kb
Host smart-5961b54a-27f4-4061-a311-dce5ab90b645
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3829403062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.3829403062
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.1452212956
Short name T2420
Test name
Test status
Simulation time 13439639515 ps
CPU time 12.74 seconds
Started Jul 18 05:48:16 PM PDT 24
Finished Jul 18 05:48:36 PM PDT 24
Peak memory 206924 kb
Host smart-a8eb1905-d145-42ea-9886-158a86588596
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1452212956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.1452212956
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1420827473
Short name T1631
Test name
Test status
Simulation time 23353247369 ps
CPU time 21.88 seconds
Started Jul 18 05:48:13 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 206920 kb
Host smart-a7e1ba2e-f9a3-49d4-a2f0-97d56e8a3e67
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1420827473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1420827473
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2388397022
Short name T1502
Test name
Test status
Simulation time 160382210 ps
CPU time 0.75 seconds
Started Jul 18 05:48:17 PM PDT 24
Finished Jul 18 05:48:25 PM PDT 24
Peak memory 206656 kb
Host smart-2e3d0432-a41b-4787-ab98-5b7a1b4dd937
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23883
97022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2388397022
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2379326937
Short name T1677
Test name
Test status
Simulation time 140577672 ps
CPU time 0.76 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:35 PM PDT 24
Peak memory 206656 kb
Host smart-6ce1ae9a-a2ff-4693-bc48-c9d1e3dee5b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23793
26937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2379326937
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2018091008
Short name T2457
Test name
Test status
Simulation time 292078643 ps
CPU time 1.1 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:33 PM PDT 24
Peak memory 206608 kb
Host smart-ce1bc539-d9a8-4ada-adb9-78d997f56584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
91008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2018091008
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.136322852
Short name T410
Test name
Test status
Simulation time 1194058418 ps
CPU time 2.5 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:37 PM PDT 24
Peak memory 206788 kb
Host smart-2afb6987-894b-42db-b76c-6c19d8461942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13632
2852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.136322852
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.949596239
Short name T1730
Test name
Test status
Simulation time 17623476200 ps
CPU time 32.35 seconds
Started Jul 18 05:48:25 PM PDT 24
Finished Jul 18 05:49:02 PM PDT 24
Peak memory 206888 kb
Host smart-9cb8866d-fe50-4e89-ba52-7ed20ea6d4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94959
6239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.949596239
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.2364134622
Short name T1497
Test name
Test status
Simulation time 401745923 ps
CPU time 1.32 seconds
Started Jul 18 05:48:36 PM PDT 24
Finished Jul 18 05:48:45 PM PDT 24
Peak memory 206668 kb
Host smart-22e3e022-e0bd-4c58-a7d9-4ff967311ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23641
34622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.2364134622
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.3493302224
Short name T1119
Test name
Test status
Simulation time 129167260 ps
CPU time 0.74 seconds
Started Jul 18 05:48:39 PM PDT 24
Finished Jul 18 05:48:48 PM PDT 24
Peak memory 206620 kb
Host smart-68211bf5-429e-4a36-81a1-7eb656799d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34933
02224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.3493302224
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.3464084890
Short name T449
Test name
Test status
Simulation time 38718862 ps
CPU time 0.68 seconds
Started Jul 18 05:48:31 PM PDT 24
Finished Jul 18 05:48:39 PM PDT 24
Peak memory 206604 kb
Host smart-51366133-b09e-43d4-a97c-3197c62d5080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34640
84890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.3464084890
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3661928580
Short name T2543
Test name
Test status
Simulation time 1096556310 ps
CPU time 2.62 seconds
Started Jul 18 05:48:31 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 206736 kb
Host smart-1c7d59ce-0dc2-4112-8902-194d4856aafa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36619
28580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3661928580
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.3299792074
Short name T178
Test name
Test status
Simulation time 237404778 ps
CPU time 1.5 seconds
Started Jul 18 05:48:26 PM PDT 24
Finished Jul 18 05:48:32 PM PDT 24
Peak memory 206776 kb
Host smart-a6b147f1-3e4c-49ca-b72d-4776e0f56c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32997
92074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.3299792074
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3228954050
Short name T2504
Test name
Test status
Simulation time 158121630 ps
CPU time 0.84 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:43 PM PDT 24
Peak memory 206616 kb
Host smart-915118f7-fc04-45dc-9dc9-7ad61042e0b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
54050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3228954050
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.3340122073
Short name T2683
Test name
Test status
Simulation time 135093383 ps
CPU time 0.81 seconds
Started Jul 18 05:48:27 PM PDT 24
Finished Jul 18 05:48:33 PM PDT 24
Peak memory 206652 kb
Host smart-bdf940b5-102f-4487-84e2-a20fb057b8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33401
22073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.3340122073
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.3182221785
Short name T2187
Test name
Test status
Simulation time 237930474 ps
CPU time 0.94 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:48:36 PM PDT 24
Peak memory 206656 kb
Host smart-6c3007c1-0421-4fc0-ab2d-5774a44ac996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31822
21785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.3182221785
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3091254088
Short name T72
Test name
Test status
Simulation time 9291833353 ps
CPU time 87.33 seconds
Started Jul 18 05:48:27 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206904 kb
Host smart-f6f54fb9-7265-41e5-9acc-7fa9d22e89c9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3091254088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3091254088
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.2706531483
Short name T443
Test name
Test status
Simulation time 187071506 ps
CPU time 0.83 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:39 PM PDT 24
Peak memory 206612 kb
Host smart-ef67b90a-1053-4323-a161-457df437916e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27065
31483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.2706531483
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3121421443
Short name T1545
Test name
Test status
Simulation time 23353577429 ps
CPU time 26.52 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206776 kb
Host smart-7f9427fe-605c-43e3-a610-77b0cfe4da37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31214
21443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3121421443
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.753277219
Short name T1703
Test name
Test status
Simulation time 3274323023 ps
CPU time 3.6 seconds
Started Jul 18 05:48:26 PM PDT 24
Finished Jul 18 05:48:34 PM PDT 24
Peak memory 206684 kb
Host smart-a654f1b3-4282-42f6-beba-a324908130a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75327
7219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.753277219
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2876154036
Short name T924
Test name
Test status
Simulation time 9854287812 ps
CPU time 78.41 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:49:53 PM PDT 24
Peak memory 206644 kb
Host smart-81e7deac-f9bd-4acb-919c-3fc2afb8a3d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28761
54036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2876154036
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.112372674
Short name T1374
Test name
Test status
Simulation time 4549697621 ps
CPU time 45.09 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:49:17 PM PDT 24
Peak memory 206904 kb
Host smart-84dc06ba-9277-4f33-b657-e20eab4b53c4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=112372674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.112372674
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.21076878
Short name T390
Test name
Test status
Simulation time 238607105 ps
CPU time 0.95 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:48 PM PDT 24
Peak memory 206620 kb
Host smart-361cf950-b56b-4ca8-806a-668637d336fa
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=21076878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.21076878
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.2835410962
Short name T2595
Test name
Test status
Simulation time 206638714 ps
CPU time 0.9 seconds
Started Jul 18 05:48:26 PM PDT 24
Finished Jul 18 05:48:31 PM PDT 24
Peak memory 206648 kb
Host smart-456cd3ed-0fb4-4cfb-ac77-c86aa3feacf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28354
10962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.2835410962
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3121270725
Short name T495
Test name
Test status
Simulation time 5873512093 ps
CPU time 173 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:51:32 PM PDT 24
Peak memory 206644 kb
Host smart-513788f7-d5f5-46cf-af07-577680579756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31212
70725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3121270725
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1550125751
Short name T868
Test name
Test status
Simulation time 7445399324 ps
CPU time 217.08 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:52:24 PM PDT 24
Peak memory 206864 kb
Host smart-36e61b8f-b0a8-4c85-b4fe-3b73d2358087
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1550125751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1550125751
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2528035539
Short name T2587
Test name
Test status
Simulation time 157575272 ps
CPU time 0.8 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:40 PM PDT 24
Peak memory 206380 kb
Host smart-ba4c5d54-1a17-4c4a-9b9c-989e5cc1960d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2528035539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2528035539
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.432401441
Short name T304
Test name
Test status
Simulation time 148702862 ps
CPU time 0.83 seconds
Started Jul 18 05:48:26 PM PDT 24
Finished Jul 18 05:48:32 PM PDT 24
Peak memory 206632 kb
Host smart-abb191fa-db8d-4baf-9f3c-8a24b109981f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43240
1441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.432401441
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3980605757
Short name T1605
Test name
Test status
Simulation time 173960083 ps
CPU time 0.86 seconds
Started Jul 18 05:48:31 PM PDT 24
Finished Jul 18 05:48:39 PM PDT 24
Peak memory 206652 kb
Host smart-1796dca8-d08d-47e9-9029-fbd34a0f4522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39806
05757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3980605757
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1728765125
Short name T1570
Test name
Test status
Simulation time 184390929 ps
CPU time 0.81 seconds
Started Jul 18 05:48:39 PM PDT 24
Finished Jul 18 05:48:49 PM PDT 24
Peak memory 206648 kb
Host smart-a1c8d94a-21b5-4223-8b87-04712ba0057d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17287
65125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1728765125
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3567334648
Short name T2095
Test name
Test status
Simulation time 175852622 ps
CPU time 0.78 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:36 PM PDT 24
Peak memory 206648 kb
Host smart-3879fd47-7123-48c0-9426-492ae93c3af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35673
34648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3567334648
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.556884339
Short name T338
Test name
Test status
Simulation time 176671588 ps
CPU time 0.8 seconds
Started Jul 18 05:48:26 PM PDT 24
Finished Jul 18 05:48:31 PM PDT 24
Peak memory 206656 kb
Host smart-e9c9df12-c759-4f82-849d-c6b22560f66e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55688
4339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.556884339
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.2962340787
Short name T633
Test name
Test status
Simulation time 154128324 ps
CPU time 0.79 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:33 PM PDT 24
Peak memory 206656 kb
Host smart-228cf270-742e-4081-b5cf-3ef328ca8f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29623
40787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.2962340787
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.346389258
Short name T1620
Test name
Test status
Simulation time 249154224 ps
CPU time 1.07 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:43 PM PDT 24
Peak memory 206648 kb
Host smart-c6b3d3dc-0c1f-4905-9446-945cfee3f09c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=346389258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.346389258
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3912806617
Short name T1091
Test name
Test status
Simulation time 150300111 ps
CPU time 0.82 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:48:37 PM PDT 24
Peak memory 206632 kb
Host smart-ddc96741-8ed8-4bef-b44f-58a9e0f2c55a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39128
06617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3912806617
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1965658003
Short name T383
Test name
Test status
Simulation time 42464681 ps
CPU time 0.71 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:48:35 PM PDT 24
Peak memory 206636 kb
Host smart-fa5f5ffe-31f4-4678-a89b-709bf03c8138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19656
58003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1965658003
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1979762588
Short name T557
Test name
Test status
Simulation time 19773787140 ps
CPU time 42.04 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:49:29 PM PDT 24
Peak memory 206892 kb
Host smart-4b202e0b-eb44-4ffd-8c0b-94c3c7c20305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19797
62588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1979762588
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.1377522
Short name T582
Test name
Test status
Simulation time 196246699 ps
CPU time 0.88 seconds
Started Jul 18 05:48:26 PM PDT 24
Finished Jul 18 05:48:32 PM PDT 24
Peak memory 206644 kb
Host smart-4dcf3a4f-814c-4078-aca8-77b594265575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13775
22 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.1377522
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.2653349911
Short name T1299
Test name
Test status
Simulation time 176822695 ps
CPU time 0.83 seconds
Started Jul 18 05:48:25 PM PDT 24
Finished Jul 18 05:48:31 PM PDT 24
Peak memory 206648 kb
Host smart-2a250737-03b3-46fb-ac04-88eff118b7eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26533
49911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.2653349911
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1312519816
Short name T297
Test name
Test status
Simulation time 173626237 ps
CPU time 0.84 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 206464 kb
Host smart-66ef39da-a182-4a2e-8a94-3820c9918519
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13125
19816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1312519816
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3223839734
Short name T1633
Test name
Test status
Simulation time 172066179 ps
CPU time 0.84 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206584 kb
Host smart-e0e80794-5fb0-4532-a1b2-c13cb1e02ff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
39734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3223839734
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3997024245
Short name T520
Test name
Test status
Simulation time 190627898 ps
CPU time 0.82 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:35 PM PDT 24
Peak memory 206620 kb
Host smart-3762dedf-9fcf-47ae-bdf2-fb483ae5a6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39970
24245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3997024245
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.2994430072
Short name T1104
Test name
Test status
Simulation time 176112054 ps
CPU time 0.78 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:48:38 PM PDT 24
Peak memory 206616 kb
Host smart-8403e14c-ef01-485f-9d3c-c24250855d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29944
30072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.2994430072
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1538182193
Short name T1321
Test name
Test status
Simulation time 155892796 ps
CPU time 0.8 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:39 PM PDT 24
Peak memory 206628 kb
Host smart-f4e2eac7-70d6-4617-9093-5b6596f32b73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15381
82193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1538182193
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1942821603
Short name T1340
Test name
Test status
Simulation time 195377733 ps
CPU time 0.87 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:48:36 PM PDT 24
Peak memory 206800 kb
Host smart-d6b93315-cd1b-44dd-9f44-c5f37fe14c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19428
21603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1942821603
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.4033371041
Short name T2554
Test name
Test status
Simulation time 4646571564 ps
CPU time 33.85 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:49:10 PM PDT 24
Peak memory 207056 kb
Host smart-2be67a04-1ef1-48c3-9c13-4c3650a485ba
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4033371041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.4033371041
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3211830565
Short name T1204
Test name
Test status
Simulation time 222896657 ps
CPU time 0.83 seconds
Started Jul 18 05:48:27 PM PDT 24
Finished Jul 18 05:48:33 PM PDT 24
Peak memory 206652 kb
Host smart-91497280-a9da-46a6-8284-304302e3c1f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32118
30565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3211830565
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.2184440694
Short name T1317
Test name
Test status
Simulation time 215284080 ps
CPU time 0.82 seconds
Started Jul 18 05:48:27 PM PDT 24
Finished Jul 18 05:48:32 PM PDT 24
Peak memory 206648 kb
Host smart-b71896f2-e1ee-4121-882b-2172dccdea29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21844
40694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.2184440694
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.881644479
Short name T315
Test name
Test status
Simulation time 898928895 ps
CPU time 2.07 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 206752 kb
Host smart-1b4cd2b4-532f-44b2-b6c3-d5312851a8ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88164
4479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.881644479
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.3682884802
Short name T147
Test name
Test status
Simulation time 3958319186 ps
CPU time 102.75 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206820 kb
Host smart-5e8e9c98-7b24-44fe-a77f-1f390ca7a1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36828
84802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.3682884802
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3389920365
Short name T1746
Test name
Test status
Simulation time 97939951 ps
CPU time 0.75 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:35 PM PDT 24
Peak memory 206708 kb
Host smart-d6a62985-81fa-4d27-b8fb-3371fed87923
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3389920365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3389920365
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1141787869
Short name T2745
Test name
Test status
Simulation time 3539474479 ps
CPU time 4.36 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:51 PM PDT 24
Peak memory 206768 kb
Host smart-0b466285-0dfb-4f92-a88b-4c26e329aaf4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1141787869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1141787869
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.839275672
Short name T2146
Test name
Test status
Simulation time 13368722148 ps
CPU time 12.07 seconds
Started Jul 18 05:48:33 PM PDT 24
Finished Jul 18 05:48:52 PM PDT 24
Peak memory 206920 kb
Host smart-d25d7eb5-29d3-4a05-b3f1-61304c2ca4b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=839275672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.839275672
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.231849257
Short name T2647
Test name
Test status
Simulation time 23500714763 ps
CPU time 25.32 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:49:02 PM PDT 24
Peak memory 206868 kb
Host smart-d33e582a-8069-467b-8f9d-57d6bba0c476
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=231849257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.231849257
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.405188691
Short name T548
Test name
Test status
Simulation time 200352675 ps
CPU time 0.89 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:34 PM PDT 24
Peak memory 206648 kb
Host smart-9564a5ad-849b-4848-8551-64fc751b06e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40518
8691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.405188691
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.2612175780
Short name T1364
Test name
Test status
Simulation time 168748591 ps
CPU time 0.87 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:48:36 PM PDT 24
Peak memory 206644 kb
Host smart-4c57261f-bfcf-4040-af8c-1e82488eb57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
75780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.2612175780
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.228560625
Short name T1294
Test name
Test status
Simulation time 459359291 ps
CPU time 1.49 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:34 PM PDT 24
Peak memory 206600 kb
Host smart-efdd8983-c0a6-4928-af51-86d8c6bb744b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22856
0625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.228560625
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.321577338
Short name T786
Test name
Test status
Simulation time 1309114273 ps
CPU time 2.9 seconds
Started Jul 18 05:48:39 PM PDT 24
Finished Jul 18 05:48:51 PM PDT 24
Peak memory 206788 kb
Host smart-60952a06-ad8e-4310-92e4-43a4156f50c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32157
7338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.321577338
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.876178330
Short name T690
Test name
Test status
Simulation time 7504931367 ps
CPU time 15.54 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:48:52 PM PDT 24
Peak memory 206856 kb
Host smart-26d80b3e-7849-4158-b9f7-1cca47187b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87617
8330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.876178330
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3940062973
Short name T1027
Test name
Test status
Simulation time 467481131 ps
CPU time 1.4 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:40 PM PDT 24
Peak memory 206644 kb
Host smart-8683d14d-e902-4a65-ac2f-6a47fe6d9991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39400
62973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3940062973
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1595057728
Short name T2593
Test name
Test status
Simulation time 174458880 ps
CPU time 0.79 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206624 kb
Host smart-450b7a01-b76c-40bb-a650-8cc1d994e8e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15950
57728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1595057728
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.4056495084
Short name T760
Test name
Test status
Simulation time 36664301 ps
CPU time 0.65 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206612 kb
Host smart-caa2bbbf-42eb-4685-b256-369318004d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40564
95084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.4056495084
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1739141032
Short name T1913
Test name
Test status
Simulation time 931930938 ps
CPU time 2.41 seconds
Started Jul 18 05:48:31 PM PDT 24
Finished Jul 18 05:48:40 PM PDT 24
Peak memory 206736 kb
Host smart-5c7cbe84-e755-49a1-b867-4597b4797096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17391
41032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1739141032
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3419765775
Short name T558
Test name
Test status
Simulation time 365034693 ps
CPU time 2.33 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206648 kb
Host smart-14f1f1e3-6928-48bc-9eaf-a800fa8f5e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
65775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3419765775
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.536484058
Short name T567
Test name
Test status
Simulation time 258133910 ps
CPU time 0.89 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:48:37 PM PDT 24
Peak memory 206636 kb
Host smart-7410ba64-1eae-4906-9500-da9a225c7168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53648
4058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.536484058
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1462124591
Short name T1526
Test name
Test status
Simulation time 146499053 ps
CPU time 0.76 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:48:37 PM PDT 24
Peak memory 206624 kb
Host smart-682524d3-682a-4632-8db0-ffb504abc2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14621
24591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1462124591
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3882425063
Short name T2291
Test name
Test status
Simulation time 194884061 ps
CPU time 0.9 seconds
Started Jul 18 05:48:41 PM PDT 24
Finished Jul 18 05:48:50 PM PDT 24
Peak memory 206108 kb
Host smart-d4510d47-efae-418e-b6c8-59210f2e66db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38824
25063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3882425063
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.4086599758
Short name T2700
Test name
Test status
Simulation time 13060165739 ps
CPU time 43.71 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:49:30 PM PDT 24
Peak memory 206668 kb
Host smart-6e026aa1-565c-4e84-a198-8ca808751cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
99758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.4086599758
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1495556412
Short name T1694
Test name
Test status
Simulation time 287884221 ps
CPU time 0.95 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:48 PM PDT 24
Peak memory 206636 kb
Host smart-1149c0a8-2cfa-4c61-9af7-c8c9678f6be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
56412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1495556412
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.225274605
Short name T1835
Test name
Test status
Simulation time 23402743094 ps
CPU time 24.31 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206716 kb
Host smart-4d11f008-63e3-49f0-b560-1ec069308f5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
4605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.225274605
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.778321063
Short name T2310
Test name
Test status
Simulation time 3298947472 ps
CPU time 3.8 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:50 PM PDT 24
Peak memory 206328 kb
Host smart-afcf9d6d-871f-4895-b65e-0ec22603cfac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77832
1063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.778321063
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.414036515
Short name T2256
Test name
Test status
Simulation time 8840494429 ps
CPU time 86.06 seconds
Started Jul 18 05:48:34 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206888 kb
Host smart-ce54f413-f213-4137-a35a-d3a2af57415f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41403
6515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.414036515
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3053056491
Short name T602
Test name
Test status
Simulation time 5054785567 ps
CPU time 132.74 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:50:59 PM PDT 24
Peak memory 206924 kb
Host smart-e9211118-9e31-4bce-aeac-d1141802f07e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3053056491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3053056491
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.3080910633
Short name T1114
Test name
Test status
Simulation time 239335535 ps
CPU time 0.97 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:45 PM PDT 24
Peak memory 206632 kb
Host smart-24900a74-18e2-4bf3-aa05-e8f225079707
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3080910633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.3080910633
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3234260358
Short name T2561
Test name
Test status
Simulation time 199371215 ps
CPU time 0.93 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206632 kb
Host smart-7040cd75-d04b-4d74-9fc3-4a7a8108cb08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32342
60358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3234260358
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3850802256
Short name T869
Test name
Test status
Simulation time 6176851097 ps
CPU time 157.16 seconds
Started Jul 18 05:48:36 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206828 kb
Host smart-63af58ef-216a-461d-9a90-b56c26840903
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508
02256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3850802256
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.4082356034
Short name T1873
Test name
Test status
Simulation time 5001741378 ps
CPU time 36.56 seconds
Started Jul 18 05:49:04 PM PDT 24
Finished Jul 18 05:49:45 PM PDT 24
Peak memory 206864 kb
Host smart-58a29764-5e24-40d6-8c4b-76aec17a6e1b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4082356034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.4082356034
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.2551734259
Short name T2692
Test name
Test status
Simulation time 171054760 ps
CPU time 0.83 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:48:38 PM PDT 24
Peak memory 206648 kb
Host smart-85497269-0e47-42ca-8486-cd519bbe6a0c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2551734259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.2551734259
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2632840313
Short name T1860
Test name
Test status
Simulation time 167165577 ps
CPU time 0.8 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:46 PM PDT 24
Peak memory 206612 kb
Host smart-260fb041-0e1a-4b3c-b5b0-c3f2c92c58fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26328
40313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2632840313
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.72782226
Short name T127
Test name
Test status
Simulation time 234777140 ps
CPU time 0.89 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206640 kb
Host smart-2f3692bf-7e8e-499a-b181-6483052e179e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72782
226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.72782226
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2864466790
Short name T500
Test name
Test status
Simulation time 220422926 ps
CPU time 0.93 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206620 kb
Host smart-47929ea6-7e58-4647-b686-e2d1e166b631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
66790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2864466790
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2377862412
Short name T1618
Test name
Test status
Simulation time 201943862 ps
CPU time 0.91 seconds
Started Jul 18 05:48:36 PM PDT 24
Finished Jul 18 05:48:45 PM PDT 24
Peak memory 206636 kb
Host smart-5bbc8422-9d74-4b30-a49e-de2d784f3f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23778
62412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2377862412
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.585580744
Short name T1001
Test name
Test status
Simulation time 192201121 ps
CPU time 0.81 seconds
Started Jul 18 05:48:40 PM PDT 24
Finished Jul 18 05:48:49 PM PDT 24
Peak memory 206640 kb
Host smart-cdf454fb-8abe-4af7-af4d-cd7553ed240e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58558
0744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.585580744
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.3549861609
Short name T175
Test name
Test status
Simulation time 148144306 ps
CPU time 0.79 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206636 kb
Host smart-a2c89678-85b0-4370-af16-cf03ac2b10a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35498
61609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.3549861609
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3996063671
Short name T2301
Test name
Test status
Simulation time 186803274 ps
CPU time 0.93 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:48:36 PM PDT 24
Peak memory 206356 kb
Host smart-1f99c7dd-ad53-4c7a-a2f7-337015edae38
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3996063671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3996063671
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.4226120647
Short name T979
Test name
Test status
Simulation time 143375503 ps
CPU time 0.78 seconds
Started Jul 18 05:48:40 PM PDT 24
Finished Jul 18 05:48:49 PM PDT 24
Peak memory 206648 kb
Host smart-81e754d6-933d-481c-8249-9699f8ce5f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42261
20647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.4226120647
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2655746480
Short name T1164
Test name
Test status
Simulation time 46387056 ps
CPU time 0.66 seconds
Started Jul 18 05:48:34 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206648 kb
Host smart-8bf9431e-992e-410b-86bd-a3482417ab91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26557
46480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2655746480
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.1961387890
Short name T1121
Test name
Test status
Simulation time 8142507044 ps
CPU time 20.35 seconds
Started Jul 18 05:50:54 PM PDT 24
Finished Jul 18 05:51:30 PM PDT 24
Peak memory 206856 kb
Host smart-03b76ae6-32e8-48be-a82d-d0c850b6c614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19613
87890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.1961387890
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.394506475
Short name T708
Test name
Test status
Simulation time 175209867 ps
CPU time 0.91 seconds
Started Jul 18 05:48:34 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206616 kb
Host smart-dfa2f0cb-1183-4991-b44a-0e624c9285c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39450
6475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.394506475
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.2626848184
Short name T834
Test name
Test status
Simulation time 202948817 ps
CPU time 0.84 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206660 kb
Host smart-879469cb-a8e3-4351-8efb-e7bffedac309
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26268
48184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.2626848184
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.2682153347
Short name T1821
Test name
Test status
Simulation time 239230155 ps
CPU time 0.92 seconds
Started Jul 18 05:48:40 PM PDT 24
Finished Jul 18 05:48:50 PM PDT 24
Peak memory 206652 kb
Host smart-2651e104-649f-4a7f-9926-3ed888b97658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26821
53347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.2682153347
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3087155319
Short name T398
Test name
Test status
Simulation time 161806285 ps
CPU time 0.79 seconds
Started Jul 18 06:03:15 PM PDT 24
Finished Jul 18 06:03:17 PM PDT 24
Peak memory 206640 kb
Host smart-222d0af0-6f5e-4a47-82fb-2286f0966b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30871
55319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3087155319
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.822750058
Short name T2293
Test name
Test status
Simulation time 137976311 ps
CPU time 0.82 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206580 kb
Host smart-1e3e55b2-fe8d-442e-9cec-b8546655d1be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82275
0058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.822750058
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.534062529
Short name T2633
Test name
Test status
Simulation time 148865046 ps
CPU time 0.81 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 206632 kb
Host smart-2d53a4ae-5eaa-4212-8548-012566747367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53406
2529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.534062529
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.2713223404
Short name T2198
Test name
Test status
Simulation time 159075971 ps
CPU time 0.77 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:48 PM PDT 24
Peak memory 206656 kb
Host smart-195b102f-4658-4beb-9791-3c1369b9320f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27132
23404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.2713223404
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2329683881
Short name T767
Test name
Test status
Simulation time 232958586 ps
CPU time 0.97 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206632 kb
Host smart-125f8933-1e35-4fdc-b82e-b2137a18cbcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23296
83881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2329683881
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.833671683
Short name T1964
Test name
Test status
Simulation time 5847862882 ps
CPU time 158.82 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:51:25 PM PDT 24
Peak memory 206844 kb
Host smart-8db7095a-76b3-4daa-927f-19bbef3f4742
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=833671683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.833671683
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.2784951342
Short name T1549
Test name
Test status
Simulation time 204078364 ps
CPU time 0.84 seconds
Started Jul 18 05:48:29 PM PDT 24
Finished Jul 18 05:48:37 PM PDT 24
Peak memory 206648 kb
Host smart-f38a821d-506a-424f-840d-eb5827a73d45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27849
51342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.2784951342
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.3180890899
Short name T2612
Test name
Test status
Simulation time 168274519 ps
CPU time 0.82 seconds
Started Jul 18 05:48:34 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206640 kb
Host smart-e149b15b-0a1c-4fea-99f1-78b0dddb3168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31808
90899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.3180890899
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2213344264
Short name T1084
Test name
Test status
Simulation time 1007497979 ps
CPU time 2.37 seconds
Started Jul 18 05:48:41 PM PDT 24
Finished Jul 18 05:48:52 PM PDT 24
Peak memory 206308 kb
Host smart-da19fa43-13f1-4535-91e2-a2feda00f0a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
44264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2213344264
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.2889700249
Short name T1297
Test name
Test status
Simulation time 4460674746 ps
CPU time 127.57 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206832 kb
Host smart-ab8c8202-6b41-4cfc-b42c-652317209447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28897
00249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.2889700249
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.2929020630
Short name T397
Test name
Test status
Simulation time 38657982 ps
CPU time 0.68 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206668 kb
Host smart-44ed88ea-b76a-4064-848c-39b5d296672a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2929020630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.2929020630
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1303137294
Short name T1798
Test name
Test status
Simulation time 3903395981 ps
CPU time 4.63 seconds
Started Jul 18 05:48:28 PM PDT 24
Finished Jul 18 05:48:37 PM PDT 24
Peak memory 206720 kb
Host smart-89707a2a-4eb6-42e7-ad0a-903b727667e4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1303137294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1303137294
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3996659250
Short name T713
Test name
Test status
Simulation time 13344478468 ps
CPU time 14.18 seconds
Started Jul 18 05:48:39 PM PDT 24
Finished Jul 18 05:49:02 PM PDT 24
Peak memory 206752 kb
Host smart-edc65315-28fc-4dcd-92e9-b5f598046b5d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3996659250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3996659250
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.2519149484
Short name T2539
Test name
Test status
Simulation time 23364381455 ps
CPU time 23.98 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:49:02 PM PDT 24
Peak memory 206752 kb
Host smart-319f5cdb-a2f1-4142-b78d-bf93b6acb299
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2519149484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.2519149484
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.630156393
Short name T1268
Test name
Test status
Simulation time 179069038 ps
CPU time 0.83 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:48:38 PM PDT 24
Peak memory 206592 kb
Host smart-1b8300c6-769a-4b0c-a49f-42e104b709b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63015
6393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.630156393
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.4103619482
Short name T2419
Test name
Test status
Simulation time 145725269 ps
CPU time 0.82 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206644 kb
Host smart-e8cb4fd3-329c-45a2-93f4-d967d81dcde5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41036
19482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.4103619482
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3137982273
Short name T2253
Test name
Test status
Simulation time 370676202 ps
CPU time 1.33 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206608 kb
Host smart-09483ca7-b948-4418-ada5-e387f547168e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31379
82273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3137982273
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2196109734
Short name T459
Test name
Test status
Simulation time 1115787065 ps
CPU time 2.55 seconds
Started Jul 18 05:48:32 PM PDT 24
Finished Jul 18 05:48:41 PM PDT 24
Peak memory 206788 kb
Host smart-02b8da22-0f65-4505-87a8-05eb388fd056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21961
09734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2196109734
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1920004369
Short name T2016
Test name
Test status
Simulation time 421704552 ps
CPU time 1.38 seconds
Started Jul 18 05:48:33 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206644 kb
Host smart-e4ee7c9d-e5bf-4458-99e6-6874785d4c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19200
04369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1920004369
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.1925668912
Short name T36
Test name
Test status
Simulation time 142619734 ps
CPU time 0.78 seconds
Started Jul 18 05:48:27 PM PDT 24
Finished Jul 18 05:48:32 PM PDT 24
Peak memory 206648 kb
Host smart-eaed806f-58d5-4d06-85d6-f8b47128e494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19256
68912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.1925668912
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.1466909210
Short name T1445
Test name
Test status
Simulation time 41046681 ps
CPU time 0.64 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206292 kb
Host smart-db0b879c-ba54-412b-8a43-8b67ce7f65bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14669
09210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.1466909210
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.3621796943
Short name T1575
Test name
Test status
Simulation time 863169312 ps
CPU time 1.91 seconds
Started Jul 18 05:48:30 PM PDT 24
Finished Jul 18 05:48:38 PM PDT 24
Peak memory 206696 kb
Host smart-c990ee85-88e9-47d5-b1a6-4804ba781097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36217
96943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.3621796943
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.1465450629
Short name T1116
Test name
Test status
Simulation time 228750186 ps
CPU time 1.42 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:48 PM PDT 24
Peak memory 206776 kb
Host smart-d9825a9e-3aeb-4129-854a-649c8c6f4e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14654
50629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.1465450629
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.2657036006
Short name T396
Test name
Test status
Simulation time 188302357 ps
CPU time 0.85 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206652 kb
Host smart-e5d0730e-991d-4499-9c72-4f8e87d7edea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26570
36006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.2657036006
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3484015321
Short name T978
Test name
Test status
Simulation time 157504160 ps
CPU time 0.8 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206384 kb
Host smart-685c59c4-4991-42e1-9c3c-a8e376dbd497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34840
15321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3484015321
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.1479232408
Short name T660
Test name
Test status
Simulation time 188930211 ps
CPU time 0.82 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206640 kb
Host smart-6f4c1462-0c69-452c-9120-392d2adcc8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14792
32408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.1479232408
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.1836378907
Short name T90
Test name
Test status
Simulation time 13844230543 ps
CPU time 53.2 seconds
Started Jul 18 05:48:37 PM PDT 24
Finished Jul 18 05:49:39 PM PDT 24
Peak memory 206888 kb
Host smart-95957d1c-4807-4721-b636-4083314889ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18363
78907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.1836378907
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2990388652
Short name T1739
Test name
Test status
Simulation time 224172706 ps
CPU time 0.89 seconds
Started Jul 18 05:48:36 PM PDT 24
Finished Jul 18 05:48:44 PM PDT 24
Peak memory 206616 kb
Host smart-e7c682c4-24a9-4d7e-9aab-4a4a739cb396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29903
88652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2990388652
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2817683107
Short name T1304
Test name
Test status
Simulation time 23353809338 ps
CPU time 22.3 seconds
Started Jul 18 05:48:38 PM PDT 24
Finished Jul 18 05:49:09 PM PDT 24
Peak memory 206760 kb
Host smart-2480f985-6bd7-456a-91b0-40170ae6fb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28176
83107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2817683107
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.4146061721
Short name T472
Test name
Test status
Simulation time 3288826188 ps
CPU time 3.64 seconds
Started Jul 18 05:48:35 PM PDT 24
Finished Jul 18 05:48:47 PM PDT 24
Peak memory 206684 kb
Host smart-a16c78ba-5bfa-4969-a93e-930af04aa236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41460
61721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.4146061721
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1268911813
Short name T2386
Test name
Test status
Simulation time 10276788101 ps
CPU time 96.14 seconds
Started Jul 18 05:48:49 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206912 kb
Host smart-e47fb4c9-fdad-4076-8c94-02591147c569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12689
11813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1268911813
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.4192820345
Short name T1501
Test name
Test status
Simulation time 7506328668 ps
CPU time 211.94 seconds
Started Jul 18 05:48:50 PM PDT 24
Finished Jul 18 05:52:24 PM PDT 24
Peak memory 206812 kb
Host smart-08c94b82-ce95-4f47-86d6-269901a5e166
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4192820345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.4192820345
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.3610002071
Short name T653
Test name
Test status
Simulation time 260789516 ps
CPU time 0.91 seconds
Started Jul 18 05:48:55 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206652 kb
Host smart-fc78b99c-ecdd-4eb4-80f3-73dece5647a6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3610002071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.3610002071
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.2133711623
Short name T1237
Test name
Test status
Simulation time 232817296 ps
CPU time 0.91 seconds
Started Jul 18 05:48:49 PM PDT 24
Finished Jul 18 05:48:53 PM PDT 24
Peak memory 206632 kb
Host smart-cdf5b2b5-4f48-4b77-a782-328d89ab8921
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21337
11623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.2133711623
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.127838802
Short name T2401
Test name
Test status
Simulation time 6123309158 ps
CPU time 42.35 seconds
Started Jul 18 05:48:50 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206908 kb
Host smart-31bf8c7d-1bd0-4f55-9492-6a140956db64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12783
8802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.127838802
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.1363611821
Short name T479
Test name
Test status
Simulation time 3143431971 ps
CPU time 33.3 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:38 PM PDT 24
Peak memory 206888 kb
Host smart-e0c51e38-178c-4359-8eef-27ce0a1f8646
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1363611821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.1363611821
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.232906998
Short name T1107
Test name
Test status
Simulation time 155936740 ps
CPU time 0.86 seconds
Started Jul 18 05:48:55 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206644 kb
Host smart-371a8aff-b173-499f-bf04-cccceb93a4ae
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=232906998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.232906998
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.3504490425
Short name T2676
Test name
Test status
Simulation time 148185089 ps
CPU time 0.82 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206664 kb
Host smart-d4f7bfab-96c4-4ef5-b399-4d2fa3b53a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35044
90425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.3504490425
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1321280338
Short name T100
Test name
Test status
Simulation time 190592825 ps
CPU time 0.83 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:57 PM PDT 24
Peak memory 206640 kb
Host smart-9e292a16-52fc-4ead-9134-ba8939542a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13212
80338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1321280338
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3683367379
Short name T335
Test name
Test status
Simulation time 153939514 ps
CPU time 0.8 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:57 PM PDT 24
Peak memory 206656 kb
Host smart-615f3d2f-74b6-4d96-a1be-57560ff19c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36833
67379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3683367379
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.4154597689
Short name T2565
Test name
Test status
Simulation time 221753256 ps
CPU time 0.81 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:48:59 PM PDT 24
Peak memory 206620 kb
Host smart-b3edb013-9e16-4a0c-9111-68da8c71eb5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41545
97689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.4154597689
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.3114659050
Short name T171
Test name
Test status
Simulation time 162926659 ps
CPU time 0.78 seconds
Started Jul 18 05:52:31 PM PDT 24
Finished Jul 18 05:52:38 PM PDT 24
Peak memory 206640 kb
Host smart-eaf3a89c-8e7a-47ae-a765-81d0552c9af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31146
59050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.3114659050
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1040574584
Short name T442
Test name
Test status
Simulation time 208134067 ps
CPU time 0.9 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206632 kb
Host smart-540c307e-becc-4321-acad-7841746560c8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1040574584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1040574584
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.1608468106
Short name T2529
Test name
Test status
Simulation time 145789190 ps
CPU time 0.78 seconds
Started Jul 18 05:48:50 PM PDT 24
Finished Jul 18 05:48:53 PM PDT 24
Peak memory 206612 kb
Host smart-2bf359c2-672c-408a-85f0-ac3cfb97d48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16084
68106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.1608468106
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.691136661
Short name T31
Test name
Test status
Simulation time 53772108 ps
CPU time 0.67 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206616 kb
Host smart-449080e3-dd58-4d0e-846e-8d2e30802741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69113
6661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.691136661
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1983693092
Short name T1132
Test name
Test status
Simulation time 19453804720 ps
CPU time 48.06 seconds
Started Jul 18 05:48:55 PM PDT 24
Finished Jul 18 05:49:51 PM PDT 24
Peak memory 206948 kb
Host smart-2c36c0eb-c692-4bcc-8ad3-41ed18189ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19836
93092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1983693092
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1268072306
Short name T2119
Test name
Test status
Simulation time 225828342 ps
CPU time 0.88 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:08 PM PDT 24
Peak memory 206616 kb
Host smart-fcce0864-6561-40a3-b087-c29c17e0b9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12680
72306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1268072306
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2359435557
Short name T1006
Test name
Test status
Simulation time 245555396 ps
CPU time 0.89 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206400 kb
Host smart-48a34232-bfe3-4980-8c79-31ad82f69831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23594
35557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2359435557
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2361686533
Short name T1224
Test name
Test status
Simulation time 219136367 ps
CPU time 0.95 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206628 kb
Host smart-e322c8e7-f066-4731-9e2a-b037b3f25899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23616
86533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2361686533
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.3322149309
Short name T81
Test name
Test status
Simulation time 219739720 ps
CPU time 0.83 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:48:59 PM PDT 24
Peak memory 206600 kb
Host smart-7099c5da-3ee6-4566-8129-f1ed696e0f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33221
49309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.3322149309
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.970094091
Short name T2173
Test name
Test status
Simulation time 249374229 ps
CPU time 0.87 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206636 kb
Host smart-10f78283-23d5-447a-9dd3-eec3fbf68439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97009
4091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.970094091
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2871919955
Short name T2265
Test name
Test status
Simulation time 178759673 ps
CPU time 0.79 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206620 kb
Host smart-a7c8884f-bb70-4d50-ac89-5f4b882742ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28719
19955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2871919955
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.4240044427
Short name T1007
Test name
Test status
Simulation time 161790341 ps
CPU time 0.79 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206612 kb
Host smart-bd90e490-f0d3-46d0-b73c-ea0e761ee885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42400
44427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.4240044427
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.4067034218
Short name T2219
Test name
Test status
Simulation time 209345354 ps
CPU time 0.95 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206612 kb
Host smart-cfed758a-2e83-462a-ac5d-e7e05bcfeb58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40670
34218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.4067034218
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.722371760
Short name T418
Test name
Test status
Simulation time 3261245503 ps
CPU time 23.39 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:49:23 PM PDT 24
Peak memory 206920 kb
Host smart-fa21ecfa-b616-4f70-8ca9-37075e388da9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=722371760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.722371760
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.412138825
Short name T1672
Test name
Test status
Simulation time 180911138 ps
CPU time 0.81 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:57 PM PDT 24
Peak memory 206664 kb
Host smart-0af98c10-b907-4053-8a6f-3c848b2b2dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41213
8825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.412138825
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.3148998445
Short name T1966
Test name
Test status
Simulation time 167312840 ps
CPU time 0.82 seconds
Started Jul 18 05:48:50 PM PDT 24
Finished Jul 18 05:48:53 PM PDT 24
Peak memory 206644 kb
Host smart-78d094d2-2f38-4937-95bb-bf6175f0fd37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31489
98445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.3148998445
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1697300428
Short name T2405
Test name
Test status
Simulation time 966823872 ps
CPU time 2.28 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:08 PM PDT 24
Peak memory 206784 kb
Host smart-813c34e8-43d1-491e-abb6-0d1041abc0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16973
00428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1697300428
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.388740138
Short name T1837
Test name
Test status
Simulation time 5360300868 ps
CPU time 51.59 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:49:46 PM PDT 24
Peak memory 206916 kb
Host smart-6f554fb9-1fd6-44c4-bd60-2271d5e42a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
0138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.388740138
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.3108133068
Short name T600
Test name
Test status
Simulation time 39723212 ps
CPU time 0.68 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:17 PM PDT 24
Peak memory 206708 kb
Host smart-18d28062-004f-4957-95a6-1b54ff769635
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3108133068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.3108133068
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.288009377
Short name T182
Test name
Test status
Simulation time 4152041126 ps
CPU time 4.62 seconds
Started Jul 18 05:43:55 PM PDT 24
Finished Jul 18 05:44:13 PM PDT 24
Peak memory 206776 kb
Host smart-bee2534d-79f1-4a33-956b-f88431105540
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=288009377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.288009377
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.608480739
Short name T1974
Test name
Test status
Simulation time 13330879072 ps
CPU time 13.03 seconds
Started Jul 18 05:44:01 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 207072 kb
Host smart-7f7a09bc-4e34-45ca-94fc-62f59ecb00eb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=608480739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.608480739
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3091735801
Short name T1826
Test name
Test status
Simulation time 23312217147 ps
CPU time 23.4 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:29 PM PDT 24
Peak memory 206848 kb
Host smart-5a271ee7-7762-4014-bdd0-f5f935a89585
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3091735801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3091735801
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1678523225
Short name T1650
Test name
Test status
Simulation time 198613068 ps
CPU time 0.88 seconds
Started Jul 18 05:43:56 PM PDT 24
Finished Jul 18 05:44:10 PM PDT 24
Peak memory 206660 kb
Host smart-a26ca6dc-a915-4d24-9cb5-3c506760cd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16785
23225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1678523225
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.333835042
Short name T1709
Test name
Test status
Simulation time 170981241 ps
CPU time 0.8 seconds
Started Jul 18 05:43:49 PM PDT 24
Finished Jul 18 05:44:06 PM PDT 24
Peak memory 206656 kb
Host smart-256fee36-a483-44cd-9471-edb4a2f9451c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33383
5042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.333835042
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2590657665
Short name T83
Test name
Test status
Simulation time 132623223 ps
CPU time 0.74 seconds
Started Jul 18 05:43:52 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206648 kb
Host smart-0510b0ed-4e80-42c1-b313-68ff2a9eadc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25906
57665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2590657665
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3856600656
Short name T875
Test name
Test status
Simulation time 437803090 ps
CPU time 1.36 seconds
Started Jul 18 05:43:52 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206656 kb
Host smart-d213e15a-5cde-4217-a555-f8bd8660b621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38566
00656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3856600656
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1442518170
Short name T2162
Test name
Test status
Simulation time 857646370 ps
CPU time 2.1 seconds
Started Jul 18 05:44:01 PM PDT 24
Finished Jul 18 05:44:13 PM PDT 24
Peak memory 206900 kb
Host smart-f67b48a6-0ef0-4bdf-8abe-c579709ed6f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14425
18170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1442518170
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.4139153365
Short name T1533
Test name
Test status
Simulation time 19205214484 ps
CPU time 38.14 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206852 kb
Host smart-9a895720-5e92-43e5-a475-a9774d213617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41391
53365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.4139153365
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.139542070
Short name T682
Test name
Test status
Simulation time 463220029 ps
CPU time 1.36 seconds
Started Jul 18 05:43:56 PM PDT 24
Finished Jul 18 05:44:10 PM PDT 24
Peak memory 206640 kb
Host smart-f2782695-2549-4a94-9741-2a547b254a26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
2070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.139542070
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1685377827
Short name T920
Test name
Test status
Simulation time 146742054 ps
CPU time 0.77 seconds
Started Jul 18 05:44:40 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206620 kb
Host smart-33d51e27-1355-4db9-9780-efc50f0419fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16853
77827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1685377827
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1427978215
Short name T2620
Test name
Test status
Simulation time 43650815 ps
CPU time 0.65 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:06 PM PDT 24
Peak memory 206660 kb
Host smart-b697e7d4-8c1a-4505-b5db-dfc679b24c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14279
78215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1427978215
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.3124620508
Short name T312
Test name
Test status
Simulation time 959342896 ps
CPU time 2.35 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206768 kb
Host smart-05c6d24e-fdaa-4d59-bbe3-d2b12e2cf686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31246
20508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.3124620508
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.90313275
Short name T514
Test name
Test status
Simulation time 208116435 ps
CPU time 1.38 seconds
Started Jul 18 05:43:54 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 206728 kb
Host smart-99fee58e-5760-45a6-8854-4a052fe747d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90313
275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.90313275
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.3920641085
Short name T1330
Test name
Test status
Simulation time 116182493416 ps
CPU time 147.53 seconds
Started Jul 18 05:43:54 PM PDT 24
Finished Jul 18 05:46:35 PM PDT 24
Peak memory 206868 kb
Host smart-f8f5ca4e-ae78-450a-ae15-2a18992de8d0
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3920641085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.3920641085
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.2321353368
Short name T2567
Test name
Test status
Simulation time 114065225887 ps
CPU time 169.44 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:46:56 PM PDT 24
Peak memory 206860 kb
Host smart-031b5426-7569-47f3-93be-55d725de295a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321353368 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.2321353368
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.3388628998
Short name T1138
Test name
Test status
Simulation time 112095131502 ps
CPU time 149.75 seconds
Started Jul 18 05:43:56 PM PDT 24
Finished Jul 18 05:46:39 PM PDT 24
Peak memory 206912 kb
Host smart-ff22480f-4530-43ee-b828-c77ad5478e71
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3388628998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.3388628998
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.958666700
Short name T2393
Test name
Test status
Simulation time 105036182012 ps
CPU time 141.35 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206824 kb
Host smart-358b9eb6-a9b9-4312-b21c-70327656459d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958666700 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.958666700
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.345121305
Short name T2317
Test name
Test status
Simulation time 108200773483 ps
CPU time 137.99 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:46:25 PM PDT 24
Peak memory 206916 kb
Host smart-7f790cc8-b5c1-449e-bb44-4ad32965cf47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34512
1305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.345121305
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.98391788
Short name T1393
Test name
Test status
Simulation time 183123641 ps
CPU time 0.84 seconds
Started Jul 18 05:43:54 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 206640 kb
Host smart-faec5eda-ccc9-4efa-ab21-e8f33ab8e551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98391
788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.98391788
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.4272306036
Short name T1300
Test name
Test status
Simulation time 143840974 ps
CPU time 0.75 seconds
Started Jul 18 05:43:57 PM PDT 24
Finished Jul 18 05:44:10 PM PDT 24
Peak memory 206644 kb
Host smart-c5e4f2dc-4fe8-4ec0-9807-e65e3aed6057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42723
06036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.4272306036
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.3860844393
Short name T2347
Test name
Test status
Simulation time 225102510 ps
CPU time 0.91 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206672 kb
Host smart-950dbd30-d8d4-4e56-9dd3-9b05f8f57300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
44393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.3860844393
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.4288859763
Short name T940
Test name
Test status
Simulation time 5122549272 ps
CPU time 45.82 seconds
Started Jul 18 05:43:52 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206928 kb
Host smart-e1d45430-6dc0-44b1-8b93-54a62308eeac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42888
59763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.4288859763
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.1354485438
Short name T2120
Test name
Test status
Simulation time 233392508 ps
CPU time 0.89 seconds
Started Jul 18 05:43:54 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206648 kb
Host smart-03898f55-0c82-486f-8d1a-2c513b7c4b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13544
85438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.1354485438
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.2703867121
Short name T1420
Test name
Test status
Simulation time 23338075972 ps
CPU time 24.27 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:44:29 PM PDT 24
Peak memory 206760 kb
Host smart-67fad02e-4d10-4224-8fef-5c543c467795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27038
67121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.2703867121
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2157610613
Short name T2311
Test name
Test status
Simulation time 3301002287 ps
CPU time 3.89 seconds
Started Jul 18 05:43:49 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 206692 kb
Host smart-749497e7-10dc-4627-9784-5d46b53e67b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21576
10613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2157610613
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.3391829242
Short name T1975
Test name
Test status
Simulation time 10280497044 ps
CPU time 292.07 seconds
Started Jul 18 05:43:56 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206908 kb
Host smart-a8bea381-d2e9-4441-a187-6a2315879802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33918
29242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.3391829242
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.2873270811
Short name T1056
Test name
Test status
Simulation time 5975402302 ps
CPU time 159.5 seconds
Started Jul 18 05:43:56 PM PDT 24
Finished Jul 18 05:46:49 PM PDT 24
Peak memory 206888 kb
Host smart-fd7a53e9-d659-4ba3-a326-d4d247ac3512
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2873270811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.2873270811
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.4083749945
Short name T844
Test name
Test status
Simulation time 237550228 ps
CPU time 0.89 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:44:06 PM PDT 24
Peak memory 206652 kb
Host smart-7e78b184-b0b0-4e4f-a4df-b8997d3a609c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4083749945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.4083749945
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1185011337
Short name T1243
Test name
Test status
Simulation time 197037232 ps
CPU time 0.84 seconds
Started Jul 18 05:43:48 PM PDT 24
Finished Jul 18 05:44:05 PM PDT 24
Peak memory 206632 kb
Host smart-af9d18a5-ff53-4bf2-b6b8-a747d52b1b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11850
11337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1185011337
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3474391114
Short name T1993
Test name
Test status
Simulation time 5181416695 ps
CPU time 35.84 seconds
Started Jul 18 05:43:57 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206888 kb
Host smart-96ba23ec-5841-4d92-8438-6b48fb7d8f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34743
91114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3474391114
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.2205505285
Short name T994
Test name
Test status
Simulation time 5228673149 ps
CPU time 39.42 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206940 kb
Host smart-ce18ac43-1980-4b29-9244-686de0f4ad58
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2205505285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.2205505285
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.1944282184
Short name T2424
Test name
Test status
Simulation time 199562954 ps
CPU time 0.83 seconds
Started Jul 18 05:43:55 PM PDT 24
Finished Jul 18 05:44:09 PM PDT 24
Peak memory 206644 kb
Host smart-953d07e9-a205-40f9-8519-452566ae089f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1944282184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.1944282184
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.3238165560
Short name T1407
Test name
Test status
Simulation time 163833135 ps
CPU time 0.81 seconds
Started Jul 18 05:43:49 PM PDT 24
Finished Jul 18 05:44:05 PM PDT 24
Peak memory 206652 kb
Host smart-6bd5b6ed-5b00-459e-8a85-94fec6693409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32381
65560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.3238165560
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.2861875695
Short name T2640
Test name
Test status
Simulation time 203171948 ps
CPU time 0.93 seconds
Started Jul 18 05:43:58 PM PDT 24
Finished Jul 18 05:44:11 PM PDT 24
Peak memory 206628 kb
Host smart-ec420164-4baf-4a43-a4f2-56826b237854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
75695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.2861875695
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.2482202306
Short name T405
Test name
Test status
Simulation time 178220287 ps
CPU time 0.83 seconds
Started Jul 18 05:43:50 PM PDT 24
Finished Jul 18 05:44:06 PM PDT 24
Peak memory 206644 kb
Host smart-81e3c57d-1887-4e54-9217-60d385d3e28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24822
02306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.2482202306
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.389509917
Short name T1583
Test name
Test status
Simulation time 190915634 ps
CPU time 0.81 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206640 kb
Host smart-4a376994-1628-43ab-bfc6-650b6c9b9d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38950
9917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.389509917
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.3067829577
Short name T1178
Test name
Test status
Simulation time 182333772 ps
CPU time 0.79 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206648 kb
Host smart-2a8e8db9-2483-4a21-9183-eaa9fe0f838e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30678
29577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.3067829577
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.4125286368
Short name T2068
Test name
Test status
Simulation time 208460784 ps
CPU time 0.9 seconds
Started Jul 18 05:43:53 PM PDT 24
Finished Jul 18 05:44:08 PM PDT 24
Peak memory 206632 kb
Host smart-3f064a0f-a7e2-4db0-b119-07593f8b50f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4125286368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.4125286368
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1705051376
Short name T2733
Test name
Test status
Simulation time 219525910 ps
CPU time 0.9 seconds
Started Jul 18 05:43:51 PM PDT 24
Finished Jul 18 05:44:07 PM PDT 24
Peak memory 206640 kb
Host smart-6046f02b-334b-4747-a299-9fe6bc183726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17050
51376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1705051376
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.2189868935
Short name T1931
Test name
Test status
Simulation time 155716342 ps
CPU time 0.77 seconds
Started Jul 18 05:43:58 PM PDT 24
Finished Jul 18 05:44:11 PM PDT 24
Peak memory 206636 kb
Host smart-302437bd-b57d-43e8-8a34-6a2d5b832ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21898
68935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.2189868935
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.920633746
Short name T23
Test name
Test status
Simulation time 45064378 ps
CPU time 0.65 seconds
Started Jul 18 05:43:47 PM PDT 24
Finished Jul 18 05:44:03 PM PDT 24
Peak memory 206632 kb
Host smart-7bca0cf6-46fa-4383-8c79-f99db442b5ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92063
3746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.920633746
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3689546960
Short name T1674
Test name
Test status
Simulation time 17582632460 ps
CPU time 40.99 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:45:05 PM PDT 24
Peak memory 206900 kb
Host smart-09451981-9354-4cb4-a2fb-53d97e7e7050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36895
46960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3689546960
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1692594598
Short name T273
Test name
Test status
Simulation time 170893012 ps
CPU time 0.84 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:19 PM PDT 24
Peak memory 206628 kb
Host smart-a742fcf1-81ed-47d4-8c27-a248f4987123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16925
94598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1692594598
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3792528529
Short name T2275
Test name
Test status
Simulation time 246160665 ps
CPU time 0.9 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:18 PM PDT 24
Peak memory 206644 kb
Host smart-763781d3-5c9d-462c-8423-8cec3a72e989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37925
28529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3792528529
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3385600999
Short name T164
Test name
Test status
Simulation time 15827147088 ps
CPU time 331.23 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:49:52 PM PDT 24
Peak memory 206904 kb
Host smart-3fcfae29-edb1-4638-a307-6f5f3e3bfb27
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3385600999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3385600999
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.1892953622
Short name T170
Test name
Test status
Simulation time 11469356654 ps
CPU time 75.77 seconds
Started Jul 18 05:44:11 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206868 kb
Host smart-da7d7c22-0b16-495c-a879-097853f20d88
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1892953622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.1892953622
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.1514997105
Short name T2365
Test name
Test status
Simulation time 11637021527 ps
CPU time 61.23 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206840 kb
Host smart-2d78be7e-705c-411a-bc63-c49fcef97c54
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1514997105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.1514997105
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.309544437
Short name T2394
Test name
Test status
Simulation time 222652612 ps
CPU time 0.95 seconds
Started Jul 18 05:44:10 PM PDT 24
Finished Jul 18 05:44:15 PM PDT 24
Peak memory 206656 kb
Host smart-9e8879e4-8348-4b38-bc1a-872549723d2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30954
4437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.309544437
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.621776082
Short name T299
Test name
Test status
Simulation time 200466646 ps
CPU time 0.87 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:44:25 PM PDT 24
Peak memory 206636 kb
Host smart-772db502-2dab-4469-b39e-dfd725f91dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62177
6082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.621776082
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3879826277
Short name T71
Test name
Test status
Simulation time 135942040 ps
CPU time 0.75 seconds
Started Jul 18 05:44:15 PM PDT 24
Finished Jul 18 05:44:23 PM PDT 24
Peak memory 206636 kb
Host smart-1ab1bf86-643c-4a4d-8881-c1caba41b3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798
26277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3879826277
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.4130771213
Short name T76
Test name
Test status
Simulation time 225296850 ps
CPU time 0.9 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:21 PM PDT 24
Peak memory 206656 kb
Host smart-f192746b-60a1-4ca7-a21b-daf277a1b6f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41307
71213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.4130771213
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.2779060317
Short name T54
Test name
Test status
Simulation time 352785040 ps
CPU time 1.18 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:22 PM PDT 24
Peak memory 206636 kb
Host smart-cf39ff00-5643-4702-9f35-335360c2d283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27790
60317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.2779060317
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2691629372
Short name T969
Test name
Test status
Simulation time 197592953 ps
CPU time 0.86 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:21 PM PDT 24
Peak memory 206656 kb
Host smart-fde5539a-e8ff-40fc-b865-33f320eac713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26916
29372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2691629372
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.66273069
Short name T664
Test name
Test status
Simulation time 148460536 ps
CPU time 0.81 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206616 kb
Host smart-5e7cdcc4-83d9-48f1-b08b-65bf33b72371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66273
069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.66273069
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1208387265
Short name T2706
Test name
Test status
Simulation time 196769794 ps
CPU time 0.85 seconds
Started Jul 18 05:44:11 PM PDT 24
Finished Jul 18 05:44:17 PM PDT 24
Peak memory 206656 kb
Host smart-e7fdc322-9306-4b43-8cde-0f03e5b822e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12083
87265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1208387265
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.2056611329
Short name T2363
Test name
Test status
Simulation time 201902099 ps
CPU time 0.92 seconds
Started Jul 18 05:44:10 PM PDT 24
Finished Jul 18 05:44:16 PM PDT 24
Peak memory 206612 kb
Host smart-6d0ccda6-3393-45ba-89a8-c26a28e16833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20566
11329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.2056611329
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.981016683
Short name T1997
Test name
Test status
Simulation time 5031996875 ps
CPU time 47.04 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:45:07 PM PDT 24
Peak memory 206864 kb
Host smart-03d56503-1e1c-402a-8e65-49bfd8f1ddf4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=981016683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.981016683
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.3092182900
Short name T1838
Test name
Test status
Simulation time 201720258 ps
CPU time 0.86 seconds
Started Jul 18 05:44:11 PM PDT 24
Finished Jul 18 05:44:17 PM PDT 24
Peak memory 206632 kb
Host smart-3c8f9412-2b11-4e28-9d6b-29439179c84c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30921
82900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.3092182900
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.989343385
Short name T1398
Test name
Test status
Simulation time 187304415 ps
CPU time 0.81 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:19 PM PDT 24
Peak memory 206616 kb
Host smart-85be9030-57bf-4f3f-8a96-af9ed672d877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98934
3385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.989343385
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.1349008949
Short name T877
Test name
Test status
Simulation time 1406888282 ps
CPU time 2.78 seconds
Started Jul 18 05:44:15 PM PDT 24
Finished Jul 18 05:44:25 PM PDT 24
Peak memory 206760 kb
Host smart-aa4d830a-40e3-4104-9913-521dcf04e3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13490
08949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.1349008949
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.833901784
Short name T672
Test name
Test status
Simulation time 5748903792 ps
CPU time 159.07 seconds
Started Jul 18 05:44:11 PM PDT 24
Finished Jul 18 05:46:55 PM PDT 24
Peak memory 206844 kb
Host smart-c4cf6b54-3e7f-445e-b984-6372c3dc1781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83390
1784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.833901784
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.3855801434
Short name T2526
Test name
Test status
Simulation time 8264114653 ps
CPU time 43.39 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:45:00 PM PDT 24
Peak memory 206972 kb
Host smart-433d7caf-77b5-4f18-a1d6-1cdf819f250a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3855801434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.3855801434
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.1215856434
Short name T1887
Test name
Test status
Simulation time 68059596 ps
CPU time 0.71 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206692 kb
Host smart-f0e79814-e1df-4570-a9bf-a7cc47223130
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1215856434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.1215856434
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.71859346
Short name T645
Test name
Test status
Simulation time 3937701001 ps
CPU time 4.28 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:04 PM PDT 24
Peak memory 206784 kb
Host smart-cba8d414-cb4d-49ca-be73-43ac05bc7c89
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=71859346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.71859346
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.1138002447
Short name T1990
Test name
Test status
Simulation time 13366601961 ps
CPU time 13.65 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206872 kb
Host smart-10b7221d-b528-4aa4-a762-007b812b81ef
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1138002447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.1138002447
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.691977051
Short name T2175
Test name
Test status
Simulation time 23365979825 ps
CPU time 29.46 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206748 kb
Host smart-f0db4dc5-fc6a-430b-bfd8-c7ee5f8114cd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=691977051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.691977051
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.2466168180
Short name T497
Test name
Test status
Simulation time 165901619 ps
CPU time 0.83 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:48:58 PM PDT 24
Peak memory 206596 kb
Host smart-0fcbe79e-bab0-4f7c-a7c6-43910a20252e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24661
68180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.2466168180
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.3512489063
Short name T559
Test name
Test status
Simulation time 164459664 ps
CPU time 0.76 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206652 kb
Host smart-b17dfa9c-86ec-45a3-a2d5-1ef7af5204dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35124
89063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.3512489063
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.951885303
Short name T765
Test name
Test status
Simulation time 193072075 ps
CPU time 0.89 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206620 kb
Host smart-75c4ac14-6db5-4393-b45d-3bfd18c648ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95188
5303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.951885303
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.1646016182
Short name T1338
Test name
Test status
Simulation time 1409454935 ps
CPU time 2.87 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206784 kb
Host smart-16ced678-4795-475b-b21f-527ea5d8d231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16460
16182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.1646016182
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.1949245505
Short name T983
Test name
Test status
Simulation time 12406191206 ps
CPU time 22.46 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206884 kb
Host smart-93cf04f6-012c-4efb-9829-0fb206407228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19492
45505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.1949245505
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3094350566
Short name T1999
Test name
Test status
Simulation time 166778926 ps
CPU time 0.78 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:57 PM PDT 24
Peak memory 206616 kb
Host smart-f15b13bf-191d-4e07-9c7f-579d31a461ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30943
50566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3094350566
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1298192134
Short name T382
Test name
Test status
Simulation time 76477330 ps
CPU time 0.78 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206640 kb
Host smart-0c2b5c5d-6f07-44a2-a836-ffe52e85fe36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
92134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1298192134
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2633491753
Short name T2645
Test name
Test status
Simulation time 911141755 ps
CPU time 2.25 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:07 PM PDT 24
Peak memory 206760 kb
Host smart-18a6cc4c-dd91-47de-abc5-5bea645defc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26334
91753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2633491753
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.1038179527
Short name T2031
Test name
Test status
Simulation time 156086360 ps
CPU time 1.29 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:56 PM PDT 24
Peak memory 206768 kb
Host smart-cbb6d596-3309-4338-b13d-8b7ebb813bdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10381
79527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.1038179527
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.668998156
Short name T1877
Test name
Test status
Simulation time 240992634 ps
CPU time 0.93 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:04 PM PDT 24
Peak memory 206628 kb
Host smart-5b2aa518-7abd-45b6-ab0e-efdbcad77665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66899
8156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.668998156
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1917746226
Short name T452
Test name
Test status
Simulation time 148447610 ps
CPU time 0.81 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206632 kb
Host smart-37860b07-19ba-494b-9f4a-30da03c1a29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19177
46226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1917746226
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1982266340
Short name T2284
Test name
Test status
Simulation time 243386780 ps
CPU time 0.94 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:56 PM PDT 24
Peak memory 206596 kb
Host smart-e10a9749-9db1-4122-9cf9-0ef64ec7f4e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
66340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1982266340
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1255580923
Short name T1259
Test name
Test status
Simulation time 210129782 ps
CPU time 0.86 seconds
Started Jul 18 05:48:50 PM PDT 24
Finished Jul 18 05:48:53 PM PDT 24
Peak memory 206648 kb
Host smart-a35977ec-0218-45aa-b965-c49906463e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12555
80923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1255580923
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.2153027814
Short name T822
Test name
Test status
Simulation time 23340632130 ps
CPU time 26.54 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:31 PM PDT 24
Peak memory 206736 kb
Host smart-c448b02c-c149-4608-a566-83fbb6192ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21530
27814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.2153027814
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.1873473244
Short name T301
Test name
Test status
Simulation time 3319152194 ps
CPU time 3.97 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206724 kb
Host smart-88bd09b7-f0c1-4fde-9a50-5a38a9e12114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18734
73244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.1873473244
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.236251339
Short name T2345
Test name
Test status
Simulation time 6860295452 ps
CPU time 65.25 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206924 kb
Host smart-3893569f-fbf0-494f-953b-520428775f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23625
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.236251339
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.1502182369
Short name T2694
Test name
Test status
Simulation time 3368635165 ps
CPU time 92.49 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:50:35 PM PDT 24
Peak memory 206844 kb
Host smart-e3f2db9b-3489-4d39-ace7-e6d1c60a3dbf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1502182369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.1502182369
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.2872297306
Short name T928
Test name
Test status
Simulation time 262444526 ps
CPU time 0.91 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:08 PM PDT 24
Peak memory 206556 kb
Host smart-ea47743b-8fb1-4e49-9d46-9a9ef6e870a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2872297306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.2872297306
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1642621555
Short name T2479
Test name
Test status
Simulation time 191378309 ps
CPU time 0.87 seconds
Started Jul 18 05:48:55 PM PDT 24
Finished Jul 18 05:49:04 PM PDT 24
Peak memory 206652 kb
Host smart-73a7a75d-0584-422f-8cbb-7651f99211dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16426
21555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1642621555
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.1187262065
Short name T1998
Test name
Test status
Simulation time 3411666840 ps
CPU time 90.06 seconds
Started Jul 18 05:48:55 PM PDT 24
Finished Jul 18 05:50:33 PM PDT 24
Peak memory 206772 kb
Host smart-18dd6ba0-2fd0-4422-b8e3-472abc3afe26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11872
62065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.1187262065
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2882748880
Short name T1033
Test name
Test status
Simulation time 3836889328 ps
CPU time 37.68 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206904 kb
Host smart-f2f6b6bb-2b3f-4cc2-ad2a-cbdeae2e91aa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2882748880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2882748880
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.52880931
Short name T715
Test name
Test status
Simulation time 158378892 ps
CPU time 0.8 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206632 kb
Host smart-4124a5f9-4195-4885-9230-ad874cbbcf85
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=52880931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.52880931
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2111813952
Short name T1819
Test name
Test status
Simulation time 146489259 ps
CPU time 0.77 seconds
Started Jul 18 05:48:52 PM PDT 24
Finished Jul 18 05:48:57 PM PDT 24
Peak memory 206644 kb
Host smart-fe4038c5-cdad-40ac-a7c0-8eaf5b01fe61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21118
13952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2111813952
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.4046707194
Short name T116
Test name
Test status
Simulation time 199247344 ps
CPU time 0.82 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206644 kb
Host smart-934a7ed0-dd42-435e-9bef-396d83592ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40467
07194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.4046707194
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3409769009
Short name T1133
Test name
Test status
Simulation time 167218240 ps
CPU time 0.82 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:07 PM PDT 24
Peak memory 206636 kb
Host smart-1a0f1c31-30f8-40ff-8c37-a4a17569250c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34097
69009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3409769009
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.543732804
Short name T823
Test name
Test status
Simulation time 183173472 ps
CPU time 0.82 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206640 kb
Host smart-f0321871-0aad-466b-97c5-8453f86601f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54373
2804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.543732804
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2368236402
Short name T2174
Test name
Test status
Simulation time 149327381 ps
CPU time 0.79 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:48:58 PM PDT 24
Peak memory 206640 kb
Host smart-5bc87752-5c14-4ef8-9864-0a13c597c464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23682
36402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2368236402
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3229818913
Short name T1281
Test name
Test status
Simulation time 174251737 ps
CPU time 0.88 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206632 kb
Host smart-9fc772f9-ccea-4762-a8bd-873ffc478473
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3229818913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3229818913
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.3691985594
Short name T2013
Test name
Test status
Simulation time 155297341 ps
CPU time 0.78 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206556 kb
Host smart-87e0b6c4-7e7b-4726-940c-65916418c242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36919
85594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.3691985594
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.2445266994
Short name T1543
Test name
Test status
Simulation time 68607006 ps
CPU time 0.67 seconds
Started Jul 18 05:48:49 PM PDT 24
Finished Jul 18 05:48:52 PM PDT 24
Peak memory 206632 kb
Host smart-ca808845-822e-4d00-bf60-f37b0bfacbc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24452
66994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.2445266994
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.165363722
Short name T2687
Test name
Test status
Simulation time 21418446737 ps
CPU time 45.03 seconds
Started Jul 18 05:48:51 PM PDT 24
Finished Jul 18 05:49:39 PM PDT 24
Peak memory 206928 kb
Host smart-17839a37-464d-4a38-b953-cfcda2862d7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16536
3722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.165363722
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3294817484
Short name T840
Test name
Test status
Simulation time 162478453 ps
CPU time 0.85 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206656 kb
Host smart-bbd72d63-9581-44ca-bf3e-9bcac1b31f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32948
17484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3294817484
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.2710565715
Short name T1658
Test name
Test status
Simulation time 237970130 ps
CPU time 0.98 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206520 kb
Host smart-6943e640-9ff2-44ca-964e-704b31324f81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27105
65715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.2710565715
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2855391771
Short name T2729
Test name
Test status
Simulation time 198076233 ps
CPU time 0.86 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206392 kb
Host smart-53873017-bab2-4aa2-b7a9-80605b736d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28553
91771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2855391771
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.2415327296
Short name T851
Test name
Test status
Simulation time 141418266 ps
CPU time 0.82 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206612 kb
Host smart-afcfe7df-e0b1-42f0-b4e8-ea9fa68512bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24153
27296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.2415327296
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.1070408869
Short name T467
Test name
Test status
Simulation time 148398130 ps
CPU time 0.78 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206620 kb
Host smart-f3ba3822-f5f2-47f7-87f1-e9966527cfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10704
08869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.1070408869
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3892594081
Short name T1456
Test name
Test status
Simulation time 160531991 ps
CPU time 0.81 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206644 kb
Host smart-813b3c55-b0c2-4d94-9051-aa3df3669926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38925
94081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3892594081
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.435935852
Short name T2715
Test name
Test status
Simulation time 158067671 ps
CPU time 0.81 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206656 kb
Host smart-d7d7ec34-efc4-4fae-ba8e-68e498548017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43593
5852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.435935852
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.2763688090
Short name T1781
Test name
Test status
Simulation time 209120148 ps
CPU time 0.94 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206628 kb
Host smart-312bfada-f744-49c5-9d8b-2f6736a31f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27636
88090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.2763688090
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.616077805
Short name T745
Test name
Test status
Simulation time 5521777287 ps
CPU time 53.36 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:50:00 PM PDT 24
Peak memory 206864 kb
Host smart-01f14192-cda6-4454-acb5-6a4bd8705de0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=616077805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.616077805
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2503345572
Short name T885
Test name
Test status
Simulation time 198724467 ps
CPU time 0.82 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206636 kb
Host smart-c909389d-4fc4-4518-ad58-3ac77bda26cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25033
45572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2503345572
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.1297916344
Short name T1255
Test name
Test status
Simulation time 208943308 ps
CPU time 0.82 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:07 PM PDT 24
Peak memory 206648 kb
Host smart-4016a902-e495-46a9-9106-29ae2ca8ca59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12979
16344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.1297916344
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1912046665
Short name T990
Test name
Test status
Simulation time 1060916044 ps
CPU time 2.44 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206628 kb
Host smart-8fbd38b1-563e-44e9-a1e1-3bbbf825bd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19120
46665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1912046665
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.46971928
Short name T1981
Test name
Test status
Simulation time 5190691973 ps
CPU time 136.8 seconds
Started Jul 18 05:48:51 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206832 kb
Host smart-75c4ae44-f01e-405e-a8ea-5423d6c072ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46971
928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.46971928
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2355821536
Short name T471
Test name
Test status
Simulation time 88794999 ps
CPU time 0.75 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:17 PM PDT 24
Peak memory 206680 kb
Host smart-a6dfd119-ae9c-49f8-b0aa-8e90abd40263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2355821536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2355821536
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.2859295454
Short name T1097
Test name
Test status
Simulation time 3490305694 ps
CPU time 4.03 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206852 kb
Host smart-66b2c866-4135-4020-ad92-23a840f92bdd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2859295454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.2859295454
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.3515491894
Short name T2360
Test name
Test status
Simulation time 13397170766 ps
CPU time 16.45 seconds
Started Jul 18 05:48:51 PM PDT 24
Finished Jul 18 05:49:10 PM PDT 24
Peak memory 206916 kb
Host smart-192076c7-f3e8-4925-84e5-7c90948c87bc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3515491894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.3515491894
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.3485542169
Short name T10
Test name
Test status
Simulation time 23407435773 ps
CPU time 28.62 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206776 kb
Host smart-618c959a-8278-4f58-af22-632861223274
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3485542169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.3485542169
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1258308437
Short name T1643
Test name
Test status
Simulation time 157026644 ps
CPU time 0.82 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206644 kb
Host smart-4f6af339-ab55-4c3e-ba40-a254882ee73e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12583
08437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1258308437
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1909115012
Short name T1517
Test name
Test status
Simulation time 157004831 ps
CPU time 0.82 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206660 kb
Host smart-35758d54-72f7-46bb-aa93-94438cac6440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19091
15012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1909115012
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.1020974757
Short name T1309
Test name
Test status
Simulation time 313452948 ps
CPU time 1.13 seconds
Started Jul 18 05:48:55 PM PDT 24
Finished Jul 18 05:49:04 PM PDT 24
Peak memory 206608 kb
Host smart-3a837ea7-af40-4b08-9ec0-aa33dbbf9a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10209
74757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.1020974757
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.2982773819
Short name T2650
Test name
Test status
Simulation time 655610981 ps
CPU time 1.55 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206616 kb
Host smart-d5d551a2-af81-41d7-ae17-34b9fd49c900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29827
73819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.2982773819
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.3765423654
Short name T2096
Test name
Test status
Simulation time 8811314323 ps
CPU time 16.07 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:21 PM PDT 24
Peak memory 206864 kb
Host smart-171f198c-0186-48f2-ad03-ae44b5e9610d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37654
23654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.3765423654
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3489750687
Short name T1696
Test name
Test status
Simulation time 425897940 ps
CPU time 1.37 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206652 kb
Host smart-8432ec83-d0d8-4d18-bab2-beccc4f8c6b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34897
50687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3489750687
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2140830947
Short name T2506
Test name
Test status
Simulation time 146564990 ps
CPU time 0.76 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206640 kb
Host smart-02f2114a-7387-44a6-9732-946d48134809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21408
30947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2140830947
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.946894140
Short name T462
Test name
Test status
Simulation time 34098554 ps
CPU time 0.64 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:01 PM PDT 24
Peak memory 206660 kb
Host smart-5f067177-29e7-478e-98e9-787b4d0a06e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94689
4140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.946894140
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2701853120
Short name T1669
Test name
Test status
Simulation time 878781063 ps
CPU time 2.2 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:09 PM PDT 24
Peak memory 206744 kb
Host smart-3a42cd13-69d1-4121-a3a6-ef31c39142bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27018
53120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2701853120
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.44197728
Short name T1919
Test name
Test status
Simulation time 190826901 ps
CPU time 1.89 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:06 PM PDT 24
Peak memory 206728 kb
Host smart-c522d3f3-f3ee-434b-9038-979d0df10314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44197
728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.44197728
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4268343104
Short name T543
Test name
Test status
Simulation time 213200322 ps
CPU time 0.9 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:05 PM PDT 24
Peak memory 206648 kb
Host smart-5c172480-8da3-44f9-9634-8c3346279bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42683
43104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4268343104
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.549485486
Short name T435
Test name
Test status
Simulation time 196618314 ps
CPU time 0.84 seconds
Started Jul 18 05:48:54 PM PDT 24
Finished Jul 18 05:49:03 PM PDT 24
Peak memory 206660 kb
Host smart-c92dceb8-e601-458b-ab0b-d750bd273cbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54948
5486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.549485486
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.2378355187
Short name T2193
Test name
Test status
Simulation time 192053765 ps
CPU time 0.88 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:08 PM PDT 24
Peak memory 206660 kb
Host smart-7f4247fe-dd00-47ba-a8ac-a8d5c878275e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23783
55187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.2378355187
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.754222751
Short name T879
Test name
Test status
Simulation time 4227426882 ps
CPU time 34.21 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:41 PM PDT 24
Peak memory 206924 kb
Host smart-36aae199-8b9f-457e-aaa0-01995e00647f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75422
2751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.754222751
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.3809337418
Short name T2508
Test name
Test status
Simulation time 255365002 ps
CPU time 0.88 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:08 PM PDT 24
Peak memory 206652 kb
Host smart-23998962-3d4a-4654-b407-965f3e722e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38093
37418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.3809337418
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.3506852838
Short name T2272
Test name
Test status
Simulation time 23306292253 ps
CPU time 22.41 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:27 PM PDT 24
Peak memory 206796 kb
Host smart-64028a66-56db-4d91-925c-445d4864f5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35068
52838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.3506852838
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2416535398
Short name T2436
Test name
Test status
Simulation time 3271089173 ps
CPU time 3.87 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:49:09 PM PDT 24
Peak memory 206724 kb
Host smart-ec7a7dd5-d976-49ed-b631-1b977b021378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24165
35398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2416535398
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.147076392
Short name T2185
Test name
Test status
Simulation time 8608350299 ps
CPU time 62.46 seconds
Started Jul 18 05:48:56 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206928 kb
Host smart-a81e3e36-8291-4ebf-8ffc-393259c4917e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707
6392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.147076392
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.3397055525
Short name T1980
Test name
Test status
Simulation time 5024894173 ps
CPU time 139.34 seconds
Started Jul 18 05:50:36 PM PDT 24
Finished Jul 18 05:53:16 PM PDT 24
Peak memory 206860 kb
Host smart-4a02705c-0505-4c28-ad88-a3a3e6a846d8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3397055525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.3397055525
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.4207652486
Short name T1101
Test name
Test status
Simulation time 266538079 ps
CPU time 0.99 seconds
Started Jul 18 05:48:59 PM PDT 24
Finished Jul 18 05:49:08 PM PDT 24
Peak memory 206628 kb
Host smart-1dc91738-0a99-4d77-9d47-d1a636c7e5e3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4207652486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.4207652486
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2414832083
Short name T1008
Test name
Test status
Simulation time 206060952 ps
CPU time 0.84 seconds
Started Jul 18 05:48:53 PM PDT 24
Finished Jul 18 05:48:59 PM PDT 24
Peak memory 206636 kb
Host smart-672810c2-f960-4d88-8ed0-0f7f2e14b6cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24148
32083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2414832083
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.598982365
Short name T1088
Test name
Test status
Simulation time 3501556241 ps
CPU time 96.5 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:50:43 PM PDT 24
Peak memory 206832 kb
Host smart-0cc298ce-8954-4b6d-8956-45e4c1e70fe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59898
2365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.598982365
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.1929461545
Short name T153
Test name
Test status
Simulation time 4611830119 ps
CPU time 41.64 seconds
Started Jul 18 05:48:57 PM PDT 24
Finished Jul 18 05:49:47 PM PDT 24
Peak memory 206900 kb
Host smart-27145c95-7229-483b-9eb7-c8dc120d2e40
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1929461545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.1929461545
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.4116774401
Short name T530
Test name
Test status
Simulation time 159194349 ps
CPU time 0.81 seconds
Started Jul 18 05:48:58 PM PDT 24
Finished Jul 18 05:49:07 PM PDT 24
Peak memory 206636 kb
Host smart-027a3c7f-fa42-457f-b2b5-af5bb387cb3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4116774401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.4116774401
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1067534012
Short name T2415
Test name
Test status
Simulation time 134717654 ps
CPU time 0.74 seconds
Started Jul 18 05:49:07 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206628 kb
Host smart-3f79f115-b272-4ad1-a355-c67a7fa7c351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10675
34012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1067534012
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2723388785
Short name T126
Test name
Test status
Simulation time 225554946 ps
CPU time 0.93 seconds
Started Jul 18 05:49:10 PM PDT 24
Finished Jul 18 05:49:13 PM PDT 24
Peak memory 206612 kb
Host smart-02dc4e14-c179-4726-aee9-d200f89dd1c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
88785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2723388785
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.952915589
Short name T468
Test name
Test status
Simulation time 182254000 ps
CPU time 0.92 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:17 PM PDT 24
Peak memory 206668 kb
Host smart-3934c3be-2edb-4953-a64e-e3ccad725caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95291
5589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.952915589
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.2303786704
Short name T999
Test name
Test status
Simulation time 187202040 ps
CPU time 0.81 seconds
Started Jul 18 05:49:10 PM PDT 24
Finished Jul 18 05:49:13 PM PDT 24
Peak memory 206640 kb
Host smart-cc78cd02-1bf3-49fa-ab78-0da13aba9bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23037
86704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.2303786704
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3899487823
Short name T2305
Test name
Test status
Simulation time 143296573 ps
CPU time 0.82 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:15 PM PDT 24
Peak memory 206620 kb
Host smart-82ecdead-f861-4a26-9e31-ca9edae66fca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38994
87823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3899487823
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3013651452
Short name T2449
Test name
Test status
Simulation time 144468217 ps
CPU time 0.88 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206660 kb
Host smart-2a00095c-d95e-4d98-84c1-19e43b9f922a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30136
51452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3013651452
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2286832535
Short name T2006
Test name
Test status
Simulation time 226786775 ps
CPU time 0.94 seconds
Started Jul 18 05:49:14 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206652 kb
Host smart-a65677a9-6e8c-42e2-96c5-a5a8ca60ead8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2286832535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2286832535
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.2570183944
Short name T2181
Test name
Test status
Simulation time 155625854 ps
CPU time 0.79 seconds
Started Jul 18 05:49:07 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206624 kb
Host smart-02feef6d-64af-4c37-bc80-54f3e1fd9dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25701
83944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.2570183944
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.500299686
Short name T846
Test name
Test status
Simulation time 45430726 ps
CPU time 0.73 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:14 PM PDT 24
Peak memory 206612 kb
Host smart-4316fc9b-9e4e-420a-9538-87f29453b9fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50029
9686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.500299686
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.3255551424
Short name T2689
Test name
Test status
Simulation time 20131894251 ps
CPU time 49.53 seconds
Started Jul 18 05:49:06 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206892 kb
Host smart-f3053a37-9791-4fea-b148-90a9e376cea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32555
51424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.3255551424
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2843337837
Short name T1902
Test name
Test status
Simulation time 224912565 ps
CPU time 0.87 seconds
Started Jul 18 05:49:08 PM PDT 24
Finished Jul 18 05:49:12 PM PDT 24
Peak memory 206640 kb
Host smart-c6303c16-8679-413c-9afa-ac9c61511ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28433
37837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2843337837
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.270809798
Short name T148
Test name
Test status
Simulation time 212137999 ps
CPU time 0.86 seconds
Started Jul 18 05:49:05 PM PDT 24
Finished Jul 18 05:49:10 PM PDT 24
Peak memory 206656 kb
Host smart-d43d3c12-e2ba-4841-8093-c9563dc42e6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27080
9798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.270809798
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3997405947
Short name T781
Test name
Test status
Simulation time 229605949 ps
CPU time 0.88 seconds
Started Jul 18 05:49:08 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206644 kb
Host smart-9decc25d-1925-48b3-b8c4-9a17523bf61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39974
05947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3997405947
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.784685188
Short name T841
Test name
Test status
Simulation time 162242166 ps
CPU time 0.8 seconds
Started Jul 18 05:49:14 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206648 kb
Host smart-a91d29c3-b8de-4888-8940-d63a07a025b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78468
5188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.784685188
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.954163196
Short name T2007
Test name
Test status
Simulation time 156862545 ps
CPU time 0.84 seconds
Started Jul 18 05:49:09 PM PDT 24
Finished Jul 18 05:49:12 PM PDT 24
Peak memory 206620 kb
Host smart-ea3b3020-ed49-499f-be2d-b0b92896ab53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95416
3196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.954163196
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.509101065
Short name T1956
Test name
Test status
Simulation time 195270998 ps
CPU time 0.8 seconds
Started Jul 18 05:49:07 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206620 kb
Host smart-c08c85a9-5a27-42cf-a978-1712b73c5b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50910
1065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.509101065
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.2022882781
Short name T1645
Test name
Test status
Simulation time 145510527 ps
CPU time 0.77 seconds
Started Jul 18 05:49:06 PM PDT 24
Finished Jul 18 05:49:10 PM PDT 24
Peak memory 206640 kb
Host smart-73043017-01a7-425e-af00-f3aa58d3722b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20228
82781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.2022882781
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3589752334
Short name T2520
Test name
Test status
Simulation time 194385735 ps
CPU time 0.91 seconds
Started Jul 18 05:49:07 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206652 kb
Host smart-4208c256-66fc-48e5-8499-5fce44727c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35897
52334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3589752334
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.39543402
Short name T524
Test name
Test status
Simulation time 4670048813 ps
CPU time 134.46 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:51:31 PM PDT 24
Peak memory 206884 kb
Host smart-d2d88218-01f3-4b1f-a9c2-83ede9852ba8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=39543402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.39543402
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.2134294809
Short name T2108
Test name
Test status
Simulation time 184514974 ps
CPU time 0.83 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:15 PM PDT 24
Peak memory 206620 kb
Host smart-a6868c63-5637-4419-85f7-75b43e244789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21342
94809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.2134294809
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.2704177656
Short name T2713
Test name
Test status
Simulation time 174792406 ps
CPU time 0.86 seconds
Started Jul 18 05:49:07 PM PDT 24
Finished Jul 18 05:49:11 PM PDT 24
Peak memory 206648 kb
Host smart-21b50af8-5758-4f2f-8cb1-5955086ac998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27041
77656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.2704177656
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2067777345
Short name T363
Test name
Test status
Simulation time 731471100 ps
CPU time 1.77 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:15 PM PDT 24
Peak memory 206796 kb
Host smart-5d8c711c-c13e-42fb-8739-31061ac8a0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20677
77345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2067777345
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1480654194
Short name T1986
Test name
Test status
Simulation time 6508760504 ps
CPU time 63.01 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:50:21 PM PDT 24
Peak memory 206836 kb
Host smart-87809fab-19f3-4cf9-810e-5965f6ea4354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14806
54194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1480654194
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.728999708
Short name T1082
Test name
Test status
Simulation time 54464496 ps
CPU time 0.68 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206696 kb
Host smart-ad2125f8-c246-4718-80ba-39eb2d09f0c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=728999708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.728999708
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2666286421
Short name T1221
Test name
Test status
Simulation time 4281555908 ps
CPU time 4.85 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:22 PM PDT 24
Peak memory 206684 kb
Host smart-ffb04051-f978-4a2e-859a-da93a4db58ce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2666286421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2666286421
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3334492470
Short name T1003
Test name
Test status
Simulation time 13410821297 ps
CPU time 14.44 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206748 kb
Host smart-7f7d1f36-2039-4b96-90a3-d6700e622870
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3334492470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3334492470
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.1419481071
Short name T2634
Test name
Test status
Simulation time 23300311880 ps
CPU time 22.47 seconds
Started Jul 18 05:49:10 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206900 kb
Host smart-d396cd72-e359-41b0-b709-a3ebe1ee7594
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1419481071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.1419481071
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.741165891
Short name T1769
Test name
Test status
Simulation time 172609820 ps
CPU time 0.89 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206632 kb
Host smart-eac9d379-97b5-4b72-899f-bab9d9fd6ccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74116
5891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.741165891
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.3102823773
Short name T1215
Test name
Test status
Simulation time 155955646 ps
CPU time 0.76 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:17 PM PDT 24
Peak memory 206640 kb
Host smart-4f6ffba7-02ec-4a72-9d41-cd8c169e4f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31028
23773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.3102823773
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.324195273
Short name T2332
Test name
Test status
Simulation time 376502584 ps
CPU time 1.23 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:23 PM PDT 24
Peak memory 206460 kb
Host smart-c82718f5-274c-4375-b7c7-e92204beaca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32419
5273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.324195273
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.3091182669
Short name T1805
Test name
Test status
Simulation time 945370924 ps
CPU time 2.03 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:23 PM PDT 24
Peak memory 206612 kb
Host smart-f5bd039b-a2a7-4467-b2a5-043fcfec4f20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
82669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.3091182669
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.99107695
Short name T768
Test name
Test status
Simulation time 11682331673 ps
CPU time 22.19 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:39 PM PDT 24
Peak memory 206892 kb
Host smart-d9fef4d6-af33-412b-b057-6cb970d1431e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99107
695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.99107695
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.418178596
Short name T292
Test name
Test status
Simulation time 460990315 ps
CPU time 1.44 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206628 kb
Host smart-dd69f278-5f3c-4fb0-b222-9761e93a38c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41817
8596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.418178596
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.3016855733
Short name T575
Test name
Test status
Simulation time 137486359 ps
CPU time 0.76 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:22 PM PDT 24
Peak memory 206584 kb
Host smart-c64098b9-8361-4143-9f61-096461454986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30168
55733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.3016855733
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2506102401
Short name T640
Test name
Test status
Simulation time 47492636 ps
CPU time 0.74 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:21 PM PDT 24
Peak memory 206664 kb
Host smart-4c46740a-e565-46a7-b3b6-28f37b9bf5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
02401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2506102401
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.666184216
Short name T1283
Test name
Test status
Simulation time 869066144 ps
CPU time 1.89 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206796 kb
Host smart-450c52b5-5979-430d-a638-92f4b8497f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66618
4216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.666184216
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1799272221
Short name T2657
Test name
Test status
Simulation time 282562622 ps
CPU time 1.59 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206648 kb
Host smart-f82999b2-3748-4990-a8c9-1186b8a9b3b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17992
72221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1799272221
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1142321193
Short name T115
Test name
Test status
Simulation time 189050783 ps
CPU time 0.89 seconds
Started Jul 18 05:49:14 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206648 kb
Host smart-78784b4d-2c01-406e-8817-2ada77a586e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11423
21193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1142321193
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3671702191
Short name T2739
Test name
Test status
Simulation time 224343836 ps
CPU time 0.83 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206644 kb
Host smart-c6467280-0c29-47b1-839a-6670d69099f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36717
02191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3671702191
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.879925196
Short name T50
Test name
Test status
Simulation time 308717162 ps
CPU time 1.08 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:14 PM PDT 24
Peak memory 206644 kb
Host smart-ef645fb6-5f05-4733-8f44-7b3d51d4f3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87992
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.879925196
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.481430119
Short name T898
Test name
Test status
Simulation time 9251193773 ps
CPU time 87.7 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:50:46 PM PDT 24
Peak memory 206904 kb
Host smart-546a9046-dcb0-4444-8485-19a1416183c9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=481430119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.481430119
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.4271349133
Short name T697
Test name
Test status
Simulation time 11154335579 ps
CPU time 92.2 seconds
Started Jul 18 05:49:30 PM PDT 24
Finished Jul 18 05:51:08 PM PDT 24
Peak memory 206908 kb
Host smart-bc8a2a8c-b58a-4957-9854-50fe4c570649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42713
49133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.4271349133
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.3506584685
Short name T300
Test name
Test status
Simulation time 203861095 ps
CPU time 0.82 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:22 PM PDT 24
Peak memory 206636 kb
Host smart-10d9f1f3-8431-4b74-9d61-651bbfeb4849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35065
84685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.3506584685
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1952859252
Short name T2329
Test name
Test status
Simulation time 23293659074 ps
CPU time 26.67 seconds
Started Jul 18 05:49:14 PM PDT 24
Finished Jul 18 05:49:46 PM PDT 24
Peak memory 206772 kb
Host smart-23f77d31-54e0-4f6d-bd63-baea841f91f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
59252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1952859252
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.3928991970
Short name T392
Test name
Test status
Simulation time 3333062368 ps
CPU time 3.62 seconds
Started Jul 18 05:49:26 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206720 kb
Host smart-251ee099-f838-4502-a8a1-380a6fdbb3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39289
91970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.3928991970
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.980169873
Short name T2471
Test name
Test status
Simulation time 8591708475 ps
CPU time 255.51 seconds
Started Jul 18 05:49:21 PM PDT 24
Finished Jul 18 05:53:41 PM PDT 24
Peak memory 206928 kb
Host smart-c4c4d1d2-cf33-4156-a9d8-9ec567db086c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98016
9873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.980169873
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.3288034193
Short name T963
Test name
Test status
Simulation time 4182605197 ps
CPU time 117.79 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206888 kb
Host smart-b478452e-bee7-468d-a294-62ba818b95c5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3288034193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.3288034193
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.3407962086
Short name T1571
Test name
Test status
Simulation time 255357428 ps
CPU time 0.98 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:49:25 PM PDT 24
Peak memory 206648 kb
Host smart-758ca7d0-179b-41ea-bc25-fd183a84cf9e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3407962086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.3407962086
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.415374115
Short name T429
Test name
Test status
Simulation time 188184997 ps
CPU time 0.88 seconds
Started Jul 18 05:49:26 PM PDT 24
Finished Jul 18 05:49:32 PM PDT 24
Peak memory 206648 kb
Host smart-9a8840bf-eda4-4eb1-aa0a-9cb4d3bb32ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537
4115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.415374115
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1433976357
Short name T1621
Test name
Test status
Simulation time 3896655540 ps
CPU time 27.53 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:49:52 PM PDT 24
Peak memory 206860 kb
Host smart-85c20d39-ec86-490a-9219-fef80516de93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14339
76357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1433976357
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.214644772
Short name T2292
Test name
Test status
Simulation time 6937961281 ps
CPU time 203.58 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:52:49 PM PDT 24
Peak memory 206884 kb
Host smart-a74b6f56-3bb3-49c7-9523-94407a1497aa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=214644772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.214644772
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3169643777
Short name T1718
Test name
Test status
Simulation time 152868864 ps
CPU time 0.77 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:18 PM PDT 24
Peak memory 206748 kb
Host smart-02e49a3c-4da3-415b-8a4a-3ce4838daec7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3169643777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3169643777
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.1053580768
Short name T952
Test name
Test status
Simulation time 162228131 ps
CPU time 0.79 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:49:25 PM PDT 24
Peak memory 206648 kb
Host smart-74bb3a15-ba27-4695-b7ff-4afca12c0ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10535
80768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.1053580768
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2700635025
Short name T135
Test name
Test status
Simulation time 228443003 ps
CPU time 0.86 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:22 PM PDT 24
Peak memory 206388 kb
Host smart-059fe41e-b0ad-415a-b540-7bed08603212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27006
35025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2700635025
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.1753927993
Short name T649
Test name
Test status
Simulation time 177487297 ps
CPU time 0.85 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:49:24 PM PDT 24
Peak memory 206648 kb
Host smart-ab2d70ae-ab99-4872-bd93-eca57f7c0a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17539
27993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.1753927993
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.3392678805
Short name T1306
Test name
Test status
Simulation time 169949619 ps
CPU time 0.86 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:27 PM PDT 24
Peak memory 206648 kb
Host smart-664699c9-00ce-4b3c-a14f-d827178eca62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33926
78805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.3392678805
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.1909084262
Short name T2025
Test name
Test status
Simulation time 244697647 ps
CPU time 0.85 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:25 PM PDT 24
Peak memory 206648 kb
Host smart-879f1724-bc91-4c84-8876-8f01fdd63758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19090
84262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.1909084262
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.848553459
Short name T172
Test name
Test status
Simulation time 154769001 ps
CPU time 0.82 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206656 kb
Host smart-22aea641-ad9f-4de5-bc41-86c52d14b83f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84855
3459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.848553459
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.3685145300
Short name T1638
Test name
Test status
Simulation time 205793684 ps
CPU time 0.94 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:34 PM PDT 24
Peak memory 206648 kb
Host smart-9ef93c58-9be6-48c5-8f74-c0991facfccc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3685145300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.3685145300
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.2952318410
Short name T1025
Test name
Test status
Simulation time 136622871 ps
CPU time 0.74 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:25 PM PDT 24
Peak memory 206640 kb
Host smart-19f0c4a1-76ed-4ce0-91e3-c672f9e934f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29523
18410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.2952318410
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1209911283
Short name T902
Test name
Test status
Simulation time 72552003 ps
CPU time 0.67 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206648 kb
Host smart-e9ecf120-eeb4-4d0e-8804-d8df87888dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12099
11283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1209911283
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1183517060
Short name T2165
Test name
Test status
Simulation time 19675319021 ps
CPU time 44.91 seconds
Started Jul 18 05:49:10 PM PDT 24
Finished Jul 18 05:49:57 PM PDT 24
Peak memory 206916 kb
Host smart-eed82683-c9b3-4af1-85ef-078bffed6d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11835
17060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1183517060
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.583603411
Short name T1058
Test name
Test status
Simulation time 172919087 ps
CPU time 0.83 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:34 PM PDT 24
Peak memory 206656 kb
Host smart-ac0b23b8-9f8f-4932-8ca7-b61ee76c3058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58360
3411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.583603411
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.158728690
Short name T692
Test name
Test status
Simulation time 235264464 ps
CPU time 0.92 seconds
Started Jul 18 05:49:24 PM PDT 24
Finished Jul 18 05:49:30 PM PDT 24
Peak memory 206652 kb
Host smart-d4d83dbd-1eba-4d02-81ba-77f79e446dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15872
8690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.158728690
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.2344422684
Short name T698
Test name
Test status
Simulation time 176856195 ps
CPU time 0.86 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206648 kb
Host smart-02d6f743-3659-49d3-8be3-555e8d1cb2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23444
22684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.2344422684
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.4089922143
Short name T463
Test name
Test status
Simulation time 183488109 ps
CPU time 0.85 seconds
Started Jul 18 05:49:22 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206588 kb
Host smart-bc0a62ac-e76e-499b-9709-8a9255dea10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40899
22143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.4089922143
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.2830889823
Short name T923
Test name
Test status
Simulation time 165820586 ps
CPU time 0.81 seconds
Started Jul 18 05:49:22 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206636 kb
Host smart-78af00ad-33c9-4050-8754-7decd6fc67a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28308
89823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.2830889823
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1234568220
Short name T2225
Test name
Test status
Simulation time 217756751 ps
CPU time 0.81 seconds
Started Jul 18 05:49:10 PM PDT 24
Finished Jul 18 05:49:13 PM PDT 24
Peak memory 206620 kb
Host smart-2aeac8b2-c9b6-4c40-8acf-c15885605eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12345
68220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1234568220
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2887494960
Short name T1136
Test name
Test status
Simulation time 199762996 ps
CPU time 0.88 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:14 PM PDT 24
Peak memory 206620 kb
Host smart-9b200d6c-0b67-41e3-b5da-bb6af1463d6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28874
94960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2887494960
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1753464075
Short name T874
Test name
Test status
Simulation time 5880916918 ps
CPU time 42.18 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:55 PM PDT 24
Peak memory 206804 kb
Host smart-c4ed1efa-ec71-4464-89da-24826a4fd663
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1753464075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1753464075
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.2882461268
Short name T1046
Test name
Test status
Simulation time 174781524 ps
CPU time 0.78 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206528 kb
Host smart-78d66cc2-29f5-4404-9cae-45bdb6105dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28824
61268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.2882461268
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.4246177175
Short name T1142
Test name
Test status
Simulation time 154264706 ps
CPU time 0.77 seconds
Started Jul 18 05:49:10 PM PDT 24
Finished Jul 18 05:49:13 PM PDT 24
Peak memory 206620 kb
Host smart-09d63403-661c-4a13-b199-d97dfd91073e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42461
77175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.4246177175
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.665530148
Short name T2652
Test name
Test status
Simulation time 1328688726 ps
CPU time 2.63 seconds
Started Jul 18 05:49:08 PM PDT 24
Finished Jul 18 05:49:14 PM PDT 24
Peak memory 206768 kb
Host smart-ee905e56-e6d0-4d02-9c4a-7ea7fbbe7b00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66553
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.665530148
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3275445841
Short name T2586
Test name
Test status
Simulation time 3514346681 ps
CPU time 31.92 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:50 PM PDT 24
Peak memory 206896 kb
Host smart-86ebf698-5e7c-4704-9e54-e75a51bb7ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32754
45841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3275445841
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.3811735116
Short name T1043
Test name
Test status
Simulation time 36457852 ps
CPU time 0.64 seconds
Started Jul 18 05:49:08 PM PDT 24
Finished Jul 18 05:49:12 PM PDT 24
Peak memory 206592 kb
Host smart-b24fe3ca-6244-4ea4-81d4-9f607afdadca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3811735116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.3811735116
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.2935511013
Short name T1271
Test name
Test status
Simulation time 4241708180 ps
CPU time 4.96 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:27 PM PDT 24
Peak memory 206696 kb
Host smart-cbeef79a-b432-471e-ad1a-18ee057e2544
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2935511013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.2935511013
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3769549263
Short name T2667
Test name
Test status
Simulation time 13516830824 ps
CPU time 12.16 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:27 PM PDT 24
Peak memory 206852 kb
Host smart-aec930c8-4dc7-4aa4-8fad-625f4d982d61
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3769549263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3769549263
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.3809796041
Short name T1970
Test name
Test status
Simulation time 23402021635 ps
CPU time 23.9 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:49 PM PDT 24
Peak memory 206776 kb
Host smart-f42df0a2-9822-4464-89ad-759e0a0421d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3809796041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.3809796041
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1661877542
Short name T2128
Test name
Test status
Simulation time 179525166 ps
CPU time 0.79 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206636 kb
Host smart-5faa03f5-1366-4d08-b0fd-e1ec5a84c9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16618
77542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1661877542
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.326861720
Short name T945
Test name
Test status
Simulation time 166919860 ps
CPU time 0.76 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:15 PM PDT 24
Peak memory 206640 kb
Host smart-90591157-ec92-45c0-9593-b3e1beb866f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32686
1720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.326861720
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.875296581
Short name T1921
Test name
Test status
Simulation time 233279312 ps
CPU time 0.98 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206628 kb
Host smart-66339543-afce-4335-8184-d5a9fa01f63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87529
6581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.875296581
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.4001619858
Short name T2212
Test name
Test status
Simulation time 330628506 ps
CPU time 1.08 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206656 kb
Host smart-184734dc-b17c-41e0-9c1a-203bdca5b048
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40016
19858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.4001619858
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1516601386
Short name T106
Test name
Test status
Simulation time 21215480991 ps
CPU time 34.97 seconds
Started Jul 18 05:49:11 PM PDT 24
Finished Jul 18 05:49:49 PM PDT 24
Peak memory 206832 kb
Host smart-8ebd456b-3c02-4703-8351-c2d92c127eeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15166
01386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1516601386
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.682377580
Short name T849
Test name
Test status
Simulation time 367362437 ps
CPU time 1.18 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:27 PM PDT 24
Peak memory 206656 kb
Host smart-14c8b225-c8d2-431d-8db9-df01f98c56c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68237
7580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.682377580
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.2323328142
Short name T1512
Test name
Test status
Simulation time 173603604 ps
CPU time 0.79 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:49:25 PM PDT 24
Peak memory 206520 kb
Host smart-4d96f965-58ad-412d-83dc-14b19985af06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23233
28142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.2323328142
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1018656725
Short name T478
Test name
Test status
Simulation time 31528557 ps
CPU time 0.66 seconds
Started Jul 18 05:49:30 PM PDT 24
Finished Jul 18 05:49:36 PM PDT 24
Peak memory 206648 kb
Host smart-a02cb98c-70c4-47ae-8306-3007c955fb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10186
56725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1018656725
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1422379210
Short name T343
Test name
Test status
Simulation time 859807094 ps
CPU time 2.12 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:22 PM PDT 24
Peak memory 206768 kb
Host smart-87e6d2a3-1ad4-4888-9d0c-5b834003142b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14223
79210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1422379210
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3998809128
Short name T2192
Test name
Test status
Simulation time 364502705 ps
CPU time 2.24 seconds
Started Jul 18 05:49:21 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206800 kb
Host smart-34f5ad6d-9f2a-4ea8-bc87-ba72b3518ff4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39988
09128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3998809128
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.2650028034
Short name T1568
Test name
Test status
Simulation time 175025092 ps
CPU time 0.81 seconds
Started Jul 18 05:49:30 PM PDT 24
Finished Jul 18 05:49:37 PM PDT 24
Peak memory 206652 kb
Host smart-d02cd568-4583-4b58-81da-c82433c8e6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26500
28034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.2650028034
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.358129015
Short name T1928
Test name
Test status
Simulation time 155886445 ps
CPU time 0.8 seconds
Started Jul 18 05:49:24 PM PDT 24
Finished Jul 18 05:49:30 PM PDT 24
Peak memory 206648 kb
Host smart-bb9b9c83-4e03-4ef2-b718-c3a1a43d3d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35812
9015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.358129015
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.589340942
Short name T1128
Test name
Test status
Simulation time 227584675 ps
CPU time 0.9 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:23 PM PDT 24
Peak memory 206636 kb
Host smart-3e8100d9-4f3f-4b41-8133-52324149e94a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58934
0942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.589340942
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.3976914394
Short name T1886
Test name
Test status
Simulation time 8307872831 ps
CPU time 80.06 seconds
Started Jul 18 05:49:22 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206924 kb
Host smart-5f1b528f-9e79-4f10-9057-22f6191a8f80
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3976914394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.3976914394
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.2721802276
Short name T1396
Test name
Test status
Simulation time 261273374 ps
CPU time 0.88 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206636 kb
Host smart-96950ba4-bfb0-4093-9f45-379f0880e053
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27218
02276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.2721802276
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1021358870
Short name T817
Test name
Test status
Simulation time 23298339323 ps
CPU time 25.95 seconds
Started Jul 18 05:49:25 PM PDT 24
Finished Jul 18 05:49:56 PM PDT 24
Peak memory 206776 kb
Host smart-70d2ebc7-3fb2-4355-948a-1e7eeea55a3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10213
58870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1021358870
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.134953373
Short name T2438
Test name
Test status
Simulation time 3319925968 ps
CPU time 3.57 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206792 kb
Host smart-b44f4c80-7bd2-4676-962b-69aafe4040a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13495
3373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.134953373
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.3090922690
Short name T154
Test name
Test status
Simulation time 6173711784 ps
CPU time 173.05 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:52:17 PM PDT 24
Peak memory 206920 kb
Host smart-5e96b4e8-7ca4-436c-b9bb-46f958e6634a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
22690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.3090922690
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1002191263
Short name T550
Test name
Test status
Simulation time 4573447723 ps
CPU time 32.16 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:49 PM PDT 24
Peak memory 206956 kb
Host smart-3b56149b-6d26-443a-9353-73029a3056ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1002191263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1002191263
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.52560136
Short name T1427
Test name
Test status
Simulation time 245163989 ps
CPU time 0.91 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206748 kb
Host smart-2e540235-295b-4f88-9860-f87433a3401e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=52560136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.52560136
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.1165997944
Short name T1513
Test name
Test status
Simulation time 192757116 ps
CPU time 0.9 seconds
Started Jul 18 05:49:23 PM PDT 24
Finished Jul 18 05:49:29 PM PDT 24
Peak memory 206648 kb
Host smart-555f5f74-d43a-4fdd-a827-03b323351bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11659
97944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.1165997944
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.708333648
Short name T2409
Test name
Test status
Simulation time 3779362192 ps
CPU time 27.52 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:47 PM PDT 24
Peak memory 206912 kb
Host smart-03d16b31-d560-4acd-a7b1-03df5a8c178d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70833
3648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.708333648
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1239584842
Short name T2381
Test name
Test status
Simulation time 5824673338 ps
CPU time 161.42 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:52:05 PM PDT 24
Peak memory 206844 kb
Host smart-cf67d3d0-b19e-4d90-8c87-85351dcb7d36
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1239584842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1239584842
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2852228849
Short name T216
Test name
Test status
Simulation time 162698017 ps
CPU time 0.83 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206652 kb
Host smart-1fe34c29-5bef-41d4-a00d-e593ecba9195
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2852228849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2852228849
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3935925430
Short name T1085
Test name
Test status
Simulation time 165510413 ps
CPU time 0.79 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206648 kb
Host smart-dceb2c06-9945-4ec2-a9f0-fac5d4246a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39359
25430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3935925430
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.1882383075
Short name T2653
Test name
Test status
Simulation time 207233448 ps
CPU time 0.86 seconds
Started Jul 18 05:49:26 PM PDT 24
Finished Jul 18 05:49:32 PM PDT 24
Peak memory 206656 kb
Host smart-1b655533-7c62-45b5-a042-4c22b6ee2ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18823
83075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.1882383075
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3228773817
Short name T2227
Test name
Test status
Simulation time 197821882 ps
CPU time 0.88 seconds
Started Jul 18 05:49:21 PM PDT 24
Finished Jul 18 05:49:27 PM PDT 24
Peak memory 206644 kb
Host smart-087962fb-d60c-48b4-8750-96f480ce7fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32287
73817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3228773817
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2075605094
Short name T336
Test name
Test status
Simulation time 148144772 ps
CPU time 0.77 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206644 kb
Host smart-953669ce-42dd-4ff7-a8c4-a8766573a113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20756
05094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2075605094
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.4067822618
Short name T21
Test name
Test status
Simulation time 202108731 ps
CPU time 0.84 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:34 PM PDT 24
Peak memory 206632 kb
Host smart-9b1c8ead-55f8-4aeb-9f1d-f94011c86c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40678
22618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.4067822618
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.1796346327
Short name T454
Test name
Test status
Simulation time 146800996 ps
CPU time 0.76 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:25 PM PDT 24
Peak memory 206648 kb
Host smart-d3e2f7f7-3245-4e02-af47-ff6278ce8898
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17963
46327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.1796346327
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2637677243
Short name T2252
Test name
Test status
Simulation time 223915301 ps
CPU time 0.96 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206652 kb
Host smart-2f212775-bdd8-49bc-8e05-046cc4b5579c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2637677243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2637677243
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.1117313726
Short name T873
Test name
Test status
Simulation time 141523488 ps
CPU time 0.76 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:26 PM PDT 24
Peak memory 206648 kb
Host smart-b5e5585c-736e-47c0-badb-7ed4ceb5b3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
13726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.1117313726
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.2297250828
Short name T2725
Test name
Test status
Simulation time 32591836 ps
CPU time 0.66 seconds
Started Jul 18 05:49:22 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206584 kb
Host smart-0ee01122-3e7b-4c6b-9cb7-cc9bf28a2a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22972
50828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.2297250828
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.2295034184
Short name T1579
Test name
Test status
Simulation time 22364967631 ps
CPU time 49 seconds
Started Jul 18 05:49:22 PM PDT 24
Finished Jul 18 05:50:16 PM PDT 24
Peak memory 206880 kb
Host smart-f196951c-b64e-4319-8796-a282c8426ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950
34184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.2295034184
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1755463063
Short name T693
Test name
Test status
Simulation time 173918947 ps
CPU time 0.87 seconds
Started Jul 18 05:49:22 PM PDT 24
Finished Jul 18 05:49:28 PM PDT 24
Peak memory 206652 kb
Host smart-6794ec98-aa70-443a-bd9d-5d2dd1aa7edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17554
63063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1755463063
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.586064747
Short name T596
Test name
Test status
Simulation time 189674003 ps
CPU time 0.81 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:22 PM PDT 24
Peak memory 206532 kb
Host smart-b355e4a5-4648-4572-9668-dc20356aec06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58606
4747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.586064747
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.2673083781
Short name T380
Test name
Test status
Simulation time 204710125 ps
CPU time 0.83 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:18 PM PDT 24
Peak memory 206616 kb
Host smart-47b96b85-0d8d-4b7a-b267-cbe83575c6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
83781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.2673083781
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.156733542
Short name T576
Test name
Test status
Simulation time 215816659 ps
CPU time 0.91 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:21 PM PDT 24
Peak memory 206400 kb
Host smart-dc0a001b-1fec-43a3-a3bd-4959dc790c4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15673
3542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.156733542
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.1742530021
Short name T1561
Test name
Test status
Simulation time 158095778 ps
CPU time 0.75 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206476 kb
Host smart-38413d3a-629a-4eff-a29a-01aa3c1be2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17425
30021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.1742530021
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3281961850
Short name T1151
Test name
Test status
Simulation time 149204662 ps
CPU time 0.77 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206452 kb
Host smart-187b8120-cbaf-440d-83d7-63cfe94ceb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32819
61850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3281961850
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.167611886
Short name T1134
Test name
Test status
Simulation time 202560555 ps
CPU time 0.81 seconds
Started Jul 18 05:49:13 PM PDT 24
Finished Jul 18 05:49:18 PM PDT 24
Peak memory 206624 kb
Host smart-9623ccaf-8f36-4e01-9521-b87381a52543
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16761
1886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.167611886
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.3535344892
Short name T372
Test name
Test status
Simulation time 241131219 ps
CPU time 0.91 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206644 kb
Host smart-ea7b07c6-320e-46bf-bc30-036734eb2209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35353
44892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.3535344892
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3839342307
Short name T2144
Test name
Test status
Simulation time 4201524934 ps
CPU time 41.25 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:56 PM PDT 24
Peak memory 206904 kb
Host smart-92c531fe-123c-401a-9ee7-e33c64b14e29
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3839342307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3839342307
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1883324665
Short name T812
Test name
Test status
Simulation time 195684612 ps
CPU time 0.83 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206456 kb
Host smart-50690b98-f12b-4546-a4d8-d53a692d464a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18833
24665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1883324665
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.627833037
Short name T546
Test name
Test status
Simulation time 191648135 ps
CPU time 0.82 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:16 PM PDT 24
Peak memory 206620 kb
Host smart-981ed61a-5a3c-4c3f-8092-a73375a1df51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62783
3037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.627833037
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.222918581
Short name T1626
Test name
Test status
Simulation time 747094659 ps
CPU time 1.78 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:49:19 PM PDT 24
Peak memory 206740 kb
Host smart-4dfca3db-7875-4f6e-9dd2-bffb9c59aeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22291
8581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.222918581
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3161712798
Short name T620
Test name
Test status
Simulation time 7427662636 ps
CPU time 211.04 seconds
Started Jul 18 05:49:12 PM PDT 24
Finished Jul 18 05:52:47 PM PDT 24
Peak memory 206836 kb
Host smart-d5113cda-5d17-4add-be03-4cf9843b18b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31617
12798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3161712798
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.2001247081
Short name T1553
Test name
Test status
Simulation time 48469722 ps
CPU time 0.69 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:42 PM PDT 24
Peak memory 206680 kb
Host smart-a9098322-c349-4834-b73e-784505eb7906
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2001247081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.2001247081
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2731699155
Short name T777
Test name
Test status
Simulation time 3874571695 ps
CPU time 4.5 seconds
Started Jul 18 05:49:20 PM PDT 24
Finished Jul 18 05:49:29 PM PDT 24
Peak memory 206720 kb
Host smart-c775106b-7d77-4c45-8a18-2de297d3baf1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2731699155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.2731699155
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2703039485
Short name T2102
Test name
Test status
Simulation time 13350480264 ps
CPU time 12.69 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:34 PM PDT 24
Peak memory 206800 kb
Host smart-c927f677-41a4-4e8c-b629-971ba5c3ea2e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2703039485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2703039485
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.2004587159
Short name T1332
Test name
Test status
Simulation time 23404389595 ps
CPU time 24.59 seconds
Started Jul 18 05:49:10 PM PDT 24
Finished Jul 18 05:49:37 PM PDT 24
Peak memory 206776 kb
Host smart-e7731e27-793f-44e1-a25b-d6eed4be0e19
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2004587159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.2004587159
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.399222013
Short name T1276
Test name
Test status
Simulation time 230937433 ps
CPU time 0.93 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:21 PM PDT 24
Peak memory 206668 kb
Host smart-315a9b64-bee9-4734-bc9c-350f2a0c7325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39922
2013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.399222013
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1277682721
Short name T673
Test name
Test status
Simulation time 163574753 ps
CPU time 0.77 seconds
Started Jul 18 05:49:19 PM PDT 24
Finished Jul 18 05:49:25 PM PDT 24
Peak memory 206660 kb
Host smart-21a00736-8857-436f-aedf-d66a121c45d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12776
82721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1277682721
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.1533476615
Short name T1451
Test name
Test status
Simulation time 483549995 ps
CPU time 1.62 seconds
Started Jul 18 05:49:15 PM PDT 24
Finished Jul 18 05:49:21 PM PDT 24
Peak memory 206644 kb
Host smart-24089761-93e0-44d7-967e-0cfa1eb9b344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15334
76615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.1533476615
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3390805345
Short name T882
Test name
Test status
Simulation time 309817824 ps
CPU time 0.98 seconds
Started Jul 18 05:49:30 PM PDT 24
Finished Jul 18 05:49:37 PM PDT 24
Peak memory 206656 kb
Host smart-049344ef-b702-4649-9e82-a670d0cfb24a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908
05345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3390805345
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2257579036
Short name T894
Test name
Test status
Simulation time 18394384773 ps
CPU time 37.24 seconds
Started Jul 18 05:49:16 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206904 kb
Host smart-d1be9983-c778-4d6a-a902-f2e138f41c87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22575
79036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2257579036
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.1267863928
Short name T651
Test name
Test status
Simulation time 351647032 ps
CPU time 1.32 seconds
Started Jul 18 05:49:25 PM PDT 24
Finished Jul 18 05:49:32 PM PDT 24
Peak memory 206652 kb
Host smart-d876b075-487b-4aed-8316-d6c3bc7a104b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12678
63928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.1267863928
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.4062685846
Short name T534
Test name
Test status
Simulation time 200033831 ps
CPU time 0.83 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:34 PM PDT 24
Peak memory 206652 kb
Host smart-d009be6a-14f8-4794-962f-23d01b063e0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40626
85846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.4062685846
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.2163059527
Short name T900
Test name
Test status
Simulation time 51821821 ps
CPU time 0.75 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206644 kb
Host smart-9c8d5d0f-174e-4d1e-815a-caa201ca62d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21630
59527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.2163059527
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.1507266435
Short name T2601
Test name
Test status
Simulation time 850139913 ps
CPU time 2.17 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:45 PM PDT 24
Peak memory 206792 kb
Host smart-7a15fdf9-1e24-463a-bc0f-6969e699c1a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15072
66435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.1507266435
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.625004077
Short name T1370
Test name
Test status
Simulation time 229225364 ps
CPU time 1.91 seconds
Started Jul 18 05:49:42 PM PDT 24
Finished Jul 18 05:49:48 PM PDT 24
Peak memory 206740 kb
Host smart-a18de5c8-30f3-471a-9bf7-f723533224ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62500
4077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.625004077
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.673218658
Short name T22
Test name
Test status
Simulation time 228668825 ps
CPU time 1 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:49:45 PM PDT 24
Peak memory 206608 kb
Host smart-8b84259e-f522-4bbc-bf32-2294221eab1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67321
8658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.673218658
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3099486482
Short name T1301
Test name
Test status
Simulation time 162033305 ps
CPU time 0.82 seconds
Started Jul 18 05:49:26 PM PDT 24
Finished Jul 18 05:49:32 PM PDT 24
Peak memory 206632 kb
Host smart-730311cb-f992-4ca2-a8fb-b816b68f5279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
86482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3099486482
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1228171044
Short name T2245
Test name
Test status
Simulation time 211849579 ps
CPU time 0.85 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:43 PM PDT 24
Peak memory 206620 kb
Host smart-162a8cc5-5a0d-4289-b135-bffa07e87245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12281
71044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1228171044
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.386980826
Short name T2511
Test name
Test status
Simulation time 10896656754 ps
CPU time 40 seconds
Started Jul 18 05:49:35 PM PDT 24
Finished Jul 18 05:50:20 PM PDT 24
Peak memory 206884 kb
Host smart-f8086222-0a93-4681-bad4-b57bfa3d38ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38698
0826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.386980826
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.1064235323
Short name T2157
Test name
Test status
Simulation time 230260590 ps
CPU time 0.95 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206632 kb
Host smart-d65e4b46-9237-4e87-8467-349640c34e73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
35323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.1064235323
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.407532090
Short name T360
Test name
Test status
Simulation time 23359220191 ps
CPU time 21.09 seconds
Started Jul 18 05:49:26 PM PDT 24
Finished Jul 18 05:49:52 PM PDT 24
Peak memory 206932 kb
Host smart-520e7826-0f5d-4886-bbee-2d7afd6bd238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40753
2090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.407532090
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.1055238945
Short name T2454
Test name
Test status
Simulation time 3261554688 ps
CPU time 3.6 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206704 kb
Host smart-96f01b69-8e75-41db-9793-79611a2f2ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10552
38945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.1055238945
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.653278667
Short name T1039
Test name
Test status
Simulation time 8507815629 ps
CPU time 62.93 seconds
Started Jul 18 05:49:31 PM PDT 24
Finished Jul 18 05:50:40 PM PDT 24
Peak memory 206928 kb
Host smart-c4f5d3d5-f082-4478-bcbf-947151c38704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65327
8667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.653278667
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.2150751583
Short name T725
Test name
Test status
Simulation time 3814351910 ps
CPU time 101.19 seconds
Started Jul 18 05:49:40 PM PDT 24
Finished Jul 18 05:51:26 PM PDT 24
Peak memory 206844 kb
Host smart-858a8e0d-5dd6-467e-9628-ccb9d338f727
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2150751583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.2150751583
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1957359834
Short name T2408
Test name
Test status
Simulation time 236308859 ps
CPU time 0.88 seconds
Started Jul 18 05:49:33 PM PDT 24
Finished Jul 18 05:49:39 PM PDT 24
Peak memory 206652 kb
Host smart-6059370b-57ad-4c9a-bd11-f7933845b009
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1957359834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1957359834
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3834387353
Short name T2129
Test name
Test status
Simulation time 194678389 ps
CPU time 0.86 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206640 kb
Host smart-d895a6bb-ddde-4b29-85a6-6b2318fc146f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38343
87353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3834387353
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.431198890
Short name T1163
Test name
Test status
Simulation time 4000513358 ps
CPU time 111.51 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206836 kb
Host smart-ec1b249a-c9ec-4838-afe6-04555711b9e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43119
8890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.431198890
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3905882985
Short name T2439
Test name
Test status
Simulation time 4951926665 ps
CPU time 142.91 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206832 kb
Host smart-9dd8532c-7f25-4e42-a3b5-73a3634b0f42
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3905882985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3905882985
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.37203356
Short name T754
Test name
Test status
Simulation time 189711082 ps
CPU time 0.87 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206620 kb
Host smart-7ec6ec7a-1091-4085-bd16-49d313c04a66
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=37203356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.37203356
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.3012101855
Short name T2135
Test name
Test status
Simulation time 196840549 ps
CPU time 0.87 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:43 PM PDT 24
Peak memory 206644 kb
Host smart-5e4fc703-cbbc-40c5-ae57-7d059197a853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30121
01855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.3012101855
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3234792503
Short name T2379
Test name
Test status
Simulation time 214377853 ps
CPU time 0.94 seconds
Started Jul 18 05:49:42 PM PDT 24
Finished Jul 18 05:49:47 PM PDT 24
Peak memory 206580 kb
Host smart-25e1b96c-5fc0-4fa8-b0c7-4047349df0f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32347
92503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3234792503
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.1967422995
Short name T508
Test name
Test status
Simulation time 186584850 ps
CPU time 0.83 seconds
Started Jul 18 05:49:33 PM PDT 24
Finished Jul 18 05:49:39 PM PDT 24
Peak memory 206652 kb
Host smart-c35cb374-771f-4f73-8d8e-b7afcaff1ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19674
22995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.1967422995
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3111289571
Short name T2484
Test name
Test status
Simulation time 178537163 ps
CPU time 0.87 seconds
Started Jul 18 05:49:31 PM PDT 24
Finished Jul 18 05:49:37 PM PDT 24
Peak memory 206660 kb
Host smart-edc5b146-32b9-4a14-8c38-8c9dc7044939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31112
89571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3111289571
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.2915246185
Short name T313
Test name
Test status
Simulation time 197843422 ps
CPU time 0.86 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206636 kb
Host smart-ffb4fcc9-1c09-4ad4-9e64-4e5231df057f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29152
46185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.2915246185
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.3217107701
Short name T2429
Test name
Test status
Simulation time 145291288 ps
CPU time 0.81 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206660 kb
Host smart-f86f60ed-321c-4701-9321-44d4b57586ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32171
07701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.3217107701
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.691183858
Short name T1939
Test name
Test status
Simulation time 236900903 ps
CPU time 0.92 seconds
Started Jul 18 05:49:31 PM PDT 24
Finished Jul 18 05:49:38 PM PDT 24
Peak memory 206632 kb
Host smart-aded60c5-3238-45b4-a99f-f7d96e330169
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=691183858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.691183858
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1851822960
Short name T1881
Test name
Test status
Simulation time 176362934 ps
CPU time 0.88 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206636 kb
Host smart-47261eab-8f17-40b7-aac2-6efa0d448880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18518
22960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1851822960
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.344656463
Short name T2152
Test name
Test status
Simulation time 85417303 ps
CPU time 0.69 seconds
Started Jul 18 05:49:31 PM PDT 24
Finished Jul 18 05:49:38 PM PDT 24
Peak memory 206632 kb
Host smart-647d5c1c-95ea-4c2d-a883-5793dd1c5480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34465
6463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.344656463
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1683817058
Short name T40
Test name
Test status
Simulation time 16051883104 ps
CPU time 40.6 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:50:13 PM PDT 24
Peak memory 206852 kb
Host smart-01703111-89f6-4b60-9ba7-9ef0f68546d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16838
17058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1683817058
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3086399875
Short name T1220
Test name
Test status
Simulation time 189672143 ps
CPU time 0.9 seconds
Started Jul 18 05:49:42 PM PDT 24
Finished Jul 18 05:49:47 PM PDT 24
Peak memory 206652 kb
Host smart-286db97d-2c74-44f1-9b2f-1f1dfce60db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30863
99875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3086399875
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.1168310290
Short name T2318
Test name
Test status
Simulation time 203022387 ps
CPU time 0.93 seconds
Started Jul 18 05:49:25 PM PDT 24
Finished Jul 18 05:49:31 PM PDT 24
Peak memory 206636 kb
Host smart-b8119bb4-5274-4cc3-a978-6b4034f78fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11683
10290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.1168310290
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.362884545
Short name T2038
Test name
Test status
Simulation time 276129405 ps
CPU time 0.99 seconds
Started Jul 18 05:49:30 PM PDT 24
Finished Jul 18 05:49:37 PM PDT 24
Peak memory 206652 kb
Host smart-83f37cf0-8889-468e-8fc7-6fa6e52e9c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36288
4545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.362884545
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.697825286
Short name T1721
Test name
Test status
Simulation time 179557450 ps
CPU time 0.83 seconds
Started Jul 18 05:49:27 PM PDT 24
Finished Jul 18 05:49:33 PM PDT 24
Peak memory 206636 kb
Host smart-20660666-7172-45c3-93dd-4541181c5d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69782
5286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.697825286
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.1355782246
Short name T2464
Test name
Test status
Simulation time 177348774 ps
CPU time 0.83 seconds
Started Jul 18 05:49:36 PM PDT 24
Finished Jul 18 05:49:41 PM PDT 24
Peak memory 206592 kb
Host smart-b2dc4cff-97c8-4c8a-957e-82fcb90c6096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13557
82246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.1355782246
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.542467107
Short name T332
Test name
Test status
Simulation time 157399821 ps
CPU time 0.81 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206612 kb
Host smart-d2674bef-adf9-4c9e-949d-8764c1c2acf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54246
7107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.542467107
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.4261678205
Short name T1083
Test name
Test status
Simulation time 155823650 ps
CPU time 0.81 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:49:45 PM PDT 24
Peak memory 206668 kb
Host smart-5bf52c75-f3cf-45b6-a472-aeb1767af351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42616
78205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.4261678205
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.372157245
Short name T1024
Test name
Test status
Simulation time 243137772 ps
CPU time 1.15 seconds
Started Jul 18 05:49:42 PM PDT 24
Finished Jul 18 05:49:47 PM PDT 24
Peak memory 206616 kb
Host smart-4bf06eb3-962f-4b16-9b41-52a37db12c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37215
7245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.372157245
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.1078808013
Short name T2546
Test name
Test status
Simulation time 4463764556 ps
CPU time 40.72 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:50:24 PM PDT 24
Peak memory 206828 kb
Host smart-15006d04-5958-420e-b769-e962dddef216
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1078808013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.1078808013
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2080522551
Short name T1193
Test name
Test status
Simulation time 185141900 ps
CPU time 0.83 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:49:45 PM PDT 24
Peak memory 206620 kb
Host smart-7d071086-1e0e-4517-baf7-100a6fb56bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20805
22551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2080522551
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3942382836
Short name T1840
Test name
Test status
Simulation time 165736176 ps
CPU time 0.84 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206636 kb
Host smart-36bdb64d-d1a2-41c1-9bf1-d93af6ebd0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39423
82836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3942382836
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.2630883608
Short name T1074
Test name
Test status
Simulation time 494118167 ps
CPU time 1.61 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206628 kb
Host smart-8e1b5a8b-25fe-479a-8e3c-3cba00feb63f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26308
83608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.2630883608
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.1665034239
Short name T1471
Test name
Test status
Simulation time 5365598245 ps
CPU time 52.15 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:50:35 PM PDT 24
Peak memory 206924 kb
Host smart-f485174a-a8dc-457b-97e5-48070f4c5126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16650
34239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.1665034239
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.4018117996
Short name T1800
Test name
Test status
Simulation time 99761401 ps
CPU time 0.74 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206700 kb
Host smart-ef921958-b0b1-4438-8166-c09a03609634
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4018117996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.4018117996
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.3827178996
Short name T1735
Test name
Test status
Simulation time 4041049209 ps
CPU time 4.62 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:39 PM PDT 24
Peak memory 206808 kb
Host smart-45c1d91e-8a4f-4ddd-bfb6-3fc58e1782f5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3827178996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.3827178996
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2364586361
Short name T1773
Test name
Test status
Simulation time 13340577500 ps
CPU time 12.6 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:55 PM PDT 24
Peak memory 206744 kb
Host smart-d3c5e938-0ab5-490b-92d5-3a052eaafe29
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2364586361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2364586361
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2167907773
Short name T1522
Test name
Test status
Simulation time 23318612201 ps
CPU time 22.78 seconds
Started Jul 18 05:49:26 PM PDT 24
Finished Jul 18 05:49:54 PM PDT 24
Peak memory 206752 kb
Host smart-f991a92d-4586-4714-9a21-113a0a88d57d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2167907773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.2167907773
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.4239578592
Short name T842
Test name
Test status
Simulation time 229404336 ps
CPU time 0.98 seconds
Started Jul 18 05:49:40 PM PDT 24
Finished Jul 18 05:49:46 PM PDT 24
Peak memory 206596 kb
Host smart-5591b2af-12d6-4832-a9f1-9f73a9ae826e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42395
78592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.4239578592
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1686433462
Short name T1315
Test name
Test status
Simulation time 194099331 ps
CPU time 0.85 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206632 kb
Host smart-b34a23d7-68ce-425c-a00a-9d550e8ec404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16864
33462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1686433462
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.1755465858
Short name T1106
Test name
Test status
Simulation time 417206851 ps
CPU time 1.24 seconds
Started Jul 18 05:49:32 PM PDT 24
Finished Jul 18 05:49:38 PM PDT 24
Peak memory 206616 kb
Host smart-7005b63c-cbd1-4ebe-a8b0-c8abf2e4dfcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17554
65858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.1755465858
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3100035817
Short name T1036
Test name
Test status
Simulation time 331281703 ps
CPU time 0.98 seconds
Started Jul 18 05:49:35 PM PDT 24
Finished Jul 18 05:49:40 PM PDT 24
Peak memory 206648 kb
Host smart-6de9c754-aaeb-490d-8357-093592f2a54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31000
35817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3100035817
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3809001103
Short name T706
Test name
Test status
Simulation time 11568878094 ps
CPU time 22.54 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:56 PM PDT 24
Peak memory 206908 kb
Host smart-d4e564cc-a2b3-4898-bb32-8c9c3e03f6d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38090
01103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3809001103
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_device_timeout.1442470071
Short name T1987
Test name
Test status
Simulation time 144857474 ps
CPU time 0.82 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206620 kb
Host smart-73d4da93-78d6-4550-8911-3709c622ec0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14424
70071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_timeout.1442470071
Directory /workspace/35.usbdev_device_timeout/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1516990813
Short name T905
Test name
Test status
Simulation time 408186665 ps
CPU time 1.3 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:36 PM PDT 24
Peak memory 206652 kb
Host smart-d7c3b766-6bbb-4272-877e-1261d0b06357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15169
90813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1516990813
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1092595727
Short name T1399
Test name
Test status
Simulation time 145098930 ps
CPU time 0.86 seconds
Started Jul 18 05:49:40 PM PDT 24
Finished Jul 18 05:49:46 PM PDT 24
Peak memory 206672 kb
Host smart-6829e6ba-90d1-4484-9fea-6dc1840ab975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10925
95727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1092595727
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.1641845219
Short name T2116
Test name
Test status
Simulation time 54453932 ps
CPU time 0.73 seconds
Started Jul 18 05:49:36 PM PDT 24
Finished Jul 18 05:49:41 PM PDT 24
Peak memory 206640 kb
Host smart-2a691c16-dbbb-4e52-9146-9f7877a8f1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418
45219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.1641845219
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.1061882279
Short name T1820
Test name
Test status
Simulation time 848823708 ps
CPU time 1.99 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:49:46 PM PDT 24
Peak memory 206736 kb
Host smart-93804592-a920-4155-b607-9204df9f78f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10618
82279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.1061882279
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.3494768296
Short name T730
Test name
Test status
Simulation time 280609988 ps
CPU time 1.93 seconds
Started Jul 18 05:49:40 PM PDT 24
Finished Jul 18 05:49:47 PM PDT 24
Peak memory 206752 kb
Host smart-6979a098-e350-43d5-a1d2-51190617e6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
68296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.3494768296
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2447345489
Short name T1021
Test name
Test status
Simulation time 173682419 ps
CPU time 0.85 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206648 kb
Host smart-be7a24cf-8d47-4d56-863a-af04203badc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
45489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2447345489
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.770075605
Short name T854
Test name
Test status
Simulation time 144386269 ps
CPU time 0.81 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:36 PM PDT 24
Peak memory 206624 kb
Host smart-44472aec-20e2-4aea-8b05-aa5ef3f557c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77007
5605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.770075605
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2347842614
Short name T1377
Test name
Test status
Simulation time 192707323 ps
CPU time 0.84 seconds
Started Jul 18 05:49:31 PM PDT 24
Finished Jul 18 05:49:38 PM PDT 24
Peak memory 206648 kb
Host smart-a8efa798-b1bf-4973-aaa8-ccd1aac99196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23478
42614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2347842614
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.4001553007
Short name T2616
Test name
Test status
Simulation time 6400836632 ps
CPU time 18.92 seconds
Started Jul 18 05:49:32 PM PDT 24
Finished Jul 18 05:49:56 PM PDT 24
Peak memory 206848 kb
Host smart-89a48cd5-b5ff-4733-a3dc-abab8ad88ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40015
53007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.4001553007
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2914419553
Short name T1310
Test name
Test status
Simulation time 172923728 ps
CPU time 0.82 seconds
Started Jul 18 05:49:43 PM PDT 24
Finished Jul 18 05:49:48 PM PDT 24
Peak memory 206636 kb
Host smart-449e2400-9b50-4ed6-8694-04aeac6dd5bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29144
19553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2914419553
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.3840762664
Short name T183
Test name
Test status
Simulation time 23318692443 ps
CPU time 24.98 seconds
Started Jul 18 05:49:33 PM PDT 24
Finished Jul 18 05:50:03 PM PDT 24
Peak memory 206776 kb
Host smart-83e84013-a53e-4c83-85b2-2ae981c0cf69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38407
62664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.3840762664
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2592037688
Short name T2540
Test name
Test status
Simulation time 3346870000 ps
CPU time 4.82 seconds
Started Jul 18 05:49:31 PM PDT 24
Finished Jul 18 05:49:41 PM PDT 24
Peak memory 206724 kb
Host smart-e2893f8e-5b0d-4887-8eb8-9aef6c295b7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25920
37688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2592037688
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.1446330313
Short name T2055
Test name
Test status
Simulation time 6778396397 ps
CPU time 47.93 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:50:32 PM PDT 24
Peak memory 206884 kb
Host smart-79e909d4-9595-45a3-ba36-c81323ccfc8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14463
30313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.1446330313
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3729069683
Short name T1378
Test name
Test status
Simulation time 4143392030 ps
CPU time 29.62 seconds
Started Jul 18 05:49:35 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206864 kb
Host smart-5b826d9f-fae3-41dc-9b4e-1993f9ced089
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3729069683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3729069683
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.3453722887
Short name T1508
Test name
Test status
Simulation time 242332424 ps
CPU time 0.94 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206616 kb
Host smart-8b4147b3-61c7-4fd5-8f54-f5b3018d2c3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3453722887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.3453722887
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.2647984886
Short name T395
Test name
Test status
Simulation time 234152667 ps
CPU time 0.93 seconds
Started Jul 18 05:49:43 PM PDT 24
Finished Jul 18 05:49:48 PM PDT 24
Peak memory 206388 kb
Host smart-0643a581-f947-4724-8fb0-55e47d225228
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26479
84886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.2647984886
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2622626029
Short name T2599
Test name
Test status
Simulation time 5927847741 ps
CPU time 164.72 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:52:28 PM PDT 24
Peak memory 206844 kb
Host smart-e0fe6061-c632-406c-a337-4d4a4da05058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26226
26029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2622626029
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.1499875894
Short name T6
Test name
Test status
Simulation time 6950305866 ps
CPU time 63.33 seconds
Started Jul 18 05:49:33 PM PDT 24
Finished Jul 18 05:50:41 PM PDT 24
Peak memory 206904 kb
Host smart-1e370097-97b1-461c-9862-af611e781258
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1499875894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.1499875894
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.1420516171
Short name T345
Test name
Test status
Simulation time 165285989 ps
CPU time 0.83 seconds
Started Jul 18 05:49:43 PM PDT 24
Finished Jul 18 05:49:48 PM PDT 24
Peak memory 206372 kb
Host smart-b276b308-606d-4fd4-8e8d-449debfff143
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1420516171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.1420516171
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.491927719
Short name T1822
Test name
Test status
Simulation time 145598162 ps
CPU time 0.78 seconds
Started Jul 18 05:49:29 PM PDT 24
Finished Jul 18 05:49:36 PM PDT 24
Peak memory 206620 kb
Host smart-dea07c91-f018-4474-9409-1d1feb9b950e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49192
7719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.491927719
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.1867165886
Short name T2297
Test name
Test status
Simulation time 190023033 ps
CPU time 0.84 seconds
Started Jul 18 05:49:35 PM PDT 24
Finished Jul 18 05:49:41 PM PDT 24
Peak memory 206652 kb
Host smart-b74dcb8a-dd62-4e4b-a585-54efeb694b51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18671
65886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.1867165886
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.4088170268
Short name T2299
Test name
Test status
Simulation time 159374335 ps
CPU time 0.79 seconds
Started Jul 18 05:49:42 PM PDT 24
Finished Jul 18 05:49:47 PM PDT 24
Peak memory 206556 kb
Host smart-38e1f8ad-26da-4d01-bf9f-54fe73f64cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40881
70268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.4088170268
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.3054493427
Short name T324
Test name
Test status
Simulation time 174813450 ps
CPU time 0.82 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:34 PM PDT 24
Peak memory 206640 kb
Host smart-6a6cf6e5-0cf0-4166-8a0a-1889d0a060a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30544
93427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.3054493427
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.2925515499
Short name T1186
Test name
Test status
Simulation time 174712395 ps
CPU time 0.85 seconds
Started Jul 18 05:49:28 PM PDT 24
Finished Jul 18 05:49:35 PM PDT 24
Peak memory 206624 kb
Host smart-1163bd6a-e1dd-4005-8f36-d88e139e4da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29255
15499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.2925515499
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1978088665
Short name T793
Test name
Test status
Simulation time 151087959 ps
CPU time 0.81 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:43 PM PDT 24
Peak memory 206636 kb
Host smart-2a1701e2-2206-435a-861b-94604a5e6996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19780
88665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1978088665
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.4264091004
Short name T2194
Test name
Test status
Simulation time 213815324 ps
CPU time 0.94 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:49:45 PM PDT 24
Peak memory 206640 kb
Host smart-7df82e2f-5701-46dd-9e7a-653ee98d27b4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4264091004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.4264091004
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.957164145
Short name T1623
Test name
Test status
Simulation time 141744532 ps
CPU time 0.74 seconds
Started Jul 18 05:49:30 PM PDT 24
Finished Jul 18 05:49:36 PM PDT 24
Peak memory 206644 kb
Host smart-5d0aadf2-3b5c-411f-aad0-e61eb0b72589
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95716
4145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.957164145
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.1719219906
Short name T1342
Test name
Test status
Simulation time 47787262 ps
CPU time 0.67 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:43 PM PDT 24
Peak memory 206616 kb
Host smart-82472c29-feed-404a-9e81-49ddf880cbac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17192
19906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.1719219906
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.4180093077
Short name T232
Test name
Test status
Simulation time 6100536821 ps
CPU time 14.51 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:58 PM PDT 24
Peak memory 206880 kb
Host smart-4455b83d-3cd7-4460-a262-4aeb6316e474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41800
93077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.4180093077
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.1357299607
Short name T571
Test name
Test status
Simulation time 184391305 ps
CPU time 0.89 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206656 kb
Host smart-a7e46953-b3b1-499e-8a6f-ed7396f14cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
99607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.1357299607
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1434977457
Short name T2629
Test name
Test status
Simulation time 165197124 ps
CPU time 0.82 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:42 PM PDT 24
Peak memory 206644 kb
Host smart-2d05590d-6866-4990-a308-63f2c662c5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14349
77457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1434977457
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.4059247505
Short name T878
Test name
Test status
Simulation time 174719735 ps
CPU time 0.86 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206648 kb
Host smart-61e09e1f-be8b-4d24-95db-8d288aba312e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40592
47505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.4059247505
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.3821431324
Short name T1934
Test name
Test status
Simulation time 151755582 ps
CPU time 0.85 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:44 PM PDT 24
Peak memory 206620 kb
Host smart-ed7ce785-c2ce-4172-8537-7a7d2d1cbc63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38214
31324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.3821431324
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3149221790
Short name T1948
Test name
Test status
Simulation time 144582226 ps
CPU time 0.76 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:43 PM PDT 24
Peak memory 206620 kb
Host smart-a8586427-4cdc-4024-ae10-4d1f635e4661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31492
21790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3149221790
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.514168082
Short name T482
Test name
Test status
Simulation time 147444233 ps
CPU time 0.79 seconds
Started Jul 18 05:49:38 PM PDT 24
Finished Jul 18 05:49:43 PM PDT 24
Peak memory 206624 kb
Host smart-1ee5d26a-91f7-41fd-941f-d0fac4181a58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51416
8082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.514168082
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.4195563983
Short name T889
Test name
Test status
Simulation time 149308157 ps
CPU time 0.76 seconds
Started Jul 18 05:49:37 PM PDT 24
Finished Jul 18 05:49:42 PM PDT 24
Peak memory 206652 kb
Host smart-2371443b-72a0-4ac4-aed3-f03baee4f69f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41955
63983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.4195563983
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.3992971213
Short name T414
Test name
Test status
Simulation time 299113767 ps
CPU time 1.02 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:49:46 PM PDT 24
Peak memory 206644 kb
Host smart-7ff7c810-a8d2-40b5-b975-433584d749a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39929
71213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.3992971213
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.840595812
Short name T669
Test name
Test status
Simulation time 4518704505 ps
CPU time 41.94 seconds
Started Jul 18 05:49:39 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206860 kb
Host smart-ea8088fb-606a-48c9-bb46-656144b8ece6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=840595812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.840595812
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1167005866
Short name T1194
Test name
Test status
Simulation time 156412500 ps
CPU time 0.88 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:04 PM PDT 24
Peak memory 206656 kb
Host smart-e984cb3a-ed8a-4cca-a53b-cd785fa94502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
05866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1167005866
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.3694815234
Short name T1559
Test name
Test status
Simulation time 200821749 ps
CPU time 0.88 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206636 kb
Host smart-032aa0f8-5f66-4f75-8676-bd84a8352e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
15234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.3694815234
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1542118318
Short name T320
Test name
Test status
Simulation time 320089558 ps
CPU time 1.08 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:02 PM PDT 24
Peak memory 206640 kb
Host smart-906a3ad3-3147-4d85-be55-b3579adba27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
18318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1542118318
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2027223590
Short name T2145
Test name
Test status
Simulation time 4752100468 ps
CPU time 46.19 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206864 kb
Host smart-768478b6-7260-48d5-a5c5-969af57e9e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20272
23590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2027223590
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.1657932953
Short name T2576
Test name
Test status
Simulation time 55057220 ps
CPU time 0.69 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:05 PM PDT 24
Peak memory 206692 kb
Host smart-6b1efc18-aabb-4cc2-aa3c-2f919c68d769
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1657932953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.1657932953
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.282244245
Short name T1389
Test name
Test status
Simulation time 3441719898 ps
CPU time 4.79 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:13 PM PDT 24
Peak memory 206804 kb
Host smart-7815bd0d-f003-4baa-87ed-99452276241a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=282244245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.282244245
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2272449470
Short name T1269
Test name
Test status
Simulation time 13369019956 ps
CPU time 12.14 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:16 PM PDT 24
Peak memory 206872 kb
Host smart-ffb25f56-deb4-4433-8648-7033d6e5bb7c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2272449470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2272449470
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.839374557
Short name T2368
Test name
Test status
Simulation time 23378434340 ps
CPU time 23.14 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206932 kb
Host smart-3c738abe-5a50-4c47-92b7-a023843fddd9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=839374557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.839374557
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3926567289
Short name T1446
Test name
Test status
Simulation time 186151349 ps
CPU time 0.89 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206648 kb
Host smart-d13e6a55-1744-453f-b1c8-dda8b66c156a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39265
67289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3926567289
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.3447288101
Short name T2261
Test name
Test status
Simulation time 140527259 ps
CPU time 0.75 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206652 kb
Host smart-7a6ddc24-5604-4893-aed7-e60fbac9d641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34472
88101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.3447288101
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.4069217552
Short name T862
Test name
Test status
Simulation time 163998311 ps
CPU time 0.8 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:49:58 PM PDT 24
Peak memory 206644 kb
Host smart-61c2119d-a41c-4d35-9653-a3f70adf6c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40692
17552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.4069217552
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.2710051863
Short name T1143
Test name
Test status
Simulation time 608827341 ps
CPU time 1.64 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:11 PM PDT 24
Peak memory 206656 kb
Host smart-c1aa3580-3186-404c-8c74-8a6c032fbed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27100
51863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.2710051863
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1335531871
Short name T837
Test name
Test status
Simulation time 15863986575 ps
CPU time 27.94 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:33 PM PDT 24
Peak memory 206848 kb
Host smart-b47707cd-9f1c-4178-96c8-af1dc2ce0a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13355
31871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1335531871
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.321935764
Short name T368
Test name
Test status
Simulation time 490561130 ps
CPU time 1.85 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:03 PM PDT 24
Peak memory 206644 kb
Host smart-44e9bc0b-f263-4dd6-8098-b74ff4bdc69e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32193
5764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.321935764
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2045563411
Short name T881
Test name
Test status
Simulation time 145818038 ps
CPU time 0.75 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206640 kb
Host smart-b7fb4980-4f92-4249-8a49-9137eb477b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20455
63411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2045563411
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2527468309
Short name T1806
Test name
Test status
Simulation time 31824379 ps
CPU time 0.68 seconds
Started Jul 18 05:49:53 PM PDT 24
Finished Jul 18 05:49:55 PM PDT 24
Peak memory 206616 kb
Host smart-0feedf6d-c6c0-4875-99c8-28a3a756a32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25274
68309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2527468309
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2584227237
Short name T1226
Test name
Test status
Simulation time 781807614 ps
CPU time 2.09 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:03 PM PDT 24
Peak memory 206784 kb
Host smart-a223ebef-58f6-4232-9c2a-6b8fa588343c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25842
27237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2584227237
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.713928415
Short name T819
Test name
Test status
Simulation time 179433960 ps
CPU time 1.85 seconds
Started Jul 18 05:49:59 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206776 kb
Host smart-c03deca9-ae4f-4a5a-8636-af6051517f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71392
8415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.713928415
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1978549008
Short name T707
Test name
Test status
Simulation time 247444654 ps
CPU time 0.92 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:04 PM PDT 24
Peak memory 206592 kb
Host smart-65f9aeef-ded7-4354-b701-f3ac7555b2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19785
49008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1978549008
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1759179555
Short name T1123
Test name
Test status
Simulation time 143720818 ps
CPU time 0.76 seconds
Started Jul 18 05:49:54 PM PDT 24
Finished Jul 18 05:49:56 PM PDT 24
Peak memory 206644 kb
Host smart-7ca8eb4e-5ac9-4d0c-a0db-7eade26c8e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17591
79555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1759179555
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.3631203860
Short name T2287
Test name
Test status
Simulation time 191864599 ps
CPU time 0.88 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:01 PM PDT 24
Peak memory 206616 kb
Host smart-c47aa50d-10b2-43d5-a138-08edb4922afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36312
03860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.3631203860
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.3150892278
Short name T225
Test name
Test status
Simulation time 7688291176 ps
CPU time 210.63 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:53:34 PM PDT 24
Peak memory 206840 kb
Host smart-39da72c1-8f2c-4b82-a730-6a249885d9f1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3150892278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.3150892278
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.1968199205
Short name T422
Test name
Test status
Simulation time 197068085 ps
CPU time 0.87 seconds
Started Jul 18 05:49:59 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206652 kb
Host smart-bffe0456-0427-4f0a-a82a-e28007d3028c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19681
99205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.1968199205
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.3665935740
Short name T1898
Test name
Test status
Simulation time 23353415158 ps
CPU time 21.96 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206792 kb
Host smart-37aca405-6333-4942-ae65-e89555e3154d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36659
35740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.3665935740
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.753623735
Short name T294
Test name
Test status
Simulation time 3346708271 ps
CPU time 3.76 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:12 PM PDT 24
Peak memory 206736 kb
Host smart-b7378904-f6ec-4f15-8d94-b2859f644409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75362
3735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.753623735
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.2709649809
Short name T2470
Test name
Test status
Simulation time 11568348796 ps
CPU time 345.76 seconds
Started Jul 18 05:49:53 PM PDT 24
Finished Jul 18 05:55:40 PM PDT 24
Peak memory 206904 kb
Host smart-8cd8d218-a758-48ae-86cc-3e4ec8f8d35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27096
49809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.2709649809
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3521084441
Short name T2406
Test name
Test status
Simulation time 4352195224 ps
CPU time 41.02 seconds
Started Jul 18 05:49:54 PM PDT 24
Finished Jul 18 05:50:36 PM PDT 24
Peak memory 206844 kb
Host smart-67fab2de-a3c6-4b19-b2fe-c742636ec8d7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3521084441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3521084441
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.876265862
Short name T1622
Test name
Test status
Simulation time 233555068 ps
CPU time 0.98 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:04 PM PDT 24
Peak memory 206452 kb
Host smart-f28508e2-a71f-47f7-bf2d-146a3812c79d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=876265862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.876265862
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1619825050
Short name T2307
Test name
Test status
Simulation time 219273524 ps
CPU time 1 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:02 PM PDT 24
Peak memory 206652 kb
Host smart-c5f89ac0-d05d-4f2d-a662-60eb2e8a9a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16198
25050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1619825050
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1101030994
Short name T2033
Test name
Test status
Simulation time 6092706902 ps
CPU time 58.64 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206904 kb
Host smart-542521b1-ea2f-48e6-8ffa-56a46d07caba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11010
30994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1101030994
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1144820436
Short name T2392
Test name
Test status
Simulation time 7315522474 ps
CPU time 68.56 seconds
Started Jul 18 05:49:59 PM PDT 24
Finished Jul 18 05:51:15 PM PDT 24
Peak memory 206852 kb
Host smart-3d8ca634-f36d-4038-badc-47368f4e42f9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1144820436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1144820436
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1281535616
Short name T507
Test name
Test status
Simulation time 153123584 ps
CPU time 0.8 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:04 PM PDT 24
Peak memory 206608 kb
Host smart-4e8a340d-5867-4ba2-9d23-bec87f731494
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1281535616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1281535616
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3087257683
Short name T972
Test name
Test status
Simulation time 150476136 ps
CPU time 0.8 seconds
Started Jul 18 05:49:59 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206572 kb
Host smart-ce77a014-e16b-4e68-9a5c-05b7d3d3b7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30872
57683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3087257683
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1162895500
Short name T2341
Test name
Test status
Simulation time 187407697 ps
CPU time 0.85 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206648 kb
Host smart-94795c59-8108-400c-a6c4-95675ca6ec45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11628
95500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1162895500
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1500272477
Short name T1093
Test name
Test status
Simulation time 234546514 ps
CPU time 0.92 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206652 kb
Host smart-a0283da7-e475-4a2e-899a-2013379adb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
72477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1500272477
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.2496249820
Short name T1034
Test name
Test status
Simulation time 163700266 ps
CPU time 0.79 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206592 kb
Host smart-bb9b6a72-da23-4370-8b9a-18cacac3f3bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24962
49820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.2496249820
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.1351904455
Short name T1660
Test name
Test status
Simulation time 205212695 ps
CPU time 0.85 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206672 kb
Host smart-98f19806-5edf-4013-afb9-c756c46018e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13519
04455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.1351904455
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.2643424796
Short name T723
Test name
Test status
Simulation time 196334210 ps
CPU time 0.8 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:01 PM PDT 24
Peak memory 206648 kb
Host smart-bc1afb9a-35d9-40df-88dd-5edc711f1eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26434
24796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.2643424796
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.1882802668
Short name T1758
Test name
Test status
Simulation time 220670991 ps
CPU time 0.92 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:06 PM PDT 24
Peak memory 206644 kb
Host smart-c59368d5-fc41-4608-b1c5-591176663fac
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1882802668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.1882802668
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3834984164
Short name T1942
Test name
Test status
Simulation time 141720567 ps
CPU time 0.77 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:00 PM PDT 24
Peak memory 206640 kb
Host smart-73d9e44a-56c9-4609-b92e-d05ef1af2ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38349
84164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3834984164
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.170311792
Short name T588
Test name
Test status
Simulation time 44177117 ps
CPU time 0.69 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:11 PM PDT 24
Peak memory 206616 kb
Host smart-c1e2c19b-9d51-4a10-be9e-f835edafefe2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17031
1792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.170311792
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1164723738
Short name T1955
Test name
Test status
Simulation time 21831240005 ps
CPU time 53.21 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206916 kb
Host smart-f8a83808-3601-41d1-8937-86712f3e7e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11647
23738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1164723738
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.81367895
Short name T1175
Test name
Test status
Simulation time 191417591 ps
CPU time 0.88 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206048 kb
Host smart-81d29f29-2c63-4fe8-b6cb-af381498880a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81367
895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.81367895
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3077779364
Short name T2679
Test name
Test status
Simulation time 233757674 ps
CPU time 0.87 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:49:58 PM PDT 24
Peak memory 206660 kb
Host smart-278f02b3-ce84-4a42-89ea-574f59133397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30777
79364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3077779364
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.1776915191
Short name T2338
Test name
Test status
Simulation time 220498793 ps
CPU time 0.84 seconds
Started Jul 18 05:49:59 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206632 kb
Host smart-d8d4f091-e511-425a-b4af-8bd4d7394b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17769
15191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.1776915191
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.182895852
Short name T2514
Test name
Test status
Simulation time 202561189 ps
CPU time 0.91 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206080 kb
Host smart-aa58eb32-9a21-4dba-8601-fdd6583a8da8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18289
5852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.182895852
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.3320943234
Short name T1793
Test name
Test status
Simulation time 151000850 ps
CPU time 0.83 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:05 PM PDT 24
Peak memory 206604 kb
Host smart-6d10a7f4-4b7f-423d-af66-7371659ee435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33209
43234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.3320943234
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.4022787921
Short name T2641
Test name
Test status
Simulation time 165666606 ps
CPU time 0.86 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:05 PM PDT 24
Peak memory 206652 kb
Host smart-168a1830-d177-4d3c-9efc-2a393e86ad02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40227
87921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.4022787921
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.27494018
Short name T957
Test name
Test status
Simulation time 149030053 ps
CPU time 0.79 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206644 kb
Host smart-ecfc709f-9983-48f0-9d5c-2b27c4ffb638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27494
018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.27494018
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.390679871
Short name T488
Test name
Test status
Simulation time 311410478 ps
CPU time 1.07 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:02 PM PDT 24
Peak memory 206648 kb
Host smart-f29e4a47-f0ae-4063-a72b-31527bc36f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
9871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.390679871
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.3588299589
Short name T1646
Test name
Test status
Simulation time 4205606472 ps
CPU time 114.33 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206860 kb
Host smart-79775471-f779-4619-9bb1-8b5fc899f7b8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3588299589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.3588299589
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3314575492
Short name T1548
Test name
Test status
Simulation time 181037049 ps
CPU time 0.81 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:01 PM PDT 24
Peak memory 206648 kb
Host smart-83f61fc5-e641-4f42-a208-8daea97ca1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33145
75492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3314575492
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2910100804
Short name T1878
Test name
Test status
Simulation time 171365512 ps
CPU time 0.86 seconds
Started Jul 18 05:50:02 PM PDT 24
Finished Jul 18 05:50:12 PM PDT 24
Peak memory 206576 kb
Host smart-8dd5aad7-9be5-44b6-b4a0-462745a588a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29101
00804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2910100804
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.682262194
Short name T1794
Test name
Test status
Simulation time 848483110 ps
CPU time 1.99 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:07 PM PDT 24
Peak memory 206792 kb
Host smart-060adf8d-f057-4d3b-9b59-39a2da40c344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68226
2194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.682262194
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.38291347
Short name T2130
Test name
Test status
Simulation time 3927570461 ps
CPU time 36.81 seconds
Started Jul 18 05:50:03 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206888 kb
Host smart-f42bfd55-0f58-4aa1-8cb8-4b57142aee7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38291
347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.38291347
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.3078143935
Short name T1197
Test name
Test status
Simulation time 30580421 ps
CPU time 0.66 seconds
Started Jul 18 05:50:09 PM PDT 24
Finished Jul 18 05:50:15 PM PDT 24
Peak memory 206652 kb
Host smart-c2cb694d-db14-4f85-b594-1fc3876ed4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3078143935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.3078143935
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1207525613
Short name T1092
Test name
Test status
Simulation time 3697725590 ps
CPU time 4.22 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:13 PM PDT 24
Peak memory 206860 kb
Host smart-8dd30d68-9e40-4547-85f8-000e112a24a2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1207525613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1207525613
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2693602543
Short name T14
Test name
Test status
Simulation time 13431160740 ps
CPU time 12.4 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:14 PM PDT 24
Peak memory 206780 kb
Host smart-f2126063-d576-42a4-a7cb-1a26cb7b668d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2693602543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2693602543
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.3505040045
Short name T946
Test name
Test status
Simulation time 23399402614 ps
CPU time 21.89 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206920 kb
Host smart-a2458184-4d7e-46ec-ac60-06e5062e6f1b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3505040045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.3505040045
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.2330378484
Short name T325
Test name
Test status
Simulation time 168466327 ps
CPU time 0.83 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:49:59 PM PDT 24
Peak memory 206660 kb
Host smart-ef223871-954e-4d23-ba2c-4a8d4bd2211a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
78484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.2330378484
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.4076325618
Short name T1239
Test name
Test status
Simulation time 154227911 ps
CPU time 0.78 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206660 kb
Host smart-3f253501-6015-4a83-8340-1156c58680d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40763
25618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.4076325618
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.3447286298
Short name T111
Test name
Test status
Simulation time 268479005 ps
CPU time 1.11 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206536 kb
Host smart-4cefa735-464f-4c95-a613-1fdb2feccf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34472
86298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.3447286298
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2844538642
Short name T2002
Test name
Test status
Simulation time 1431452793 ps
CPU time 3.46 seconds
Started Jul 18 05:50:02 PM PDT 24
Finished Jul 18 05:50:14 PM PDT 24
Peak memory 206684 kb
Host smart-691f149d-f484-4fa4-a5aa-8809b240f3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28445
38642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2844538642
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.2898220883
Short name T1510
Test name
Test status
Simulation time 12963484485 ps
CPU time 21.85 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:29 PM PDT 24
Peak memory 206848 kb
Host smart-6a4debc3-6784-4249-9af5-e69d8e4562c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28982
20883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.2898220883
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.239726104
Short name T19
Test name
Test status
Simulation time 393707445 ps
CPU time 1.31 seconds
Started Jul 18 05:49:59 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206612 kb
Host smart-a7f6ef54-914a-411f-a309-dbe1cf8692c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23972
6104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.239726104
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.2045065600
Short name T1391
Test name
Test status
Simulation time 147568268 ps
CPU time 0.77 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206656 kb
Host smart-7a6efb13-bea8-44da-9384-d8c51f563124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20450
65600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.2045065600
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2964249795
Short name T646
Test name
Test status
Simulation time 34468189 ps
CPU time 0.69 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206624 kb
Host smart-e9d09c31-139d-42a3-b365-d16ac3d6cb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29642
49795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2964249795
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2350907664
Short name T303
Test name
Test status
Simulation time 1005216717 ps
CPU time 2.36 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206740 kb
Host smart-1990a8fe-16bf-472d-9d69-42a80a85f892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23509
07664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2350907664
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.2538640455
Short name T670
Test name
Test status
Simulation time 283323342 ps
CPU time 2.01 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206764 kb
Host smart-283b246c-739e-4710-950a-3eea5d8ed98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25386
40455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.2538640455
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.2490577771
Short name T533
Test name
Test status
Simulation time 164929294 ps
CPU time 0.8 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206620 kb
Host smart-03c3022b-b5a7-4b6f-9ceb-783bedf59790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24905
77771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.2490577771
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.4221032497
Short name T2180
Test name
Test status
Simulation time 166672179 ps
CPU time 0.8 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206268 kb
Host smart-9f130d17-34c5-48ce-b3cd-ae4d1d2b7c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42210
32497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.4221032497
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.3134175552
Short name T2004
Test name
Test status
Simulation time 244011745 ps
CPU time 0.95 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206808 kb
Host smart-a2ebed2b-3941-4fc8-a2e6-0b845b032561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31341
75552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.3134175552
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.4259657283
Short name T1947
Test name
Test status
Simulation time 9341297394 ps
CPU time 68.18 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:51:17 PM PDT 24
Peak memory 206556 kb
Host smart-b2f75a8d-fc10-4ef0-aa43-9f4e47d22967
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4259657283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.4259657283
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.3246590951
Short name T2661
Test name
Test status
Simulation time 210011090 ps
CPU time 0.9 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206808 kb
Host smart-715541ff-f5d1-4f72-8059-e7b3aa51c6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32465
90951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.3246590951
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.1470290676
Short name T1586
Test name
Test status
Simulation time 23330170935 ps
CPU time 22.97 seconds
Started Jul 18 05:50:02 PM PDT 24
Finished Jul 18 05:50:34 PM PDT 24
Peak memory 206760 kb
Host smart-076d9654-2580-40b0-b21e-96962d4d3ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14702
90676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.1470290676
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3080844277
Short name T1120
Test name
Test status
Simulation time 3306082467 ps
CPU time 3.83 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206720 kb
Host smart-9755b8b7-c95e-4f80-9e9e-198748a97179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30808
44277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3080844277
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.1274209544
Short name T2500
Test name
Test status
Simulation time 7869347039 ps
CPU time 226.31 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:53:51 PM PDT 24
Peak memory 206880 kb
Host smart-055f9d2c-8170-48bb-8cd4-ffbf17ad5f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12742
09544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.1274209544
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.305962517
Short name T1546
Test name
Test status
Simulation time 5497307548 ps
CPU time 153.19 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:52:36 PM PDT 24
Peak memory 206836 kb
Host smart-1ea17037-9566-42d0-babf-8a111de4c971
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=305962517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.305962517
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1706220459
Short name T1207
Test name
Test status
Simulation time 256581097 ps
CPU time 0.98 seconds
Started Jul 18 05:50:03 PM PDT 24
Finished Jul 18 05:50:12 PM PDT 24
Peak memory 206616 kb
Host smart-57889263-120f-4354-9ac4-8e69de6b87dd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1706220459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1706220459
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1537591082
Short name T955
Test name
Test status
Simulation time 200181785 ps
CPU time 0.88 seconds
Started Jul 18 05:50:03 PM PDT 24
Finished Jul 18 05:50:12 PM PDT 24
Peak memory 206612 kb
Host smart-531d77ff-0bc4-41b3-bc47-779041dd2964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15375
91082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1537591082
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.2616630595
Short name T2648
Test name
Test status
Simulation time 4005997141 ps
CPU time 112.45 seconds
Started Jul 18 05:49:55 PM PDT 24
Finished Jul 18 05:51:50 PM PDT 24
Peak memory 206860 kb
Host smart-21547049-aea0-4d65-aabf-b555ef0f9630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26166
30595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.2616630595
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.1266737624
Short name T1076
Test name
Test status
Simulation time 5428941503 ps
CPU time 148.1 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:52:27 PM PDT 24
Peak memory 206804 kb
Host smart-5a5da5e7-d1d4-4917-8bd5-2a97f5817f24
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1266737624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.1266737624
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.888225508
Short name T2703
Test name
Test status
Simulation time 158529122 ps
CPU time 0.78 seconds
Started Jul 18 05:49:57 PM PDT 24
Finished Jul 18 05:50:04 PM PDT 24
Peak memory 206612 kb
Host smart-ce36dfd1-4730-49b6-9ad8-dc058a4328bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=888225508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.888225508
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.3376450746
Short name T290
Test name
Test status
Simulation time 197410339 ps
CPU time 0.84 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206664 kb
Host smart-78ed538a-9c2d-4ea7-950e-b985276d9465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33764
50746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.3376450746
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.1479256219
Short name T2045
Test name
Test status
Simulation time 255388841 ps
CPU time 0.89 seconds
Started Jul 18 05:49:56 PM PDT 24
Finished Jul 18 05:50:00 PM PDT 24
Peak memory 206616 kb
Host smart-037a282a-8724-4fa3-b996-661fdbf559b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14792
56219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.1479256219
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.873181941
Short name T1716
Test name
Test status
Simulation time 193631180 ps
CPU time 0.93 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:06 PM PDT 24
Peak memory 206556 kb
Host smart-a3e3be52-aa05-403b-b7fb-4effcb0b6629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87318
1941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.873181941
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2854592064
Short name T2371
Test name
Test status
Simulation time 223564467 ps
CPU time 0.83 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:06 PM PDT 24
Peak memory 206636 kb
Host smart-c791a7b4-3780-4799-a074-534ae3669f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28545
92064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2854592064
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1124008174
Short name T2749
Test name
Test status
Simulation time 225050927 ps
CPU time 0.9 seconds
Started Jul 18 05:49:58 PM PDT 24
Finished Jul 18 05:50:06 PM PDT 24
Peak memory 206556 kb
Host smart-0cd0b3aa-4c3e-496a-b20b-901bfd73585e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11240
08174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1124008174
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.3393694395
Short name T919
Test name
Test status
Simulation time 228132041 ps
CPU time 0.81 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206616 kb
Host smart-58bcd022-ed3c-4b7c-bfed-95a8277aa7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33936
94395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.3393694395
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.480053697
Short name T1585
Test name
Test status
Simulation time 207480986 ps
CPU time 0.87 seconds
Started Jul 18 05:49:59 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206616 kb
Host smart-74f5d54e-86a6-496e-84ea-8caa0a3d918f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=480053697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.480053697
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.954800222
Short name T1489
Test name
Test status
Simulation time 158432101 ps
CPU time 0.77 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206652 kb
Host smart-fd3a35d8-f71e-433f-b0ce-d16672885811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95480
0222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.954800222
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.3120633501
Short name T787
Test name
Test status
Simulation time 33413413 ps
CPU time 0.66 seconds
Started Jul 18 05:50:03 PM PDT 24
Finished Jul 18 05:50:12 PM PDT 24
Peak memory 206648 kb
Host smart-e43f18c4-a5e8-4aa4-a4cf-c1e2d3442b7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31206
33501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.3120633501
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.1398809084
Short name T1429
Test name
Test status
Simulation time 13239426421 ps
CPU time 28.8 seconds
Started Jul 18 05:50:02 PM PDT 24
Finished Jul 18 05:50:39 PM PDT 24
Peak memory 206880 kb
Host smart-7fe80593-7c9c-4d27-89b4-e0b471d04da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13988
09084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.1398809084
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.661180821
Short name T726
Test name
Test status
Simulation time 204379771 ps
CPU time 0.86 seconds
Started Jul 18 05:50:05 PM PDT 24
Finished Jul 18 05:50:14 PM PDT 24
Peak memory 206652 kb
Host smart-2ddad218-ea68-48ae-a512-27d2fa009baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66118
0821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.661180821
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.3672100588
Short name T2078
Test name
Test status
Simulation time 234454860 ps
CPU time 0.94 seconds
Started Jul 18 05:50:04 PM PDT 24
Finished Jul 18 05:50:13 PM PDT 24
Peak memory 206648 kb
Host smart-569c08cb-b891-4f17-8840-1fea68613399
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36721
00588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.3672100588
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2107574870
Short name T1664
Test name
Test status
Simulation time 211144166 ps
CPU time 0.9 seconds
Started Jul 18 05:50:01 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206596 kb
Host smart-9f005275-ad10-4ab7-8792-9773ac627e5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
74870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2107574870
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.3027282286
Short name T2104
Test name
Test status
Simulation time 170807320 ps
CPU time 0.88 seconds
Started Jul 18 05:50:04 PM PDT 24
Finished Jul 18 05:50:13 PM PDT 24
Peak memory 206648 kb
Host smart-2b7fe63d-de67-4c1d-a292-8b1bb058e08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30272
82286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.3027282286
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2425329494
Short name T2453
Test name
Test status
Simulation time 177632922 ps
CPU time 0.86 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206544 kb
Host smart-915c8a78-0124-4066-aaed-87dd82565620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24253
29494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2425329494
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.3953465692
Short name T843
Test name
Test status
Simulation time 173706893 ps
CPU time 0.87 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206648 kb
Host smart-f4cbf4e6-1997-4b35-8d53-48b2de1361ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39534
65692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.3953465692
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.4093843987
Short name T2105
Test name
Test status
Simulation time 168150873 ps
CPU time 0.78 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206636 kb
Host smart-46d1dc9f-faaf-4b61-a493-b98547b2535b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40938
43987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.4093843987
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.522898203
Short name T2498
Test name
Test status
Simulation time 207204667 ps
CPU time 0.9 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:08 PM PDT 24
Peak memory 206628 kb
Host smart-47b89c2b-633c-4627-a515-b8d16c0cabf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52289
8203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.522898203
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2698643031
Short name T1444
Test name
Test status
Simulation time 3571294176 ps
CPU time 100.75 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:51:49 PM PDT 24
Peak memory 206596 kb
Host smart-5cd1b694-0d4e-41bb-94aa-82ede3c68133
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2698643031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2698643031
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.2323599275
Short name T499
Test name
Test status
Simulation time 173223585 ps
CPU time 0.82 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206340 kb
Host smart-bf8afd1a-d8f1-479a-a8aa-71590839a653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23235
99275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.2323599275
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1409057904
Short name T2
Test name
Test status
Simulation time 148721715 ps
CPU time 0.79 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:09 PM PDT 24
Peak memory 206616 kb
Host smart-f467a43d-2540-408f-87b4-b2374d624b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14090
57904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1409057904
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.1938345300
Short name T699
Test name
Test status
Simulation time 587450111 ps
CPU time 1.7 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:50:10 PM PDT 24
Peak memory 206620 kb
Host smart-1be22ca0-ec0a-4c67-94ff-8ac214b485c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19383
45300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.1938345300
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.2582682745
Short name T161
Test name
Test status
Simulation time 4777963271 ps
CPU time 133.68 seconds
Started Jul 18 05:50:00 PM PDT 24
Finished Jul 18 05:52:21 PM PDT 24
Peak memory 206844 kb
Host smart-0715796a-5ffe-4ceb-ad88-198dad052a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25826
82745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.2582682745
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.2675095764
Short name T1468
Test name
Test status
Simulation time 34397730 ps
CPU time 0.66 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:50:29 PM PDT 24
Peak memory 206700 kb
Host smart-754dd25a-466a-41d1-b068-1d97fbdb5523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2675095764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.2675095764
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1288751619
Short name T1557
Test name
Test status
Simulation time 3820139988 ps
CPU time 4.5 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206752 kb
Host smart-b366527a-69c6-470f-b99a-2be0753b80b7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1288751619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1288751619
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.3047704093
Short name T211
Test name
Test status
Simulation time 13362854562 ps
CPU time 12.7 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:38 PM PDT 24
Peak memory 206764 kb
Host smart-9ad43f48-87a2-4ae5-b76f-62151aeab941
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3047704093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.3047704093
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.883366033
Short name T2583
Test name
Test status
Simulation time 23412778655 ps
CPU time 26.81 seconds
Started Jul 18 05:50:10 PM PDT 24
Finished Jul 18 05:50:43 PM PDT 24
Peak memory 206780 kb
Host smart-e25568a4-f690-478b-a64d-954a779cd5cc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=883366033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.883366033
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.164051952
Short name T2563
Test name
Test status
Simulation time 152176228 ps
CPU time 0.8 seconds
Started Jul 18 05:50:09 PM PDT 24
Finished Jul 18 05:50:17 PM PDT 24
Peak memory 206660 kb
Host smart-ffb49960-c181-448a-b33a-dea25e1f8052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16405
1952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.164051952
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.1056899680
Short name T1431
Test name
Test status
Simulation time 141083253 ps
CPU time 0.78 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:27 PM PDT 24
Peak memory 206672 kb
Host smart-8bb466ae-01a2-400b-ab02-289563d65f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10568
99680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.1056899680
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2979028397
Short name T2380
Test name
Test status
Simulation time 311545990 ps
CPU time 1.2 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206532 kb
Host smart-d29ba04d-82ae-40fb-96e2-fd8e92c893d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29790
28397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2979028397
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.118212063
Short name T1569
Test name
Test status
Simulation time 726384723 ps
CPU time 1.85 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206668 kb
Host smart-7464a63b-df7e-4428-a1ca-6b98ce18748c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11821
2063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.118212063
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1179851322
Short name T1343
Test name
Test status
Simulation time 11140406926 ps
CPU time 22.26 seconds
Started Jul 18 05:50:10 PM PDT 24
Finished Jul 18 05:50:38 PM PDT 24
Peak memory 206864 kb
Host smart-e3f07878-0bf0-4809-820c-815b92854b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11798
51322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1179851322
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.873624922
Short name T668
Test name
Test status
Simulation time 357039773 ps
CPU time 1.19 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206668 kb
Host smart-d8b31ad1-78ed-4096-8731-d3138ff8e40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87362
4922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.873624922
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.1313642516
Short name T42
Test name
Test status
Simulation time 135728440 ps
CPU time 0.74 seconds
Started Jul 18 05:50:10 PM PDT 24
Finished Jul 18 05:50:17 PM PDT 24
Peak memory 206640 kb
Host smart-43d7e741-6134-40ef-93c4-16be158e9396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13136
42516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.1313642516
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.3743562113
Short name T446
Test name
Test status
Simulation time 43597603 ps
CPU time 0.7 seconds
Started Jul 18 05:50:09 PM PDT 24
Finished Jul 18 05:50:16 PM PDT 24
Peak memory 206608 kb
Host smart-00a09b9b-1373-4645-be85-c69c14f55a4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37435
62113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.3743562113
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3752032794
Short name T2651
Test name
Test status
Simulation time 825543064 ps
CPU time 2.06 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:24 PM PDT 24
Peak memory 206752 kb
Host smart-431a6310-4856-4716-aa5b-c635baf2f1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37520
32794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3752032794
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2656528310
Short name T1687
Test name
Test status
Simulation time 358594662 ps
CPU time 2.1 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206784 kb
Host smart-b23b38d4-a826-418c-be9a-39997eb46587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26565
28310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2656528310
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.1061377779
Short name T1311
Test name
Test status
Simulation time 238182653 ps
CPU time 0.91 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206644 kb
Host smart-a5764094-d61d-45c9-b719-ca2661ce0459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10613
77779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1061377779
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3430988079
Short name T1118
Test name
Test status
Simulation time 150485097 ps
CPU time 0.79 seconds
Started Jul 18 05:50:13 PM PDT 24
Finished Jul 18 05:50:20 PM PDT 24
Peak memory 206652 kb
Host smart-4404ef6c-079d-4e66-8f6c-0f48be75857a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
88079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3430988079
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.763147110
Short name T1789
Test name
Test status
Simulation time 226262399 ps
CPU time 0.92 seconds
Started Jul 18 05:50:11 PM PDT 24
Finished Jul 18 05:50:18 PM PDT 24
Peak memory 206580 kb
Host smart-1f165dc8-fa96-42ae-9710-4f831bedcac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76314
7110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.763147110
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.1179666272
Short name T1246
Test name
Test status
Simulation time 9407917589 ps
CPU time 83.03 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:51:41 PM PDT 24
Peak memory 206908 kb
Host smart-e94a9dfc-70b8-4818-bf90-0eb7493689f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11796
66272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.1179666272
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.4161265177
Short name T656
Test name
Test status
Simulation time 192730414 ps
CPU time 0.86 seconds
Started Jul 18 05:50:09 PM PDT 24
Finished Jul 18 05:50:17 PM PDT 24
Peak memory 206648 kb
Host smart-7375b0b3-c1c9-4a67-9882-6415977823ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41612
65177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.4161265177
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.3033266901
Short name T1784
Test name
Test status
Simulation time 23360847781 ps
CPU time 23.83 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:49 PM PDT 24
Peak memory 206772 kb
Host smart-1f914bcb-ad38-4bea-ba19-ed6bb642b346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30332
66901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.3033266901
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.2348355059
Short name T1750
Test name
Test status
Simulation time 3286584662 ps
CPU time 3.84 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:30 PM PDT 24
Peak memory 206724 kb
Host smart-e0e09a38-3e92-4eaa-a3ea-4a3e0716d3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23483
55059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.2348355059
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.1369132304
Short name T2658
Test name
Test status
Simulation time 12315123630 ps
CPU time 117.87 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:52:19 PM PDT 24
Peak memory 206912 kb
Host smart-8ea14f43-92b1-4b1f-a1c8-019ec3d581a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13691
32304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.1369132304
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.4003557898
Short name T2697
Test name
Test status
Simulation time 6319069339 ps
CPU time 60.12 seconds
Started Jul 18 05:50:10 PM PDT 24
Finished Jul 18 05:51:16 PM PDT 24
Peak memory 206836 kb
Host smart-63fc9cca-c567-4594-8f07-720cb2422fc3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4003557898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.4003557898
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.3243927809
Short name T2591
Test name
Test status
Simulation time 237553420 ps
CPU time 0.9 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206624 kb
Host smart-f3a22463-0f6d-4c41-a156-f8cf9f6a8b89
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3243927809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.3243927809
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.1669160743
Short name T1529
Test name
Test status
Simulation time 208625096 ps
CPU time 0.87 seconds
Started Jul 18 05:50:18 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206632 kb
Host smart-7d1b37b4-1900-438d-b1c0-1b579993656b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16691
60743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.1669160743
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.3051689709
Short name T1325
Test name
Test status
Simulation time 4234043254 ps
CPU time 29.9 seconds
Started Jul 18 05:50:11 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206916 kb
Host smart-b7da6670-d3f3-4552-818b-540b3b19681a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30516
89709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.3051689709
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.3868650205
Short name T553
Test name
Test status
Simulation time 6068213744 ps
CPU time 57.63 seconds
Started Jul 18 05:50:20 PM PDT 24
Finished Jul 18 05:51:28 PM PDT 24
Peak memory 206832 kb
Host smart-cabc1cf7-6843-4a5c-a642-512443248e65
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3868650205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.3868650205
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1483305586
Short name T1192
Test name
Test status
Simulation time 156741907 ps
CPU time 0.79 seconds
Started Jul 18 05:50:11 PM PDT 24
Finished Jul 18 05:50:18 PM PDT 24
Peak memory 206620 kb
Host smart-6917ea38-e243-463f-87ce-e24d2600e332
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1483305586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1483305586
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3042982138
Short name T428
Test name
Test status
Simulation time 173052988 ps
CPU time 0.84 seconds
Started Jul 18 05:50:13 PM PDT 24
Finished Jul 18 05:50:21 PM PDT 24
Peak memory 206648 kb
Host smart-03634c32-dd27-432a-b0f6-9aab24a10ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30429
82138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3042982138
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.707346570
Short name T2460
Test name
Test status
Simulation time 183157773 ps
CPU time 0.97 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206648 kb
Host smart-e3e570e1-c4fc-471c-b65c-665c704de677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70734
6570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.707346570
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1906164894
Short name T626
Test name
Test status
Simulation time 199620079 ps
CPU time 0.88 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:24 PM PDT 24
Peak memory 206620 kb
Host smart-76ced5f3-5952-4029-bd5f-8a957ca5f776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19061
64894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1906164894
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3866524626
Short name T1233
Test name
Test status
Simulation time 171656018 ps
CPU time 0.88 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:25 PM PDT 24
Peak memory 206660 kb
Host smart-788130d2-cc5d-48f2-b998-08c2d20c1906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38665
24626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3866524626
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2218284592
Short name T1302
Test name
Test status
Simulation time 240049884 ps
CPU time 0.94 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206500 kb
Host smart-1775618b-dff2-492a-8674-d041ef76865d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22182
84592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2218284592
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.231584270
Short name T506
Test name
Test status
Simulation time 151246136 ps
CPU time 0.75 seconds
Started Jul 18 05:51:17 PM PDT 24
Finished Jul 18 05:51:29 PM PDT 24
Peak memory 206648 kb
Host smart-b4a9eddf-4dc1-4504-b2e9-3d1725265ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23158
4270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.231584270
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.4287652491
Short name T2626
Test name
Test status
Simulation time 208830798 ps
CPU time 0.87 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206636 kb
Host smart-f432fe33-9e4a-4180-872a-5fb89b649e98
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4287652491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.4287652491
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1391462659
Short name T1635
Test name
Test status
Simulation time 213810061 ps
CPU time 0.88 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:22 PM PDT 24
Peak memory 206656 kb
Host smart-307980aa-52cf-47a4-b3f0-1f1915875350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13914
62659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1391462659
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2639263484
Short name T1890
Test name
Test status
Simulation time 43778370 ps
CPU time 0.65 seconds
Started Jul 18 05:50:13 PM PDT 24
Finished Jul 18 05:50:21 PM PDT 24
Peak memory 206636 kb
Host smart-7a72c0e7-533a-45ed-8d72-ebc6fa28bc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26392
63484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2639263484
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.2484039088
Short name T1201
Test name
Test status
Simulation time 17666621127 ps
CPU time 37.94 seconds
Started Jul 18 05:50:11 PM PDT 24
Finished Jul 18 05:50:55 PM PDT 24
Peak memory 206860 kb
Host smart-ecb20ac1-acc8-40e1-b6d3-f1ac1da4f2c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24840
39088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.2484039088
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.2217503768
Short name T532
Test name
Test status
Simulation time 163771617 ps
CPU time 0.84 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206656 kb
Host smart-36df1c78-6aec-46b8-a327-78db0a5c461b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
03768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.2217503768
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.6412483
Short name T326
Test name
Test status
Simulation time 194233208 ps
CPU time 0.88 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206648 kb
Host smart-222f7d1b-202c-4ccc-9483-a4fc32979d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64124
83 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.6412483
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.1152344497
Short name T318
Test name
Test status
Simulation time 234019000 ps
CPU time 0.92 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206648 kb
Host smart-692b3c76-3dd8-4ec4-b352-506e5ffa1723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11523
44497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.1152344497
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3799005673
Short name T1394
Test name
Test status
Simulation time 177977352 ps
CPU time 0.83 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:44 PM PDT 24
Peak memory 206648 kb
Host smart-19f4274a-86db-4117-a27c-63d897f11ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37990
05673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3799005673
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.1513891050
Short name T69
Test name
Test status
Simulation time 175951748 ps
CPU time 0.8 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206612 kb
Host smart-abc5f10f-1641-4ad1-8357-666fc64d3b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15138
91050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.1513891050
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.912726866
Short name T1712
Test name
Test status
Simulation time 152225867 ps
CPU time 0.8 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206648 kb
Host smart-faaca01f-2f38-4ccb-84e4-46e3e66b6584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91272
6866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.912726866
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1966609934
Short name T1105
Test name
Test status
Simulation time 154034838 ps
CPU time 0.77 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206652 kb
Host smart-f212f94d-9afd-4ca1-88b8-922e15295197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19666
09934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1966609934
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.85712480
Short name T49
Test name
Test status
Simulation time 216383829 ps
CPU time 1 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206644 kb
Host smart-f1e783a3-138d-45cc-94d9-28aef205f284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85712
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.85712480
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.3460486397
Short name T2376
Test name
Test status
Simulation time 4562770213 ps
CPU time 32.16 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:57 PM PDT 24
Peak memory 206916 kb
Host smart-6db002bf-4f9a-4550-9c71-c90dcae5741b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3460486397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.3460486397
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3358941023
Short name T949
Test name
Test status
Simulation time 170366258 ps
CPU time 0.79 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206632 kb
Host smart-3eac6b28-871a-460f-9f76-cb41c1170f7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589
41023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3358941023
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.1754444285
Short name T1847
Test name
Test status
Simulation time 168895956 ps
CPU time 0.77 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206648 kb
Host smart-29b75e9a-bc9d-4cb0-8367-2ce1163daa3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
44285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.1754444285
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.1444689828
Short name T385
Test name
Test status
Simulation time 621639613 ps
CPU time 1.66 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:20 PM PDT 24
Peak memory 206640 kb
Host smart-b636d3f9-0878-4d33-8496-dbde2e8bf4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14446
89828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.1444689828
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.1324865030
Short name T1492
Test name
Test status
Simulation time 5037873000 ps
CPU time 37.39 seconds
Started Jul 18 05:50:25 PM PDT 24
Finished Jul 18 05:51:14 PM PDT 24
Peak memory 206916 kb
Host smart-0aba755b-ef2a-468d-ae2a-c8f915a59653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13248
65030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.1324865030
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1421619571
Short name T886
Test name
Test status
Simulation time 49813066 ps
CPU time 0.69 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206696 kb
Host smart-3f7a2a7b-cefd-45b4-b6ca-6867ea0d1200
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1421619571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1421619571
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1157189653
Short name T2207
Test name
Test status
Simulation time 4363891983 ps
CPU time 4.94 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:29 PM PDT 24
Peak memory 206692 kb
Host smart-379c1652-569d-409f-bb51-4578ca00e346
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1157189653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1157189653
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2521026820
Short name T1692
Test name
Test status
Simulation time 13377680086 ps
CPU time 12.14 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:56 PM PDT 24
Peak memory 206812 kb
Host smart-ee626aa6-d64d-4761-aea5-c6ce38630d68
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2521026820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2521026820
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3867505875
Short name T1888
Test name
Test status
Simulation time 23321173505 ps
CPU time 23.97 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:51:02 PM PDT 24
Peak memory 206752 kb
Host smart-a2b1b656-a324-48cb-a3c5-217dd2496543
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3867505875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3867505875
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.3004081811
Short name T2264
Test name
Test status
Simulation time 163347174 ps
CPU time 0.8 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206672 kb
Host smart-ff37c34d-ed9d-44e9-8c20-f22524c64e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30040
81811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.3004081811
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.303242582
Short name T2387
Test name
Test status
Simulation time 144318602 ps
CPU time 0.75 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206660 kb
Host smart-ba35fdd6-0cba-4def-88a7-d34c390c5911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30324
2582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.303242582
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.1800040248
Short name T2117
Test name
Test status
Simulation time 603327609 ps
CPU time 1.65 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:29 PM PDT 24
Peak memory 206724 kb
Host smart-24f5eb48-d5b7-4690-9373-981ba550c4f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18000
40248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.1800040248
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.249101292
Short name T1296
Test name
Test status
Simulation time 482930422 ps
CPU time 1.44 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206612 kb
Host smart-4a1ebccc-7df3-4825-8f09-a065aaab93c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
1292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.249101292
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.1546729403
Short name T1637
Test name
Test status
Simulation time 6867228961 ps
CPU time 13.45 seconds
Started Jul 18 05:50:24 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206868 kb
Host smart-e49085d2-dca6-43dd-9b1e-c1185a1672c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467
29403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.1546729403
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1428907588
Short name T2594
Test name
Test status
Simulation time 472739389 ps
CPU time 1.47 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206652 kb
Host smart-617da9ae-fbde-47b2-a562-8dfb9479a1e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14289
07588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1428907588
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.722684912
Short name T2517
Test name
Test status
Simulation time 141432860 ps
CPU time 0.73 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206656 kb
Host smart-aad640be-c135-48f9-ab8b-e1dcd4f23a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72268
4912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.722684912
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3945475993
Short name T1834
Test name
Test status
Simulation time 41531520 ps
CPU time 0.69 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206664 kb
Host smart-f20a7c1f-6912-4ded-a1b6-0713b98458c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39454
75993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3945475993
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1847829161
Short name T2681
Test name
Test status
Simulation time 744331924 ps
CPU time 1.86 seconds
Started Jul 18 05:50:11 PM PDT 24
Finished Jul 18 05:50:18 PM PDT 24
Peak memory 206792 kb
Host smart-746492c9-b83c-4b57-a294-c9c304a41b4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
29161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1847829161
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3483448320
Short name T176
Test name
Test status
Simulation time 154220571 ps
CPU time 1.31 seconds
Started Jul 18 05:50:20 PM PDT 24
Finished Jul 18 05:50:31 PM PDT 24
Peak memory 206704 kb
Host smart-9e6d4470-3915-40d2-9eca-3bda3f3f95c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34834
48320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3483448320
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.1930164096
Short name T2447
Test name
Test status
Simulation time 169839339 ps
CPU time 0.82 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:50:39 PM PDT 24
Peak memory 206640 kb
Host smart-e74fffd7-7329-451e-b3d3-f5d638873919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19301
64096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.1930164096
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2006005580
Short name T2353
Test name
Test status
Simulation time 159468878 ps
CPU time 0.78 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206616 kb
Host smart-fb8e6cc4-308b-4214-8070-a0a40f18cdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20060
05580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2006005580
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3011446041
Short name T2607
Test name
Test status
Simulation time 222158494 ps
CPU time 0.9 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:50:44 PM PDT 24
Peak memory 206624 kb
Host smart-0a52cb64-cd5b-4ada-ab3a-44417f91927c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30114
46041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3011446041
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.3216303804
Short name T964
Test name
Test status
Simulation time 6826795444 ps
CPU time 196.76 seconds
Started Jul 18 05:50:23 PM PDT 24
Finished Jul 18 05:53:51 PM PDT 24
Peak memory 206816 kb
Host smart-994a0fdc-fc48-4cb8-8720-5f26a40dacd1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3216303804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3216303804
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.782236959
Short name T1866
Test name
Test status
Simulation time 221094399 ps
CPU time 0.87 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:50:57 PM PDT 24
Peak memory 206668 kb
Host smart-1e7c1669-37a1-46eb-9286-fb5b26e3f0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78223
6959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.782236959
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1630689530
Short name T2186
Test name
Test status
Simulation time 23349497043 ps
CPU time 26.78 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206792 kb
Host smart-ab77a0c7-80e0-45ad-a6ea-7c6811f682c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16306
89530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1630689530
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.2541947082
Short name T1498
Test name
Test status
Simulation time 3326799343 ps
CPU time 3.95 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206704 kb
Host smart-514621d1-d9be-4f47-a78f-8bfd6b24c180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25419
47082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.2541947082
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.4164632647
Short name T1441
Test name
Test status
Simulation time 7951730551 ps
CPU time 76.52 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206896 kb
Host smart-1d8bdada-7523-4754-86d3-cc93d7cc7a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41646
32647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.4164632647
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2958274294
Short name T2094
Test name
Test status
Simulation time 4785366444 ps
CPU time 36.5 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:51:32 PM PDT 24
Peak memory 206864 kb
Host smart-8da46561-1a1f-4734-9327-8ca579c3f992
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2958274294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2958274294
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.1430090147
Short name T2737
Test name
Test status
Simulation time 237737599 ps
CPU time 0.91 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:50:54 PM PDT 24
Peak memory 206668 kb
Host smart-b4c0057c-994a-46d7-afa2-9468c1783299
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1430090147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.1430090147
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2988104696
Short name T2707
Test name
Test status
Simulation time 183237468 ps
CPU time 0.86 seconds
Started Jul 18 05:50:21 PM PDT 24
Finished Jul 18 05:50:32 PM PDT 24
Peak memory 206640 kb
Host smart-8176e63a-754b-438b-ad5e-c95d20354913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
04696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2988104696
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3334100213
Short name T580
Test name
Test status
Simulation time 4653752852 ps
CPU time 32.48 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206800 kb
Host smart-0c980012-7136-49f1-937f-f527991cec5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33341
00213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3334100213
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.1264785640
Short name T1671
Test name
Test status
Simulation time 4941780199 ps
CPU time 130.44 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:52:54 PM PDT 24
Peak memory 206844 kb
Host smart-d01b6162-ff73-4d46-817b-3c9ef6405bd7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1264785640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.1264785640
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.1774069686
Short name T1740
Test name
Test status
Simulation time 165632924 ps
CPU time 0.78 seconds
Started Jul 18 05:50:20 PM PDT 24
Finished Jul 18 05:50:31 PM PDT 24
Peak memory 206644 kb
Host smart-51b93af9-8df7-4b86-a9cf-9fd6b36b9c7c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1774069686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.1774069686
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.4066316394
Short name T933
Test name
Test status
Simulation time 158967600 ps
CPU time 0.78 seconds
Started Jul 18 05:50:13 PM PDT 24
Finished Jul 18 05:50:21 PM PDT 24
Peak memory 206624 kb
Host smart-bc7ce5b5-82e7-469a-a280-e9074720b371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40663
16394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.4066316394
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1339579620
Short name T134
Test name
Test status
Simulation time 233658488 ps
CPU time 0.84 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:51 PM PDT 24
Peak memory 206652 kb
Host smart-a4038d07-2234-4780-a282-cceb28648689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
79620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1339579620
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.1291028776
Short name T982
Test name
Test status
Simulation time 198887155 ps
CPU time 0.96 seconds
Started Jul 18 05:50:20 PM PDT 24
Finished Jul 18 05:50:32 PM PDT 24
Peak memory 206648 kb
Host smart-cd7e170c-e37a-4a1b-b7ad-7288e7358a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12910
28776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.1291028776
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2074683905
Short name T1862
Test name
Test status
Simulation time 175667738 ps
CPU time 0.88 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206656 kb
Host smart-9922691f-6acf-49c8-a8ec-7b7ea743e801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
83905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2074683905
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1060409036
Short name T1864
Test name
Test status
Simulation time 196049402 ps
CPU time 0.88 seconds
Started Jul 18 05:50:25 PM PDT 24
Finished Jul 18 05:50:37 PM PDT 24
Peak memory 206652 kb
Host smart-e2921d17-b355-4b8b-a18c-f2290b4767da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10604
09036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1060409036
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1411089146
Short name T1169
Test name
Test status
Simulation time 165861637 ps
CPU time 0.8 seconds
Started Jul 18 05:50:18 PM PDT 24
Finished Jul 18 05:50:29 PM PDT 24
Peak memory 206440 kb
Host smart-98095110-d0f0-4d5b-9058-e739d7596cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14110
89146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1411089146
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.3877524445
Short name T150
Test name
Test status
Simulation time 209598755 ps
CPU time 0.89 seconds
Started Jul 18 05:50:18 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206616 kb
Host smart-7d9928cd-9cac-4e07-8903-830cc157da98
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3877524445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.3877524445
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.2411772054
Short name T2709
Test name
Test status
Simulation time 137453994 ps
CPU time 0.76 seconds
Started Jul 18 05:50:13 PM PDT 24
Finished Jul 18 05:50:21 PM PDT 24
Peak memory 206652 kb
Host smart-8ead55af-cd0b-4cf0-8755-f6c4e1f9dd96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24117
72054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.2411772054
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.4169744205
Short name T2288
Test name
Test status
Simulation time 47604069 ps
CPU time 0.7 seconds
Started Jul 18 05:50:27 PM PDT 24
Finished Jul 18 05:50:41 PM PDT 24
Peak memory 206616 kb
Host smart-64ffb099-d4f1-444e-930f-16743a17be39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41697
44205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.4169744205
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.901231267
Short name T700
Test name
Test status
Simulation time 8233243256 ps
CPU time 17.89 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:40 PM PDT 24
Peak memory 206896 kb
Host smart-1c503243-da9e-485c-aaab-af042a1cb133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90123
1267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.901231267
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2411809792
Short name T1491
Test name
Test status
Simulation time 166159884 ps
CPU time 0.9 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:50:41 PM PDT 24
Peak memory 206620 kb
Host smart-b8781c31-87d3-4ea2-8a7f-c6af26e9b445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24118
09792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2411809792
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1579445185
Short name T610
Test name
Test status
Simulation time 230537302 ps
CPU time 0.91 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206652 kb
Host smart-feb92da0-b88a-4709-9bd0-93e9d0be9464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15794
45185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1579445185
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.1442574348
Short name T831
Test name
Test status
Simulation time 178629706 ps
CPU time 0.87 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:19 PM PDT 24
Peak memory 206616 kb
Host smart-f9ec8e47-2252-40d6-9058-476ca490dc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14425
74348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.1442574348
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2254110788
Short name T2489
Test name
Test status
Simulation time 193666098 ps
CPU time 0.83 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206652 kb
Host smart-780b2d18-3277-469a-8038-aff54b47b5c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22541
10788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2254110788
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.3862707634
Short name T103
Test name
Test status
Simulation time 211447236 ps
CPU time 0.86 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206636 kb
Host smart-26163a91-9232-41f2-a028-db566eedda42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38627
07634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.3862707634
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1705309958
Short name T413
Test name
Test status
Simulation time 158310667 ps
CPU time 0.75 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206644 kb
Host smart-a5f7f758-2355-4bbe-8683-65ca008fd076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17053
09958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1705309958
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1349064780
Short name T855
Test name
Test status
Simulation time 190468523 ps
CPU time 0.81 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206616 kb
Host smart-80be9921-5ab5-40cd-a58b-f96cd285a252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13490
64780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1349064780
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3207429287
Short name T2218
Test name
Test status
Simulation time 249584695 ps
CPU time 1.01 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206608 kb
Host smart-c0d9cbbf-ea6e-439d-9a80-4cebc59e6265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32074
29287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3207429287
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.376959432
Short name T1060
Test name
Test status
Simulation time 5083523987 ps
CPU time 48.09 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:51:14 PM PDT 24
Peak memory 206860 kb
Host smart-0de58970-d3b9-4f10-ab82-f7c393d950bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=376959432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.376959432
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.158471246
Short name T929
Test name
Test status
Simulation time 159297004 ps
CPU time 0.78 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206616 kb
Host smart-3460cd2d-e94b-4aed-a41a-29a4e1eaf752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15847
1246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.158471246
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1689731651
Short name T1384
Test name
Test status
Simulation time 183086025 ps
CPU time 0.86 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206656 kb
Host smart-232c9148-5ba1-46b6-a47f-345d2a8d493d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16897
31651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1689731651
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.4137926587
Short name T2734
Test name
Test status
Simulation time 1137087888 ps
CPU time 2.5 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206760 kb
Host smart-2f4221c4-069f-46ff-a854-1789d6e88bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41379
26587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.4137926587
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.2918908867
Short name T2208
Test name
Test status
Simulation time 6957703649 ps
CPU time 183.63 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:53:29 PM PDT 24
Peak memory 206888 kb
Host smart-0bd3e2e7-95d4-4935-84bb-c0130ee9ce1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
08867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.2918908867
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.3494098065
Short name T1181
Test name
Test status
Simulation time 37666032 ps
CPU time 0.68 seconds
Started Jul 18 05:44:38 PM PDT 24
Finished Jul 18 05:44:44 PM PDT 24
Peak memory 206684 kb
Host smart-ef37f487-1fa4-4ff8-8722-8439e0da8a88
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3494098065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.3494098065
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.716135208
Short name T734
Test name
Test status
Simulation time 4138848739 ps
CPU time 5.02 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:44:27 PM PDT 24
Peak memory 206684 kb
Host smart-3c85deba-968a-4b81-8735-47766e5683cd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=716135208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.716135208
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.2379375607
Short name T1098
Test name
Test status
Simulation time 13419621815 ps
CPU time 12.71 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:31 PM PDT 24
Peak memory 206780 kb
Host smart-918a3de1-6e06-43b6-80ab-bf15206cc90c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2379375607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.2379375607
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3003047018
Short name T1935
Test name
Test status
Simulation time 23359144966 ps
CPU time 23.73 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:44 PM PDT 24
Peak memory 206860 kb
Host smart-c4905172-cea7-498f-8b02-defae76cd932
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3003047018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3003047018
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1678453754
Short name T370
Test name
Test status
Simulation time 148768872 ps
CPU time 0.78 seconds
Started Jul 18 05:44:11 PM PDT 24
Finished Jul 18 05:44:17 PM PDT 24
Peak memory 206676 kb
Host smart-85b16e19-4a9c-4144-93c6-22cca97db8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16784
53754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1678453754
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.1013904017
Short name T53
Test name
Test status
Simulation time 156367164 ps
CPU time 0.86 seconds
Started Jul 18 05:44:09 PM PDT 24
Finished Jul 18 05:44:15 PM PDT 24
Peak memory 206652 kb
Host smart-6d922849-8b03-478e-b8fb-ca4a04988efe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10139
04017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.1013904017
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3443713753
Short name T62
Test name
Test status
Simulation time 144576427 ps
CPU time 0.79 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:22 PM PDT 24
Peak memory 206632 kb
Host smart-5e624468-8a7a-42ca-8756-91185077581f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34437
13753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3443713753
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.1821715878
Short name T431
Test name
Test status
Simulation time 147566941 ps
CPU time 0.8 seconds
Started Jul 18 05:44:09 PM PDT 24
Finished Jul 18 05:44:15 PM PDT 24
Peak memory 206616 kb
Host smart-b3990b29-07df-40b3-8adc-ecd21af7577e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18217
15878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.1821715878
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.3577939121
Short name T788
Test name
Test status
Simulation time 302369213 ps
CPU time 1.17 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:21 PM PDT 24
Peak memory 206668 kb
Host smart-dc31287b-e551-4ba3-b8cf-9e5ea8bcdfcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35779
39121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.3577939121
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1927342174
Short name T2466
Test name
Test status
Simulation time 18829919899 ps
CPU time 36.35 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:44:58 PM PDT 24
Peak memory 206872 kb
Host smart-cbddee2a-4f25-4982-960a-10d2f72a01e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19273
42174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1927342174
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1283802947
Short name T1516
Test name
Test status
Simulation time 488267822 ps
CPU time 1.49 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:20 PM PDT 24
Peak memory 206596 kb
Host smart-816db0f3-97bf-4de9-ae3c-27d72e071387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
02947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1283802947
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.4200977724
Short name T1518
Test name
Test status
Simulation time 142480263 ps
CPU time 0.74 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206616 kb
Host smart-d11d9ae4-4ff2-4c4d-ac07-45ae8ede60dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42009
77724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.4200977724
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3903539810
Short name T2398
Test name
Test status
Simulation time 35489122 ps
CPU time 0.67 seconds
Started Jul 18 05:44:10 PM PDT 24
Finished Jul 18 05:44:15 PM PDT 24
Peak memory 206644 kb
Host smart-2536ec89-32fd-4b7f-91d4-6efd58a0ca8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39035
39810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3903539810
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.2849502477
Short name T2269
Test name
Test status
Simulation time 980427302 ps
CPU time 2.27 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:22 PM PDT 24
Peak memory 206748 kb
Host smart-86b39516-9e05-457e-8253-a0d8b54f4762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28495
02477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.2849502477
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1524330660
Short name T2190
Test name
Test status
Simulation time 245130651 ps
CPU time 1.34 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:20 PM PDT 24
Peak memory 206716 kb
Host smart-8ee0c7a0-16fd-420b-a419-cdf2e9343335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15243
30660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1524330660
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.1848874310
Short name T1814
Test name
Test status
Simulation time 115183746798 ps
CPU time 171.29 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:47:08 PM PDT 24
Peak memory 206848 kb
Host smart-f3e078f6-af78-454c-b663-572ba438ac2b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1848874310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.1848874310
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.108338574
Short name T322
Test name
Test status
Simulation time 90171669808 ps
CPU time 119.24 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:46:20 PM PDT 24
Peak memory 206876 kb
Host smart-d06e7cf9-26b5-4b46-a30d-6f0afe9cd125
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108338574 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.108338574
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.2900374762
Short name T28
Test name
Test status
Simulation time 120097445745 ps
CPU time 148.27 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:46:48 PM PDT 24
Peak memory 206840 kb
Host smart-5e8339d9-f522-4506-aa48-d9f450857779
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2900374762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.2900374762
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.1245896115
Short name T1875
Test name
Test status
Simulation time 82111264178 ps
CPU time 111.43 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206868 kb
Host smart-b6096198-5d6f-4e92-8d61-af84e951b031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245896115 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.1245896115
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.3624997417
Short name T2559
Test name
Test status
Simulation time 114173869285 ps
CPU time 152.64 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:46:53 PM PDT 24
Peak memory 206928 kb
Host smart-dfaa6e33-3d3d-4aee-84fe-57c5306a8947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
97417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.3624997417
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.1713712104
Short name T1249
Test name
Test status
Simulation time 234633153 ps
CPU time 0.88 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:44:25 PM PDT 24
Peak memory 206628 kb
Host smart-4a26a8b9-fab2-49b9-b040-9ce1409cd18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17137
12104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.1713712104
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.1229256617
Short name T1857
Test name
Test status
Simulation time 159070225 ps
CPU time 0.85 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:20 PM PDT 24
Peak memory 206596 kb
Host smart-64a9beda-806e-48ea-b56a-b272f9702ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12292
56617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.1229256617
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2170323776
Short name T1400
Test name
Test status
Simulation time 223024881 ps
CPU time 0.91 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:19 PM PDT 24
Peak memory 206640 kb
Host smart-825d5623-de46-48ab-afc7-8c4796f05294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21703
23776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2170323776
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.3626107779
Short name T1028
Test name
Test status
Simulation time 7265163691 ps
CPU time 24.42 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:44:46 PM PDT 24
Peak memory 206872 kb
Host smart-9db7b9c3-b9de-433b-baaa-83b8ae058778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36261
07779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.3626107779
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2131267755
Short name T1273
Test name
Test status
Simulation time 192100846 ps
CPU time 0.89 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:20 PM PDT 24
Peak memory 206652 kb
Host smart-ca3d4ec6-fa47-4653-82ce-0465058bea5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312
67755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2131267755
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.3740146814
Short name T860
Test name
Test status
Simulation time 23380222620 ps
CPU time 25.52 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:42 PM PDT 24
Peak memory 206748 kb
Host smart-24ed8737-b56e-4cfd-9c18-6773021d6c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37401
46814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.3740146814
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.739720596
Short name T2384
Test name
Test status
Simulation time 3332084056 ps
CPU time 3.63 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:44:25 PM PDT 24
Peak memory 206684 kb
Host smart-b2d21275-1788-4462-b0b4-18cdf6237745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73972
0596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.739720596
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.3918704314
Short name T157
Test name
Test status
Simulation time 6300154105 ps
CPU time 56.36 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206880 kb
Host smart-bdde3fb0-50a7-4110-86df-e1f76aa823dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39187
04314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.3918704314
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.310515545
Short name T517
Test name
Test status
Simulation time 6996463214 ps
CPU time 193.14 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:47:30 PM PDT 24
Peak memory 206900 kb
Host smart-cc6da549-c47e-4b9d-b1f9-c05498625664
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=310515545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.310515545
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2729516169
Short name T369
Test name
Test status
Simulation time 235644709 ps
CPU time 0.95 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:20 PM PDT 24
Peak memory 206616 kb
Host smart-eda8e3ac-fe85-4446-8d4d-0c050efaa62d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2729516169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2729516169
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.84196310
Short name T1867
Test name
Test status
Simulation time 208873225 ps
CPU time 0.88 seconds
Started Jul 18 05:44:12 PM PDT 24
Finished Jul 18 05:44:19 PM PDT 24
Peak memory 206620 kb
Host smart-e2414146-bd4d-4bd7-b200-7048b72ec2fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84196
310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.84196310
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3902591846
Short name T1903
Test name
Test status
Simulation time 6282008710 ps
CPU time 59.67 seconds
Started Jul 18 05:44:11 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206844 kb
Host smart-13c22447-ef3b-49bb-be3b-a2cd6a097141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39025
91846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3902591846
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.274969755
Short name T766
Test name
Test status
Simulation time 4239388950 ps
CPU time 29.42 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:50 PM PDT 24
Peak memory 206896 kb
Host smart-794c6fa5-ea91-487e-9b54-dfb7e3914298
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=274969755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.274969755
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.2867536990
Short name T1770
Test name
Test status
Simulation time 162318102 ps
CPU time 0.78 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:20 PM PDT 24
Peak memory 206644 kb
Host smart-e6f26c76-077b-4b77-a75a-1e99b50debc3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2867536990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.2867536990
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.288396411
Short name T1054
Test name
Test status
Simulation time 162480532 ps
CPU time 0.78 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:44:25 PM PDT 24
Peak memory 206616 kb
Host smart-f6df1a40-b842-4457-8b4f-86d1ae6386f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28839
6411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.288396411
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.275922522
Short name T1472
Test name
Test status
Simulation time 224087045 ps
CPU time 0.89 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:44:26 PM PDT 24
Peak memory 206812 kb
Host smart-bdc7f082-f40e-4d0a-9cca-a8fe0efb6652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27592
2522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.275922522
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.1507775248
Short name T756
Test name
Test status
Simulation time 182462413 ps
CPU time 0.78 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:44:22 PM PDT 24
Peak memory 206656 kb
Host smart-ceecbc1a-e374-4f81-a0c8-fdaa99059bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15077
75248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.1507775248
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2158434889
Short name T2557
Test name
Test status
Simulation time 153529402 ps
CPU time 0.76 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206640 kb
Host smart-cef9f2e3-ea55-4e7d-ae77-ad3b9da1462e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21584
34889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2158434889
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2848131281
Short name T1495
Test name
Test status
Simulation time 157484299 ps
CPU time 0.79 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206816 kb
Host smart-3651fff0-4246-4a48-8d88-c6612e8f9448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28481
31281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2848131281
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.376784844
Short name T1519
Test name
Test status
Simulation time 172646870 ps
CPU time 0.85 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206660 kb
Host smart-c84a8ca0-fa4e-497e-90b7-ee68941767f2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=376784844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.376784844
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3677680540
Short name T1971
Test name
Test status
Simulation time 288897495 ps
CPU time 1.02 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:44:26 PM PDT 24
Peak memory 206816 kb
Host smart-31e5e091-5817-4811-9926-1a53f723d263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36776
80540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3677680540
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.1258015550
Short name T2473
Test name
Test status
Simulation time 144841620 ps
CPU time 0.78 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206648 kb
Host smart-4795ccc0-1c04-473f-a0e6-cd67b9123e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12580
15550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.1258015550
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.3436531004
Short name T2221
Test name
Test status
Simulation time 36157209 ps
CPU time 0.66 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206636 kb
Host smart-de90d837-8d3f-4a4f-b92f-3d172531f197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34365
31004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.3436531004
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.214165238
Short name T1156
Test name
Test status
Simulation time 10280582506 ps
CPU time 23.08 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:43 PM PDT 24
Peak memory 206964 kb
Host smart-40816b73-d359-4bd9-a4e6-e6b49dc3bda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21416
5238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.214165238
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.486865329
Short name T2350
Test name
Test status
Simulation time 201334300 ps
CPU time 0.84 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:44:25 PM PDT 24
Peak memory 206572 kb
Host smart-ccf0178c-7a46-41ac-9daf-f0252a15fc89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48686
5329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.486865329
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2612937017
Short name T2547
Test name
Test status
Simulation time 217439624 ps
CPU time 0.88 seconds
Started Jul 18 05:44:17 PM PDT 24
Finished Jul 18 05:44:25 PM PDT 24
Peak memory 206636 kb
Host smart-719ddd76-f858-4281-afcd-af4a17056fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26129
37017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2612937017
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.3613056973
Short name T174
Test name
Test status
Simulation time 10794855273 ps
CPU time 209.07 seconds
Started Jul 18 05:44:14 PM PDT 24
Finished Jul 18 05:47:51 PM PDT 24
Peak memory 206952 kb
Host smart-758b57e9-19c9-43d8-8238-237f07ef8e2e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3613056973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.3613056973
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2439184134
Short name T2630
Test name
Test status
Simulation time 6916555251 ps
CPU time 181.81 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:47:22 PM PDT 24
Peak memory 206888 kb
Host smart-96042e73-6a0b-4b42-ae14-1bd1b99318d7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2439184134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2439184134
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.2542247249
Short name T379
Test name
Test status
Simulation time 11738140637 ps
CPU time 58.04 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:45:17 PM PDT 24
Peak memory 206956 kb
Host smart-b9ab7887-d5e7-47d1-b326-3fe902850c70
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2542247249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.2542247249
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.644283316
Short name T887
Test name
Test status
Simulation time 288196408 ps
CPU time 1.01 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206636 kb
Host smart-c4da72a1-b2c1-4c89-a7bd-57b4a66b2dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64428
3316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.644283316
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.1407078578
Short name T1685
Test name
Test status
Simulation time 157504041 ps
CPU time 0.85 seconds
Started Jul 18 05:44:16 PM PDT 24
Finished Jul 18 05:44:24 PM PDT 24
Peak memory 206628 kb
Host smart-cac30ce9-68bb-46f4-94e0-3c422f27eb6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14070
78578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.1407078578
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.95534636
Short name T2686
Test name
Test status
Simulation time 184642259 ps
CPU time 0.79 seconds
Started Jul 18 05:44:15 PM PDT 24
Finished Jul 18 05:44:23 PM PDT 24
Peak memory 206652 kb
Host smart-721371fd-5b62-4d72-8e93-84deedce9339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95534
636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.95534636
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.4198461866
Short name T2211
Test name
Test status
Simulation time 187756543 ps
CPU time 0.85 seconds
Started Jul 18 05:44:15 PM PDT 24
Finished Jul 18 05:44:23 PM PDT 24
Peak memory 206636 kb
Host smart-cb77b2ec-820f-4675-b7bf-d741f3f87f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41984
61866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.4198461866
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3258526023
Short name T203
Test name
Test status
Simulation time 392515428 ps
CPU time 1.23 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:40 PM PDT 24
Peak memory 224448 kb
Host smart-5f3cd862-220e-476a-901f-555e194c0f83
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3258526023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3258526023
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.4224421929
Short name T55
Test name
Test status
Simulation time 510179380 ps
CPU time 1.36 seconds
Started Jul 18 05:44:13 PM PDT 24
Finished Jul 18 05:44:21 PM PDT 24
Peak memory 206632 kb
Host smart-12d9d955-6c57-47be-bb42-c0dfc0e841f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42244
21929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.4224421929
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.2215305096
Short name T2412
Test name
Test status
Simulation time 308825472 ps
CPU time 1.01 seconds
Started Jul 18 05:44:34 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 206624 kb
Host smart-2cec517c-c45d-4b67-8e9b-b9fbde4235a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22153
05096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.2215305096
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2012492584
Short name T1432
Test name
Test status
Simulation time 163415682 ps
CPU time 0.81 seconds
Started Jul 18 05:44:33 PM PDT 24
Finished Jul 18 05:44:35 PM PDT 24
Peak memory 206636 kb
Host smart-b60b4a26-74fb-430c-a95b-c9eaec87f655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
92584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2012492584
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2649425960
Short name T1715
Test name
Test status
Simulation time 166556071 ps
CPU time 0.82 seconds
Started Jul 18 05:44:35 PM PDT 24
Finished Jul 18 05:44:39 PM PDT 24
Peak memory 206632 kb
Host smart-4e56ab11-ce58-4fd2-b0f0-c4ad7dc5b370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26494
25960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2649425960
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1996183473
Short name T1940
Test name
Test status
Simulation time 233162478 ps
CPU time 1.08 seconds
Started Jul 18 05:44:34 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 206812 kb
Host smart-7f66426b-e259-4aec-8df2-6167e9120344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19961
83473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1996183473
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.143397148
Short name T1473
Test name
Test status
Simulation time 4107712920 ps
CPU time 117.49 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:46:36 PM PDT 24
Peak memory 206860 kb
Host smart-333b86ae-8e24-405f-b031-367bd1efe9c1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=143397148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.143397148
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.74889570
Short name T2346
Test name
Test status
Simulation time 194317031 ps
CPU time 0.92 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:39 PM PDT 24
Peak memory 206652 kb
Host smart-84d323c1-c98a-46b4-9e58-2ef2be6ca3d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74889
570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.74889570
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1541657747
Short name T2551
Test name
Test status
Simulation time 217728816 ps
CPU time 0.86 seconds
Started Jul 18 05:44:40 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206604 kb
Host smart-66e15adb-b7a2-4525-8c26-984a24a86a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15416
57747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1541657747
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.4098919681
Short name T691
Test name
Test status
Simulation time 494129008 ps
CPU time 1.35 seconds
Started Jul 18 05:44:34 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 206636 kb
Host smart-41fb43c6-9a2a-435f-9585-38d94c1a7767
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40989
19681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.4098919681
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.2482808525
Short name T884
Test name
Test status
Simulation time 4731753662 ps
CPU time 127.69 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:46:49 PM PDT 24
Peak memory 206548 kb
Host smart-a1a786b3-0a20-4775-8d71-9c9e651d1630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24828
08525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.2482808525
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.223359672
Short name T2427
Test name
Test status
Simulation time 35741952 ps
CPU time 0.67 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:50:40 PM PDT 24
Peak memory 206680 kb
Host smart-a7aa2cd5-a2ad-4c90-94bd-0d0b8c19606e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=223359672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.223359672
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.2216158829
Short name T408
Test name
Test status
Simulation time 4299388666 ps
CPU time 5.26 seconds
Started Jul 18 05:50:21 PM PDT 24
Finished Jul 18 05:50:36 PM PDT 24
Peak memory 206764 kb
Host smart-af925ca6-7bc1-4495-b08c-91e5e7f72a5a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2216158829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.2216158829
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1899705349
Short name T1125
Test name
Test status
Simulation time 13420601589 ps
CPU time 12.81 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:35 PM PDT 24
Peak memory 206892 kb
Host smart-f6ec61e4-cbb5-48bf-90b2-531172133a1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1899705349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1899705349
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.3298908876
Short name T1453
Test name
Test status
Simulation time 23339703369 ps
CPU time 22.65 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:51:08 PM PDT 24
Peak memory 206780 kb
Host smart-3e8c3a46-5af7-47de-af07-8dcf72a7e321
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3298908876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.3298908876
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.141781380
Short name T2493
Test name
Test status
Simulation time 168703971 ps
CPU time 0.81 seconds
Started Jul 18 05:50:20 PM PDT 24
Finished Jul 18 05:50:31 PM PDT 24
Peak memory 206656 kb
Host smart-16f32401-2d53-4212-ae32-0087954e9b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14178
1380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.141781380
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3533634116
Short name T618
Test name
Test status
Simulation time 153794948 ps
CPU time 0.77 seconds
Started Jul 18 05:50:12 PM PDT 24
Finished Jul 18 05:50:18 PM PDT 24
Peak memory 206648 kb
Host smart-7ec04bfc-9071-4208-9d34-53f6fa1f71ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35336
34116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3533634116
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3493999875
Short name T2138
Test name
Test status
Simulation time 487404444 ps
CPU time 1.45 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:25 PM PDT 24
Peak memory 206744 kb
Host smart-873fba27-8755-495f-a0ea-6b4a8f63a1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34939
99875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3493999875
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2045119125
Short name T1238
Test name
Test status
Simulation time 759648767 ps
CPU time 1.81 seconds
Started Jul 18 05:50:13 PM PDT 24
Finished Jul 18 05:50:22 PM PDT 24
Peak memory 206728 kb
Host smart-4b96920f-ca4e-410c-94a3-4b87353eb1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
19125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2045119125
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1266050365
Short name T2455
Test name
Test status
Simulation time 23026792181 ps
CPU time 52.17 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206900 kb
Host smart-7b055944-61c1-473f-a5e5-950f9e7a74d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12660
50365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1266050365
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.2200640640
Short name T1425
Test name
Test status
Simulation time 575128088 ps
CPU time 1.48 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:46 PM PDT 24
Peak memory 206624 kb
Host smart-b882083a-f755-4236-b5b5-b7250dbd2848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22006
40640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.2200640640
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1470656868
Short name T2153
Test name
Test status
Simulation time 184403496 ps
CPU time 0.82 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206628 kb
Host smart-9b6ade25-04ac-4505-8d60-80a9eef1ea53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14706
56868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1470656868
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.3619680671
Short name T2574
Test name
Test status
Simulation time 70672107 ps
CPU time 0.69 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:50:30 PM PDT 24
Peak memory 206644 kb
Host smart-5fc8e896-5299-45cc-b65e-3adcf8b52938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36196
80671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.3619680671
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.3430752912
Short name T1590
Test name
Test status
Simulation time 917714479 ps
CPU time 2.2 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:50:58 PM PDT 24
Peak memory 206756 kb
Host smart-a815a63b-a0ca-4498-ba4f-4215f02697d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34307
52912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.3430752912
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.1771967224
Short name T1465
Test name
Test status
Simulation time 162477962 ps
CPU time 1.4 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:50:57 PM PDT 24
Peak memory 206808 kb
Host smart-562f7cc4-1937-4fb0-b7d3-437ce3c3e861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17719
67224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.1771967224
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.390132057
Short name T2355
Test name
Test status
Simulation time 236972776 ps
CPU time 0.9 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:46 PM PDT 24
Peak memory 206664 kb
Host smart-09c4eef0-5c9f-40f3-bf67-e33153e2cc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39013
2057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.390132057
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.2485921861
Short name T2441
Test name
Test status
Simulation time 155303431 ps
CPU time 0.78 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206644 kb
Host smart-c6ce187d-9362-45f7-87d6-de944ddffdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24859
21861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.2485921861
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.349562503
Short name T642
Test name
Test status
Simulation time 195569993 ps
CPU time 0.85 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206648 kb
Host smart-0e731d5e-70d0-47b4-b039-ad52f8127dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34956
2503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.349562503
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.1615590779
Short name T102
Test name
Test status
Simulation time 6556157157 ps
CPU time 186.16 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:53:32 PM PDT 24
Peak memory 206872 kb
Host smart-9705a6da-6267-4f72-b8fa-ea15a3b05415
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1615590779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.1615590779
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.3578853436
Short name T2672
Test name
Test status
Simulation time 11959496989 ps
CPU time 103.92 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:52:31 PM PDT 24
Peak memory 206920 kb
Host smart-1f30158b-dfd3-45ed-b0e0-dedc00180317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35788
53436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.3578853436
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.407730600
Short name T342
Test name
Test status
Simulation time 242909898 ps
CPU time 0.91 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206648 kb
Host smart-9c6e7d71-cffb-4e19-9b54-3379a7af8698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40773
0600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.407730600
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3368594259
Short name T2149
Test name
Test status
Simulation time 23328169002 ps
CPU time 24.43 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:51:09 PM PDT 24
Peak memory 206772 kb
Host smart-e9523a05-767d-41df-99b3-5abf11d6d70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33685
94259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3368594259
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.4220535123
Short name T1045
Test name
Test status
Simulation time 3299419600 ps
CPU time 3.67 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206716 kb
Host smart-3a90e433-aa39-40d7-b29f-9234d4595296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42205
35123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.4220535123
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1300169368
Short name T1899
Test name
Test status
Simulation time 8559700878 ps
CPU time 238.4 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:54:27 PM PDT 24
Peak memory 206900 kb
Host smart-7d1db11e-33b9-4e47-83e4-b467faf280a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13001
69368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1300169368
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.263222780
Short name T2548
Test name
Test status
Simulation time 273681570 ps
CPU time 0.96 seconds
Started Jul 18 05:50:20 PM PDT 24
Finished Jul 18 05:50:31 PM PDT 24
Peak memory 206648 kb
Host smart-7dc8114c-5bb8-41fc-bfde-6108801b5d4f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=263222780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.263222780
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3209463397
Short name T426
Test name
Test status
Simulation time 202992257 ps
CPU time 0.93 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:50:30 PM PDT 24
Peak memory 206616 kb
Host smart-90dbf1a0-8b3b-4711-9b93-801e79217c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32094
63397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3209463397
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.1405186351
Short name T1736
Test name
Test status
Simulation time 4657651961 ps
CPU time 131.04 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:52:36 PM PDT 24
Peak memory 207016 kb
Host smart-d8871fa0-5be4-47b3-b7e7-1b8ee54ababb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14051
86351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.1405186351
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.1928724656
Short name T944
Test name
Test status
Simulation time 5271017672 ps
CPU time 51.13 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206844 kb
Host smart-1ebb0bcd-33bf-470e-a7cc-5d181cdafdca
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1928724656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.1928724656
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.226475059
Short name T2435
Test name
Test status
Simulation time 174165057 ps
CPU time 0.85 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:22 PM PDT 24
Peak memory 206652 kb
Host smart-c0879f3d-a3c1-43fb-932b-8f2217e7abfd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=226475059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.226475059
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.327529042
Short name T1536
Test name
Test status
Simulation time 156655997 ps
CPU time 0.75 seconds
Started Jul 18 05:50:14 PM PDT 24
Finished Jul 18 05:50:23 PM PDT 24
Peak memory 206652 kb
Host smart-4d5b04f3-3d17-4780-9e8e-48ae46873f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32752
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.327529042
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.128990148
Short name T131
Test name
Test status
Simulation time 216802319 ps
CPU time 0.89 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206632 kb
Host smart-dcd05c11-d93c-49aa-ae53-bfaaee041435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12899
0148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.128990148
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.211037743
Short name T2076
Test name
Test status
Simulation time 166334845 ps
CPU time 0.81 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206648 kb
Host smart-6de33e42-f9ef-4889-bd58-eeea8bafaaed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21103
7743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.211037743
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.3453289887
Short name T1395
Test name
Test status
Simulation time 205602004 ps
CPU time 0.9 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206652 kb
Host smart-a3caad82-e7bb-4223-b012-e68e7ad26992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34532
89887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.3453289887
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.4133349494
Short name T1584
Test name
Test status
Simulation time 163736582 ps
CPU time 0.78 seconds
Started Jul 18 05:50:18 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206640 kb
Host smart-794dbba7-8aa7-4db2-bc39-37b56de8b43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41333
49494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.4133349494
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1558518163
Short name T1455
Test name
Test status
Simulation time 202477485 ps
CPU time 0.83 seconds
Started Jul 18 05:50:11 PM PDT 24
Finished Jul 18 05:50:18 PM PDT 24
Peak memory 206616 kb
Host smart-c6bd8aba-88b4-44e6-ab77-46c9a7107348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
18163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1558518163
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.147157044
Short name T1595
Test name
Test status
Simulation time 223160344 ps
CPU time 0.87 seconds
Started Jul 18 05:50:16 PM PDT 24
Finished Jul 18 05:50:26 PM PDT 24
Peak memory 206660 kb
Host smart-90a5f6d9-727a-449b-867b-a317faebfb70
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=147157044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.147157044
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.3349992276
Short name T1135
Test name
Test status
Simulation time 148989546 ps
CPU time 0.74 seconds
Started Jul 18 05:50:18 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206648 kb
Host smart-c47a9a3a-8022-49e6-b58f-fde03e5dc3c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33499
92276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.3349992276
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.1116478533
Short name T2532
Test name
Test status
Simulation time 30573756 ps
CPU time 0.66 seconds
Started Jul 18 05:50:17 PM PDT 24
Finished Jul 18 05:50:28 PM PDT 24
Peak memory 206520 kb
Host smart-c2a184c7-da6a-4f23-87c0-3ad4d98f5eda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11164
78533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.1116478533
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.4109535746
Short name T753
Test name
Test status
Simulation time 14055636391 ps
CPU time 33.64 seconds
Started Jul 18 05:50:19 PM PDT 24
Finished Jul 18 05:51:03 PM PDT 24
Peak memory 206924 kb
Host smart-da4bce53-1d15-430d-be16-d023d4ba0b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41095
35746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.4109535746
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2698791697
Short name T1644
Test name
Test status
Simulation time 150346318 ps
CPU time 0.76 seconds
Started Jul 18 05:50:18 PM PDT 24
Finished Jul 18 05:50:29 PM PDT 24
Peak memory 206484 kb
Host smart-87f5865d-8c18-4009-89c4-7ae0396016a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26987
91697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2698791697
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1709324268
Short name T1460
Test name
Test status
Simulation time 171647325 ps
CPU time 0.81 seconds
Started Jul 18 05:50:21 PM PDT 24
Finished Jul 18 05:50:33 PM PDT 24
Peak memory 206628 kb
Host smart-67ff5ea2-2558-41ea-b117-4d348003bf7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
24268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1709324268
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.3987129602
Short name T1515
Test name
Test status
Simulation time 210813690 ps
CPU time 0.86 seconds
Started Jul 18 05:50:20 PM PDT 24
Finished Jul 18 05:50:31 PM PDT 24
Peak memory 206640 kb
Host smart-48a0ed56-627f-455c-a91a-1a4185ab791b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39871
29602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.3987129602
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.87887607
Short name T2711
Test name
Test status
Simulation time 224079506 ps
CPU time 0.88 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:25 PM PDT 24
Peak memory 206656 kb
Host smart-efbaac53-a1c3-4593-865c-b4fd94835455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87887
607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.87887607
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.3671572572
Short name T741
Test name
Test status
Simulation time 190232787 ps
CPU time 0.83 seconds
Started Jul 18 05:50:15 PM PDT 24
Finished Jul 18 05:50:25 PM PDT 24
Peak memory 206628 kb
Host smart-17bfd9fd-a240-4506-9d69-feabbffe5d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36715
72572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.3671572572
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2991532505
Short name T2122
Test name
Test status
Simulation time 169201017 ps
CPU time 0.83 seconds
Started Jul 18 05:50:13 PM PDT 24
Finished Jul 18 05:50:20 PM PDT 24
Peak memory 206632 kb
Host smart-01b93819-063e-4389-bb33-8d48ac25f5c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29915
32505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2991532505
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.2560764988
Short name T2201
Test name
Test status
Simulation time 199813023 ps
CPU time 0.79 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:50 PM PDT 24
Peak memory 206652 kb
Host smart-026341c3-b525-4785-bffd-455766a5ea91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
64988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.2560764988
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1883900800
Short name T388
Test name
Test status
Simulation time 217968704 ps
CPU time 0.9 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206652 kb
Host smart-ce062556-300f-4427-b562-0f614cc08e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
00800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1883900800
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.1566117495
Short name T1267
Test name
Test status
Simulation time 4236846514 ps
CPU time 32.61 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:51:24 PM PDT 24
Peak memory 206896 kb
Host smart-ca720dcc-21bb-4416-9886-f758eeaeacf0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1566117495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.1566117495
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.3141392460
Short name T1904
Test name
Test status
Simulation time 177394516 ps
CPU time 0.82 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206648 kb
Host smart-33690586-3782-4159-bf1d-d5a61ec89fe4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31413
92460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.3141392460
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.3243930443
Short name T830
Test name
Test status
Simulation time 181316095 ps
CPU time 0.8 seconds
Started Jul 18 05:50:25 PM PDT 24
Finished Jul 18 05:50:37 PM PDT 24
Peak memory 206636 kb
Host smart-89d46d58-877a-49b5-b60e-2c2109e6d1fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32439
30443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.3243930443
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.2741887059
Short name T2383
Test name
Test status
Simulation time 760060446 ps
CPU time 1.72 seconds
Started Jul 18 05:50:27 PM PDT 24
Finished Jul 18 05:50:42 PM PDT 24
Peak memory 206756 kb
Host smart-b3c17dd3-8b1f-4564-9b79-bad7a0446152
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27418
87059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.2741887059
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2189680832
Short name T1565
Test name
Test status
Simulation time 3783384755 ps
CPU time 104.28 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:52:36 PM PDT 24
Peak memory 206860 kb
Host smart-d19179de-446d-47d0-b1f1-9a5c16e0b301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21896
80832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2189680832
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.3593987195
Short name T2364
Test name
Test status
Simulation time 129686349 ps
CPU time 0.74 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:50:54 PM PDT 24
Peak memory 206692 kb
Host smart-f14d1247-1524-4408-a55e-3efdc32911c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3593987195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.3593987195
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.2781721403
Short name T1797
Test name
Test status
Simulation time 3902010483 ps
CPU time 6 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206708 kb
Host smart-f5587fcf-88a5-4eef-a707-b00a0f181ee6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2781721403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.2781721403
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.1635939848
Short name T2744
Test name
Test status
Simulation time 13445852361 ps
CPU time 13.91 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:59 PM PDT 24
Peak memory 206908 kb
Host smart-5706e424-1ea3-4d1a-83d7-baf67bd0ea73
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1635939848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.1635939848
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3402058794
Short name T1842
Test name
Test status
Simulation time 23363099102 ps
CPU time 22.55 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206776 kb
Host smart-443d618e-a173-4af6-87d1-a0dc71e14c9e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3402058794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3402058794
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.3350630736
Short name T1979
Test name
Test status
Simulation time 158046524 ps
CPU time 0.82 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:50:44 PM PDT 24
Peak memory 206648 kb
Host smart-c305305c-1ab1-424a-9440-a8d25679415d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33506
30736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.3350630736
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.330406349
Short name T2032
Test name
Test status
Simulation time 157863526 ps
CPU time 0.76 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206656 kb
Host smart-212ccb9c-1172-4cca-a6be-bfdbd95bbd47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33040
6349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.330406349
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1374764564
Short name T1885
Test name
Test status
Simulation time 216827127 ps
CPU time 0.89 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:50:42 PM PDT 24
Peak memory 206540 kb
Host smart-68c11bc6-7152-45b5-954b-39f5a214be92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13747
64564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1374764564
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1844812014
Short name T1876
Test name
Test status
Simulation time 688846378 ps
CPU time 1.72 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206720 kb
Host smart-b714d32b-cfa8-4bdb-a71f-82d1dcb233a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18448
12014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1844812014
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1691734369
Short name T2106
Test name
Test status
Simulation time 15392442165 ps
CPU time 27.95 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:51:15 PM PDT 24
Peak memory 206848 kb
Host smart-27ce553f-f35b-4313-a15b-5b7e32b3a11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16917
34369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1691734369
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.440543179
Short name T2530
Test name
Test status
Simulation time 469110405 ps
CPU time 1.37 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206648 kb
Host smart-9f009362-4403-42b1-931a-3d2df6a84335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44054
3179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.440543179
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1496045743
Short name T1171
Test name
Test status
Simulation time 139397108 ps
CPU time 0.81 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:50:44 PM PDT 24
Peak memory 206652 kb
Host smart-0f5b5f62-e0dd-48ff-8385-5598678aec56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960
45743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1496045743
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.2115946124
Short name T1146
Test name
Test status
Simulation time 41016632 ps
CPU time 0.69 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206644 kb
Host smart-e2ac2a48-4da3-4bc1-9496-2908630941fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21159
46124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.2115946124
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.4271302601
Short name T2621
Test name
Test status
Simulation time 738762525 ps
CPU time 2.02 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206784 kb
Host smart-94cce8b6-597f-4527-ab06-d0a7f89925b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42713
02601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.4271302601
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3396610551
Short name T2726
Test name
Test status
Simulation time 322832138 ps
CPU time 2.17 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:49 PM PDT 24
Peak memory 206732 kb
Host smart-2ee02b31-9be2-4855-9b82-247c0b28f83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33966
10551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3396610551
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3857098284
Short name T1112
Test name
Test status
Simulation time 212129698 ps
CPU time 0.9 seconds
Started Jul 18 05:50:25 PM PDT 24
Finished Jul 18 05:50:39 PM PDT 24
Peak memory 206644 kb
Host smart-9d93c75d-9231-486d-a908-d3d317d2d44b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38570
98284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3857098284
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.2838105242
Short name T1179
Test name
Test status
Simulation time 186176191 ps
CPU time 0.84 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206644 kb
Host smart-d8eb41a5-2ad7-434e-8b93-14603e618160
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28381
05242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.2838105242
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.1107005824
Short name T1477
Test name
Test status
Simulation time 254318530 ps
CPU time 0.85 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:46 PM PDT 24
Peak memory 206636 kb
Host smart-f8be91f9-925d-4fde-b941-e3d59e757a99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11070
05824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.1107005824
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.2313801642
Short name T206
Test name
Test status
Simulation time 8975648765 ps
CPU time 245.43 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:54:45 PM PDT 24
Peak memory 206956 kb
Host smart-9ce070c6-3953-458b-88ca-673ce5d571e1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2313801642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.2313801642
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.250615205
Short name T1286
Test name
Test status
Simulation time 9340123046 ps
CPU time 82.9 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:52:10 PM PDT 24
Peak memory 206884 kb
Host smart-a3c4f58d-ece9-48b4-a151-2910c10c025f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25061
5205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.250615205
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3638867946
Short name T789
Test name
Test status
Simulation time 169193878 ps
CPU time 0.85 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:49 PM PDT 24
Peak memory 206648 kb
Host smart-999bf250-ee8f-4cc8-b0d9-b17147cf4014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
67946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3638867946
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3469517482
Short name T2688
Test name
Test status
Simulation time 23318155855 ps
CPU time 22.38 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:51:02 PM PDT 24
Peak memory 206780 kb
Host smart-6e50d15c-cba6-4713-9aea-20688419279c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34695
17482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3469517482
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.4221880974
Short name T2223
Test name
Test status
Simulation time 3319567606 ps
CPU time 3.88 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206720 kb
Host smart-797320dd-ae3c-4a7b-b540-304ffd0394bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42218
80974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.4221880974
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2080952997
Short name T1632
Test name
Test status
Simulation time 8120478074 ps
CPU time 61.61 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:51:41 PM PDT 24
Peak memory 206896 kb
Host smart-bf946405-5ae8-426d-8985-5ae173dc87bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20809
52997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2080952997
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2484737787
Short name T1852
Test name
Test status
Simulation time 2983769355 ps
CPU time 21.53 seconds
Started Jul 18 05:50:24 PM PDT 24
Finished Jul 18 05:50:57 PM PDT 24
Peak memory 206888 kb
Host smart-1c183b67-33ef-4bf6-b1fc-89d8ef2ba1af
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2484737787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2484737787
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1836391210
Short name T2235
Test name
Test status
Simulation time 239282832 ps
CPU time 1.01 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206652 kb
Host smart-64bf2b0d-5673-4c3b-b2ec-3e20c59b50cf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1836391210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1836391210
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.749509057
Short name T2331
Test name
Test status
Simulation time 192056389 ps
CPU time 0.91 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206624 kb
Host smart-f219c9b1-900b-426b-887c-4521f26682c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74950
9057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.749509057
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1279636825
Short name T1373
Test name
Test status
Simulation time 4143964400 ps
CPU time 30.65 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206828 kb
Host smart-53fcc13f-581b-416e-a2ed-759d55d08e2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12796
36825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1279636825
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2276660019
Short name T2589
Test name
Test status
Simulation time 3963222532 ps
CPU time 104.09 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:52:23 PM PDT 24
Peak memory 206884 kb
Host smart-cf58955f-1c5a-4eb1-a072-9908720adb3e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2276660019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2276660019
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.1084946985
Short name T531
Test name
Test status
Simulation time 156676338 ps
CPU time 0.76 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206648 kb
Host smart-42f54662-d07e-4f88-8e65-68acb31d53b9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1084946985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.1084946985
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.3563258906
Short name T328
Test name
Test status
Simulation time 178302856 ps
CPU time 0.77 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206532 kb
Host smart-40330893-64ec-44eb-adf8-300d633791ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35632
58906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.3563258906
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.495531871
Short name T1609
Test name
Test status
Simulation time 180289202 ps
CPU time 0.83 seconds
Started Jul 18 05:50:34 PM PDT 24
Finished Jul 18 05:50:56 PM PDT 24
Peak memory 206644 kb
Host smart-6837ca36-5d0e-4890-a4c9-6ad16f9ee7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49553
1871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.495531871
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1612888543
Short name T354
Test name
Test status
Simulation time 219557905 ps
CPU time 0.9 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206668 kb
Host smart-2228807f-fcbf-47c1-a329-820c96c827fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16128
88543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1612888543
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.920343832
Short name T1683
Test name
Test status
Simulation time 146511378 ps
CPU time 0.75 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206656 kb
Host smart-222a7b29-66fa-4889-8b71-b9c95fb698cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92034
3832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.920343832
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1390333615
Short name T311
Test name
Test status
Simulation time 197125853 ps
CPU time 0.82 seconds
Started Jul 18 05:50:24 PM PDT 24
Finished Jul 18 05:50:36 PM PDT 24
Peak memory 206636 kb
Host smart-f03dbd0d-f40a-46bd-a3df-3371ca989bd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13903
33615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1390333615
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3609607418
Short name T2443
Test name
Test status
Simulation time 179611857 ps
CPU time 0.82 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206632 kb
Host smart-0e34d868-38c1-4318-979b-f96fde2c2e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36096
07418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3609607418
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.911291458
Short name T376
Test name
Test status
Simulation time 218625989 ps
CPU time 0.98 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206624 kb
Host smart-e1a1a562-f7c9-47a1-a805-1b2d9c8d6664
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=911291458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.911291458
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.271982418
Short name T37
Test name
Test status
Simulation time 167185874 ps
CPU time 0.75 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206644 kb
Host smart-8634ed6b-f8ac-4e36-b589-e8f702601ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27198
2418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.271982418
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.325814374
Short name T2699
Test name
Test status
Simulation time 38865032 ps
CPU time 0.67 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206644 kb
Host smart-1ad9eca7-74cf-4cdc-9bc5-bda545bc93a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32581
4374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.325814374
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.2802291116
Short name T233
Test name
Test status
Simulation time 14609859445 ps
CPU time 30.72 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:51:18 PM PDT 24
Peak memory 206920 kb
Host smart-ffe4e769-48d9-48b8-8eba-0684840bcb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28022
91116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.2802291116
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1676836143
Short name T696
Test name
Test status
Simulation time 193608516 ps
CPU time 0.85 seconds
Started Jul 18 05:50:25 PM PDT 24
Finished Jul 18 05:50:37 PM PDT 24
Peak memory 206636 kb
Host smart-8fb63ce4-d8b3-4376-9ec1-4f4d5758bbbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16768
36143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1676836143
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3893273022
Short name T2053
Test name
Test status
Simulation time 264064069 ps
CPU time 0.97 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:50:44 PM PDT 24
Peak memory 206656 kb
Host smart-a064c443-0944-4d28-960c-347e142b7aa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38932
73022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3893273022
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.2561511240
Short name T1406
Test name
Test status
Simulation time 172830377 ps
CPU time 0.79 seconds
Started Jul 18 05:50:25 PM PDT 24
Finished Jul 18 05:50:38 PM PDT 24
Peak memory 206632 kb
Host smart-1f006762-0b77-4ef5-adf7-10af899ac11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25615
11240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.2561511240
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1968673717
Short name T1257
Test name
Test status
Simulation time 201277602 ps
CPU time 0.9 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206668 kb
Host smart-67124176-265f-4042-a740-cc6c800a38bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19686
73717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1968673717
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.2999006643
Short name T496
Test name
Test status
Simulation time 147411144 ps
CPU time 0.75 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206632 kb
Host smart-253605e7-421a-420e-a1d0-2193ec5bb243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29990
06643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.2999006643
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.2710126919
Short name T2582
Test name
Test status
Simulation time 190399205 ps
CPU time 0.82 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206668 kb
Host smart-c2d0c349-0084-41d9-951e-a9a7f96348f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27101
26919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.2710126919
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1279951429
Short name T1554
Test name
Test status
Simulation time 179877254 ps
CPU time 0.84 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206620 kb
Host smart-d22f827c-8fda-46bb-826e-91e711bfce4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12799
51429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1279951429
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.4242204561
Short name T48
Test name
Test status
Simulation time 245187011 ps
CPU time 0.96 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206632 kb
Host smart-556a63fc-b01d-4d6c-bf66-73cef07b0acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42422
04561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.4242204561
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2367503514
Short name T565
Test name
Test status
Simulation time 3689286723 ps
CPU time 35.61 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:51:29 PM PDT 24
Peak memory 206856 kb
Host smart-9256cd8c-bde6-420d-bdab-4cfd50b136f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2367503514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2367503514
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.997163316
Short name T204
Test name
Test status
Simulation time 183448979 ps
CPU time 0.89 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:51 PM PDT 24
Peak memory 206652 kb
Host smart-0b2fc41a-54ba-4092-880e-45b8c553e487
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99716
3316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.997163316
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.3040812883
Short name T291
Test name
Test status
Simulation time 189705081 ps
CPU time 0.85 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206620 kb
Host smart-223c1fa6-89a4-4254-b2e9-c9b85882a3dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30408
12883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.3040812883
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2482402164
Short name T1757
Test name
Test status
Simulation time 1019011580 ps
CPU time 2.36 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206732 kb
Host smart-3b3e8003-7de9-4f45-a412-371804287fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24824
02164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2482402164
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2720258984
Short name T2289
Test name
Test status
Simulation time 6262864094 ps
CPU time 61.42 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:51:53 PM PDT 24
Peak memory 206864 kb
Host smart-4f2ed54a-69ec-4b8a-8cae-9e8ea1868c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
58984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2720258984
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2641502513
Short name T181
Test name
Test status
Simulation time 48629689 ps
CPU time 0.72 seconds
Started Jul 18 05:50:37 PM PDT 24
Finished Jul 18 05:50:59 PM PDT 24
Peak memory 206680 kb
Host smart-b0603459-86ef-4ff0-b113-c4fa1f8a1ac3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2641502513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2641502513
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.2256136766
Short name T2018
Test name
Test status
Simulation time 3605255770 ps
CPU time 4.31 seconds
Started Jul 18 05:50:37 PM PDT 24
Finished Jul 18 05:51:02 PM PDT 24
Peak memory 206712 kb
Host smart-7dc98be2-434c-4582-ad8a-e1c5de4cfc84
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2256136766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.2256136766
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.501248720
Short name T212
Test name
Test status
Simulation time 13426149355 ps
CPU time 12.46 seconds
Started Jul 18 05:50:34 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206840 kb
Host smart-f87f1365-17bc-44e2-a903-02db9a88b3d0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=501248720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.501248720
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.1053814742
Short name T2131
Test name
Test status
Simulation time 23387730414 ps
CPU time 29.35 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:51:25 PM PDT 24
Peak memory 206744 kb
Host smart-f3b35d27-a1d7-44a7-abfb-d7ce57f0bc69
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1053814742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.1053814742
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1943906159
Short name T2588
Test name
Test status
Simulation time 173457532 ps
CPU time 0.86 seconds
Started Jul 18 05:50:37 PM PDT 24
Finished Jul 18 05:50:58 PM PDT 24
Peak memory 206624 kb
Host smart-b041a342-9178-429e-99fc-adde973c3398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19439
06159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1943906159
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.472324800
Short name T1844
Test name
Test status
Simulation time 204273238 ps
CPU time 0.81 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206728 kb
Host smart-15dffcbf-6916-4e36-a1d3-cf0e902d435e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47232
4800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.472324800
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.2470343182
Short name T2316
Test name
Test status
Simulation time 163259854 ps
CPU time 0.8 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206724 kb
Host smart-218ea3aa-f59f-43ee-b6ab-d0ec674c84fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24703
43182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.2470343182
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.819661579
Short name T480
Test name
Test status
Simulation time 339845576 ps
CPU time 1.07 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206632 kb
Host smart-a19644e1-9abf-4511-8f18-8900e7224f2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81966
1579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.819661579
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1034290533
Short name T96
Test name
Test status
Simulation time 16560108358 ps
CPU time 30.1 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:30 PM PDT 24
Peak memory 206908 kb
Host smart-3b77e47a-8b36-44a9-b2c0-ceea8ee416a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10342
90533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1034290533
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.4026967123
Short name T2141
Test name
Test status
Simulation time 378885349 ps
CPU time 1.31 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206636 kb
Host smart-3ac7c6df-3f97-4031-a68a-1be87899b5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40269
67123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.4026967123
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.983185986
Short name T856
Test name
Test status
Simulation time 148931756 ps
CPU time 0.76 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:00 PM PDT 24
Peak memory 206640 kb
Host smart-767eaaba-c8a9-470c-8b82-8a367e7b7b82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98318
5986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.983185986
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.299816153
Short name T758
Test name
Test status
Simulation time 34504866 ps
CPU time 0.66 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206624 kb
Host smart-3b15e565-f8b8-4076-b375-dc34e6e2f16a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29981
6153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.299816153
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.494663708
Short name T1907
Test name
Test status
Simulation time 770934735 ps
CPU time 2.12 seconds
Started Jul 18 05:50:49 PM PDT 24
Finished Jul 18 05:51:08 PM PDT 24
Peak memory 206640 kb
Host smart-412fd75a-6c80-4282-8a43-ce89df155b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49466
3708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.494663708
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2020928445
Short name T404
Test name
Test status
Simulation time 173846703 ps
CPU time 1.72 seconds
Started Jul 18 05:50:40 PM PDT 24
Finished Jul 18 05:51:03 PM PDT 24
Peak memory 206720 kb
Host smart-7a1d6da2-7215-4962-a0d7-034541933352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20209
28445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2020928445
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.4084789858
Short name T2210
Test name
Test status
Simulation time 227258068 ps
CPU time 0.86 seconds
Started Jul 18 05:50:48 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206640 kb
Host smart-81b0bb2e-4a6f-4ff4-865e-3d19c0c3050d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40847
89858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.4084789858
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.1630096406
Short name T847
Test name
Test status
Simulation time 196345824 ps
CPU time 0.86 seconds
Started Jul 18 05:50:40 PM PDT 24
Finished Jul 18 05:51:02 PM PDT 24
Peak memory 206632 kb
Host smart-ae827dd5-bb35-49a0-8b36-a0218e0c37ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16300
96406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.1630096406
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.4138287716
Short name T149
Test name
Test status
Simulation time 268075883 ps
CPU time 0.89 seconds
Started Jul 18 05:50:48 PM PDT 24
Finished Jul 18 05:51:06 PM PDT 24
Peak memory 206620 kb
Host smart-9372a9c2-0974-48ab-951e-7fb86d81fc8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41382
87716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.4138287716
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2257590435
Short name T1159
Test name
Test status
Simulation time 5274542815 ps
CPU time 134 seconds
Started Jul 18 05:50:48 PM PDT 24
Finished Jul 18 05:53:19 PM PDT 24
Peak memory 206828 kb
Host smart-ce7bdc2c-aea3-4d77-8239-ef56e5edf35c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2257590435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2257590435
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.2392350696
Short name T867
Test name
Test status
Simulation time 11932573593 ps
CPU time 98.2 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:52:35 PM PDT 24
Peak memory 207084 kb
Host smart-05f5ec66-772f-412e-967c-a8af879d772a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23923
50696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.2392350696
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.378192880
Short name T445
Test name
Test status
Simulation time 264309996 ps
CPU time 1.02 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206628 kb
Host smart-6be9e272-1814-4eee-87f2-c39f3f78e325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37819
2880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.378192880
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1000878347
Short name T1791
Test name
Test status
Simulation time 23280945224 ps
CPU time 23.31 seconds
Started Jul 18 05:50:36 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206944 kb
Host smart-60607ab9-885f-43e9-affe-141095c69bb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10008
78347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1000878347
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2562385623
Short name T1778
Test name
Test status
Simulation time 3299591723 ps
CPU time 4.12 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:50:59 PM PDT 24
Peak memory 206684 kb
Host smart-89cf4fce-0722-4f13-9971-966f52fa6248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
85623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2562385623
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.2191977580
Short name T2469
Test name
Test status
Simulation time 8557128755 ps
CPU time 60.99 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:51:56 PM PDT 24
Peak memory 206856 kb
Host smart-7ea6e33a-7977-404c-a355-6f03848cb9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21919
77580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.2191977580
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.2873260935
Short name T2702
Test name
Test status
Simulation time 4357326558 ps
CPU time 40.3 seconds
Started Jul 18 05:50:36 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 207012 kb
Host smart-9e2cdf0d-83e0-4646-bef2-f2915f2ecc4c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2873260935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.2873260935
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1044032592
Short name T2642
Test name
Test status
Simulation time 240959805 ps
CPU time 0.97 seconds
Started Jul 18 05:50:48 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206792 kb
Host smart-c33cb9e0-d046-42e2-a234-96a1b895102c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1044032592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1044032592
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.969581408
Short name T636
Test name
Test status
Simulation time 196309040 ps
CPU time 0.86 seconds
Started Jul 18 05:50:26 PM PDT 24
Finished Jul 18 05:50:40 PM PDT 24
Peak memory 206616 kb
Host smart-4e56d27f-276c-4c35-a1cf-0e1043243411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96958
1408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.969581408
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1500947464
Short name T509
Test name
Test status
Simulation time 3772371116 ps
CPU time 25.9 seconds
Started Jul 18 05:50:35 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206884 kb
Host smart-f086ea04-3c66-4aef-bc65-a5c092b9e443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15009
47464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1500947464
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.2019308416
Short name T1523
Test name
Test status
Simulation time 4924971355 ps
CPU time 39.5 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:51:26 PM PDT 24
Peak memory 206808 kb
Host smart-f98265fb-9efe-4e6a-bb93-b8315a5f4ea4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2019308416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.2019308416
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2734998474
Short name T2008
Test name
Test status
Simulation time 157595370 ps
CPU time 0.77 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:45 PM PDT 24
Peak memory 206508 kb
Host smart-a5755f2b-fb70-48b8-b321-8c939f3f1e7e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2734998474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2734998474
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.4109346452
Short name T1165
Test name
Test status
Simulation time 177088885 ps
CPU time 0.78 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:49 PM PDT 24
Peak memory 206612 kb
Host smart-f1c6edea-1648-41bb-87b4-f85916360d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41093
46452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.4109346452
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.457929319
Short name T1894
Test name
Test status
Simulation time 204139394 ps
CPU time 0.87 seconds
Started Jul 18 05:50:27 PM PDT 24
Finished Jul 18 05:50:41 PM PDT 24
Peak memory 206632 kb
Host smart-db379c9c-7d94-41d3-bba7-e6ceffbd1a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45792
9319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.457929319
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.647955812
Short name T1290
Test name
Test status
Simulation time 226725872 ps
CPU time 0.88 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:51 PM PDT 24
Peak memory 206592 kb
Host smart-ff9e06ab-d9ac-4482-9ff0-2c005a943e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64795
5812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.647955812
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3088598572
Short name T2556
Test name
Test status
Simulation time 162948459 ps
CPU time 0.8 seconds
Started Jul 18 05:50:29 PM PDT 24
Finished Jul 18 05:50:46 PM PDT 24
Peak memory 206616 kb
Host smart-55175dda-c41b-4159-a801-a5aa2f700fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30885
98572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3088598572
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.1715919612
Short name T1414
Test name
Test status
Simulation time 157739585 ps
CPU time 0.77 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206648 kb
Host smart-510b1496-2ec6-4851-91fa-197e7cf6c7a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17159
19612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.1715919612
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.81604783
Short name T2009
Test name
Test status
Simulation time 154051207 ps
CPU time 0.79 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:48 PM PDT 24
Peak memory 206600 kb
Host smart-dfcea1a4-974e-4ac1-b1fd-175f00f27687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81604
783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.81604783
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.543892453
Short name T811
Test name
Test status
Simulation time 268972014 ps
CPU time 0.97 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:50:43 PM PDT 24
Peak memory 206580 kb
Host smart-75152fe5-1b67-492b-a51a-f317f1d1bc5f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=543892453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.543892453
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.987450223
Short name T185
Test name
Test status
Simulation time 199085586 ps
CPU time 0.82 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:50 PM PDT 24
Peak memory 206600 kb
Host smart-2e048124-7bc8-4f85-8c76-16726f2b520f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98745
0223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.987450223
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1614724744
Short name T2071
Test name
Test status
Simulation time 38448687 ps
CPU time 0.66 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:50:53 PM PDT 24
Peak memory 206628 kb
Host smart-fae18e86-795f-4fe5-a498-619f7367a5f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16147
24744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1614724744
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.1572804487
Short name T1242
Test name
Test status
Simulation time 6208241613 ps
CPU time 13.7 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:51:06 PM PDT 24
Peak memory 206912 kb
Host smart-39f633eb-d640-400c-b2ed-fe50e2374d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15728
04487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.1572804487
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3083791185
Short name T615
Test name
Test status
Simulation time 184294994 ps
CPU time 0.86 seconds
Started Jul 18 05:50:37 PM PDT 24
Finished Jul 18 05:50:59 PM PDT 24
Peak memory 206640 kb
Host smart-5ab1d728-a896-495e-90dd-a152befa0dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30837
91185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3083791185
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.3984090003
Short name T2747
Test name
Test status
Simulation time 196253964 ps
CPU time 0.83 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206636 kb
Host smart-d9135bb2-7892-4ed3-a0f0-236fb9c13ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39840
90003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.3984090003
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.478423786
Short name T678
Test name
Test status
Simulation time 190155783 ps
CPU time 0.82 seconds
Started Jul 18 05:50:44 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206640 kb
Host smart-3c4e1aac-dca6-46e4-af05-7e75288f71fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47842
3786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.478423786
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.2016354607
Short name T2619
Test name
Test status
Simulation time 179417585 ps
CPU time 0.83 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206620 kb
Host smart-00f9b6d9-bf9b-4d6a-9ae6-afc3da401433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20163
54607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.2016354607
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1555117635
Short name T1893
Test name
Test status
Simulation time 153756064 ps
CPU time 0.78 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206624 kb
Host smart-7423e495-edee-42ce-8e46-5c766d0d8d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15551
17635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1555117635
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.3052272313
Short name T1153
Test name
Test status
Simulation time 156179928 ps
CPU time 0.81 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206608 kb
Host smart-11b0da2a-15a6-478e-ba58-b782ae346522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
72313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.3052272313
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.2642686276
Short name T2584
Test name
Test status
Simulation time 188679100 ps
CPU time 0.77 seconds
Started Jul 18 05:50:32 PM PDT 24
Finished Jul 18 05:50:52 PM PDT 24
Peak memory 206640 kb
Host smart-97e375b7-93f3-4eba-96de-cb741ac3e481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26426
86276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.2642686276
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.3408666061
Short name T631
Test name
Test status
Simulation time 253873122 ps
CPU time 0.93 seconds
Started Jul 18 05:50:31 PM PDT 24
Finished Jul 18 05:50:51 PM PDT 24
Peak memory 206628 kb
Host smart-bd26d780-9e7e-4468-b0b0-8247c553b2d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34086
66061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.3408666061
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1283323364
Short name T2160
Test name
Test status
Simulation time 4636767103 ps
CPU time 31 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:51:25 PM PDT 24
Peak memory 206808 kb
Host smart-0cc3963f-bdcb-4649-a22c-2d96fe4aae8f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1283323364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1283323364
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2486358439
Short name T1895
Test name
Test status
Simulation time 161208314 ps
CPU time 0.8 seconds
Started Jul 18 05:50:36 PM PDT 24
Finished Jul 18 05:50:57 PM PDT 24
Peak memory 206588 kb
Host smart-600d7c11-2633-4193-abd0-6871302a975c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24863
58439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2486358439
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.2422677701
Short name T2433
Test name
Test status
Simulation time 172286472 ps
CPU time 0.83 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:00 PM PDT 24
Peak memory 206620 kb
Host smart-26d31ffd-b92d-4d01-bca6-0fa6c5e8ad13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24226
77701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.2422677701
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3642279552
Short name T2684
Test name
Test status
Simulation time 1040876962 ps
CPU time 2.11 seconds
Started Jul 18 05:50:33 PM PDT 24
Finished Jul 18 05:50:55 PM PDT 24
Peak memory 206796 kb
Host smart-c3c08405-e965-4add-893d-5d9e80677ae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36422
79552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3642279552
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1346135970
Short name T832
Test name
Test status
Simulation time 3115655703 ps
CPU time 79.8 seconds
Started Jul 18 05:50:28 PM PDT 24
Finished Jul 18 05:52:03 PM PDT 24
Peak memory 206972 kb
Host smart-a662ff8f-9d54-43a7-9e99-b5e8b333b28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13461
35970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1346135970
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.967682014
Short name T420
Test name
Test status
Simulation time 55263142 ps
CPU time 0.69 seconds
Started Jul 18 05:50:42 PM PDT 24
Finished Jul 18 05:51:03 PM PDT 24
Peak memory 206672 kb
Host smart-c9fe8ce7-1147-42dd-b060-8f0493090815
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=967682014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.967682014
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2725789018
Short name T866
Test name
Test status
Simulation time 3640611215 ps
CPU time 4.61 seconds
Started Jul 18 05:50:48 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206708 kb
Host smart-f19c5623-7d16-4285-af91-08d0f4d6154a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2725789018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.2725789018
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1610360157
Short name T1013
Test name
Test status
Simulation time 13362867543 ps
CPU time 11.93 seconds
Started Jul 18 05:50:49 PM PDT 24
Finished Jul 18 05:51:18 PM PDT 24
Peak memory 206860 kb
Host smart-dd676495-4871-436b-8abd-3500c39fd9e9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1610360157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1610360157
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.1459838117
Short name T528
Test name
Test status
Simulation time 23351621412 ps
CPU time 23.18 seconds
Started Jul 18 05:50:37 PM PDT 24
Finished Jul 18 05:51:22 PM PDT 24
Peak memory 206760 kb
Host smart-ae6d90c3-7f96-4e25-922b-3e7c64ac1109
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1459838117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.1459838117
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.3191229302
Short name T579
Test name
Test status
Simulation time 149765609 ps
CPU time 0.76 seconds
Started Jul 18 05:50:30 PM PDT 24
Finished Jul 18 05:50:47 PM PDT 24
Peak memory 206648 kb
Host smart-9b947638-cb50-43cf-83c8-6eb7c5a32fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31912
29302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.3191229302
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.301684787
Short name T1882
Test name
Test status
Simulation time 150209798 ps
CPU time 0.74 seconds
Started Jul 18 05:50:49 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206404 kb
Host smart-3706f2d2-88be-4b7a-be95-e75b8c5c371b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30168
4787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.301684787
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3316498654
Short name T1145
Test name
Test status
Simulation time 369647654 ps
CPU time 1.27 seconds
Started Jul 18 05:50:48 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206628 kb
Host smart-1030fe66-51f7-4805-8b85-e280f189a880
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33164
98654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3316498654
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3408795790
Short name T704
Test name
Test status
Simulation time 690437460 ps
CPU time 1.77 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:02 PM PDT 24
Peak memory 206800 kb
Host smart-cc07a4a7-beac-478a-b11a-d563ab93d873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
95790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3408795790
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.3888851632
Short name T2111
Test name
Test status
Simulation time 19542668340 ps
CPU time 38.58 seconds
Started Jul 18 05:50:52 PM PDT 24
Finished Jul 18 05:51:47 PM PDT 24
Peak memory 206620 kb
Host smart-e39d00d5-c3b0-43d5-9681-61d4bf0023e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38888
51632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.3888851632
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3442176192
Short name T1366
Test name
Test status
Simulation time 489743092 ps
CPU time 1.37 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206660 kb
Host smart-7c7da15e-34b6-4588-a64b-04f7c69461d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34421
76192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3442176192
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.609154840
Short name T483
Test name
Test status
Simulation time 151662718 ps
CPU time 0.75 seconds
Started Jul 18 05:50:44 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206652 kb
Host smart-7f05eef6-f268-4402-851e-dc61fa2231ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60915
4840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.609154840
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.2041251402
Short name T2525
Test name
Test status
Simulation time 48970336 ps
CPU time 0.67 seconds
Started Jul 18 05:50:42 PM PDT 24
Finished Jul 18 05:51:03 PM PDT 24
Peak memory 206648 kb
Host smart-75f7e58b-763b-4a19-9c6e-ed6c8f707eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20412
51402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.2041251402
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.159867903
Short name T1005
Test name
Test status
Simulation time 734387720 ps
CPU time 1.84 seconds
Started Jul 18 05:50:45 PM PDT 24
Finished Jul 18 05:51:06 PM PDT 24
Peak memory 206768 kb
Host smart-765cfd8c-13b3-44a7-b2b6-b23f8f8de490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15986
7903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.159867903
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.1920188917
Short name T177
Test name
Test status
Simulation time 179935746 ps
CPU time 2.14 seconds
Started Jul 18 05:50:55 PM PDT 24
Finished Jul 18 05:51:13 PM PDT 24
Peak memory 206788 kb
Host smart-c8a8c5dd-bedc-46ba-96a6-98ba3025bff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19201
88917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.1920188917
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.195199321
Short name T2126
Test name
Test status
Simulation time 179549092 ps
CPU time 0.9 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:00 PM PDT 24
Peak memory 206616 kb
Host smart-fd95b7f3-22cf-4e90-87be-b5d05cca896c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19519
9321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.195199321
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2885429047
Short name T561
Test name
Test status
Simulation time 196696586 ps
CPU time 0.8 seconds
Started Jul 18 05:50:49 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206816 kb
Host smart-3915d114-63c9-46f3-a600-8f1eb7704327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28854
29047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2885429047
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.1963693177
Short name T1478
Test name
Test status
Simulation time 244166880 ps
CPU time 1.01 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206808 kb
Host smart-473a1990-794c-432a-8c3c-194a92b66912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19636
93177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.1963693177
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.499481150
Short name T2637
Test name
Test status
Simulation time 5310149960 ps
CPU time 48.12 seconds
Started Jul 18 05:50:49 PM PDT 24
Finished Jul 18 05:51:54 PM PDT 24
Peak memory 207024 kb
Host smart-7789308f-f910-4c3e-9977-004e6ccde5b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=499481150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.499481150
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.3947963127
Short name T2176
Test name
Test status
Simulation time 11969538704 ps
CPU time 47.27 seconds
Started Jul 18 05:50:47 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206852 kb
Host smart-e66c3ccb-ac91-437a-aa42-e7dc2cdc7f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39479
63127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3947963127
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.3442962189
Short name T2113
Test name
Test status
Simulation time 222333003 ps
CPU time 0.93 seconds
Started Jul 18 05:50:52 PM PDT 24
Finished Jul 18 05:51:09 PM PDT 24
Peak memory 206420 kb
Host smart-c385b972-f487-4733-a0a3-21a0f9777df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34429
62189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.3442962189
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.4210947799
Short name T839
Test name
Test status
Simulation time 23283170214 ps
CPU time 21.8 seconds
Started Jul 18 05:50:56 PM PDT 24
Finished Jul 18 05:51:33 PM PDT 24
Peak memory 206356 kb
Host smart-303141d0-cc80-490a-9164-a028ffe597a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42109
47799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.4210947799
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2813863129
Short name T1697
Test name
Test status
Simulation time 3361082752 ps
CPU time 4.11 seconds
Started Jul 18 05:50:50 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206880 kb
Host smart-f5ec7f5b-0119-47d8-8614-24a52e2917ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28138
63129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2813863129
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1078612085
Short name T1732
Test name
Test status
Simulation time 6706978249 ps
CPU time 178.38 seconds
Started Jul 18 05:50:56 PM PDT 24
Finished Jul 18 05:54:09 PM PDT 24
Peak memory 206900 kb
Host smart-03fb2027-f7ef-4848-b524-2a7756f129ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10786
12085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1078612085
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.1728569464
Short name T1701
Test name
Test status
Simulation time 4377729585 ps
CPU time 28.42 seconds
Started Jul 18 05:50:56 PM PDT 24
Finished Jul 18 05:51:39 PM PDT 24
Peak memory 206884 kb
Host smart-f272115a-528f-44cd-92c5-e713b1188436
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1728569464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.1728569464
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.269443078
Short name T1205
Test name
Test status
Simulation time 264232637 ps
CPU time 0.96 seconds
Started Jul 18 05:50:53 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206636 kb
Host smart-4385ea0d-a206-4fde-9130-c010c5b82278
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=269443078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.269443078
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.3491390155
Short name T903
Test name
Test status
Simulation time 196077092 ps
CPU time 0.89 seconds
Started Jul 18 05:50:56 PM PDT 24
Finished Jul 18 05:51:12 PM PDT 24
Peak memory 206624 kb
Host smart-69db3546-3570-442b-a59c-29172eef572d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34913
90155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.3491390155
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2195583974
Short name T591
Test name
Test status
Simulation time 3732743805 ps
CPU time 29.21 seconds
Started Jul 18 05:50:53 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 206828 kb
Host smart-e07a7e08-89ae-4a5e-a716-6309750f163d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21955
83974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2195583974
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.3617152611
Short name T1564
Test name
Test status
Simulation time 5635656433 ps
CPU time 51.39 seconds
Started Jul 18 05:50:53 PM PDT 24
Finished Jul 18 05:52:00 PM PDT 24
Peak memory 206892 kb
Host smart-f2e8d218-2134-4015-a654-6c319078a9ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3617152611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.3617152611
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.733294040
Short name T2496
Test name
Test status
Simulation time 159372250 ps
CPU time 0.82 seconds
Started Jul 18 05:50:56 PM PDT 24
Finished Jul 18 05:51:12 PM PDT 24
Peak memory 206316 kb
Host smart-f9b4e60d-4839-4f24-840e-f35b14de1243
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=733294040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.733294040
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.1751685230
Short name T1673
Test name
Test status
Simulation time 158003054 ps
CPU time 0.78 seconds
Started Jul 18 05:50:54 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206636 kb
Host smart-58f0cec5-abc5-4edc-b448-12603263ddc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17516
85230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.1751685230
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.2939871615
Short name T141
Test name
Test status
Simulation time 237211252 ps
CPU time 0.89 seconds
Started Jul 18 05:50:56 PM PDT 24
Finished Jul 18 05:51:11 PM PDT 24
Peak memory 206628 kb
Host smart-73ccec01-3791-46d8-8e48-d30c8eec01b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29398
71615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.2939871615
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2518636787
Short name T1430
Test name
Test status
Simulation time 175199007 ps
CPU time 0.89 seconds
Started Jul 18 05:50:56 PM PDT 24
Finished Jul 18 05:51:12 PM PDT 24
Peak memory 206628 kb
Host smart-85cea87a-7191-41f9-aa3d-3fb1ef6d084e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25186
36787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2518636787
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.1919824141
Short name T1488
Test name
Test status
Simulation time 187776513 ps
CPU time 0.82 seconds
Started Jul 18 05:50:54 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206640 kb
Host smart-43513195-f4bd-414a-a64d-06128b517042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19198
24141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.1919824141
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.1790574129
Short name T1351
Test name
Test status
Simulation time 162818884 ps
CPU time 0.75 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:02 PM PDT 24
Peak memory 205736 kb
Host smart-deec7c88-187d-4c1d-a85d-e91d56897bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17905
74129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.1790574129
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.113771064
Short name T2063
Test name
Test status
Simulation time 214100864 ps
CPU time 0.82 seconds
Started Jul 18 05:50:53 PM PDT 24
Finished Jul 18 05:51:09 PM PDT 24
Peak memory 206640 kb
Host smart-3b4ffdd1-18ae-4447-ae0e-d49eef37698d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11377
1064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.113771064
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.292160809
Short name T1206
Test name
Test status
Simulation time 186208011 ps
CPU time 0.89 seconds
Started Jul 18 05:50:58 PM PDT 24
Finished Jul 18 05:51:14 PM PDT 24
Peak memory 206640 kb
Host smart-14aa4301-8a47-493a-a3a0-69bbe07684fb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=292160809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.292160809
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3487999935
Short name T1354
Test name
Test status
Simulation time 160408420 ps
CPU time 0.74 seconds
Started Jul 18 05:50:44 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206640 kb
Host smart-fa0df85c-76fb-41cd-9290-e35557a27ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34879
99935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3487999935
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3617570520
Short name T1350
Test name
Test status
Simulation time 82556840 ps
CPU time 0.73 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:00 PM PDT 24
Peak memory 206612 kb
Host smart-54231548-034d-437c-be61-9d410b04d4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36175
70520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3617570520
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.2489592873
Short name T1607
Test name
Test status
Simulation time 23111382295 ps
CPU time 53.04 seconds
Started Jul 18 05:50:54 PM PDT 24
Finished Jul 18 05:52:03 PM PDT 24
Peak memory 206924 kb
Host smart-b402bac6-450d-42fc-9485-3160bbb35c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24895
92873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.2489592873
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.467655584
Short name T1962
Test name
Test status
Simulation time 168036237 ps
CPU time 0.85 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206656 kb
Host smart-30b5fd5b-8190-47ce-8a54-b1a5a43ed86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46765
5584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.467655584
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3394174083
Short name T2183
Test name
Test status
Simulation time 258654890 ps
CPU time 0.91 seconds
Started Jul 18 05:50:44 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206648 kb
Host smart-3fda77d8-e819-4237-894a-d45af7e31d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33941
74083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3394174083
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.789860370
Short name T1329
Test name
Test status
Simulation time 175436471 ps
CPU time 0.81 seconds
Started Jul 18 05:50:54 PM PDT 24
Finished Jul 18 05:51:11 PM PDT 24
Peak memory 206652 kb
Host smart-60859aed-a69d-42ca-b5a3-76f4ce76185d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78986
0370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.789860370
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.1455326933
Short name T785
Test name
Test status
Simulation time 168654226 ps
CPU time 0.81 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206636 kb
Host smart-ee05a988-f80e-4583-8a1b-8a0d753d2c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14553
26933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.1455326933
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2999068056
Short name T1066
Test name
Test status
Simulation time 141739618 ps
CPU time 0.75 seconds
Started Jul 18 05:50:46 PM PDT 24
Finished Jul 18 05:51:05 PM PDT 24
Peak memory 206612 kb
Host smart-7fd6e9fb-795f-409d-a815-8d3e673c574d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29990
68056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2999068056
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1691336927
Short name T2678
Test name
Test status
Simulation time 177469457 ps
CPU time 0.77 seconds
Started Jul 18 05:50:40 PM PDT 24
Finished Jul 18 05:51:02 PM PDT 24
Peak memory 206624 kb
Host smart-1d5e430e-aea4-4519-8008-90ce02b4193e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16913
36927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1691336927
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3146567778
Short name T578
Test name
Test status
Simulation time 185721046 ps
CPU time 0.81 seconds
Started Jul 18 05:50:44 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206648 kb
Host smart-9d5577d5-05be-4fd4-814e-8c8924c23de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31465
67778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3146567778
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1550948978
Short name T1659
Test name
Test status
Simulation time 210703963 ps
CPU time 0.97 seconds
Started Jul 18 05:50:39 PM PDT 24
Finished Jul 18 05:51:01 PM PDT 24
Peak memory 206628 kb
Host smart-7192aa8f-43f9-4a7b-8de0-6bf14f93883b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15509
48978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1550948978
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.3272593365
Short name T158
Test name
Test status
Simulation time 4658651977 ps
CPU time 36 seconds
Started Jul 18 05:50:41 PM PDT 24
Finished Jul 18 05:51:38 PM PDT 24
Peak memory 206916 kb
Host smart-75b61032-d19f-41c6-ba30-486ae7df28b7
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3272593365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.3272593365
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.2980715725
Short name T1443
Test name
Test status
Simulation time 179041043 ps
CPU time 0.82 seconds
Started Jul 18 05:50:52 PM PDT 24
Finished Jul 18 05:51:09 PM PDT 24
Peak memory 206620 kb
Host smart-552d897d-afac-4ef5-92fe-1216f5c7b455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29807
15725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.2980715725
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.3803287113
Short name T419
Test name
Test status
Simulation time 173314197 ps
CPU time 0.75 seconds
Started Jul 18 05:50:54 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206640 kb
Host smart-a1c3ae0c-97fe-46fd-afe5-675ae7d1e6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38032
87113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.3803287113
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.2456766709
Short name T1785
Test name
Test status
Simulation time 199823439 ps
CPU time 0.83 seconds
Started Jul 18 05:50:49 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206672 kb
Host smart-35c2bf13-c105-4eb4-bfee-655a6c5b9214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24567
66709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.2456766709
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.2388863152
Short name T350
Test name
Test status
Simulation time 3292101967 ps
CPU time 92.87 seconds
Started Jul 18 05:50:53 PM PDT 24
Finished Jul 18 05:52:41 PM PDT 24
Peak memory 206852 kb
Host smart-e2dfff12-820f-42b1-83e2-efee66dcbf11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23888
63152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.2388863152
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3068388517
Short name T1539
Test name
Test status
Simulation time 45662783 ps
CPU time 0.68 seconds
Started Jul 18 05:51:02 PM PDT 24
Finished Jul 18 05:51:16 PM PDT 24
Peak memory 206680 kb
Host smart-bc631e20-d088-4ac2-ad31-aaeb540e2c9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3068388517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3068388517
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3901357213
Short name T7
Test name
Test status
Simulation time 3940461029 ps
CPU time 4.91 seconds
Started Jul 18 05:50:38 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206804 kb
Host smart-18bc787c-0f5a-470f-9e58-ebc9019c8cad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3901357213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3901357213
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.3412585916
Short name T2719
Test name
Test status
Simulation time 13377654825 ps
CPU time 13.66 seconds
Started Jul 18 05:50:51 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206748 kb
Host smart-9c688762-f1d6-4f96-85ed-fc5d1d3ad019
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3412585916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.3412585916
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.3275751359
Short name T2505
Test name
Test status
Simulation time 23431901794 ps
CPU time 26.03 seconds
Started Jul 18 05:50:53 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206760 kb
Host smart-468239ff-649a-480a-892b-83e118215518
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3275751359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.3275751359
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3019550308
Short name T1896
Test name
Test status
Simulation time 199931094 ps
CPU time 0.82 seconds
Started Jul 18 05:50:45 PM PDT 24
Finished Jul 18 05:51:05 PM PDT 24
Peak memory 206648 kb
Host smart-69d61690-aded-40f3-b66c-1b23e4d39039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30195
50308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3019550308
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.1803555268
Short name T909
Test name
Test status
Simulation time 179226992 ps
CPU time 0.83 seconds
Started Jul 18 05:50:45 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206620 kb
Host smart-5d38aa3d-3065-426f-a034-2268220c9776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18035
55268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.1803555268
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2705931381
Short name T1738
Test name
Test status
Simulation time 232124033 ps
CPU time 0.94 seconds
Started Jul 18 05:50:49 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206812 kb
Host smart-17a8a0fa-cd45-4524-93d9-3d14fe3ed764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
31381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2705931381
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.2137897959
Short name T2577
Test name
Test status
Simulation time 855835612 ps
CPU time 1.93 seconds
Started Jul 18 05:50:45 PM PDT 24
Finished Jul 18 05:51:06 PM PDT 24
Peak memory 206736 kb
Host smart-76180d7d-7c69-4105-a34e-659fe1358e21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21378
97959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.2137897959
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.595078854
Short name T975
Test name
Test status
Simulation time 16214345986 ps
CPU time 34.99 seconds
Started Jul 18 05:50:46 PM PDT 24
Finished Jul 18 05:51:39 PM PDT 24
Peak memory 206856 kb
Host smart-bbf9276c-a0e8-43c9-a346-c9dd9208fecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59507
8854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.595078854
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3853680806
Short name T1629
Test name
Test status
Simulation time 439176052 ps
CPU time 1.31 seconds
Started Jul 18 05:52:21 PM PDT 24
Finished Jul 18 05:52:37 PM PDT 24
Peak memory 206616 kb
Host smart-69524c40-8145-4a4b-9baf-b6667de01dbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
80806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3853680806
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2450055425
Short name T2056
Test name
Test status
Simulation time 168443827 ps
CPU time 0.83 seconds
Started Jul 18 05:50:41 PM PDT 24
Finished Jul 18 05:51:03 PM PDT 24
Peak memory 206648 kb
Host smart-1de6a9a7-3144-44ac-b6c2-06e22639bd69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24500
55425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2450055425
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.276707575
Short name T1858
Test name
Test status
Simulation time 39941990 ps
CPU time 0.71 seconds
Started Jul 18 05:50:44 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206624 kb
Host smart-fe22ae23-e36e-41f1-9c79-c6ac2b167b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27670
7575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.276707575
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.3363018507
Short name T1503
Test name
Test status
Simulation time 1084888209 ps
CPU time 2.28 seconds
Started Jul 18 05:50:53 PM PDT 24
Finished Jul 18 05:51:10 PM PDT 24
Peak memory 206764 kb
Host smart-8d47403d-c7bb-4e48-96c3-3f0530d5cc4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33630
18507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.3363018507
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.819581132
Short name T2682
Test name
Test status
Simulation time 285161860 ps
CPU time 1.65 seconds
Started Jul 18 05:50:42 PM PDT 24
Finished Jul 18 05:51:04 PM PDT 24
Peak memory 206796 kb
Host smart-0775aa01-8760-4b22-91e2-71a7faf737aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81958
1132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.819581132
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.551972868
Short name T2052
Test name
Test status
Simulation time 197312139 ps
CPU time 0.82 seconds
Started Jul 18 05:50:45 PM PDT 24
Finished Jul 18 05:51:05 PM PDT 24
Peak memory 206640 kb
Host smart-0b6412ec-ba6b-426e-8b5c-f44051328a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55197
2868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.551972868
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.2339867257
Short name T917
Test name
Test status
Simulation time 149581361 ps
CPU time 0.74 seconds
Started Jul 18 05:50:48 PM PDT 24
Finished Jul 18 05:51:07 PM PDT 24
Peak memory 206816 kb
Host smart-a24ede65-272d-43de-8c8c-8da1f2298f11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23398
67257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.2339867257
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2597831332
Short name T2166
Test name
Test status
Simulation time 151293443 ps
CPU time 0.83 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206604 kb
Host smart-2a24b630-62be-4611-a38e-020255c24097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25978
31332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2597831332
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3731777581
Short name T721
Test name
Test status
Simulation time 8819923503 ps
CPU time 25.44 seconds
Started Jul 18 05:51:17 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206844 kb
Host smart-f12ee7d3-03df-4380-8a16-a9234c7d821e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317
77581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3731777581
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.3638850301
Short name T2326
Test name
Test status
Simulation time 233249926 ps
CPU time 0.96 seconds
Started Jul 18 05:51:01 PM PDT 24
Finished Jul 18 05:51:16 PM PDT 24
Peak memory 206596 kb
Host smart-d1dbfacd-9a27-4eb2-a7e7-c5095424212c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
50301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.3638850301
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.3088814114
Short name T1802
Test name
Test status
Simulation time 23311516291 ps
CPU time 26.92 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:47 PM PDT 24
Peak memory 206776 kb
Host smart-064a1da6-7864-437f-a8f1-f7cba4f4b141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30888
14114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.3088814114
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.2931840666
Short name T2736
Test name
Test status
Simulation time 3345633359 ps
CPU time 3.89 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:25 PM PDT 24
Peak memory 206720 kb
Host smart-1552abef-c502-48f4-8dc1-94062d4770f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29318
40666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.2931840666
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.2939537745
Short name T1912
Test name
Test status
Simulation time 6550443910 ps
CPU time 46.23 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:52:05 PM PDT 24
Peak memory 206892 kb
Host smart-a29d89ae-8755-4dbb-9dac-c32ae8c627b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29395
37745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.2939537745
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1541379723
Short name T1077
Test name
Test status
Simulation time 5017179906 ps
CPU time 46.23 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:52:04 PM PDT 24
Peak memory 206860 kb
Host smart-909eeae6-56df-406d-8369-18db28c43ca0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1541379723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1541379723
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.4066502799
Short name T1762
Test name
Test status
Simulation time 234982964 ps
CPU time 0.87 seconds
Started Jul 18 05:51:01 PM PDT 24
Finished Jul 18 05:51:16 PM PDT 24
Peak memory 206640 kb
Host smart-ff340d92-e3bc-443d-8690-29838a359b73
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4066502799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.4066502799
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1095770711
Short name T1127
Test name
Test status
Simulation time 213435275 ps
CPU time 0.91 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206624 kb
Host smart-502bbd1d-5d5c-48a6-a538-e08bf2f088c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
70711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1095770711
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1946527155
Short name T327
Test name
Test status
Simulation time 6199648473 ps
CPU time 170.89 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:54:10 PM PDT 24
Peak memory 206820 kb
Host smart-e5da32a4-9dba-4a7a-b2a5-bcb21653c79c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19465
27155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1946527155
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1369626823
Short name T2179
Test name
Test status
Simulation time 5186271974 ps
CPU time 144.63 seconds
Started Jul 18 05:51:10 PM PDT 24
Finished Jul 18 05:53:48 PM PDT 24
Peak memory 206844 kb
Host smart-5f9ae90f-9c6e-44de-bf43-71eb5b1dd850
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1369626823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1369626823
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2639593936
Short name T2544
Test name
Test status
Simulation time 149322032 ps
CPU time 0.8 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206652 kb
Host smart-7f3fd905-0ab5-4e8b-b442-13009d3fb210
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2639593936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2639593936
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.1201681944
Short name T2091
Test name
Test status
Simulation time 153642680 ps
CPU time 0.77 seconds
Started Jul 18 05:51:03 PM PDT 24
Finished Jul 18 05:51:17 PM PDT 24
Peak memory 206636 kb
Host smart-68f8cc40-88e7-4f59-9d07-dfd750ddf104
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12016
81944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.1201681944
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3886930989
Short name T118
Test name
Test status
Simulation time 188897962 ps
CPU time 0.84 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206656 kb
Host smart-dcadca47-8967-4e58-81c0-3ef2c5f48aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38869
30989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3886930989
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2966320096
Short name T1984
Test name
Test status
Simulation time 206993186 ps
CPU time 0.87 seconds
Started Jul 18 05:51:01 PM PDT 24
Finished Jul 18 05:51:16 PM PDT 24
Peak memory 206628 kb
Host smart-91b44d06-7215-46aa-9ec1-bf9730b0d0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29663
20096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2966320096
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3448807820
Short name T1731
Test name
Test status
Simulation time 158297589 ps
CPU time 0.77 seconds
Started Jul 18 05:51:03 PM PDT 24
Finished Jul 18 05:51:17 PM PDT 24
Peak memory 206644 kb
Host smart-f635bbac-a7f3-494f-811e-a6784ebabf87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
07820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3448807820
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.1909023590
Short name T2072
Test name
Test status
Simulation time 171832475 ps
CPU time 0.78 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206656 kb
Host smart-86f27f42-6d9d-461d-b3df-603e13d769e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19090
23590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.1909023590
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.104696153
Short name T959
Test name
Test status
Simulation time 153232990 ps
CPU time 0.8 seconds
Started Jul 18 05:51:03 PM PDT 24
Finished Jul 18 05:51:17 PM PDT 24
Peak memory 206652 kb
Host smart-3973a770-e328-4611-a28c-91269da3ea24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10469
6153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.104696153
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3468665646
Short name T541
Test name
Test status
Simulation time 200023986 ps
CPU time 0.91 seconds
Started Jul 18 05:51:17 PM PDT 24
Finished Jul 18 05:51:30 PM PDT 24
Peak memory 206632 kb
Host smart-ab30f250-70d4-46fd-b57e-4b06146f12c2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3468665646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3468665646
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1202850673
Short name T2041
Test name
Test status
Simulation time 143794614 ps
CPU time 0.76 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206648 kb
Host smart-60f2054a-46a7-4f68-9366-ce9488b5efd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12028
50673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1202850673
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.1004618809
Short name T1751
Test name
Test status
Simulation time 31294017 ps
CPU time 0.68 seconds
Started Jul 18 05:51:20 PM PDT 24
Finished Jul 18 05:51:32 PM PDT 24
Peak memory 206624 kb
Host smart-bc24e79a-f1c1-495d-81f7-392b93783f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10046
18809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.1004618809
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.3393590153
Short name T1745
Test name
Test status
Simulation time 14033024017 ps
CPU time 29.19 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:47 PM PDT 24
Peak memory 206848 kb
Host smart-970cfac1-7c2a-4c10-b6c4-8dfbe2758992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33935
90153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.3393590153
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.855522725
Short name T736
Test name
Test status
Simulation time 192227916 ps
CPU time 0.89 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206652 kb
Host smart-354f38c6-fd73-4f15-a5ec-bcd20809cd66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85552
2725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.855522725
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.104310169
Short name T1198
Test name
Test status
Simulation time 235968820 ps
CPU time 0.88 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206656 kb
Host smart-6c0ae79c-7958-451b-b83a-c279129f36ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10431
0169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.104310169
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.689668830
Short name T1734
Test name
Test status
Simulation time 218814312 ps
CPU time 0.92 seconds
Started Jul 18 05:51:03 PM PDT 24
Finished Jul 18 05:51:17 PM PDT 24
Peak memory 206648 kb
Host smart-05319489-a783-4691-a000-92aa151ce794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68966
8830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.689668830
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2421965900
Short name T1763
Test name
Test status
Simulation time 138405197 ps
CPU time 0.77 seconds
Started Jul 18 05:51:04 PM PDT 24
Finished Jul 18 05:51:18 PM PDT 24
Peak memory 206616 kb
Host smart-c5bd1f5f-b6fc-4d32-9b36-a165cce398ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24219
65900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2421965900
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.880316840
Short name T577
Test name
Test status
Simulation time 155748235 ps
CPU time 0.76 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206632 kb
Host smart-8e9b7849-90be-410d-81a4-708f41f6daf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88031
6840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.880316840
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.632231841
Short name T2148
Test name
Test status
Simulation time 162578195 ps
CPU time 0.78 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206644 kb
Host smart-1fa51334-60bf-4583-ae4e-e5293d059ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63223
1841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.632231841
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2642154104
Short name T1686
Test name
Test status
Simulation time 233244616 ps
CPU time 0.92 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206660 kb
Host smart-46f9fb57-14f4-4284-b313-c5ad6ea7a795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26421
54104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2642154104
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.2906594050
Short name T2315
Test name
Test status
Simulation time 6515689284 ps
CPU time 185.02 seconds
Started Jul 18 05:51:04 PM PDT 24
Finished Jul 18 05:54:22 PM PDT 24
Peak memory 206832 kb
Host smart-addb604b-063e-4dc2-8c53-78ede6c4f31c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2906594050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.2906594050
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.3737795564
Short name T2411
Test name
Test status
Simulation time 176424322 ps
CPU time 0.84 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206640 kb
Host smart-f28579e2-f1de-4bf5-a8b8-849b68fef740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37377
95564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.3737795564
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2927912712
Short name T427
Test name
Test status
Simulation time 155719433 ps
CPU time 0.77 seconds
Started Jul 18 05:51:03 PM PDT 24
Finished Jul 18 05:51:17 PM PDT 24
Peak memory 206648 kb
Host smart-e491a571-4acb-458c-8ba9-3e5726c18a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29279
12712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2927912712
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.144494238
Short name T937
Test name
Test status
Simulation time 378938915 ps
CPU time 1.23 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206620 kb
Host smart-a79c1533-1ab0-41bc-b5e1-c8e42b539b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14449
4238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.144494238
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1034735213
Short name T556
Test name
Test status
Simulation time 3207522805 ps
CPU time 29.04 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:51 PM PDT 24
Peak memory 206864 kb
Host smart-e5bee3a1-3d17-4637-83fd-6ee54ab357ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10347
35213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1034735213
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.783404457
Short name T1856
Test name
Test status
Simulation time 34064937 ps
CPU time 0.67 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 205708 kb
Host smart-184d862d-e4c6-40bd-90ba-ac8f8b1a1c81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=783404457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.783404457
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.1310475622
Short name T461
Test name
Test status
Simulation time 3724934182 ps
CPU time 4.52 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:22 PM PDT 24
Peak memory 206992 kb
Host smart-2be9288d-6c0d-4a32-960f-792144101ca2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1310475622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.1310475622
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.882267612
Short name T1552
Test name
Test status
Simulation time 13337003941 ps
CPU time 11.63 seconds
Started Jul 18 05:51:04 PM PDT 24
Finished Jul 18 05:51:29 PM PDT 24
Peak memory 206856 kb
Host smart-be7e6068-8d3a-4a17-8521-7afe6fc854c2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=882267612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.882267612
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.1669537658
Short name T595
Test name
Test status
Simulation time 23343226739 ps
CPU time 29.14 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:50 PM PDT 24
Peak memory 206776 kb
Host smart-5ad9e111-9ea5-49dc-a9ec-a4ffe64504a5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1669537658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.1669537658
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.2662590979
Short name T2274
Test name
Test status
Simulation time 209850302 ps
CPU time 0.87 seconds
Started Jul 18 05:51:02 PM PDT 24
Finished Jul 18 05:51:16 PM PDT 24
Peak memory 206648 kb
Host smart-1a947676-7660-4242-a8fb-052d52d9d292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26625
90979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.2662590979
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3126578959
Short name T2474
Test name
Test status
Simulation time 159421950 ps
CPU time 0.8 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206632 kb
Host smart-8dafe65a-ac17-4c8f-8add-39aff98dd455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31265
78959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3126578959
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.756186394
Short name T1210
Test name
Test status
Simulation time 369693843 ps
CPU time 1.28 seconds
Started Jul 18 05:51:03 PM PDT 24
Finished Jul 18 05:51:17 PM PDT 24
Peak memory 206616 kb
Host smart-b372cd2b-1100-4dcd-85d3-9b6d6294a608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75618
6394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.756186394
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.4275033061
Short name T1615
Test name
Test status
Simulation time 373030156 ps
CPU time 1.23 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206604 kb
Host smart-4ea46f3d-6dd2-4db6-9786-f28c7f9ed0b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42750
33061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.4275033061
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.4172317834
Short name T641
Test name
Test status
Simulation time 22777201684 ps
CPU time 43.42 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:52:01 PM PDT 24
Peak memory 207048 kb
Host smart-169bdf20-c594-4218-b94b-a9f1b6ed88ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41723
17834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.4172317834
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3989719688
Short name T486
Test name
Test status
Simulation time 373821633 ps
CPU time 1.23 seconds
Started Jul 18 05:51:04 PM PDT 24
Finished Jul 18 05:51:18 PM PDT 24
Peak memory 206648 kb
Host smart-9592d91c-6848-468c-8fc0-fe3ab345dea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39897
19688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3989719688
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.2054122925
Short name T2283
Test name
Test status
Simulation time 142737942 ps
CPU time 0.76 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206624 kb
Host smart-64d4b90b-25c0-4b50-9ade-f91ff8e8e64d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20541
22925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.2054122925
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1260365438
Short name T1261
Test name
Test status
Simulation time 64069511 ps
CPU time 0.73 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206620 kb
Host smart-1750e175-e49d-4f5d-ad70-d16b1687c0c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12603
65438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1260365438
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3626500094
Short name T612
Test name
Test status
Simulation time 916291464 ps
CPU time 2.11 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:22 PM PDT 24
Peak memory 206780 kb
Host smart-381e8b35-4a91-4487-b047-85f83aad7530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36265
00094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3626500094
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1310610237
Short name T2099
Test name
Test status
Simulation time 227132237 ps
CPU time 1.63 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206740 kb
Host smart-9eca3890-0535-4089-81c3-dc0dc0d1cce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13106
10237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1310610237
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2316709093
Short name T1700
Test name
Test status
Simulation time 160272388 ps
CPU time 0.82 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206652 kb
Host smart-985c1902-ec4b-4762-8a01-098d55c0f4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
09093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2316709093
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3859507695
Short name T876
Test name
Test status
Simulation time 155086411 ps
CPU time 0.81 seconds
Started Jul 18 05:51:17 PM PDT 24
Finished Jul 18 05:51:30 PM PDT 24
Peak memory 206624 kb
Host smart-8f2ba39a-89bb-436e-bad0-91f9d7b50aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38595
07695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3859507695
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.3492105646
Short name T1737
Test name
Test status
Simulation time 259131667 ps
CPU time 0.93 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206660 kb
Host smart-a0310cc2-13c4-4c12-a021-eb23b7173b9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34921
05646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.3492105646
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.1794469000
Short name T2067
Test name
Test status
Simulation time 6366172862 ps
CPU time 187.55 seconds
Started Jul 18 05:51:03 PM PDT 24
Finished Jul 18 05:54:23 PM PDT 24
Peak memory 206856 kb
Host smart-d31c1fea-421f-460f-8112-6be1ef6e352e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1794469000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.1794469000
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1452416518
Short name T2259
Test name
Test status
Simulation time 169393358 ps
CPU time 0.8 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206636 kb
Host smart-52901697-f977-47b5-b02d-59c6e27b5791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14524
16518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1452416518
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2387812026
Short name T1094
Test name
Test status
Simulation time 23355172045 ps
CPU time 21.1 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:39 PM PDT 24
Peak memory 206776 kb
Host smart-9b4b6787-1283-49dd-8926-47efc1118b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23878
12026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2387812026
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.4131514277
Short name T513
Test name
Test status
Simulation time 3336720477 ps
CPU time 3.78 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:22 PM PDT 24
Peak memory 206688 kb
Host smart-16bc5b8a-6170-49d2-a21b-fcb34240d068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
14277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.4131514277
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2712631072
Short name T1938
Test name
Test status
Simulation time 10360938894 ps
CPU time 74.87 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:52:35 PM PDT 24
Peak memory 206912 kb
Host smart-e6c1420a-43ad-45df-82db-b73746a2f39b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126
31072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2712631072
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.1257829133
Short name T597
Test name
Test status
Simulation time 6281153227 ps
CPU time 44.02 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:52:03 PM PDT 24
Peak memory 206852 kb
Host smart-2eabeaee-028a-4254-8d38-84eeeb9f2a88
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1257829133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.1257829133
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3654051316
Short name T1184
Test name
Test status
Simulation time 243852875 ps
CPU time 0.96 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206632 kb
Host smart-c0b94519-d5b1-4701-8f0b-4a1fc2f90110
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3654051316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3654051316
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1791943224
Short name T1335
Test name
Test status
Simulation time 210572416 ps
CPU time 0.88 seconds
Started Jul 18 05:51:04 PM PDT 24
Finished Jul 18 05:51:18 PM PDT 24
Peak memory 206616 kb
Host smart-8cdd80ab-7e1b-4d2f-b7f8-14c5beeefebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17919
43224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1791943224
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.3405746996
Short name T1603
Test name
Test status
Simulation time 5391402383 ps
CPU time 46.31 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:52:08 PM PDT 24
Peak memory 206884 kb
Host smart-63a9ccdf-fa2c-4bef-b8e7-8ec75a638153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34057
46996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.3405746996
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.2927971443
Short name T658
Test name
Test status
Simulation time 4904813334 ps
CPU time 137.58 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:53:35 PM PDT 24
Peak memory 206816 kb
Host smart-a2b1c9c1-5136-4d6f-ae1d-e2d29fb3931d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2927971443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.2927971443
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3151839426
Short name T331
Test name
Test status
Simulation time 164018518 ps
CPU time 0.8 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206656 kb
Host smart-92637384-8a60-4667-b7a4-ad3939672a52
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3151839426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3151839426
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3275693723
Short name T358
Test name
Test status
Simulation time 148049673 ps
CPU time 0.77 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206804 kb
Host smart-bfe4795b-1f30-4f60-9419-3c7193423005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32756
93723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3275693723
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.572079204
Short name T120
Test name
Test status
Simulation time 160515741 ps
CPU time 0.79 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206640 kb
Host smart-e00e74bc-22a0-4679-be0d-84bcdd77437f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57207
9204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.572079204
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.290960035
Short name T1871
Test name
Test status
Simulation time 158231619 ps
CPU time 0.83 seconds
Started Jul 18 05:51:06 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206616 kb
Host smart-58af3ddb-748a-4ddd-a2d2-cc098a538670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
0035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.290960035
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.3258896788
Short name T989
Test name
Test status
Simulation time 255860097 ps
CPU time 0.86 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206612 kb
Host smart-9edbc7ea-9efd-49c8-b206-826b8998d016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32588
96788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.3258896788
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.27801750
Short name T2714
Test name
Test status
Simulation time 193349373 ps
CPU time 0.85 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:22 PM PDT 24
Peak memory 206636 kb
Host smart-910efebd-1db4-4dbb-aa1c-6eaa184367dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27801
750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.27801750
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.1074740180
Short name T2349
Test name
Test status
Simulation time 154528697 ps
CPU time 0.77 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:18 PM PDT 24
Peak memory 206648 kb
Host smart-ae8b04ce-2c46-4eda-82e4-213f7e9f23ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10747
40180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.1074740180
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2586592028
Short name T1464
Test name
Test status
Simulation time 210721759 ps
CPU time 1 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206632 kb
Host smart-84d07475-559e-4331-9c28-245687da4cab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2586592028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2586592028
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2170747009
Short name T1222
Test name
Test status
Simulation time 142236534 ps
CPU time 0.76 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206640 kb
Host smart-ba2dbb1b-ba7c-4428-be2f-11bc37995df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21707
47009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2170747009
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3123643933
Short name T30
Test name
Test status
Simulation time 48809511 ps
CPU time 0.7 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:22 PM PDT 24
Peak memory 206616 kb
Host smart-47676fbc-dd92-4070-888a-db1a70706009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31236
43933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3123643933
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3356250544
Short name T2236
Test name
Test status
Simulation time 7929110166 ps
CPU time 17.79 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:39 PM PDT 24
Peak memory 206924 kb
Host smart-5ec9fc78-906f-4551-9534-d23179720e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33562
50544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3356250544
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1326772707
Short name T1926
Test name
Test status
Simulation time 263217789 ps
CPU time 0.92 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206636 kb
Host smart-7c0171c9-6445-478a-bfc7-ba475ea2adb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13267
72707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1326772707
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1458022708
Short name T2639
Test name
Test status
Simulation time 242297531 ps
CPU time 0.93 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206648 kb
Host smart-702845c1-a1ff-4955-93db-ec63331d73cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14580
22708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1458022708
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.842142188
Short name T1599
Test name
Test status
Simulation time 183389771 ps
CPU time 0.82 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:20 PM PDT 24
Peak memory 206644 kb
Host smart-98ae41af-b8e9-4416-87bb-56958b64817a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84214
2188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.842142188
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.2092430956
Short name T2027
Test name
Test status
Simulation time 178741276 ps
CPU time 0.87 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206668 kb
Host smart-38b97a05-d894-46d5-91d0-e7459254d271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20924
30956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.2092430956
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.3981544427
Short name T2680
Test name
Test status
Simulation time 179029978 ps
CPU time 0.85 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206616 kb
Host smart-38b5925d-1c54-493f-8c5c-bbbcb0295a49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39815
44427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.3981544427
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.2569107739
Short name T1874
Test name
Test status
Simulation time 168001793 ps
CPU time 0.82 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206352 kb
Host smart-da9b78d7-ec9d-499f-b898-ebfb3129f358
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25691
07739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.2569107739
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2659908716
Short name T505
Test name
Test status
Simulation time 156079190 ps
CPU time 0.78 seconds
Started Jul 18 05:51:09 PM PDT 24
Finished Jul 18 05:51:23 PM PDT 24
Peak memory 206380 kb
Host smart-5524bfae-17a2-4de4-a683-0a8aa2f9480b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26599
08716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2659908716
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.640862166
Short name T2432
Test name
Test status
Simulation time 224353858 ps
CPU time 0.94 seconds
Started Jul 18 05:51:12 PM PDT 24
Finished Jul 18 05:51:25 PM PDT 24
Peak memory 206612 kb
Host smart-d74a1368-c770-4706-a635-2e4f64329a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64086
2166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.640862166
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1621849274
Short name T425
Test name
Test status
Simulation time 4113387980 ps
CPU time 114.87 seconds
Started Jul 18 05:51:12 PM PDT 24
Finished Jul 18 05:53:19 PM PDT 24
Peak memory 206892 kb
Host smart-ab2cc385-7ab9-4d41-b0b7-e263b22d7b44
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1621849274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1621849274
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.2803159434
Short name T145
Test name
Test status
Simulation time 171596032 ps
CPU time 0.87 seconds
Started Jul 18 05:51:08 PM PDT 24
Finished Jul 18 05:51:21 PM PDT 24
Peak memory 206612 kb
Host smart-a5485acb-4f89-415d-8496-8007b014dfdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28031
59434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.2803159434
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.33984627
Short name T2100
Test name
Test status
Simulation time 237756260 ps
CPU time 0.85 seconds
Started Jul 18 05:51:18 PM PDT 24
Finished Jul 18 05:51:31 PM PDT 24
Peak memory 206620 kb
Host smart-dda5eafa-bf0d-473a-b984-4c2ab9927a04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33984
627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.33984627
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.2244670917
Short name T2487
Test name
Test status
Simulation time 506554344 ps
CPU time 1.37 seconds
Started Jul 18 05:51:05 PM PDT 24
Finished Jul 18 05:51:19 PM PDT 24
Peak memory 206804 kb
Host smart-bc09b428-34d7-46d4-95b8-8109486ac970
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22446
70917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.2244670917
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1131498678
Short name T1946
Test name
Test status
Simulation time 7612243135 ps
CPU time 212.78 seconds
Started Jul 18 05:51:07 PM PDT 24
Finished Jul 18 05:54:52 PM PDT 24
Peak memory 205908 kb
Host smart-88dad074-91b5-4149-98f0-19182e12743a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11314
98678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1131498678
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.4035629860
Short name T2428
Test name
Test status
Simulation time 35612753 ps
CPU time 0.67 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206680 kb
Host smart-fb30ce64-b67f-4146-af7b-d262b2253fb2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4035629860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.4035629860
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.3785753007
Short name T8
Test name
Test status
Simulation time 3992218326 ps
CPU time 4.37 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:41 PM PDT 24
Peak memory 206768 kb
Host smart-a25451c9-6541-4e32-9322-38b8cafb08e1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3785753007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.3785753007
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1549889273
Short name T2503
Test name
Test status
Simulation time 13373111052 ps
CPU time 16.63 seconds
Started Jul 18 05:51:18 PM PDT 24
Finished Jul 18 05:51:46 PM PDT 24
Peak memory 206776 kb
Host smart-316aa66f-911a-4f6c-b92c-efe4d68f5d41
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1549889273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1549889273
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.3184039444
Short name T1889
Test name
Test status
Simulation time 23312630379 ps
CPU time 25.24 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:58 PM PDT 24
Peak memory 206752 kb
Host smart-8403e9c2-a60a-46e8-adec-5454c3354ac6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3184039444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.3184039444
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3780896898
Short name T2279
Test name
Test status
Simulation time 158281587 ps
CPU time 0.82 seconds
Started Jul 18 05:51:19 PM PDT 24
Finished Jul 18 05:51:31 PM PDT 24
Peak memory 206616 kb
Host smart-b1270992-ff33-4829-b5f6-ba2caac3754f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37808
96898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3780896898
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.5496246
Short name T2077
Test name
Test status
Simulation time 147082970 ps
CPU time 0.75 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 206612 kb
Host smart-93aabb03-a0b4-48cc-bee3-3b74971a32ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54962
46 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.5496246
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.4281237457
Short name T1260
Test name
Test status
Simulation time 180982317 ps
CPU time 0.85 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 205748 kb
Host smart-cd29b32b-d3f3-48a7-82a2-023261c79d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42812
37457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.4281237457
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.3063496525
Short name T1788
Test name
Test status
Simulation time 781804077 ps
CPU time 2 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206744 kb
Host smart-0787b5d1-de76-40cf-80eb-1a3a5b3ad9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30634
96525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.3063496525
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.365579221
Short name T584
Test name
Test status
Simulation time 7227877968 ps
CPU time 13.71 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206832 kb
Host smart-0a72fdce-9890-4bfd-9808-385f5dcc117a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36557
9221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.365579221
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1267042465
Short name T2276
Test name
Test status
Simulation time 413079002 ps
CPU time 1.45 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206008 kb
Host smart-a5ac53ad-78e2-4ccb-a14e-5d52a00d6500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
42465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1267042465
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.84358019
Short name T2110
Test name
Test status
Simulation time 159284604 ps
CPU time 0.78 seconds
Started Jul 18 05:51:20 PM PDT 24
Finished Jul 18 05:51:32 PM PDT 24
Peak memory 206616 kb
Host smart-4a326f31-dc7c-41ac-83ea-50f1ac785a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84358
019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.84358019
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.1943033390
Short name T2673
Test name
Test status
Simulation time 45225303 ps
CPU time 0.68 seconds
Started Jul 18 05:51:18 PM PDT 24
Finished Jul 18 05:51:30 PM PDT 24
Peak memory 206636 kb
Host smart-cdbc6c41-d2b4-4f67-a77d-2032a1ef24a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19430
33390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.1943033390
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3736982373
Short name T956
Test name
Test status
Simulation time 998209899 ps
CPU time 2.14 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206704 kb
Host smart-4bc2ced0-7afc-4e12-8aa9-2cf4813897a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37369
82373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3736982373
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.3752129691
Short name T808
Test name
Test status
Simulation time 270163659 ps
CPU time 1.7 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:42 PM PDT 24
Peak memory 206800 kb
Host smart-e3d484fd-d95f-42a6-8dd8-d2c655ec4215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37521
29691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.3752129691
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.1944290664
Short name T1916
Test name
Test status
Simulation time 182564741 ps
CPU time 0.82 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206444 kb
Host smart-8a3f6e2a-c1e1-43b0-874c-11386087e31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19442
90664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.1944290664
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.2543331188
Short name T801
Test name
Test status
Simulation time 163069012 ps
CPU time 0.8 seconds
Started Jul 18 05:51:17 PM PDT 24
Finished Jul 18 05:51:30 PM PDT 24
Peak memory 206656 kb
Host smart-ffc1cef7-4866-4761-8bcc-8b5161cdf579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25433
31188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.2543331188
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3503105640
Short name T1777
Test name
Test status
Simulation time 201250898 ps
CPU time 0.85 seconds
Started Jul 18 05:51:32 PM PDT 24
Finished Jul 18 05:51:46 PM PDT 24
Peak memory 206652 kb
Host smart-21897bd5-a44b-492f-a11a-62ee26947a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35031
05640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3503105640
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.2473020351
Short name T1818
Test name
Test status
Simulation time 5022268243 ps
CPU time 16.52 seconds
Started Jul 18 05:51:18 PM PDT 24
Finished Jul 18 05:51:46 PM PDT 24
Peak memory 206880 kb
Host smart-086a4b9d-c33a-42b0-b2f6-0572fb3f17a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24730
20351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.2473020351
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1345539810
Short name T1808
Test name
Test status
Simulation time 241175070 ps
CPU time 0.89 seconds
Started Jul 18 05:51:32 PM PDT 24
Finished Jul 18 05:51:47 PM PDT 24
Peak memory 206612 kb
Host smart-f10e1bae-6612-46b3-99aa-f23b79757b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13455
39810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1345539810
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.2944226050
Short name T1100
Test name
Test status
Simulation time 23307283645 ps
CPU time 25.5 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:52:00 PM PDT 24
Peak memory 206772 kb
Host smart-5634011b-f76b-499d-817f-c05366c79e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442
26050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.2944226050
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.3552271866
Short name T2151
Test name
Test status
Simulation time 3302866405 ps
CPU time 3.75 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:44 PM PDT 24
Peak memory 206684 kb
Host smart-b42e9f43-59bb-4bf4-bb4c-4942e3dffea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35522
71866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.3552271866
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2169004739
Short name T91
Test name
Test status
Simulation time 6214761070 ps
CPU time 42.91 seconds
Started Jul 18 05:51:20 PM PDT 24
Finished Jul 18 05:52:15 PM PDT 24
Peak memory 206880 kb
Host smart-f59095a6-062b-4a18-9b7d-9913545bc425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21690
04739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2169004739
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.3882709628
Short name T1279
Test name
Test status
Simulation time 6971937485 ps
CPU time 52.43 seconds
Started Jul 18 05:51:20 PM PDT 24
Finished Jul 18 05:52:24 PM PDT 24
Peak memory 206908 kb
Host smart-1d200bf5-02c5-410f-a56f-0b27fad579df
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3882709628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.3882709628
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1436115340
Short name T772
Test name
Test status
Simulation time 265090446 ps
CPU time 0.97 seconds
Started Jul 18 05:51:18 PM PDT 24
Finished Jul 18 05:51:30 PM PDT 24
Peak memory 206648 kb
Host smart-e0327e18-fe32-41e0-ad33-7056554f3505
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1436115340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1436115340
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.3397007204
Short name T1349
Test name
Test status
Simulation time 192212986 ps
CPU time 0.86 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:33 PM PDT 24
Peak memory 206628 kb
Host smart-44c7179f-f12f-4530-a9fb-b3b903e51b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33970
07204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.3397007204
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.4185893022
Short name T522
Test name
Test status
Simulation time 6512227673 ps
CPU time 47.55 seconds
Started Jul 18 05:51:19 PM PDT 24
Finished Jul 18 05:52:18 PM PDT 24
Peak memory 206808 kb
Host smart-e4088c86-4583-4546-b07c-d9f0ebe9e094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41858
93022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.4185893022
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.57969757
Short name T2241
Test name
Test status
Simulation time 7589511158 ps
CPU time 72.4 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:52:52 PM PDT 24
Peak memory 206912 kb
Host smart-a5559ae8-7680-48b0-a526-5b2931601c9d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=57969757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.57969757
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1963177818
Short name T1588
Test name
Test status
Simulation time 151052509 ps
CPU time 0.87 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:33 PM PDT 24
Peak memory 206648 kb
Host smart-bd7e3880-ab54-4a68-875c-a0aa93719a87
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1963177818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1963177818
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.1153966866
Short name T2333
Test name
Test status
Simulation time 153698992 ps
CPU time 0.8 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:33 PM PDT 24
Peak memory 206632 kb
Host smart-baaa6656-d754-49e3-9bd1-4000356bb888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11539
66866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.1153966866
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1917364243
Short name T121
Test name
Test status
Simulation time 200830167 ps
CPU time 0.87 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:41 PM PDT 24
Peak memory 206620 kb
Host smart-7da0a25e-9bb6-4667-b2ac-7c5035e61b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19173
64243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1917364243
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.163611432
Short name T474
Test name
Test status
Simulation time 173073240 ps
CPU time 0.78 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206632 kb
Host smart-9e209a46-2e81-4c79-8886-26f817643a07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16361
1432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.163611432
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.4271368688
Short name T1069
Test name
Test status
Simulation time 191033699 ps
CPU time 0.83 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:33 PM PDT 24
Peak memory 206580 kb
Host smart-857b67ed-8d6e-4bb4-bd3f-398a1ba2c98a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42713
68688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.4271368688
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.1376099240
Short name T601
Test name
Test status
Simulation time 170326630 ps
CPU time 0.79 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206136 kb
Host smart-93c37593-255f-41e2-9a8c-b97331ba9857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13760
99240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.1376099240
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.803067165
Short name T712
Test name
Test status
Simulation time 153966526 ps
CPU time 0.83 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206388 kb
Host smart-72d11fe1-dec9-4e8b-a408-e173f6e9b3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80306
7165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.803067165
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3637717272
Short name T794
Test name
Test status
Simulation time 219622343 ps
CPU time 0.95 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206656 kb
Host smart-a8f93b31-1d08-4a93-ae1a-2e7fcf3ac85f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3637717272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3637717272
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3194660080
Short name T2358
Test name
Test status
Simulation time 175216459 ps
CPU time 0.81 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206644 kb
Host smart-b9eac429-f53c-4441-968b-01671d28dfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31946
60080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3194660080
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.2988535195
Short name T33
Test name
Test status
Simulation time 61654155 ps
CPU time 0.68 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206644 kb
Host smart-3ac3ceb2-8344-4de7-8e2c-875b4df28eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29885
35195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.2988535195
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3293730532
Short name T230
Test name
Test status
Simulation time 9376701955 ps
CPU time 22.85 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:52:00 PM PDT 24
Peak memory 215140 kb
Host smart-164d5fbd-6975-405f-b34d-985e954bfa1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32937
30532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3293730532
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.4173877082
Short name T621
Test name
Test status
Simulation time 167906243 ps
CPU time 0.82 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206640 kb
Host smart-cde88b41-ea9f-429b-8ab5-2033b9b537bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41738
77082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.4173877082
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.2509290966
Short name T1566
Test name
Test status
Simulation time 196818929 ps
CPU time 0.83 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 206668 kb
Host smart-1cd10394-14b6-4680-abcb-91777146e14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25092
90966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.2509290966
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.723197987
Short name T2169
Test name
Test status
Simulation time 170682567 ps
CPU time 0.87 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206656 kb
Host smart-1e23945d-710d-46b5-ab00-52268618620d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72319
7987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.723197987
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1954748815
Short name T2064
Test name
Test status
Simulation time 163478023 ps
CPU time 0.8 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:33 PM PDT 24
Peak memory 206632 kb
Host smart-7a57278c-e202-40cd-9802-1a17e5825d46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19547
48815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1954748815
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.729641581
Short name T2205
Test name
Test status
Simulation time 185715170 ps
CPU time 0.82 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206652 kb
Host smart-2e2100ac-fe2b-459b-ae3e-40f6588dc279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72964
1581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.729641581
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2407296119
Short name T114
Test name
Test status
Simulation time 153023897 ps
CPU time 0.75 seconds
Started Jul 18 05:51:20 PM PDT 24
Finished Jul 18 05:51:32 PM PDT 24
Peak memory 206612 kb
Host smart-2e5e0973-655b-434f-8c89-f391e5239d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24072
96119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2407296119
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.4246911539
Short name T2462
Test name
Test status
Simulation time 185791975 ps
CPU time 0.8 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:41 PM PDT 24
Peak memory 206636 kb
Host smart-d37f6015-7c4c-42d0-8e45-37c8e708d14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42469
11539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.4246911539
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1007927369
Short name T502
Test name
Test status
Simulation time 261091255 ps
CPU time 0.98 seconds
Started Jul 18 05:51:20 PM PDT 24
Finished Jul 18 05:51:32 PM PDT 24
Peak memory 206612 kb
Host smart-74974f3d-47fa-4eac-84a2-810172a55f0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10079
27369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1007927369
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.3561403916
Short name T473
Test name
Test status
Simulation time 3583344722 ps
CPU time 97.62 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:53:17 PM PDT 24
Peak memory 206860 kb
Host smart-1826b054-3629-448c-b665-e7093f65ba93
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3561403916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.3561403916
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2851115721
Short name T912
Test name
Test status
Simulation time 175716284 ps
CPU time 0.81 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206620 kb
Host smart-3e903932-501c-475e-b0e6-8d7838f61e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
15721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2851115721
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.537215352
Short name T2263
Test name
Test status
Simulation time 230678525 ps
CPU time 0.89 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:42 PM PDT 24
Peak memory 206616 kb
Host smart-f9fb447e-28a5-4db8-a7c4-8aea51f8e524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53721
5352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.537215352
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3561012725
Short name T82
Test name
Test status
Simulation time 1214461684 ps
CPU time 2.45 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:38 PM PDT 24
Peak memory 206816 kb
Host smart-0e53c235-19b6-4f85-b27e-8378338489ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35610
12725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3561012725
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.4166741674
Short name T1278
Test name
Test status
Simulation time 3235232894 ps
CPU time 24.62 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206860 kb
Host smart-104f45fa-bf2e-4832-826e-4a8718f487e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41667
41674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.4166741674
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.753386310
Short name T2475
Test name
Test status
Simulation time 38439056 ps
CPU time 0.65 seconds
Started Jul 18 05:51:32 PM PDT 24
Finished Jul 18 05:51:46 PM PDT 24
Peak memory 206652 kb
Host smart-1fa6f0a7-b0d1-4996-9dc0-4d14fd198fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=753386310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.753386310
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.4206012386
Short name T833
Test name
Test status
Simulation time 4113562019 ps
CPU time 4.73 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 206716 kb
Host smart-ca1aad77-9125-4d50-9120-8107a223ed7f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4206012386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.4206012386
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.3962333971
Short name T1961
Test name
Test status
Simulation time 13333739425 ps
CPU time 13.49 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:47 PM PDT 24
Peak memory 206740 kb
Host smart-2f73c068-d231-44e6-85f2-bc26eebd14f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3962333971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.3962333971
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1079216199
Short name T1150
Test name
Test status
Simulation time 23297368818 ps
CPU time 21.71 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206888 kb
Host smart-dddbf772-0dc7-48f4-a98c-2c9d0a17ec92
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1079216199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1079216199
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.2266934329
Short name T371
Test name
Test status
Simulation time 150921721 ps
CPU time 0.76 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206648 kb
Host smart-bc43b938-a3f3-45bb-a7fd-0fb68a35f650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22669
34329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.2266934329
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.2433306006
Short name T2555
Test name
Test status
Simulation time 140786324 ps
CPU time 0.84 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206600 kb
Host smart-0b2cf1d7-09e5-42d8-8d80-adcafc3f2a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24333
06006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.2433306006
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.2502909858
Short name T1507
Test name
Test status
Simulation time 314063858 ps
CPU time 1.06 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:42 PM PDT 24
Peak memory 206644 kb
Host smart-11e531fc-ef6b-48d7-8f3c-1b575760f03d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25029
09858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.2502909858
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.2365509357
Short name T770
Test name
Test status
Simulation time 606847205 ps
CPU time 1.58 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:42 PM PDT 24
Peak memory 206656 kb
Host smart-287b1b52-dfc7-4732-b207-0f2a0bb06773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23655
09357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.2365509357
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.2177769349
Short name T2512
Test name
Test status
Simulation time 10321687924 ps
CPU time 18.77 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:51:56 PM PDT 24
Peak memory 206828 kb
Host smart-a2060188-94b0-45c7-957f-28f6fb923498
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21777
69349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.2177769349
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1981457557
Short name T1945
Test name
Test status
Simulation time 281814705 ps
CPU time 1.11 seconds
Started Jul 18 05:51:28 PM PDT 24
Finished Jul 18 05:51:42 PM PDT 24
Peak memory 206648 kb
Host smart-a91d5d56-abe9-4bf4-bb3d-0b807c73a508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19814
57557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1981457557
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.3172001928
Short name T729
Test name
Test status
Simulation time 150571572 ps
CPU time 0.78 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206632 kb
Host smart-7f2895ea-e737-438f-8eaf-1f895b5a495e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31720
01928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.3172001928
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.2047998339
Short name T1525
Test name
Test status
Simulation time 34828980 ps
CPU time 0.64 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:51:38 PM PDT 24
Peak memory 206608 kb
Host smart-08f24b91-03bc-4fcd-8815-44ffb70e6ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20479
98339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.2047998339
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.709391561
Short name T737
Test name
Test status
Simulation time 731393136 ps
CPU time 1.83 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:42 PM PDT 24
Peak memory 206700 kb
Host smart-187e3af9-a7e1-4ae3-8d03-ebca1fab29f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70939
1561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.709391561
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2954232821
Short name T1244
Test name
Test status
Simulation time 385165632 ps
CPU time 2.15 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206744 kb
Host smart-e7c03060-c7bb-485a-b168-58d0a832f1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29542
32821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2954232821
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.78335185
Short name T1891
Test name
Test status
Simulation time 203885862 ps
CPU time 0.88 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206640 kb
Host smart-2aa1a5bf-c02e-497b-b70b-45083005c7b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78335
185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.78335185
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1741889291
Short name T2217
Test name
Test status
Simulation time 151715570 ps
CPU time 0.78 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206652 kb
Host smart-e7500c67-818b-42c4-9d27-91632a09bc00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17418
89291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1741889291
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.2471993640
Short name T1851
Test name
Test status
Simulation time 215152693 ps
CPU time 0.87 seconds
Started Jul 18 05:51:29 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206652 kb
Host smart-08dd0a37-2b61-41ce-8f99-8c36430050dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24719
93640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.2471993640
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.729799863
Short name T1493
Test name
Test status
Simulation time 5108830595 ps
CPU time 15.02 seconds
Started Jul 18 05:51:21 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206884 kb
Host smart-715deb07-a7e8-4e50-bc45-db4f5df5946c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72979
9863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.729799863
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.3768037219
Short name T27
Test name
Test status
Simulation time 178086033 ps
CPU time 0.82 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206636 kb
Host smart-4060ea45-e928-4365-8218-41cce09c3c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37680
37219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.3768037219
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.760225855
Short name T511
Test name
Test status
Simulation time 23405299068 ps
CPU time 23.93 seconds
Started Jul 18 05:51:31 PM PDT 24
Finished Jul 18 05:52:09 PM PDT 24
Peak memory 206020 kb
Host smart-ce54f796-b278-4183-af70-2f8b8303151a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76022
5855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.760225855
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3904043848
Short name T1742
Test name
Test status
Simulation time 3293300092 ps
CPU time 4.06 seconds
Started Jul 18 05:51:30 PM PDT 24
Finished Jul 18 05:51:49 PM PDT 24
Peak memory 206720 kb
Host smart-78c9f4ef-1503-4073-944a-d97d06d5d883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39040
43848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3904043848
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.3038634730
Short name T2382
Test name
Test status
Simulation time 10673053977 ps
CPU time 308.47 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:56:44 PM PDT 24
Peak memory 206912 kb
Host smart-f3a5cb91-4bec-4e39-98c3-d60d3ed46396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30386
34730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.3038634730
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3658590503
Short name T1782
Test name
Test status
Simulation time 4581399768 ps
CPU time 127.63 seconds
Started Jul 18 05:51:31 PM PDT 24
Finished Jul 18 05:53:53 PM PDT 24
Peak memory 206848 kb
Host smart-7cc77f70-846d-460b-b785-4ce6d53efa8f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3658590503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3658590503
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.4100378550
Short name T2452
Test name
Test status
Simulation time 236194217 ps
CPU time 0.88 seconds
Started Jul 18 05:51:32 PM PDT 24
Finished Jul 18 05:51:47 PM PDT 24
Peak memory 206652 kb
Host smart-977702ec-52e0-4fe9-82e9-add64f873465
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4100378550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.4100378550
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1925536922
Short name T1029
Test name
Test status
Simulation time 201111101 ps
CPU time 0.89 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206632 kb
Host smart-6ad64525-b0c3-4284-bf41-31bc61fa8d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19255
36922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1925536922
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.4037545888
Short name T583
Test name
Test status
Simulation time 5647666443 ps
CPU time 51.14 seconds
Started Jul 18 05:51:33 PM PDT 24
Finished Jul 18 05:52:38 PM PDT 24
Peak memory 206904 kb
Host smart-6f01a790-b47b-4e4a-a713-2f952c4c87e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40375
45888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.4037545888
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1628307703
Short name T1713
Test name
Test status
Simulation time 4854223025 ps
CPU time 125.45 seconds
Started Jul 18 05:51:32 PM PDT 24
Finished Jul 18 05:53:59 PM PDT 24
Peak memory 206828 kb
Host smart-0d977359-bc88-4169-a464-12c6d377ab8c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1628307703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1628307703
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3325305607
Short name T1573
Test name
Test status
Simulation time 154102454 ps
CPU time 0.75 seconds
Started Jul 18 05:51:34 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206636 kb
Host smart-5a3f52c7-8011-4104-8464-49fbc0c2beca
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3325305607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3325305607
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.1872067160
Short name T1117
Test name
Test status
Simulation time 158659895 ps
CPU time 0.76 seconds
Started Jul 18 05:51:34 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206628 kb
Host smart-7b63955e-82f9-4554-8a6c-e52938f55f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18720
67160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.1872067160
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.3340240943
Short name T2213
Test name
Test status
Simulation time 187799341 ps
CPU time 0.82 seconds
Started Jul 18 05:51:34 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206508 kb
Host smart-95c2fc3f-55fd-4991-9796-8070227bb11f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33402
40943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.3340240943
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.4045157625
Short name T79
Test name
Test status
Simulation time 261918754 ps
CPU time 0.93 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206120 kb
Host smart-8c8d1a5b-1b13-4a55-be25-b3a35d8ffa41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40451
57625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.4045157625
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.1806482794
Short name T836
Test name
Test status
Simulation time 172896174 ps
CPU time 0.81 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206636 kb
Host smart-9b013dcc-be72-4904-ad68-981ef3a53331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18064
82794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.1806482794
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.3642451259
Short name T1514
Test name
Test status
Simulation time 196656246 ps
CPU time 0.88 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206616 kb
Host smart-7459d66a-45d4-446e-90f4-a7220d300a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36424
51259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.3642451259
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.1343956960
Short name T1915
Test name
Test status
Simulation time 157753529 ps
CPU time 0.8 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206624 kb
Host smart-8088dad4-f390-41e1-85a0-431e18730764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13439
56960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.1343956960
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.993940155
Short name T498
Test name
Test status
Simulation time 246332742 ps
CPU time 0.94 seconds
Started Jul 18 05:51:34 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206224 kb
Host smart-e1fb1b21-6026-4b38-9455-e469047c5dde
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=993940155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.993940155
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.4090017741
Short name T1527
Test name
Test status
Simulation time 138127174 ps
CPU time 0.85 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 205996 kb
Host smart-41f4964e-3a4d-422d-9094-7ce23662bab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40900
17741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.4090017741
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2955776279
Short name T742
Test name
Test status
Simulation time 31201810 ps
CPU time 0.62 seconds
Started Jul 18 05:51:34 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206632 kb
Host smart-041cea45-efe5-45b5-8a7d-bb00a8960333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29557
76279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2955776279
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.1569532415
Short name T2196
Test name
Test status
Simulation time 13078598036 ps
CPU time 30.32 seconds
Started Jul 18 05:51:34 PM PDT 24
Finished Jul 18 05:52:17 PM PDT 24
Peak memory 206908 kb
Host smart-20cf02dc-8ba0-4c7e-89fc-e311ccddbff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15695
32415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.1569532415
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.610137519
Short name T1157
Test name
Test status
Simulation time 176108482 ps
CPU time 0.94 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206640 kb
Host smart-fe770f9c-f5a0-4d8a-a055-92ab4725ca8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61013
7519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.610137519
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.3363063881
Short name T1910
Test name
Test status
Simulation time 223395402 ps
CPU time 0.88 seconds
Started Jul 18 05:51:23 PM PDT 24
Finished Jul 18 05:51:35 PM PDT 24
Peak memory 206640 kb
Host smart-0e227051-d18e-4e9b-be4b-fdf4a234c866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33630
63881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.3363063881
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.3240645648
Short name T1408
Test name
Test status
Simulation time 162619625 ps
CPU time 0.85 seconds
Started Jul 18 05:51:28 PM PDT 24
Finished Jul 18 05:51:43 PM PDT 24
Peak memory 206660 kb
Host smart-0ea81168-4c5f-4cfa-88b2-7615733fc644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32406
45648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.3240645648
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1492435675
Short name T465
Test name
Test status
Simulation time 217045480 ps
CPU time 0.82 seconds
Started Jul 18 05:51:35 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206632 kb
Host smart-83c9c8d5-054f-49f7-9d6b-7775e150701d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14924
35675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1492435675
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.1186009559
Short name T1303
Test name
Test status
Simulation time 149272288 ps
CPU time 0.74 seconds
Started Jul 18 05:51:34 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206328 kb
Host smart-b9d5aa9d-dc8b-40e2-85d4-f38772daf3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11860
09559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.1186009559
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.388011340
Short name T1952
Test name
Test status
Simulation time 146431467 ps
CPU time 0.82 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 206636 kb
Host smart-c9685e4e-4ab5-45a8-ae47-9e7d6a06eee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38801
1340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.388011340
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2066739749
Short name T1900
Test name
Test status
Simulation time 151703552 ps
CPU time 0.83 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 206652 kb
Host smart-896acdc3-9c34-414b-b5e7-7a82dcd0f56b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20667
39749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2066739749
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.4292189312
Short name T1087
Test name
Test status
Simulation time 283573727 ps
CPU time 0.91 seconds
Started Jul 18 05:51:33 PM PDT 24
Finished Jul 18 05:51:48 PM PDT 24
Peak memory 206628 kb
Host smart-bca795ec-db56-4a0d-8bd4-40829fb790cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42921
89312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.4292189312
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3653894695
Short name T2266
Test name
Test status
Simulation time 7110610213 ps
CPU time 66.74 seconds
Started Jul 18 05:51:29 PM PDT 24
Finished Jul 18 05:52:49 PM PDT 24
Peak memory 206880 kb
Host smart-810af101-a605-4b07-9c4f-fc4029c26063
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3653894695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3653894695
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4087574422
Short name T2456
Test name
Test status
Simulation time 182110542 ps
CPU time 0.85 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:37 PM PDT 24
Peak memory 206632 kb
Host smart-8d0397e9-d9bb-453b-af84-0cb8269c7593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40875
74422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4087574422
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.1677102609
Short name T381
Test name
Test status
Simulation time 177620984 ps
CPU time 0.79 seconds
Started Jul 18 05:51:28 PM PDT 24
Finished Jul 18 05:51:44 PM PDT 24
Peak memory 206032 kb
Host smart-648b2c84-7bb9-42c6-904a-02de0dac1e15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16771
02609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.1677102609
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1701976337
Short name T2668
Test name
Test status
Simulation time 1144988718 ps
CPU time 2.18 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206576 kb
Host smart-d838a865-a1ab-4294-bfaf-ea5d142dffd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
76337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1701976337
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1284445918
Short name T2399
Test name
Test status
Simulation time 4586323395 ps
CPU time 130.98 seconds
Started Jul 18 05:51:28 PM PDT 24
Finished Jul 18 05:53:54 PM PDT 24
Peak memory 206164 kb
Host smart-6e953681-37a9-47d8-b99c-65f949d56558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12844
45918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1284445918
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.4205253635
Short name T180
Test name
Test status
Simulation time 107784226 ps
CPU time 0.72 seconds
Started Jul 18 05:51:37 PM PDT 24
Finished Jul 18 05:51:50 PM PDT 24
Peak memory 206704 kb
Host smart-1d3aaec3-06aa-41e6-b3bd-9b61ad6291e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4205253635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.4205253635
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.111995756
Short name T1166
Test name
Test status
Simulation time 3567734191 ps
CPU time 4.29 seconds
Started Jul 18 05:51:26 PM PDT 24
Finished Jul 18 05:51:43 PM PDT 24
Peak memory 206692 kb
Host smart-87a980b7-a3e7-4c66-8a56-10264309b575
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=111995756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.111995756
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.1320843682
Short name T1035
Test name
Test status
Simulation time 13415277396 ps
CPU time 12 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:51:49 PM PDT 24
Peak memory 206924 kb
Host smart-bb23c21d-d29a-4863-8ea0-9628a4526160
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1320843682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.1320843682
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.661889354
Short name T2337
Test name
Test status
Simulation time 23336322446 ps
CPU time 22.85 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:52:04 PM PDT 24
Peak memory 206772 kb
Host smart-a47c8128-373e-4a29-8971-cb59c7a758c2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=661889354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.661889354
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3696066074
Short name T1312
Test name
Test status
Simulation time 147214589 ps
CPU time 0.77 seconds
Started Jul 18 05:51:22 PM PDT 24
Finished Jul 18 05:51:34 PM PDT 24
Peak memory 206660 kb
Host smart-37a50971-254d-4d09-a89e-911286cb5b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36960
66074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3696066074
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.1290466244
Short name T2515
Test name
Test status
Simulation time 150914996 ps
CPU time 0.79 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:41 PM PDT 24
Peak memory 206648 kb
Host smart-09db0885-936e-4417-b9c5-320f0a323ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12904
66244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.1290466244
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.72065443
Short name T1922
Test name
Test status
Simulation time 367442894 ps
CPU time 1.2 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:51:39 PM PDT 24
Peak memory 206608 kb
Host smart-674c078d-8f20-4578-93a3-07089150513b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72065
443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.72065443
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3367439202
Short name T806
Test name
Test status
Simulation time 1177433863 ps
CPU time 2.84 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:51:40 PM PDT 24
Peak memory 206788 kb
Host smart-b7871be0-1e3b-4523-8660-7df64526141c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33674
39202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3367439202
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.3554396048
Short name T2222
Test name
Test status
Simulation time 22869277069 ps
CPU time 42.99 seconds
Started Jul 18 05:51:25 PM PDT 24
Finished Jul 18 05:52:20 PM PDT 24
Peak memory 206884 kb
Host smart-f7a21d28-d853-4bab-8070-c5e33439e184
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35543
96048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.3554396048
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.3121349465
Short name T1015
Test name
Test status
Simulation time 469497984 ps
CPU time 1.58 seconds
Started Jul 18 05:51:29 PM PDT 24
Finished Jul 18 05:51:45 PM PDT 24
Peak memory 206556 kb
Host smart-505f35fa-5b20-488a-8860-148487615da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31213
49465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.3121349465
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3079513226
Short name T2209
Test name
Test status
Simulation time 162726086 ps
CPU time 0.81 seconds
Started Jul 18 05:51:27 PM PDT 24
Finished Jul 18 05:51:41 PM PDT 24
Peak memory 206620 kb
Host smart-298af600-4d9a-46fa-82b0-fb5f747fcd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30795
13226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3079513226
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.79819488
Short name T1168
Test name
Test status
Simulation time 38774407 ps
CPU time 0.69 seconds
Started Jul 18 05:51:29 PM PDT 24
Finished Jul 18 05:51:43 PM PDT 24
Peak memory 206640 kb
Host smart-05f1514d-1c0e-4bc6-8fcd-cb398aba96e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79819
488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.79819488
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2223518981
Short name T1511
Test name
Test status
Simulation time 740825277 ps
CPU time 1.91 seconds
Started Jul 18 05:51:29 PM PDT 24
Finished Jul 18 05:51:45 PM PDT 24
Peak memory 206664 kb
Host smart-b54783e0-0965-48af-81cb-845874177119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22235
18981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2223518981
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.619413352
Short name T2255
Test name
Test status
Simulation time 168258390 ps
CPU time 1.56 seconds
Started Jul 18 05:51:31 PM PDT 24
Finished Jul 18 05:51:46 PM PDT 24
Peak memory 206080 kb
Host smart-e3ad23ad-a98a-40a3-b678-55acb1e0054b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61941
3352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.619413352
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.2088876785
Short name T1155
Test name
Test status
Simulation time 196429078 ps
CPU time 0.86 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:54 PM PDT 24
Peak memory 206664 kb
Host smart-18068ae1-86a7-4abe-b3b5-d25fa74d9b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20888
76785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.2088876785
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.188896405
Short name T981
Test name
Test status
Simulation time 142880453 ps
CPU time 0.76 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206592 kb
Host smart-a13ee7b2-e27f-4d3f-a9e5-4bdfa5d628e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18889
6405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.188896405
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.1656685666
Short name T432
Test name
Test status
Simulation time 199086142 ps
CPU time 0.84 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:51:51 PM PDT 24
Peak memory 206648 kb
Host smart-aa8a6200-b2b7-4da3-90c7-c876e8e570d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16566
85666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.1656685666
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2812366317
Short name T1096
Test name
Test status
Simulation time 9716582736 ps
CPU time 269.69 seconds
Started Jul 18 05:51:33 PM PDT 24
Finished Jul 18 05:56:16 PM PDT 24
Peak memory 206936 kb
Host smart-2ddc8e99-e44b-4ada-9641-15c514d48ea6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2812366317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2812366317
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.2568255465
Short name T1397
Test name
Test status
Simulation time 12514532135 ps
CPU time 37.47 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:52:28 PM PDT 24
Peak memory 206864 kb
Host smart-ae7a2c52-ec18-4a56-a7f3-d905f8a70d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25682
55465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.2568255465
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3604587122
Short name T1670
Test name
Test status
Simulation time 191320104 ps
CPU time 0.78 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:51:51 PM PDT 24
Peak memory 206612 kb
Host smart-11012542-10f6-4843-b8e9-4e447fb0ed4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36045
87122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3604587122
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.708842342
Short name T625
Test name
Test status
Simulation time 23310020787 ps
CPU time 21.67 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:52:19 PM PDT 24
Peak memory 206720 kb
Host smart-9cce72d4-4523-4265-a5e6-1e16e05dd5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70884
2342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.708842342
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.3041017102
Short name T2040
Test name
Test status
Simulation time 3334365680 ps
CPU time 3.92 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:51:54 PM PDT 24
Peak memory 206704 kb
Host smart-4bd862a7-1598-488d-bde5-1a39ab4b24d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30410
17102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.3041017102
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.869080139
Short name T710
Test name
Test status
Simulation time 8857546405 ps
CPU time 62.45 seconds
Started Jul 18 05:51:53 PM PDT 24
Finished Jul 18 05:53:03 PM PDT 24
Peak memory 206916 kb
Host smart-ecf46e03-6fcd-4e60-9a77-84cf6e370732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86908
0139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.869080139
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3327417062
Short name T695
Test name
Test status
Simulation time 4251335655 ps
CPU time 117.71 seconds
Started Jul 18 05:51:46 PM PDT 24
Finished Jul 18 05:53:54 PM PDT 24
Peak memory 206848 kb
Host smart-98f28390-591e-4aef-9bf5-bd5b9432685c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3327417062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3327417062
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1015202083
Short name T590
Test name
Test status
Simulation time 236132141 ps
CPU time 0.97 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:54 PM PDT 24
Peak memory 206672 kb
Host smart-5977bfbd-7ed7-4406-8dd9-5af8a0dfd7f7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1015202083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1015202083
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.211464978
Short name T1316
Test name
Test status
Simulation time 241536865 ps
CPU time 0.88 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206668 kb
Host smart-e4d10cee-20a6-45a0-a544-40a2fb7d6b34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21146
4978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.211464978
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.271695238
Short name T330
Test name
Test status
Simulation time 2993326430 ps
CPU time 82.85 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:53:13 PM PDT 24
Peak memory 206848 kb
Host smart-61341af1-7fa0-41e4-b8e0-a342c56bd995
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27169
5238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.271695238
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.4107991801
Short name T2516
Test name
Test status
Simulation time 4784177971 ps
CPU time 45.44 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:52:37 PM PDT 24
Peak memory 206864 kb
Host smart-a9e18d57-f64e-4c32-a589-8df1fddacbc3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4107991801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.4107991801
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.183971970
Short name T521
Test name
Test status
Simulation time 151472680 ps
CPU time 0.76 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:53 PM PDT 24
Peak memory 206628 kb
Host smart-2f55bd26-5a94-4746-b62c-4a2d3426678c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=183971970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.183971970
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.4216710293
Short name T746
Test name
Test status
Simulation time 153695832 ps
CPU time 0.82 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206644 kb
Host smart-ffdc7434-8658-4802-aa29-36a4251dc33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42167
10293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.4216710293
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1584514693
Short name T133
Test name
Test status
Simulation time 279371964 ps
CPU time 0.95 seconds
Started Jul 18 05:51:45 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206636 kb
Host smart-beb40272-a043-4cee-a538-685d1dd553cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15845
14693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1584514693
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3944952463
Short name T1630
Test name
Test status
Simulation time 185797057 ps
CPU time 0.87 seconds
Started Jul 18 05:51:43 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206648 kb
Host smart-e804f727-e28e-4e16-8533-183a465c3e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39449
52463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3944952463
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3845025929
Short name T1520
Test name
Test status
Simulation time 172594039 ps
CPU time 0.82 seconds
Started Jul 18 05:51:43 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206648 kb
Host smart-38c1bdb0-ce73-4621-9a40-979594fbc278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38450
25929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3845025929
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.794245337
Short name T1796
Test name
Test status
Simulation time 166182323 ps
CPU time 0.79 seconds
Started Jul 18 05:51:51 PM PDT 24
Finished Jul 18 05:52:00 PM PDT 24
Peak memory 206636 kb
Host smart-52bb9379-3df0-4498-8ff6-a75cc83ee6f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79424
5337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.794245337
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.3929761803
Short name T943
Test name
Test status
Simulation time 180066364 ps
CPU time 0.8 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:51:50 PM PDT 24
Peak memory 206656 kb
Host smart-7dad220b-50bf-4fd5-ac5d-c18fb99129a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39297
61803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.3929761803
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.2454107314
Short name T1404
Test name
Test status
Simulation time 238689523 ps
CPU time 0.95 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:53 PM PDT 24
Peak memory 206368 kb
Host smart-e5ca3ac2-4caf-4e5b-91a5-0c3c13188271
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2454107314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.2454107314
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2681681804
Short name T1189
Test name
Test status
Simulation time 138037622 ps
CPU time 0.77 seconds
Started Jul 18 05:51:58 PM PDT 24
Finished Jul 18 05:52:08 PM PDT 24
Peak memory 206608 kb
Host smart-edf06f94-be8c-40e4-9395-23a9a872fa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26816
81804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2681681804
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.663292303
Short name T25
Test name
Test status
Simulation time 41652807 ps
CPU time 0.65 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:51:51 PM PDT 24
Peak memory 206608 kb
Host smart-8bb985a7-caa5-4270-aa8e-823719c029b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66329
2303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.663292303
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1267423109
Short name T2230
Test name
Test status
Simulation time 9635000091 ps
CPU time 20.52 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:52:11 PM PDT 24
Peak memory 206876 kb
Host smart-68375871-ea58-4925-b131-075a33e4856c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12674
23109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1267423109
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.1328353281
Short name T1869
Test name
Test status
Simulation time 211148981 ps
CPU time 0.86 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:51:51 PM PDT 24
Peak memory 206660 kb
Host smart-08ab2900-9cb5-4dfe-8cab-089faaa5692c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13283
53281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.1328353281
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.451015651
Short name T1535
Test name
Test status
Simulation time 225014844 ps
CPU time 0.91 seconds
Started Jul 18 05:51:43 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206620 kb
Host smart-2e3f087a-8538-4ab1-9fb3-263755d9711a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45101
5651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.451015651
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1254276563
Short name T2011
Test name
Test status
Simulation time 181838894 ps
CPU time 0.83 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:51:51 PM PDT 24
Peak memory 206648 kb
Host smart-c6ef40f2-9397-4549-8b65-88a6a38a5acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12542
76563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1254276563
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.1422755337
Short name T333
Test name
Test status
Simulation time 147144902 ps
CPU time 0.77 seconds
Started Jul 18 05:51:42 PM PDT 24
Finished Jul 18 05:51:58 PM PDT 24
Peak memory 206636 kb
Host smart-5716e61a-7172-4740-a4db-d9f50b3e68f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14227
55337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.1422755337
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.1267343424
Short name T824
Test name
Test status
Simulation time 205098077 ps
CPU time 0.85 seconds
Started Jul 18 05:51:45 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206616 kb
Host smart-bf12cc11-fffa-40ee-8b2b-fe135e2ef270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12673
43424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.1267343424
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.2193329739
Short name T2224
Test name
Test status
Simulation time 159441404 ps
CPU time 0.74 seconds
Started Jul 18 05:51:49 PM PDT 24
Finished Jul 18 05:52:04 PM PDT 24
Peak memory 206644 kb
Host smart-c434d838-5819-44a8-9eae-3581c5d79489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21933
29739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.2193329739
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.4029924043
Short name T2066
Test name
Test status
Simulation time 155707531 ps
CPU time 0.76 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206600 kb
Host smart-fca462eb-abbb-45f3-926e-e0d42c57ee2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40299
24043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.4029924043
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2479385268
Short name T931
Test name
Test status
Simulation time 215172242 ps
CPU time 0.97 seconds
Started Jul 18 05:51:47 PM PDT 24
Finished Jul 18 05:51:58 PM PDT 24
Peak memory 206628 kb
Host smart-46e2566f-7aa6-454f-b871-5205aa1ddb30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24793
85268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2479385268
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3791640957
Short name T1969
Test name
Test status
Simulation time 6330464645 ps
CPU time 58.21 seconds
Started Jul 18 05:51:37 PM PDT 24
Finished Jul 18 05:52:47 PM PDT 24
Peak memory 206860 kb
Host smart-c84b3166-b52a-4837-890f-bb8cfdf4a0af
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3791640957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3791640957
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3700195758
Short name T2665
Test name
Test status
Simulation time 182193963 ps
CPU time 0.87 seconds
Started Jul 18 05:51:45 PM PDT 24
Finished Jul 18 05:51:56 PM PDT 24
Peak memory 206636 kb
Host smart-7afec60b-f508-4ebe-bf2a-82d089c038da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37001
95758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3700195758
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2181571518
Short name T489
Test name
Test status
Simulation time 239185429 ps
CPU time 0.92 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206644 kb
Host smart-302be6a1-4f7a-4021-b745-d55c95b228ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21815
71518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2181571518
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.1543088681
Short name T761
Test name
Test status
Simulation time 876526319 ps
CPU time 2.03 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206756 kb
Host smart-c0d4a0b8-816c-4f43-a760-d26ed0954d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15430
88681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.1543088681
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1880922146
Short name T377
Test name
Test status
Simulation time 6206993878 ps
CPU time 167.44 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:54:39 PM PDT 24
Peak memory 206608 kb
Host smart-796a4cb0-3251-4e21-9f82-49b2cd5fed56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18809
22146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1880922146
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_timeout_missing_host_handshake.1005037180
Short name T2304
Test name
Test status
Simulation time 140793761 ps
CPU time 0.8 seconds
Started Jul 18 05:51:24 PM PDT 24
Finished Jul 18 05:51:36 PM PDT 24
Peak memory 206632 kb
Host smart-af1d227d-e1ac-4f74-93b2-25b2b07909fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10050
37180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_timeout_missing_host_handshake.1005037180
Directory /workspace/48.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.1903364107
Short name T2598
Test name
Test status
Simulation time 44101756 ps
CPU time 0.72 seconds
Started Jul 18 05:51:53 PM PDT 24
Finished Jul 18 05:52:02 PM PDT 24
Peak memory 206688 kb
Host smart-1f0082c4-8568-4f41-9069-11e912845756
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1903364107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.1903364107
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.3158623341
Short name T1479
Test name
Test status
Simulation time 3894240468 ps
CPU time 4.73 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206720 kb
Host smart-6feb8a76-c7fb-4ef8-ab28-2434cd16a239
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3158623341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.3158623341
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.2056589042
Short name T13
Test name
Test status
Simulation time 13341642272 ps
CPU time 14.12 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:52:06 PM PDT 24
Peak memory 206888 kb
Host smart-eba0cdfc-e80f-4169-83c9-fa64cce5d709
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2056589042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.2056589042
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.220802677
Short name T1748
Test name
Test status
Simulation time 23355194861 ps
CPU time 22.49 seconds
Started Jul 18 05:51:50 PM PDT 24
Finished Jul 18 05:52:22 PM PDT 24
Peak memory 206844 kb
Host smart-1746b4e0-09b2-4c7e-b005-9f94a08a0893
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=220802677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.220802677
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.4058779435
Short name T389
Test name
Test status
Simulation time 162640700 ps
CPU time 0.8 seconds
Started Jul 18 05:51:45 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206648 kb
Host smart-fa566b40-2007-4ea8-be71-4648d380d322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40587
79435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.4058779435
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2998220352
Short name T60
Test name
Test status
Simulation time 167649371 ps
CPU time 0.78 seconds
Started Jul 18 05:51:44 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206652 kb
Host smart-a235c10e-047d-4100-874e-7b6a4af26103
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29982
20352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2998220352
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.1008070005
Short name T635
Test name
Test status
Simulation time 554508024 ps
CPU time 1.73 seconds
Started Jul 18 05:51:54 PM PDT 24
Finished Jul 18 05:52:04 PM PDT 24
Peak memory 206612 kb
Host smart-f1752093-e3ed-4abe-83c3-d6bfd73c8451
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10080
70005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.1008070005
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.452783163
Short name T1596
Test name
Test status
Simulation time 852385439 ps
CPU time 1.84 seconds
Started Jul 18 05:51:42 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206720 kb
Host smart-a54d6206-b455-4f2d-81d0-d3797f592075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45278
3163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.452783163
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.530197698
Short name T702
Test name
Test status
Simulation time 9258433288 ps
CPU time 17.59 seconds
Started Jul 18 05:51:37 PM PDT 24
Finished Jul 18 05:52:06 PM PDT 24
Peak memory 207020 kb
Host smart-a2a1be1a-3754-4dc2-b272-5ac01a837f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53019
7698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.530197698
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.2486370942
Short name T570
Test name
Test status
Simulation time 348198729 ps
CPU time 1.17 seconds
Started Jul 18 05:51:42 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206648 kb
Host smart-5cde8a16-907d-4431-96a2-23fc9c09cda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24863
70942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.2486370942
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.4176237566
Short name T1766
Test name
Test status
Simulation time 145081621 ps
CPU time 0.81 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206652 kb
Host smart-172069a3-d2d3-41b8-82f0-a4377cbf0beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41762
37566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.4176237566
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3545808055
Short name T1319
Test name
Test status
Simulation time 38697406 ps
CPU time 0.71 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206628 kb
Host smart-76883624-469d-4827-9637-0319924e31d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35458
08055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3545808055
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.362153472
Short name T2268
Test name
Test status
Simulation time 822896874 ps
CPU time 1.89 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206740 kb
Host smart-0e0b141c-642d-4d5a-ad32-0ebd4754dd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36215
3472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.362153472
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.2922612252
Short name T2024
Test name
Test status
Simulation time 282751086 ps
CPU time 1.68 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:53 PM PDT 24
Peak memory 206788 kb
Host smart-bdd33d35-7793-4c8f-9cd6-b6a89308cc34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29226
12252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.2922612252
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.42327939
Short name T539
Test name
Test status
Simulation time 284489998 ps
CPU time 0.94 seconds
Started Jul 18 05:51:46 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206660 kb
Host smart-9cd2d67c-e883-48b0-9e4f-01c6f7d734fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42327
939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.42327939
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.601545538
Short name T1208
Test name
Test status
Simulation time 155307153 ps
CPU time 0.78 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206644 kb
Host smart-f4299bf0-26c6-459f-9fd0-52ba38152779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60154
5538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.601545538
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.1802573306
Short name T316
Test name
Test status
Simulation time 208031205 ps
CPU time 0.92 seconds
Started Jul 18 05:51:39 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206656 kb
Host smart-ca1588c1-a621-4f20-8f65-cd1eb896aad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18025
73306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.1802573306
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.112717892
Short name T1144
Test name
Test status
Simulation time 7961953129 ps
CPU time 228.42 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:55:41 PM PDT 24
Peak memory 206876 kb
Host smart-dbf624ab-2b71-4ddf-ae4d-57f29064f02e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=112717892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.112717892
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.2980930912
Short name T1412
Test name
Test status
Simulation time 13444079233 ps
CPU time 49.42 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:52:42 PM PDT 24
Peak memory 206892 kb
Host smart-0cf1167e-5d96-4d25-98ec-67488d9682f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29809
30912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.2980930912
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.2892656483
Short name T2627
Test name
Test status
Simulation time 209187694 ps
CPU time 0.86 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:53 PM PDT 24
Peak memory 206656 kb
Host smart-ba1843cb-68cc-42dc-a9bf-063e643d8e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28926
56483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.2892656483
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1747648431
Short name T1804
Test name
Test status
Simulation time 23347387739 ps
CPU time 27.02 seconds
Started Jul 18 05:51:42 PM PDT 24
Finished Jul 18 05:52:20 PM PDT 24
Peak memory 206756 kb
Host smart-3bd328eb-859b-469f-8db9-924002116da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17476
48431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1747648431
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2151506854
Short name T1861
Test name
Test status
Simulation time 3283161850 ps
CPU time 3.76 seconds
Started Jul 18 05:51:43 PM PDT 24
Finished Jul 18 05:51:57 PM PDT 24
Peak memory 206688 kb
Host smart-30749410-fe55-457b-95b3-04e68dcc6f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21515
06854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2151506854
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.2431403924
Short name T2163
Test name
Test status
Simulation time 8271732947 ps
CPU time 56.71 seconds
Started Jul 18 05:51:52 PM PDT 24
Finished Jul 18 05:52:57 PM PDT 24
Peak memory 206940 kb
Host smart-0143d9c4-009c-4bb7-8769-1e4f2531dc90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24314
03924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.2431403924
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.2193477845
Short name T1247
Test name
Test status
Simulation time 4459768688 ps
CPU time 30.74 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:52:23 PM PDT 24
Peak memory 206792 kb
Host smart-b8707f89-718a-4e64-8df4-5ee16bbfbd43
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2193477845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.2193477845
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.822389487
Short name T1044
Test name
Test status
Simulation time 239915894 ps
CPU time 0.95 seconds
Started Jul 18 05:51:54 PM PDT 24
Finished Jul 18 05:52:04 PM PDT 24
Peak memory 206468 kb
Host smart-5e141189-1e98-451d-bcc5-a8815bbfe7b5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=822389487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.822389487
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.2140453212
Short name T296
Test name
Test status
Simulation time 188150163 ps
CPU time 0.85 seconds
Started Jul 18 05:51:59 PM PDT 24
Finished Jul 18 05:52:09 PM PDT 24
Peak memory 206616 kb
Host smart-c0700085-7504-4868-a7b7-cfce9b1a87d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21404
53212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.2140453212
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.870790232
Short name T2510
Test name
Test status
Simulation time 6179345310 ps
CPU time 171.34 seconds
Started Jul 18 05:51:54 PM PDT 24
Finished Jul 18 05:54:54 PM PDT 24
Peak memory 206748 kb
Host smart-e5ee6955-6239-4ccf-8f43-5189f80eda67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87079
0232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.870790232
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.305737063
Short name T2285
Test name
Test status
Simulation time 3516796361 ps
CPU time 96.51 seconds
Started Jul 18 05:51:38 PM PDT 24
Finished Jul 18 05:53:26 PM PDT 24
Peak memory 206868 kb
Host smart-a41e6a2c-a37b-40cd-8a22-895572cd026e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=305737063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.305737063
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.4085999274
Short name T2659
Test name
Test status
Simulation time 184080429 ps
CPU time 0.79 seconds
Started Jul 18 05:51:55 PM PDT 24
Finished Jul 18 05:52:04 PM PDT 24
Peak memory 206620 kb
Host smart-6d2e073c-f0cf-419b-a2ff-cda21834e924
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4085999274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.4085999274
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3532427451
Short name T444
Test name
Test status
Simulation time 144170067 ps
CPU time 0.74 seconds
Started Jul 18 05:51:56 PM PDT 24
Finished Jul 18 05:52:06 PM PDT 24
Peak memory 206640 kb
Host smart-3c821aca-bc35-4913-9c5f-f0fb971b8cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35324
27451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3532427451
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2088394684
Short name T2340
Test name
Test status
Simulation time 158202151 ps
CPU time 0.78 seconds
Started Jul 18 05:51:57 PM PDT 24
Finished Jul 18 05:52:07 PM PDT 24
Peak memory 206620 kb
Host smart-fccb13ba-113b-47a8-9ccc-d83b7580ba38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20883
94684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2088394684
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1675409999
Short name T1612
Test name
Test status
Simulation time 176238618 ps
CPU time 0.83 seconds
Started Jul 18 05:51:53 PM PDT 24
Finished Jul 18 05:52:02 PM PDT 24
Peak memory 206608 kb
Host smart-6f513c4f-b5c3-46b7-8b56-638cacad7df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16754
09999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1675409999
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3785199103
Short name T639
Test name
Test status
Simulation time 170650316 ps
CPU time 0.84 seconds
Started Jul 18 05:51:52 PM PDT 24
Finished Jul 18 05:52:01 PM PDT 24
Peak memory 206596 kb
Host smart-06f00bbf-c02e-433f-8898-f4550c64def5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37851
99103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3785199103
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.1454757110
Short name T1252
Test name
Test status
Simulation time 155632755 ps
CPU time 0.78 seconds
Started Jul 18 05:51:40 PM PDT 24
Finished Jul 18 05:51:52 PM PDT 24
Peak memory 206668 kb
Host smart-7ffa7061-4360-4a70-a64c-57234171ebe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14547
57110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.1454757110
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.464801751
Short name T1816
Test name
Test status
Simulation time 254246495 ps
CPU time 0.9 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:53 PM PDT 24
Peak memory 206656 kb
Host smart-e267552e-98fc-4354-b315-1064f55b3c9e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=464801751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.464801751
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3307307684
Short name T703
Test name
Test status
Simulation time 200467711 ps
CPU time 0.81 seconds
Started Jul 18 05:51:37 PM PDT 24
Finished Jul 18 05:51:50 PM PDT 24
Peak memory 206648 kb
Host smart-fce18cb4-b94f-43fd-865a-bedd1fab57fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33073
07684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3307307684
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.227899988
Short name T1470
Test name
Test status
Simulation time 68114134 ps
CPU time 0.68 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:51:53 PM PDT 24
Peak memory 206652 kb
Host smart-3bbe719a-00bc-471e-95a3-2879fab24bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22789
9988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.227899988
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.2978267627
Short name T234
Test name
Test status
Simulation time 14962342203 ps
CPU time 31.37 seconds
Started Jul 18 05:51:41 PM PDT 24
Finished Jul 18 05:52:24 PM PDT 24
Peak memory 206924 kb
Host smart-5ac9b389-255e-48da-9ff3-698859e871b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29782
67627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.2978267627
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.2236619251
Short name T272
Test name
Test status
Simulation time 195713536 ps
CPU time 0.87 seconds
Started Jul 18 05:51:43 PM PDT 24
Finished Jul 18 05:51:55 PM PDT 24
Peak memory 206644 kb
Host smart-74cd28ec-9f2e-47e9-8b41-f4d5d04fbc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366
19251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.2236619251
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.948150713
Short name T17
Test name
Test status
Simulation time 169761689 ps
CPU time 0.82 seconds
Started Jul 18 05:52:06 PM PDT 24
Finished Jul 18 05:52:20 PM PDT 24
Peak memory 206804 kb
Host smart-c9d32328-96ed-4979-8d26-3a13ac6f767a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94815
0713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.948150713
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.575151198
Short name T475
Test name
Test status
Simulation time 197773295 ps
CPU time 0.87 seconds
Started Jul 18 05:51:52 PM PDT 24
Finished Jul 18 05:52:01 PM PDT 24
Peak memory 206656 kb
Host smart-54e2f7d2-b88f-4657-9c3f-442da3dd34ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57515
1198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.575151198
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.37427660
Short name T2426
Test name
Test status
Simulation time 176930008 ps
CPU time 0.85 seconds
Started Jul 18 05:51:50 PM PDT 24
Finished Jul 18 05:52:00 PM PDT 24
Peak memory 206652 kb
Host smart-a0b09f35-233e-4502-99e1-cc3fc3c3381f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37427
660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.37427660
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.3857942496
Short name T367
Test name
Test status
Simulation time 159673148 ps
CPU time 0.8 seconds
Started Jul 18 05:51:50 PM PDT 24
Finished Jul 18 05:52:00 PM PDT 24
Peak memory 206632 kb
Host smart-6e4f0dcd-721f-4a3d-9b8b-2ffe4342af29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38579
42496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.3857942496
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2255672047
Short name T1676
Test name
Test status
Simulation time 151335518 ps
CPU time 0.8 seconds
Started Jul 18 05:52:03 PM PDT 24
Finished Jul 18 05:52:16 PM PDT 24
Peak memory 206664 kb
Host smart-af7d5a2e-f7c2-4d25-b338-7d260daee75b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22556
72047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2255672047
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3451499240
Short name T1695
Test name
Test status
Simulation time 174215588 ps
CPU time 0.85 seconds
Started Jul 18 05:52:06 PM PDT 24
Finished Jul 18 05:52:20 PM PDT 24
Peak memory 206616 kb
Host smart-30c20852-f634-44b3-965e-2c42815540fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34514
99240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3451499240
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.3824002437
Short name T2159
Test name
Test status
Simulation time 273372372 ps
CPU time 0.96 seconds
Started Jul 18 05:52:08 PM PDT 24
Finished Jul 18 05:52:23 PM PDT 24
Peak memory 206588 kb
Host smart-37cb2fa0-a534-4385-83ee-1db86d0bb94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38240
02437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.3824002437
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.953087735
Short name T1790
Test name
Test status
Simulation time 4560534600 ps
CPU time 42.08 seconds
Started Jul 18 05:52:01 PM PDT 24
Finished Jul 18 05:52:54 PM PDT 24
Peak memory 206940 kb
Host smart-4f491f5b-99f0-4ad7-b32e-4e0fa87f1666
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=953087735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.953087735
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.3630845738
Short name T870
Test name
Test status
Simulation time 172286483 ps
CPU time 0.8 seconds
Started Jul 18 05:52:12 PM PDT 24
Finished Jul 18 05:52:27 PM PDT 24
Peak memory 206636 kb
Host smart-77c36b7c-843f-4544-a542-ff0921f85ade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36308
45738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.3630845738
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.3439990541
Short name T2112
Test name
Test status
Simulation time 161090177 ps
CPU time 0.85 seconds
Started Jul 18 05:52:11 PM PDT 24
Finished Jul 18 05:52:25 PM PDT 24
Peak memory 206616 kb
Host smart-3d6adca0-33fb-4c11-b932-584fb7d7c4cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34399
90541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.3439990541
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.2705951185
Short name T1346
Test name
Test status
Simulation time 254261808 ps
CPU time 0.94 seconds
Started Jul 18 05:51:56 PM PDT 24
Finished Jul 18 05:52:06 PM PDT 24
Peak memory 206636 kb
Host smart-58c06414-a7a5-4787-8aeb-8c5165826a11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
51185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.2705951185
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.360275395
Short name T2712
Test name
Test status
Simulation time 4689696216 ps
CPU time 129.93 seconds
Started Jul 18 05:52:11 PM PDT 24
Finished Jul 18 05:54:34 PM PDT 24
Peak memory 206880 kb
Host smart-d77416f7-e00d-4778-b2dd-3c89c6d2eacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36027
5395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.360275395
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.917544081
Short name T1410
Test name
Test status
Simulation time 75431983 ps
CPU time 0.7 seconds
Started Jul 18 05:44:44 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206704 kb
Host smart-32a85531-55ea-4915-93e3-922066252b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=917544081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.917544081
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.1787061666
Short name T930
Test name
Test status
Simulation time 4273072576 ps
CPU time 4.81 seconds
Started Jul 18 05:44:34 PM PDT 24
Finished Jul 18 05:44:40 PM PDT 24
Peak memory 206676 kb
Host smart-d5dafc9a-9dba-4e79-b450-04653e030a29
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1787061666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.1787061666
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2041348927
Short name T2036
Test name
Test status
Simulation time 13352864588 ps
CPU time 13.7 seconds
Started Jul 18 05:44:35 PM PDT 24
Finished Jul 18 05:44:51 PM PDT 24
Peak memory 206740 kb
Host smart-8a54268f-0b7a-4558-9435-019b1932bc90
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2041348927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2041348927
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.1296347159
Short name T2220
Test name
Test status
Simulation time 23488240019 ps
CPU time 25 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:45:03 PM PDT 24
Peak memory 206916 kb
Host smart-9022743b-b14b-48f6-a71b-5abbdd764bd5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1296347159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.1296347159
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.716774896
Short name T2022
Test name
Test status
Simulation time 211131192 ps
CPU time 0.82 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:40 PM PDT 24
Peak memory 206660 kb
Host smart-caf88c5f-42bc-42ed-b860-2945d6d88a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71677
4896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.716774896
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2489560338
Short name T2366
Test name
Test status
Simulation time 148198003 ps
CPU time 0.77 seconds
Started Jul 18 05:44:34 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 206620 kb
Host smart-ded942d6-9a66-43e2-86d7-f3f23095a661
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24895
60338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2489560338
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2792790323
Short name T2184
Test name
Test status
Simulation time 336517487 ps
CPU time 1.13 seconds
Started Jul 18 05:44:34 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 206668 kb
Host smart-41f6791e-f108-4ae9-b5ce-35f9773e3aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27927
90323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2792790323
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.651091757
Short name T2140
Test name
Test status
Simulation time 282897466 ps
CPU time 0.97 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:41 PM PDT 24
Peak memory 206616 kb
Host smart-b4a61470-0965-471b-91b6-e9af4aea98e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65109
1757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.651091757
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.1167989998
Short name T755
Test name
Test status
Simulation time 21903564491 ps
CPU time 42.08 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:45:22 PM PDT 24
Peak memory 206864 kb
Host smart-d4262b41-d71f-4e00-a62e-b5e88e872429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11679
89998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.1167989998
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.583323944
Short name T341
Test name
Test status
Simulation time 439295501 ps
CPU time 1.31 seconds
Started Jul 18 05:44:38 PM PDT 24
Finished Jul 18 05:44:44 PM PDT 24
Peak memory 206648 kb
Host smart-767971ed-b810-4c22-aca1-8969fc38edd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58332
3944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.583323944
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.48068989
Short name T41
Test name
Test status
Simulation time 145539382 ps
CPU time 0.77 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:40 PM PDT 24
Peak memory 206596 kb
Host smart-31867122-69b6-44c4-8b61-a78a726c3244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48068
989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.48068989
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.714958281
Short name T2615
Test name
Test status
Simulation time 103814237 ps
CPU time 0.71 seconds
Started Jul 18 05:44:33 PM PDT 24
Finished Jul 18 05:44:35 PM PDT 24
Peak memory 206628 kb
Host smart-544df1df-01ff-4798-a577-0796357b107b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71495
8281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.714958281
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1030020643
Short name T2150
Test name
Test status
Simulation time 1035165393 ps
CPU time 2.36 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:41 PM PDT 24
Peak memory 206800 kb
Host smart-fc672255-8d41-4463-b227-c7974cc2d7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10300
20643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1030020643
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.4259071493
Short name T2562
Test name
Test status
Simulation time 194327254 ps
CPU time 1.23 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:44:42 PM PDT 24
Peak memory 206568 kb
Host smart-5d16a9d7-fc26-42a0-8e6b-02b7df4dc2a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42590
71493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.4259071493
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.824087903
Short name T665
Test name
Test status
Simulation time 236653515 ps
CPU time 0.92 seconds
Started Jul 18 05:44:34 PM PDT 24
Finished Jul 18 05:44:37 PM PDT 24
Peak memory 206648 kb
Host smart-90685b76-3a0e-4228-abee-16706ebf3137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82408
7903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.824087903
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.1863676391
Short name T1011
Test name
Test status
Simulation time 140914678 ps
CPU time 0.73 seconds
Started Jul 18 05:44:35 PM PDT 24
Finished Jul 18 05:44:39 PM PDT 24
Peak memory 206628 kb
Host smart-b1a69bc9-0e18-44d3-8ad6-127af979a5e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18636
76391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.1863676391
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.211211917
Short name T910
Test name
Test status
Simulation time 197193673 ps
CPU time 0.89 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:44:41 PM PDT 24
Peak memory 206592 kb
Host smart-2d8a6797-fda9-4c9d-b155-c79383efd917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21121
1917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.211211917
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.170661534
Short name T1381
Test name
Test status
Simulation time 10152250926 ps
CPU time 281.53 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:49:23 PM PDT 24
Peak memory 206840 kb
Host smart-d24e3eab-6454-43f6-b920-c29cdc35a172
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=170661534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.170661534
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3731723782
Short name T1884
Test name
Test status
Simulation time 5681095642 ps
CPU time 20.61 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:45:00 PM PDT 24
Peak memory 206840 kb
Host smart-fc94c0f6-fae3-4e9a-95dd-3d99cb4b2eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37317
23782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3731723782
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.4165023759
Short name T2560
Test name
Test status
Simulation time 230180036 ps
CPU time 0.86 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:44:42 PM PDT 24
Peak memory 206636 kb
Host smart-deb2c1b9-d087-43fe-8242-17bb40d4d323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
23759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.4165023759
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.4247924768
Short name T2492
Test name
Test status
Simulation time 23351909255 ps
CPU time 24.46 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206760 kb
Host smart-a0714f13-a5d2-4ae0-8ccd-b68dd5da6e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42479
24768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.4247924768
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.931268253
Short name T992
Test name
Test status
Simulation time 3343694987 ps
CPU time 3.83 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:48 PM PDT 24
Peak memory 206692 kb
Host smart-6c958fb5-bf6f-4f49-869e-fd9d679d13b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93126
8253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.931268253
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.448997971
Short name T2400
Test name
Test status
Simulation time 7356960850 ps
CPU time 202.32 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:48:13 PM PDT 24
Peak memory 206928 kb
Host smart-323e568b-e35c-4168-8faf-1e29a8b021bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44899
7971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.448997971
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.332482169
Short name T2242
Test name
Test status
Simulation time 3872852914 ps
CPU time 34.93 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206840 kb
Host smart-c5838125-eff0-4371-8cec-9a72238d5066
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=332482169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.332482169
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.768579699
Short name T1413
Test name
Test status
Simulation time 235611076 ps
CPU time 0.89 seconds
Started Jul 18 05:44:40 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206620 kb
Host smart-d628a3e9-2371-4dbc-9f05-cec151886e05
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=768579699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.768579699
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.17996756
Short name T683
Test name
Test status
Simulation time 189051481 ps
CPU time 0.9 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:40 PM PDT 24
Peak memory 206632 kb
Host smart-90e67981-a4cd-4e58-a004-f671c1148bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17996
756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.17996756
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2018028070
Short name T2271
Test name
Test status
Simulation time 5790388014 ps
CPU time 43.71 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:45:28 PM PDT 24
Peak memory 206908 kb
Host smart-e0fc21d3-50fa-4528-80d7-8b6577ee7e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20180
28070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2018028070
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3614464259
Short name T436
Test name
Test status
Simulation time 4090919424 ps
CPU time 41.15 seconds
Started Jul 18 05:44:41 PM PDT 24
Finished Jul 18 05:45:28 PM PDT 24
Peak memory 206876 kb
Host smart-5cc31701-24e3-477c-8d8e-22fce0ba0722
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3614464259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3614464259
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.3038975350
Short name T1705
Test name
Test status
Simulation time 176920308 ps
CPU time 0.84 seconds
Started Jul 18 05:44:40 PM PDT 24
Finished Jul 18 05:44:48 PM PDT 24
Peak memory 206616 kb
Host smart-3ac6fe9d-a620-46a4-9c38-7fd337bbfee3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3038975350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.3038975350
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.2950617651
Short name T2014
Test name
Test status
Simulation time 135893635 ps
CPU time 0.76 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:44:50 PM PDT 24
Peak memory 206656 kb
Host smart-996281a6-8a6e-4668-a682-387c6e3d65e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29506
17651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.2950617651
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.3662079843
Short name T1080
Test name
Test status
Simulation time 209622655 ps
CPU time 0.89 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206624 kb
Host smart-6b7f6de1-7493-48ec-9a8a-e228b5a9cbe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36620
79843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.3662079843
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.4158124381
Short name T1336
Test name
Test status
Simulation time 254199582 ps
CPU time 0.85 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:44:50 PM PDT 24
Peak memory 206612 kb
Host smart-9b82157e-7f64-4a0e-be71-5ed8df57417f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41581
24381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.4158124381
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2831843249
Short name T1327
Test name
Test status
Simulation time 190725187 ps
CPU time 0.86 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:46 PM PDT 24
Peak memory 206624 kb
Host smart-b059f61a-c3a4-475b-99ab-58d77f84deca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28318
43249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2831843249
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3700752682
Short name T1776
Test name
Test status
Simulation time 185612119 ps
CPU time 0.85 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:53 PM PDT 24
Peak memory 206672 kb
Host smart-a218d80a-2102-48f6-8d0f-a3e8f9f18423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37007
52682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3700752682
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.3446585158
Short name T1293
Test name
Test status
Simulation time 152113934 ps
CPU time 0.77 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:44:50 PM PDT 24
Peak memory 206660 kb
Host smart-806264ed-3f33-4e2e-9a4a-3482c2e80489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34465
85158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.3446585158
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1021118692
Short name T1020
Test name
Test status
Simulation time 264383622 ps
CPU time 1.01 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:53 PM PDT 24
Peak memory 206672 kb
Host smart-ccad6e4d-8881-442a-bd46-117ed02ecfd2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1021118692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1021118692
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.358916732
Short name T2731
Test name
Test status
Simulation time 146004672 ps
CPU time 0.77 seconds
Started Jul 18 05:44:38 PM PDT 24
Finished Jul 18 05:44:44 PM PDT 24
Peak memory 206648 kb
Host smart-d6c91593-ceca-4692-9ef7-44409ddbb708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35891
6732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.358916732
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.196419775
Short name T1690
Test name
Test status
Simulation time 77031178 ps
CPU time 0.71 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:53 PM PDT 24
Peak memory 206672 kb
Host smart-cc9970f8-eaba-4b28-9a2a-6f336d1f7c54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19641
9775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.196419775
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4059571619
Short name T1933
Test name
Test status
Simulation time 21610712351 ps
CPU time 47.47 seconds
Started Jul 18 05:44:41 PM PDT 24
Finished Jul 18 05:45:34 PM PDT 24
Peak memory 206872 kb
Host smart-b506bbaa-7bde-4017-aadb-150e8e835d0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40595
71619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4059571619
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.4082302710
Short name T1111
Test name
Test status
Simulation time 204681981 ps
CPU time 0.92 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206652 kb
Host smart-93467f67-39d8-4861-8e47-60f3435e902a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40823
02710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.4082302710
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.779172196
Short name T2430
Test name
Test status
Simulation time 213193035 ps
CPU time 0.92 seconds
Started Jul 18 05:44:52 PM PDT 24
Finished Jul 18 05:44:56 PM PDT 24
Peak memory 206644 kb
Host smart-b9669380-eea3-46a2-a29d-f7c1fbfe0b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77917
2196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.779172196
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1857467237
Short name T757
Test name
Test status
Simulation time 7667367924 ps
CPU time 74.24 seconds
Started Jul 18 05:44:52 PM PDT 24
Finished Jul 18 05:46:09 PM PDT 24
Peak memory 206744 kb
Host smart-c46269d5-e3e9-485c-a33a-f89e228f6c9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1857467237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1857467237
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.332290740
Short name T167
Test name
Test status
Simulation time 7673701697 ps
CPU time 71.52 seconds
Started Jul 18 05:44:52 PM PDT 24
Finished Jul 18 05:46:07 PM PDT 24
Peak memory 206640 kb
Host smart-ffdf93d6-848c-4d15-b555-cbe4d9e74650
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=332290740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.332290740
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.2436472069
Short name T35
Test name
Test status
Simulation time 7489080742 ps
CPU time 29.13 seconds
Started Jul 18 05:44:42 PM PDT 24
Finished Jul 18 05:45:18 PM PDT 24
Peak memory 206864 kb
Host smart-887ca410-669f-4585-b5d3-c0589978c866
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2436472069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.2436472069
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3575494596
Short name T2058
Test name
Test status
Simulation time 248128594 ps
CPU time 0.97 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:44:51 PM PDT 24
Peak memory 206656 kb
Host smart-99c95e8c-3f9b-4f8f-817f-eb94c1240e4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35754
94596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3575494596
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1518385084
Short name T2240
Test name
Test status
Simulation time 190320444 ps
CPU time 0.83 seconds
Started Jul 18 05:44:42 PM PDT 24
Finished Jul 18 05:44:49 PM PDT 24
Peak memory 206644 kb
Host smart-33268cda-83b3-42ce-b5e0-f9485462a34a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15183
85084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1518385084
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1396125087
Short name T2302
Test name
Test status
Simulation time 185348364 ps
CPU time 0.81 seconds
Started Jul 18 05:44:44 PM PDT 24
Finished Jul 18 05:44:51 PM PDT 24
Peak memory 206640 kb
Host smart-ecd7419a-4ff8-4ede-9c28-7ce42a9f9807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13961
25087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1396125087
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.4046800955
Short name T718
Test name
Test status
Simulation time 147963475 ps
CPU time 0.74 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206560 kb
Host smart-b5e1b695-a241-4178-bfa6-a64aecfe286c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40468
00955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.4046800955
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.3267140908
Short name T2348
Test name
Test status
Simulation time 152783195 ps
CPU time 0.82 seconds
Started Jul 18 05:44:52 PM PDT 24
Finished Jul 18 05:44:56 PM PDT 24
Peak memory 206456 kb
Host smart-81940602-a529-46f6-b8ea-342c4a50b9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32671
40908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.3267140908
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2770896459
Short name T838
Test name
Test status
Simulation time 237327389 ps
CPU time 0.97 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206632 kb
Host smart-7ee16a1e-5cd5-4b8c-b847-c7f584eefba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27708
96459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2770896459
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.294587311
Short name T1437
Test name
Test status
Simulation time 5391737241 ps
CPU time 52.31 seconds
Started Jul 18 05:44:42 PM PDT 24
Finished Jul 18 05:45:41 PM PDT 24
Peak memory 206856 kb
Host smart-f0650dcc-8f30-4069-9d52-77099a7ed793
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=294587311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.294587311
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1942915954
Short name T970
Test name
Test status
Simulation time 169875791 ps
CPU time 0.8 seconds
Started Jul 18 05:44:48 PM PDT 24
Finished Jul 18 05:44:54 PM PDT 24
Peak memory 206672 kb
Host smart-6068e982-62a5-4c73-bea5-7a0f27e65380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19429
15954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1942915954
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.2776862034
Short name T1422
Test name
Test status
Simulation time 188986170 ps
CPU time 0.81 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:44:51 PM PDT 24
Peak memory 206620 kb
Host smart-25b53204-33af-4dae-91a3-d828d2e339a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27768
62034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.2776862034
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.3274548161
Short name T1932
Test name
Test status
Simulation time 1253637534 ps
CPU time 2.68 seconds
Started Jul 18 05:44:48 PM PDT 24
Finished Jul 18 05:44:56 PM PDT 24
Peak memory 206792 kb
Host smart-72a73bb2-9473-4ea7-a5a5-259c5268cd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32745
48161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3274548161
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1991011091
Short name T2154
Test name
Test status
Simulation time 3912537016 ps
CPU time 112.74 seconds
Started Jul 18 05:44:42 PM PDT 24
Finished Jul 18 05:46:42 PM PDT 24
Peak memory 206836 kb
Host smart-93708de3-6841-413e-a84b-e765586053e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19910
11091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1991011091
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3460783369
Short name T1318
Test name
Test status
Simulation time 87691545 ps
CPU time 0.71 seconds
Started Jul 18 05:45:43 PM PDT 24
Finished Jul 18 05:45:59 PM PDT 24
Peak memory 206644 kb
Host smart-c968755e-b4f1-4055-bdc8-ba4ad0d2e0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3460783369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3460783369
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.391871732
Short name T1148
Test name
Test status
Simulation time 4145376455 ps
CPU time 4.65 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:56 PM PDT 24
Peak memory 206704 kb
Host smart-b9334691-cc79-4427-92a8-057641387802
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=391871732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.391871732
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.1494547860
Short name T984
Test name
Test status
Simulation time 13389991850 ps
CPU time 13.14 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:53 PM PDT 24
Peak memory 206824 kb
Host smart-bc52b996-a0c4-4814-9557-e65fc7c97b0f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1494547860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.1494547860
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.2479955834
Short name T9
Test name
Test status
Simulation time 23356361575 ps
CPU time 28.14 seconds
Started Jul 18 05:44:38 PM PDT 24
Finished Jul 18 05:45:11 PM PDT 24
Peak memory 206680 kb
Host smart-aa893a2c-b58d-4038-bef5-4fd2b732c31e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2479955834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.2479955834
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.461312560
Short name T671
Test name
Test status
Simulation time 214517654 ps
CPU time 0.88 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:44:42 PM PDT 24
Peak memory 206648 kb
Host smart-d1717cb3-664f-44b1-b41d-35c51d786faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46131
2560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.461312560
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.2303570891
Short name T1996
Test name
Test status
Simulation time 198585679 ps
CPU time 0.95 seconds
Started Jul 18 05:44:36 PM PDT 24
Finished Jul 18 05:44:40 PM PDT 24
Peak memory 206644 kb
Host smart-c737e8e8-9753-4247-9277-90ea54df9284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23035
70891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.2303570891
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.3371969114
Short name T966
Test name
Test status
Simulation time 471102695 ps
CPU time 1.54 seconds
Started Jul 18 05:44:35 PM PDT 24
Finished Jul 18 05:44:39 PM PDT 24
Peak memory 206624 kb
Host smart-2c0e89a4-057d-419d-8037-27097470459f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33719
69114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.3371969114
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.3443833916
Short name T953
Test name
Test status
Simulation time 1356796958 ps
CPU time 3.04 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206792 kb
Host smart-932d84f1-ba00-4e63-a40d-11034c816f8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
33916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.3443833916
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.963863778
Short name T1447
Test name
Test status
Simulation time 13397558412 ps
CPU time 25.72 seconds
Started Jul 18 05:44:38 PM PDT 24
Finished Jul 18 05:45:09 PM PDT 24
Peak memory 206776 kb
Host smart-64ac4733-f092-4dce-9bdf-1e4cb793ca1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96386
3778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.963863778
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.1760200592
Short name T406
Test name
Test status
Simulation time 426221216 ps
CPU time 1.26 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:44:43 PM PDT 24
Peak memory 206644 kb
Host smart-58ff2eee-0ead-494b-b21f-bde6ef11ff95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
00592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.1760200592
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.3790919494
Short name T2685
Test name
Test status
Simulation time 158560009 ps
CPU time 0.78 seconds
Started Jul 18 05:44:41 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206616 kb
Host smart-f94db7d4-65e4-42f1-8f85-86cc1f1ae608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37909
19494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.3790919494
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2303496003
Short name T1487
Test name
Test status
Simulation time 67678761 ps
CPU time 0.74 seconds
Started Jul 18 05:44:40 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206608 kb
Host smart-19b15847-4c1a-4cef-a6b3-57e72a946fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23034
96003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2303496003
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.4123725607
Short name T1347
Test name
Test status
Simulation time 908612542 ps
CPU time 2.33 seconds
Started Jul 18 05:44:41 PM PDT 24
Finished Jul 18 05:44:49 PM PDT 24
Peak memory 206692 kb
Host smart-2d6ea0dc-fc47-4e47-b1c3-45a24f5f2eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41237
25607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.4123725607
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.234706773
Short name T477
Test name
Test status
Simulation time 195288508 ps
CPU time 1.68 seconds
Started Jul 18 05:44:40 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206336 kb
Host smart-fcf8e6c3-793c-4f46-803e-0be73e6937c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23470
6773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.234706773
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.1458485365
Short name T991
Test name
Test status
Simulation time 218300418 ps
CPU time 0.88 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206608 kb
Host smart-da844bcd-70b0-47fe-81ec-1eaf9141a9e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584
85365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.1458485365
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.3384917494
Short name T2248
Test name
Test status
Simulation time 160596776 ps
CPU time 0.83 seconds
Started Jul 18 05:44:41 PM PDT 24
Finished Jul 18 05:44:48 PM PDT 24
Peak memory 206616 kb
Host smart-6cc91db5-0dc7-48c0-9722-0cc17a67955c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33849
17494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.3384917494
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2437814116
Short name T2260
Test name
Test status
Simulation time 250630862 ps
CPU time 0.97 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206620 kb
Host smart-88909ab5-483d-42eb-ad1f-8fcc183f5cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24378
14116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2437814116
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.53544275
Short name T1651
Test name
Test status
Simulation time 6927342459 ps
CPU time 194.5 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:47:59 PM PDT 24
Peak memory 206848 kb
Host smart-cdf614f1-362d-4c68-8f6d-2e254f28456c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=53544275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.53544275
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.1061142460
Short name T339
Test name
Test status
Simulation time 181676209 ps
CPU time 0.87 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:44:50 PM PDT 24
Peak memory 206648 kb
Host smart-dd16d649-6716-42d6-a37a-2f164de12b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10611
42460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.1061142460
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2624716442
Short name T965
Test name
Test status
Simulation time 23317371922 ps
CPU time 22.16 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:45:11 PM PDT 24
Peak memory 206748 kb
Host smart-94f02e15-54c0-43db-8859-a401f8a5a3fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26247
16442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2624716442
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1208527437
Short name T298
Test name
Test status
Simulation time 3276490793 ps
CPU time 4.12 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:49 PM PDT 24
Peak memory 206704 kb
Host smart-7b576d45-5e1a-4005-bbc5-3559fba4235e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
27437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1208527437
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.47396376
Short name T1831
Test name
Test status
Simulation time 8766200485 ps
CPU time 59.12 seconds
Started Jul 18 05:44:38 PM PDT 24
Finished Jul 18 05:45:42 PM PDT 24
Peak memory 206928 kb
Host smart-9aa4d61d-3565-4089-b07c-d0b8b4094c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47396
376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.47396376
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.2523939805
Short name T1409
Test name
Test status
Simulation time 7602714504 ps
CPU time 74.18 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:46:06 PM PDT 24
Peak memory 206920 kb
Host smart-d6fc3481-c718-4fcd-990e-e28e78ea9551
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2523939805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.2523939805
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.555148529
Short name T1131
Test name
Test status
Simulation time 240081370 ps
CPU time 0.95 seconds
Started Jul 18 05:44:40 PM PDT 24
Finished Jul 18 05:44:47 PM PDT 24
Peak memory 206636 kb
Host smart-af315f25-26ac-4b93-9e11-ff52a9703e1f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=555148529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.555148529
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.3010785438
Short name T2324
Test name
Test status
Simulation time 211653061 ps
CPU time 0.91 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206652 kb
Host smart-ab5da1b4-d53d-4a2d-ae1b-6115b803a568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30107
85438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.3010785438
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.151557896
Short name T2644
Test name
Test status
Simulation time 4498818478 ps
CPU time 33.4 seconds
Started Jul 18 05:44:44 PM PDT 24
Finished Jul 18 05:45:24 PM PDT 24
Peak memory 206924 kb
Host smart-5918283b-44fa-4edc-aab2-cbeaf88ffd43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15155
7896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.151557896
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.627873751
Short name T1480
Test name
Test status
Simulation time 5893119049 ps
CPU time 171.75 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:47:33 PM PDT 24
Peak memory 206868 kb
Host smart-c17a1b9e-9123-4ccc-88f7-d9642ab605c4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=627873751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.627873751
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1279517467
Short name T2467
Test name
Test status
Simulation time 168138798 ps
CPU time 0.84 seconds
Started Jul 18 05:44:39 PM PDT 24
Finished Jul 18 05:44:45 PM PDT 24
Peak memory 206636 kb
Host smart-f9fbca7e-ac78-4728-8552-803fc22db335
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1279517467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1279517467
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.2326989077
Short name T415
Test name
Test status
Simulation time 164291633 ps
CPU time 0.84 seconds
Started Jul 18 05:44:50 PM PDT 24
Finished Jul 18 05:44:55 PM PDT 24
Peak memory 206652 kb
Host smart-2113957c-08c3-4971-bfe8-59fe5f6446de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23269
89077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.2326989077
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1741708723
Short name T138
Test name
Test status
Simulation time 189268866 ps
CPU time 0.87 seconds
Started Jul 18 05:44:37 PM PDT 24
Finished Jul 18 05:44:43 PM PDT 24
Peak memory 206604 kb
Host smart-f6c52625-7447-4501-aabc-1717db055948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17417
08723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1741708723
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2832179312
Short name T2575
Test name
Test status
Simulation time 158550808 ps
CPU time 0.77 seconds
Started Jul 18 05:44:48 PM PDT 24
Finished Jul 18 05:44:54 PM PDT 24
Peak memory 206664 kb
Host smart-bfda8e11-ebf9-4c78-8873-f3aca1592b91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28321
79312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2832179312
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.3187633472
Short name T1057
Test name
Test status
Simulation time 157962153 ps
CPU time 0.78 seconds
Started Jul 18 05:44:43 PM PDT 24
Finished Jul 18 05:44:51 PM PDT 24
Peak memory 206660 kb
Host smart-a9995ec9-55ad-4ab5-996a-7e42b4974734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31876
33472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.3187633472
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2814089905
Short name T632
Test name
Test status
Simulation time 155622555 ps
CPU time 0.79 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206528 kb
Host smart-e352b0b8-426f-40b6-b527-f5e8057226d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28140
89905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2814089905
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.2300497508
Short name T1129
Test name
Test status
Simulation time 162297764 ps
CPU time 0.82 seconds
Started Jul 18 05:44:52 PM PDT 24
Finished Jul 18 05:44:56 PM PDT 24
Peak memory 206648 kb
Host smart-c2129701-f439-475a-9266-cda3370003f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23004
97508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.2300497508
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.2845061342
Short name T720
Test name
Test status
Simulation time 229511800 ps
CPU time 0.97 seconds
Started Jul 18 05:44:49 PM PDT 24
Finished Jul 18 05:44:54 PM PDT 24
Peak memory 206656 kb
Host smart-d134527f-99a3-4eb6-ab43-4c84c4bd61ee
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2845061342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2845061342
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2228719049
Short name T2320
Test name
Test status
Simulation time 146122169 ps
CPU time 0.79 seconds
Started Jul 18 05:44:45 PM PDT 24
Finished Jul 18 05:44:52 PM PDT 24
Peak memory 206624 kb
Host smart-7083b7d1-1b40-4973-a3a6-264669f2c8ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22287
19049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2228719049
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.392353325
Short name T1016
Test name
Test status
Simulation time 64471363 ps
CPU time 0.74 seconds
Started Jul 18 05:45:29 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206672 kb
Host smart-dbedab21-89f1-451e-962d-f73016644331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39235
3325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.392353325
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3027221373
Short name T1786
Test name
Test status
Simulation time 19789772055 ps
CPU time 43.37 seconds
Started Jul 18 05:44:38 PM PDT 24
Finished Jul 18 05:45:26 PM PDT 24
Peak memory 206928 kb
Host smart-2f100ee6-620c-44a9-b6cf-de431f98a4ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30272
21373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3027221373
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.991945196
Short name T1783
Test name
Test status
Simulation time 153265693 ps
CPU time 0.79 seconds
Started Jul 18 05:44:48 PM PDT 24
Finished Jul 18 05:44:53 PM PDT 24
Peak memory 206668 kb
Host smart-d2374dff-7069-41ab-be52-e4f3b183561e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99194
5196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.991945196
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2599254720
Short name T657
Test name
Test status
Simulation time 157690775 ps
CPU time 0.78 seconds
Started Jul 18 05:44:58 PM PDT 24
Finished Jul 18 05:45:00 PM PDT 24
Peak memory 206652 kb
Host smart-49801fe3-71a5-4b18-a675-909e20422b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25992
54720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2599254720
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.341568037
Short name T329
Test name
Test status
Simulation time 7951425464 ps
CPU time 50.48 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:53 PM PDT 24
Peak memory 206888 kb
Host smart-af4ebf24-aa47-44c3-a477-4c26091ab417
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=341568037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.341568037
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.1650572858
Short name T184
Test name
Test status
Simulation time 7890149518 ps
CPU time 38.44 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206888 kb
Host smart-38ad54c7-f5f2-4e1a-ba5f-8533e54ca76e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1650572858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.1650572858
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.2907998973
Short name T1462
Test name
Test status
Simulation time 13143760846 ps
CPU time 258.88 seconds
Started Jul 18 05:44:58 PM PDT 24
Finished Jul 18 05:49:20 PM PDT 24
Peak memory 206932 kb
Host smart-93002017-b722-46ab-a914-454944271055
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2907998973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.2907998973
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.3795259478
Short name T791
Test name
Test status
Simulation time 169427284 ps
CPU time 0.82 seconds
Started Jul 18 05:44:57 PM PDT 24
Finished Jul 18 05:44:58 PM PDT 24
Peak memory 206624 kb
Host smart-ef5dce4f-45db-44ef-aa5b-37a9ca78b219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37952
59478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.3795259478
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3627768753
Short name T346
Test name
Test status
Simulation time 143716779 ps
CPU time 0.78 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:13 PM PDT 24
Peak memory 206620 kb
Host smart-8b7f130f-d3a5-4ce5-be28-7f001b72e690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277
68753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3627768753
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.1655101896
Short name T1263
Test name
Test status
Simulation time 167599392 ps
CPU time 0.75 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:10 PM PDT 24
Peak memory 206616 kb
Host smart-b12b96ce-9d98-41db-8420-e045053f7529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16551
01896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.1655101896
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.210434264
Short name T2666
Test name
Test status
Simulation time 168780201 ps
CPU time 0.82 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:05 PM PDT 24
Peak memory 206612 kb
Host smart-da01c0fe-3e2f-4e71-b2c1-6ec6243e7e9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21043
4264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.210434264
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3600399288
Short name T2545
Test name
Test status
Simulation time 161599448 ps
CPU time 0.78 seconds
Started Jul 18 05:45:02 PM PDT 24
Finished Jul 18 05:45:11 PM PDT 24
Peak memory 206640 kb
Host smart-aa94b778-9eab-4e4b-b8c7-04b1eb686d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36003
99288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3600399288
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1921674568
Short name T2247
Test name
Test status
Simulation time 230462309 ps
CPU time 0.93 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:10 PM PDT 24
Peak memory 206608 kb
Host smart-1d6acccc-1c2a-44a3-a6a0-ceee893907d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19216
74568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1921674568
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3016957444
Short name T2012
Test name
Test status
Simulation time 5672546893 ps
CPU time 58.44 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206884 kb
Host smart-115476c4-ba73-47f3-b8ec-e1ef07c9eaa0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3016957444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3016957444
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3061224381
Short name T598
Test name
Test status
Simulation time 155482102 ps
CPU time 0.78 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206656 kb
Host smart-3178c7d8-73a0-4d43-8def-e090302547b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30612
24381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3061224381
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.804708606
Short name T1474
Test name
Test status
Simulation time 166978607 ps
CPU time 0.81 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:05 PM PDT 24
Peak memory 206612 kb
Host smart-64164bb5-7c46-46b6-bf5e-6d118b0b185c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80470
8606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.804708606
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.3359376451
Short name T1897
Test name
Test status
Simulation time 265045513 ps
CPU time 1 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206640 kb
Host smart-4ee4133a-4e20-4649-bf3f-2811a9105b23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
76451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.3359376451
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.1031995464
Short name T1174
Test name
Test status
Simulation time 3882968961 ps
CPU time 26.45 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206848 kb
Host smart-3acca247-1a4b-4fa8-ad10-38071d8248f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10319
95464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.1031995464
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.3363265608
Short name T1275
Test name
Test status
Simulation time 51203456 ps
CPU time 0.7 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206688 kb
Host smart-08bb841e-8f62-4682-8f54-f540856aee2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3363265608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.3363265608
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.4253568490
Short name T1611
Test name
Test status
Simulation time 4030963782 ps
CPU time 4.61 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:07 PM PDT 24
Peak memory 206872 kb
Host smart-949a9cce-dab7-42cb-9ca2-14d80ab8ab0d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4253568490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.4253568490
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2556550061
Short name T2483
Test name
Test status
Simulation time 13467128033 ps
CPU time 14.18 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:18 PM PDT 24
Peak memory 206924 kb
Host smart-eb3f4609-d686-4b7c-a2b8-cec9ed550809
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2556550061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2556550061
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.41686808
Short name T2098
Test name
Test status
Simulation time 23365993741 ps
CPU time 29.36 seconds
Started Jul 18 05:44:57 PM PDT 24
Finished Jul 18 05:45:27 PM PDT 24
Peak memory 206756 kb
Host smart-a05f8341-17b6-4204-b936-13bb1730d087
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=41686808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.41686808
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.3963395372
Short name T2267
Test name
Test status
Simulation time 144850760 ps
CPU time 0.81 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:09 PM PDT 24
Peak memory 206676 kb
Host smart-e374dae8-1f90-4004-98ac-6960e4f1ccdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39633
95372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.3963395372
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3436627653
Short name T2434
Test name
Test status
Simulation time 152560591 ps
CPU time 0.78 seconds
Started Jul 18 05:44:58 PM PDT 24
Finished Jul 18 05:45:01 PM PDT 24
Peak memory 206660 kb
Host smart-8679446f-d9c8-451b-ac77-a5ba98197ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34366
27653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3436627653
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3072049208
Short name T110
Test name
Test status
Simulation time 503862122 ps
CPU time 1.52 seconds
Started Jul 18 05:45:02 PM PDT 24
Finished Jul 18 05:45:12 PM PDT 24
Peak memory 206616 kb
Host smart-9cb23406-b09e-4868-a70a-6d7b0b29c2c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30720
49208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3072049208
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.3311918587
Short name T872
Test name
Test status
Simulation time 1055265793 ps
CPU time 2.42 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:09 PM PDT 24
Peak memory 206744 kb
Host smart-64891f03-687c-43c7-95ff-cce50794301e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33119
18587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.3311918587
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.2393868715
Short name T2716
Test name
Test status
Simulation time 10993351456 ps
CPU time 20.54 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:27 PM PDT 24
Peak memory 206904 kb
Host smart-88e6735f-698f-4bbb-98b9-39eb2369fdb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23938
68715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.2393868715
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.827315765
Short name T2001
Test name
Test status
Simulation time 365710865 ps
CPU time 1.15 seconds
Started Jul 18 05:44:58 PM PDT 24
Finished Jul 18 05:45:01 PM PDT 24
Peak memory 206616 kb
Host smart-dce5d579-ce04-46cb-9492-b1578b0656c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82731
5765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.827315765
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.2208007309
Short name T523
Test name
Test status
Simulation time 194731608 ps
CPU time 0.85 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:03 PM PDT 24
Peak memory 206652 kb
Host smart-14aef170-e285-4f7f-af48-4261f4995196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22080
07309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.2208007309
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3663748982
Short name T308
Test name
Test status
Simulation time 32438318 ps
CPU time 0.65 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206628 kb
Host smart-c38a09bf-4e13-4b74-a799-3eb9d64185c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36637
48982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3663748982
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.426082029
Short name T1989
Test name
Test status
Simulation time 802320676 ps
CPU time 1.87 seconds
Started Jul 18 05:44:58 PM PDT 24
Finished Jul 18 05:45:03 PM PDT 24
Peak memory 206768 kb
Host smart-7df1ac5a-66c6-4724-bc38-dd556386734d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42608
2029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.426082029
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1333269037
Short name T1968
Test name
Test status
Simulation time 176192970 ps
CPU time 1.77 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206756 kb
Host smart-d20b8bdc-161c-4e8d-a04b-86cffaf60d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13332
69037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1333269037
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.1793693306
Short name T1037
Test name
Test status
Simulation time 232467245 ps
CPU time 0.86 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206644 kb
Host smart-2921367d-c2e8-41e9-94c8-f994621a402f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17936
93306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.1793693306
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.1255012816
Short name T1901
Test name
Test status
Simulation time 139043865 ps
CPU time 0.81 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:05 PM PDT 24
Peak memory 206656 kb
Host smart-3641666d-3054-4872-a0c0-430dab01108d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12550
12816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.1255012816
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.754073798
Short name T748
Test name
Test status
Simulation time 172931518 ps
CPU time 0.85 seconds
Started Jul 18 05:44:58 PM PDT 24
Finished Jul 18 05:45:01 PM PDT 24
Peak memory 206656 kb
Host smart-4b46fddb-7f15-47f4-9d96-0e9f7433a411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75407
3798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.754073798
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.3533064573
Short name T1323
Test name
Test status
Simulation time 7492171097 ps
CPU time 53.71 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:46:01 PM PDT 24
Peak memory 206908 kb
Host smart-43a286a9-2f61-4e9c-905b-709c3bb37212
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3533064573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3533064573
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.3771200581
Short name T815
Test name
Test status
Simulation time 5385172955 ps
CPU time 16.54 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:25 PM PDT 24
Peak memory 206884 kb
Host smart-7f2800e1-5e3d-43ae-8e57-3c2e686563eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37712
00581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.3771200581
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.1006572090
Short name T1419
Test name
Test status
Simulation time 212731867 ps
CPU time 0.92 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206648 kb
Host smart-5b16935b-2e83-4c1d-b176-f2cedd8d7692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10065
72090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.1006572090
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.3823328625
Short name T1954
Test name
Test status
Simulation time 23390797618 ps
CPU time 22.99 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:35 PM PDT 24
Peak memory 206792 kb
Host smart-7648930c-2231-43ca-9da4-1ba375356865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38233
28625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.3823328625
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.2175160883
Short name T1418
Test name
Test status
Simulation time 3274227228 ps
CPU time 4 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206716 kb
Host smart-581f5dd4-64fa-4a08-aa66-1aaa9cf0184f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21751
60883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.2175160883
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.2607651818
Short name T1212
Test name
Test status
Simulation time 6555224291 ps
CPU time 49.24 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 207088 kb
Host smart-6b111702-6b03-4658-85d6-aef6e414981f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26076
51818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.2607651818
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.3697568782
Short name T2325
Test name
Test status
Simulation time 7330862377 ps
CPU time 212.38 seconds
Started Jul 18 05:45:02 PM PDT 24
Finished Jul 18 05:48:42 PM PDT 24
Peak memory 206812 kb
Host smart-63aa9a07-6f60-4960-b35d-fa4690896a2d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3697568782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.3697568782
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.421738619
Short name T2171
Test name
Test status
Simulation time 293305750 ps
CPU time 0.96 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:03 PM PDT 24
Peak memory 206648 kb
Host smart-3f9a945e-3082-4dbd-9a6d-f0f274e2ef0d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=421738619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.421738619
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.2252724494
Short name T344
Test name
Test status
Simulation time 204578551 ps
CPU time 0.88 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206632 kb
Host smart-55a2b972-ba79-4b51-a3ea-7adbcfacb248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
24494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.2252724494
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1450822652
Short name T1754
Test name
Test status
Simulation time 4499455862 ps
CPU time 30.13 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206904 kb
Host smart-652aae99-1f25-48c3-acdb-8df47154f45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14508
22652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1450822652
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3499739222
Short name T2632
Test name
Test status
Simulation time 6242090713 ps
CPU time 57.77 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:46:02 PM PDT 24
Peak memory 206880 kb
Host smart-0efa9740-588b-4db9-9e55-1d5df8e14f1e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3499739222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3499739222
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.3461259971
Short name T340
Test name
Test status
Simulation time 147700802 ps
CPU time 0.82 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206652 kb
Host smart-116a1552-1d1b-45f7-9840-1327e95d71b1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3461259971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.3461259971
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.470496063
Short name T1423
Test name
Test status
Simulation time 174750201 ps
CPU time 0.79 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:09 PM PDT 24
Peak memory 206592 kb
Host smart-6b5c6021-d56c-4861-8eb4-1beb7a726ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47049
6063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.470496063
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3597081936
Short name T124
Test name
Test status
Simulation time 184738973 ps
CPU time 0.84 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206644 kb
Host smart-6f20f996-47a0-44bc-9e4e-dcc03564805b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35970
81936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3597081936
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1040333462
Short name T916
Test name
Test status
Simulation time 190324760 ps
CPU time 0.91 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:14 PM PDT 24
Peak memory 206460 kb
Host smart-65447a5c-ca77-4d49-82ec-c1bc00afb9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10403
33462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1040333462
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2930304307
Short name T2566
Test name
Test status
Simulation time 185045423 ps
CPU time 0.86 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206604 kb
Host smart-fa5c3dfd-c6b2-45b8-96c3-42ee2321e14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29303
04307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2930304307
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.577343972
Short name T1593
Test name
Test status
Simulation time 176097317 ps
CPU time 0.77 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:10 PM PDT 24
Peak memory 206644 kb
Host smart-ea129622-5749-4f3d-9c1b-76320ae8e7b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57734
3972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.577343972
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.3712392253
Short name T763
Test name
Test status
Simulation time 148594749 ps
CPU time 0.85 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206816 kb
Host smart-07803c8e-b8d0-4dd4-ac41-b16a4bc412ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37123
92253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.3712392253
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1424778046
Short name T306
Test name
Test status
Simulation time 215471356 ps
CPU time 0.92 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:14 PM PDT 24
Peak memory 206480 kb
Host smart-d2d15386-82cc-4eda-8b73-eab2a3450437
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1424778046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1424778046
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.2652823429
Short name T1850
Test name
Test status
Simulation time 136273191 ps
CPU time 0.8 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206812 kb
Host smart-fc5557cf-b96d-4eba-8ad1-24e7dfcd460f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26528
23429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.2652823429
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.445121520
Short name T2281
Test name
Test status
Simulation time 78442121 ps
CPU time 0.72 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:03 PM PDT 24
Peak memory 206628 kb
Host smart-32651bda-5191-43c1-936f-b56ba117940c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44512
1520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.445121520
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1399531953
Short name T2273
Test name
Test status
Simulation time 7103199619 ps
CPU time 15.98 seconds
Started Jul 18 05:45:02 PM PDT 24
Finished Jul 18 05:45:25 PM PDT 24
Peak memory 206916 kb
Host smart-73ba1878-727c-47ae-a487-320132cc84dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13995
31953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1399531953
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3416879455
Short name T1780
Test name
Test status
Simulation time 156094980 ps
CPU time 0.77 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:13 PM PDT 24
Peak memory 206656 kb
Host smart-f4e41d80-d74f-4f5e-8776-7e7db7a00473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34168
79455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3416879455
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3203539861
Short name T968
Test name
Test status
Simulation time 215080213 ps
CPU time 0.91 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:14 PM PDT 24
Peak memory 206652 kb
Host smart-70aae7ff-f9a4-4ea8-a2a5-0e17efc61e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32035
39861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3203539861
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.212803821
Short name T883
Test name
Test status
Simulation time 4407436208 ps
CPU time 35.99 seconds
Started Jul 18 05:45:06 PM PDT 24
Finished Jul 18 05:45:54 PM PDT 24
Peak memory 206836 kb
Host smart-b1647a3d-3618-4ffb-aa77-cc66139ae67b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=212803821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.212803821
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.1011287084
Short name T2410
Test name
Test status
Simulation time 11732381533 ps
CPU time 213.2 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:48:46 PM PDT 24
Peak memory 206924 kb
Host smart-8ddaedae-3b74-4045-836b-cbc299e1944d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1011287084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.1011287084
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2227843246
Short name T2590
Test name
Test status
Simulation time 21323226606 ps
CPU time 133.2 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:47:25 PM PDT 24
Peak memory 206868 kb
Host smart-1b268937-5172-4b28-a72c-86dbdb6fa746
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2227843246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2227843246
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.2222677280
Short name T2118
Test name
Test status
Simulation time 199358388 ps
CPU time 0.86 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:09 PM PDT 24
Peak memory 206636 kb
Host smart-2795277f-aa05-46d5-b7a1-b39fe5fe6b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22226
77280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.2222677280
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.27121347
Short name T1950
Test name
Test status
Simulation time 170608170 ps
CPU time 0.83 seconds
Started Jul 18 05:45:06 PM PDT 24
Finished Jul 18 05:45:18 PM PDT 24
Peak memory 206636 kb
Host smart-39bf41d1-c8ae-479e-8077-3ea737cf6c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27121
347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.27121347
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.3006648718
Short name T1023
Test name
Test status
Simulation time 150789734 ps
CPU time 0.75 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206632 kb
Host smart-22551910-650a-42c8-a3dc-564057867ad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30066
48718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.3006648718
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1459899934
Short name T421
Test name
Test status
Simulation time 177866695 ps
CPU time 0.8 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:05 PM PDT 24
Peak memory 206608 kb
Host smart-7d740a6e-8cd3-41c4-b4c4-1a5a7d37e6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14598
99934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1459899934
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2207230378
Short name T1601
Test name
Test status
Simulation time 215521071 ps
CPU time 0.8 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:45:19 PM PDT 24
Peak memory 206640 kb
Host smart-e2064dfd-8fcc-40ba-bbc0-ee3b45d8d586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22072
30378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2207230378
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.767691922
Short name T2581
Test name
Test status
Simulation time 208745688 ps
CPU time 0.94 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206368 kb
Host smart-85ef2a67-6ccc-4825-b1e3-cd397c13c790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76769
1922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.767691922
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3403144125
Short name T159
Test name
Test status
Simulation time 3506168440 ps
CPU time 33.96 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:46 PM PDT 24
Peak memory 206916 kb
Host smart-9d715b46-1ee9-42e0-9d08-7cb5cf08f632
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3403144125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3403144125
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2952854511
Short name T2132
Test name
Test status
Simulation time 200666973 ps
CPU time 0.84 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:45:19 PM PDT 24
Peak memory 206596 kb
Host smart-8083ad88-16be-46e0-b827-85d3b504c95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29528
54511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2952854511
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.1613585691
Short name T1113
Test name
Test status
Simulation time 170652315 ps
CPU time 0.8 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:24 PM PDT 24
Peak memory 206588 kb
Host smart-6d5b3c02-e258-4f2e-ab3f-3a3197ad4d64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16135
85691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.1613585691
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.565649156
Short name T2721
Test name
Test status
Simulation time 251628776 ps
CPU time 0.94 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:45:19 PM PDT 24
Peak memory 206656 kb
Host smart-f0f815ee-f5cd-44f6-949b-c0e4cf1f87f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56564
9156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.565649156
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.1550313716
Short name T573
Test name
Test status
Simulation time 5438306517 ps
CPU time 53.21 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:46:16 PM PDT 24
Peak memory 206916 kb
Host smart-f698ce29-dc19-4394-8f1f-88fcabeb3074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15503
13716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.1550313716
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.3952559390
Short name T1459
Test name
Test status
Simulation time 62817183 ps
CPU time 0.67 seconds
Started Jul 18 05:45:09 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206624 kb
Host smart-6aaca452-2aa0-442f-9110-5fc5f3b44447
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3952559390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.3952559390
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.524733215
Short name T593
Test name
Test status
Simulation time 4231033988 ps
CPU time 5.32 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:28 PM PDT 24
Peak memory 206776 kb
Host smart-2f26cbb5-e116-4888-b0dc-65d2b4d0e445
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=524733215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.524733215
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.4196002700
Short name T2536
Test name
Test status
Simulation time 13344687177 ps
CPU time 15.92 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:27 PM PDT 24
Peak memory 206716 kb
Host smart-00895111-e628-49f2-b262-52e8b7fbde81
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4196002700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.4196002700
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.1295826878
Short name T15
Test name
Test status
Simulation time 23347457765 ps
CPU time 25.81 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:48 PM PDT 24
Peak memory 206768 kb
Host smart-8f73b3a1-36fa-4ba9-9db1-0c2f0a2aa32c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1295826878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.1295826878
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.1859801699
Short name T1747
Test name
Test status
Simulation time 180007773 ps
CPU time 0.85 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206648 kb
Host smart-d1efd3ed-5e43-49e6-9522-2400cb26d698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18598
01699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.1859801699
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.1197402079
Short name T469
Test name
Test status
Simulation time 135176997 ps
CPU time 0.79 seconds
Started Jul 18 05:45:02 PM PDT 24
Finished Jul 18 05:45:11 PM PDT 24
Peak memory 206624 kb
Host smart-5e89ed4a-e1e8-45ec-99c7-f96b965e3fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11974
02079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.1197402079
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.290098343
Short name T629
Test name
Test status
Simulation time 250686376 ps
CPU time 0.99 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:12 PM PDT 24
Peak memory 206620 kb
Host smart-d3a80b9d-deab-4beb-85d4-9db63a795d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29009
8343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.290098343
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.3032021561
Short name T2451
Test name
Test status
Simulation time 1053882414 ps
CPU time 2.36 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:11 PM PDT 24
Peak memory 206792 kb
Host smart-df682395-688a-4b3a-8c48-a438e8cbc183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30320
21561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.3032021561
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.372709207
Short name T2107
Test name
Test status
Simulation time 20423112413 ps
CPU time 36.24 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:50 PM PDT 24
Peak memory 206852 kb
Host smart-a9dd2618-ccc3-4970-9240-b834c18d38db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37270
9207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.372709207
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.2258961418
Short name T604
Test name
Test status
Simulation time 500940949 ps
CPU time 1.38 seconds
Started Jul 18 05:44:58 PM PDT 24
Finished Jul 18 05:45:02 PM PDT 24
Peak memory 206644 kb
Host smart-9351439a-c458-4222-bead-e2d98d6575aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22589
61418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.2258961418
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3106621124
Short name T2342
Test name
Test status
Simulation time 165316399 ps
CPU time 0.77 seconds
Started Jul 18 05:44:59 PM PDT 24
Finished Jul 18 05:45:05 PM PDT 24
Peak memory 206652 kb
Host smart-6abb5143-cb72-4693-b911-70e2c71360e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31066
21124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3106621124
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.692736851
Short name T2416
Test name
Test status
Simulation time 36436605 ps
CPU time 0.71 seconds
Started Jul 18 05:45:08 PM PDT 24
Finished Jul 18 05:45:20 PM PDT 24
Peak memory 206628 kb
Host smart-1505d230-f76f-4be5-b8d1-6cb95c44652b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69273
6851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.692736851
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1588176772
Short name T714
Test name
Test status
Simulation time 916971858 ps
CPU time 2.13 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206752 kb
Host smart-42a9ffde-b40c-4fe6-afd2-1d3d6f77372e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15881
76772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1588176772
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1348588667
Short name T1832
Test name
Test status
Simulation time 345712569 ps
CPU time 1.88 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206760 kb
Host smart-89c1c007-de67-48a0-9167-f3f0e8774fd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13485
88667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1348588667
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1625714025
Short name T373
Test name
Test status
Simulation time 205605551 ps
CPU time 0.91 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:13 PM PDT 24
Peak memory 206648 kb
Host smart-9e5b2070-cfc3-4b05-8658-1868e74a02a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16257
14025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1625714025
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.864522283
Short name T1530
Test name
Test status
Simulation time 165954480 ps
CPU time 0.76 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206652 kb
Host smart-15d74b06-4e06-4dd9-b0ba-ab840ee51ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86452
2283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.864522283
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.2953941106
Short name T1704
Test name
Test status
Simulation time 211296371 ps
CPU time 0.91 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206652 kb
Host smart-82bc2ef1-152c-4bb0-bccd-ed4080d796ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29539
41106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.2953941106
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.896533363
Short name T638
Test name
Test status
Simulation time 7973886002 ps
CPU time 26.09 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:40 PM PDT 24
Peak memory 206872 kb
Host smart-92f54c10-7ccc-4b08-8a62-0ca85a7eaee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89653
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.896533363
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.1027956364
Short name T2188
Test name
Test status
Simulation time 221697735 ps
CPU time 0.83 seconds
Started Jul 18 05:45:02 PM PDT 24
Finished Jul 18 05:45:11 PM PDT 24
Peak memory 206640 kb
Host smart-f194b3c9-bd83-4d7d-837d-155b4acc3c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10279
56364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.1027956364
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.3290265376
Short name T2137
Test name
Test status
Simulation time 23304952510 ps
CPU time 31.15 seconds
Started Jul 18 05:45:03 PM PDT 24
Finished Jul 18 05:45:42 PM PDT 24
Peak memory 206760 kb
Host smart-5ed126ad-82f5-4ea3-91ed-9be406129e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32902
65376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.3290265376
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.1491438373
Short name T1688
Test name
Test status
Simulation time 3316502167 ps
CPU time 3.89 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:13 PM PDT 24
Peak memory 206704 kb
Host smart-2847e46d-367e-47be-a11c-78d9cb730fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14914
38373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.1491438373
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.2381289980
Short name T2722
Test name
Test status
Simulation time 6536287527 ps
CPU time 181.23 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:48:11 PM PDT 24
Peak memory 206896 kb
Host smart-71346051-1de7-480f-b7c0-a9096fb0ed1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23812
89980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.2381289980
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.650947927
Short name T2296
Test name
Test status
Simulation time 7371000929 ps
CPU time 202.87 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:48:45 PM PDT 24
Peak memory 207008 kb
Host smart-245771e6-523c-4294-bb5e-91b3d21e874f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=650947927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.650947927
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2209832425
Short name T2362
Test name
Test status
Simulation time 241827025 ps
CPU time 0.9 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206792 kb
Host smart-2e51c69c-4715-41fb-81f8-7fa7483404fc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2209832425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2209832425
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.4261160452
Short name T2564
Test name
Test status
Simulation time 205325575 ps
CPU time 0.93 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:08 PM PDT 24
Peak memory 206396 kb
Host smart-bbdf6cab-1958-4090-b6fe-4f62df2324ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42611
60452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.4261160452
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.967751974
Short name T977
Test name
Test status
Simulation time 4603513500 ps
CPU time 31.86 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:45 PM PDT 24
Peak memory 206928 kb
Host smart-b39efd1c-9903-444d-903e-1bcf76747ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96775
1974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.967751974
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.1669379781
Short name T865
Test name
Test status
Simulation time 2980084430 ps
CPU time 82.89 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:46:30 PM PDT 24
Peak memory 206696 kb
Host smart-a57cf2f0-6980-458e-a6a8-ef40182ffc91
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1669379781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.1669379781
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.1699515109
Short name T1616
Test name
Test status
Simulation time 202927790 ps
CPU time 0.84 seconds
Started Jul 18 05:45:01 PM PDT 24
Finished Jul 18 05:45:09 PM PDT 24
Peak memory 206656 kb
Host smart-9b0029a6-7669-46ae-89e4-c8499856873b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1699515109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.1699515109
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3290106496
Short name T962
Test name
Test status
Simulation time 141682498 ps
CPU time 0.76 seconds
Started Jul 18 05:45:06 PM PDT 24
Finished Jul 18 05:45:18 PM PDT 24
Peak memory 206648 kb
Host smart-313fd2b1-e9d1-4367-aeb4-0950b562253b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32901
06496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3290106496
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.522811313
Short name T1004
Test name
Test status
Simulation time 169368777 ps
CPU time 0.79 seconds
Started Jul 18 05:45:05 PM PDT 24
Finished Jul 18 05:45:17 PM PDT 24
Peak memory 206640 kb
Host smart-de865e99-8f05-4ad2-be69-cc02febc7bc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52281
1313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.522811313
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2071563137
Short name T2136
Test name
Test status
Simulation time 175587697 ps
CPU time 0.83 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:45:19 PM PDT 24
Peak memory 206656 kb
Host smart-2168831b-c48f-4c4e-9460-126818e19151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20715
63137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2071563137
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3852105124
Short name T569
Test name
Test status
Simulation time 232811456 ps
CPU time 0.93 seconds
Started Jul 18 05:45:51 PM PDT 24
Finished Jul 18 05:46:04 PM PDT 24
Peak memory 206640 kb
Host smart-f8ca0575-8274-4588-87b7-efec082ad8a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38521
05124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3852105124
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3048108572
Short name T1073
Test name
Test status
Simulation time 151869089 ps
CPU time 0.81 seconds
Started Jul 18 05:45:02 PM PDT 24
Finished Jul 18 05:45:11 PM PDT 24
Peak memory 206656 kb
Host smart-02c72b38-090d-4c73-af0c-802e49083353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30481
08572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3048108572
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.230720250
Short name T568
Test name
Test status
Simulation time 238303938 ps
CPU time 0.99 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:45:20 PM PDT 24
Peak memory 206652 kb
Host smart-0b012aea-ed77-4659-bb21-f917ab3ecb58
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=230720250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.230720250
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.3456307510
Short name T798
Test name
Test status
Simulation time 134947117 ps
CPU time 0.76 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:45:19 PM PDT 24
Peak memory 206604 kb
Host smart-b2749665-f7ad-488c-b4bf-2858b683e95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34563
07510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.3456307510
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1130772330
Short name T32
Test name
Test status
Simulation time 45758489 ps
CPU time 0.66 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:14 PM PDT 24
Peak memory 206628 kb
Host smart-3f79d040-6643-4625-9d4e-87ea714d22c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
72330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1130772330
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.3889783559
Short name T1698
Test name
Test status
Simulation time 9613754492 ps
CPU time 22.77 seconds
Started Jul 18 05:45:00 PM PDT 24
Finished Jul 18 05:45:30 PM PDT 24
Peak memory 206920 kb
Host smart-154293c8-45cf-46eb-b52a-f6a13ef04f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38897
83559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.3889783559
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.2264017445
Short name T630
Test name
Test status
Simulation time 213235471 ps
CPU time 0.9 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:15 PM PDT 24
Peak memory 206404 kb
Host smart-5b30f579-94ef-4110-a465-8b086cebd22b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22640
17445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.2264017445
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1915493403
Short name T948
Test name
Test status
Simulation time 213199435 ps
CPU time 0.99 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:16 PM PDT 24
Peak memory 206632 kb
Host smart-d9e534b3-4322-4fe3-aab3-051263227ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19154
93403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1915493403
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2076780519
Short name T1976
Test name
Test status
Simulation time 8533411959 ps
CPU time 55.03 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:46:08 PM PDT 24
Peak memory 206904 kb
Host smart-0de4af46-ec7a-4130-b311-9f3dfb1bd45f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2076780519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2076780519
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.746116157
Short name T988
Test name
Test status
Simulation time 12219844566 ps
CPU time 62.87 seconds
Started Jul 18 05:45:08 PM PDT 24
Finished Jul 18 05:46:23 PM PDT 24
Peak memory 206896 kb
Host smart-e68c84ef-7bd7-450b-8218-81a743628be5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=746116157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.746116157
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3281392434
Short name T1341
Test name
Test status
Simulation time 10117259161 ps
CPU time 191.94 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:48:30 PM PDT 24
Peak memory 206896 kb
Host smart-3c4b3cc8-7189-4d7a-887f-18d69525282d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3281392434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3281392434
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2033498478
Short name T1684
Test name
Test status
Simulation time 260092906 ps
CPU time 0.94 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:14 PM PDT 24
Peak memory 206652 kb
Host smart-4cf00efe-2eb0-44ef-8baa-48ca6caf3976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
98478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2033498478
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.3786847448
Short name T906
Test name
Test status
Simulation time 175677977 ps
CPU time 0.85 seconds
Started Jul 18 05:45:04 PM PDT 24
Finished Jul 18 05:45:14 PM PDT 24
Peak memory 206596 kb
Host smart-72d344d9-2afc-430e-b60c-e475934cbac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37868
47448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.3786847448
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.883240355
Short name T70
Test name
Test status
Simulation time 164736720 ps
CPU time 0.8 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:45:20 PM PDT 24
Peak memory 206616 kb
Host smart-05a619a4-8d07-40f1-9e55-4e963e89e6cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88324
0355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.883240355
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.4008237589
Short name T654
Test name
Test status
Simulation time 157744893 ps
CPU time 0.79 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:45:27 PM PDT 24
Peak memory 206636 kb
Host smart-a4fe6cdb-399e-4a85-83a7-6e6a6176337f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40082
37589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.4008237589
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.1614352999
Short name T1920
Test name
Test status
Simulation time 146312057 ps
CPU time 0.78 seconds
Started Jul 18 05:45:18 PM PDT 24
Finished Jul 18 05:45:35 PM PDT 24
Peak memory 206772 kb
Host smart-4162fff3-7693-4876-9c1e-2909a7f2ad9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16143
52999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.1614352999
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.4131313150
Short name T1109
Test name
Test status
Simulation time 200035907 ps
CPU time 0.9 seconds
Started Jul 18 05:45:18 PM PDT 24
Finished Jul 18 05:45:35 PM PDT 24
Peak memory 206776 kb
Host smart-72bac04b-1cfc-4fd2-aa92-407ba0c8df68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41313
13150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4131313150
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2944024960
Short name T941
Test name
Test status
Simulation time 4317711155 ps
CPU time 123.79 seconds
Started Jul 18 05:45:14 PM PDT 24
Finished Jul 18 05:47:32 PM PDT 24
Peak memory 206532 kb
Host smart-ed0349cd-5596-4bc3-903c-2f963618db8c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2944024960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2944024960
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.1261681668
Short name T2446
Test name
Test status
Simulation time 186081797 ps
CPU time 0.81 seconds
Started Jul 18 05:45:15 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206640 kb
Host smart-126b8ed2-a85a-4f74-8fc9-23462c60b5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12616
81668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.1261681668
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2319298086
Short name T1830
Test name
Test status
Simulation time 164890429 ps
CPU time 0.8 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:45:34 PM PDT 24
Peak memory 206620 kb
Host smart-8a520907-b973-4386-9dbb-5363fa56148b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23192
98086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2319298086
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.1015744487
Short name T613
Test name
Test status
Simulation time 1191166358 ps
CPU time 2.42 seconds
Started Jul 18 05:45:15 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206760 kb
Host smart-79f3268f-7f56-495f-8d46-968588b40a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10157
44487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.1015744487
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.3543399068
Short name T434
Test name
Test status
Simulation time 7242003523 ps
CPU time 70.08 seconds
Started Jul 18 05:45:07 PM PDT 24
Finished Jul 18 05:46:29 PM PDT 24
Peak memory 206848 kb
Host smart-8670f323-6fbd-4da6-a43f-fb86f174a52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
99068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.3543399068
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2932852942
Short name T1388
Test name
Test status
Simulation time 74772463 ps
CPU time 0.68 seconds
Started Jul 18 05:45:22 PM PDT 24
Finished Jul 18 05:45:40 PM PDT 24
Peak memory 206688 kb
Host smart-ac4a41e0-92ae-4068-92b7-17cd9a5aeb17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2932852942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2932852942
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.2357636523
Short name T1067
Test name
Test status
Simulation time 3982989146 ps
CPU time 4.54 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206872 kb
Host smart-1b580334-9a39-4165-811c-1d87935118c5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2357636523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.2357636523
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3518348005
Short name T731
Test name
Test status
Simulation time 13343323543 ps
CPU time 15.69 seconds
Started Jul 18 05:45:13 PM PDT 24
Finished Jul 18 05:45:43 PM PDT 24
Peak memory 206752 kb
Host smart-4e7e737e-8624-4a21-9eec-b84bd0564ead
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3518348005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3518348005
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.753188543
Short name T1209
Test name
Test status
Simulation time 23322004431 ps
CPU time 22.42 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:45:49 PM PDT 24
Peak memory 206708 kb
Host smart-ab453bc3-f091-43b4-931b-fec34678d686
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=753188543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.753188543
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.691104151
Short name T2534
Test name
Test status
Simulation time 153221526 ps
CPU time 0.86 seconds
Started Jul 18 05:45:11 PM PDT 24
Finished Jul 18 05:45:25 PM PDT 24
Peak memory 206620 kb
Host smart-280b1f1b-d361-43eb-beb3-a2500f495a0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69110
4151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.691104151
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2987832818
Short name T1733
Test name
Test status
Simulation time 170048845 ps
CPU time 0.81 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:45:26 PM PDT 24
Peak memory 206656 kb
Host smart-e15ce215-870f-4beb-9bc9-25261eeba60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29878
32818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2987832818
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2969248397
Short name T2418
Test name
Test status
Simulation time 474667232 ps
CPU time 1.44 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:24 PM PDT 24
Peak memory 206960 kb
Host smart-be383e06-182f-493b-98f9-5d621f34979f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29692
48397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2969248397
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2146269989
Short name T80
Test name
Test status
Simulation time 1269365460 ps
CPU time 2.8 seconds
Started Jul 18 05:45:09 PM PDT 24
Finished Jul 18 05:45:24 PM PDT 24
Peak memory 206728 kb
Host smart-36a92635-4d60-430d-8ebd-c356cdc3c9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21462
69989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2146269989
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.1291937612
Short name T1256
Test name
Test status
Simulation time 13904124544 ps
CPU time 24.85 seconds
Started Jul 18 05:45:11 PM PDT 24
Finished Jul 18 05:45:49 PM PDT 24
Peak memory 206864 kb
Host smart-1f013215-9a9c-4f9d-8c0e-4fef6686fd88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12919
37612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.1291937612
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3240313711
Short name T2597
Test name
Test status
Simulation time 416204153 ps
CPU time 1.24 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:36 PM PDT 24
Peak memory 206804 kb
Host smart-223dd7a0-80b8-404b-9fcc-13f34de28138
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32403
13711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3240313711
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1406632971
Short name T1717
Test name
Test status
Simulation time 192086357 ps
CPU time 0.82 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:45:33 PM PDT 24
Peak memory 206632 kb
Host smart-342b3e18-d033-4a3b-8dcb-f0eb3bef2cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14066
32971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1406632971
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.2952020501
Short name T1458
Test name
Test status
Simulation time 103060965 ps
CPU time 0.71 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:45:27 PM PDT 24
Peak memory 206612 kb
Host smart-bfb9e79a-cc06-43df-b9bf-2d7b89900cb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29520
20501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.2952020501
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.3324268557
Short name T709
Test name
Test status
Simulation time 848457159 ps
CPU time 2.13 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:45:35 PM PDT 24
Peak memory 206956 kb
Host smart-619a97c9-1d63-436d-be5b-2615e3da7c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
68557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.3324268557
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.827832187
Short name T997
Test name
Test status
Simulation time 186597280 ps
CPU time 2.07 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:26 PM PDT 24
Peak memory 206956 kb
Host smart-a1b2bd61-8095-4ef2-90bd-406011960e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82783
2187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.827832187
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1416838278
Short name T349
Test name
Test status
Simulation time 184462413 ps
CPU time 0.87 seconds
Started Jul 18 05:45:20 PM PDT 24
Finished Jul 18 05:45:38 PM PDT 24
Peak memory 206624 kb
Host smart-3ee0cb92-d794-4708-8b79-e4fdfa6e3de1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14168
38278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1416838278
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.1907485153
Short name T2522
Test name
Test status
Simulation time 146939797 ps
CPU time 0.74 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206616 kb
Host smart-b686f102-bdfa-43ff-9da4-d57e9059d3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19074
85153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.1907485153
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3571024051
Short name T2344
Test name
Test status
Simulation time 163597376 ps
CPU time 0.79 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206636 kb
Host smart-180a7a2b-ecda-4bf6-bd80-f5381b8bbe33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35710
24051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3571024051
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_invalid_sync.2263029949
Short name T2440
Test name
Test status
Simulation time 5760487648 ps
CPU time 39.15 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:46:10 PM PDT 24
Peak memory 206812 kb
Host smart-149ff1ca-a5ca-4b2a-b8b5-f9faf60e909c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2263029949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_invalid_sync.2263029949
Directory /workspace/9.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.3466517896
Short name T108
Test name
Test status
Simulation time 4368056781 ps
CPU time 16.56 seconds
Started Jul 18 05:45:18 PM PDT 24
Finished Jul 18 05:45:50 PM PDT 24
Peak memory 206832 kb
Host smart-69620473-2344-42d3-a407-58c406b4f9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34665
17896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.3466517896
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1969332106
Short name T317
Test name
Test status
Simulation time 275808935 ps
CPU time 0.99 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:45:34 PM PDT 24
Peak memory 206560 kb
Host smart-134b58dc-0c7c-4f9b-a6a1-ad5e077e97c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19693
32106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1969332106
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3381371379
Short name T1560
Test name
Test status
Simulation time 23313234159 ps
CPU time 26.43 seconds
Started Jul 18 05:45:12 PM PDT 24
Finished Jul 18 05:45:53 PM PDT 24
Peak memory 206756 kb
Host smart-4b631448-2e5c-443e-a755-d801891a7a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33813
71379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3381371379
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.3487252886
Short name T1217
Test name
Test status
Simulation time 3334759429 ps
CPU time 3.54 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:35 PM PDT 24
Peak memory 206692 kb
Host smart-a0989a6b-3092-44f0-a4d0-c571f992e207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34872
52886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.3487252886
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1149013948
Short name T2073
Test name
Test status
Simulation time 8042656302 ps
CPU time 218.16 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:49:09 PM PDT 24
Peak memory 206920 kb
Host smart-471f65c7-bb49-4ee6-93e8-94680028ceb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11490
13948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1149013948
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.1695901732
Short name T828
Test name
Test status
Simulation time 5302157791 ps
CPU time 37.04 seconds
Started Jul 18 05:45:18 PM PDT 24
Finished Jul 18 05:46:11 PM PDT 24
Peak memory 206840 kb
Host smart-2ca46db8-7d38-4511-98ad-cee7cbc91ec4
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1695901732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.1695901732
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3934307191
Short name T2026
Test name
Test status
Simulation time 260146474 ps
CPU time 0.89 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206620 kb
Host smart-b477b928-8a86-45a8-9214-03588f81d795
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3934307191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3934307191
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.2001861297
Short name T1140
Test name
Test status
Simulation time 223397557 ps
CPU time 0.93 seconds
Started Jul 18 05:45:08 PM PDT 24
Finished Jul 18 05:45:21 PM PDT 24
Peak memory 206652 kb
Host smart-aa5a5151-2d14-414b-8408-eb8d72e381a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20018
61297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.2001861297
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.4194877735
Short name T1592
Test name
Test status
Simulation time 4586122957 ps
CPU time 126.41 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:47:38 PM PDT 24
Peak memory 207024 kb
Host smart-54bf4b61-e710-41fe-b0cf-189545a568ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41948
77735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.4194877735
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.1810387408
Short name T1977
Test name
Test status
Simulation time 6966417269 ps
CPU time 68.21 seconds
Started Jul 18 05:45:17 PM PDT 24
Finished Jul 18 05:46:41 PM PDT 24
Peak memory 206788 kb
Host smart-a0951790-c7b5-4270-a455-c19c54b42255
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1810387408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.1810387408
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.4005702515
Short name T2286
Test name
Test status
Simulation time 161285436 ps
CPU time 0.76 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206632 kb
Host smart-4ba91c1d-d8a5-4e6a-aa68-612b1f9f0a89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4005702515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.4005702515
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3580923960
Short name T310
Test name
Test status
Simulation time 152047220 ps
CPU time 0.77 seconds
Started Jul 18 05:45:09 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206632 kb
Host smart-23647199-a975-4b83-a61f-8924006d3440
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
23960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3580923960
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3551193908
Short name T1562
Test name
Test status
Simulation time 156850024 ps
CPU time 0.77 seconds
Started Jul 18 05:45:15 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206620 kb
Host smart-5837d563-5cfb-45e9-b0f6-93b597bcf545
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
93908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3551193908
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2163268367
Short name T762
Test name
Test status
Simulation time 169492781 ps
CPU time 0.81 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206608 kb
Host smart-cd0861d8-967f-4a63-bd60-f5126992845f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
68367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2163268367
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.3687814566
Short name T1803
Test name
Test status
Simulation time 211233702 ps
CPU time 0.82 seconds
Started Jul 18 05:45:15 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206620 kb
Host smart-b9c69b1b-08eb-4f45-abad-08ea69ef6199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36878
14566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.3687814566
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.351280114
Short name T2280
Test name
Test status
Simulation time 167100605 ps
CPU time 0.9 seconds
Started Jul 18 05:45:14 PM PDT 24
Finished Jul 18 05:45:29 PM PDT 24
Peak memory 206224 kb
Host smart-2d2833bd-efe8-4833-9435-177b0dde77e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35128
0114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.351280114
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3760924680
Short name T1126
Test name
Test status
Simulation time 162346573 ps
CPU time 0.86 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206636 kb
Host smart-7cc7341e-3f1c-491b-a1c9-9b4b79865448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37609
24680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3760924680
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.28905737
Short name T674
Test name
Test status
Simulation time 197717882 ps
CPU time 0.93 seconds
Started Jul 18 05:45:15 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206612 kb
Host smart-4927a405-3ca0-4862-a816-e43c0e32a3c9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=28905737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.28905737
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.601936475
Short name T1433
Test name
Test status
Simulation time 149902200 ps
CPU time 0.78 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:31 PM PDT 24
Peak memory 206604 kb
Host smart-2f0bef45-017f-495c-ad03-e9d7c0a4c032
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60193
6475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.601936475
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1502119717
Short name T1124
Test name
Test status
Simulation time 41498395 ps
CPU time 0.66 seconds
Started Jul 18 05:45:11 PM PDT 24
Finished Jul 18 05:45:26 PM PDT 24
Peak memory 206616 kb
Host smart-afc04df6-f0db-4de9-88a5-4bb70a8d1ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15021
19717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1502119717
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.553565753
Short name T1699
Test name
Test status
Simulation time 7140087813 ps
CPU time 16.53 seconds
Started Jul 18 05:45:15 PM PDT 24
Finished Jul 18 05:45:47 PM PDT 24
Peak memory 206880 kb
Host smart-6214078e-941b-4cc1-a0b8-54afcfe6ff00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55356
5753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.553565753
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.3567638000
Short name T1722
Test name
Test status
Simulation time 205435735 ps
CPU time 0.83 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206628 kb
Host smart-226835f1-2fe0-4283-b184-532a5b084b6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35676
38000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.3567638000
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.312612361
Short name T1387
Test name
Test status
Simulation time 189840565 ps
CPU time 0.83 seconds
Started Jul 18 05:45:18 PM PDT 24
Finished Jul 18 05:45:35 PM PDT 24
Peak memory 206808 kb
Host smart-9d708cda-c30e-466a-bc79-a342ed1eef52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31261
2361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.312612361
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1286516456
Short name T162
Test name
Test status
Simulation time 8801403238 ps
CPU time 55.98 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:46:27 PM PDT 24
Peak memory 206932 kb
Host smart-ca404606-7c87-456e-8cea-8e64b79033cf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1286516456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1286516456
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.3061922225
Short name T1597
Test name
Test status
Simulation time 7784398091 ps
CPU time 44.49 seconds
Started Jul 18 05:45:14 PM PDT 24
Finished Jul 18 05:46:14 PM PDT 24
Peak memory 206920 kb
Host smart-72840b7a-26ac-498a-9600-5adc597f106d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3061922225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.3061922225
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.2789763826
Short name T986
Test name
Test status
Simulation time 244899840 ps
CPU time 0.92 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206636 kb
Host smart-45ee6a4a-1bdc-4e9f-be2d-c70eb83369cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
63826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.2789763826
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.4049236736
Short name T1065
Test name
Test status
Simulation time 165554272 ps
CPU time 0.81 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206616 kb
Host smart-01afdff0-a51b-450b-98ff-bfb42979c87f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40492
36736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.4049236736
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.4052108034
Short name T2610
Test name
Test status
Simulation time 150211150 ps
CPU time 0.77 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:36 PM PDT 24
Peak memory 206648 kb
Host smart-165819dd-2374-4647-a48c-b40124f0f6a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40521
08034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.4052108034
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2594978453
Short name T542
Test name
Test status
Simulation time 167062942 ps
CPU time 0.82 seconds
Started Jul 18 05:45:16 PM PDT 24
Finished Jul 18 05:45:32 PM PDT 24
Peak memory 206620 kb
Host smart-e3e88080-f90f-4786-8fc8-9dd135a9738b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25949
78453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2594978453
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.1219172274
Short name T441
Test name
Test status
Simulation time 152033647 ps
CPU time 0.78 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206652 kb
Host smart-9a15a6be-608f-417e-8eb4-dd1d045135d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
72274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.1219172274
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1060341476
Short name T685
Test name
Test status
Simulation time 296282522 ps
CPU time 1.05 seconds
Started Jul 18 05:45:22 PM PDT 24
Finished Jul 18 05:45:40 PM PDT 24
Peak memory 206640 kb
Host smart-18f1b210-29fe-4852-a08f-2e09c6eaedcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10603
41476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1060341476
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.608643638
Short name T2486
Test name
Test status
Simulation time 4455160394 ps
CPU time 32.22 seconds
Started Jul 18 05:45:18 PM PDT 24
Finished Jul 18 05:46:06 PM PDT 24
Peak memory 206844 kb
Host smart-fbf16259-26ae-4588-9bc2-6c2ab9d25c88
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=608643638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.608643638
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2245146589
Short name T456
Test name
Test status
Simulation time 171213337 ps
CPU time 0.76 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:23 PM PDT 24
Peak memory 206732 kb
Host smart-f1008a2d-797e-4c12-93e0-8752daf8c510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22451
46589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2245146589
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3715492009
Short name T603
Test name
Test status
Simulation time 169208014 ps
CPU time 0.82 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:45:37 PM PDT 24
Peak memory 206468 kb
Host smart-20751ed2-49a9-483c-9a1e-f0198a0fbae3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37154
92009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3715492009
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.1441166785
Short name T438
Test name
Test status
Simulation time 1322774678 ps
CPU time 2.64 seconds
Started Jul 18 05:45:10 PM PDT 24
Finished Jul 18 05:45:25 PM PDT 24
Peak memory 206872 kb
Host smart-cfbf1c49-d084-48e5-a3ab-efd275c70df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411
66785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.1441166785
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.563470070
Short name T411
Test name
Test status
Simulation time 6256578363 ps
CPU time 163.07 seconds
Started Jul 18 05:45:19 PM PDT 24
Finished Jul 18 05:48:19 PM PDT 24
Peak memory 206844 kb
Host smart-73d4f29d-4fa5-46f0-a711-7d26c6418835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56347
0070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.563470070
Directory /workspace/9.usbdev_streaming_out/latest
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