Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	76730	1		T1	3		T2	4		T3	4
all_values[1]	76730	1		T1	3		T2	4		T3	4
all_values[2]	76730	1		T1	3		T2	4		T3	4
all_values[3]	76730	1		T1	3		T2	4		T3	4
all_values[4]	76730	1		T1	3		T2	4		T3	4
all_values[5]	76730	1		T1	3		T2	4		T3	4
all_values[6]	76730	1		T1	3		T2	4		T3	4
all_values[7]	76730	1		T1	3		T2	4		T3	4
all_values[8]	76730	1		T1	3		T2	4		T3	4
all_values[9]	76730	1		T1	3		T2	4		T3	4
all_values[10]	76730	1		T1	3		T2	4		T3	4
all_values[11]	76730	1		T1	3		T2	4		T3	4
all_values[12]	76730	1		T1	3		T2	4		T3	4
all_values[13]	76730	1		T1	3		T2	4		T3	4
all_values[14]	76730	1		T1	3		T2	4		T3	4
all_values[15]	76730	1		T1	3		T2	4		T3	4
all_values[16]	76730	1		T1	3		T2	4		T3	4
all_values[17]	76730	1		T1	3		T2	4		T3	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1374278	1		T1	51		T2	72		T3	72
auto[1]	6862	1		T1	3		T33	5		T7	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1376335	1		T1	54		T2	72		T3	72
auto[1]	4805	1		T199	124		T196	50		T197	77

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	75761	1		T2	4		T3	4		T30	3
all_values[0]	auto[0]	auto[1]	147	1		T199	5		T196	4		T197	3
all_values[0]	auto[1]	auto[0]	691	1		T1	3		T18	3		T55	4
all_values[0]	auto[1]	auto[1]	131	1		T199	3		T197	2		T198	2
all_values[1]	auto[0]	auto[0]	74951	1		T1	3		T2	4		T3	4
all_values[1]	auto[0]	auto[1]	143	1		T199	4		T197	1		T198	7
all_values[1]	auto[1]	auto[0]	1525	1		T7	2		T17	14		T41	2
all_values[1]	auto[1]	auto[1]	111	1		T197	4		T198	1		T281	1
all_values[2]	auto[0]	auto[0]	76339	1		T1	3		T2	4		T3	4
all_values[2]	auto[0]	auto[1]	130	1		T199	2		T197	3		T198	4
all_values[2]	auto[1]	auto[0]	135	1		T46	2		T47	2		T48	2
all_values[2]	auto[1]	auto[1]	126	1		T199	5		T197	2		T198	4
all_values[3]	auto[0]	auto[0]	74944	1		T1	3		T2	4		T3	4
all_values[3]	auto[0]	auto[1]	123	1		T199	4		T196	1		T198	1
all_values[3]	auto[1]	auto[0]	1521	1		T69	1485		T199	1		T196	1
all_values[3]	auto[1]	auto[1]	142	1		T199	1		T196	3		T197	3
all_values[4]	auto[0]	auto[0]	76434	1		T1	3		T2	4		T3	4
all_values[4]	auto[0]	auto[1]	137	1		T199	1		T197	4		T198	4
all_values[4]	auto[1]	auto[0]	36	1		T70	2		T290	5		T291	2
all_values[4]	auto[1]	auto[1]	123	1		T199	7		T196	4		T198	4
all_values[5]	auto[0]	auto[0]	76447	1		T1	3		T2	4		T3	4
all_values[5]	auto[0]	auto[1]	134	1		T199	4		T197	1		T198	5
all_values[5]	auto[1]	auto[0]	38	1		T199	1		T281	2		T290	1
all_values[5]	auto[1]	auto[1]	111	1		T199	3		T196	3		T197	4
all_values[6]	auto[0]	auto[0]	76429	1		T1	3		T2	4		T3	4
all_values[6]	auto[0]	auto[1]	170	1		T199	5		T196	4		T197	1
all_values[6]	auto[1]	auto[0]	15	1		T197	1		T198	2		T290	1
all_values[6]	auto[1]	auto[1]	116	1		T199	3		T196	1		T197	3
all_values[7]	auto[0]	auto[0]	76413	1		T1	3		T2	4		T3	4
all_values[7]	auto[0]	auto[1]	141	1		T199	5		T196	1		T197	3
all_values[7]	auto[1]	auto[0]	31	1		T57	2		T58	2		T59	2
all_values[7]	auto[1]	auto[1]	145	1		T199	3		T196	4		T197	1
all_values[8]	auto[0]	auto[0]	76430	1		T1	3		T2	4		T3	4
all_values[8]	auto[0]	auto[1]	138	1		T199	4		T196	4		T198	5
all_values[8]	auto[1]	auto[0]	38	1		T62	11		T282	2		T292	1
all_values[8]	auto[1]	auto[1]	124	1		T199	3		T196	1		T197	5
all_values[9]	auto[0]	auto[0]	76416	1		T1	3		T2	4		T3	4
all_values[9]	auto[0]	auto[1]	107	1		T199	2		T197	3		T198	4
all_values[9]	auto[1]	auto[0]	55	1		T33	5		T53	5		T68	5
all_values[9]	auto[1]	auto[1]	152	1		T199	5		T197	1		T198	2
all_values[10]	auto[0]	auto[0]	76428	1		T1	3		T2	4		T3	4
all_values[10]	auto[0]	auto[1]	117	1		T199	3		T197	1		T198	3
all_values[10]	auto[1]	auto[0]	34	1		T199	3		T196	4		T281	1
all_values[10]	auto[1]	auto[1]	151	1		T199	1		T197	4		T198	5
all_values[11]	auto[0]	auto[0]	76334	1		T1	3		T2	4		T3	4
all_values[11]	auto[0]	auto[1]	147	1		T199	2		T197	3		T198	4
all_values[11]	auto[1]	auto[0]	128	1		T54	2		T74	2		T75	2
all_values[11]	auto[1]	auto[1]	121	1		T199	6		T196	4		T197	1
all_values[12]	auto[0]	auto[0]	76415	1		T1	3		T2	4		T3	4
all_values[12]	auto[0]	auto[1]	148	1		T199	6		T196	2		T197	4
all_values[12]	auto[1]	auto[0]	30	1		T78	3		T79	3		T80	3
all_values[12]	auto[1]	auto[1]	137	1		T199	2		T196	3		T197	1
all_values[13]	auto[0]	auto[0]	76435	1		T1	3		T2	4		T3	4
all_values[13]	auto[0]	auto[1]	130	1		T199	4		T197	3		T198	2
all_values[13]	auto[1]	auto[0]	23	1		T199	1		T196	1		T293	4
all_values[13]	auto[1]	auto[1]	142	1		T199	1		T197	1		T198	6
all_values[14]	auto[0]	auto[0]	76438	1		T1	3		T2	4		T3	4
all_values[14]	auto[0]	auto[1]	111	1		T199	1		T198	1		T281	3
all_values[14]	auto[1]	auto[0]	29	1		T196	1		T294	1		T295	2
all_values[14]	auto[1]	auto[1]	152	1		T199	6		T197	3		T198	7
all_values[15]	auto[0]	auto[0]	76425	1		T1	3		T2	4		T3	4
all_values[15]	auto[0]	auto[1]	140	1		T199	5		T196	4		T198	5
all_values[15]	auto[1]	auto[0]	37	1		T199	1		T198	2		T290	1
all_values[15]	auto[1]	auto[1]	128	1		T199	2		T196	1		T197	4
all_values[16]	auto[0]	auto[0]	76418	1		T1	3		T2	4		T3	4
all_values[16]	auto[0]	auto[1]	107	1		T199	3		T197	4		T198	2
all_values[16]	auto[1]	auto[0]	54	1		T71	8		T72	8		T73	8
all_values[16]	auto[1]	auto[1]	151	1		T199	5		T196	3		T198	6
all_values[17]	auto[0]	auto[0]	76430	1		T1	3		T2	4		T3	4
all_values[17]	auto[0]	auto[1]	121	1		T199	3		T198	7		T281	6
all_values[17]	auto[1]	auto[0]	28	1		T64	2		T281	1		T293	1
all_values[17]	auto[1]	auto[1]	151	1		T199	5		T196	3		T197	4