Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	76730	1		T1	3		T2	4		T3	4
all_pins[1]	76730	1		T1	3		T2	4		T3	4
all_pins[2]	76730	1		T1	3		T2	4		T3	4
all_pins[3]	76730	1		T1	3		T2	4		T3	4
all_pins[4]	76730	1		T1	3		T2	4		T3	4
all_pins[5]	76730	1		T1	3		T2	4		T3	4
all_pins[6]	76730	1		T1	3		T2	4		T3	4
all_pins[7]	76730	1		T1	3		T2	4		T3	4
all_pins[8]	76730	1		T1	3		T2	4		T3	4
all_pins[9]	76730	1		T1	3		T2	4		T3	4
all_pins[10]	76730	1		T1	3		T2	4		T3	4
all_pins[11]	76730	1		T1	3		T2	4		T3	4
all_pins[12]	76730	1		T1	3		T2	4		T3	4
all_pins[13]	76730	1		T1	3		T2	4		T3	4
all_pins[14]	76730	1		T1	3		T2	4		T3	4
all_pins[15]	76730	1		T1	3		T2	4		T3	4
all_pins[16]	76730	1		T1	3		T2	4		T3	4
all_pins[17]	76730	1		T1	3		T2	4		T3	4

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1378834	1		T1	54		T2	72		T3	72
values[0x1]	2306	1		T33	2		T7	1		T17	12
transitions[0x0=>0x1]	2003	1		T33	2		T7	1		T17	12
transitions[0x1=>0x0]	2018	1		T33	2		T7	1		T17	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	76632	1		T1	3		T2	4		T3	4
all_pins[0]	values[0x1]	98	1		T55	1		T56	1		T296	1
all_pins[0]	transitions[0x0=>0x1]	87	1		T55	1		T56	1		T296	1
all_pins[0]	transitions[0x1=>0x0]	984	1		T7	1		T17	12		T41	1
all_pins[1]	values[0x0]	75735	1		T1	3		T2	4		T3	4
all_pins[1]	values[0x1]	995	1		T7	1		T17	12		T41	1
all_pins[1]	transitions[0x0=>0x1]	986	1		T7	1		T17	12		T41	1
all_pins[1]	transitions[0x1=>0x0]	108	1		T46	1		T47	1		T48	1
all_pins[2]	values[0x0]	76613	1		T1	3		T2	4		T3	4
all_pins[2]	values[0x1]	117	1		T46	1		T47	1		T48	1
all_pins[2]	transitions[0x0=>0x1]	99	1		T46	1		T47	1		T48	1
all_pins[2]	transitions[0x1=>0x0]	50	1		T69	1		T199	1		T196	2
all_pins[3]	values[0x0]	76662	1		T1	3		T2	4		T3	4
all_pins[3]	values[0x1]	68	1		T69	1		T199	1		T196	2
all_pins[3]	transitions[0x0=>0x1]	53	1		T69	1		T197	2		T198	1
all_pins[3]	transitions[0x1=>0x0]	33	1		T70	1		T199	2		T196	1
all_pins[4]	values[0x0]	76682	1		T1	3		T2	4		T3	4
all_pins[4]	values[0x1]	48	1		T70	1		T199	3		T196	3
all_pins[4]	transitions[0x0=>0x1]	37	1		T70	1		T199	2		T196	1
all_pins[4]	transitions[0x1=>0x0]	40	1		T199	1		T197	2		T198	2
all_pins[5]	values[0x0]	76679	1		T1	3		T2	4		T3	4
all_pins[5]	values[0x1]	51	1		T199	2		T196	2		T197	2
all_pins[5]	transitions[0x0=>0x1]	46	1		T196	2		T197	2		T198	2
all_pins[5]	transitions[0x1=>0x0]	54	1		T198	3		T281	2		T293	3
all_pins[6]	values[0x0]	76671	1		T1	3		T2	4		T3	4
all_pins[6]	values[0x1]	59	1		T199	2		T198	3		T281	2
all_pins[6]	transitions[0x0=>0x1]	47	1		T199	2		T198	3		T281	2
all_pins[6]	transitions[0x1=>0x0]	44	1		T57	1		T58	1		T59	1
all_pins[7]	values[0x0]	76674	1		T1	3		T2	4		T3	4
all_pins[7]	values[0x1]	56	1		T57	1		T58	1		T59	1
all_pins[7]	transitions[0x0=>0x1]	44	1		T57	1		T58	1		T59	1
all_pins[7]	transitions[0x1=>0x0]	46	1		T62	1		T196	1		T197	2
all_pins[8]	values[0x0]	76672	1		T1	3		T2	4		T3	4
all_pins[8]	values[0x1]	58	1		T62	1		T196	1		T197	2
all_pins[8]	transitions[0x0=>0x1]	46	1		T62	1		T196	1		T197	2
all_pins[8]	transitions[0x1=>0x0]	78	1		T33	2		T53	2		T68	2
all_pins[9]	values[0x0]	76640	1		T1	3		T2	4		T3	4
all_pins[9]	values[0x1]	90	1		T33	2		T53	2		T68	2
all_pins[9]	transitions[0x0=>0x1]	77	1		T33	2		T53	2		T68	2
all_pins[9]	transitions[0x1=>0x0]	55	1		T198	3		T281	3		T282	2
all_pins[10]	values[0x0]	76662	1		T1	3		T2	4		T3	4
all_pins[10]	values[0x1]	68	1		T197	1		T198	3		T281	3
all_pins[10]	transitions[0x0=>0x1]	47	1		T197	1		T198	3		T281	2
all_pins[10]	transitions[0x1=>0x0]	105	1		T54	1		T74	1		T75	1
all_pins[11]	values[0x0]	76604	1		T1	3		T2	4		T3	4
all_pins[11]	values[0x1]	126	1		T54	1		T74	1		T75	1
all_pins[11]	transitions[0x0=>0x1]	110	1		T54	1		T74	1		T75	1
all_pins[11]	transitions[0x1=>0x0]	59	1		T78	1		T79	1		T80	1
all_pins[12]	values[0x0]	76655	1		T1	3		T2	4		T3	4
all_pins[12]	values[0x1]	75	1		T78	1		T79	1		T80	1
all_pins[12]	transitions[0x0=>0x1]	50	1		T78	1		T79	1		T80	1
all_pins[12]	transitions[0x1=>0x0]	57	1		T199	1		T197	1		T198	4
all_pins[13]	values[0x0]	76648	1		T1	3		T2	4		T3	4
all_pins[13]	values[0x1]	82	1		T199	1		T197	1		T198	4
all_pins[13]	transitions[0x0=>0x1]	54	1		T199	1		T197	1		T198	3
all_pins[13]	transitions[0x1=>0x0]	45	1		T199	2		T197	2		T198	1
all_pins[14]	values[0x0]	76657	1		T1	3		T2	4		T3	4
all_pins[14]	values[0x1]	73	1		T199	2		T197	2		T198	2
all_pins[14]	transitions[0x0=>0x1]	47	1		T199	2		T197	2		T198	2
all_pins[14]	transitions[0x1=>0x0]	51	1		T196	1		T198	1		T282	2
all_pins[15]	values[0x0]	76653	1		T1	3		T2	4		T3	4
all_pins[15]	values[0x1]	77	1		T196	1		T198	1		T282	5
all_pins[15]	transitions[0x0=>0x1]	59	1		T196	1		T198	1		T282	4
all_pins[15]	transitions[0x1=>0x0]	76	1		T71	4		T72	4		T73	4
all_pins[16]	values[0x0]	76636	1		T1	3		T2	4		T3	4
all_pins[16]	values[0x1]	94	1		T71	4		T72	4		T73	4
all_pins[16]	transitions[0x0=>0x1]	72	1		T71	4		T72	4		T73	4
all_pins[16]	transitions[0x1=>0x0]	49	1		T64	1		T197	2		T282	1
all_pins[17]	values[0x0]	76659	1		T1	3		T2	4		T3	4
all_pins[17]	values[0x1]	71	1		T64	1		T199	3		T196	1
all_pins[17]	transitions[0x0=>0x1]	42	1		T64	1		T196	1		T197	1
all_pins[17]	transitions[0x1=>0x0]	84	1		T55	1		T56	1		T296	1