Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.56 97.84 93.79 97.44 75.00 96.26 98.17 96.40


Total test records in report: 2847
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T2765 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3748724453 Jul 20 05:51:13 PM PDT 24 Jul 20 05:51:18 PM PDT 24 503092740 ps
T2766 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.352394414 Jul 20 05:51:28 PM PDT 24 Jul 20 05:51:30 PM PDT 24 58449406 ps
T298 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3710085444 Jul 20 05:51:26 PM PDT 24 Jul 20 05:51:28 PM PDT 24 49238640 ps
T300 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2258328201 Jul 20 05:51:09 PM PDT 24 Jul 20 05:51:10 PM PDT 24 44270138 ps
T2767 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.680669455 Jul 20 05:51:14 PM PDT 24 Jul 20 05:51:17 PM PDT 24 256677303 ps
T304 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2638125378 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:24 PM PDT 24 45809567 ps
T301 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3879078222 Jul 20 05:51:41 PM PDT 24 Jul 20 05:51:42 PM PDT 24 31806626 ps
T226 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.372208420 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:27 PM PDT 24 120396769 ps
T287 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.549829836 Jul 20 05:51:29 PM PDT 24 Jul 20 05:51:37 PM PDT 24 1740831498 ps
T2768 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1927164215 Jul 20 05:51:25 PM PDT 24 Jul 20 05:51:29 PM PDT 24 77832066 ps
T2769 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1483248334 Jul 20 05:51:50 PM PDT 24 Jul 20 05:51:51 PM PDT 24 70805066 ps
T2770 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1197403222 Jul 20 05:51:20 PM PDT 24 Jul 20 05:51:21 PM PDT 24 60567500 ps
T2771 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2740023245 Jul 20 05:51:27 PM PDT 24 Jul 20 05:51:30 PM PDT 24 37503575 ps
T2772 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.340781867 Jul 20 05:51:25 PM PDT 24 Jul 20 05:51:29 PM PDT 24 332914441 ps
T285 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3736042545 Jul 20 05:51:27 PM PDT 24 Jul 20 05:51:32 PM PDT 24 654708157 ps
T2773 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2532484597 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:25 PM PDT 24 138474537 ps
T2774 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1628361165 Jul 20 05:51:36 PM PDT 24 Jul 20 05:51:37 PM PDT 24 52634492 ps
T262 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.835608217 Jul 20 05:51:17 PM PDT 24 Jul 20 05:51:18 PM PDT 24 45987629 ps
T2775 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1670956056 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:27 PM PDT 24 119096175 ps
T263 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.754718283 Jul 20 05:51:38 PM PDT 24 Jul 20 05:51:40 PM PDT 24 58984165 ps
T2776 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2357818311 Jul 20 05:51:21 PM PDT 24 Jul 20 05:51:24 PM PDT 24 404200667 ps
T2777 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2463393488 Jul 20 05:51:38 PM PDT 24 Jul 20 05:51:40 PM PDT 24 62480412 ps
T2778 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3497620703 Jul 20 05:51:44 PM PDT 24 Jul 20 05:51:47 PM PDT 24 177112264 ps
T2779 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2623763984 Jul 20 05:51:28 PM PDT 24 Jul 20 05:51:32 PM PDT 24 95054715 ps
T2780 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2283686909 Jul 20 05:51:26 PM PDT 24 Jul 20 05:51:30 PM PDT 24 107219485 ps
T2781 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1509860865 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:28 PM PDT 24 264565537 ps
T2782 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1689269546 Jul 20 05:51:29 PM PDT 24 Jul 20 05:51:34 PM PDT 24 259791673 ps
T2783 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1707530297 Jul 20 05:51:08 PM PDT 24 Jul 20 05:51:09 PM PDT 24 71969077 ps
T288 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.490311733 Jul 20 05:51:25 PM PDT 24 Jul 20 05:51:32 PM PDT 24 826403125 ps
T2784 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2419465443 Jul 20 05:51:20 PM PDT 24 Jul 20 05:51:22 PM PDT 24 172236526 ps
T2785 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4219879249 Jul 20 05:51:32 PM PDT 24 Jul 20 05:51:35 PM PDT 24 232205974 ps
T2786 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2299699876 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:26 PM PDT 24 129972542 ps
T2787 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4179149757 Jul 20 05:51:31 PM PDT 24 Jul 20 05:51:33 PM PDT 24 38967439 ps
T2788 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3226942801 Jul 20 05:51:21 PM PDT 24 Jul 20 05:51:25 PM PDT 24 198321235 ps
T2789 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3172301578 Jul 20 05:51:14 PM PDT 24 Jul 20 05:51:19 PM PDT 24 187430701 ps
T2790 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4191059009 Jul 20 05:51:29 PM PDT 24 Jul 20 05:51:33 PM PDT 24 89728163 ps
T2791 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1002078762 Jul 20 05:51:28 PM PDT 24 Jul 20 05:51:32 PM PDT 24 95162720 ps
T2792 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2719615719 Jul 20 05:51:36 PM PDT 24 Jul 20 05:51:37 PM PDT 24 109207901 ps
T2793 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4039432933 Jul 20 05:51:42 PM PDT 24 Jul 20 05:51:43 PM PDT 24 94423042 ps
T2794 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3965762890 Jul 20 05:51:41 PM PDT 24 Jul 20 05:51:42 PM PDT 24 43136926 ps
T2795 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1250384081 Jul 20 05:51:34 PM PDT 24 Jul 20 05:51:37 PM PDT 24 374741978 ps
T2796 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2016651320 Jul 20 05:51:25 PM PDT 24 Jul 20 05:51:34 PM PDT 24 552559656 ps
T2797 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1644836073 Jul 20 05:51:19 PM PDT 24 Jul 20 05:51:21 PM PDT 24 50368631 ps
T2798 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3155065497 Jul 20 05:51:43 PM PDT 24 Jul 20 05:51:46 PM PDT 24 198692038 ps
T289 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3752308986 Jul 20 05:51:25 PM PDT 24 Jul 20 05:51:32 PM PDT 24 673949112 ps
T2799 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2629411107 Jul 20 05:51:21 PM PDT 24 Jul 20 05:51:23 PM PDT 24 91661804 ps
T2800 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.980784830 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:25 PM PDT 24 132234086 ps
T2801 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2894117115 Jul 20 05:51:33 PM PDT 24 Jul 20 05:51:36 PM PDT 24 92862746 ps
T2802 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.368030065 Jul 20 05:51:48 PM PDT 24 Jul 20 05:51:50 PM PDT 24 118585707 ps
T286 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1374770488 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:28 PM PDT 24 1372870338 ps
T2803 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2167875099 Jul 20 05:51:30 PM PDT 24 Jul 20 05:51:39 PM PDT 24 2082986230 ps
T2804 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2772589431 Jul 20 05:51:21 PM PDT 24 Jul 20 05:51:25 PM PDT 24 567499091 ps
T2805 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4052694803 Jul 20 05:51:46 PM PDT 24 Jul 20 05:51:48 PM PDT 24 95949991 ps
T2806 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.618308829 Jul 20 05:51:51 PM PDT 24 Jul 20 05:51:52 PM PDT 24 39509609 ps
T227 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3443392747 Jul 20 05:51:26 PM PDT 24 Jul 20 05:51:30 PM PDT 24 113420675 ps
T2807 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1367566403 Jul 20 05:51:45 PM PDT 24 Jul 20 05:51:46 PM PDT 24 65748515 ps
T2808 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2263973812 Jul 20 05:51:29 PM PDT 24 Jul 20 05:51:32 PM PDT 24 40672515 ps
T2809 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4139361807 Jul 20 05:51:37 PM PDT 24 Jul 20 05:51:38 PM PDT 24 41073903 ps
T2810 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2566105877 Jul 20 05:51:27 PM PDT 24 Jul 20 05:51:36 PM PDT 24 157612294 ps
T2811 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.862961570 Jul 20 05:51:28 PM PDT 24 Jul 20 05:51:31 PM PDT 24 43270881 ps
T2812 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3225188417 Jul 20 05:51:18 PM PDT 24 Jul 20 05:51:20 PM PDT 24 53132221 ps
T2813 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3920128988 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:28 PM PDT 24 520448346 ps
T228 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2415221173 Jul 20 05:51:44 PM PDT 24 Jul 20 05:51:47 PM PDT 24 223252406 ps
T2814 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.409224584 Jul 20 05:51:31 PM PDT 24 Jul 20 05:51:34 PM PDT 24 52959512 ps
T2815 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2301521397 Jul 20 05:51:20 PM PDT 24 Jul 20 05:51:22 PM PDT 24 97789060 ps
T2816 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4139134301 Jul 20 05:51:45 PM PDT 24 Jul 20 05:51:47 PM PDT 24 35856461 ps
T2817 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.897030216 Jul 20 05:51:46 PM PDT 24 Jul 20 05:51:52 PM PDT 24 992302126 ps
T2818 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2981856595 Jul 20 05:51:28 PM PDT 24 Jul 20 05:51:32 PM PDT 24 59610294 ps
T2819 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.879076339 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:26 PM PDT 24 39957793 ps
T2820 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.23489136 Jul 20 05:51:39 PM PDT 24 Jul 20 05:51:40 PM PDT 24 114029550 ps
T2821 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2834894786 Jul 20 05:51:50 PM PDT 24 Jul 20 05:51:52 PM PDT 24 64804525 ps
T2822 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1770332024 Jul 20 05:51:33 PM PDT 24 Jul 20 05:51:34 PM PDT 24 106254474 ps
T2823 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2252759352 Jul 20 05:51:29 PM PDT 24 Jul 20 05:51:37 PM PDT 24 36814275 ps
T2824 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3211651837 Jul 20 05:51:28 PM PDT 24 Jul 20 05:51:31 PM PDT 24 56608391 ps
T2825 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.965466842 Jul 20 05:51:27 PM PDT 24 Jul 20 05:51:30 PM PDT 24 162157192 ps
T2826 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3306261067 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:26 PM PDT 24 57200822 ps
T2827 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3631287569 Jul 20 05:51:53 PM PDT 24 Jul 20 05:51:54 PM PDT 24 44021766 ps
T2828 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.117986063 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:26 PM PDT 24 181350126 ps
T2829 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2687822869 Jul 20 05:51:12 PM PDT 24 Jul 20 05:51:15 PM PDT 24 164758157 ps
T2830 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3896611669 Jul 20 05:51:25 PM PDT 24 Jul 20 05:51:34 PM PDT 24 64269651 ps
T2831 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.820645724 Jul 20 05:51:27 PM PDT 24 Jul 20 05:51:30 PM PDT 24 97034370 ps
T2832 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2802737983 Jul 20 05:51:26 PM PDT 24 Jul 20 05:51:29 PM PDT 24 58636079 ps
T2833 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.802425456 Jul 20 05:51:18 PM PDT 24 Jul 20 05:51:21 PM PDT 24 119837804 ps
T2834 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3267807990 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:27 PM PDT 24 282163489 ps
T2835 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1996281599 Jul 20 05:51:44 PM PDT 24 Jul 20 05:51:46 PM PDT 24 31712144 ps
T2836 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.268285238 Jul 20 05:51:40 PM PDT 24 Jul 20 05:51:41 PM PDT 24 37941382 ps
T2837 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1181970835 Jul 20 05:51:29 PM PDT 24 Jul 20 05:51:33 PM PDT 24 107327668 ps
T2838 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2101596572 Jul 20 05:51:30 PM PDT 24 Jul 20 05:51:35 PM PDT 24 100045484 ps
T2839 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1280573280 Jul 20 05:51:29 PM PDT 24 Jul 20 05:51:33 PM PDT 24 77534951 ps
T2840 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.236656482 Jul 20 05:51:56 PM PDT 24 Jul 20 05:51:57 PM PDT 24 52653820 ps
T2841 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.528684050 Jul 20 05:51:23 PM PDT 24 Jul 20 05:51:28 PM PDT 24 152581979 ps
T2842 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.429120763 Jul 20 05:51:34 PM PDT 24 Jul 20 05:51:36 PM PDT 24 167626168 ps
T2843 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2589014900 Jul 20 05:51:28 PM PDT 24 Jul 20 05:51:40 PM PDT 24 1415146824 ps
T2844 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3347416725 Jul 20 05:51:19 PM PDT 24 Jul 20 05:51:21 PM PDT 24 67537786 ps
T2845 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1198225509 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:29 PM PDT 24 923478117 ps
T2846 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.631372689 Jul 20 05:51:41 PM PDT 24 Jul 20 05:51:42 PM PDT 24 59975515 ps
T2847 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2868158628 Jul 20 05:51:22 PM PDT 24 Jul 20 05:51:27 PM PDT 24 372629236 ps

Test location /workspace/coverage/default/10.usbdev_device_address.2084629992
Short name T27
Test name
Test status
Simulation time 10566518653 ps
CPU time 22.97 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:32 PM PDT 24
Peak memory 206920 kb
Host smart-ac605b66-afcd-416f-8d5c-9ce93f077be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20846
29992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.2084629992
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3180984012
Short name T5
Test name
Test status
Simulation time 6636712950 ps
CPU time 181.88 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206856 kb
Host smart-0a6847c1-1279-46c1-af1f-83898f4005a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31809
84012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3180984012
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3264219374
Short name T198
Test name
Test status
Simulation time 38548204 ps
CPU time 0.69 seconds
Started Jul 20 05:51:53 PM PDT 24
Finished Jul 20 05:51:54 PM PDT 24
Peak memory 206288 kb
Host smart-79527cda-1eb3-4645-855d-70f268533893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3264219374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3264219374
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.209784481
Short name T9
Test name
Test status
Simulation time 23312773262 ps
CPU time 22.69 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:24:08 PM PDT 24
Peak memory 206872 kb
Host smart-c2785c7f-0f28-4def-99b4-d665b82aa9ed
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=209784481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.209784481
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.3066957144
Short name T187
Test name
Test status
Simulation time 786911619 ps
CPU time 4.85 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:35 PM PDT 24
Peak memory 205700 kb
Host smart-a2f10f5f-eb28-4404-b7c6-dac585de7295
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3066957144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.3066957144
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.1232122722
Short name T30
Test name
Test status
Simulation time 164843286 ps
CPU time 0.82 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206652 kb
Host smart-70310486-b0e0-47e2-b2d2-e5b7ba5dc14f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
22722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.1232122722
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.234278889
Short name T293
Test name
Test status
Simulation time 32919755 ps
CPU time 0.69 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206228 kb
Host smart-bc346fba-f8da-42d4-a3dd-d2557788a1d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=234278889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.234278889
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.2701291272
Short name T89
Test name
Test status
Simulation time 9447405383 ps
CPU time 79.95 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206780 kb
Host smart-926f7eb2-9315-4719-9f06-c2a25dc905d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27012
91272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.2701291272
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3240333156
Short name T47
Test name
Test status
Simulation time 180701652 ps
CPU time 0.8 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206664 kb
Host smart-98226b55-342a-4c96-95df-9c4ebbd6700e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32403
33156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3240333156
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2342307095
Short name T106
Test name
Test status
Simulation time 354527201 ps
CPU time 1.2 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:16 PM PDT 24
Peak memory 206652 kb
Host smart-df273859-3f7e-436d-a437-4eea491f6d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23423
07095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2342307095
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.524931158
Short name T218
Test name
Test status
Simulation time 126060298 ps
CPU time 2.18 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:33 PM PDT 24
Peak memory 206588 kb
Host smart-73158e90-2f07-42bf-8818-654435e4a3a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=524931158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.524931158
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1099063310
Short name T45
Test name
Test status
Simulation time 9893633386 ps
CPU time 45.67 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 206940 kb
Host smart-e5da989a-134f-488c-84ff-921b923418cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1099063310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1099063310
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2451352875
Short name T112
Test name
Test status
Simulation time 196133742 ps
CPU time 0.81 seconds
Started Jul 20 06:18:39 PM PDT 24
Finished Jul 20 06:18:41 PM PDT 24
Peak memory 206644 kb
Host smart-f4815549-9347-4cf9-ba7c-01ed3569001a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24513
52875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2451352875
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.4040044102
Short name T11
Test name
Test status
Simulation time 4345130487 ps
CPU time 4.61 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:29 PM PDT 24
Peak memory 206388 kb
Host smart-e4b00d7f-3a15-4f7c-a6a3-3f1072f1c4d8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4040044102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.4040044102
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.753210288
Short name T20
Test name
Test status
Simulation time 64322931 ps
CPU time 0.65 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:10 PM PDT 24
Peak memory 206652 kb
Host smart-3e8fd35e-5693-465b-9481-868b004d58aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75321
0288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.753210288
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.4113927450
Short name T196
Test name
Test status
Simulation time 45213330 ps
CPU time 0.66 seconds
Started Jul 20 05:51:06 PM PDT 24
Finished Jul 20 05:51:07 PM PDT 24
Peak memory 206204 kb
Host smart-3cdd9715-5809-4bcd-8fc2-bd92438582d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4113927450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.4113927450
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2661137528
Short name T201
Test name
Test status
Simulation time 777694830 ps
CPU time 1.57 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:18:26 PM PDT 24
Peak memory 225556 kb
Host smart-0211c2b1-113d-40d7-80dc-b9fd08c060cf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2661137528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2661137528
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.4041883827
Short name T175
Test name
Test status
Simulation time 32032871 ps
CPU time 0.68 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:23:19 PM PDT 24
Peak memory 206700 kb
Host smart-388d37e7-a90f-4a7e-adbf-3aa5d5a5d882
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4041883827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.4041883827
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.1403155695
Short name T81
Test name
Test status
Simulation time 319491219 ps
CPU time 1.03 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:06 PM PDT 24
Peak memory 206660 kb
Host smart-4b2c1735-11f6-4e76-9793-92b4713ab6c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14031
55695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.1403155695
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.1408515049
Short name T52
Test name
Test status
Simulation time 20175157785 ps
CPU time 22.23 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:39 PM PDT 24
Peak memory 206740 kb
Host smart-96aae2ab-c63d-491f-9055-5b20bbc2b013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14085
15049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1408515049
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.2287529856
Short name T49
Test name
Test status
Simulation time 23964844030 ps
CPU time 574.89 seconds
Started Jul 20 06:19:32 PM PDT 24
Finished Jul 20 06:29:08 PM PDT 24
Peak memory 207004 kb
Host smart-4347b840-4b70-4f5f-99c8-9351c0567723
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2287529856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.2287529856
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.2593585700
Short name T251
Test name
Test status
Simulation time 45072701 ps
CPU time 0.96 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 206400 kb
Host smart-a434690d-1c53-43e1-abcb-9cadf454eee4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2593585700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.2593585700
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.394692457
Short name T56
Test name
Test status
Simulation time 244572864 ps
CPU time 0.97 seconds
Started Jul 20 06:19:58 PM PDT 24
Finished Jul 20 06:20:00 PM PDT 24
Peak memory 206648 kb
Host smart-bfde054e-d8b2-41c0-8b6f-cd10eaa29860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39469
2457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.394692457
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.1477716816
Short name T54
Test name
Test status
Simulation time 138643299 ps
CPU time 0.87 seconds
Started Jul 20 06:22:38 PM PDT 24
Finished Jul 20 06:22:41 PM PDT 24
Peak memory 206636 kb
Host smart-f409e5d5-da5b-426d-8cd2-7db0e8805cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14777
16816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.1477716816
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.3879078222
Short name T301
Test name
Test status
Simulation time 31806626 ps
CPU time 0.67 seconds
Started Jul 20 05:51:41 PM PDT 24
Finished Jul 20 05:51:42 PM PDT 24
Peak memory 206288 kb
Host smart-8a73c5ed-224e-4301-9637-16e6b2d5bbb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3879078222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.3879078222
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.2785215210
Short name T15
Test name
Test status
Simulation time 13344396973 ps
CPU time 12.19 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:23 PM PDT 24
Peak memory 206780 kb
Host smart-b2500899-3da1-48fe-b2e8-a976cfcd8ef6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2785215210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.2785215210
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3752308986
Short name T289
Test name
Test status
Simulation time 673949112 ps
CPU time 4.56 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206496 kb
Host smart-83e5e3e6-8bf9-473a-b636-8cad0b99975b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3752308986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3752308986
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.3734892574
Short name T157
Test name
Test status
Simulation time 12832374558 ps
CPU time 279.17 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:25:40 PM PDT 24
Peak memory 206600 kb
Host smart-b6f6cdaa-4cac-4064-ab2e-0092d765f561
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3734892574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.3734892574
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3793614606
Short name T6
Test name
Test status
Simulation time 5545027371 ps
CPU time 53.19 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:22:31 PM PDT 24
Peak memory 206752 kb
Host smart-72ffcc46-732c-4468-b619-543e8b6377db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3793614606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3793614606
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.2227199293
Short name T71
Test name
Test status
Simulation time 550530407 ps
CPU time 1.58 seconds
Started Jul 20 06:17:57 PM PDT 24
Finished Jul 20 06:17:59 PM PDT 24
Peak memory 206652 kb
Host smart-51a2ac5a-1f1b-4c79-ada3-8308f4183f16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22271
99293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.2227199293
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2591701230
Short name T291
Test name
Test status
Simulation time 44843691 ps
CPU time 0.7 seconds
Started Jul 20 05:51:31 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 206204 kb
Host smart-07c0853f-6f08-4c85-bb59-23fced1333e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2591701230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2591701230
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1374770488
Short name T286
Test name
Test status
Simulation time 1372870338 ps
CPU time 5.41 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 206400 kb
Host smart-af3b1423-b802-43b6-80d8-7c3a1c906d55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1374770488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1374770488
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/25.usbdev_device_address.396498544
Short name T94
Test name
Test status
Simulation time 10170699726 ps
CPU time 20.7 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206900 kb
Host smart-a64d02a7-622b-42ba-887a-eefb127fb663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39649
8544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.396498544
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.2710090125
Short name T381
Test name
Test status
Simulation time 1310712984 ps
CPU time 2.89 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:23:57 PM PDT 24
Peak memory 206684 kb
Host smart-dae8a49b-d765-4889-b937-beb620f2c329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27100
90125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.2710090125
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3443392747
Short name T227
Test name
Test status
Simulation time 113420675 ps
CPU time 2.82 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 222840 kb
Host smart-ca8526b8-a3f6-4d54-9b40-0d90ed062b64
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3443392747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3443392747
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1370933555
Short name T62
Test name
Test status
Simulation time 250074451 ps
CPU time 0.97 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:19 PM PDT 24
Peak memory 206648 kb
Host smart-b6b8caf0-1307-4bcf-b708-91bf0d3e2244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13709
33555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1370933555
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.2289821559
Short name T256
Test name
Test status
Simulation time 994455567 ps
CPU time 9.29 seconds
Started Jul 20 05:51:14 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 206388 kb
Host smart-4eba6fa1-da0e-4c76-90f6-f392045728f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2289821559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.2289821559
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.148212332
Short name T68
Test name
Test status
Simulation time 143127764 ps
CPU time 0.76 seconds
Started Jul 20 06:17:49 PM PDT 24
Finished Jul 20 06:17:51 PM PDT 24
Peak memory 206648 kb
Host smart-00fff118-2ba4-461f-9a7d-6bd45a0fa9c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14821
2332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.148212332
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2860436420
Short name T159
Test name
Test status
Simulation time 10011438625 ps
CPU time 57.99 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:19:16 PM PDT 24
Peak memory 206856 kb
Host smart-09acf35e-2843-42ea-b2f5-792bbb7a07d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2860436420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2860436420
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.4149236280
Short name T93
Test name
Test status
Simulation time 9143609871 ps
CPU time 81.95 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206908 kb
Host smart-a547d4aa-ca64-43fd-89c6-542e4f50eafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41492
36280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.4149236280
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1776212740
Short name T36
Test name
Test status
Simulation time 37084757 ps
CPU time 0.66 seconds
Started Jul 20 06:22:53 PM PDT 24
Finished Jul 20 06:22:57 PM PDT 24
Peak memory 206632 kb
Host smart-e70808eb-ebf1-4043-9f9c-047aad8293db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17762
12740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1776212740
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1125978294
Short name T440
Test name
Test status
Simulation time 141673747 ps
CPU time 0.78 seconds
Started Jul 20 06:18:35 PM PDT 24
Finished Jul 20 06:18:37 PM PDT 24
Peak memory 206316 kb
Host smart-fc713456-9830-4e9d-a5eb-e7cc0918e717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11259
78294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1125978294
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.4201582841
Short name T2187
Test name
Test status
Simulation time 23322469836 ps
CPU time 23.1 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:27 PM PDT 24
Peak memory 206776 kb
Host smart-4a7a4327-dbb8-466f-abda-c19033f428d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42015
82841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.4201582841
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1960047012
Short name T559
Test name
Test status
Simulation time 279154391 ps
CPU time 2.07 seconds
Started Jul 20 06:17:49 PM PDT 24
Finished Jul 20 06:17:52 PM PDT 24
Peak memory 206920 kb
Host smart-6c5f8571-35cd-40db-bc81-537c9341f122
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19600
47012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1960047012
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.2114405726
Short name T87
Test name
Test status
Simulation time 145568681 ps
CPU time 0.77 seconds
Started Jul 20 06:18:51 PM PDT 24
Finished Jul 20 06:18:52 PM PDT 24
Peak memory 206588 kb
Host smart-09305bdd-af02-44a0-a6b4-f7fcea66f917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21144
05726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.2114405726
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.734218032
Short name T59
Test name
Test status
Simulation time 173607682 ps
CPU time 0.78 seconds
Started Jul 20 06:17:49 PM PDT 24
Finished Jul 20 06:17:51 PM PDT 24
Peak memory 206776 kb
Host smart-9095fb4b-dc3d-46ae-b0a0-d83c39acef87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73421
8032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.734218032
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.1631129950
Short name T69
Test name
Test status
Simulation time 4172277691 ps
CPU time 8.85 seconds
Started Jul 20 06:17:57 PM PDT 24
Finished Jul 20 06:18:06 PM PDT 24
Peak memory 206840 kb
Host smart-b9262808-28f5-43f6-868b-6fbc8f6715bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16311
29950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.1631129950
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.196831377
Short name T70
Test name
Test status
Simulation time 169549086 ps
CPU time 0.8 seconds
Started Jul 20 06:17:57 PM PDT 24
Finished Jul 20 06:17:58 PM PDT 24
Peak memory 206648 kb
Host smart-d005d155-3456-48bf-9cce-10d395232f8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19683
1377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.196831377
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.2787489412
Short name T2314
Test name
Test status
Simulation time 165389377 ps
CPU time 0.78 seconds
Started Jul 20 06:18:19 PM PDT 24
Finished Jul 20 06:18:20 PM PDT 24
Peak memory 206648 kb
Host smart-1b4267f0-6c60-4a0a-84e0-82fc928180f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27874
89412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.2787489412
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3826347184
Short name T86
Test name
Test status
Simulation time 6100355453 ps
CPU time 41.32 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206924 kb
Host smart-9ac28d7b-8e9c-404a-b6bb-e3ed49c2873d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3826347184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3826347184
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1497460713
Short name T64
Test name
Test status
Simulation time 159669947 ps
CPU time 0.83 seconds
Started Jul 20 06:19:12 PM PDT 24
Finished Jul 20 06:19:14 PM PDT 24
Peak memory 206656 kb
Host smart-be1064e7-0141-43ca-81c3-08a95736a374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14974
60713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1497460713
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.980784830
Short name T2800
Test name
Test status
Simulation time 132234086 ps
CPU time 1.62 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:25 PM PDT 24
Peak memory 206564 kb
Host smart-ccb9458d-e7fc-435b-8d60-b3f4c00347bd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=980784830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.980784830
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1571003905
Short name T134
Test name
Test status
Simulation time 160847659 ps
CPU time 0.82 seconds
Started Jul 20 06:18:08 PM PDT 24
Finished Jul 20 06:18:09 PM PDT 24
Peak memory 206664 kb
Host smart-a6940044-7fc0-4bff-a584-dbf969522346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15710
03905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1571003905
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.1917595412
Short name T1728
Test name
Test status
Simulation time 492456706 ps
CPU time 1.37 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:20 PM PDT 24
Peak memory 206624 kb
Host smart-ead9f418-4837-4b44-bc8e-147301908dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19175
95412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.1917595412
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.234510700
Short name T128
Test name
Test status
Simulation time 198216247 ps
CPU time 0.83 seconds
Started Jul 20 06:21:09 PM PDT 24
Finished Jul 20 06:21:11 PM PDT 24
Peak memory 206668 kb
Host smart-a8944f04-91d0-4be7-ae4e-2c47c2b4c907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23451
0700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.234510700
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2772250418
Short name T138
Test name
Test status
Simulation time 209662352 ps
CPU time 0.87 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206672 kb
Host smart-970ac942-2b8e-4da0-ad82-def5eb26f6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27722
50418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2772250418
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1659664817
Short name T1808
Test name
Test status
Simulation time 195837550 ps
CPU time 0.84 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206624 kb
Host smart-77c98638-bdf4-4d05-8210-9faece232300
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16596
64817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1659664817
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2787558791
Short name T2159
Test name
Test status
Simulation time 206099772 ps
CPU time 0.86 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:04 PM PDT 24
Peak memory 206656 kb
Host smart-8d982cc8-b0b4-4d10-adb9-b6446dd9e9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27875
58791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2787558791
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.3566695060
Short name T2541
Test name
Test status
Simulation time 185150224 ps
CPU time 0.8 seconds
Started Jul 20 06:22:13 PM PDT 24
Finished Jul 20 06:22:15 PM PDT 24
Peak memory 206652 kb
Host smart-4ba08c63-af20-4465-a8cb-035af50a1607
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35666
95060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.3566695060
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.4291304672
Short name T133
Test name
Test status
Simulation time 183884421 ps
CPU time 0.88 seconds
Started Jul 20 06:22:47 PM PDT 24
Finished Jul 20 06:22:52 PM PDT 24
Peak memory 206668 kb
Host smart-36bf5c1d-4c2a-4a35-ad66-9394827102da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42913
04672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.4291304672
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.3284877918
Short name T139
Test name
Test status
Simulation time 179903541 ps
CPU time 0.81 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206656 kb
Host smart-52314761-1922-4171-adf1-10b007ed4d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32848
77918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.3284877918
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.2085881647
Short name T125
Test name
Test status
Simulation time 188574813 ps
CPU time 0.88 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206652 kb
Host smart-f4e94700-9630-4e8f-88b9-6ce1b21a9585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
81647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.2085881647
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.474470712
Short name T129
Test name
Test status
Simulation time 246319231 ps
CPU time 0.9 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:17 PM PDT 24
Peak memory 206652 kb
Host smart-39d080c2-9671-412b-b713-83765062f706
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47447
0712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.474470712
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.2050169855
Short name T143
Test name
Test status
Simulation time 213058372 ps
CPU time 0.86 seconds
Started Jul 20 06:25:26 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206628 kb
Host smart-8acca59e-c1e4-488d-84ca-83b2fd1e63b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20501
69855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.2050169855
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1897959679
Short name T2752
Test name
Test status
Simulation time 75827085 ps
CPU time 1.98 seconds
Started Jul 20 05:51:08 PM PDT 24
Finished Jul 20 05:51:10 PM PDT 24
Peak memory 205920 kb
Host smart-2c95fd3e-ab95-44e9-87d8-f30404073e98
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1897959679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1897959679
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1707530297
Short name T2783
Test name
Test status
Simulation time 71969077 ps
CPU time 0.83 seconds
Started Jul 20 05:51:08 PM PDT 24
Finished Jul 20 05:51:09 PM PDT 24
Peak memory 205792 kb
Host smart-3fa1ee58-1094-43ce-a3dd-1b95529a8bca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1707530297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1707530297
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.234006132
Short name T230
Test name
Test status
Simulation time 168316378 ps
CPU time 1.65 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 218716 kb
Host smart-e39f93a3-4149-4c29-b8f2-9746fc85eba8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234006132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev
_csr_mem_rw_with_rand_reset.234006132
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.835608217
Short name T262
Test name
Test status
Simulation time 45987629 ps
CPU time 0.81 seconds
Started Jul 20 05:51:17 PM PDT 24
Finished Jul 20 05:51:18 PM PDT 24
Peak memory 206308 kb
Host smart-9f00c8bd-13c2-4571-aed1-d747812f1063
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=835608217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.835608217
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3226942801
Short name T2788
Test name
Test status
Simulation time 198321235 ps
CPU time 2.41 seconds
Started Jul 20 05:51:21 PM PDT 24
Finished Jul 20 05:51:25 PM PDT 24
Peak memory 214616 kb
Host smart-735d7e98-a441-448f-8366-25ecfcc2b0cd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3226942801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3226942801
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.3172301578
Short name T2789
Test name
Test status
Simulation time 187430701 ps
CPU time 3.88 seconds
Started Jul 20 05:51:14 PM PDT 24
Finished Jul 20 05:51:19 PM PDT 24
Peak memory 206400 kb
Host smart-7723c174-6930-4c18-9aca-b9ac81dcf903
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3172301578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.3172301578
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.2576338464
Short name T2761
Test name
Test status
Simulation time 119443850 ps
CPU time 1.66 seconds
Started Jul 20 05:51:17 PM PDT 24
Finished Jul 20 05:51:19 PM PDT 24
Peak memory 206496 kb
Host smart-072c6710-b9d1-441e-a7fd-c23ef3b646e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2576338464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.2576338464
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4016386207
Short name T224
Test name
Test status
Simulation time 106576969 ps
CPU time 1.39 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 214692 kb
Host smart-3d3d83db-2485-4273-b6f9-a41d85387582
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4016386207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.4016386207
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3016766412
Short name T213
Test name
Test status
Simulation time 418249493 ps
CPU time 2.74 seconds
Started Jul 20 05:51:19 PM PDT 24
Finished Jul 20 05:51:22 PM PDT 24
Peak memory 206544 kb
Host smart-d00b113a-5b69-498f-915a-6f71ace229eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3016766412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3016766412
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.2687822869
Short name T2829
Test name
Test status
Simulation time 164758157 ps
CPU time 2.08 seconds
Started Jul 20 05:51:12 PM PDT 24
Finished Jul 20 05:51:15 PM PDT 24
Peak memory 206404 kb
Host smart-00eb1e5e-cb22-4927-8150-b73f2f7afded
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2687822869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.2687822869
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1631723936
Short name T255
Test name
Test status
Simulation time 939029357 ps
CPU time 8.77 seconds
Started Jul 20 05:51:11 PM PDT 24
Finished Jul 20 05:51:20 PM PDT 24
Peak memory 206380 kb
Host smart-ef830345-461c-4de6-a580-98dc126c05b0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1631723936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1631723936
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.3347416725
Short name T2844
Test name
Test status
Simulation time 67537786 ps
CPU time 0.89 seconds
Started Jul 20 05:51:19 PM PDT 24
Finished Jul 20 05:51:21 PM PDT 24
Peak memory 206324 kb
Host smart-886f1e23-77a2-4f82-9673-23212c8a411d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3347416725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.3347416725
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.1821894469
Short name T2760
Test name
Test status
Simulation time 93221720 ps
CPU time 1.18 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 214384 kb
Host smart-b89c79fe-2384-4884-8e6b-28490cc706a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821894469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.1821894469
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.2629411107
Short name T2799
Test name
Test status
Simulation time 91661804 ps
CPU time 0.79 seconds
Started Jul 20 05:51:21 PM PDT 24
Finished Jul 20 05:51:23 PM PDT 24
Peak memory 206340 kb
Host smart-f8ad429f-85a3-4a58-8446-b4cdfc85da82
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2629411107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.2629411107
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.2258328201
Short name T300
Test name
Test status
Simulation time 44270138 ps
CPU time 0.69 seconds
Started Jul 20 05:51:09 PM PDT 24
Finished Jul 20 05:51:10 PM PDT 24
Peak memory 206288 kb
Host smart-37661be7-fa86-4c96-bf01-899fef497b17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2258328201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.2258328201
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.227732710
Short name T258
Test name
Test status
Simulation time 195045558 ps
CPU time 2.34 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:23 PM PDT 24
Peak memory 214672 kb
Host smart-edac1cfc-0c57-4371-afe8-17b0602aaa3b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=227732710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.227732710
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.680669455
Short name T2767
Test name
Test status
Simulation time 256677303 ps
CPU time 2.71 seconds
Started Jul 20 05:51:14 PM PDT 24
Finished Jul 20 05:51:17 PM PDT 24
Peak memory 206396 kb
Host smart-d00205bc-87aa-4167-b23d-2a5b00e00814
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=680669455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.680669455
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2301521397
Short name T2815
Test name
Test status
Simulation time 97789060 ps
CPU time 1.05 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:22 PM PDT 24
Peak memory 206460 kb
Host smart-21ae886e-d094-4812-9f9f-39500be70259
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2301521397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2301521397
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.1198225509
Short name T2845
Test name
Test status
Simulation time 923478117 ps
CPU time 4.52 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:29 PM PDT 24
Peak memory 206524 kb
Host smart-4d26d432-0309-4bee-90fc-a468423196f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1198225509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.1198225509
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.4191059009
Short name T2790
Test name
Test status
Simulation time 89728163 ps
CPU time 1.32 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:33 PM PDT 24
Peak memory 214668 kb
Host smart-9093940a-0a88-479e-b3f4-996d4e4803c2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191059009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.4191059009
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.230500009
Short name T252
Test name
Test status
Simulation time 37932527 ps
CPU time 0.78 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 05:51:52 PM PDT 24
Peak memory 206280 kb
Host smart-48bd0688-45c1-4f1c-a1da-cbab8e5953c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=230500009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.230500009
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.2252759352
Short name T2823
Test name
Test status
Simulation time 36814275 ps
CPU time 0.69 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:37 PM PDT 24
Peak memory 206360 kb
Host smart-f90054b9-fd26-486d-afd0-0d5e860e1843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2252759352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.2252759352
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.3678175165
Short name T2754
Test name
Test status
Simulation time 54787051 ps
CPU time 1.01 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:31 PM PDT 24
Peak memory 206540 kb
Host smart-06f1f3d0-d00d-4961-8ee0-a79f19abf336
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3678175165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.3678175165
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.3896611669
Short name T2830
Test name
Test status
Simulation time 64269651 ps
CPU time 1.58 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 222240 kb
Host smart-f02de695-5cf8-4e1c-a8f4-5da29d40dba6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3896611669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.3896611669
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3466701489
Short name T283
Test name
Test status
Simulation time 459125669 ps
CPU time 2.68 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:31 PM PDT 24
Peak memory 206520 kb
Host smart-08aa4d5a-7b49-42ff-a170-1761128927c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3466701489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3466701489
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2566105877
Short name T2810
Test name
Test status
Simulation time 157612294 ps
CPU time 1.89 seconds
Started Jul 20 05:51:27 PM PDT 24
Finished Jul 20 05:51:36 PM PDT 24
Peak memory 214724 kb
Host smart-d51110e4-1681-40e3-afc8-5fd7b6e232ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566105877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.2566105877
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.1717449715
Short name T279
Test name
Test status
Simulation time 89197683 ps
CPU time 1.06 seconds
Started Jul 20 05:51:33 PM PDT 24
Finished Jul 20 05:51:35 PM PDT 24
Peak memory 206472 kb
Host smart-251f8f61-8177-4989-883f-81195cb860db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1717449715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.1717449715
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.820645724
Short name T2831
Test name
Test status
Simulation time 97034370 ps
CPU time 0.72 seconds
Started Jul 20 05:51:27 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 206280 kb
Host smart-f6779ad7-8c8e-42cf-9f55-0821ceb2bd10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=820645724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.820645724
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.2112160033
Short name T269
Test name
Test status
Simulation time 226901464 ps
CPU time 1.5 seconds
Started Jul 20 05:51:36 PM PDT 24
Finished Jul 20 05:51:38 PM PDT 24
Peak memory 206448 kb
Host smart-5682150b-e6ae-46e4-8dc3-0656037e2922
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2112160033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.2112160033
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1689269546
Short name T2782
Test name
Test status
Simulation time 259791673 ps
CPU time 2.64 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 214756 kb
Host smart-921e4831-d142-405e-97a4-b686c41524a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1689269546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1689269546
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.2068962884
Short name T280
Test name
Test status
Simulation time 840931169 ps
CPU time 4.53 seconds
Started Jul 20 05:51:33 PM PDT 24
Finished Jul 20 05:51:38 PM PDT 24
Peak memory 206464 kb
Host smart-a006042e-8952-49e1-a1e2-745bf0eaa775
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2068962884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.2068962884
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1002078762
Short name T2791
Test name
Test status
Simulation time 95162720 ps
CPU time 1.22 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 214808 kb
Host smart-73dd124a-58ac-4805-a1d5-e0bf4c5e47bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002078762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1002078762
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.4179149757
Short name T2787
Test name
Test status
Simulation time 38967439 ps
CPU time 0.75 seconds
Started Jul 20 05:51:31 PM PDT 24
Finished Jul 20 05:51:33 PM PDT 24
Peak memory 206300 kb
Host smart-6b4c08ce-d2a6-4db8-bed9-fb49d4a34251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4179149757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.4179149757
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.1250384081
Short name T2795
Test name
Test status
Simulation time 374741978 ps
CPU time 1.91 seconds
Started Jul 20 05:51:34 PM PDT 24
Finished Jul 20 05:51:37 PM PDT 24
Peak memory 206480 kb
Host smart-789bd404-dc67-4b52-8767-e0a020521cd6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1250384081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.1250384081
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.2415221173
Short name T228
Test name
Test status
Simulation time 223252406 ps
CPU time 2.07 seconds
Started Jul 20 05:51:44 PM PDT 24
Finished Jul 20 05:51:47 PM PDT 24
Peak memory 222560 kb
Host smart-7b7d4641-6b6e-4c06-b85b-a8277ba604e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2415221173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.2415221173
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.3736042545
Short name T285
Test name
Test status
Simulation time 654708157 ps
CPU time 2.75 seconds
Started Jul 20 05:51:27 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206548 kb
Host smart-06c1aae0-5139-4486-8dcc-3f8db77029d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3736042545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.3736042545
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.2894117115
Short name T2801
Test name
Test status
Simulation time 92862746 ps
CPU time 1.88 seconds
Started Jul 20 05:51:33 PM PDT 24
Finished Jul 20 05:51:36 PM PDT 24
Peak memory 214800 kb
Host smart-55271d16-d453-4cfe-9b87-0ddc3df3e1d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2894117115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.2894117115
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.2749800313
Short name T259
Test name
Test status
Simulation time 105403917 ps
CPU time 0.9 seconds
Started Jul 20 05:51:32 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 206332 kb
Host smart-b9853b17-925d-42ab-abca-4084b45f70e3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2749800313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.2749800313
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3710085444
Short name T298
Test name
Test status
Simulation time 49238640 ps
CPU time 0.7 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 206288 kb
Host smart-c6525d08-0f1b-4b38-8206-748d9cbf1c98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3710085444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3710085444
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.631372689
Short name T2846
Test name
Test status
Simulation time 59975515 ps
CPU time 0.97 seconds
Started Jul 20 05:51:41 PM PDT 24
Finished Jul 20 05:51:42 PM PDT 24
Peak memory 206472 kb
Host smart-f19722c8-0dc8-4c24-a79f-7f1de237439b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=631372689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.631372689
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2101596572
Short name T2838
Test name
Test status
Simulation time 100045484 ps
CPU time 2.74 seconds
Started Jul 20 05:51:30 PM PDT 24
Finished Jul 20 05:51:35 PM PDT 24
Peak memory 206612 kb
Host smart-78dc3e61-f1dd-40c6-847e-9a5df554124a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2101596572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2101596572
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.611502255
Short name T189
Test name
Test status
Simulation time 80947534 ps
CPU time 1.18 seconds
Started Jul 20 05:51:31 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 216444 kb
Host smart-65071c73-b003-463e-a672-4ae02c0b7198
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611502255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbde
v_csr_mem_rw_with_rand_reset.611502255
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2719615719
Short name T2792
Test name
Test status
Simulation time 109207901 ps
CPU time 1.03 seconds
Started Jul 20 05:51:36 PM PDT 24
Finished Jul 20 05:51:37 PM PDT 24
Peak memory 206448 kb
Host smart-4b55e5ce-6fee-4e3c-b486-c1177015db0b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2719615719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2719615719
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1530850478
Short name T302
Test name
Test status
Simulation time 47087218 ps
CPU time 0.69 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:35 PM PDT 24
Peak memory 206288 kb
Host smart-bf3519ab-86aa-46c0-81c3-51762967bee7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1530850478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1530850478
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.429120763
Short name T2842
Test name
Test status
Simulation time 167626168 ps
CPU time 1.54 seconds
Started Jul 20 05:51:34 PM PDT 24
Finished Jul 20 05:51:36 PM PDT 24
Peak memory 206516 kb
Host smart-18ca67b5-e250-4500-a376-89aa2bf4604f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=429120763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.429120763
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2532484597
Short name T2773
Test name
Test status
Simulation time 138474537 ps
CPU time 1.88 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:25 PM PDT 24
Peak memory 214700 kb
Host smart-8815a635-ddf9-45df-a353-77e825c876d8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2532484597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2532484597
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3920128988
Short name T2813
Test name
Test status
Simulation time 520448346 ps
CPU time 2.71 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 206568 kb
Host smart-160493b0-493a-41b2-894e-eeb8564d7011
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3920128988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3920128988
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.965466842
Short name T2825
Test name
Test status
Simulation time 162157192 ps
CPU time 1.27 seconds
Started Jul 20 05:51:27 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 214664 kb
Host smart-5402d4b6-7b16-4e9c-86e2-042df0f2dad4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965466842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde
v_csr_mem_rw_with_rand_reset.965466842
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.754718283
Short name T263
Test name
Test status
Simulation time 58984165 ps
CPU time 0.99 seconds
Started Jul 20 05:51:38 PM PDT 24
Finished Jul 20 05:51:40 PM PDT 24
Peak memory 206392 kb
Host smart-99443ed1-477e-48c8-8aa0-a4b6be1a89d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=754718283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.754718283
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3497620703
Short name T2778
Test name
Test status
Simulation time 177112264 ps
CPU time 1.54 seconds
Started Jul 20 05:51:44 PM PDT 24
Finished Jul 20 05:51:47 PM PDT 24
Peak memory 206548 kb
Host smart-b0546ee2-c3d8-4a95-bc25-bc28886904d8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3497620703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3497620703
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1678807109
Short name T223
Test name
Test status
Simulation time 137074656 ps
CPU time 2.68 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 222864 kb
Host smart-06a26b71-a273-4926-98b2-f8fbb2d30c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1678807109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1678807109
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2167875099
Short name T2803
Test name
Test status
Simulation time 2082986230 ps
CPU time 6.41 seconds
Started Jul 20 05:51:30 PM PDT 24
Finished Jul 20 05:51:39 PM PDT 24
Peak memory 206456 kb
Host smart-198314c4-8d80-4c32-988d-d9ba71dd26e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2167875099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2167875099
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3263129474
Short name T2756
Test name
Test status
Simulation time 63090410 ps
CPU time 1.41 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:29 PM PDT 24
Peak memory 214920 kb
Host smart-97c19787-00ea-4937-9d3b-ecabc8ae4a6f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263129474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3263129474
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2981856595
Short name T2818
Test name
Test status
Simulation time 59610294 ps
CPU time 0.96 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206416 kb
Host smart-bb75e444-08c4-4fd3-91bc-4b17e55a1bca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2981856595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2981856595
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1770332024
Short name T2822
Test name
Test status
Simulation time 106254474 ps
CPU time 0.79 seconds
Started Jul 20 05:51:33 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 206292 kb
Host smart-0fb64dd8-a07e-4aed-9a24-ac7f27517a15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1770332024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1770332024
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1280573280
Short name T2839
Test name
Test status
Simulation time 77534951 ps
CPU time 1.43 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:33 PM PDT 24
Peak memory 206664 kb
Host smart-1f3b30a4-1606-4348-8583-f1eb8e7d31b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1280573280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1280573280
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.4127206709
Short name T222
Test name
Test status
Simulation time 347116248 ps
CPU time 3.44 seconds
Started Jul 20 05:51:40 PM PDT 24
Finished Jul 20 05:51:44 PM PDT 24
Peak memory 214804 kb
Host smart-2bf1286b-8428-49c1-837f-9e90a16a4313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4127206709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.4127206709
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.549829836
Short name T287
Test name
Test status
Simulation time 1740831498 ps
CPU time 5.59 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:37 PM PDT 24
Peak memory 206568 kb
Host smart-3fbbc539-866c-4ced-a271-c8caaebe25ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=549829836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.549829836
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3984394628
Short name T231
Test name
Test status
Simulation time 101897013 ps
CPU time 1.22 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:31 PM PDT 24
Peak memory 214720 kb
Host smart-ff7ac1c5-cd97-4ea5-8da3-011a875af452
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984394628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3984394628
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.862961570
Short name T2811
Test name
Test status
Simulation time 43270881 ps
CPU time 0.81 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:31 PM PDT 24
Peak memory 206336 kb
Host smart-b73a6101-7f1c-4024-9f3b-c1a5c594971c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=862961570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.862961570
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2740023245
Short name T2771
Test name
Test status
Simulation time 37503575 ps
CPU time 0.63 seconds
Started Jul 20 05:51:27 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 206288 kb
Host smart-1bfcc063-0910-449b-a525-f8b748525bf6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2740023245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2740023245
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.2623763984
Short name T2779
Test name
Test status
Simulation time 95054715 ps
CPU time 1.1 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 205792 kb
Host smart-82d96836-c616-4d3d-bbfa-8589664eb764
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2623763984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.2623763984
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.897030216
Short name T2817
Test name
Test status
Simulation time 992302126 ps
CPU time 5.27 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:51:52 PM PDT 24
Peak memory 206560 kb
Host smart-785a3297-e4d9-40bb-b9d9-4b07b58c6919
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=897030216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.897030216
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3155065497
Short name T2798
Test name
Test status
Simulation time 198692038 ps
CPU time 1.89 seconds
Started Jul 20 05:51:43 PM PDT 24
Finished Jul 20 05:51:46 PM PDT 24
Peak memory 214820 kb
Host smart-dc19b6bc-7335-49af-a482-0ac3394ac162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155065497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3155065497
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1795555613
Short name T295
Test name
Test status
Simulation time 38862063 ps
CPU time 0.68 seconds
Started Jul 20 05:51:37 PM PDT 24
Finished Jul 20 05:51:38 PM PDT 24
Peak memory 206284 kb
Host smart-c62b4999-8dc2-4256-8ba2-54361a85da8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1795555613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1795555613
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.1776263149
Short name T2755
Test name
Test status
Simulation time 51133354 ps
CPU time 1.06 seconds
Started Jul 20 05:51:43 PM PDT 24
Finished Jul 20 05:51:44 PM PDT 24
Peak memory 206432 kb
Host smart-33d91780-dbaa-4f89-945d-6f8dd5571f15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1776263149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.1776263149
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1181970835
Short name T2837
Test name
Test status
Simulation time 107327668 ps
CPU time 1.81 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:33 PM PDT 24
Peak memory 222424 kb
Host smart-730eba50-dc08-4eb7-8f08-313a67542b88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1181970835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1181970835
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3468294082
Short name T284
Test name
Test status
Simulation time 1161670593 ps
CPU time 3.21 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 206580 kb
Host smart-6cbce3c1-4d17-426d-953a-fe8794ccddd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3468294082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3468294082
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.368030065
Short name T2802
Test name
Test status
Simulation time 118585707 ps
CPU time 1.36 seconds
Started Jul 20 05:51:48 PM PDT 24
Finished Jul 20 05:51:50 PM PDT 24
Peak memory 214820 kb
Host smart-94bbbcfa-8952-4a19-a91a-09cc3b50de94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368030065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.368030065
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.3707250074
Short name T267
Test name
Test status
Simulation time 101326856 ps
CPU time 0.91 seconds
Started Jul 20 05:51:42 PM PDT 24
Finished Jul 20 05:51:43 PM PDT 24
Peak memory 206264 kb
Host smart-2862fdfa-1c0f-4ca2-83d1-ec0df179522e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3707250074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.3707250074
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.1594165607
Short name T299
Test name
Test status
Simulation time 39144544 ps
CPU time 0.65 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 206260 kb
Host smart-9e204b8f-328d-443b-be56-0cbb310fc4c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1594165607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.1594165607
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.1702142610
Short name T268
Test name
Test status
Simulation time 56266206 ps
CPU time 1.08 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206468 kb
Host smart-0874392b-c8d6-4fbd-b9d0-fe697fc76d51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1702142610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.1702142610
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1927045702
Short name T219
Test name
Test status
Simulation time 139613944 ps
CPU time 1.67 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 222144 kb
Host smart-e0993e4f-4516-4345-aa64-e0a0631f88ac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1927045702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1927045702
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.490311733
Short name T288
Test name
Test status
Simulation time 826403125 ps
CPU time 4.82 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206548 kb
Host smart-9a0e7b96-18d5-4764-9b31-c8f1fcb119ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=490311733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.490311733
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.802425456
Short name T2833
Test name
Test status
Simulation time 119837804 ps
CPU time 2.05 seconds
Started Jul 20 05:51:18 PM PDT 24
Finished Jul 20 05:51:21 PM PDT 24
Peak memory 206456 kb
Host smart-f680903b-27d6-4b44-8de3-cebec77bde2d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=802425456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.802425456
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.2177210872
Short name T191
Test name
Test status
Simulation time 1069293028 ps
CPU time 8.17 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:33 PM PDT 24
Peak memory 206456 kb
Host smart-2caaf90f-278a-40ab-b0bd-4a19e7001833
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2177210872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.2177210872
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2857469459
Short name T2750
Test name
Test status
Simulation time 75101374 ps
CPU time 0.94 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 206228 kb
Host smart-93a95a41-0399-48e1-ab9a-a01295ffd6e7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2857469459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2857469459
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1516895435
Short name T225
Test name
Test status
Simulation time 160447535 ps
CPU time 1.87 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 214700 kb
Host smart-69122646-1a41-4968-99ea-1799d68b87d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516895435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1516895435
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1197403222
Short name T2770
Test name
Test status
Simulation time 60567500 ps
CPU time 0.85 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:21 PM PDT 24
Peak memory 206312 kb
Host smart-94934197-2e5b-4edb-8af9-dee0775f93e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1197403222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1197403222
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.352394414
Short name T2766
Test name
Test status
Simulation time 58449406 ps
CPU time 0.67 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 206312 kb
Host smart-1bb5987e-a9a3-49b4-88ba-566f0e4a7c99
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=352394414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.352394414
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.44704024
Short name T254
Test name
Test status
Simulation time 202157460 ps
CPU time 2.38 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:33 PM PDT 24
Peak memory 214804 kb
Host smart-5fba7f69-d336-4e9d-9fea-43346f9b6ffb
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=44704024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.44704024
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3748724453
Short name T2765
Test name
Test status
Simulation time 503092740 ps
CPU time 4.63 seconds
Started Jul 20 05:51:13 PM PDT 24
Finished Jul 20 05:51:18 PM PDT 24
Peak memory 206392 kb
Host smart-db14cb28-8181-48c5-a689-6f70d7e11f87
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3748724453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3748724453
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2802737983
Short name T2832
Test name
Test status
Simulation time 58636079 ps
CPU time 0.99 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:29 PM PDT 24
Peak memory 206456 kb
Host smart-d8ff423e-686d-456b-befc-3c10d6334360
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2802737983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2802737983
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3267807990
Short name T2834
Test name
Test status
Simulation time 282163489 ps
CPU time 2.78 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 214720 kb
Host smart-e5808ddc-19ea-4dbf-aa93-d0e40546f61d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3267807990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3267807990
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2357818311
Short name T2776
Test name
Test status
Simulation time 404200667 ps
CPU time 2.83 seconds
Started Jul 20 05:51:21 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 206388 kb
Host smart-7f4db828-affb-4767-8aba-9f3b05dee78f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2357818311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2357818311
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.4139134301
Short name T2816
Test name
Test status
Simulation time 35856461 ps
CPU time 0.66 seconds
Started Jul 20 05:51:45 PM PDT 24
Finished Jul 20 05:51:47 PM PDT 24
Peak memory 206252 kb
Host smart-86606792-4824-465e-bfaf-c1a65f40b2bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4139134301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.4139134301
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2264064018
Short name T2753
Test name
Test status
Simulation time 51621642 ps
CPU time 0.68 seconds
Started Jul 20 05:51:39 PM PDT 24
Finished Jul 20 05:51:40 PM PDT 24
Peak memory 206280 kb
Host smart-45e2ce50-81a4-4642-ba40-dcf4d6e744a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2264064018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2264064018
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.1996281599
Short name T2835
Test name
Test status
Simulation time 31712144 ps
CPU time 0.69 seconds
Started Jul 20 05:51:44 PM PDT 24
Finished Jul 20 05:51:46 PM PDT 24
Peak memory 206288 kb
Host smart-26079222-1a34-4700-a067-38ffabf75d67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1996281599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.1996281599
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.2175884299
Short name T290
Test name
Test status
Simulation time 34281223 ps
CPU time 0.67 seconds
Started Jul 20 05:51:48 PM PDT 24
Finished Jul 20 05:51:50 PM PDT 24
Peak memory 206280 kb
Host smart-a719e8d8-eb49-48dd-9f8b-0e64bb435217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2175884299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.2175884299
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.2463393488
Short name T2777
Test name
Test status
Simulation time 62480412 ps
CPU time 0.7 seconds
Started Jul 20 05:51:38 PM PDT 24
Finished Jul 20 05:51:40 PM PDT 24
Peak memory 206312 kb
Host smart-3e4c0ff1-02f2-4e2e-80eb-d85fb9648280
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2463393488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.2463393488
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1628361165
Short name T2774
Test name
Test status
Simulation time 52634492 ps
CPU time 0.66 seconds
Started Jul 20 05:51:36 PM PDT 24
Finished Jul 20 05:51:37 PM PDT 24
Peak memory 206284 kb
Host smart-6cfb4781-dc8f-4d83-9214-4ddea36aebad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1628361165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1628361165
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1367566403
Short name T2807
Test name
Test status
Simulation time 65748515 ps
CPU time 0.7 seconds
Started Jul 20 05:51:45 PM PDT 24
Finished Jul 20 05:51:46 PM PDT 24
Peak memory 206284 kb
Host smart-5849e21f-bdf1-4481-a321-c2dad2092d3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1367566403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1367566403
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3631287569
Short name T2827
Test name
Test status
Simulation time 44021766 ps
CPU time 0.71 seconds
Started Jul 20 05:51:53 PM PDT 24
Finished Jul 20 05:51:54 PM PDT 24
Peak memory 206292 kb
Host smart-120f9378-4676-47f5-a35a-51fb8d94b007
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3631287569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3631287569
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2834894786
Short name T2821
Test name
Test status
Simulation time 64804525 ps
CPU time 0.74 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 05:51:52 PM PDT 24
Peak memory 206288 kb
Host smart-3d9965f0-c391-4aba-ac61-82d0839ba65e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2834894786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2834894786
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3219328017
Short name T260
Test name
Test status
Simulation time 331022132 ps
CPU time 3.62 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 206468 kb
Host smart-4e8230f4-d7a0-48c7-84ce-43cdcc9f1ce8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3219328017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3219328017
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.2016651320
Short name T2796
Test name
Test status
Simulation time 552559656 ps
CPU time 7.25 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 206392 kb
Host smart-818dbf41-162b-4b95-9a54-b422869381a1
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2016651320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.2016651320
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3175583613
Short name T261
Test name
Test status
Simulation time 323673209 ps
CPU time 1.21 seconds
Started Jul 20 05:51:27 PM PDT 24
Finished Jul 20 05:51:31 PM PDT 24
Peak memory 206296 kb
Host smart-29d0681d-b1c9-429c-a092-0d7f0ba42c70
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3175583613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3175583613
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3789634556
Short name T2762
Test name
Test status
Simulation time 152269479 ps
CPU time 2 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 217988 kb
Host smart-144adcd4-c007-4b00-99e9-bb3225f5056d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789634556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3789634556
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1641458536
Short name T2763
Test name
Test status
Simulation time 72315776 ps
CPU time 0.98 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 206404 kb
Host smart-a8a8d4b6-3e50-4427-b082-fbede50132ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1641458536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1641458536
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.3306261067
Short name T2826
Test name
Test status
Simulation time 57200822 ps
CPU time 0.68 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 206292 kb
Host smart-d07ccb99-664f-4274-98ce-c5d0f81b2131
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3306261067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.3306261067
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4219879249
Short name T2785
Test name
Test status
Simulation time 232205974 ps
CPU time 2.52 seconds
Started Jul 20 05:51:32 PM PDT 24
Finished Jul 20 05:51:35 PM PDT 24
Peak memory 214676 kb
Host smart-46c79001-e5bb-46ba-9338-7e260a0bbc3f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4219879249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4219879249
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.340781867
Short name T2772
Test name
Test status
Simulation time 332914441 ps
CPU time 2.47 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:29 PM PDT 24
Peak memory 206396 kb
Host smart-b6b1b421-069e-4443-93aa-db8b8a5ddfd2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=340781867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.340781867
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1670956056
Short name T2775
Test name
Test status
Simulation time 119096175 ps
CPU time 1.53 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 206572 kb
Host smart-fe640af9-e4bd-4f3e-a06b-5d3b6018366e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1670956056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1670956056
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.2419465443
Short name T2784
Test name
Test status
Simulation time 172236526 ps
CPU time 1.72 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:22 PM PDT 24
Peak memory 206596 kb
Host smart-b6663ce1-593b-46b4-91e0-4e7a6a87fe0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2419465443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.2419465443
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1507097823
Short name T306
Test name
Test status
Simulation time 832171176 ps
CPU time 2.87 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 206544 kb
Host smart-291fbd16-694b-4db7-9501-e4d1ee5315ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1507097823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1507097823
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2981622476
Short name T303
Test name
Test status
Simulation time 40350121 ps
CPU time 0.65 seconds
Started Jul 20 05:51:35 PM PDT 24
Finished Jul 20 05:51:36 PM PDT 24
Peak memory 206292 kb
Host smart-be0a3b92-8844-4fad-882f-440f1e7bd2fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2981622476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2981622476
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1259866351
Short name T292
Test name
Test status
Simulation time 43714728 ps
CPU time 0.69 seconds
Started Jul 20 05:51:44 PM PDT 24
Finished Jul 20 05:51:45 PM PDT 24
Peak memory 206284 kb
Host smart-1bd15d6b-de19-40b7-b7d8-627240d8eadc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1259866351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1259866351
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.593003352
Short name T2764
Test name
Test status
Simulation time 45521053 ps
CPU time 0.67 seconds
Started Jul 20 05:51:49 PM PDT 24
Finished Jul 20 05:51:51 PM PDT 24
Peak memory 206280 kb
Host smart-4210880d-9911-42e7-ad59-530ed5006d9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=593003352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.593003352
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.23489136
Short name T2820
Test name
Test status
Simulation time 114029550 ps
CPU time 0.72 seconds
Started Jul 20 05:51:39 PM PDT 24
Finished Jul 20 05:51:40 PM PDT 24
Peak memory 206272 kb
Host smart-84d520a6-a00c-4c9b-a8ad-79426dcce860
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=23489136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.23489136
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3233374925
Short name T2759
Test name
Test status
Simulation time 32698730 ps
CPU time 0.64 seconds
Started Jul 20 05:52:00 PM PDT 24
Finished Jul 20 05:52:01 PM PDT 24
Peak memory 206288 kb
Host smart-389becab-de46-4313-b8a1-f1f1dccd5e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3233374925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3233374925
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.347575358
Short name T281
Test name
Test status
Simulation time 91461183 ps
CPU time 0.73 seconds
Started Jul 20 05:51:40 PM PDT 24
Finished Jul 20 05:51:42 PM PDT 24
Peak memory 206284 kb
Host smart-18a19264-3f5c-4f35-ba03-dc82594bef1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=347575358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.347575358
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.618308829
Short name T2806
Test name
Test status
Simulation time 39509609 ps
CPU time 0.68 seconds
Started Jul 20 05:51:51 PM PDT 24
Finished Jul 20 05:51:52 PM PDT 24
Peak memory 206224 kb
Host smart-5ddf986c-0556-43fc-b50b-9450d83e608e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=618308829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.618308829
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1483248334
Short name T2769
Test name
Test status
Simulation time 70805066 ps
CPU time 0.73 seconds
Started Jul 20 05:51:50 PM PDT 24
Finished Jul 20 05:51:51 PM PDT 24
Peak memory 206280 kb
Host smart-9b87785a-7d90-4605-bab7-3bf9fa8c1cee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1483248334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1483248334
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.3316173476
Short name T297
Test name
Test status
Simulation time 39541059 ps
CPU time 0.7 seconds
Started Jul 20 05:51:41 PM PDT 24
Finished Jul 20 05:51:42 PM PDT 24
Peak memory 206288 kb
Host smart-26f99b92-af1d-4824-8ec0-4e893ab36df0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3316173476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.3316173476
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.2868158628
Short name T2847
Test name
Test status
Simulation time 372629236 ps
CPU time 3.43 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 206436 kb
Host smart-4ceadb90-b8db-41ce-be53-3ca7743d9692
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2868158628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.2868158628
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.2589014900
Short name T2843
Test name
Test status
Simulation time 1415146824 ps
CPU time 9.03 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:40 PM PDT 24
Peak memory 206544 kb
Host smart-6ef10365-9893-407d-90bc-bab260c26684
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2589014900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.2589014900
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3161192650
Short name T250
Test name
Test status
Simulation time 74427775 ps
CPU time 0.93 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 206296 kb
Host smart-e9f1b3bb-e9b5-4340-be22-174c8d538ad7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3161192650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3161192650
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2299699876
Short name T2786
Test name
Test status
Simulation time 129972542 ps
CPU time 1.4 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 214800 kb
Host smart-82b5bafc-80ed-44a2-8360-500591b55a33
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299699876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2299699876
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3087751851
Short name T214
Test name
Test status
Simulation time 48783353 ps
CPU time 0.8 seconds
Started Jul 20 05:51:21 PM PDT 24
Finished Jul 20 05:51:22 PM PDT 24
Peak memory 206240 kb
Host smart-7610460c-ca45-473f-81e0-389de65c38e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3087751851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3087751851
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3887584056
Short name T197
Test name
Test status
Simulation time 45372442 ps
CPU time 0.64 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 206276 kb
Host smart-0fba12f3-225a-4482-b8e1-379a04675a91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3887584056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3887584056
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.3225188417
Short name T2812
Test name
Test status
Simulation time 53132221 ps
CPU time 1.41 seconds
Started Jul 20 05:51:18 PM PDT 24
Finished Jul 20 05:51:20 PM PDT 24
Peak memory 215984 kb
Host smart-b955b9dc-efef-41b1-a48e-64d2ecc52ba8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3225188417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.3225188417
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1509860865
Short name T2781
Test name
Test status
Simulation time 264565537 ps
CPU time 2.53 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 206364 kb
Host smart-9f1940d4-d995-4894-b736-3e78aba0b300
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1509860865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1509860865
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.117986063
Short name T2828
Test name
Test status
Simulation time 181350126 ps
CPU time 1.61 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 206496 kb
Host smart-40ce741d-d65d-4080-9f25-ebefb9f9db4c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=117986063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.117986063
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1946691024
Short name T277
Test name
Test status
Simulation time 429079865 ps
CPU time 2.9 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 206424 kb
Host smart-3b23e330-5872-4ab6-a82e-a66154556298
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1946691024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1946691024
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.236656482
Short name T2840
Test name
Test status
Simulation time 52653820 ps
CPU time 0.68 seconds
Started Jul 20 05:51:56 PM PDT 24
Finished Jul 20 05:51:57 PM PDT 24
Peak memory 206308 kb
Host smart-7138c303-b18e-4bc2-8fab-a6e3054f1431
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=236656482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.236656482
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.3965762890
Short name T2794
Test name
Test status
Simulation time 43136926 ps
CPU time 0.69 seconds
Started Jul 20 05:51:41 PM PDT 24
Finished Jul 20 05:51:42 PM PDT 24
Peak memory 206300 kb
Host smart-0cc7d81a-aae9-4c33-b708-c92a97ab8209
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3965762890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.3965762890
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1239562013
Short name T305
Test name
Test status
Simulation time 87601145 ps
CPU time 0.71 seconds
Started Jul 20 05:51:57 PM PDT 24
Finished Jul 20 05:51:58 PM PDT 24
Peak memory 206296 kb
Host smart-7353cd55-54e5-4ab0-b797-d5f9f4067c9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1239562013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1239562013
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3605545620
Short name T282
Test name
Test status
Simulation time 54529777 ps
CPU time 0.68 seconds
Started Jul 20 05:51:56 PM PDT 24
Finished Jul 20 05:51:57 PM PDT 24
Peak memory 206292 kb
Host smart-c1b7b512-9045-4734-9685-7949c8251804
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3605545620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3605545620
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.4039432933
Short name T2793
Test name
Test status
Simulation time 94423042 ps
CPU time 0.77 seconds
Started Jul 20 05:51:42 PM PDT 24
Finished Jul 20 05:51:43 PM PDT 24
Peak memory 206288 kb
Host smart-d731b389-f834-44ac-919c-961f1bec36eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4039432933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.4039432933
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.268285238
Short name T2836
Test name
Test status
Simulation time 37941382 ps
CPU time 0.64 seconds
Started Jul 20 05:51:40 PM PDT 24
Finished Jul 20 05:51:41 PM PDT 24
Peak memory 206276 kb
Host smart-078d9e95-66d6-4b51-8ac5-6481f6146155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=268285238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.268285238
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.680126208
Short name T199
Test name
Test status
Simulation time 34821209 ps
CPU time 0.7 seconds
Started Jul 20 05:51:34 PM PDT 24
Finished Jul 20 05:51:35 PM PDT 24
Peak memory 206300 kb
Host smart-482df2dd-ffc2-4dd8-8d92-0918c845a0c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=680126208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.680126208
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.4052694803
Short name T2805
Test name
Test status
Simulation time 95949991 ps
CPU time 0.76 seconds
Started Jul 20 05:51:46 PM PDT 24
Finished Jul 20 05:51:48 PM PDT 24
Peak memory 206300 kb
Host smart-20f07a09-ba96-4516-b749-068b8006ba4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4052694803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.4052694803
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.4139361807
Short name T2809
Test name
Test status
Simulation time 41073903 ps
CPU time 0.67 seconds
Started Jul 20 05:51:37 PM PDT 24
Finished Jul 20 05:51:38 PM PDT 24
Peak memory 206280 kb
Host smart-9584023e-da88-4b3c-b787-76303df5547a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4139361807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.4139361807
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.795734783
Short name T294
Test name
Test status
Simulation time 51720143 ps
CPU time 0.67 seconds
Started Jul 20 05:51:53 PM PDT 24
Finished Jul 20 05:51:55 PM PDT 24
Peak memory 206280 kb
Host smart-6c800569-b144-4620-b56a-f3009f9f17d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=795734783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.795734783
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1691268180
Short name T2757
Test name
Test status
Simulation time 189072128 ps
CPU time 1.76 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 214748 kb
Host smart-7154d795-fdc7-4e45-bae5-961a21a7efdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691268180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1691268180
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.1267659780
Short name T2751
Test name
Test status
Simulation time 61144863 ps
CPU time 0.84 seconds
Started Jul 20 05:51:24 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 206280 kb
Host smart-a3effe6f-3c88-454c-83bb-66e4cc6bdcec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1267659780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.1267659780
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.879076339
Short name T2819
Test name
Test status
Simulation time 39957793 ps
CPU time 0.65 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:26 PM PDT 24
Peak memory 206008 kb
Host smart-ffc6c9e5-e778-492a-b91a-aee4a40df325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=879076339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.879076339
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3770244875
Short name T270
Test name
Test status
Simulation time 98975475 ps
CPU time 1.16 seconds
Started Jul 20 05:51:21 PM PDT 24
Finished Jul 20 05:51:22 PM PDT 24
Peak memory 206516 kb
Host smart-87907d5a-5d7e-453a-807f-980e36d177e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3770244875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3770244875
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.372208420
Short name T226
Test name
Test status
Simulation time 120396769 ps
CPU time 2.09 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 214748 kb
Host smart-1802a70f-2004-4505-bf10-1c8467cf03df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=372208420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.372208420
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.2283686909
Short name T2780
Test name
Test status
Simulation time 107219485 ps
CPU time 2.25 seconds
Started Jul 20 05:51:26 PM PDT 24
Finished Jul 20 05:51:30 PM PDT 24
Peak memory 214700 kb
Host smart-58fbe85f-a6f4-4e85-a91c-7481d9b1cec8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283686909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.2283686909
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.1436707971
Short name T253
Test name
Test status
Simulation time 80543841 ps
CPU time 1.06 seconds
Started Jul 20 05:51:24 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 206424 kb
Host smart-3812fb13-8dee-4b12-a896-9cb9b7c47dd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1436707971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.1436707971
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3211651837
Short name T2824
Test name
Test status
Simulation time 56608391 ps
CPU time 0.69 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:31 PM PDT 24
Peak memory 206196 kb
Host smart-16a6732e-16c7-4dfd-b65f-0b3a43117159
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3211651837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3211651837
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1678281331
Short name T265
Test name
Test status
Simulation time 182526287 ps
CPU time 1.71 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:31 PM PDT 24
Peak memory 206396 kb
Host smart-3ba814fc-04fb-42f0-b338-c7902f81a635
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1678281331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1678281331
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.528684050
Short name T2841
Test name
Test status
Simulation time 152581979 ps
CPU time 2.22 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 214792 kb
Host smart-c98cddf8-7032-417e-9aba-54309a419b12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=528684050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.528684050
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.2772589431
Short name T2804
Test name
Test status
Simulation time 567499091 ps
CPU time 2.84 seconds
Started Jul 20 05:51:21 PM PDT 24
Finished Jul 20 05:51:25 PM PDT 24
Peak memory 206456 kb
Host smart-2f98ad5e-1c60-4afd-9873-da46e1c8ce92
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2772589431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.2772589431
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1927164215
Short name T2768
Test name
Test status
Simulation time 77832066 ps
CPU time 1.47 seconds
Started Jul 20 05:51:25 PM PDT 24
Finished Jul 20 05:51:29 PM PDT 24
Peak memory 214748 kb
Host smart-aca75c60-5c02-448c-b505-77972b6f504a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927164215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1927164215
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1549563151
Short name T264
Test name
Test status
Simulation time 57014022 ps
CPU time 0.88 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206360 kb
Host smart-af20c983-6543-4ada-b63b-0c67fa4be487
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1549563151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1549563151
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2638125378
Short name T304
Test name
Test status
Simulation time 45809567 ps
CPU time 0.68 seconds
Started Jul 20 05:51:22 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 206284 kb
Host smart-1a542efc-b029-483b-a6ff-6f93d1b79b02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2638125378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2638125378
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.1360806919
Short name T215
Test name
Test status
Simulation time 207878762 ps
CPU time 1.68 seconds
Started Jul 20 05:51:23 PM PDT 24
Finished Jul 20 05:51:27 PM PDT 24
Peak memory 206552 kb
Host smart-06b638ef-ca0c-4529-9d70-c0c742512b96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1360806919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.1360806919
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.647796872
Short name T212
Test name
Test status
Simulation time 139837591 ps
CPU time 1.59 seconds
Started Jul 20 05:51:21 PM PDT 24
Finished Jul 20 05:51:23 PM PDT 24
Peak memory 221992 kb
Host smart-527ca8d5-b57b-40f0-ba26-f5acb9e15a66
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=647796872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.647796872
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3948361992
Short name T278
Test name
Test status
Simulation time 919264367 ps
CPU time 3.15 seconds
Started Jul 20 05:51:20 PM PDT 24
Finished Jul 20 05:51:24 PM PDT 24
Peak memory 206500 kb
Host smart-56dfc78d-2774-4e65-93cb-2a47b6f3be0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3948361992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3948361992
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3435019623
Short name T220
Test name
Test status
Simulation time 177750065 ps
CPU time 1.91 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:36 PM PDT 24
Peak memory 214692 kb
Host smart-5d412e23-0243-41ff-8cd0-2b3952fb6a2a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435019623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.3435019623
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.2422579741
Short name T257
Test name
Test status
Simulation time 57263284 ps
CPU time 0.98 seconds
Started Jul 20 05:51:32 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 206428 kb
Host smart-c37360a0-2e4b-4556-8781-8a45f3e432bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2422579741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.2422579741
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1644836073
Short name T2797
Test name
Test status
Simulation time 50368631 ps
CPU time 0.68 seconds
Started Jul 20 05:51:19 PM PDT 24
Finished Jul 20 05:51:21 PM PDT 24
Peak memory 206304 kb
Host smart-2aa07db4-9252-4e39-9c03-a6e31636c497
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1644836073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1644836073
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3905769615
Short name T266
Test name
Test status
Simulation time 100759486 ps
CPU time 1.67 seconds
Started Jul 20 05:51:17 PM PDT 24
Finished Jul 20 05:51:19 PM PDT 24
Peak memory 206568 kb
Host smart-6e65cd0e-6bd1-4367-a894-3afbabb7c91a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3905769615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3905769615
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2845045946
Short name T221
Test name
Test status
Simulation time 146822815 ps
CPU time 2.38 seconds
Started Jul 20 05:51:24 PM PDT 24
Finished Jul 20 05:51:28 PM PDT 24
Peak memory 206480 kb
Host smart-9fdb3983-6717-4a71-b458-20cf8b133132
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2845045946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2845045946
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.941649169
Short name T211
Test name
Test status
Simulation time 606276721 ps
CPU time 2.61 seconds
Started Jul 20 05:51:28 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 206468 kb
Host smart-f3749a13-10e2-4fef-8e47-11041718639d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=941649169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.941649169
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.2180251298
Short name T188
Test name
Test status
Simulation time 98608124 ps
CPU time 2.38 seconds
Started Jul 20 05:51:41 PM PDT 24
Finished Jul 20 05:51:44 PM PDT 24
Peak memory 214736 kb
Host smart-b3f4cbcf-acdb-4dba-be16-b86ebc1e4cda
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180251298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.2180251298
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.637379937
Short name T2758
Test name
Test status
Simulation time 84604136 ps
CPU time 0.88 seconds
Started Jul 20 05:51:33 PM PDT 24
Finished Jul 20 05:51:35 PM PDT 24
Peak memory 206276 kb
Host smart-70abb9c6-90ba-47dc-943d-84490e0196d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=637379937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.637379937
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.2263973812
Short name T2808
Test name
Test status
Simulation time 40672515 ps
CPU time 0.66 seconds
Started Jul 20 05:51:29 PM PDT 24
Finished Jul 20 05:51:32 PM PDT 24
Peak memory 206272 kb
Host smart-95285696-6c14-48b7-9d3b-eeb82add69df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2263973812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.2263973812
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.2182682069
Short name T2749
Test name
Test status
Simulation time 228486061 ps
CPU time 1.59 seconds
Started Jul 20 05:51:37 PM PDT 24
Finished Jul 20 05:51:39 PM PDT 24
Peak memory 206548 kb
Host smart-87a4ff8a-34c8-4760-9402-47a002c24d11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2182682069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.2182682069
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.409224584
Short name T2814
Test name
Test status
Simulation time 52959512 ps
CPU time 1.32 seconds
Started Jul 20 05:51:31 PM PDT 24
Finished Jul 20 05:51:34 PM PDT 24
Peak memory 206548 kb
Host smart-e131e7fb-d416-4c70-ae0e-388e3590b83d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=409224584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.409224584
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.572500517
Short name T845
Test name
Test status
Simulation time 105884081 ps
CPU time 0.75 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:18:24 PM PDT 24
Peak memory 206680 kb
Host smart-d1e74283-1b7e-491e-8eb3-22ca380018dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=572500517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.572500517
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.1397508949
Short name T541
Test name
Test status
Simulation time 3922872273 ps
CPU time 4.65 seconds
Started Jul 20 06:17:41 PM PDT 24
Finished Jul 20 06:17:46 PM PDT 24
Peak memory 206836 kb
Host smart-0bff04c4-7999-4da1-8aa0-4eb742f746c9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1397508949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.1397508949
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3477847555
Short name T609
Test name
Test status
Simulation time 13380264688 ps
CPU time 12.4 seconds
Started Jul 20 06:17:43 PM PDT 24
Finished Jul 20 06:17:56 PM PDT 24
Peak memory 206784 kb
Host smart-b2f99f27-5ea6-4e1c-952a-9ec8f14a401e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3477847555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3477847555
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.2721763733
Short name T1293
Test name
Test status
Simulation time 23429376959 ps
CPU time 24.37 seconds
Started Jul 20 06:17:42 PM PDT 24
Finished Jul 20 06:18:08 PM PDT 24
Peak memory 206784 kb
Host smart-2e6baef6-1163-4c55-882d-b90e96fe14a6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2721763733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.2721763733
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.658659554
Short name T2293
Test name
Test status
Simulation time 206274122 ps
CPU time 0.88 seconds
Started Jul 20 06:17:51 PM PDT 24
Finished Jul 20 06:17:52 PM PDT 24
Peak memory 206652 kb
Host smart-3b6f48ce-9dfe-4e8e-be6f-6121b16025ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65865
9554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.658659554
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.144250941
Short name T2071
Test name
Test status
Simulation time 148229738 ps
CPU time 0.83 seconds
Started Jul 20 06:17:53 PM PDT 24
Finished Jul 20 06:17:54 PM PDT 24
Peak memory 206656 kb
Host smart-63e0581a-3ba4-4946-8427-b2e929144500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14425
0941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.144250941
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.1062303063
Short name T2716
Test name
Test status
Simulation time 423579201 ps
CPU time 1.43 seconds
Started Jul 20 06:17:51 PM PDT 24
Finished Jul 20 06:17:53 PM PDT 24
Peak memory 206644 kb
Host smart-332b95b9-a9c5-4e4d-8d77-74884bf3e0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10623
03063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.1062303063
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.2043621958
Short name T876
Test name
Test status
Simulation time 1115850745 ps
CPU time 2.4 seconds
Started Jul 20 06:17:49 PM PDT 24
Finished Jul 20 06:17:52 PM PDT 24
Peak memory 206720 kb
Host smart-480ac5cb-b019-40b9-b34c-ce6ea4a1d368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20436
21958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.2043621958
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.2787358892
Short name T1365
Test name
Test status
Simulation time 21044355756 ps
CPU time 39.84 seconds
Started Jul 20 06:17:49 PM PDT 24
Finished Jul 20 06:18:29 PM PDT 24
Peak memory 206928 kb
Host smart-a8f7bc41-713d-46dd-91d3-9602171f4694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27873
58892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.2787358892
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.3443895671
Short name T2294
Test name
Test status
Simulation time 313495637 ps
CPU time 1.15 seconds
Started Jul 20 06:17:46 PM PDT 24
Finished Jul 20 06:17:48 PM PDT 24
Peak memory 206636 kb
Host smart-a5ca978c-92da-4740-9dbd-6209996b891f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34438
95671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.3443895671
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.2039648672
Short name T1890
Test name
Test status
Simulation time 184509797 ps
CPU time 0.79 seconds
Started Jul 20 06:17:50 PM PDT 24
Finished Jul 20 06:17:52 PM PDT 24
Peak memory 206660 kb
Host smart-5ccd50fe-b09e-457d-941c-189f03d20d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20396
48672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.2039648672
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.2612013789
Short name T1135
Test name
Test status
Simulation time 5117362507 ps
CPU time 31.47 seconds
Started Jul 20 06:17:50 PM PDT 24
Finished Jul 20 06:18:22 PM PDT 24
Peak memory 206868 kb
Host smart-a23dbf81-366c-44c6-b414-d5e0a76aa534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26120
13789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.2612013789
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.2662632453
Short name T2319
Test name
Test status
Simulation time 88636627 ps
CPU time 0.7 seconds
Started Jul 20 06:17:49 PM PDT 24
Finished Jul 20 06:17:50 PM PDT 24
Peak memory 206640 kb
Host smart-8aaf5bbf-02dd-4b02-a428-8409a649b089
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26626
32453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2662632453
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.3215284473
Short name T1043
Test name
Test status
Simulation time 858234621 ps
CPU time 2.02 seconds
Started Jul 20 06:17:50 PM PDT 24
Finished Jul 20 06:17:52 PM PDT 24
Peak memory 206704 kb
Host smart-3a2eff85-f172-4b4a-92ba-c3973c50eef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32152
84473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.3215284473
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.1093636201
Short name T42
Test name
Test status
Simulation time 86194015211 ps
CPU time 110.83 seconds
Started Jul 20 06:17:49 PM PDT 24
Finished Jul 20 06:19:41 PM PDT 24
Peak memory 206864 kb
Host smart-5534e6ad-63ec-400c-be35-4e6ca7c9d45e
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1093636201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.1093636201
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.4116240933
Short name T646
Test name
Test status
Simulation time 86201718231 ps
CPU time 119.3 seconds
Started Jul 20 06:17:51 PM PDT 24
Finished Jul 20 06:19:51 PM PDT 24
Peak memory 206856 kb
Host smart-52b93936-1eb0-4cf5-bfd9-40d4ce74abc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116240933 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.4116240933
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.2567614533
Short name T2695
Test name
Test status
Simulation time 108149333468 ps
CPU time 155.57 seconds
Started Jul 20 06:17:50 PM PDT 24
Finished Jul 20 06:20:26 PM PDT 24
Peak memory 206836 kb
Host smart-167f191d-18c5-4afd-8108-cbaea588ce3d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2567614533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.2567614533
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3922373675
Short name T2245
Test name
Test status
Simulation time 81109276507 ps
CPU time 124.28 seconds
Started Jul 20 06:17:50 PM PDT 24
Finished Jul 20 06:19:54 PM PDT 24
Peak memory 206864 kb
Host smart-aa01b667-4432-4323-8e0c-2b64f31a1073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922373675 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3922373675
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.2171892031
Short name T2213
Test name
Test status
Simulation time 81224549777 ps
CPU time 118.17 seconds
Started Jul 20 06:17:54 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 206848 kb
Host smart-331f553b-931d-43b9-aea8-838b0e78e6a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21718
92031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.2171892031
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.2644564233
Short name T486
Test name
Test status
Simulation time 204269832 ps
CPU time 0.92 seconds
Started Jul 20 06:17:57 PM PDT 24
Finished Jul 20 06:17:59 PM PDT 24
Peak memory 206644 kb
Host smart-f576e7e1-0d3d-47e9-aa04-ce08e9c17cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26445
64233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.2644564233
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.543775508
Short name T1250
Test name
Test status
Simulation time 152222281 ps
CPU time 0.78 seconds
Started Jul 20 06:17:58 PM PDT 24
Finished Jul 20 06:17:59 PM PDT 24
Peak memory 206636 kb
Host smart-5683a0d0-f08c-4bb8-9ada-ee0ca8199f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54377
5508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.543775508
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.2575939609
Short name T2629
Test name
Test status
Simulation time 206190622 ps
CPU time 0.84 seconds
Started Jul 20 06:18:05 PM PDT 24
Finished Jul 20 06:18:07 PM PDT 24
Peak memory 206660 kb
Host smart-575615fe-b5fa-4e34-a59c-3cfe12d1183f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25759
39609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.2575939609
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.2746488448
Short name T2204
Test name
Test status
Simulation time 11967654299 ps
CPU time 104.03 seconds
Started Jul 20 06:18:05 PM PDT 24
Finished Jul 20 06:19:50 PM PDT 24
Peak memory 206912 kb
Host smart-5aba4481-7bb3-4649-9b60-3e772cd741c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27464
88448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.2746488448
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.798653784
Short name T1742
Test name
Test status
Simulation time 217251734 ps
CPU time 0.86 seconds
Started Jul 20 06:17:56 PM PDT 24
Finished Jul 20 06:17:57 PM PDT 24
Peak memory 206632 kb
Host smart-febe0adb-86ab-4707-ae8b-ec8fba194d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79865
3784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.798653784
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.545072620
Short name T72
Test name
Test status
Simulation time 584578294 ps
CPU time 1.58 seconds
Started Jul 20 06:17:56 PM PDT 24
Finished Jul 20 06:17:58 PM PDT 24
Peak memory 206664 kb
Host smart-55d4e81b-3393-4926-a9f3-8a11c309f72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54507
2620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.545072620
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1011968045
Short name T1155
Test name
Test status
Simulation time 23347233873 ps
CPU time 25.53 seconds
Started Jul 20 06:17:56 PM PDT 24
Finished Jul 20 06:18:22 PM PDT 24
Peak memory 206776 kb
Host smart-4ed81817-9c1f-4b29-9aee-743c3a6a08a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10119
68045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1011968045
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.875565386
Short name T2604
Test name
Test status
Simulation time 3259375442 ps
CPU time 4.34 seconds
Started Jul 20 06:17:56 PM PDT 24
Finished Jul 20 06:18:01 PM PDT 24
Peak memory 206704 kb
Host smart-446062fb-8c0d-4f12-968a-5e7193a5331a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87556
5386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.875565386
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3137652393
Short name T1150
Test name
Test status
Simulation time 8605992207 ps
CPU time 76.65 seconds
Started Jul 20 06:17:55 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206916 kb
Host smart-505b37e6-0a1d-422e-8d29-eb782de77fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31376
52393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3137652393
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.225767973
Short name T1824
Test name
Test status
Simulation time 5761980585 ps
CPU time 151.33 seconds
Started Jul 20 06:17:55 PM PDT 24
Finished Jul 20 06:20:26 PM PDT 24
Peak memory 206864 kb
Host smart-df16c558-f656-4132-abc8-b305e30c7bbd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=225767973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.225767973
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.2894326265
Short name T2488
Test name
Test status
Simulation time 232021257 ps
CPU time 0.85 seconds
Started Jul 20 06:17:55 PM PDT 24
Finished Jul 20 06:17:56 PM PDT 24
Peak memory 206644 kb
Host smart-c4dbe45f-a68e-4f4f-90f3-4b0c269e3950
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2894326265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.2894326265
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.53692749
Short name T1324
Test name
Test status
Simulation time 196833229 ps
CPU time 0.87 seconds
Started Jul 20 06:17:57 PM PDT 24
Finished Jul 20 06:17:59 PM PDT 24
Peak memory 206644 kb
Host smart-35878126-3b87-4c70-8561-3ae59b4218bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53692
749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.53692749
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2228373318
Short name T496
Test name
Test status
Simulation time 3958570324 ps
CPU time 115.09 seconds
Started Jul 20 06:17:55 PM PDT 24
Finished Jul 20 06:19:50 PM PDT 24
Peak memory 206848 kb
Host smart-0871157b-181a-4cc3-b512-8f5b90121a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22283
73318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2228373318
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.3970994794
Short name T2660
Test name
Test status
Simulation time 3168738044 ps
CPU time 30.61 seconds
Started Jul 20 06:17:58 PM PDT 24
Finished Jul 20 06:18:29 PM PDT 24
Peak memory 206872 kb
Host smart-efc885e5-1457-4189-a941-459070fd1415
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3970994794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.3970994794
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1038484900
Short name T310
Test name
Test status
Simulation time 164345609 ps
CPU time 0.8 seconds
Started Jul 20 06:17:56 PM PDT 24
Finished Jul 20 06:17:57 PM PDT 24
Peak memory 206628 kb
Host smart-1ab278bc-8c1d-4143-8f18-9586cf777c51
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1038484900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1038484900
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.3703281308
Short name T2508
Test name
Test status
Simulation time 170089741 ps
CPU time 0.81 seconds
Started Jul 20 06:17:55 PM PDT 24
Finished Jul 20 06:17:56 PM PDT 24
Peak memory 206644 kb
Host smart-19485881-a32a-4ad5-b3ce-58d409ef457b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37032
81308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.3703281308
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3804324692
Short name T73
Test name
Test status
Simulation time 576235327 ps
CPU time 1.57 seconds
Started Jul 20 06:18:05 PM PDT 24
Finished Jul 20 06:18:08 PM PDT 24
Peak memory 206648 kb
Host smart-52ec7406-c0ff-4107-bb63-9bce1cef820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38043
24692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.3804324692
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2904478550
Short name T2225
Test name
Test status
Simulation time 194215194 ps
CPU time 0.87 seconds
Started Jul 20 06:18:02 PM PDT 24
Finished Jul 20 06:18:03 PM PDT 24
Peak memory 206696 kb
Host smart-c3b6ce7f-33b7-4cfc-8aa5-c1f43a6364da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29044
78550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2904478550
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2758108620
Short name T395
Test name
Test status
Simulation time 167708030 ps
CPU time 0.78 seconds
Started Jul 20 06:18:09 PM PDT 24
Finished Jul 20 06:18:10 PM PDT 24
Peak memory 206664 kb
Host smart-21949f56-2a15-404b-8c1b-4294db83ce67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27581
08620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2758108620
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.1308684403
Short name T1323
Test name
Test status
Simulation time 148421528 ps
CPU time 0.76 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:06 PM PDT 24
Peak memory 206608 kb
Host smart-9305c64f-bf4a-4f4b-aa13-5f52fab02922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13086
84403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.1308684403
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.32286868
Short name T2189
Test name
Test status
Simulation time 154827710 ps
CPU time 0.79 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:06 PM PDT 24
Peak memory 206656 kb
Host smart-d44f1caf-043d-4e7b-ba6d-00b5a69b8c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32286
868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.32286868
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2720278220
Short name T1774
Test name
Test status
Simulation time 179965316 ps
CPU time 0.82 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:06 PM PDT 24
Peak memory 206632 kb
Host smart-716674ec-27e1-497f-b35c-8008011de378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27202
78220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2720278220
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.365904988
Short name T2303
Test name
Test status
Simulation time 240961576 ps
CPU time 1.01 seconds
Started Jul 20 06:18:03 PM PDT 24
Finished Jul 20 06:18:05 PM PDT 24
Peak memory 206664 kb
Host smart-7da86195-4031-45c9-b781-65129e5a00da
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=365904988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.365904988
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.719740157
Short name T2417
Test name
Test status
Simulation time 189020765 ps
CPU time 0.88 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:06 PM PDT 24
Peak memory 206632 kb
Host smart-bcc4ccf2-e967-45a3-9700-721251038702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71974
0157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.719740157
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.571454951
Short name T2414
Test name
Test status
Simulation time 243725808 ps
CPU time 0.94 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:05 PM PDT 24
Peak memory 206652 kb
Host smart-8d042a48-2fe6-46e1-869b-8e2175718b0e
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=571454951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.571454951
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2282556506
Short name T194
Test name
Test status
Simulation time 210349010 ps
CPU time 0.9 seconds
Started Jul 20 06:18:09 PM PDT 24
Finished Jul 20 06:18:11 PM PDT 24
Peak memory 206664 kb
Host smart-5bca26ab-2f45-49c8-a073-2cb5f65701eb
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2282556506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2282556506
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3009014977
Short name T1011
Test name
Test status
Simulation time 147712065 ps
CPU time 0.81 seconds
Started Jul 20 06:18:09 PM PDT 24
Finished Jul 20 06:18:10 PM PDT 24
Peak memory 206632 kb
Host smart-c6138113-7f10-4f8b-bc3d-3837d0ebc534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30090
14977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3009014977
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.2039263421
Short name T711
Test name
Test status
Simulation time 43068358 ps
CPU time 0.66 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:05 PM PDT 24
Peak memory 206652 kb
Host smart-6b9fda42-6c9b-4871-9962-9c65888a0f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20392
63421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.2039263421
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.3518422777
Short name T1014
Test name
Test status
Simulation time 9260413389 ps
CPU time 21.08 seconds
Started Jul 20 06:18:04 PM PDT 24
Finished Jul 20 06:18:26 PM PDT 24
Peak memory 206936 kb
Host smart-70cf25fd-5b11-4db1-8622-35bb2f735ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35184
22777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.3518422777
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2544697912
Short name T296
Test name
Test status
Simulation time 238129069 ps
CPU time 0.93 seconds
Started Jul 20 06:18:02 PM PDT 24
Finished Jul 20 06:18:03 PM PDT 24
Peak memory 206668 kb
Host smart-f81db109-5863-4a62-a0ea-c45f42b3bd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25446
97912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2544697912
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.3172500734
Short name T393
Test name
Test status
Simulation time 233458248 ps
CPU time 0.9 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:19 PM PDT 24
Peak memory 206656 kb
Host smart-ae6639a0-3040-4cc6-bf63-e0af6fa0fc30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31725
00734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.3172500734
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.3872600306
Short name T164
Test name
Test status
Simulation time 15864507032 ps
CPU time 113.61 seconds
Started Jul 20 06:18:16 PM PDT 24
Finished Jul 20 06:20:10 PM PDT 24
Peak memory 206964 kb
Host smart-ef0a5655-3b27-438a-8746-7352705c9d7f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3872600306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.3872600306
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1395814655
Short name T895
Test name
Test status
Simulation time 16813427859 ps
CPU time 119.09 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:20:17 PM PDT 24
Peak memory 206944 kb
Host smart-c7b674a0-2799-4017-811e-4a23b4f7555c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1395814655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1395814655
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3032875772
Short name T1187
Test name
Test status
Simulation time 241572046 ps
CPU time 0.88 seconds
Started Jul 20 06:18:19 PM PDT 24
Finished Jul 20 06:18:20 PM PDT 24
Peak memory 206644 kb
Host smart-94847483-1145-448b-8dd9-30550f8aaeaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30328
75772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3032875772
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.3159510542
Short name T411
Test name
Test status
Simulation time 192933939 ps
CPU time 0.87 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:19 PM PDT 24
Peak memory 206636 kb
Host smart-6a5ebc3d-bd32-4aa3-8773-04c3cfc0e0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31595
10542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.3159510542
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.2452378034
Short name T1179
Test name
Test status
Simulation time 213778304 ps
CPU time 0.9 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:18 PM PDT 24
Peak memory 206644 kb
Host smart-b9b429b9-3171-4a43-bf69-f281d3f5eb46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24523
78034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.2452378034
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.3700047916
Short name T173
Test name
Test status
Simulation time 306311774 ps
CPU time 0.97 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:19 PM PDT 24
Peak memory 206656 kb
Host smart-c1b827fb-b144-42b8-b4ef-a884b363c381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37000
47916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.3700047916
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3306826109
Short name T1878
Test name
Test status
Simulation time 149097586 ps
CPU time 0.8 seconds
Started Jul 20 06:18:17 PM PDT 24
Finished Jul 20 06:18:19 PM PDT 24
Peak memory 206636 kb
Host smart-d24240ee-633a-45e4-a575-2a498ce7c87d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33068
26109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3306826109
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.2713099536
Short name T1167
Test name
Test status
Simulation time 158420900 ps
CPU time 0.82 seconds
Started Jul 20 06:18:16 PM PDT 24
Finished Jul 20 06:18:18 PM PDT 24
Peak memory 206648 kb
Host smart-11c013f2-dfd2-402d-baf8-74b16d8a642e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27130
99536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.2713099536
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.3602450223
Short name T155
Test name
Test status
Simulation time 222283452 ps
CPU time 0.89 seconds
Started Jul 20 06:18:16 PM PDT 24
Finished Jul 20 06:18:17 PM PDT 24
Peak memory 206656 kb
Host smart-fd0b3888-d5a3-48dc-b914-2370d416a9a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36024
50223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.3602450223
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.3021405586
Short name T752
Test name
Test status
Simulation time 4169499859 ps
CPU time 39.99 seconds
Started Jul 20 06:18:16 PM PDT 24
Finished Jul 20 06:18:57 PM PDT 24
Peak memory 206816 kb
Host smart-856486ba-3e40-4647-9984-2c06eeef1c56
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3021405586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.3021405586
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.146796695
Short name T1522
Test name
Test status
Simulation time 151369693 ps
CPU time 0.8 seconds
Started Jul 20 06:18:19 PM PDT 24
Finished Jul 20 06:18:20 PM PDT 24
Peak memory 206652 kb
Host smart-7bcaa5cf-5ecb-4e4f-ac0b-2b293a94df29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14679
6695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.146796695
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.537004438
Short name T1503
Test name
Test status
Simulation time 152130515 ps
CPU time 0.76 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:18:24 PM PDT 24
Peak memory 206652 kb
Host smart-bff3aa4f-29c7-4bd0-91ba-898b1431507c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53700
4438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.537004438
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.213300937
Short name T2700
Test name
Test status
Simulation time 1205300706 ps
CPU time 2.87 seconds
Started Jul 20 06:18:26 PM PDT 24
Finished Jul 20 06:18:30 PM PDT 24
Peak memory 206648 kb
Host smart-ba57fb44-76df-4d56-b71c-9b714c42f32f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21330
0937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.213300937
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.773001476
Short name T988
Test name
Test status
Simulation time 6322253330 ps
CPU time 42.99 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:19:07 PM PDT 24
Peak memory 207016 kb
Host smart-9fb319f4-8c89-4c01-bee6-0bdcd08f5fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77300
1476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.773001476
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3945226559
Short name T2689
Test name
Test status
Simulation time 7258066867 ps
CPU time 183.82 seconds
Started Jul 20 06:18:25 PM PDT 24
Finished Jul 20 06:21:30 PM PDT 24
Peak memory 207016 kb
Host smart-83555d19-1d15-4c95-b7f6-93e145d3ad84
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3945226559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3945226559
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.1745117996
Short name T1434
Test name
Test status
Simulation time 66345218 ps
CPU time 0.71 seconds
Started Jul 20 06:18:40 PM PDT 24
Finished Jul 20 06:18:42 PM PDT 24
Peak memory 206716 kb
Host smart-e1d88ada-d781-4d87-b5e3-e6fb1c506e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1745117996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.1745117996
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.11395886
Short name T2080
Test name
Test status
Simulation time 4083243425 ps
CPU time 5.4 seconds
Started Jul 20 06:18:27 PM PDT 24
Finished Jul 20 06:18:33 PM PDT 24
Peak memory 206840 kb
Host smart-6d278369-c755-40f9-bf03-70ed9548971b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=11395886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.11395886
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3248161564
Short name T2423
Test name
Test status
Simulation time 13445970396 ps
CPU time 12.33 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:18:36 PM PDT 24
Peak memory 206924 kb
Host smart-3e08be12-3d81-488a-b757-6bb665b519d3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3248161564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3248161564
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.4119331515
Short name T1384
Test name
Test status
Simulation time 23335182244 ps
CPU time 23.93 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:18:47 PM PDT 24
Peak memory 206776 kb
Host smart-1eb5150a-25b9-4066-a981-fc52648f2ff3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4119331515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.4119331515
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.4285791288
Short name T2241
Test name
Test status
Simulation time 149993605 ps
CPU time 0.82 seconds
Started Jul 20 06:18:24 PM PDT 24
Finished Jul 20 06:18:26 PM PDT 24
Peak memory 206668 kb
Host smart-8a8ef707-65fb-4a96-a6de-8967997089d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42857
91288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.4285791288
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1844421257
Short name T2476
Test name
Test status
Simulation time 184737773 ps
CPU time 0.83 seconds
Started Jul 20 06:18:24 PM PDT 24
Finished Jul 20 06:18:25 PM PDT 24
Peak memory 206652 kb
Host smart-0a60366e-1fba-4f67-8340-d15caee9a94f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18444
21257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1844421257
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.2176876275
Short name T33
Test name
Test status
Simulation time 141281751 ps
CPU time 0.76 seconds
Started Jul 20 06:18:24 PM PDT 24
Finished Jul 20 06:18:26 PM PDT 24
Peak memory 206648 kb
Host smart-382c2033-aac2-4414-b35c-409c620037b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21768
76275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.2176876275
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.1398807532
Short name T648
Test name
Test status
Simulation time 175826911 ps
CPU time 0.88 seconds
Started Jul 20 06:18:27 PM PDT 24
Finished Jul 20 06:18:28 PM PDT 24
Peak memory 206632 kb
Host smart-49ee25b2-079b-4836-b098-1aeef971f617
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13988
07532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.1398807532
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.735400290
Short name T641
Test name
Test status
Simulation time 378867342 ps
CPU time 1.31 seconds
Started Jul 20 06:18:25 PM PDT 24
Finished Jul 20 06:18:27 PM PDT 24
Peak memory 206652 kb
Host smart-d3d1476e-f456-4452-84ea-4aa9cccfb7a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73540
0290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.735400290
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.2553753526
Short name T1331
Test name
Test status
Simulation time 1244127507 ps
CPU time 2.67 seconds
Started Jul 20 06:18:25 PM PDT 24
Finished Jul 20 06:18:29 PM PDT 24
Peak memory 206768 kb
Host smart-b3e285ac-31ee-4af6-8af0-da741165c56e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25537
53526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.2553753526
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.2118541979
Short name T2202
Test name
Test status
Simulation time 15200869332 ps
CPU time 29.84 seconds
Started Jul 20 06:18:26 PM PDT 24
Finished Jul 20 06:18:56 PM PDT 24
Peak memory 206928 kb
Host smart-dd1228b4-0690-46a3-a0d0-b4aa8b602f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21185
41979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.2118541979
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.2070394333
Short name T1329
Test name
Test status
Simulation time 382289396 ps
CPU time 1.18 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:18:25 PM PDT 24
Peak memory 206648 kb
Host smart-46821f00-c963-4e27-9c73-1cbb63ee2955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20703
94333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.2070394333
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.4140154744
Short name T2250
Test name
Test status
Simulation time 169251619 ps
CPU time 0.78 seconds
Started Jul 20 06:18:38 PM PDT 24
Finished Jul 20 06:18:39 PM PDT 24
Peak memory 206640 kb
Host smart-92879dec-95e5-486c-9db8-8e45c09d7673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41401
54744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.4140154744
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.2696934102
Short name T229
Test name
Test status
Simulation time 127105739 ps
CPU time 0.77 seconds
Started Jul 20 06:18:25 PM PDT 24
Finished Jul 20 06:18:26 PM PDT 24
Peak memory 206632 kb
Host smart-d7c57294-22ac-40c0-bffb-bff591a5658b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26969
34102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.2696934102
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.148156408
Short name T1627
Test name
Test status
Simulation time 811501879 ps
CPU time 2.08 seconds
Started Jul 20 06:18:22 PM PDT 24
Finished Jul 20 06:18:25 PM PDT 24
Peak memory 206688 kb
Host smart-fd76db9e-1aff-432b-b44e-20f5a88d0a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14815
6408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.148156408
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.1422519862
Short name T2070
Test name
Test status
Simulation time 264348599 ps
CPU time 1.61 seconds
Started Jul 20 06:18:23 PM PDT 24
Finished Jul 20 06:18:25 PM PDT 24
Peak memory 206804 kb
Host smart-0fd238f4-db89-4008-9845-d92e7f3d54a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14225
19862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.1422519862
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.1274466900
Short name T318
Test name
Test status
Simulation time 89187547154 ps
CPU time 114.46 seconds
Started Jul 20 06:18:26 PM PDT 24
Finished Jul 20 06:20:21 PM PDT 24
Peak memory 206844 kb
Host smart-e52b417b-bd76-46c3-bff0-a95197537ae9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1274466900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.1274466900
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3476052097
Short name T2418
Test name
Test status
Simulation time 101129143319 ps
CPU time 137.39 seconds
Started Jul 20 06:18:30 PM PDT 24
Finished Jul 20 06:20:47 PM PDT 24
Peak memory 206876 kb
Host smart-3e0ee89c-6a88-4536-8e47-80b4409208f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476052097 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3476052097
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.3634160738
Short name T239
Test name
Test status
Simulation time 106101212140 ps
CPU time 150.99 seconds
Started Jul 20 06:18:35 PM PDT 24
Finished Jul 20 06:21:07 PM PDT 24
Peak memory 206864 kb
Host smart-20b7489b-2f5e-42f1-adec-8983657ea1b1
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3634160738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.3634160738
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.3345806427
Short name T972
Test name
Test status
Simulation time 84056190967 ps
CPU time 105.69 seconds
Started Jul 20 06:18:34 PM PDT 24
Finished Jul 20 06:20:20 PM PDT 24
Peak memory 206936 kb
Host smart-0f39624c-4660-485f-bad0-8ef79dd6e6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345806427 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.3345806427
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.617654392
Short name T1046
Test name
Test status
Simulation time 106144819595 ps
CPU time 133.38 seconds
Started Jul 20 06:18:31 PM PDT 24
Finished Jul 20 06:20:45 PM PDT 24
Peak memory 206920 kb
Host smart-e7eb1319-1ca0-47c0-88c4-adf0fc01350c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61765
4392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.617654392
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1948758906
Short name T2739
Test name
Test status
Simulation time 244136622 ps
CPU time 0.91 seconds
Started Jul 20 06:18:39 PM PDT 24
Finished Jul 20 06:18:41 PM PDT 24
Peak memory 206628 kb
Host smart-3076512a-ef9f-43dc-94a4-3ef9f74b921b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19487
58906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1948758906
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.804951133
Short name T1581
Test name
Test status
Simulation time 136021402 ps
CPU time 0.77 seconds
Started Jul 20 06:18:32 PM PDT 24
Finished Jul 20 06:18:33 PM PDT 24
Peak memory 206628 kb
Host smart-cc6b7304-0be7-4157-9eaa-583658ee8eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80495
1133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.804951133
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.1012934824
Short name T1656
Test name
Test status
Simulation time 183645879 ps
CPU time 0.84 seconds
Started Jul 20 06:18:34 PM PDT 24
Finished Jul 20 06:18:36 PM PDT 24
Peak memory 206652 kb
Host smart-9271b936-1d54-40fd-aa8f-3ab7c9e80e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10129
34824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.1012934824
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.2947429271
Short name T2670
Test name
Test status
Simulation time 12449939912 ps
CPU time 106.09 seconds
Started Jul 20 06:18:35 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206900 kb
Host smart-934ed8ad-14e7-4ffe-a6bf-3874521ae562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29474
29271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.2947429271
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.3211093193
Short name T2133
Test name
Test status
Simulation time 164933634 ps
CPU time 0.8 seconds
Started Jul 20 06:18:33 PM PDT 24
Finished Jul 20 06:18:34 PM PDT 24
Peak memory 206652 kb
Host smart-7845bdb7-61ee-45da-b374-cd91edc97601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32110
93193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.3211093193
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3230571501
Short name T2746
Test name
Test status
Simulation time 23311794252 ps
CPU time 20.86 seconds
Started Jul 20 06:18:32 PM PDT 24
Finished Jul 20 06:18:53 PM PDT 24
Peak memory 206756 kb
Host smart-87134543-c778-4530-9156-5ceb35f33b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32305
71501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3230571501
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.3717773940
Short name T1632
Test name
Test status
Simulation time 3308460947 ps
CPU time 3.7 seconds
Started Jul 20 06:18:33 PM PDT 24
Finished Jul 20 06:18:37 PM PDT 24
Peak memory 206716 kb
Host smart-c7f4bec3-86d5-4341-9c96-563f4aa5bf24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37177
73940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.3717773940
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.698541797
Short name T2568
Test name
Test status
Simulation time 7515190317 ps
CPU time 52.65 seconds
Started Jul 20 06:18:36 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 206900 kb
Host smart-ca2edda5-d3fe-4c8d-b6ff-9bb4bb896939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69854
1797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.698541797
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.1306921120
Short name T1097
Test name
Test status
Simulation time 5639428229 ps
CPU time 155.63 seconds
Started Jul 20 06:18:33 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206856 kb
Host smart-bb432b97-4a91-4800-8b46-729213c43373
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1306921120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.1306921120
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.3887249446
Short name T407
Test name
Test status
Simulation time 242869347 ps
CPU time 0.88 seconds
Started Jul 20 06:18:34 PM PDT 24
Finished Jul 20 06:18:36 PM PDT 24
Peak memory 206652 kb
Host smart-b784047a-6f49-4813-8881-12b6b76465b3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3887249446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.3887249446
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.1278522673
Short name T1202
Test name
Test status
Simulation time 182900058 ps
CPU time 0.89 seconds
Started Jul 20 06:18:46 PM PDT 24
Finished Jul 20 06:18:48 PM PDT 24
Peak memory 206652 kb
Host smart-daa2a3cc-7fc3-4956-8063-c5a7d583b230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12785
22673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.1278522673
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2604302703
Short name T1903
Test name
Test status
Simulation time 5271600625 ps
CPU time 48.38 seconds
Started Jul 20 06:18:39 PM PDT 24
Finished Jul 20 06:19:28 PM PDT 24
Peak memory 206916 kb
Host smart-857c9b08-36cf-4d10-9a1f-a47d4d14dfdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26043
02703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2604302703
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.3986311568
Short name T623
Test name
Test status
Simulation time 7173664695 ps
CPU time 65.8 seconds
Started Jul 20 06:18:33 PM PDT 24
Finished Jul 20 06:19:40 PM PDT 24
Peak memory 206864 kb
Host smart-b476c52b-e64e-4056-9058-9bf21d61cdc9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3986311568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.3986311568
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.117982092
Short name T851
Test name
Test status
Simulation time 201574047 ps
CPU time 0.8 seconds
Started Jul 20 06:18:35 PM PDT 24
Finished Jul 20 06:18:37 PM PDT 24
Peak memory 206320 kb
Host smart-e82141ca-18f1-4ede-87cc-14ca5b425e9c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=117982092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.117982092
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1514264321
Short name T2282
Test name
Test status
Simulation time 154436891 ps
CPU time 0.83 seconds
Started Jul 20 06:18:32 PM PDT 24
Finished Jul 20 06:18:33 PM PDT 24
Peak memory 206624 kb
Host smart-4c9c84c6-32a1-4b30-a81b-8cee200cc3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15142
64321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1514264321
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.3641853024
Short name T966
Test name
Test status
Simulation time 183984462 ps
CPU time 0.87 seconds
Started Jul 20 06:18:40 PM PDT 24
Finished Jul 20 06:18:41 PM PDT 24
Peak memory 206632 kb
Host smart-6d145bf0-5268-4aa1-8ee7-f8a8e7fe0042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36418
53024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.3641853024
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3808251211
Short name T1185
Test name
Test status
Simulation time 155049754 ps
CPU time 0.84 seconds
Started Jul 20 06:18:37 PM PDT 24
Finished Jul 20 06:18:39 PM PDT 24
Peak memory 206624 kb
Host smart-b7f7d86c-dcc5-4cd2-89cf-0aae9cc97062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38082
51211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3808251211
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3055076654
Short name T1260
Test name
Test status
Simulation time 158001960 ps
CPU time 0.78 seconds
Started Jul 20 06:18:39 PM PDT 24
Finished Jul 20 06:18:41 PM PDT 24
Peak memory 206636 kb
Host smart-0c73cd1b-fe99-436b-a617-3f49fa05f38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30550
76654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3055076654
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.2984265694
Short name T1955
Test name
Test status
Simulation time 218311044 ps
CPU time 0.83 seconds
Started Jul 20 06:18:32 PM PDT 24
Finished Jul 20 06:18:34 PM PDT 24
Peak memory 206664 kb
Host smart-40b4f054-0211-41a8-8fb7-e42941929162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29842
65694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.2984265694
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.3372382480
Short name T1020
Test name
Test status
Simulation time 211089846 ps
CPU time 0.9 seconds
Started Jul 20 06:18:33 PM PDT 24
Finished Jul 20 06:18:35 PM PDT 24
Peak memory 206648 kb
Host smart-5b13dbeb-ba8b-45c9-9a9c-055538314388
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3372382480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.3372382480
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.3513305918
Short name T2044
Test name
Test status
Simulation time 208415469 ps
CPU time 0.89 seconds
Started Jul 20 06:18:31 PM PDT 24
Finished Jul 20 06:18:32 PM PDT 24
Peak memory 206656 kb
Host smart-9822ba7a-11e3-4ee7-ad3f-9c1f08c99d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35133
05918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.3513305918
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2074609381
Short name T2285
Test name
Test status
Simulation time 37375996 ps
CPU time 0.68 seconds
Started Jul 20 06:18:33 PM PDT 24
Finished Jul 20 06:18:34 PM PDT 24
Peak memory 206644 kb
Host smart-4cdd9af1-9e0e-466f-83f7-5e99928c2b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20746
09381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2074609381
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.62468239
Short name T244
Test name
Test status
Simulation time 8147572203 ps
CPU time 18.46 seconds
Started Jul 20 06:18:35 PM PDT 24
Finished Jul 20 06:18:54 PM PDT 24
Peak memory 206896 kb
Host smart-cc6f5918-6d5a-4aa2-ae1d-6b492157a8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62468
239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.62468239
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.1707734692
Short name T1122
Test name
Test status
Simulation time 194839368 ps
CPU time 0.82 seconds
Started Jul 20 06:18:31 PM PDT 24
Finished Jul 20 06:18:33 PM PDT 24
Peak memory 206656 kb
Host smart-ba1fff91-fc38-41e3-b431-5c7610d35a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17077
34692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.1707734692
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.2139589972
Short name T1350
Test name
Test status
Simulation time 215696976 ps
CPU time 0.95 seconds
Started Jul 20 06:18:48 PM PDT 24
Finished Jul 20 06:18:49 PM PDT 24
Peak memory 206624 kb
Host smart-2994416c-b2d8-4a55-91aa-491c6d90f0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21395
89972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.2139589972
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.1025717231
Short name T651
Test name
Test status
Simulation time 10969233423 ps
CPU time 53.41 seconds
Started Jul 20 06:18:44 PM PDT 24
Finished Jul 20 06:19:38 PM PDT 24
Peak memory 206912 kb
Host smart-4ca74945-6e70-4004-b086-21b4abab525d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1025717231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.1025717231
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.3807411819
Short name T160
Test name
Test status
Simulation time 11818586336 ps
CPU time 59.03 seconds
Started Jul 20 06:18:48 PM PDT 24
Finished Jul 20 06:19:48 PM PDT 24
Peak memory 206856 kb
Host smart-434b2bcd-f692-48cd-b230-56cf1c127d0b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3807411819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.3807411819
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.2612286675
Short name T2723
Test name
Test status
Simulation time 19226284705 ps
CPU time 442.96 seconds
Started Jul 20 06:18:46 PM PDT 24
Finished Jul 20 06:26:10 PM PDT 24
Peak memory 206900 kb
Host smart-e7ef4d85-494a-4002-8f7b-e97cdf9d97f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2612286675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.2612286675
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.3961802529
Short name T2455
Test name
Test status
Simulation time 174071927 ps
CPU time 0.86 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:18:45 PM PDT 24
Peak memory 206652 kb
Host smart-8192be01-4615-4826-8ba5-6b597b4056f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39618
02529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.3961802529
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.3918261438
Short name T2618
Test name
Test status
Simulation time 183120316 ps
CPU time 0.88 seconds
Started Jul 20 06:18:44 PM PDT 24
Finished Jul 20 06:18:46 PM PDT 24
Peak memory 206652 kb
Host smart-be84b0b0-5e29-4272-9c9a-b3a016e80168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39182
61438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.3918261438
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.2629166893
Short name T2482
Test name
Test status
Simulation time 225002091 ps
CPU time 0.81 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:18:45 PM PDT 24
Peak memory 206664 kb
Host smart-965f4091-3e3d-449d-bb32-45c244adcc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26291
66893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.2629166893
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.2726957184
Short name T79
Test name
Test status
Simulation time 156105674 ps
CPU time 0.83 seconds
Started Jul 20 06:18:42 PM PDT 24
Finished Jul 20 06:18:44 PM PDT 24
Peak memory 206660 kb
Host smart-9825ced4-81db-4c3e-b002-de4e0772e090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27269
57184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.2726957184
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3284512004
Short name T200
Test name
Test status
Simulation time 971617852 ps
CPU time 1.77 seconds
Started Jul 20 06:18:46 PM PDT 24
Finished Jul 20 06:18:48 PM PDT 24
Peak memory 224500 kb
Host smart-a3d25c8e-0df7-4810-a02a-af281d30db31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3284512004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3284512004
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.3025439069
Short name T1472
Test name
Test status
Simulation time 361450404 ps
CPU time 1.23 seconds
Started Jul 20 06:18:42 PM PDT 24
Finished Jul 20 06:18:43 PM PDT 24
Peak memory 206696 kb
Host smart-908e9faa-c8ae-4673-a4dc-38ce9015614c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30254
39069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.3025439069
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.1651068440
Short name T1776
Test name
Test status
Simulation time 241679770 ps
CPU time 0.96 seconds
Started Jul 20 06:18:44 PM PDT 24
Finished Jul 20 06:18:46 PM PDT 24
Peak memory 206632 kb
Host smart-7b647936-4deb-4a70-bfa3-e1f67d5ad192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16510
68440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.1651068440
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.2432216743
Short name T19
Test name
Test status
Simulation time 154738987 ps
CPU time 0.93 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:18:46 PM PDT 24
Peak memory 206636 kb
Host smart-c33a51e9-ad9a-4e82-8916-23af272b0475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24322
16743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.2432216743
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1583051806
Short name T1626
Test name
Test status
Simulation time 166925668 ps
CPU time 0.83 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:18:45 PM PDT 24
Peak memory 206768 kb
Host smart-56ce23cb-adfc-4894-9268-fd453f61df90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15830
51806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1583051806
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2998697802
Short name T1712
Test name
Test status
Simulation time 205344412 ps
CPU time 0.9 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:18:46 PM PDT 24
Peak memory 206644 kb
Host smart-405d465d-dd9f-4a88-bd72-b85acffbea7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29986
97802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2998697802
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2660110148
Short name T2523
Test name
Test status
Simulation time 6082471921 ps
CPU time 162.71 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:21:27 PM PDT 24
Peak memory 206864 kb
Host smart-bef4a29e-4d6f-4f49-ab4b-3def1b479a90
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2660110148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2660110148
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.1918089481
Short name T413
Test name
Test status
Simulation time 184263225 ps
CPU time 0.79 seconds
Started Jul 20 06:18:44 PM PDT 24
Finished Jul 20 06:18:46 PM PDT 24
Peak memory 206660 kb
Host smart-4f80f184-72e1-4411-b1be-7739fa471cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19180
89481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.1918089481
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1647649780
Short name T891
Test name
Test status
Simulation time 172617928 ps
CPU time 0.85 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:18:44 PM PDT 24
Peak memory 206652 kb
Host smart-12af39ac-a036-4625-ab21-58ac13ba8c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
49780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1647649780
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2031313428
Short name T1863
Test name
Test status
Simulation time 1329777946 ps
CPU time 2.71 seconds
Started Jul 20 06:18:45 PM PDT 24
Finished Jul 20 06:18:48 PM PDT 24
Peak memory 206780 kb
Host smart-4ec0aba3-d578-4441-8629-abba819d47c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20313
13428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2031313428
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1989304385
Short name T1647
Test name
Test status
Simulation time 4194052528 ps
CPU time 117.68 seconds
Started Jul 20 06:18:43 PM PDT 24
Finished Jul 20 06:20:42 PM PDT 24
Peak memory 206804 kb
Host smart-1e87dd29-4752-44f5-b0c8-b64d6efe01af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19893
04385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1989304385
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.2912068115
Short name T2554
Test name
Test status
Simulation time 137083652 ps
CPU time 0.78 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 206696 kb
Host smart-e40a9d7f-a32d-42e4-b3bd-6bf110017185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2912068115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.2912068115
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.2333296635
Short name T1183
Test name
Test status
Simulation time 3455480008 ps
CPU time 4.09 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:21:02 PM PDT 24
Peak memory 206716 kb
Host smart-7120518b-f97a-481a-925d-ed26e724bdcb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2333296635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.2333296635
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1356118976
Short name T1603
Test name
Test status
Simulation time 13355320550 ps
CPU time 11.59 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206864 kb
Host smart-bfe64b3f-0cfe-483d-b3ce-15c660bad487
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1356118976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1356118976
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.106285605
Short name T2331
Test name
Test status
Simulation time 23403419685 ps
CPU time 25.87 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:34 PM PDT 24
Peak memory 206920 kb
Host smart-2f824ea6-b87d-4c13-8bb7-122137325b40
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=106285605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.106285605
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.1095447407
Short name T518
Test name
Test status
Simulation time 160708488 ps
CPU time 0.8 seconds
Started Jul 20 06:21:05 PM PDT 24
Finished Jul 20 06:21:06 PM PDT 24
Peak memory 206656 kb
Host smart-25e0829c-2d8e-4b15-b5b8-caf1553d2022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10954
47407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.1095447407
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.4026269862
Short name T1979
Test name
Test status
Simulation time 240417106 ps
CPU time 0.86 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206668 kb
Host smart-00f21d31-b935-4a34-bd72-168929e3d9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40262
69862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.4026269862
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.1103448739
Short name T2494
Test name
Test status
Simulation time 242746402 ps
CPU time 0.95 seconds
Started Jul 20 06:21:09 PM PDT 24
Finished Jul 20 06:21:11 PM PDT 24
Peak memory 206636 kb
Host smart-5d18e721-1ea7-4df9-98da-5627507c6c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11034
48739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.1103448739
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.344642058
Short name T582
Test name
Test status
Simulation time 493841639 ps
CPU time 1.42 seconds
Started Jul 20 06:21:07 PM PDT 24
Finished Jul 20 06:21:09 PM PDT 24
Peak memory 206592 kb
Host smart-19a4d6e7-ae42-455b-8ef8-2ca3989c6dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34464
2058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.344642058
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.2172650958
Short name T1493
Test name
Test status
Simulation time 455267880 ps
CPU time 1.37 seconds
Started Jul 20 06:21:07 PM PDT 24
Finished Jul 20 06:21:09 PM PDT 24
Peak memory 206656 kb
Host smart-a5133c65-2132-4aeb-9fdb-50a554b2f97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21726
50958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.2172650958
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3871265272
Short name T48
Test name
Test status
Simulation time 143691937 ps
CPU time 0.74 seconds
Started Jul 20 06:21:05 PM PDT 24
Finished Jul 20 06:21:07 PM PDT 24
Peak memory 206632 kb
Host smart-9128c074-162a-4c14-8d28-dd66cacc0dd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38712
65272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3871265272
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.564906578
Short name T1696
Test name
Test status
Simulation time 46957641 ps
CPU time 0.67 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206640 kb
Host smart-fdf6c634-659b-4994-bf60-ec3a55d9c076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56490
6578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.564906578
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.2285868444
Short name T329
Test name
Test status
Simulation time 992807193 ps
CPU time 2.35 seconds
Started Jul 20 06:21:07 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206800 kb
Host smart-175a5911-c08f-4e63-9728-2198e45a96a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22858
68444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.2285868444
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.277109500
Short name T2054
Test name
Test status
Simulation time 184324856 ps
CPU time 1.95 seconds
Started Jul 20 06:21:06 PM PDT 24
Finished Jul 20 06:21:08 PM PDT 24
Peak memory 206792 kb
Host smart-cd0934cd-6b1b-4e48-9762-7f2b1258cb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27710
9500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.277109500
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.3030896859
Short name T2017
Test name
Test status
Simulation time 215716105 ps
CPU time 0.9 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206648 kb
Host smart-90f0b2fa-4e60-4d16-8caf-9c54296e2e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30308
96859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.3030896859
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3324035388
Short name T348
Test name
Test status
Simulation time 161162479 ps
CPU time 0.82 seconds
Started Jul 20 06:21:06 PM PDT 24
Finished Jul 20 06:21:07 PM PDT 24
Peak memory 206652 kb
Host smart-46e7a25e-7b60-4349-a196-81a99cc53c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33240
35388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3324035388
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.2391881564
Short name T1170
Test name
Test status
Simulation time 226863720 ps
CPU time 0.99 seconds
Started Jul 20 06:21:09 PM PDT 24
Finished Jul 20 06:21:11 PM PDT 24
Peak memory 206648 kb
Host smart-c52d5738-ac54-4f3e-b36c-d1b857f07ea2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23918
81564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.2391881564
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.1025591518
Short name T927
Test name
Test status
Simulation time 10193530072 ps
CPU time 77.36 seconds
Started Jul 20 06:21:05 PM PDT 24
Finished Jul 20 06:22:23 PM PDT 24
Peak memory 206868 kb
Host smart-617ccba6-95b3-4141-9dba-d6534ce4a2f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10255
91518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.1025591518
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2517227895
Short name T2358
Test name
Test status
Simulation time 180236943 ps
CPU time 0.83 seconds
Started Jul 20 06:21:05 PM PDT 24
Finished Jul 20 06:21:06 PM PDT 24
Peak memory 206628 kb
Host smart-eccce553-68eb-461b-bb8d-966d980d300a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25172
27895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2517227895
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.943275337
Short name T2228
Test name
Test status
Simulation time 23326451635 ps
CPU time 22.76 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:32 PM PDT 24
Peak memory 206748 kb
Host smart-7ebe232d-ddfa-4ba9-88ab-ff0dd5944406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94327
5337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.943275337
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2088324165
Short name T2401
Test name
Test status
Simulation time 3383047346 ps
CPU time 3.81 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:13 PM PDT 24
Peak memory 206720 kb
Host smart-d908d4fb-516a-4dc8-b752-84e5e9292b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20883
24165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2088324165
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.2009152125
Short name T2007
Test name
Test status
Simulation time 5998423265 ps
CPU time 156.42 seconds
Started Jul 20 06:21:14 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206852 kb
Host smart-aee0c60d-6d1e-4044-bf9e-1d6a59061370
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2009152125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.2009152125
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1482577906
Short name T905
Test name
Test status
Simulation time 246165223 ps
CPU time 0.97 seconds
Started Jul 20 06:21:10 PM PDT 24
Finished Jul 20 06:21:11 PM PDT 24
Peak memory 206656 kb
Host smart-3261e77c-da02-4422-9931-2d51276cdd7c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1482577906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1482577906
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3135905071
Short name T1063
Test name
Test status
Simulation time 194686888 ps
CPU time 0.86 seconds
Started Jul 20 06:21:13 PM PDT 24
Finished Jul 20 06:21:15 PM PDT 24
Peak memory 206652 kb
Host smart-eda8c2e3-f36f-4235-aa80-4cd0008c0a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31359
05071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3135905071
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.3860828416
Short name T1465
Test name
Test status
Simulation time 5776708362 ps
CPU time 43.45 seconds
Started Jul 20 06:21:07 PM PDT 24
Finished Jul 20 06:21:51 PM PDT 24
Peak memory 206896 kb
Host smart-69ca4f5a-842a-4c47-8d82-2aa4f516f471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
28416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.3860828416
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.1124350843
Short name T2687
Test name
Test status
Simulation time 3608338850 ps
CPU time 100.87 seconds
Started Jul 20 06:21:14 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 206884 kb
Host smart-8a8ad955-08f1-4cd4-b630-91c15f2e3379
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1124350843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.1124350843
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3266523645
Short name T1667
Test name
Test status
Simulation time 204558013 ps
CPU time 0.85 seconds
Started Jul 20 06:21:06 PM PDT 24
Finished Jul 20 06:21:08 PM PDT 24
Peak memory 206648 kb
Host smart-6753cb92-a322-4ef8-ac64-a49dc0d6cae0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3266523645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3266523645
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1298950853
Short name T578
Test name
Test status
Simulation time 149646132 ps
CPU time 0.75 seconds
Started Jul 20 06:21:08 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206640 kb
Host smart-ee2d0e35-af40-400f-ad37-d3eec0ace3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12989
50853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1298950853
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1366824953
Short name T987
Test name
Test status
Simulation time 175498864 ps
CPU time 0.82 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:20 PM PDT 24
Peak memory 206652 kb
Host smart-3beef322-acd4-4a75-9400-e3bb78371901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13668
24953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1366824953
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.1875386526
Short name T781
Test name
Test status
Simulation time 189563784 ps
CPU time 0.83 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 206648 kb
Host smart-16649cc5-52a3-4822-8a15-e4160084c5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18753
86526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.1875386526
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.415671479
Short name T475
Test name
Test status
Simulation time 178659977 ps
CPU time 0.82 seconds
Started Jul 20 06:21:15 PM PDT 24
Finished Jul 20 06:21:16 PM PDT 24
Peak memory 206640 kb
Host smart-63aff23d-f273-44ff-ada0-3cf65f6c2306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41567
1479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.415671479
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.390026438
Short name T156
Test name
Test status
Simulation time 165500673 ps
CPU time 0.83 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 206652 kb
Host smart-e79f6710-0e76-4f52-bfe5-342e41e7d12b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39002
6438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.390026438
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.485746921
Short name T2564
Test name
Test status
Simulation time 234988030 ps
CPU time 1 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206596 kb
Host smart-233af696-57ec-4a42-b4c0-77f3cd1bc568
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=485746921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.485746921
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3124264435
Short name T1120
Test name
Test status
Simulation time 140500027 ps
CPU time 0.75 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 206656 kb
Host smart-dbe41700-cde3-474a-92fb-7f0e60f5722b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31242
64435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3124264435
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.3294380627
Short name T37
Test name
Test status
Simulation time 32034258 ps
CPU time 0.67 seconds
Started Jul 20 06:21:14 PM PDT 24
Finished Jul 20 06:21:16 PM PDT 24
Peak memory 206648 kb
Host smart-26a533d8-67a5-4305-933e-77706ca61c57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32943
80627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.3294380627
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.1268146330
Short name T1304
Test name
Test status
Simulation time 19227956692 ps
CPU time 40.4 seconds
Started Jul 20 06:21:17 PM PDT 24
Finished Jul 20 06:21:59 PM PDT 24
Peak memory 215080 kb
Host smart-148f5e9b-235e-4985-a427-f5e31e2abb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12681
46330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.1268146330
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.1229255655
Short name T779
Test name
Test status
Simulation time 183942630 ps
CPU time 0.83 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:19 PM PDT 24
Peak memory 206644 kb
Host smart-5c7951e0-7790-437a-afe7-cb2ff03c02d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12292
55655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.1229255655
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.4226233213
Short name T2490
Test name
Test status
Simulation time 240863244 ps
CPU time 0.91 seconds
Started Jul 20 06:21:15 PM PDT 24
Finished Jul 20 06:21:17 PM PDT 24
Peak memory 206652 kb
Host smart-ae54f7c6-d184-473a-9217-09235de12d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42262
33213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.4226233213
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1033468275
Short name T2062
Test name
Test status
Simulation time 248413221 ps
CPU time 0.99 seconds
Started Jul 20 06:21:21 PM PDT 24
Finished Jul 20 06:21:22 PM PDT 24
Peak memory 206644 kb
Host smart-c763799c-2da7-47e3-9bb9-b9374b4bdd05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10334
68275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1033468275
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2452071034
Short name T330
Test name
Test status
Simulation time 179817459 ps
CPU time 0.83 seconds
Started Jul 20 06:21:15 PM PDT 24
Finished Jul 20 06:21:17 PM PDT 24
Peak memory 206624 kb
Host smart-c4949d3c-b51b-47ff-9489-1483a656b8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24520
71034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2452071034
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.1214934532
Short name T1491
Test name
Test status
Simulation time 147174044 ps
CPU time 0.74 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206640 kb
Host smart-bb9c9a46-1eaf-40e5-b1eb-e12dddb5812e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12149
34532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.1214934532
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.147407464
Short name T994
Test name
Test status
Simulation time 156399181 ps
CPU time 0.81 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206632 kb
Host smart-899eb586-7820-43aa-b568-254f1af76bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14740
7464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.147407464
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.3490197973
Short name T1076
Test name
Test status
Simulation time 158432091 ps
CPU time 0.81 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:20 PM PDT 24
Peak memory 206656 kb
Host smart-5c6e5585-3cbe-493c-af92-f71e6e4d9d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34901
97973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.3490197973
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.2446945705
Short name T835
Test name
Test status
Simulation time 189404306 ps
CPU time 0.84 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:17 PM PDT 24
Peak memory 206632 kb
Host smart-698b68d7-81c7-4a05-9a17-2e13c32093f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24469
45705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.2446945705
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.868437890
Short name T1757
Test name
Test status
Simulation time 3884938794 ps
CPU time 27.89 seconds
Started Jul 20 06:21:15 PM PDT 24
Finished Jul 20 06:21:44 PM PDT 24
Peak memory 206928 kb
Host smart-73b9bcd3-39ee-4e42-820a-3ad36a3cf265
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=868437890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.868437890
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.3009066786
Short name T1935
Test name
Test status
Simulation time 152728902 ps
CPU time 0.74 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:20 PM PDT 24
Peak memory 206632 kb
Host smart-4bfd9476-d20e-4b4a-8ab9-19c76ee8d24b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30090
66786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.3009066786
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.435108551
Short name T1633
Test name
Test status
Simulation time 149853578 ps
CPU time 0.8 seconds
Started Jul 20 06:21:17 PM PDT 24
Finished Jul 20 06:21:19 PM PDT 24
Peak memory 206632 kb
Host smart-f54c07b2-40b3-4025-ba92-fc352cd1c6a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43510
8551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.435108551
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.2889487029
Short name T2141
Test name
Test status
Simulation time 608744603 ps
CPU time 1.59 seconds
Started Jul 20 06:21:22 PM PDT 24
Finished Jul 20 06:21:24 PM PDT 24
Peak memory 206644 kb
Host smart-88773665-a1a9-40b5-a9e7-cf62676dc56a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28894
87029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.2889487029
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3181968967
Short name T4
Test name
Test status
Simulation time 3427224007 ps
CPU time 87.74 seconds
Started Jul 20 06:21:15 PM PDT 24
Finished Jul 20 06:22:44 PM PDT 24
Peak memory 206848 kb
Host smart-7661d13a-386d-48cf-8d16-a1153ba42dc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31819
68967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3181968967
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.1548723703
Short name T790
Test name
Test status
Simulation time 36877499 ps
CPU time 0.67 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206704 kb
Host smart-ac332c25-acd8-4a62-b582-9b46d9ddbd40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1548723703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.1548723703
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.457396151
Short name T1548
Test name
Test status
Simulation time 3535426612 ps
CPU time 4.11 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206824 kb
Host smart-885f8bd9-4eee-4817-bbcc-3d88fe25ff46
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=457396151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.457396151
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.3983316992
Short name T1031
Test name
Test status
Simulation time 13419700652 ps
CPU time 12.7 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:30 PM PDT 24
Peak memory 206780 kb
Host smart-5305c6a2-3d78-4318-af17-7eab7ecdebd7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3983316992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.3983316992
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1942522748
Short name T1664
Test name
Test status
Simulation time 23411949234 ps
CPU time 26.1 seconds
Started Jul 20 06:21:17 PM PDT 24
Finished Jul 20 06:21:44 PM PDT 24
Peak memory 206788 kb
Host smart-86327edc-0473-4ff4-8af8-84650ae144f3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1942522748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1942522748
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.4218010041
Short name T976
Test name
Test status
Simulation time 214442510 ps
CPU time 0.84 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 206644 kb
Host smart-8edf5866-f58c-4edc-9882-0029dd2a5511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42180
10041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.4218010041
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.2501768055
Short name T661
Test name
Test status
Simulation time 162732986 ps
CPU time 0.81 seconds
Started Jul 20 06:21:14 PM PDT 24
Finished Jul 20 06:21:15 PM PDT 24
Peak memory 206660 kb
Host smart-0f6ad2df-a3a8-4416-990b-27a6d3ad74ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25017
68055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.2501768055
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3514327814
Short name T649
Test name
Test status
Simulation time 210109534 ps
CPU time 0.87 seconds
Started Jul 20 06:21:19 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206636 kb
Host smart-6261e81e-e0a0-4495-8ea0-c5e0502c6e0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35143
27814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3514327814
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.2969343971
Short name T847
Test name
Test status
Simulation time 1011613840 ps
CPU time 2.3 seconds
Started Jul 20 06:21:17 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206804 kb
Host smart-82b5dc37-8621-4dcd-810a-82ac4627c73f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29693
43971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.2969343971
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.903552244
Short name T483
Test name
Test status
Simulation time 16760410821 ps
CPU time 31.46 seconds
Started Jul 20 06:21:13 PM PDT 24
Finished Jul 20 06:21:45 PM PDT 24
Peak memory 206852 kb
Host smart-861de61d-991b-45c6-a4f7-852d2e4e4a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90355
2244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.903552244
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.4183166531
Short name T1748
Test name
Test status
Simulation time 406621883 ps
CPU time 1.25 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:19 PM PDT 24
Peak memory 206700 kb
Host smart-51267f65-d36d-4768-a2e9-aae3081b8724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41831
66531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.4183166531
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.1580876844
Short name T2708
Test name
Test status
Simulation time 151919838 ps
CPU time 0.77 seconds
Started Jul 20 06:21:15 PM PDT 24
Finished Jul 20 06:21:17 PM PDT 24
Peak memory 206656 kb
Host smart-eab67787-675b-46dd-a7ed-f1eece42184b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
76844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.1580876844
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.1708090666
Short name T1050
Test name
Test status
Simulation time 39368167 ps
CPU time 0.66 seconds
Started Jul 20 06:21:17 PM PDT 24
Finished Jul 20 06:21:19 PM PDT 24
Peak memory 206648 kb
Host smart-be23d645-1a46-4711-872b-caf3380e2489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17080
90666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.1708090666
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1462619279
Short name T1785
Test name
Test status
Simulation time 830044749 ps
CPU time 2.12 seconds
Started Jul 20 06:21:17 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206780 kb
Host smart-4390a8ca-717c-4071-9a31-ea6cd209e8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14626
19279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1462619279
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.1170546360
Short name T2466
Test name
Test status
Simulation time 352649369 ps
CPU time 1.97 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:19 PM PDT 24
Peak memory 206748 kb
Host smart-575add1f-58e6-4459-8c1d-2583f00e8c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11705
46360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.1170546360
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.3924932200
Short name T1773
Test name
Test status
Simulation time 230614055 ps
CPU time 0.92 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:20 PM PDT 24
Peak memory 206644 kb
Host smart-51f4794c-9cbd-4f6f-803d-4c5a8260debe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39249
32200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.3924932200
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.4029878127
Short name T369
Test name
Test status
Simulation time 195612484 ps
CPU time 0.79 seconds
Started Jul 20 06:21:17 PM PDT 24
Finished Jul 20 06:21:20 PM PDT 24
Peak memory 206656 kb
Host smart-4965c4da-9b2b-4e22-9b38-cf8fa70fc64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40298
78127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.4029878127
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3460513932
Short name T2525
Test name
Test status
Simulation time 261229106 ps
CPU time 0.95 seconds
Started Jul 20 06:21:16 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 206652 kb
Host smart-d2de02cd-9bab-4922-be19-1ab33d597811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34605
13932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3460513932
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.3210545401
Short name T2709
Test name
Test status
Simulation time 6746928220 ps
CPU time 62.28 seconds
Started Jul 20 06:21:19 PM PDT 24
Finished Jul 20 06:22:22 PM PDT 24
Peak memory 206892 kb
Host smart-60e8ddc3-c4fc-47db-a710-8c7402d49b43
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3210545401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.3210545401
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.1751524377
Short name T1846
Test name
Test status
Simulation time 10362304318 ps
CPU time 36.27 seconds
Started Jul 20 06:21:18 PM PDT 24
Finished Jul 20 06:21:56 PM PDT 24
Peak memory 206868 kb
Host smart-93842693-34a7-4698-9546-eecd1e788dbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17515
24377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1751524377
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.2112595929
Short name T2640
Test name
Test status
Simulation time 209092290 ps
CPU time 0.81 seconds
Started Jul 20 06:21:23 PM PDT 24
Finished Jul 20 06:21:25 PM PDT 24
Peak memory 206660 kb
Host smart-2866acc0-2036-40d8-b6cf-026036db112e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21125
95929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.2112595929
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.1603156471
Short name T1267
Test name
Test status
Simulation time 23354125570 ps
CPU time 24.09 seconds
Started Jul 20 06:21:27 PM PDT 24
Finished Jul 20 06:21:52 PM PDT 24
Peak memory 206748 kb
Host smart-0e08cfdb-cbc5-4268-b747-c50355fb4042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
56471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.1603156471
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.2087577830
Short name T1496
Test name
Test status
Simulation time 3349838382 ps
CPU time 4.21 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:31 PM PDT 24
Peak memory 206660 kb
Host smart-26390325-8099-4b9c-a915-c12fed18393f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20875
77830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.2087577830
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.1134001085
Short name T683
Test name
Test status
Simulation time 9209460998 ps
CPU time 261.23 seconds
Started Jul 20 06:21:25 PM PDT 24
Finished Jul 20 06:25:47 PM PDT 24
Peak memory 206968 kb
Host smart-b96ea359-e1b5-42a3-bbf6-7c6fb63e9770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11340
01085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1134001085
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.3962366534
Short name T2623
Test name
Test status
Simulation time 3932242145 ps
CPU time 111.08 seconds
Started Jul 20 06:21:24 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206844 kb
Host smart-c4fffd50-f622-4f29-893c-707338440d08
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3962366534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.3962366534
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.3245252452
Short name T22
Test name
Test status
Simulation time 235147809 ps
CPU time 0.94 seconds
Started Jul 20 06:21:30 PM PDT 24
Finished Jul 20 06:21:32 PM PDT 24
Peak memory 206656 kb
Host smart-a842cac3-143a-4350-8564-55b3371be759
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3245252452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.3245252452
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.2882372678
Short name T2268
Test name
Test status
Simulation time 187459167 ps
CPU time 0.84 seconds
Started Jul 20 06:21:27 PM PDT 24
Finished Jul 20 06:21:29 PM PDT 24
Peak memory 206648 kb
Host smart-f99ef2fb-33a1-4606-9301-578c966f7b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
72678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.2882372678
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.266624866
Short name T717
Test name
Test status
Simulation time 6113293759 ps
CPU time 57.19 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:22:24 PM PDT 24
Peak memory 206920 kb
Host smart-8b405726-5117-4b81-a41b-cfc0c00c5720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26662
4866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.266624866
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.574943796
Short name T1763
Test name
Test status
Simulation time 5854361654 ps
CPU time 54.32 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:22:29 PM PDT 24
Peak memory 206412 kb
Host smart-6ace6022-60ff-4f68-baa9-7bf010665395
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=574943796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.574943796
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.785421118
Short name T1777
Test name
Test status
Simulation time 158676421 ps
CPU time 0.81 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:27 PM PDT 24
Peak memory 206660 kb
Host smart-42246039-50dd-4f81-a02c-6932f45a795d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=785421118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.785421118
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.3759178035
Short name T2557
Test name
Test status
Simulation time 141063215 ps
CPU time 0.77 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206644 kb
Host smart-794b3ec1-7066-4258-921e-3ed58628c100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37591
78035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.3759178035
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.3199361895
Short name T126
Test name
Test status
Simulation time 215650252 ps
CPU time 0.85 seconds
Started Jul 20 06:21:28 PM PDT 24
Finished Jul 20 06:21:30 PM PDT 24
Peak memory 206652 kb
Host smart-55a7a657-93f9-4ddb-b364-56bb3a8dea32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31993
61895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.3199361895
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.3843032957
Short name T1206
Test name
Test status
Simulation time 170382441 ps
CPU time 0.83 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206656 kb
Host smart-d08e3008-4458-4dfd-b3c5-2405ca77957f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38430
32957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.3843032957
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.1339452566
Short name T1743
Test name
Test status
Simulation time 177976576 ps
CPU time 0.77 seconds
Started Jul 20 06:21:29 PM PDT 24
Finished Jul 20 06:21:30 PM PDT 24
Peak memory 206652 kb
Host smart-f99c9cc6-f834-41f1-8c41-5d555250ab0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13394
52566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.1339452566
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3979957950
Short name T2644
Test name
Test status
Simulation time 201807162 ps
CPU time 0.87 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:27 PM PDT 24
Peak memory 206652 kb
Host smart-1d9a6743-793b-4330-a0c9-cd62daf3505b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39799
57950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3979957950
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.1849492292
Short name T1349
Test name
Test status
Simulation time 155743948 ps
CPU time 0.82 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206640 kb
Host smart-8045fe25-c394-4d78-ac9d-392901f2afc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18494
92292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.1849492292
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.2237263873
Short name T787
Test name
Test status
Simulation time 247385397 ps
CPU time 0.96 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206636 kb
Host smart-4c584b3a-df76-4a93-9f4b-73745cf339ce
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2237263873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.2237263873
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3810298221
Short name T1676
Test name
Test status
Simulation time 153007380 ps
CPU time 0.76 seconds
Started Jul 20 06:21:24 PM PDT 24
Finished Jul 20 06:21:25 PM PDT 24
Peak memory 206648 kb
Host smart-de302b27-bd67-41d0-9f1c-ff8db5272a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38102
98221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3810298221
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1466172563
Short name T2068
Test name
Test status
Simulation time 39411666 ps
CPU time 0.66 seconds
Started Jul 20 06:21:28 PM PDT 24
Finished Jul 20 06:21:29 PM PDT 24
Peak memory 206644 kb
Host smart-087e02e7-ca29-4df9-abf7-ed9429ce43f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14661
72563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1466172563
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2460823498
Short name T957
Test name
Test status
Simulation time 9706761352 ps
CPU time 21.32 seconds
Started Jul 20 06:21:27 PM PDT 24
Finished Jul 20 06:21:49 PM PDT 24
Peak memory 206896 kb
Host smart-8a9fb049-d49d-451b-b702-1fbe41c5d626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24608
23498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2460823498
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.370298969
Short name T657
Test name
Test status
Simulation time 175065144 ps
CPU time 0.85 seconds
Started Jul 20 06:21:30 PM PDT 24
Finished Jul 20 06:21:32 PM PDT 24
Peak memory 206664 kb
Host smart-b2ce43d8-4c62-438b-a3ad-8f456cc6488d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.370298969
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.960558294
Short name T2384
Test name
Test status
Simulation time 206181211 ps
CPU time 0.89 seconds
Started Jul 20 06:21:24 PM PDT 24
Finished Jul 20 06:21:25 PM PDT 24
Peak memory 206652 kb
Host smart-a82255a4-0ec5-4e45-b2c7-dd632b50f803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96055
8294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.960558294
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.3306764706
Short name T2621
Test name
Test status
Simulation time 227983261 ps
CPU time 0.93 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206656 kb
Host smart-11567e81-dc7e-4eea-b0e7-225c0b2edcfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33067
64706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.3306764706
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.2230763046
Short name T2594
Test name
Test status
Simulation time 150483602 ps
CPU time 0.77 seconds
Started Jul 20 06:21:23 PM PDT 24
Finished Jul 20 06:21:25 PM PDT 24
Peak memory 206624 kb
Host smart-e4afc0a5-0185-47d6-a731-df9a0008da7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22307
63046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.2230763046
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.50223655
Short name T953
Test name
Test status
Simulation time 155232042 ps
CPU time 0.79 seconds
Started Jul 20 06:21:29 PM PDT 24
Finished Jul 20 06:21:30 PM PDT 24
Peak memory 206652 kb
Host smart-bfba3fc5-8f03-4d3d-b70d-df843373b153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50223
655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.50223655
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.3049217573
Short name T888
Test name
Test status
Simulation time 179091520 ps
CPU time 0.82 seconds
Started Jul 20 06:21:24 PM PDT 24
Finished Jul 20 06:21:25 PM PDT 24
Peak memory 206648 kb
Host smart-283cd8e2-f1bb-4e87-98fe-14c69e3cea00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30492
17573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.3049217573
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.2790338875
Short name T784
Test name
Test status
Simulation time 170246022 ps
CPU time 0.76 seconds
Started Jul 20 06:21:27 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206648 kb
Host smart-7a3a40d7-a146-475f-96dd-b7674145a010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27903
38875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.2790338875
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1324713351
Short name T1644
Test name
Test status
Simulation time 251694183 ps
CPU time 1 seconds
Started Jul 20 06:21:26 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206656 kb
Host smart-13bb19fb-b695-44d7-af94-3307e2f18fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13247
13351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1324713351
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.2432352784
Short name T1482
Test name
Test status
Simulation time 6571064990 ps
CPU time 47.52 seconds
Started Jul 20 06:21:30 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206904 kb
Host smart-7f986485-0690-4583-acf6-cd15d0bd345a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2432352784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.2432352784
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.2328078306
Short name T146
Test name
Test status
Simulation time 158730600 ps
CPU time 0.82 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206204 kb
Host smart-210ef79b-13fe-4a83-9d2a-04a310dc3681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23280
78306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.2328078306
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.2671541458
Short name T2344
Test name
Test status
Simulation time 202207150 ps
CPU time 0.89 seconds
Started Jul 20 06:21:29 PM PDT 24
Finished Jul 20 06:21:31 PM PDT 24
Peak memory 206656 kb
Host smart-6adf64ce-7d7e-4266-9b94-24a79f7a2ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26715
41458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.2671541458
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.738841363
Short name T2316
Test name
Test status
Simulation time 1141355970 ps
CPU time 2.47 seconds
Started Jul 20 06:21:25 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206748 kb
Host smart-a9c32dbb-6f0c-4a1d-8dd1-1eed7e7f5fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73884
1363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.738841363
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.2693510989
Short name T412
Test name
Test status
Simulation time 2989878316 ps
CPU time 22.54 seconds
Started Jul 20 06:21:29 PM PDT 24
Finished Jul 20 06:21:52 PM PDT 24
Peak memory 206928 kb
Host smart-72e77950-2dd4-4e09-99a7-5a74cd6065ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26935
10989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.2693510989
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.1264054012
Short name T410
Test name
Test status
Simulation time 52482318 ps
CPU time 0.71 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 206696 kb
Host smart-0b68f2a5-71aa-466a-a8e4-19206ce74bdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1264054012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.1264054012
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.1546048649
Short name T2343
Test name
Test status
Simulation time 3409801867 ps
CPU time 4.08 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:21:40 PM PDT 24
Peak memory 206720 kb
Host smart-21cc8634-53ff-4f1e-a668-7fa29c3dc762
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1546048649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.1546048649
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.2230115077
Short name T897
Test name
Test status
Simulation time 13405287252 ps
CPU time 13.66 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:50 PM PDT 24
Peak memory 206776 kb
Host smart-c8b6ece8-0d0e-47d2-adb0-07ebe1fe19df
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2230115077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.2230115077
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2216324378
Short name T2550
Test name
Test status
Simulation time 23418106369 ps
CPU time 25.64 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:22:02 PM PDT 24
Peak memory 206868 kb
Host smart-528c30a2-fb54-42db-9611-81b528f92eaa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2216324378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2216324378
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2484341043
Short name T2261
Test name
Test status
Simulation time 169042564 ps
CPU time 0.78 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:21:36 PM PDT 24
Peak memory 206652 kb
Host smart-5596c382-86d9-4f19-9cab-427f8354a4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24843
41043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2484341043
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1779833750
Short name T2711
Test name
Test status
Simulation time 166282601 ps
CPU time 0.8 seconds
Started Jul 20 06:21:39 PM PDT 24
Finished Jul 20 06:21:41 PM PDT 24
Peak memory 206628 kb
Host smart-714bb2d8-d3f9-4324-bdb9-958fd70897db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17798
33750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1779833750
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.3145276959
Short name T1176
Test name
Test status
Simulation time 339134588 ps
CPU time 1.26 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206624 kb
Host smart-a89f941b-c895-458f-9725-e452bbbf1ad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31452
76959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.3145276959
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1449163461
Short name T909
Test name
Test status
Simulation time 980264116 ps
CPU time 2.31 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:39 PM PDT 24
Peak memory 206776 kb
Host smart-49c7bd07-dd14-48da-80c8-16022e760644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14491
63461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1449163461
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3462655399
Short name T1811
Test name
Test status
Simulation time 14131357052 ps
CPU time 27 seconds
Started Jul 20 06:21:37 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 206896 kb
Host smart-69a6480c-6e28-4bcb-94f6-bbcbaf3d31b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34626
55399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3462655399
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.780728365
Short name T1786
Test name
Test status
Simulation time 530379683 ps
CPU time 1.48 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206656 kb
Host smart-c4dad93e-0574-4308-99a6-bcb53f01c3ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78072
8365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.780728365
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3525613360
Short name T1856
Test name
Test status
Simulation time 161139735 ps
CPU time 0.8 seconds
Started Jul 20 06:21:36 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206620 kb
Host smart-7766d8aa-d213-435c-99bb-3afcb46dd403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35256
13360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3525613360
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.3602337503
Short name T564
Test name
Test status
Simulation time 31369005 ps
CPU time 0.69 seconds
Started Jul 20 06:21:37 PM PDT 24
Finished Jul 20 06:21:40 PM PDT 24
Peak memory 206560 kb
Host smart-10726c5a-bac1-4cc1-aead-a534fa027318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36023
37503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.3602337503
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.3704609370
Short name T477
Test name
Test status
Simulation time 873433024 ps
CPU time 2.23 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:37 PM PDT 24
Peak memory 206740 kb
Host smart-d0b313b1-f748-4701-b1cd-b606396c14a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37046
09370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.3704609370
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.2192348224
Short name T1800
Test name
Test status
Simulation time 281991346 ps
CPU time 2.21 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:36 PM PDT 24
Peak memory 206740 kb
Host smart-a52b8b8f-6417-4206-b238-9bb910c6fc38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
48224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.2192348224
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3557092596
Short name T2717
Test name
Test status
Simulation time 240098999 ps
CPU time 0.92 seconds
Started Jul 20 06:21:32 PM PDT 24
Finished Jul 20 06:21:33 PM PDT 24
Peak memory 206648 kb
Host smart-8a0e11e5-d9f7-4ac7-9efe-184a2f771947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35570
92596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3557092596
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.4000267741
Short name T2227
Test name
Test status
Simulation time 150816086 ps
CPU time 0.78 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:21:37 PM PDT 24
Peak memory 206620 kb
Host smart-7ad273f5-6083-4eeb-9073-2142e5ae7493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
67741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.4000267741
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.1158935285
Short name T149
Test name
Test status
Simulation time 172539352 ps
CPU time 0.89 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206700 kb
Host smart-fcd0c3bf-3f5c-49b0-9ef0-40c9529d12ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11589
35285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.1158935285
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.2518099408
Short name T2048
Test name
Test status
Simulation time 6362045728 ps
CPU time 24.15 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:22:00 PM PDT 24
Peak memory 206912 kb
Host smart-f47c3f72-9f45-4930-adae-c13cd9e4155b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25180
99408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.2518099408
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3270880936
Short name T1720
Test name
Test status
Simulation time 187539796 ps
CPU time 0.87 seconds
Started Jul 20 06:21:38 PM PDT 24
Finished Jul 20 06:21:40 PM PDT 24
Peak memory 206660 kb
Host smart-c04e99b6-c68a-4fcc-8e63-9fc05a9db576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32708
80936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3270880936
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2750370766
Short name T2111
Test name
Test status
Simulation time 23318805410 ps
CPU time 21.75 seconds
Started Jul 20 06:21:40 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206748 kb
Host smart-be35cd2f-4dd5-427e-993b-1e0f6d90633a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27503
70766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2750370766
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.306821409
Short name T1203
Test name
Test status
Simulation time 3276154736 ps
CPU time 4.31 seconds
Started Jul 20 06:21:37 PM PDT 24
Finished Jul 20 06:21:42 PM PDT 24
Peak memory 206720 kb
Host smart-75294f21-5b66-4b9e-8539-c93a124b1699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30682
1409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.306821409
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3554432656
Short name T1487
Test name
Test status
Simulation time 8256884778 ps
CPU time 57.86 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:22:32 PM PDT 24
Peak memory 206920 kb
Host smart-f41a80d9-a2cd-414c-a0b7-6b5a41c57fd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35544
32656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3554432656
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.3509083416
Short name T2211
Test name
Test status
Simulation time 6209842291 ps
CPU time 55.04 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:22:31 PM PDT 24
Peak memory 206900 kb
Host smart-e7d9439d-cc70-48bb-89ad-cd21bd5e560c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3509083416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.3509083416
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.3845482908
Short name T1174
Test name
Test status
Simulation time 240535990 ps
CPU time 0.9 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206784 kb
Host smart-cdfa8650-7a16-419d-8229-743c70481733
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3845482908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.3845482908
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.2343038163
Short name T775
Test name
Test status
Simulation time 186953302 ps
CPU time 0.94 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:21:37 PM PDT 24
Peak memory 206652 kb
Host smart-b6846415-c853-4d2f-85d0-f955dec19367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23430
38163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.2343038163
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.809328590
Short name T700
Test name
Test status
Simulation time 5666284499 ps
CPU time 164.81 seconds
Started Jul 20 06:21:31 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206844 kb
Host smart-fab19a4b-cada-4b4e-9940-28e34dc2afbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80932
8590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.809328590
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.150192949
Short name T681
Test name
Test status
Simulation time 4532796537 ps
CPU time 126.28 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:23:42 PM PDT 24
Peak memory 206840 kb
Host smart-9916b975-73d4-4606-99b4-8d19de4d02e8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=150192949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.150192949
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3112131928
Short name T1188
Test name
Test status
Simulation time 209890247 ps
CPU time 0.88 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:21:37 PM PDT 24
Peak memory 206652 kb
Host smart-83947e2a-461b-428b-aea9-b81e8af8677c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3112131928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3112131928
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.1696598669
Short name T1075
Test name
Test status
Simulation time 155114347 ps
CPU time 0.81 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:34 PM PDT 24
Peak memory 206744 kb
Host smart-fe921724-871d-46be-bae7-9beed72a98ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16965
98669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.1696598669
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.1724246677
Short name T523
Test name
Test status
Simulation time 147234848 ps
CPU time 0.78 seconds
Started Jul 20 06:21:37 PM PDT 24
Finished Jul 20 06:21:39 PM PDT 24
Peak memory 206648 kb
Host smart-8cef4a76-1058-4378-bcd4-a31d39dd37f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17242
46677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.1724246677
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.2232355492
Short name T361
Test name
Test status
Simulation time 235209074 ps
CPU time 0.89 seconds
Started Jul 20 06:21:37 PM PDT 24
Finished Jul 20 06:21:40 PM PDT 24
Peak memory 206528 kb
Host smart-d96b2328-17b7-4830-bdde-750daa0256b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22323
55492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.2232355492
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.4169805285
Short name T1683
Test name
Test status
Simulation time 162549525 ps
CPU time 0.8 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206656 kb
Host smart-ab76a9a3-56e2-4cad-87af-ee805a903f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41698
05285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.4169805285
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.2862150553
Short name T841
Test name
Test status
Simulation time 187290828 ps
CPU time 0.82 seconds
Started Jul 20 06:21:36 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206660 kb
Host smart-bd41692b-51e7-4d35-8b45-efa44a4582fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28621
50553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.2862150553
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.385665057
Short name T2686
Test name
Test status
Simulation time 213943446 ps
CPU time 0.88 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206652 kb
Host smart-877095b3-556f-4c80-b8e7-79e3b16a39cd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=385665057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.385665057
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2498925677
Short name T1094
Test name
Test status
Simulation time 141933857 ps
CPU time 0.77 seconds
Started Jul 20 06:21:36 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206668 kb
Host smart-41fb80bc-d0f7-413b-825e-68d06db93681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24989
25677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2498925677
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.81752701
Short name T816
Test name
Test status
Simulation time 32690376 ps
CPU time 0.62 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:34 PM PDT 24
Peak memory 206776 kb
Host smart-d046b036-624e-46cc-9b3f-712f07a5cb89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81752
701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.81752701
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.1559066871
Short name T245
Test name
Test status
Simulation time 17876625335 ps
CPU time 39.79 seconds
Started Jul 20 06:21:37 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206888 kb
Host smart-0139b941-a7aa-4c30-b1e6-9360b8696db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15590
66871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.1559066871
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1043972369
Short name T805
Test name
Test status
Simulation time 166417149 ps
CPU time 0.81 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:36 PM PDT 24
Peak memory 206660 kb
Host smart-e100039f-ec9a-4eba-b35f-0bc027e9ac93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10439
72369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1043972369
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.2314049807
Short name T1025
Test name
Test status
Simulation time 168286980 ps
CPU time 0.8 seconds
Started Jul 20 06:21:33 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206648 kb
Host smart-6c776824-b81c-4eb5-acb9-0f6528d172e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23140
49807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.2314049807
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.3629366141
Short name T2067
Test name
Test status
Simulation time 216640599 ps
CPU time 0.88 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206664 kb
Host smart-bf41d71f-6bec-4ae9-a349-f14026847c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36293
66141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.3629366141
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.841668024
Short name T325
Test name
Test status
Simulation time 208994351 ps
CPU time 0.93 seconds
Started Jul 20 06:21:34 PM PDT 24
Finished Jul 20 06:21:37 PM PDT 24
Peak memory 206644 kb
Host smart-ba06a747-71d0-4046-9545-6b703af184d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84166
8024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.841668024
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.1144275555
Short name T1121
Test name
Test status
Simulation time 149332313 ps
CPU time 0.79 seconds
Started Jul 20 06:21:36 PM PDT 24
Finished Jul 20 06:21:39 PM PDT 24
Peak memory 206600 kb
Host smart-18eb531b-a9ab-427e-a7dc-6796a035c7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11442
75555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.1144275555
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2961091759
Short name T1534
Test name
Test status
Simulation time 152907101 ps
CPU time 0.79 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206640 kb
Host smart-bf8860f5-a3a5-4373-8945-2e396a9c35fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29610
91759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2961091759
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.3678606697
Short name T1565
Test name
Test status
Simulation time 160277888 ps
CPU time 0.8 seconds
Started Jul 20 06:21:30 PM PDT 24
Finished Jul 20 06:21:32 PM PDT 24
Peak memory 206636 kb
Host smart-fe82ddc1-4605-45f2-9f2a-36c055455f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36786
06697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.3678606697
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2268654964
Short name T743
Test name
Test status
Simulation time 196647598 ps
CPU time 0.96 seconds
Started Jul 20 06:21:36 PM PDT 24
Finished Jul 20 06:21:39 PM PDT 24
Peak memory 206584 kb
Host smart-3e843bc2-7889-464b-8e9e-0af8c5efbcb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22686
54964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2268654964
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.4096117701
Short name T612
Test name
Test status
Simulation time 172660000 ps
CPU time 0.86 seconds
Started Jul 20 06:21:35 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206652 kb
Host smart-33314b4d-0ca7-495e-a002-fdad36df8fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40961
17701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.4096117701
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.2996513604
Short name T750
Test name
Test status
Simulation time 167299933 ps
CPU time 0.8 seconds
Started Jul 20 06:21:40 PM PDT 24
Finished Jul 20 06:21:41 PM PDT 24
Peak memory 206624 kb
Host smart-67f54175-94ec-4935-8352-bfaac8232ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29965
13604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.2996513604
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.352195402
Short name T1450
Test name
Test status
Simulation time 212455003 ps
CPU time 1 seconds
Started Jul 20 06:21:46 PM PDT 24
Finished Jul 20 06:21:48 PM PDT 24
Peak memory 206656 kb
Host smart-a542ffaf-8e32-426a-b91a-b01443cd9eff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
5402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.352195402
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.2124689929
Short name T603
Test name
Test status
Simulation time 5737710945 ps
CPU time 41.68 seconds
Started Jul 20 06:21:48 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206976 kb
Host smart-fbb3bc89-6f2e-4b4c-af7e-956649639324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21246
89929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.2124689929
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.1413887153
Short name T950
Test name
Test status
Simulation time 34159813 ps
CPU time 0.68 seconds
Started Jul 20 06:21:49 PM PDT 24
Finished Jul 20 06:21:50 PM PDT 24
Peak memory 206716 kb
Host smart-87b3bcec-c53c-49c9-a922-637e847994bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1413887153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.1413887153
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2318553155
Short name T216
Test name
Test status
Simulation time 3635871091 ps
CPU time 4.28 seconds
Started Jul 20 06:21:40 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 206876 kb
Host smart-17ae0ecb-48d8-4ce2-91d7-ade2f4e46051
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2318553155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2318553155
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2106084444
Short name T50
Test name
Test status
Simulation time 13348594223 ps
CPU time 12.72 seconds
Started Jul 20 06:21:50 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206748 kb
Host smart-6651f4f5-2cee-4f37-89c7-67666bd53b38
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2106084444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2106084444
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3223463740
Short name T812
Test name
Test status
Simulation time 23504693178 ps
CPU time 24.57 seconds
Started Jul 20 06:21:45 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 206868 kb
Host smart-65828290-7590-480f-a5ff-1c0cf9100bee
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3223463740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3223463740
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.1552470685
Short name T1901
Test name
Test status
Simulation time 216184285 ps
CPU time 0.83 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206624 kb
Host smart-816f2190-b3f1-4a26-9a84-008b03575a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
70685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.1552470685
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1228636263
Short name T2317
Test name
Test status
Simulation time 223128326 ps
CPU time 0.84 seconds
Started Jul 20 06:21:45 PM PDT 24
Finished Jul 20 06:21:47 PM PDT 24
Peak memory 206624 kb
Host smart-f4e6a14a-ae31-44e2-8d9d-e263735a4a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12286
36263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1228636263
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2835320582
Short name T1385
Test name
Test status
Simulation time 491872217 ps
CPU time 1.44 seconds
Started Jul 20 06:21:41 PM PDT 24
Finished Jul 20 06:21:43 PM PDT 24
Peak memory 206692 kb
Host smart-a7b72610-ac29-4175-bdbc-69cec7a0aa57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28353
20582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2835320582
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.54413976
Short name T2707
Test name
Test status
Simulation time 1459838716 ps
CPU time 3.29 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:21:49 PM PDT 24
Peak memory 206760 kb
Host smart-e71ef760-27e7-41b9-abd0-95c4f825bc3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54413
976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.54413976
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.4181915165
Short name T165
Test name
Test status
Simulation time 10843131557 ps
CPU time 20.04 seconds
Started Jul 20 06:21:41 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206928 kb
Host smart-9223093a-60c9-4b97-9a4b-d7e08c65da3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41819
15165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.4181915165
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.1322273298
Short name T1052
Test name
Test status
Simulation time 348768419 ps
CPU time 1.15 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206620 kb
Host smart-562e94a3-609a-4f39-aa72-91ee2a28f3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13222
73298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.1322273298
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.3517175293
Short name T726
Test name
Test status
Simulation time 179145843 ps
CPU time 0.88 seconds
Started Jul 20 06:21:43 PM PDT 24
Finished Jul 20 06:21:45 PM PDT 24
Peak memory 206664 kb
Host smart-0f3e2d3b-b547-47b6-a5c9-0d3e176d5651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35171
75293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.3517175293
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.63589951
Short name T733
Test name
Test status
Simulation time 75412382 ps
CPU time 0.68 seconds
Started Jul 20 06:21:42 PM PDT 24
Finished Jul 20 06:21:44 PM PDT 24
Peak memory 206644 kb
Host smart-540e1c6a-f724-401d-8d2d-686483537123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63589
951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.63589951
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2577142323
Short name T1149
Test name
Test status
Simulation time 933749183 ps
CPU time 2.54 seconds
Started Jul 20 06:21:42 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 206788 kb
Host smart-276d4bec-aed8-405d-a4b3-eba6fb159a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25771
42323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2577142323
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3931909872
Short name T1181
Test name
Test status
Simulation time 206247679 ps
CPU time 2.28 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:21:47 PM PDT 24
Peak memory 206736 kb
Host smart-7819b871-39ed-4dc3-b2c3-3212520ac578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39319
09872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3931909872
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.1154729862
Short name T2724
Test name
Test status
Simulation time 203298321 ps
CPU time 0.88 seconds
Started Jul 20 06:21:45 PM PDT 24
Finished Jul 20 06:21:47 PM PDT 24
Peak memory 206648 kb
Host smart-aaba7379-e672-4412-ba5d-c192b5f980e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11547
29862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.1154729862
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.3742261637
Short name T837
Test name
Test status
Simulation time 200182785 ps
CPU time 0.86 seconds
Started Jul 20 06:21:43 PM PDT 24
Finished Jul 20 06:21:45 PM PDT 24
Peak memory 206652 kb
Host smart-d774860b-a539-40a8-9de1-d96dc40763cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37422
61637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.3742261637
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.3840952006
Short name T1236
Test name
Test status
Simulation time 235811747 ps
CPU time 0.92 seconds
Started Jul 20 06:21:43 PM PDT 24
Finished Jul 20 06:21:45 PM PDT 24
Peak memory 206652 kb
Host smart-d072549d-c08e-454e-b484-9f6d32bc1093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38409
52006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.3840952006
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.2278448818
Short name T1423
Test name
Test status
Simulation time 4013001191 ps
CPU time 13.43 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:21:59 PM PDT 24
Peak memory 206844 kb
Host smart-5edc49cb-adfc-4fe1-82a5-826ca6551ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22784
48818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.2278448818
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.340923408
Short name T2259
Test name
Test status
Simulation time 257658363 ps
CPU time 0.95 seconds
Started Jul 20 06:21:41 PM PDT 24
Finished Jul 20 06:21:44 PM PDT 24
Peak memory 206640 kb
Host smart-7e266987-5eb4-459b-805b-f0821bb2b7e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34092
3408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.340923408
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.2734994943
Short name T1211
Test name
Test status
Simulation time 23337762144 ps
CPU time 26.83 seconds
Started Jul 20 06:21:43 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 206772 kb
Host smart-c520e4f6-0e3c-4309-b8e4-1754e46a53a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27349
94943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.2734994943
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.2112937122
Short name T2600
Test name
Test status
Simulation time 3378804211 ps
CPU time 3.98 seconds
Started Jul 20 06:21:45 PM PDT 24
Finished Jul 20 06:21:51 PM PDT 24
Peak memory 206716 kb
Host smart-7e7c2787-900e-4bc8-a62a-643daf44608d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21129
37122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.2112937122
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.54394480
Short name T1827
Test name
Test status
Simulation time 10794822057 ps
CPU time 75.62 seconds
Started Jul 20 06:21:41 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 207016 kb
Host smart-0f130a73-e68f-44d6-b7a7-964becfa8e76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54394
480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.54394480
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.2106859629
Short name T1978
Test name
Test status
Simulation time 5031270299 ps
CPU time 50.18 seconds
Started Jul 20 06:21:45 PM PDT 24
Finished Jul 20 06:22:36 PM PDT 24
Peak memory 206828 kb
Host smart-c816a655-7255-4764-882b-bb413a317a85
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2106859629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.2106859629
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2835663484
Short name T1958
Test name
Test status
Simulation time 239786274 ps
CPU time 0.89 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 206652 kb
Host smart-6486296d-ab72-4048-88fe-2a5153c3331c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2835663484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2835663484
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3159462510
Short name T1933
Test name
Test status
Simulation time 191115787 ps
CPU time 0.92 seconds
Started Jul 20 06:21:46 PM PDT 24
Finished Jul 20 06:21:48 PM PDT 24
Peak memory 206648 kb
Host smart-ed5fccb7-76e0-435c-9fbf-f5e008ce4316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31594
62510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3159462510
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.952364529
Short name T2173
Test name
Test status
Simulation time 5835487079 ps
CPU time 41.24 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:22:27 PM PDT 24
Peak memory 206916 kb
Host smart-2183ffa8-d468-42db-a583-082ba2b13f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95236
4529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.952364529
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.359328632
Short name T2304
Test name
Test status
Simulation time 5880024263 ps
CPU time 55.45 seconds
Started Jul 20 06:21:41 PM PDT 24
Finished Jul 20 06:22:38 PM PDT 24
Peak memory 206868 kb
Host smart-9ce0c18d-147e-4dee-a6a5-3f4f67b7f64e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=359328632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.359328632
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.3359300647
Short name T2742
Test name
Test status
Simulation time 190128149 ps
CPU time 0.82 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 206652 kb
Host smart-78701eea-1a7c-4a79-abe8-d85c6779f27b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3359300647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.3359300647
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.2239095863
Short name T2279
Test name
Test status
Simulation time 143361432 ps
CPU time 0.75 seconds
Started Jul 20 06:21:41 PM PDT 24
Finished Jul 20 06:21:43 PM PDT 24
Peak memory 206692 kb
Host smart-297ac405-e569-4ef2-9e61-1308390f6aaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22390
95863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.2239095863
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.4240286923
Short name T2410
Test name
Test status
Simulation time 145750144 ps
CPU time 0.84 seconds
Started Jul 20 06:21:44 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 206652 kb
Host smart-e1f014bf-cb49-4896-bba6-ad12b4f556b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42402
86923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.4240286923
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.981580688
Short name T2269
Test name
Test status
Simulation time 180120241 ps
CPU time 0.82 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206620 kb
Host smart-f7adce69-408e-45f6-af5c-18a500930705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98158
0688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.981580688
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.37515090
Short name T351
Test name
Test status
Simulation time 190646762 ps
CPU time 0.82 seconds
Started Jul 20 06:21:42 PM PDT 24
Finished Jul 20 06:21:44 PM PDT 24
Peak memory 206656 kb
Host smart-e1726f21-920c-4150-9884-68bec60ebc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37515
090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.37515090
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.4226510338
Short name T1281
Test name
Test status
Simulation time 149468359 ps
CPU time 0.77 seconds
Started Jul 20 06:21:43 PM PDT 24
Finished Jul 20 06:21:46 PM PDT 24
Peak memory 206652 kb
Host smart-c4a3d247-fb88-45c0-8f94-5f33162c0241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42265
10338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.4226510338
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.134952916
Short name T1942
Test name
Test status
Simulation time 240547618 ps
CPU time 0.98 seconds
Started Jul 20 06:21:45 PM PDT 24
Finished Jul 20 06:21:47 PM PDT 24
Peak memory 206648 kb
Host smart-2bc8b04d-d2ff-450c-a0b0-51dd5bd1f5f1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=134952916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.134952916
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.2072553220
Short name T1342
Test name
Test status
Simulation time 141946563 ps
CPU time 0.77 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206652 kb
Host smart-2632ef59-7f55-47a3-8a21-7e51997d660e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20725
53220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.2072553220
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4249903303
Short name T1051
Test name
Test status
Simulation time 40406056 ps
CPU time 0.68 seconds
Started Jul 20 06:21:50 PM PDT 24
Finished Jul 20 06:21:52 PM PDT 24
Peak memory 206628 kb
Host smart-20fdd8f0-9c00-4338-b46b-6530a6ba5f35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42499
03303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4249903303
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.4292996813
Short name T248
Test name
Test status
Simulation time 19678830334 ps
CPU time 45.73 seconds
Started Jul 20 06:21:48 PM PDT 24
Finished Jul 20 06:22:35 PM PDT 24
Peak memory 207068 kb
Host smart-d50741df-f559-49ae-9068-619974b2c359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42929
96813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.4292996813
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2943247819
Short name T1360
Test name
Test status
Simulation time 183327272 ps
CPU time 0.88 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206656 kb
Host smart-75d8532c-ed96-4b48-a13b-5dd43b800187
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29432
47819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2943247819
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.4197095635
Short name T2428
Test name
Test status
Simulation time 256731106 ps
CPU time 0.92 seconds
Started Jul 20 06:21:54 PM PDT 24
Finished Jul 20 06:21:56 PM PDT 24
Peak memory 206644 kb
Host smart-c4fb9ec7-c20e-4fa0-af38-87b6348a8148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41970
95635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.4197095635
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.3412481288
Short name T1426
Test name
Test status
Simulation time 179880606 ps
CPU time 0.85 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206652 kb
Host smart-c080f057-55e7-4a0f-a7d6-96f428e07952
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34124
81288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.3412481288
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.290736113
Short name T2635
Test name
Test status
Simulation time 171833171 ps
CPU time 0.82 seconds
Started Jul 20 06:21:53 PM PDT 24
Finished Jul 20 06:21:55 PM PDT 24
Peak memory 206636 kb
Host smart-f134cdd9-b441-4a36-afb3-51489294cf58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29073
6113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.290736113
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.2231812447
Short name T1119
Test name
Test status
Simulation time 152716688 ps
CPU time 0.82 seconds
Started Jul 20 06:21:54 PM PDT 24
Finished Jul 20 06:21:56 PM PDT 24
Peak memory 206652 kb
Host smart-550f0eb3-ff92-467b-8bbb-b56fb10ecbb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22318
12447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.2231812447
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.3807289042
Short name T1247
Test name
Test status
Simulation time 213800420 ps
CPU time 0.83 seconds
Started Jul 20 06:21:50 PM PDT 24
Finished Jul 20 06:21:52 PM PDT 24
Peak memory 206588 kb
Host smart-69b0bf22-70eb-43d7-9e32-2d3901767c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
89042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.3807289042
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4121722265
Short name T2210
Test name
Test status
Simulation time 160728816 ps
CPU time 0.95 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:54 PM PDT 24
Peak memory 206656 kb
Host smart-ef4d3907-00c1-462c-8586-32b7d9a422ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41217
22265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4121722265
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.1634089168
Short name T1819
Test name
Test status
Simulation time 248104953 ps
CPU time 0.93 seconds
Started Jul 20 06:21:50 PM PDT 24
Finished Jul 20 06:21:51 PM PDT 24
Peak memory 206740 kb
Host smart-eeb8c38e-2750-49d2-88f7-8a0cc5183f91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16340
89168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.1634089168
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.756993569
Short name T1327
Test name
Test status
Simulation time 6550000307 ps
CPU time 47.17 seconds
Started Jul 20 06:21:54 PM PDT 24
Finished Jul 20 06:22:42 PM PDT 24
Peak memory 206836 kb
Host smart-7c3632ef-bcb8-4561-92de-fa5eea8c7a8d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=756993569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.756993569
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.2249709841
Short name T1661
Test name
Test status
Simulation time 166920094 ps
CPU time 0.82 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:21:55 PM PDT 24
Peak memory 206620 kb
Host smart-86110990-1714-43ec-ab54-9c0fa80836e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22497
09841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.2249709841
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.487373368
Short name T2613
Test name
Test status
Simulation time 210119246 ps
CPU time 0.8 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:54 PM PDT 24
Peak memory 206656 kb
Host smart-82d66be9-2cf9-4d61-8634-26109964aa95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48737
3368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.487373368
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.4205164420
Short name T677
Test name
Test status
Simulation time 1278928544 ps
CPU time 2.52 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:21:56 PM PDT 24
Peak memory 206796 kb
Host smart-de2b8cdf-911f-44c6-ba7f-a497348d68b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
64420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.4205164420
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.884496899
Short name T1828
Test name
Test status
Simulation time 3159427093 ps
CPU time 28.75 seconds
Started Jul 20 06:21:49 PM PDT 24
Finished Jul 20 06:22:19 PM PDT 24
Peak memory 206920 kb
Host smart-a28a67e5-bc37-46f5-993e-68e13bde85b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88449
6899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.884496899
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1058034198
Short name T352
Test name
Test status
Simulation time 98186544 ps
CPU time 0.73 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206696 kb
Host smart-d1daea43-30a1-4fa9-838c-3afc1aefe3a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1058034198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1058034198
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.875707763
Short name T1471
Test name
Test status
Simulation time 3906021927 ps
CPU time 4.4 seconds
Started Jul 20 06:21:50 PM PDT 24
Finished Jul 20 06:21:55 PM PDT 24
Peak memory 206716 kb
Host smart-58ad5c3a-f9f7-4cd9-b85d-736c4e2e5d5b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=875707763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.875707763
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.180797309
Short name T2642
Test name
Test status
Simulation time 13328691814 ps
CPU time 11.56 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206900 kb
Host smart-f83f0acf-e78e-480c-85fa-aca330ff48d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=180797309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.180797309
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1115534200
Short name T8
Test name
Test status
Simulation time 23384217096 ps
CPU time 22.87 seconds
Started Jul 20 06:21:54 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206780 kb
Host smart-99b81cc4-a819-4470-ac69-c1b1b3f4f0df
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1115534200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1115534200
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1316722523
Short name T2181
Test name
Test status
Simulation time 169936541 ps
CPU time 0.83 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206668 kb
Host smart-7983bf57-440b-4830-960b-ef4b99c9f9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13167
22523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1316722523
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.1169040245
Short name T2646
Test name
Test status
Simulation time 190066641 ps
CPU time 0.85 seconds
Started Jul 20 06:21:51 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206632 kb
Host smart-ae759218-5b14-4dfd-b2cf-63a240d8614e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11690
40245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.1169040245
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3460683137
Short name T1105
Test name
Test status
Simulation time 448863618 ps
CPU time 1.43 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:21:55 PM PDT 24
Peak memory 206644 kb
Host smart-fbbfadad-41cf-43b4-9cc5-482b955acf8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34606
83137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3460683137
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2009767505
Short name T1787
Test name
Test status
Simulation time 1240703669 ps
CPU time 3.41 seconds
Started Jul 20 06:21:49 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206740 kb
Host smart-a9b95808-d316-4821-9226-98ca64c17868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20097
67505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2009767505
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.1488826863
Short name T598
Test name
Test status
Simulation time 15263829945 ps
CPU time 29.67 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:22:23 PM PDT 24
Peak memory 206840 kb
Host smart-486ab491-de77-47bf-b75e-e5cbba193d08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14888
26863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.1488826863
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.982446053
Short name T1495
Test name
Test status
Simulation time 387777211 ps
CPU time 1.23 seconds
Started Jul 20 06:21:50 PM PDT 24
Finished Jul 20 06:21:53 PM PDT 24
Peak memory 206652 kb
Host smart-8168e77a-0d60-44d0-a408-1577097eab3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98244
6053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.982446053
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.810254083
Short name T2351
Test name
Test status
Simulation time 144495590 ps
CPU time 0.76 seconds
Started Jul 20 06:21:53 PM PDT 24
Finished Jul 20 06:21:55 PM PDT 24
Peak memory 206660 kb
Host smart-be1ac1be-79ef-4e04-9ae0-ed792ee08306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81025
4083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.810254083
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.4190405432
Short name T1282
Test name
Test status
Simulation time 39392740 ps
CPU time 0.68 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:21:55 PM PDT 24
Peak memory 206656 kb
Host smart-ee38bc23-71bb-4c05-85a8-d3bebfdedabe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41904
05432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.4190405432
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.2802378766
Short name T481
Test name
Test status
Simulation time 925707146 ps
CPU time 2.42 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:21:56 PM PDT 24
Peak memory 206740 kb
Host smart-579a810c-44e3-4b43-a2db-7695273b55d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28023
78766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.2802378766
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1033031435
Short name T84
Test name
Test status
Simulation time 243295384 ps
CPU time 1.79 seconds
Started Jul 20 06:21:52 PM PDT 24
Finished Jul 20 06:21:56 PM PDT 24
Peak memory 206792 kb
Host smart-c674f987-cf52-4110-9100-83e014c4571b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330
31435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1033031435
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.3346379886
Short name T521
Test name
Test status
Simulation time 189301330 ps
CPU time 0.85 seconds
Started Jul 20 06:21:56 PM PDT 24
Finished Jul 20 06:21:58 PM PDT 24
Peak memory 206652 kb
Host smart-2a1f9dbf-2190-4eee-a5f6-585aa142ed24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33463
79886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.3346379886
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.687731811
Short name T1249
Test name
Test status
Simulation time 142564724 ps
CPU time 0.75 seconds
Started Jul 20 06:22:06 PM PDT 24
Finished Jul 20 06:22:07 PM PDT 24
Peak memory 206616 kb
Host smart-9765b6ed-6cbb-4bf1-aa3b-e8287fbb2901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68773
1811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.687731811
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.185429083
Short name T506
Test name
Test status
Simulation time 218778873 ps
CPU time 0.94 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:02 PM PDT 24
Peak memory 206652 kb
Host smart-66a80959-3a86-470e-9e4d-0e60772f7c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18542
9083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.185429083
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_invalid_sync.4019185000
Short name T76
Test name
Test status
Simulation time 4797684382 ps
CPU time 42.99 seconds
Started Jul 20 06:21:58 PM PDT 24
Finished Jul 20 06:22:43 PM PDT 24
Peak memory 206924 kb
Host smart-cc1f32d3-5e6c-4616-a3de-29c5ebfc6dc4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4019185000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_invalid_sync.4019185000
Directory /workspace/14.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.958223929
Short name T1411
Test name
Test status
Simulation time 8744841861 ps
CPU time 27.62 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:32 PM PDT 24
Peak memory 206896 kb
Host smart-3be2cb5e-5284-4368-bcb1-5281ecc13329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95822
3929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.958223929
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3460300366
Short name T65
Test name
Test status
Simulation time 202903277 ps
CPU time 0.82 seconds
Started Jul 20 06:21:57 PM PDT 24
Finished Jul 20 06:21:58 PM PDT 24
Peak memory 206636 kb
Host smart-686cece0-f292-48ae-ad3a-372d0d5a1d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34603
00366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3460300366
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.769399219
Short name T2252
Test name
Test status
Simulation time 3304139144 ps
CPU time 4.57 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:07 PM PDT 24
Peak memory 206724 kb
Host smart-25311ca1-1d41-4165-b0e1-d0f07e7e657d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76939
9219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.769399219
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.1306150876
Short name T233
Test name
Test status
Simulation time 7501860883 ps
CPU time 212.66 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:25:35 PM PDT 24
Peak memory 206948 kb
Host smart-1563f1e3-776b-4603-9fa5-bcfe6a999d3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13061
50876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.1306150876
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.2060577955
Short name T202
Test name
Test status
Simulation time 4753950476 ps
CPU time 133.48 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206788 kb
Host smart-054740e7-0fe3-4de0-87c8-a9fcb3abb369
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2060577955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.2060577955
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.974654306
Short name T1379
Test name
Test status
Simulation time 239561700 ps
CPU time 0.94 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206648 kb
Host smart-90d210cd-8ce7-4cc1-8ffb-7c032e904e74
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=974654306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.974654306
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.3490703711
Short name T562
Test name
Test status
Simulation time 242372074 ps
CPU time 0.87 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:02 PM PDT 24
Peak memory 206652 kb
Host smart-2e61ca25-e851-444c-9e42-9ef2dee41ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34907
03711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.3490703711
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.868667154
Short name T2039
Test name
Test status
Simulation time 6466720306 ps
CPU time 175 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206856 kb
Host smart-7504a810-a3a3-4889-99ac-9d165910129b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86866
7154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.868667154
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.3811135847
Short name T1924
Test name
Test status
Simulation time 5122549371 ps
CPU time 47.55 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206892 kb
Host smart-e149a57d-3906-49a5-a734-c7d136ccc5db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3811135847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.3811135847
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1186889705
Short name T749
Test name
Test status
Simulation time 212120583 ps
CPU time 0.88 seconds
Started Jul 20 06:22:01 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206660 kb
Host smart-6c799df0-dbf4-48e2-a930-09f2f3e97a35
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1186889705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1186889705
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3085015900
Short name T1268
Test name
Test status
Simulation time 152671417 ps
CPU time 0.82 seconds
Started Jul 20 06:21:58 PM PDT 24
Finished Jul 20 06:22:01 PM PDT 24
Peak memory 206652 kb
Host smart-d73896b6-0bf5-4941-9329-9408d79f4e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30850
15900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3085015900
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.749602715
Short name T349
Test name
Test status
Simulation time 160576452 ps
CPU time 0.8 seconds
Started Jul 20 06:22:01 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206648 kb
Host smart-98b65123-f00e-4353-a37c-41e7b2de2cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74960
2715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.749602715
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.4104619785
Short name T2051
Test name
Test status
Simulation time 208899962 ps
CPU time 0.84 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:02 PM PDT 24
Peak memory 206644 kb
Host smart-bb95cc20-7606-46bf-b1e7-3706c72f22c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41046
19785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.4104619785
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2253462886
Short name T2422
Test name
Test status
Simulation time 150469767 ps
CPU time 0.79 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206640 kb
Host smart-17b87b44-88ab-4d08-a2e2-930f2dd38aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22534
62886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2253462886
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.3782395391
Short name T1396
Test name
Test status
Simulation time 154717858 ps
CPU time 0.76 seconds
Started Jul 20 06:21:57 PM PDT 24
Finished Jul 20 06:21:58 PM PDT 24
Peak memory 206648 kb
Host smart-1b937abb-8af3-44bc-b8af-a08933740ef6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37823
95391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.3782395391
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.2938054552
Short name T2337
Test name
Test status
Simulation time 257848584 ps
CPU time 0.97 seconds
Started Jul 20 06:22:01 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206660 kb
Host smart-5bc864a6-6e74-447b-9f22-916331046154
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2938054552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.2938054552
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1735945780
Short name T1768
Test name
Test status
Simulation time 147117783 ps
CPU time 0.81 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:04 PM PDT 24
Peak memory 206660 kb
Host smart-007839ce-64d5-41a5-a4dd-8497d4933884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17359
45780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1735945780
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.2004154980
Short name T40
Test name
Test status
Simulation time 86547747 ps
CPU time 0.69 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206632 kb
Host smart-8fffbdcf-052d-4bae-b7cd-3f362819ad99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20041
54980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.2004154980
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3490005172
Short name T1806
Test name
Test status
Simulation time 15405737815 ps
CPU time 31.21 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:34 PM PDT 24
Peak memory 206936 kb
Host smart-e8fb801e-04af-4a30-bb96-8d771c8234a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34900
05172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3490005172
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.3384514109
Short name T2459
Test name
Test status
Simulation time 166009224 ps
CPU time 0.84 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206648 kb
Host smart-61dc4919-375b-4bdd-b2a2-7f66d0bffcf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33845
14109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.3384514109
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.4138021659
Short name T932
Test name
Test status
Simulation time 167186389 ps
CPU time 0.87 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206644 kb
Host smart-88a08f00-b676-4655-a693-9f312839de2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41380
21659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.4138021659
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2655259150
Short name T577
Test name
Test status
Simulation time 203664150 ps
CPU time 0.88 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206656 kb
Host smart-279497dc-25e5-4613-a90c-bf988e713f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26552
59150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2655259150
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.3333734624
Short name T2433
Test name
Test status
Simulation time 230483260 ps
CPU time 0.91 seconds
Started Jul 20 06:22:06 PM PDT 24
Finished Jul 20 06:22:08 PM PDT 24
Peak memory 206600 kb
Host smart-b26b4e58-5d9a-4398-8c77-09ebc9c488a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33337
34624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.3333734624
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.3648337129
Short name T2462
Test name
Test status
Simulation time 188829263 ps
CPU time 0.87 seconds
Started Jul 20 06:21:58 PM PDT 24
Finished Jul 20 06:22:00 PM PDT 24
Peak memory 206636 kb
Host smart-52a69f67-8de1-4b20-9f1c-d1ac194e2e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36483
37129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.3648337129
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3555276073
Short name T2019
Test name
Test status
Simulation time 164196927 ps
CPU time 0.77 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206648 kb
Host smart-74d55a9b-30ce-4958-8a8c-66dc3cac6b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
76073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3555276073
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.3686998453
Short name T397
Test name
Test status
Simulation time 176130449 ps
CPU time 0.81 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:04 PM PDT 24
Peak memory 206696 kb
Host smart-b0b59cc3-f4c1-4469-afdc-13e7e3ad77f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36869
98453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.3686998453
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1091339643
Short name T1857
Test name
Test status
Simulation time 249970141 ps
CPU time 0.97 seconds
Started Jul 20 06:21:58 PM PDT 24
Finished Jul 20 06:22:02 PM PDT 24
Peak memory 206628 kb
Host smart-7b5509ea-b9b1-4df1-ae6e-06bcb84f2add
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10913
39643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1091339643
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2497195007
Short name T1861
Test name
Test status
Simulation time 5013465937 ps
CPU time 34.56 seconds
Started Jul 20 06:22:03 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206860 kb
Host smart-5b761049-bed1-4795-ba6c-b8cd2a678475
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2497195007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2497195007
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1238783361
Short name T145
Test name
Test status
Simulation time 163147758 ps
CPU time 0.8 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:02 PM PDT 24
Peak memory 206632 kb
Host smart-e8b2615b-989e-4643-878a-5fd59039eb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12387
83361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1238783361
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.853910581
Short name T654
Test name
Test status
Simulation time 234064796 ps
CPU time 0.93 seconds
Started Jul 20 06:22:02 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 206632 kb
Host smart-ea996352-0505-48a0-a8cd-27755be590e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85391
0581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.853910581
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2439169378
Short name T2703
Test name
Test status
Simulation time 1142065228 ps
CPU time 2.68 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206808 kb
Host smart-37476ff9-4b59-45c2-89df-60d682e75920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
69378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2439169378
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1987200420
Short name T1146
Test name
Test status
Simulation time 7818013614 ps
CPU time 54.36 seconds
Started Jul 20 06:22:01 PM PDT 24
Finished Jul 20 06:22:59 PM PDT 24
Peak memory 206856 kb
Host smart-3482f0a6-1735-4ed4-8ed0-c3da9010b90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19872
00420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1987200420
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2653614605
Short name T1654
Test name
Test status
Simulation time 74730657 ps
CPU time 0.72 seconds
Started Jul 20 06:22:14 PM PDT 24
Finished Jul 20 06:22:16 PM PDT 24
Peak memory 206696 kb
Host smart-6cb8767a-5a6e-4772-b594-d7a9257ba523
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2653614605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2653614605
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.4223177823
Short name T2220
Test name
Test status
Simulation time 4050340094 ps
CPU time 4.69 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:07 PM PDT 24
Peak memory 206716 kb
Host smart-3a21c7fe-6e6b-4d7a-a578-e87bc1d9976e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4223177823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.4223177823
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.973031678
Short name T2636
Test name
Test status
Simulation time 13373911754 ps
CPU time 12.5 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:15 PM PDT 24
Peak memory 206888 kb
Host smart-2395a3bf-25d1-436c-a3cf-454ea19fb668
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=973031678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.973031678
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3082582048
Short name T1132
Test name
Test status
Simulation time 23379318598 ps
CPU time 23.22 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:26 PM PDT 24
Peak memory 206924 kb
Host smart-3824d554-1737-4613-bb77-1b398d73b763
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3082582048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3082582048
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.266872117
Short name T472
Test name
Test status
Simulation time 183430532 ps
CPU time 0.84 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206656 kb
Host smart-6df3beb1-9d8d-4563-8b9e-634c073802c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26687
2117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.266872117
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1218594611
Short name T2301
Test name
Test status
Simulation time 167749354 ps
CPU time 0.81 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:01 PM PDT 24
Peak memory 206628 kb
Host smart-7b708174-def9-4b92-a347-3b8143434df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12185
94611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1218594611
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.4212334647
Short name T2484
Test name
Test status
Simulation time 343503138 ps
CPU time 1.19 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206644 kb
Host smart-55f54cbc-8f1a-46d0-9c2c-1ccee5c9fceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42123
34647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.4212334647
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.3675816741
Short name T1086
Test name
Test status
Simulation time 755511368 ps
CPU time 1.71 seconds
Started Jul 20 06:21:58 PM PDT 24
Finished Jul 20 06:22:01 PM PDT 24
Peak memory 206732 kb
Host smart-805d13ac-2fda-4c59-8986-7d2246992783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36758
16741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.3675816741
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.3643867740
Short name T1706
Test name
Test status
Simulation time 6280232187 ps
CPU time 11.22 seconds
Started Jul 20 06:22:01 PM PDT 24
Finished Jul 20 06:22:16 PM PDT 24
Peak memory 206896 kb
Host smart-49983949-0ce4-416f-ba71-9ad8a98eef12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36438
67740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.3643867740
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.1964005763
Short name T2069
Test name
Test status
Simulation time 472859418 ps
CPU time 1.41 seconds
Started Jul 20 06:22:02 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 206652 kb
Host smart-8df3b169-0411-4f27-a4a4-e9b3b61a50c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19640
05763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.1964005763
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.1660406295
Short name T1672
Test name
Test status
Simulation time 138734901 ps
CPU time 0.74 seconds
Started Jul 20 06:21:59 PM PDT 24
Finished Jul 20 06:22:03 PM PDT 24
Peak memory 206660 kb
Host smart-8a1dca83-a61b-405e-84d6-f7f85b7620ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16604
06295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.1660406295
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.2007268838
Short name T2099
Test name
Test status
Simulation time 40827559 ps
CPU time 0.79 seconds
Started Jul 20 06:22:00 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206640 kb
Host smart-6659be73-c461-4d2d-9079-5cdd725e1919
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20072
68838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.2007268838
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3077213088
Short name T684
Test name
Test status
Simulation time 925761579 ps
CPU time 2.36 seconds
Started Jul 20 06:22:02 PM PDT 24
Finished Jul 20 06:22:07 PM PDT 24
Peak memory 206772 kb
Host smart-517e52de-ec34-4ec7-a53c-3c1a531ef59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30772
13088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3077213088
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.572786483
Short name T1297
Test name
Test status
Simulation time 407643782 ps
CPU time 2.49 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 206736 kb
Host smart-c8d8a041-b2cd-4e10-b73e-ae72fc13bae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57278
6483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.572786483
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.598831899
Short name T1837
Test name
Test status
Simulation time 187201363 ps
CPU time 0.85 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:22:10 PM PDT 24
Peak memory 206644 kb
Host smart-7c2aae8a-ac69-4dbb-aca3-0ffe938d7afc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59883
1899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.598831899
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.1012322028
Short name T696
Test name
Test status
Simulation time 142763114 ps
CPU time 0.76 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 206652 kb
Host smart-f9948602-e0c1-4d76-9b9d-42b3e58640dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10123
22028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.1012322028
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.986858938
Short name T2369
Test name
Test status
Simulation time 219242738 ps
CPU time 0.91 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:22:10 PM PDT 24
Peak memory 206656 kb
Host smart-0b7d2996-21e1-478f-b6b5-284cfb24dc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98685
8938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.986858938
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.2848250838
Short name T2229
Test name
Test status
Simulation time 5951817104 ps
CPU time 53.78 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206900 kb
Host smart-38f65774-5efe-49cd-8db8-3d0869ae5811
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2848250838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2848250838
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2216801690
Short name T363
Test name
Test status
Simulation time 203505277 ps
CPU time 0.88 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:22:10 PM PDT 24
Peak memory 206660 kb
Host smart-68beb701-c818-419e-96b6-5c73fae42859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22168
01690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2216801690
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3949496041
Short name T647
Test name
Test status
Simulation time 23362599100 ps
CPU time 25.5 seconds
Started Jul 20 06:22:05 PM PDT 24
Finished Jul 20 06:22:32 PM PDT 24
Peak memory 206760 kb
Host smart-59f08fca-1151-4655-a728-7e425aba1197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39494
96041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3949496041
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2850052157
Short name T2421
Test name
Test status
Simulation time 3261772533 ps
CPU time 4.03 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:22:12 PM PDT 24
Peak memory 206708 kb
Host smart-e83174de-28e4-48a1-9f93-9cba16a7a8ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28500
52157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2850052157
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.310305977
Short name T1886
Test name
Test status
Simulation time 11945803280 ps
CPU time 113.43 seconds
Started Jul 20 06:22:05 PM PDT 24
Finished Jul 20 06:24:00 PM PDT 24
Peak memory 206936 kb
Host smart-48674a13-610f-4e30-9541-bd73b7553a4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31030
5977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.310305977
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.2070096916
Short name T2718
Test name
Test status
Simulation time 3849002187 ps
CPU time 102.5 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:23:50 PM PDT 24
Peak memory 206852 kb
Host smart-ecf74415-d5c9-4ba8-9c54-3e83e01859ed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2070096916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.2070096916
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3757090172
Short name T2426
Test name
Test status
Simulation time 265400297 ps
CPU time 0.95 seconds
Started Jul 20 06:22:04 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 206656 kb
Host smart-a1f3401b-728a-485f-8d42-9c8e1f64fa53
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3757090172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3757090172
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.3069879705
Short name T1552
Test name
Test status
Simulation time 204433977 ps
CPU time 0.93 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:22:10 PM PDT 24
Peak memory 206652 kb
Host smart-b1e61dfa-5e9c-4b14-92e8-9b2b2f05af34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30698
79705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.3069879705
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.4150462478
Short name T2032
Test name
Test status
Simulation time 3409596479 ps
CPU time 25.97 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:36 PM PDT 24
Peak memory 206932 kb
Host smart-b2a21158-b5a3-4945-a88f-9d99e350f9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41504
62478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.4150462478
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2763150819
Short name T469
Test name
Test status
Simulation time 6428726943 ps
CPU time 61.28 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206900 kb
Host smart-0ad826d7-56e3-4b24-ac6b-c08e44787e44
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2763150819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2763150819
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.1168060384
Short name T989
Test name
Test status
Simulation time 186506812 ps
CPU time 0.85 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:22:10 PM PDT 24
Peak memory 206660 kb
Host smart-25675075-6982-4621-aeda-34d191ff4ce6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1168060384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.1168060384
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2065322543
Short name T1628
Test name
Test status
Simulation time 166807172 ps
CPU time 0.79 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:22:08 PM PDT 24
Peak memory 206636 kb
Host smart-d83222f5-be58-4dfa-b785-66d46aae2862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20653
22543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2065322543
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.123062151
Short name T100
Test name
Test status
Simulation time 206597582 ps
CPU time 0.89 seconds
Started Jul 20 06:22:04 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 206652 kb
Host smart-f70fce84-1a33-4bcd-95c2-f8056bbebac9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12306
2151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.123062151
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.827164479
Short name T2156
Test name
Test status
Simulation time 161536390 ps
CPU time 0.84 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:12 PM PDT 24
Peak memory 206652 kb
Host smart-7ea15750-9c70-41cf-96de-096c0550c00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82716
4479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.827164479
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.1530126210
Short name T206
Test name
Test status
Simulation time 199278159 ps
CPU time 0.85 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:22:09 PM PDT 24
Peak memory 206644 kb
Host smart-696f07a6-49bb-4469-bc20-2cb502985361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15301
26210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.1530126210
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.2256440065
Short name T1697
Test name
Test status
Simulation time 196259052 ps
CPU time 0.8 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 206656 kb
Host smart-66534e98-6b6d-4ad9-9f84-b3a59fc3d501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22564
40065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.2256440065
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1166987648
Short name T2074
Test name
Test status
Simulation time 155110700 ps
CPU time 0.79 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:22:09 PM PDT 24
Peak memory 206656 kb
Host smart-1e48b35c-3d97-430d-9077-2972554deb36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11669
87648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1166987648
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1029642391
Short name T636
Test name
Test status
Simulation time 246922102 ps
CPU time 1 seconds
Started Jul 20 06:22:08 PM PDT 24
Finished Jul 20 06:22:10 PM PDT 24
Peak memory 206652 kb
Host smart-82aaccf1-14b7-4f15-97c5-75533a629ffb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1029642391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1029642391
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1445967005
Short name T571
Test name
Test status
Simulation time 152367724 ps
CPU time 0.76 seconds
Started Jul 20 06:22:06 PM PDT 24
Finished Jul 20 06:22:08 PM PDT 24
Peak memory 206640 kb
Host smart-8a7fbfde-b332-45b8-9d13-b0229bb3a2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14459
67005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1445967005
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3394610366
Short name T916
Test name
Test status
Simulation time 14776611436 ps
CPU time 37.08 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:47 PM PDT 24
Peak memory 206968 kb
Host smart-d639756d-463c-4e80-a0f5-4ab3b2c1c7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33946
10366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3394610366
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.4091106081
Short name T730
Test name
Test status
Simulation time 180226799 ps
CPU time 0.84 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:22:09 PM PDT 24
Peak memory 206668 kb
Host smart-a9d88feb-2f1e-4546-9e1d-ccf37a54309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40911
06081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.4091106081
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.105058043
Short name T1790
Test name
Test status
Simulation time 192567710 ps
CPU time 0.82 seconds
Started Jul 20 06:22:05 PM PDT 24
Finished Jul 20 06:22:07 PM PDT 24
Peak memory 206628 kb
Host smart-1e7ac7f9-2d7e-428d-8522-05f231289879
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10505
8043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.105058043
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.525704384
Short name T2307
Test name
Test status
Simulation time 224105601 ps
CPU time 0.9 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:22:09 PM PDT 24
Peak memory 206644 kb
Host smart-382a6ddc-f246-4350-b054-95ac0e9d4d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52570
4384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.525704384
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.2953017269
Short name T1832
Test name
Test status
Simulation time 180593835 ps
CPU time 0.81 seconds
Started Jul 20 06:22:06 PM PDT 24
Finished Jul 20 06:22:07 PM PDT 24
Peak memory 206644 kb
Host smart-b497bdd8-79a0-46b3-b0b6-e949d7725405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29530
17269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.2953017269
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3819002056
Short name T1983
Test name
Test status
Simulation time 189892912 ps
CPU time 0.81 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 206660 kb
Host smart-1ac98e96-4615-4509-a71f-e6c15b952c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38190
02056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3819002056
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.1997794149
Short name T1395
Test name
Test status
Simulation time 170822732 ps
CPU time 0.83 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:11 PM PDT 24
Peak memory 206652 kb
Host smart-1bb15132-6c91-4974-829c-1d1bb67ffa0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19977
94149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.1997794149
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.4177895482
Short name T2740
Test name
Test status
Simulation time 153954044 ps
CPU time 0.76 seconds
Started Jul 20 06:22:07 PM PDT 24
Finished Jul 20 06:22:09 PM PDT 24
Peak memory 206648 kb
Host smart-481d909d-6ccb-43b2-96ad-324500eb7b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41778
95482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.4177895482
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3384125037
Short name T2558
Test name
Test status
Simulation time 198447500 ps
CPU time 0.87 seconds
Started Jul 20 06:22:06 PM PDT 24
Finished Jul 20 06:22:08 PM PDT 24
Peak memory 206616 kb
Host smart-2850e433-7acd-4614-852f-d0b43d3a7c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33841
25037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3384125037
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2933966739
Short name T799
Test name
Test status
Simulation time 4343057521 ps
CPU time 129.53 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206848 kb
Host smart-4e1d6aa4-8723-4e54-a4e1-fd33b123f923
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2933966739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2933966739
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.717372665
Short name T2153
Test name
Test status
Simulation time 215516267 ps
CPU time 0.85 seconds
Started Jul 20 06:22:09 PM PDT 24
Finished Jul 20 06:22:12 PM PDT 24
Peak memory 206648 kb
Host smart-ca5a050d-84d9-437a-9bad-022b56eb4863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71737
2665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.717372665
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.2092037706
Short name T241
Test name
Test status
Simulation time 248754386 ps
CPU time 0.83 seconds
Started Jul 20 06:22:04 PM PDT 24
Finished Jul 20 06:22:07 PM PDT 24
Peak memory 206628 kb
Host smart-5dd80646-08d4-419a-900e-8ede4258efa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
37706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.2092037706
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2640890035
Short name T237
Test name
Test status
Simulation time 660503826 ps
CPU time 1.75 seconds
Started Jul 20 06:22:14 PM PDT 24
Finished Jul 20 06:22:17 PM PDT 24
Peak memory 206648 kb
Host smart-6dfbfe1d-4847-4293-85e5-d6f7b1683beb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26408
90035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2640890035
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.2381333230
Short name T1970
Test name
Test status
Simulation time 6094342980 ps
CPU time 50.78 seconds
Started Jul 20 06:22:04 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 206920 kb
Host smart-79e0e8a0-4b79-4219-be39-ece18bfe4375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
33230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.2381333230
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.1404236753
Short name T2022
Test name
Test status
Simulation time 40993679 ps
CPU time 0.68 seconds
Started Jul 20 06:22:27 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206724 kb
Host smart-f4ecc349-a7fb-4db2-a3ed-79c7dd31193d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1404236753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.1404236753
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.3475629501
Short name T705
Test name
Test status
Simulation time 3391926493 ps
CPU time 4.15 seconds
Started Jul 20 06:22:13 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206712 kb
Host smart-2610e037-e5e7-4a9f-9e0f-46cb386ed2a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3475629501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.3475629501
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2840963554
Short name T605
Test name
Test status
Simulation time 13379457522 ps
CPU time 12.79 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:31 PM PDT 24
Peak memory 206788 kb
Host smart-e5997028-1606-41b4-994c-a64b0ecc3dba
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2840963554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2840963554
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.3414382900
Short name T1462
Test name
Test status
Simulation time 23370720140 ps
CPU time 27.07 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206920 kb
Host smart-100b6479-981d-4105-b615-d895409a461d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3414382900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.3414382900
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.654344854
Short name T2114
Test name
Test status
Simulation time 166582113 ps
CPU time 0.81 seconds
Started Jul 20 06:22:13 PM PDT 24
Finished Jul 20 06:22:14 PM PDT 24
Peak memory 206628 kb
Host smart-38d456a7-7ef4-43cc-a353-e438fb0c6b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65434
4854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.654344854
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.1932271838
Short name T2518
Test name
Test status
Simulation time 142473778 ps
CPU time 0.76 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:20 PM PDT 24
Peak memory 206668 kb
Host smart-dce8f4bf-5674-47ac-8f7d-3eb3a98f83ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19322
71838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.1932271838
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.991395338
Short name T356
Test name
Test status
Simulation time 488335150 ps
CPU time 1.41 seconds
Started Jul 20 06:22:13 PM PDT 24
Finished Jul 20 06:22:16 PM PDT 24
Peak memory 206652 kb
Host smart-c17f4e94-f291-4f61-8ba1-f331288bab03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99139
5338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.991395338
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1808134256
Short name T2311
Test name
Test status
Simulation time 1063153047 ps
CPU time 2.54 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:21 PM PDT 24
Peak memory 206800 kb
Host smart-b4bc6268-735f-4bfd-b425-b0719dca5116
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18081
34256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1808134256
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.388631622
Short name T505
Test name
Test status
Simulation time 11695583732 ps
CPU time 20.49 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:37 PM PDT 24
Peak memory 206860 kb
Host smart-bb269724-99cd-40c4-9a7f-5885dc4def89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
1622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.388631622
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.2202669103
Short name T2177
Test name
Test status
Simulation time 372626259 ps
CPU time 1.15 seconds
Started Jul 20 06:22:13 PM PDT 24
Finished Jul 20 06:22:15 PM PDT 24
Peak memory 206696 kb
Host smart-74378315-df04-4d80-94c6-0db4b401bd1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22026
69103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.2202669103
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.1334952933
Short name T2622
Test name
Test status
Simulation time 147217221 ps
CPU time 0.77 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206660 kb
Host smart-cbcb8d04-e0d6-4ed4-8a08-e70dbd3c7628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13349
52933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.1334952933
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.3918631108
Short name T452
Test name
Test status
Simulation time 35877944 ps
CPU time 0.61 seconds
Started Jul 20 06:22:15 PM PDT 24
Finished Jul 20 06:22:17 PM PDT 24
Peak memory 206592 kb
Host smart-ebd681e7-ec0f-4b92-a678-40ba48af0bd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39186
31108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.3918631108
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.3034316897
Short name T2690
Test name
Test status
Simulation time 985903680 ps
CPU time 2.13 seconds
Started Jul 20 06:22:15 PM PDT 24
Finished Jul 20 06:22:19 PM PDT 24
Peak memory 206808 kb
Host smart-4adf9072-4a3f-48d3-81ae-771b728a4492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30343
16897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.3034316897
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.3571422764
Short name T1222
Test name
Test status
Simulation time 276743148 ps
CPU time 2.14 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:21 PM PDT 24
Peak memory 206740 kb
Host smart-ed63d7e5-fd2e-41ae-a121-304cc0f6c45b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35714
22764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.3571422764
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.1045878896
Short name T1907
Test name
Test status
Simulation time 218977050 ps
CPU time 0.96 seconds
Started Jul 20 06:22:14 PM PDT 24
Finished Jul 20 06:22:16 PM PDT 24
Peak memory 206648 kb
Host smart-126de6de-9d9a-4d8f-93cd-166484e2bbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
78896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.1045878896
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.2960810105
Short name T928
Test name
Test status
Simulation time 139671638 ps
CPU time 0.76 seconds
Started Jul 20 06:22:12 PM PDT 24
Finished Jul 20 06:22:13 PM PDT 24
Peak memory 206632 kb
Host smart-32531eaf-842e-4572-9a70-6021c07212bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29608
10105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.2960810105
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2060392311
Short name T2463
Test name
Test status
Simulation time 218796048 ps
CPU time 0.88 seconds
Started Jul 20 06:22:15 PM PDT 24
Finished Jul 20 06:22:17 PM PDT 24
Peak memory 206656 kb
Host smart-6d5f8d34-cfd3-470c-ac3c-b16f1ab04a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20603
92311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2060392311
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.1804273596
Short name T97
Test name
Test status
Simulation time 8871160509 ps
CPU time 261.04 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:26:40 PM PDT 24
Peak memory 206832 kb
Host smart-652a6a03-784d-42f9-9aac-77f83c7f5513
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1804273596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.1804273596
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.167820501
Short name T1772
Test name
Test status
Simulation time 12490319246 ps
CPU time 43.93 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206992 kb
Host smart-245e088c-d6c6-43fe-9f0e-535e68be87c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16782
0501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.167820501
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.1745569942
Short name T1516
Test name
Test status
Simulation time 194003789 ps
CPU time 0.87 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:20 PM PDT 24
Peak memory 206652 kb
Host smart-997527e6-1856-468e-9c50-3b0e78525932
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17455
69942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.1745569942
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.4235005840
Short name T550
Test name
Test status
Simulation time 23300476655 ps
CPU time 25.48 seconds
Started Jul 20 06:22:15 PM PDT 24
Finished Jul 20 06:22:41 PM PDT 24
Peak memory 206784 kb
Host smart-a95ba0f5-5e95-4a85-9538-385777a1ff26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42350
05840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.4235005840
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.3358941248
Short name T2601
Test name
Test status
Simulation time 3308130416 ps
CPU time 4.12 seconds
Started Jul 20 06:22:12 PM PDT 24
Finished Jul 20 06:22:17 PM PDT 24
Peak memory 206720 kb
Host smart-38a7b6ce-54f8-4a55-ae19-03ae31728fc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33589
41248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.3358941248
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1938583193
Short name T2597
Test name
Test status
Simulation time 9734030586 ps
CPU time 266.86 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:26:46 PM PDT 24
Peak memory 206900 kb
Host smart-f52e5c0b-7d2c-4b2f-a01a-f4490fdc1bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19385
83193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1938583193
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.715784849
Short name T378
Test name
Test status
Simulation time 3176481077 ps
CPU time 30.92 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206844 kb
Host smart-7dafc5b8-cd6f-43fa-8281-e3f03a4f0ff5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=715784849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.715784849
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.3046777914
Short name T334
Test name
Test status
Simulation time 233930315 ps
CPU time 0.9 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:20 PM PDT 24
Peak memory 206664 kb
Host smart-8a48b1e9-4edc-4534-a16d-c702a9169383
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3046777914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.3046777914
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.1650348989
Short name T1060
Test name
Test status
Simulation time 260001177 ps
CPU time 0.97 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:19 PM PDT 24
Peak memory 206656 kb
Host smart-3edbb217-e452-4397-88e8-3aa337c012f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16503
48989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.1650348989
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3252963616
Short name T1417
Test name
Test status
Simulation time 3967658005 ps
CPU time 110.27 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206844 kb
Host smart-14257b6d-cf1a-4bbb-82a0-852ddda75227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32529
63616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3252963616
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.485250330
Short name T1791
Test name
Test status
Simulation time 7075085825 ps
CPU time 53.19 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:23:12 PM PDT 24
Peak memory 206924 kb
Host smart-5ed3effe-7845-4d65-b939-53ab698ebe2c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=485250330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.485250330
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.2647665500
Short name T1990
Test name
Test status
Simulation time 149820380 ps
CPU time 0.79 seconds
Started Jul 20 06:22:14 PM PDT 24
Finished Jul 20 06:22:16 PM PDT 24
Peak memory 206652 kb
Host smart-cd5fd344-cfce-4fd6-95e5-f3a5cb3ff904
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2647665500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.2647665500
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3268881916
Short name T1169
Test name
Test status
Simulation time 157867984 ps
CPU time 0.74 seconds
Started Jul 20 06:22:14 PM PDT 24
Finished Jul 20 06:22:16 PM PDT 24
Peak memory 206668 kb
Host smart-2b16d66a-ef2b-444c-a56c-55f8cbd2597a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32688
81916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3268881916
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.53484874
Short name T1673
Test name
Test status
Simulation time 179121884 ps
CPU time 0.81 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206600 kb
Host smart-bcacc80e-acbf-4bcf-af2b-502b49f4e677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53484
874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.53484874
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3711447175
Short name T402
Test name
Test status
Simulation time 150793641 ps
CPU time 0.82 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:20 PM PDT 24
Peak memory 206648 kb
Host smart-0e039ef9-16da-4a33-aaba-61322c0f938e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37114
47175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3711447175
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.3052167002
Short name T1775
Test name
Test status
Simulation time 266634566 ps
CPU time 0.88 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:19 PM PDT 24
Peak memory 206596 kb
Host smart-78f16971-cbb9-42d6-bb92-274f845c5387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30521
67002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.3052167002
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.3441524312
Short name T172
Test name
Test status
Simulation time 165457330 ps
CPU time 0.79 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:20 PM PDT 24
Peak memory 206644 kb
Host smart-1d567c20-8b12-426a-a2b9-34acc6dd3b99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34415
24312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.3441524312
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3052718627
Short name T551
Test name
Test status
Simulation time 222059397 ps
CPU time 0.91 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206600 kb
Host smart-8a24bd19-41c3-4deb-a0a4-294492e83d70
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3052718627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3052718627
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.2199396660
Short name T1099
Test name
Test status
Simulation time 150433723 ps
CPU time 0.73 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:19 PM PDT 24
Peak memory 206768 kb
Host smart-27a66500-aa80-4f1b-8b72-c9db8793eee3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21993
96660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.2199396660
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.2048233418
Short name T39
Test name
Test status
Simulation time 58219515 ps
CPU time 0.67 seconds
Started Jul 20 06:22:16 PM PDT 24
Finished Jul 20 06:22:18 PM PDT 24
Peak memory 206652 kb
Host smart-a7ae0f38-5505-4242-835e-cf7908e66757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20482
33418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.2048233418
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2645592036
Short name T2035
Test name
Test status
Simulation time 14027216694 ps
CPU time 32.2 seconds
Started Jul 20 06:22:18 PM PDT 24
Finished Jul 20 06:22:52 PM PDT 24
Peak memory 206948 kb
Host smart-0f026d24-f19c-4dbc-8845-1745a13900cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26455
92036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2645592036
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1747393002
Short name T1490
Test name
Test status
Simulation time 176448048 ps
CPU time 0.9 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:20 PM PDT 24
Peak memory 206656 kb
Host smart-9976ea5b-acac-4acf-905d-fb1137abef06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17473
93002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1747393002
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1389868401
Short name T602
Test name
Test status
Simulation time 207544970 ps
CPU time 0.9 seconds
Started Jul 20 06:22:15 PM PDT 24
Finished Jul 20 06:22:17 PM PDT 24
Peak memory 206656 kb
Host smart-b40f2fb1-b8ee-4780-b5c4-0d627efe101b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13898
68401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1389868401
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.3915628003
Short name T1144
Test name
Test status
Simulation time 218009730 ps
CPU time 0.85 seconds
Started Jul 20 06:22:13 PM PDT 24
Finished Jul 20 06:22:15 PM PDT 24
Peak memory 206740 kb
Host smart-5dac515f-c054-405f-bd00-022b616cef90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39156
28003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.3915628003
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.1225941240
Short name T1595
Test name
Test status
Simulation time 169177967 ps
CPU time 0.84 seconds
Started Jul 20 06:22:17 PM PDT 24
Finished Jul 20 06:22:20 PM PDT 24
Peak memory 206616 kb
Host smart-4f784935-ef89-423e-b4d0-60cd8e91633c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
41240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.1225941240
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.4174490703
Short name T794
Test name
Test status
Simulation time 169581048 ps
CPU time 0.82 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:27 PM PDT 24
Peak memory 206632 kb
Host smart-5a613a81-eb3c-4bb7-80f7-913f31e08e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
90703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.4174490703
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.2276380299
Short name T1002
Test name
Test status
Simulation time 154699519 ps
CPU time 0.78 seconds
Started Jul 20 06:22:24 PM PDT 24
Finished Jul 20 06:22:26 PM PDT 24
Peak memory 206696 kb
Host smart-e7da07b2-76b9-4830-979c-cd1978295adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22763
80299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.2276380299
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.508318108
Short name T2391
Test name
Test status
Simulation time 151018912 ps
CPU time 0.78 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:29 PM PDT 24
Peak memory 206652 kb
Host smart-ab0cfc1f-5b68-4dc1-96d5-877db9d41338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50831
8108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.508318108
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.1992941706
Short name T546
Test name
Test status
Simulation time 237303695 ps
CPU time 1 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:29 PM PDT 24
Peak memory 206640 kb
Host smart-ce7642cd-6211-4187-8e8f-ed29e20c55d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
41706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.1992941706
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2273138213
Short name T150
Test name
Test status
Simulation time 4757096573 ps
CPU time 35.54 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206916 kb
Host smart-18db61c0-17f7-4331-a856-2da4083c13bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2273138213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2273138213
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3950396098
Short name T2744
Test name
Test status
Simulation time 161642488 ps
CPU time 0.82 seconds
Started Jul 20 06:22:25 PM PDT 24
Finished Jul 20 06:22:27 PM PDT 24
Peak memory 206744 kb
Host smart-069c4533-94cc-4c13-937c-a3eeb32832cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39503
96098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3950396098
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.1826831990
Short name T674
Test name
Test status
Simulation time 172512021 ps
CPU time 0.85 seconds
Started Jul 20 06:22:27 PM PDT 24
Finished Jul 20 06:22:29 PM PDT 24
Peak memory 206636 kb
Host smart-51a904b7-4182-4cb2-ac25-0ef5b35f5817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18268
31990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.1826831990
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3674446424
Short name T1871
Test name
Test status
Simulation time 307209885 ps
CPU time 1.04 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:28 PM PDT 24
Peak memory 206652 kb
Host smart-9dd87559-f801-4c17-b813-198ab0883ae7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36744
46424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3674446424
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.3196078817
Short name T1600
Test name
Test status
Simulation time 4886187999 ps
CPU time 46.27 seconds
Started Jul 20 06:22:27 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206924 kb
Host smart-a550c228-b732-441d-855a-ac9b4a35c38c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31960
78817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.3196078817
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.3794580094
Short name T178
Test name
Test status
Simulation time 62539480 ps
CPU time 0.71 seconds
Started Jul 20 06:22:34 PM PDT 24
Finished Jul 20 06:22:35 PM PDT 24
Peak memory 206700 kb
Host smart-ed319477-ce06-4580-a8d3-234c226e8307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3794580094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.3794580094
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.3865823213
Short name T2058
Test name
Test status
Simulation time 3493339352 ps
CPU time 4.06 seconds
Started Jul 20 06:22:29 PM PDT 24
Finished Jul 20 06:22:34 PM PDT 24
Peak memory 206684 kb
Host smart-eda61d56-13ab-446a-854f-c43d91cd42a4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3865823213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.3865823213
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.2177239437
Short name T1752
Test name
Test status
Simulation time 13419300332 ps
CPU time 12.82 seconds
Started Jul 20 06:22:29 PM PDT 24
Finished Jul 20 06:22:43 PM PDT 24
Peak memory 206892 kb
Host smart-924a1719-d64d-4054-a0b8-2cbf90031acd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2177239437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.2177239437
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.994995866
Short name T51
Test name
Test status
Simulation time 23417022523 ps
CPU time 27.05 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:55 PM PDT 24
Peak memory 206792 kb
Host smart-44d94dd4-7c41-4074-a636-735286449948
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=994995866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.994995866
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.3084691872
Short name T2456
Test name
Test status
Simulation time 180667862 ps
CPU time 0.83 seconds
Started Jul 20 06:22:25 PM PDT 24
Finished Jul 20 06:22:26 PM PDT 24
Peak memory 206644 kb
Host smart-4082c005-15fa-4a15-9429-eb4f128a3f24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30846
91872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.3084691872
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.4096087471
Short name T458
Test name
Test status
Simulation time 136902252 ps
CPU time 0.77 seconds
Started Jul 20 06:22:29 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206648 kb
Host smart-9814a677-3a5c-4d99-8def-51004c74e6df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40960
87471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.4096087471
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.3241432940
Short name T235
Test name
Test status
Simulation time 537407327 ps
CPU time 1.71 seconds
Started Jul 20 06:22:27 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206792 kb
Host smart-9f581ac0-95d4-4001-a8ca-0131b7a0464e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32414
32940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.3241432940
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.158096618
Short name T1363
Test name
Test status
Simulation time 284488871 ps
CPU time 0.95 seconds
Started Jul 20 06:22:28 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206656 kb
Host smart-2d60ca78-1e4c-4029-9e8b-a9790d3dc32c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15809
6618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.158096618
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.2814647199
Short name T2444
Test name
Test status
Simulation time 17802677007 ps
CPU time 30.81 seconds
Started Jul 20 06:22:27 PM PDT 24
Finished Jul 20 06:22:59 PM PDT 24
Peak memory 206904 kb
Host smart-fcab1d85-a34f-4706-9fd5-93e456b98d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28146
47199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.2814647199
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.2709876506
Short name T1755
Test name
Test status
Simulation time 429008734 ps
CPU time 1.39 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:29 PM PDT 24
Peak memory 206656 kb
Host smart-1fe10842-12cf-434b-8a7b-08b75e418832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27098
76506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.2709876506
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.821501990
Short name T1524
Test name
Test status
Simulation time 135348557 ps
CPU time 0.76 seconds
Started Jul 20 06:22:28 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206656 kb
Host smart-5912aeb3-1cf7-4158-9031-0ea7b3a999d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82150
1990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.821501990
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.214501692
Short name T982
Test name
Test status
Simulation time 39264202 ps
CPU time 0.78 seconds
Started Jul 20 06:22:27 PM PDT 24
Finished Jul 20 06:22:29 PM PDT 24
Peak memory 206636 kb
Host smart-041d5568-0b41-4b4e-9d51-a3e39e50cca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
1692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.214501692
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.2869266165
Short name T1022
Test name
Test status
Simulation time 989532831 ps
CPU time 2.39 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206708 kb
Host smart-4d11428e-7583-45b9-a887-43a328c37f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28692
66165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.2869266165
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.576277002
Short name T1780
Test name
Test status
Simulation time 251319442 ps
CPU time 1.3 seconds
Started Jul 20 06:22:27 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206796 kb
Host smart-2c7a6e5b-0e0e-4812-8f30-004d34cc5c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57627
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.576277002
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.2536840274
Short name T540
Test name
Test status
Simulation time 197314158 ps
CPU time 0.93 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:28 PM PDT 24
Peak memory 206640 kb
Host smart-cce262b9-c4bf-460c-b55e-7322669daac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25368
40274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.2536840274
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3046490501
Short name T594
Test name
Test status
Simulation time 178911142 ps
CPU time 0.8 seconds
Started Jul 20 06:22:28 PM PDT 24
Finished Jul 20 06:22:30 PM PDT 24
Peak memory 206676 kb
Host smart-96f4b568-0466-4a26-adcd-f20738dda713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30464
90501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3046490501
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1505345652
Short name T316
Test name
Test status
Simulation time 228687709 ps
CPU time 0.92 seconds
Started Jul 20 06:22:25 PM PDT 24
Finished Jul 20 06:22:27 PM PDT 24
Peak memory 206660 kb
Host smart-7408cafa-6530-4e30-bf80-50cdbaddd6e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15053
45652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1505345652
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.3379681058
Short name T2583
Test name
Test status
Simulation time 5094903904 ps
CPU time 45.35 seconds
Started Jul 20 06:22:29 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206920 kb
Host smart-dbc24a30-e8e0-4f1d-8ca5-940d6b166566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33796
81058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.3379681058
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.2951112968
Short name T1308
Test name
Test status
Simulation time 178253471 ps
CPU time 0.85 seconds
Started Jul 20 06:22:25 PM PDT 24
Finished Jul 20 06:22:27 PM PDT 24
Peak memory 206652 kb
Host smart-dbceee4d-5668-4702-ba11-1c6eff3c93fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29511
12968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.2951112968
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.1694308054
Short name T1506
Test name
Test status
Simulation time 23333167714 ps
CPU time 21.26 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:22:48 PM PDT 24
Peak memory 206716 kb
Host smart-67ec1968-b2f5-40fa-b989-c071c4e9cba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16943
08054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.1694308054
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.169553366
Short name T236
Test name
Test status
Simulation time 3403875301 ps
CPU time 3.61 seconds
Started Jul 20 06:22:24 PM PDT 24
Finished Jul 20 06:22:28 PM PDT 24
Peak memory 206720 kb
Host smart-c52046bf-99c2-4c9a-bfc0-5bdf08e0b950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16955
3366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.169553366
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2725421460
Short name T1070
Test name
Test status
Simulation time 5245803111 ps
CPU time 141 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206924 kb
Host smart-30c1099a-4a8f-488b-a044-cd7a3c0960b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27254
21460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2725421460
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.4142798200
Short name T951
Test name
Test status
Simulation time 5394805303 ps
CPU time 39.36 seconds
Started Jul 20 06:22:26 PM PDT 24
Finished Jul 20 06:23:07 PM PDT 24
Peak memory 206852 kb
Host smart-2b0082d5-a862-4218-8ee5-16fb8ae766cf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4142798200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.4142798200
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.1433425430
Short name T1347
Test name
Test status
Simulation time 237980189 ps
CPU time 0.95 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206640 kb
Host smart-ba5d65cb-e530-4b1c-b7f9-de4cfd9eeb0e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1433425430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.1433425430
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1249127637
Short name T1854
Test name
Test status
Simulation time 228294461 ps
CPU time 0.89 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:46 PM PDT 24
Peak memory 206616 kb
Host smart-c1ec11d5-747b-49ea-a996-a0363314be2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12491
27637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1249127637
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4034392703
Short name T2323
Test name
Test status
Simulation time 5880010392 ps
CPU time 161.73 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:25:17 PM PDT 24
Peak memory 206876 kb
Host smart-db53ae1b-ee92-4a28-99d5-cb685aaa7cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40343
92703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4034392703
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2848401624
Short name T2736
Test name
Test status
Simulation time 5162901527 ps
CPU time 140.8 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206876 kb
Host smart-4ca7d414-e917-4e43-9a14-48ddee36cbc7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2848401624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2848401624
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.902850272
Short name T2248
Test name
Test status
Simulation time 154944162 ps
CPU time 0.81 seconds
Started Jul 20 06:22:39 PM PDT 24
Finished Jul 20 06:22:42 PM PDT 24
Peak memory 206644 kb
Host smart-2ecf005a-cf97-43be-aa3c-c3b56f89ccd1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=902850272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.902850272
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.3834418906
Short name T1291
Test name
Test status
Simulation time 164593459 ps
CPU time 0.79 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:46 PM PDT 24
Peak memory 206612 kb
Host smart-41ec8be9-d7ab-4d6d-acbb-a20c5a8820fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38344
18906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.3834418906
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.1847578559
Short name T1148
Test name
Test status
Simulation time 193574663 ps
CPU time 0.86 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206656 kb
Host smart-77beca30-98d8-4277-b72d-26a3761df75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18475
78559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.1847578559
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.2884499705
Short name T2668
Test name
Test status
Simulation time 265530332 ps
CPU time 0.89 seconds
Started Jul 20 06:22:36 PM PDT 24
Finished Jul 20 06:22:39 PM PDT 24
Peak memory 206656 kb
Host smart-7a2e85aa-f499-430f-a6f2-b4decc688a5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28844
99705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.2884499705
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.41599203
Short name T725
Test name
Test status
Simulation time 184590744 ps
CPU time 0.89 seconds
Started Jul 20 06:22:34 PM PDT 24
Finished Jul 20 06:22:35 PM PDT 24
Peak memory 206652 kb
Host smart-1f512db7-1b8f-4f54-8d9c-962f39a8a816
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41599
203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.41599203
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.552244391
Short name T2606
Test name
Test status
Simulation time 141633014 ps
CPU time 0.93 seconds
Started Jul 20 06:22:34 PM PDT 24
Finished Jul 20 06:22:36 PM PDT 24
Peak memory 206636 kb
Host smart-dd9b88f0-5e65-4519-9068-d1e2d3de2faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55224
4391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.552244391
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.494457263
Short name T2330
Test name
Test status
Simulation time 143193818 ps
CPU time 0.79 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:39 PM PDT 24
Peak memory 206656 kb
Host smart-8b4f9733-6e89-45c0-b490-a097804bd5aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49445
7263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.494457263
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.1628847543
Short name T991
Test name
Test status
Simulation time 240129172 ps
CPU time 0.94 seconds
Started Jul 20 06:22:39 PM PDT 24
Finished Jul 20 06:22:42 PM PDT 24
Peak memory 206656 kb
Host smart-487b4b32-2191-4b1f-aca7-4780449a4d4c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1628847543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.1628847543
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2510998014
Short name T2447
Test name
Test status
Simulation time 142142309 ps
CPU time 0.78 seconds
Started Jul 20 06:22:36 PM PDT 24
Finished Jul 20 06:22:39 PM PDT 24
Peak memory 206640 kb
Host smart-41dbff29-7bc3-4e74-975e-a572f2eec17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25109
98014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2510998014
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3410625498
Short name T1910
Test name
Test status
Simulation time 64846608 ps
CPU time 0.71 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:22:38 PM PDT 24
Peak memory 206652 kb
Host smart-cc449d04-9177-4f4f-8434-1305aecfbdcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34106
25498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3410625498
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.36091452
Short name T234
Test name
Test status
Simulation time 5854191112 ps
CPU time 14.26 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:53 PM PDT 24
Peak memory 206960 kb
Host smart-6704745d-11b1-40a2-9da6-ed1516d7a0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36091
452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.36091452
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.3896178458
Short name T860
Test name
Test status
Simulation time 173091201 ps
CPU time 0.85 seconds
Started Jul 20 06:22:38 PM PDT 24
Finished Jul 20 06:22:41 PM PDT 24
Peak memory 206656 kb
Host smart-97a58def-83b2-4c5d-aeef-8f69cde6edc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38961
78458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.3896178458
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.1578407375
Short name T986
Test name
Test status
Simulation time 238914472 ps
CPU time 0.9 seconds
Started Jul 20 06:22:34 PM PDT 24
Finished Jul 20 06:22:35 PM PDT 24
Peak memory 206636 kb
Host smart-59f1464e-8f07-439a-b21e-ccd2adbef8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15784
07375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.1578407375
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2090600018
Short name T1646
Test name
Test status
Simulation time 283477345 ps
CPU time 0.94 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206620 kb
Host smart-d63ad6bc-5703-49cb-b27c-44c888420ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20906
00018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2090600018
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1667606280
Short name T2671
Test name
Test status
Simulation time 153386611 ps
CPU time 0.81 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:22:38 PM PDT 24
Peak memory 206644 kb
Host smart-788c8400-2237-4825-8440-6348da6fcf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16676
06280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1667606280
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.2817309376
Short name T2082
Test name
Test status
Simulation time 193005395 ps
CPU time 0.83 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206620 kb
Host smart-4915c01a-ce2b-4f0d-b053-682831443d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28173
09376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.2817309376
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1595423306
Short name T635
Test name
Test status
Simulation time 150196317 ps
CPU time 0.81 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:22:37 PM PDT 24
Peak memory 206648 kb
Host smart-60fb7f6e-b1d9-4962-8272-d419cf438d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15954
23306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1595423306
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.3249060455
Short name T1725
Test name
Test status
Simulation time 258328014 ps
CPU time 1.01 seconds
Started Jul 20 06:22:34 PM PDT 24
Finished Jul 20 06:22:36 PM PDT 24
Peak memory 206648 kb
Host smart-4e782cb5-d109-4d74-ba80-e021d062c425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32490
60455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.3249060455
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3781290613
Short name T2669
Test name
Test status
Simulation time 3925365667 ps
CPU time 37.71 seconds
Started Jul 20 06:22:36 PM PDT 24
Finished Jul 20 06:23:16 PM PDT 24
Peak memory 206908 kb
Host smart-42665948-b57e-4380-ab44-b1c93dae694f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3781290613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3781290613
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.1582970563
Short name T2034
Test name
Test status
Simulation time 210207369 ps
CPU time 0.81 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:39 PM PDT 24
Peak memory 206648 kb
Host smart-dbe04973-8b45-4162-8173-19de6d4e322c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15829
70563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.1582970563
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.562952190
Short name T954
Test name
Test status
Simulation time 160080242 ps
CPU time 0.81 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206608 kb
Host smart-2cda4f76-959a-4e4c-a25b-53881aa536f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56295
2190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.562952190
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1513773134
Short name T545
Test name
Test status
Simulation time 916660175 ps
CPU time 2.11 seconds
Started Jul 20 06:22:39 PM PDT 24
Finished Jul 20 06:22:43 PM PDT 24
Peak memory 206784 kb
Host smart-3c99e179-fbe2-4f36-8cb5-bafbb48d5e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15137
73134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1513773134
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.797893391
Short name T762
Test name
Test status
Simulation time 4552832042 ps
CPU time 129.06 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206864 kb
Host smart-62330433-0e78-4891-89b9-6f74ec15528e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79789
3391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.797893391
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.2470190113
Short name T2632
Test name
Test status
Simulation time 62977296 ps
CPU time 0.7 seconds
Started Jul 20 06:22:47 PM PDT 24
Finished Jul 20 06:22:52 PM PDT 24
Peak memory 206700 kb
Host smart-d3cfbbae-58f7-48a3-9cae-1da892a25c4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2470190113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.2470190113
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.2410075513
Short name T2053
Test name
Test status
Simulation time 4031429344 ps
CPU time 4.56 seconds
Started Jul 20 06:22:36 PM PDT 24
Finished Jul 20 06:22:42 PM PDT 24
Peak memory 206720 kb
Host smart-8d57ac9d-7873-4030-865b-b1512d7a5cce
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2410075513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.2410075513
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.1183290135
Short name T2203
Test name
Test status
Simulation time 13479086611 ps
CPU time 12.41 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:57 PM PDT 24
Peak memory 206868 kb
Host smart-d9b7a808-202e-4c80-8a4e-1b30e6c5c5b6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1183290135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.1183290135
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.992813356
Short name T1724
Test name
Test status
Simulation time 23342039017 ps
CPU time 29.08 seconds
Started Jul 20 06:22:36 PM PDT 24
Finished Jul 20 06:23:07 PM PDT 24
Peak memory 206784 kb
Host smart-5ed7d3eb-13cf-4348-9f15-5b3a1e1be029
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=992813356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.992813356
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2598860452
Short name T2603
Test name
Test status
Simulation time 160626790 ps
CPU time 0.87 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:22:38 PM PDT 24
Peak memory 206588 kb
Host smart-f60fb48c-effe-4e35-bb34-81927f528c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25988
60452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2598860452
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.225445551
Short name T1925
Test name
Test status
Simulation time 142726478 ps
CPU time 0.77 seconds
Started Jul 20 06:22:39 PM PDT 24
Finished Jul 20 06:22:42 PM PDT 24
Peak memory 206660 kb
Host smart-8088f2b1-a58c-4b32-b5a0-7e77b9486294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22544
5551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.225445551
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.964395596
Short name T2387
Test name
Test status
Simulation time 378416116 ps
CPU time 1.2 seconds
Started Jul 20 06:22:34 PM PDT 24
Finished Jul 20 06:22:35 PM PDT 24
Peak memory 206628 kb
Host smart-42873fa5-a57b-4292-ba93-7f8256fad5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96439
5596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.964395596
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.568692254
Short name T2693
Test name
Test status
Simulation time 1113186653 ps
CPU time 2.48 seconds
Started Jul 20 06:22:39 PM PDT 24
Finished Jul 20 06:22:43 PM PDT 24
Peak memory 206652 kb
Host smart-c8414d15-39b9-422b-99be-49e3419f9944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56869
2254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.568692254
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1659360725
Short name T2277
Test name
Test status
Simulation time 13454982545 ps
CPU time 27.57 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:23:13 PM PDT 24
Peak memory 206792 kb
Host smart-68af84b6-609d-4bdc-a0a0-d032ed7d8793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16593
60725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1659360725
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.858329349
Short name T1973
Test name
Test status
Simulation time 496914329 ps
CPU time 1.42 seconds
Started Jul 20 06:22:39 PM PDT 24
Finished Jul 20 06:22:42 PM PDT 24
Peak memory 206648 kb
Host smart-caf3f619-5fe3-4d5f-bf27-7aa6b0d7000e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85832
9349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.858329349
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.1876119801
Short name T451
Test name
Test status
Simulation time 164744507 ps
CPU time 0.77 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:22:38 PM PDT 24
Peak memory 206656 kb
Host smart-e3807e98-2fdb-411c-b4f8-4bea8e8c63e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18761
19801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.1876119801
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.1184259773
Short name T2313
Test name
Test status
Simulation time 76896604 ps
CPU time 0.72 seconds
Started Jul 20 06:22:36 PM PDT 24
Finished Jul 20 06:22:39 PM PDT 24
Peak memory 206648 kb
Host smart-daa071c4-2499-4983-afbb-bd4066c94c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11842
59773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.1184259773
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.1446372699
Short name T1865
Test name
Test status
Simulation time 958817408 ps
CPU time 2.27 seconds
Started Jul 20 06:22:38 PM PDT 24
Finished Jul 20 06:22:43 PM PDT 24
Peak memory 206796 kb
Host smart-4890728e-73d4-4e37-8cb1-270ee10cbc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14463
72699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.1446372699
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3475257396
Short name T858
Test name
Test status
Simulation time 201443759 ps
CPU time 1.2 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206752 kb
Host smart-02d38393-f116-479f-87e0-e259486b1c63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34752
57396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3475257396
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.4141284496
Short name T1310
Test name
Test status
Simulation time 223654705 ps
CPU time 0.95 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206616 kb
Host smart-02a5d6e5-54a1-403f-83a7-4a5848dbbe80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41412
84496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.4141284496
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2531011241
Short name T2200
Test name
Test status
Simulation time 178031149 ps
CPU time 0.88 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:39 PM PDT 24
Peak memory 206644 kb
Host smart-64050645-63a2-4f0f-9eb5-e2b9828c98ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25310
11241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2531011241
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.987986225
Short name T1707
Test name
Test status
Simulation time 200001025 ps
CPU time 0.85 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206648 kb
Host smart-2eec0ee1-43ec-40e5-a4b0-2163746b8946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98798
6225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.987986225
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.1781679992
Short name T519
Test name
Test status
Simulation time 11921154811 ps
CPU time 106.3 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 207020 kb
Host smart-a750a99a-51f6-4bc4-8515-aebe43d61e43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17816
79992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.1781679992
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.3133161388
Short name T1610
Test name
Test status
Simulation time 192370392 ps
CPU time 0.84 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:22:37 PM PDT 24
Peak memory 206652 kb
Host smart-86c338a2-e241-4f0d-acc9-ca15cc580a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31331
61388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.3133161388
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.3424634750
Short name T2495
Test name
Test status
Simulation time 23322287839 ps
CPU time 28.95 seconds
Started Jul 20 06:22:38 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206776 kb
Host smart-8fd1c3fa-d9e8-481d-9ace-650f82060a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34246
34750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.3424634750
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.1041696440
Short name T921
Test name
Test status
Simulation time 3310480026 ps
CPU time 3.75 seconds
Started Jul 20 06:22:36 PM PDT 24
Finished Jul 20 06:22:42 PM PDT 24
Peak memory 206716 kb
Host smart-8fed89e9-ed48-4fb7-a2fe-e3c7d06d32aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10416
96440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.1041696440
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.669240878
Short name T1113
Test name
Test status
Simulation time 9069791113 ps
CPU time 71.38 seconds
Started Jul 20 06:22:39 PM PDT 24
Finished Jul 20 06:23:52 PM PDT 24
Peak memory 206852 kb
Host smart-e0c54ceb-076f-4dbd-9bf1-02cf059f6b52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66924
0878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.669240878
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1467041269
Short name T587
Test name
Test status
Simulation time 4268972653 ps
CPU time 121.16 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:24:38 PM PDT 24
Peak memory 206916 kb
Host smart-c1f0270a-66f1-4e95-8f09-0ffe9130c06f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1467041269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1467041269
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.3613004293
Short name T2411
Test name
Test status
Simulation time 286205677 ps
CPU time 1.01 seconds
Started Jul 20 06:22:37 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206652 kb
Host smart-c0f03953-7ef3-4986-b050-3ad4dab9d04e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3613004293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.3613004293
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.3023812989
Short name T2226
Test name
Test status
Simulation time 201442971 ps
CPU time 0.88 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:22:37 PM PDT 24
Peak memory 206656 kb
Host smart-bbdaee92-8474-40fd-a731-1f7a7d79c31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30238
12989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.3023812989
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.3249729907
Short name T756
Test name
Test status
Simulation time 5398123609 ps
CPU time 152.47 seconds
Started Jul 20 06:22:35 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206864 kb
Host smart-76215b83-0006-4647-bc78-5656f316414a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32497
29907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.3249729907
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.2592692348
Short name T886
Test name
Test status
Simulation time 4545390386 ps
CPU time 40.85 seconds
Started Jul 20 06:22:47 PM PDT 24
Finished Jul 20 06:23:31 PM PDT 24
Peak memory 206904 kb
Host smart-a611ce32-6254-4730-bdac-326e643f4983
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2592692348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.2592692348
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.2800872106
Short name T208
Test name
Test status
Simulation time 154387081 ps
CPU time 0.78 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:46 PM PDT 24
Peak memory 206652 kb
Host smart-da43f99b-2e5a-4299-8285-2c49e1e3a97f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2800872106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.2800872106
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2694072484
Short name T2725
Test name
Test status
Simulation time 153054415 ps
CPU time 0.76 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:49 PM PDT 24
Peak memory 206620 kb
Host smart-4d16932e-2ffc-4edc-b113-1ba114fb78d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26940
72484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2694072484
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.635472331
Short name T120
Test name
Test status
Simulation time 194450533 ps
CPU time 0.81 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206652 kb
Host smart-bbcf770e-2e3f-446f-bc32-c4eb1a6bb9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63547
2331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.635472331
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.1257447603
Short name T1899
Test name
Test status
Simulation time 206797635 ps
CPU time 0.85 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206644 kb
Host smart-3e82b22e-5616-4251-a47b-103b5fbf8455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12574
47603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.1257447603
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.586973755
Short name T1502
Test name
Test status
Simulation time 157159158 ps
CPU time 0.8 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206648 kb
Host smart-e1c24f88-3d3b-4ace-bf09-3f139f9a931e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58697
3755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.586973755
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2854276000
Short name T1845
Test name
Test status
Simulation time 143798166 ps
CPU time 0.8 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:48 PM PDT 24
Peak memory 206660 kb
Host smart-beaa0282-8130-4be2-af68-e417444e037d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28542
76000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2854276000
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3333198301
Short name T2132
Test name
Test status
Simulation time 176528156 ps
CPU time 0.81 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:22:46 PM PDT 24
Peak memory 206660 kb
Host smart-be31ddf7-63a6-43c0-81d1-7c562e765180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33331
98301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3333198301
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.331051691
Short name T2748
Test name
Test status
Simulation time 217551238 ps
CPU time 0.89 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:48 PM PDT 24
Peak memory 206660 kb
Host smart-58f6d0bd-6e7b-4b37-846d-85b3cc9cd8d8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=331051691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.331051691
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.4032703885
Short name T1442
Test name
Test status
Simulation time 140685062 ps
CPU time 0.78 seconds
Started Jul 20 06:22:41 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206624 kb
Host smart-ecba9d06-7712-4d9b-b462-b37c78681d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40327
03885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.4032703885
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.3405534033
Short name T930
Test name
Test status
Simulation time 81039743 ps
CPU time 0.71 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206624 kb
Host smart-c6a2c99e-9966-41d5-90c7-0dc369388741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34055
34033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.3405534033
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.692140236
Short name T1439
Test name
Test status
Simulation time 14058788995 ps
CPU time 28.98 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:23:13 PM PDT 24
Peak memory 215208 kb
Host smart-6e241812-e4cd-4969-b28e-a1f7d44afabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69214
0236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.692140236
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1073806820
Short name T2136
Test name
Test status
Simulation time 179297168 ps
CPU time 0.91 seconds
Started Jul 20 06:22:47 PM PDT 24
Finished Jul 20 06:22:51 PM PDT 24
Peak memory 206640 kb
Host smart-beb76948-cc72-4b70-97a4-ed024928b92c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10738
06820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1073806820
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.3882720979
Short name T2095
Test name
Test status
Simulation time 209050165 ps
CPU time 0.84 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:48 PM PDT 24
Peak memory 206648 kb
Host smart-23273f15-97bc-42c3-b739-e7894bfd2db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38827
20979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.3882720979
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.2287202658
Short name T859
Test name
Test status
Simulation time 235848127 ps
CPU time 0.88 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:22:48 PM PDT 24
Peak memory 206652 kb
Host smart-0f5c33c3-6346-4f00-bc14-2a4edb8651d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22872
02658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.2287202658
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.902461140
Short name T1062
Test name
Test status
Simulation time 241448827 ps
CPU time 0.91 seconds
Started Jul 20 06:22:51 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 206648 kb
Host smart-bc75b934-90b9-4fda-86b7-30bf2708d8bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90246
1140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.902461140
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1667583529
Short name T2506
Test name
Test status
Simulation time 177621767 ps
CPU time 0.82 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:22:47 PM PDT 24
Peak memory 206656 kb
Host smart-6e3d7336-3f26-4247-a8fb-da4bfbb02098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16675
83529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1667583529
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.768449034
Short name T1162
Test name
Test status
Simulation time 217351943 ps
CPU time 0.82 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:49 PM PDT 24
Peak memory 206632 kb
Host smart-afd697f4-9d1b-4bd2-94e4-cabbfc780669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76844
9034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.768449034
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.1582752391
Short name T2721
Test name
Test status
Simulation time 160133471 ps
CPU time 0.8 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:49 PM PDT 24
Peak memory 206644 kb
Host smart-6955f660-613c-477b-bac0-d994939284a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15827
52391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.1582752391
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.213182264
Short name T1177
Test name
Test status
Simulation time 226911349 ps
CPU time 0.97 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206656 kb
Host smart-b5aef617-7043-4e5f-adb3-3e0a7782683f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21318
2264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.213182264
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.596974208
Short name T1946
Test name
Test status
Simulation time 4993936019 ps
CPU time 35.25 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 206924 kb
Host smart-9375fb87-f190-45c7-bd83-945d2c4be407
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=596974208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.596974208
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.1868220306
Short name T1607
Test name
Test status
Simulation time 228964506 ps
CPU time 0.86 seconds
Started Jul 20 06:22:46 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206644 kb
Host smart-c3437f28-8bf1-461e-922c-8a637c7fedeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18682
20306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.1868220306
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3242739804
Short name T993
Test name
Test status
Simulation time 199102433 ps
CPU time 0.86 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:22:47 PM PDT 24
Peak memory 206660 kb
Host smart-e3f48f17-6899-4b8c-b070-1635ad4f8c13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32427
39804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3242739804
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.2896961751
Short name T2217
Test name
Test status
Simulation time 689704742 ps
CPU time 1.73 seconds
Started Jul 20 06:22:47 PM PDT 24
Finished Jul 20 06:22:52 PM PDT 24
Peak memory 206800 kb
Host smart-68022052-e8cd-463c-834d-1032378aabcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28969
61751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.2896961751
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.279389561
Short name T716
Test name
Test status
Simulation time 6331727104 ps
CPU time 178.56 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206840 kb
Host smart-bdf9f782-8bf1-4cbe-83c4-cf740dab8a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27938
9561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.279389561
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.3808050583
Short name T1226
Test name
Test status
Simulation time 102390112 ps
CPU time 0.75 seconds
Started Jul 20 06:22:55 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206672 kb
Host smart-593c2c88-cbd7-4e16-b827-55be2f69f772
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3808050583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.3808050583
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2263951484
Short name T1380
Test name
Test status
Simulation time 3732632124 ps
CPU time 4.68 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206692 kb
Host smart-a8b81515-9ea1-4313-8b4d-8224d5276540
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2263951484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2263951484
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.2566940095
Short name T1879
Test name
Test status
Simulation time 13302494189 ps
CPU time 13.38 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:23:00 PM PDT 24
Peak memory 206772 kb
Host smart-efceb43d-d38c-4d17-868c-423c7a4c14f2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2566940095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.2566940095
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2264215405
Short name T1468
Test name
Test status
Simulation time 23386692656 ps
CPU time 23.64 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:23:12 PM PDT 24
Peak memory 206744 kb
Host smart-1e088a4f-2f1c-4101-a009-6fa357db5ac7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2264215405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2264215405
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.2030712296
Short name T2362
Test name
Test status
Simulation time 179266932 ps
CPU time 0.85 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:22:47 PM PDT 24
Peak memory 206656 kb
Host smart-86a81839-77c0-4feb-9d51-d3c356648166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20307
12296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.2030712296
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.1358973957
Short name T1209
Test name
Test status
Simulation time 141634610 ps
CPU time 0.77 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:22:47 PM PDT 24
Peak memory 206644 kb
Host smart-7cc84f10-b3e5-4e09-a756-6a2fefc925b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13589
73957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.1358973957
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1225979858
Short name T2276
Test name
Test status
Simulation time 199703084 ps
CPU time 0.87 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:48 PM PDT 24
Peak memory 206660 kb
Host smart-859e8bc7-0364-4323-b051-eeb29fd26002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12259
79858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1225979858
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.1278822224
Short name T1512
Test name
Test status
Simulation time 1096825012 ps
CPU time 2.46 seconds
Started Jul 20 06:22:47 PM PDT 24
Finished Jul 20 06:22:53 PM PDT 24
Peak memory 206804 kb
Host smart-a8f9d01f-accb-42ac-844c-857f630364fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12788
22224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.1278822224
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.1014756062
Short name T1532
Test name
Test status
Simulation time 16467301785 ps
CPU time 31.25 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:23:20 PM PDT 24
Peak memory 206868 kb
Host smart-7f8ae7db-dc11-4143-8d97-f637122935dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10147
56062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.1014756062
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3456594919
Short name T2278
Test name
Test status
Simulation time 302345933 ps
CPU time 1.15 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:22:46 PM PDT 24
Peak memory 206644 kb
Host smart-44ddbbfc-0595-40e4-a49b-28a2ae432321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34565
94919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3456594919
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_enable.2477084898
Short name T426
Test name
Test status
Simulation time 40598890 ps
CPU time 0.66 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:49 PM PDT 24
Peak memory 206648 kb
Host smart-712026b7-d39b-498c-ac09-fd478adea90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24770
84898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2477084898
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.1828447927
Short name T2442
Test name
Test status
Simulation time 838705993 ps
CPU time 1.94 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:49 PM PDT 24
Peak memory 206752 kb
Host smart-f03e3cbb-6871-4165-9056-985d33396280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
47927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.1828447927
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.1442694357
Short name T692
Test name
Test status
Simulation time 169153908 ps
CPU time 1.67 seconds
Started Jul 20 06:22:51 PM PDT 24
Finished Jul 20 06:22:57 PM PDT 24
Peak memory 206792 kb
Host smart-57eb4bcb-bc4b-4810-9967-4b51ed8beb15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14426
94357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.1442694357
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.2704426644
Short name T878
Test name
Test status
Simulation time 167282815 ps
CPU time 0.88 seconds
Started Jul 20 06:22:42 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206640 kb
Host smart-744cae25-ca5a-48e4-b77a-183c46167788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27044
26644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.2704426644
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.3236886362
Short name T2540
Test name
Test status
Simulation time 143750262 ps
CPU time 0.76 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:49 PM PDT 24
Peak memory 206672 kb
Host smart-599597e5-1031-4458-b71a-ee6773da72b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32368
86362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.3236886362
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3213276093
Short name T367
Test name
Test status
Simulation time 250778068 ps
CPU time 0.94 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:55 PM PDT 24
Peak memory 206628 kb
Host smart-05e88263-0200-4242-a697-f873609ea698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32132
76093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3213276093
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.1485342425
Short name T821
Test name
Test status
Simulation time 191868534 ps
CPU time 0.84 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:48 PM PDT 24
Peak memory 206652 kb
Host smart-aa7dbbc1-502d-4291-946a-703e4bcb0266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14853
42425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.1485342425
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.3860495546
Short name T614
Test name
Test status
Simulation time 23341763069 ps
CPU time 28.43 seconds
Started Jul 20 06:22:43 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206776 kb
Host smart-4614f294-ca2e-4074-9306-2cd5fe4dcdd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38604
95546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.3860495546
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3368891354
Short name T1593
Test name
Test status
Simulation time 3360933120 ps
CPU time 3.88 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:22:53 PM PDT 24
Peak memory 206724 kb
Host smart-cc31c4fa-705b-4036-a367-cea0dc139e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33688
91354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3368891354
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.4036060665
Short name T1566
Test name
Test status
Simulation time 9241468183 ps
CPU time 259.05 seconds
Started Jul 20 06:22:47 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206916 kb
Host smart-ddaedac8-bf55-4a58-9cd0-5b425d354d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40360
60665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.4036060665
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.2603201606
Short name T782
Test name
Test status
Simulation time 6596864935 ps
CPU time 60.61 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206844 kb
Host smart-c8e73b8b-f090-46d5-8e91-6b7e01bb7351
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2603201606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.2603201606
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.661078091
Short name T1653
Test name
Test status
Simulation time 240788165 ps
CPU time 0.92 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206620 kb
Host smart-7d6283b8-8e1b-467b-be29-a50996850bf8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=661078091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.661078091
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2859121062
Short name T1738
Test name
Test status
Simulation time 196294636 ps
CPU time 0.83 seconds
Started Jul 20 06:22:51 PM PDT 24
Finished Jul 20 06:22:55 PM PDT 24
Peak memory 206648 kb
Host smart-2590ad37-eefe-450f-a9f3-6fb82ceae252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28591
21062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2859121062
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.4231620352
Short name T359
Test name
Test status
Simulation time 4869406465 ps
CPU time 135.13 seconds
Started Jul 20 06:22:45 PM PDT 24
Finished Jul 20 06:25:04 PM PDT 24
Peak memory 206892 kb
Host smart-b4fa9098-e932-4af3-9462-9268c8b18821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42316
20352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.4231620352
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.3846170477
Short name T1301
Test name
Test status
Simulation time 3080719135 ps
CPU time 88.39 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206836 kb
Host smart-d1db7b2f-729c-410a-bfc2-890cb96fae8e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3846170477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.3846170477
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.4153270330
Short name T347
Test name
Test status
Simulation time 198891360 ps
CPU time 0.81 seconds
Started Jul 20 06:22:52 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 206652 kb
Host smart-3752519c-e13e-41b0-979a-b45d6645d233
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4153270330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.4153270330
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.3682676836
Short name T491
Test name
Test status
Simulation time 202115066 ps
CPU time 0.83 seconds
Started Jul 20 06:22:53 PM PDT 24
Finished Jul 20 06:22:57 PM PDT 24
Peak memory 206648 kb
Host smart-bb234678-8b3e-475a-8632-26798e783246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36826
76836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.3682676836
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.2565845570
Short name T1111
Test name
Test status
Simulation time 154385699 ps
CPU time 0.78 seconds
Started Jul 20 06:22:44 PM PDT 24
Finished Jul 20 06:22:50 PM PDT 24
Peak memory 206640 kb
Host smart-8f1e9449-6c37-4bd9-a642-44a5c7c0d2d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
45570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.2565845570
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.2255847914
Short name T586
Test name
Test status
Simulation time 170389927 ps
CPU time 0.82 seconds
Started Jul 20 06:22:52 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 206652 kb
Host smart-cd79b235-154b-48c0-8027-067cc547b83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22558
47914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.2255847914
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.4213910261
Short name T1139
Test name
Test status
Simulation time 198541004 ps
CPU time 0.86 seconds
Started Jul 20 06:22:46 PM PDT 24
Finished Jul 20 06:22:51 PM PDT 24
Peak memory 206644 kb
Host smart-ec96f3cb-d741-4b41-a538-40a45b00f8da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42139
10261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.4213910261
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.2181019186
Short name T2125
Test name
Test status
Simulation time 155330319 ps
CPU time 0.78 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206648 kb
Host smart-1b3f8eaa-0a72-4e29-ad27-9fc350abbf73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21810
19186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.2181019186
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.2530750792
Short name T1016
Test name
Test status
Simulation time 197140298 ps
CPU time 0.89 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206660 kb
Host smart-0d97aba5-73ec-40f7-80e8-0c55a78809b4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2530750792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.2530750792
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1280073998
Short name T1677
Test name
Test status
Simulation time 140645378 ps
CPU time 0.76 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206644 kb
Host smart-e8e5cf21-2ee6-4271-b23b-6a0dd571fd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12800
73998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1280073998
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.935088095
Short name T1575
Test name
Test status
Simulation time 11592731749 ps
CPU time 27.42 seconds
Started Jul 20 06:22:53 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 206960 kb
Host smart-3f6c9af6-7e8e-4e71-98eb-069262c15861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93508
8095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.935088095
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.4290738265
Short name T766
Test name
Test status
Simulation time 190927138 ps
CPU time 0.82 seconds
Started Jul 20 06:22:53 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206656 kb
Host smart-a57e793a-90aa-4de5-9a44-b6913e65b854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42907
38265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.4290738265
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1499780804
Short name T406
Test name
Test status
Simulation time 178997404 ps
CPU time 0.86 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206640 kb
Host smart-d70150cd-05cb-48b7-a291-e99b64120242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14997
80804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1499780804
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3110730737
Short name T2292
Test name
Test status
Simulation time 227118503 ps
CPU time 0.92 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206640 kb
Host smart-1fb71a81-a2b9-4c08-8bc7-1ba39b9d3cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31107
30737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3110730737
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.2761249331
Short name T911
Test name
Test status
Simulation time 243407718 ps
CPU time 0.9 seconds
Started Jul 20 06:22:49 PM PDT 24
Finished Jul 20 06:22:53 PM PDT 24
Peak memory 206656 kb
Host smart-9c65cabb-fb0a-494a-9a91-ed0bdd309e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27612
49331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.2761249331
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.3719420998
Short name T1747
Test name
Test status
Simulation time 145778359 ps
CPU time 0.78 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:55 PM PDT 24
Peak memory 206632 kb
Host smart-8a683d7e-1e15-4ab6-b2d4-21f5763e772d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37194
20998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.3719420998
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.1467522142
Short name T621
Test name
Test status
Simulation time 150813722 ps
CPU time 0.81 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206648 kb
Host smart-f93e6b64-2361-4a9b-9c90-c781083b10ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14675
22142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.1467522142
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.1789005355
Short name T401
Test name
Test status
Simulation time 178590026 ps
CPU time 0.81 seconds
Started Jul 20 06:22:49 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206744 kb
Host smart-a845768c-a969-44be-bc62-6b5dc4c69c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17890
05355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.1789005355
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.833875623
Short name T852
Test name
Test status
Simulation time 218064294 ps
CPU time 0.88 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206644 kb
Host smart-576341aa-e1b9-46b1-b938-0aac331bbf15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83387
5623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.833875623
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.840130173
Short name T1479
Test name
Test status
Simulation time 191338699 ps
CPU time 0.84 seconds
Started Jul 20 06:22:51 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 206656 kb
Host smart-d61aa882-0875-499d-880f-98b086de345f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84013
0173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.840130173
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.2833813104
Short name T826
Test name
Test status
Simulation time 175557207 ps
CPU time 0.81 seconds
Started Jul 20 06:22:49 PM PDT 24
Finished Jul 20 06:22:53 PM PDT 24
Peak memory 206652 kb
Host smart-4af85954-30cf-4f58-917f-5be3bb8f290c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28338
13104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.2833813104
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.2816872479
Short name T1402
Test name
Test status
Simulation time 575946832 ps
CPU time 1.42 seconds
Started Jul 20 06:22:53 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206640 kb
Host smart-1e7b9111-b4fb-4a92-b99b-4ba0873da3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28168
72479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.2816872479
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.65736346
Short name T170
Test name
Test status
Simulation time 7533334708 ps
CPU time 72.78 seconds
Started Jul 20 06:22:51 PM PDT 24
Finished Jul 20 06:24:08 PM PDT 24
Peak memory 206904 kb
Host smart-a529156c-fb18-4482-b2c1-242127eada2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65736
346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.65736346
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.31937661
Short name T2489
Test name
Test status
Simulation time 41036571 ps
CPU time 0.67 seconds
Started Jul 20 06:19:08 PM PDT 24
Finished Jul 20 06:19:09 PM PDT 24
Peak memory 206716 kb
Host smart-c82aeca4-9e30-4c8a-ba8a-75a79b0b23d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=31937661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.31937661
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.467813741
Short name T675
Test name
Test status
Simulation time 4092630716 ps
CPU time 4.91 seconds
Started Jul 20 06:18:54 PM PDT 24
Finished Jul 20 06:18:59 PM PDT 24
Peak memory 206692 kb
Host smart-1ecebeea-fb83-4dc0-8383-9c1bebd350fa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=467813741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.467813741
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.3151290877
Short name T2517
Test name
Test status
Simulation time 13316024055 ps
CPU time 11.97 seconds
Started Jul 20 06:18:53 PM PDT 24
Finished Jul 20 06:19:06 PM PDT 24
Peak memory 206840 kb
Host smart-76955321-72f8-4a6b-b15b-fcb5ce5a6b3d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3151290877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.3151290877
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.3534035767
Short name T2553
Test name
Test status
Simulation time 23345109683 ps
CPU time 24.55 seconds
Started Jul 20 06:18:54 PM PDT 24
Finished Jul 20 06:19:19 PM PDT 24
Peak memory 206784 kb
Host smart-7d1df9d5-3e3d-4246-98d8-63bdbaa43d66
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3534035767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.3534035767
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.915440645
Short name T2127
Test name
Test status
Simulation time 215814250 ps
CPU time 0.9 seconds
Started Jul 20 06:18:52 PM PDT 24
Finished Jul 20 06:18:53 PM PDT 24
Peak memory 206656 kb
Host smart-03f1b01e-5488-42ee-885c-e3f086765233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91544
0645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.915440645
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2298061208
Short name T58
Test name
Test status
Simulation time 159897515 ps
CPU time 0.82 seconds
Started Jul 20 06:18:53 PM PDT 24
Finished Jul 20 06:18:54 PM PDT 24
Peak memory 206656 kb
Host smart-e3c6e6d1-53c1-4b55-862d-d90618953524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22980
61208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2298061208
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.2069348548
Short name T1006
Test name
Test status
Simulation time 148728316 ps
CPU time 0.81 seconds
Started Jul 20 06:18:53 PM PDT 24
Finished Jul 20 06:18:55 PM PDT 24
Peak memory 206660 kb
Host smart-de8c360d-5529-43ff-90e6-9a576b494958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693
48548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.2069348548
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.2168847151
Short name T67
Test name
Test status
Simulation time 310283483 ps
CPU time 1.11 seconds
Started Jul 20 06:18:52 PM PDT 24
Finished Jul 20 06:18:54 PM PDT 24
Peak memory 206648 kb
Host smart-e040de82-8172-4c7e-a8fb-2b36de6a1981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21688
47151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.2168847151
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3461738812
Short name T1735
Test name
Test status
Simulation time 580994619 ps
CPU time 1.6 seconds
Started Jul 20 06:18:49 PM PDT 24
Finished Jul 20 06:18:51 PM PDT 24
Peak memory 206664 kb
Host smart-537587a6-1bb0-4a80-bd07-d944f55aabca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34617
38812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3461738812
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.231265709
Short name T1458
Test name
Test status
Simulation time 10404527803 ps
CPU time 21.07 seconds
Started Jul 20 06:18:53 PM PDT 24
Finished Jul 20 06:19:15 PM PDT 24
Peak memory 206860 kb
Host smart-d9be43cc-792a-4bc1-8212-f50800b48059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23126
5709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.231265709
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.3247309532
Short name T597
Test name
Test status
Simulation time 448633031 ps
CPU time 1.3 seconds
Started Jul 20 06:18:52 PM PDT 24
Finished Jul 20 06:18:55 PM PDT 24
Peak memory 206644 kb
Host smart-f234f4ea-acea-4b99-b20a-b84cc1fdd813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32473
09532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.3247309532
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2183603101
Short name T1200
Test name
Test status
Simulation time 183142205 ps
CPU time 0.78 seconds
Started Jul 20 06:18:55 PM PDT 24
Finished Jul 20 06:18:57 PM PDT 24
Peak memory 206620 kb
Host smart-237e8e77-8692-40c8-8bb5-ba638ca08ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21836
03101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2183603101
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.741368995
Short name T1937
Test name
Test status
Simulation time 41667559 ps
CPU time 0.66 seconds
Started Jul 20 06:18:51 PM PDT 24
Finished Jul 20 06:18:52 PM PDT 24
Peak memory 206648 kb
Host smart-8632d0c5-aa54-4aee-8910-ee958f197dd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74136
8995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.741368995
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.3419789173
Short name T615
Test name
Test status
Simulation time 914052538 ps
CPU time 2.36 seconds
Started Jul 20 06:18:50 PM PDT 24
Finished Jul 20 06:18:53 PM PDT 24
Peak memory 206720 kb
Host smart-b917f173-475f-4369-b9f3-30e41d5aa0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34197
89173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.3419789173
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.3592594623
Short name T2485
Test name
Test status
Simulation time 189138371 ps
CPU time 1.48 seconds
Started Jul 20 06:18:52 PM PDT 24
Finished Jul 20 06:18:54 PM PDT 24
Peak memory 206748 kb
Host smart-574bf247-2884-4a3a-9d0a-3e40b3962449
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35925
94623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.3592594623
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.4140085182
Short name T941
Test name
Test status
Simulation time 94172425751 ps
CPU time 119.72 seconds
Started Jul 20 06:18:54 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206900 kb
Host smart-f80c7ab8-819c-4310-b406-a86d59e108c7
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4140085182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.4140085182
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1190232545
Short name T2169
Test name
Test status
Simulation time 93250149788 ps
CPU time 126.59 seconds
Started Jul 20 06:18:56 PM PDT 24
Finished Jul 20 06:21:03 PM PDT 24
Peak memory 206864 kb
Host smart-a52094e9-b779-4c06-a61e-02e671875fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190232545 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1190232545
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.254386219
Short name T1855
Test name
Test status
Simulation time 108092829506 ps
CPU time 140.02 seconds
Started Jul 20 06:18:54 PM PDT 24
Finished Jul 20 06:21:15 PM PDT 24
Peak memory 206876 kb
Host smart-75dda5ed-7d7e-4b5b-97a7-9ee67f6c982b
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=254386219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.254386219
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.2746915891
Short name T43
Test name
Test status
Simulation time 105203317777 ps
CPU time 158.91 seconds
Started Jul 20 06:18:53 PM PDT 24
Finished Jul 20 06:21:33 PM PDT 24
Peak memory 206872 kb
Host smart-370c5395-5399-4241-af32-ee5438f998ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746915891 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.2746915891
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.4205118988
Short name T1976
Test name
Test status
Simulation time 119207393576 ps
CPU time 153.5 seconds
Started Jul 20 06:19:04 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206924 kb
Host smart-d8b45048-b47d-4727-bf7d-48dbf5cac23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42051
18988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.4205118988
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.144038629
Short name T1333
Test name
Test status
Simulation time 209419974 ps
CPU time 0.9 seconds
Started Jul 20 06:19:03 PM PDT 24
Finished Jul 20 06:19:05 PM PDT 24
Peak memory 206640 kb
Host smart-f99562ec-cd4e-4ae1-9dd5-e161eed0cd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14403
8629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.144038629
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.2651137552
Short name T2535
Test name
Test status
Simulation time 162274759 ps
CPU time 0.8 seconds
Started Jul 20 06:19:04 PM PDT 24
Finished Jul 20 06:19:06 PM PDT 24
Peak memory 206652 kb
Host smart-5c031501-4ae6-4e2b-84f0-fcce3700be74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26511
37552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.2651137552
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.3120065951
Short name T1574
Test name
Test status
Simulation time 218016945 ps
CPU time 0.87 seconds
Started Jul 20 06:19:04 PM PDT 24
Finished Jul 20 06:19:05 PM PDT 24
Peak memory 206644 kb
Host smart-5b8d3149-ecca-4576-aa45-09ece36d752d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31200
65951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.3120065951
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.1017660547
Short name T1675
Test name
Test status
Simulation time 5620016501 ps
CPU time 19.22 seconds
Started Jul 20 06:19:06 PM PDT 24
Finished Jul 20 06:19:27 PM PDT 24
Peak memory 206928 kb
Host smart-fd9276b8-003e-4d2f-9c05-db56ceecc65e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10176
60547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.1017660547
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.4278564644
Short name T1474
Test name
Test status
Simulation time 178708582 ps
CPU time 0.78 seconds
Started Jul 20 06:19:04 PM PDT 24
Finished Jul 20 06:19:05 PM PDT 24
Peak memory 206636 kb
Host smart-bb21066d-8c7b-4799-89a1-9cc2e3925d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42785
64644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.4278564644
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1747388839
Short name T179
Test name
Test status
Simulation time 23316757386 ps
CPU time 25.25 seconds
Started Jul 20 06:19:04 PM PDT 24
Finished Jul 20 06:19:30 PM PDT 24
Peak memory 206752 kb
Host smart-d93750a8-5cb3-4b63-b063-a06fd91ee824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17473
88839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1747388839
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.643437445
Short name T41
Test name
Test status
Simulation time 3330852250 ps
CPU time 4.41 seconds
Started Jul 20 06:19:03 PM PDT 24
Finished Jul 20 06:19:08 PM PDT 24
Peak memory 206700 kb
Host smart-35372a7b-fa7e-4deb-9364-e1c337e250d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64343
7445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.643437445
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3152016082
Short name T915
Test name
Test status
Simulation time 6496208394 ps
CPU time 172.46 seconds
Started Jul 20 06:19:05 PM PDT 24
Finished Jul 20 06:21:58 PM PDT 24
Peak memory 206928 kb
Host smart-37ab1e38-8d7c-4906-aa25-f0ff8304b14b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31520
16082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3152016082
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3273107332
Short name T357
Test name
Test status
Simulation time 7476804417 ps
CPU time 55.16 seconds
Started Jul 20 06:19:06 PM PDT 24
Finished Jul 20 06:20:02 PM PDT 24
Peak memory 206900 kb
Host smart-a7f76c9a-079e-407b-86d0-968f3e5d7d60
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3273107332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3273107332
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.4281417350
Short name T2480
Test name
Test status
Simulation time 243147558 ps
CPU time 0.92 seconds
Started Jul 20 06:19:05 PM PDT 24
Finished Jul 20 06:19:07 PM PDT 24
Peak memory 206644 kb
Host smart-2e6a07c9-a583-4929-8cbd-127d1d164705
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4281417350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.4281417350
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.982322130
Short name T2652
Test name
Test status
Simulation time 232526482 ps
CPU time 0.91 seconds
Started Jul 20 06:19:06 PM PDT 24
Finished Jul 20 06:19:08 PM PDT 24
Peak memory 206652 kb
Host smart-a345d3ab-69df-40bd-ae49-f16379c2c490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98232
2130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.982322130
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.1712416744
Short name T2445
Test name
Test status
Simulation time 4435058029 ps
CPU time 123.65 seconds
Started Jul 20 06:19:05 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206860 kb
Host smart-e79b0608-828d-44de-aafa-1417b0017f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17124
16744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.1712416744
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.638145533
Short name T516
Test name
Test status
Simulation time 6286856810 ps
CPU time 166.76 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:21:57 PM PDT 24
Peak memory 206868 kb
Host smart-41ae354c-239c-4f1a-a4a1-bac941da5eae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=638145533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.638145533
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3842645836
Short name T1499
Test name
Test status
Simulation time 187182471 ps
CPU time 0.81 seconds
Started Jul 20 06:19:06 PM PDT 24
Finished Jul 20 06:19:08 PM PDT 24
Peak memory 206656 kb
Host smart-f5cf54da-ea5a-47be-9464-16905346754e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3842645836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3842645836
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.3743627390
Short name T862
Test name
Test status
Simulation time 145467211 ps
CPU time 0.77 seconds
Started Jul 20 06:19:03 PM PDT 24
Finished Jul 20 06:19:04 PM PDT 24
Peak memory 206636 kb
Host smart-42919f25-0c8b-4deb-97f8-8535557c990e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37436
27390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.3743627390
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3484674880
Short name T1709
Test name
Test status
Simulation time 195060561 ps
CPU time 0.85 seconds
Started Jul 20 06:19:06 PM PDT 24
Finished Jul 20 06:19:09 PM PDT 24
Peak memory 206652 kb
Host smart-9b86d688-eac3-44cf-9ca5-0ace3ad2630f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34846
74880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3484674880
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.3705700126
Short name T628
Test name
Test status
Simulation time 183288148 ps
CPU time 0.9 seconds
Started Jul 20 06:19:05 PM PDT 24
Finished Jul 20 06:19:07 PM PDT 24
Peak memory 206636 kb
Host smart-320be314-9ff5-4262-a1df-8743b975a646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37057
00126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.3705700126
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1987675953
Short name T1588
Test name
Test status
Simulation time 174306242 ps
CPU time 0.9 seconds
Started Jul 20 06:19:03 PM PDT 24
Finished Jul 20 06:19:05 PM PDT 24
Peak memory 206668 kb
Host smart-86a31a6d-0f89-4f92-b5f9-ef9c651b8e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19876
75953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1987675953
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.501669328
Short name T2645
Test name
Test status
Simulation time 183878307 ps
CPU time 0.88 seconds
Started Jul 20 06:19:05 PM PDT 24
Finished Jul 20 06:19:07 PM PDT 24
Peak memory 206644 kb
Host smart-1e95d34a-c93b-49f9-acfa-e823a4030f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50166
9328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.501669328
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1569436876
Short name T1112
Test name
Test status
Simulation time 173086398 ps
CPU time 0.82 seconds
Started Jul 20 06:19:05 PM PDT 24
Finished Jul 20 06:19:07 PM PDT 24
Peak memory 206664 kb
Host smart-b66514be-5d46-4dfb-be46-aa8e0b64dc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15694
36876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1569436876
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.4079848124
Short name T1913
Test name
Test status
Simulation time 306382739 ps
CPU time 1.06 seconds
Started Jul 20 06:19:07 PM PDT 24
Finished Jul 20 06:19:09 PM PDT 24
Peak memory 206656 kb
Host smart-1795da21-e260-41db-a2e9-03f8e7a0b356
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4079848124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.4079848124
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.549213450
Short name T193
Test name
Test status
Simulation time 224746990 ps
CPU time 0.96 seconds
Started Jul 20 06:19:05 PM PDT 24
Finished Jul 20 06:19:07 PM PDT 24
Peak memory 206636 kb
Host smart-aa0e63b7-9ec7-4b37-abd2-91177174ffcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54921
3450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.549213450
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.3084820884
Short name T2163
Test name
Test status
Simulation time 178114607 ps
CPU time 0.8 seconds
Started Jul 20 06:19:06 PM PDT 24
Finished Jul 20 06:19:08 PM PDT 24
Peak memory 206660 kb
Host smart-7c5c619c-6f1d-4fd6-a5a3-78a3f0575015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30848
20884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.3084820884
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.4280524733
Short name T2271
Test name
Test status
Simulation time 35925830 ps
CPU time 0.64 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:11 PM PDT 24
Peak memory 206632 kb
Host smart-6026b397-f10c-4582-bebd-6709c0328ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42805
24733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.4280524733
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.4117619797
Short name T1622
Test name
Test status
Simulation time 8136359872 ps
CPU time 19.08 seconds
Started Jul 20 06:19:10 PM PDT 24
Finished Jul 20 06:19:30 PM PDT 24
Peak memory 206880 kb
Host smart-7231f06b-13c5-4e30-a019-d336ec46b517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
19797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.4117619797
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.564883950
Short name T755
Test name
Test status
Simulation time 207070832 ps
CPU time 0.88 seconds
Started Jul 20 06:19:10 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206624 kb
Host smart-41576467-22ac-4305-b0f2-931705dca54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56488
3950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.564883950
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.2707978779
Short name T337
Test name
Test status
Simulation time 266190678 ps
CPU time 0.97 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206632 kb
Host smart-f5e5ef84-6649-41b3-bca3-a49cce7d7039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27079
78779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.2707978779
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.822565179
Short name T1609
Test name
Test status
Simulation time 4086412943 ps
CPU time 26.52 seconds
Started Jul 20 06:19:10 PM PDT 24
Finished Jul 20 06:19:38 PM PDT 24
Peak memory 206840 kb
Host smart-48763e8c-99da-4ef4-ade5-eb8ab3b83db5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=822565179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.822565179
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.3084319668
Short name T2254
Test name
Test status
Simulation time 8450250181 ps
CPU time 73.15 seconds
Started Jul 20 06:19:07 PM PDT 24
Finished Jul 20 06:20:21 PM PDT 24
Peak memory 206944 kb
Host smart-5029ff94-b2a1-4137-940f-99d456500a8f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3084319668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.3084319668
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.3383197194
Short name T2634
Test name
Test status
Simulation time 14421041004 ps
CPU time 95.78 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:20:50 PM PDT 24
Peak memory 206800 kb
Host smart-0307981c-7751-44a7-8f55-b1072a8f23dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3383197194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.3383197194
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.46858798
Short name T1054
Test name
Test status
Simulation time 199073387 ps
CPU time 0.87 seconds
Started Jul 20 06:19:12 PM PDT 24
Finished Jul 20 06:19:14 PM PDT 24
Peak memory 206632 kb
Host smart-71cdba99-6f3a-4eaf-a9e2-16d671951349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46858
798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.46858798
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.2590389184
Short name T2139
Test name
Test status
Simulation time 166395275 ps
CPU time 0.79 seconds
Started Jul 20 06:19:10 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206648 kb
Host smart-5aa3577c-29eb-4ee0-bfb6-24531e1cbc0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25903
89184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.2590389184
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.1588446362
Short name T2363
Test name
Test status
Simulation time 147755721 ps
CPU time 0.71 seconds
Started Jul 20 06:19:11 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206648 kb
Host smart-71b59186-2f9a-403b-97a0-bccd805ae733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15884
46362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.1588446362
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2913515326
Short name T80
Test name
Test status
Simulation time 168825740 ps
CPU time 0.79 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:11 PM PDT 24
Peak memory 206656 kb
Host smart-3de15242-01d5-492a-8dab-e6e1587fbf12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29135
15326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2913515326
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.3731990961
Short name T186
Test name
Test status
Simulation time 419725834 ps
CPU time 1.24 seconds
Started Jul 20 06:19:12 PM PDT 24
Finished Jul 20 06:19:14 PM PDT 24
Peak memory 224396 kb
Host smart-83f7a902-b2c2-46a1-926b-762471167e2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3731990961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.3731990961
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.725925381
Short name T60
Test name
Test status
Simulation time 400876625 ps
CPU time 1.24 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:11 PM PDT 24
Peak memory 206640 kb
Host smart-35134291-9721-432e-a34b-a3ef000ea6b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72592
5381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.725925381
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2992996045
Short name T161
Test name
Test status
Simulation time 169598558 ps
CPU time 0.82 seconds
Started Jul 20 06:19:07 PM PDT 24
Finished Jul 20 06:19:09 PM PDT 24
Peak memory 206632 kb
Host smart-8e42128b-0a7f-4442-9a70-e2a6ef82cb3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29929
96045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2992996045
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.1442762423
Short name T2104
Test name
Test status
Simulation time 161907206 ps
CPU time 0.77 seconds
Started Jul 20 06:19:10 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206648 kb
Host smart-c244bb70-3563-4e44-877a-98dbfc22d9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14427
62423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.1442762423
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.3368302156
Short name T354
Test name
Test status
Simulation time 164913572 ps
CPU time 0.82 seconds
Started Jul 20 06:19:12 PM PDT 24
Finished Jul 20 06:19:14 PM PDT 24
Peak memory 206468 kb
Host smart-a9f7f1af-689d-4ff6-859a-51ebfd8168f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33683
02156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.3368302156
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.4275823799
Short name T2500
Test name
Test status
Simulation time 260598436 ps
CPU time 0.94 seconds
Started Jul 20 06:19:10 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206660 kb
Host smart-5748f34e-d4c7-4b77-981f-6aff1504ba47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42758
23799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.4275823799
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.2028857860
Short name T2308
Test name
Test status
Simulation time 4542915923 ps
CPU time 43.98 seconds
Started Jul 20 06:19:11 PM PDT 24
Finished Jul 20 06:19:57 PM PDT 24
Peak memory 206920 kb
Host smart-29e5ea8a-ba35-471a-9a64-8f80bfb33633
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2028857860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.2028857860
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1948286253
Short name T1563
Test name
Test status
Simulation time 157688034 ps
CPU time 0.77 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:19:15 PM PDT 24
Peak memory 206592 kb
Host smart-35013186-40ae-4905-879b-d700638eeead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19482
86253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1948286253
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.19163932
Short name T2610
Test name
Test status
Simulation time 169076425 ps
CPU time 0.8 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:19:15 PM PDT 24
Peak memory 206640 kb
Host smart-68f0bea7-673b-4269-a77b-400812a271f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19163
932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.19163932
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1465261752
Short name T1410
Test name
Test status
Simulation time 546472304 ps
CPU time 1.48 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:12 PM PDT 24
Peak memory 206632 kb
Host smart-38eb46aa-67b6-4956-83df-687bddd8b012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14652
61752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1465261752
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.191099042
Short name T1467
Test name
Test status
Simulation time 4873528810 ps
CPU time 46.47 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:56 PM PDT 24
Peak memory 206908 kb
Host smart-168533c7-7070-495e-becf-6502e268c4dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19109
9042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.191099042
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.4011274218
Short name T2000
Test name
Test status
Simulation time 11888508606 ps
CPU time 59.47 seconds
Started Jul 20 06:19:10 PM PDT 24
Finished Jul 20 06:20:11 PM PDT 24
Peak memory 206984 kb
Host smart-7da5c224-876d-41a1-9122-91bedbbcead9
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4011274218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.4011274218
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.1994162714
Short name T1392
Test name
Test status
Simulation time 74249121 ps
CPU time 0.7 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206692 kb
Host smart-2fba6dd7-54ac-4bee-b700-ea0a3bc5483e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1994162714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.1994162714
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.2920844213
Short name T476
Test name
Test status
Simulation time 4187473902 ps
CPU time 5.47 seconds
Started Jul 20 06:22:49 PM PDT 24
Finished Jul 20 06:22:57 PM PDT 24
Peak memory 206812 kb
Host smart-7fdf5609-53aa-4d92-b6c4-0f2c2c428c59
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2920844213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.2920844213
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.2849384157
Short name T195
Test name
Test status
Simulation time 13375369147 ps
CPU time 16.52 seconds
Started Jul 20 06:22:56 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206784 kb
Host smart-50fe8575-f9e5-4c4d-9799-a0b2d458166c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2849384157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.2849384157
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.2761949604
Short name T511
Test name
Test status
Simulation time 23336416619 ps
CPU time 23.72 seconds
Started Jul 20 06:22:51 PM PDT 24
Finished Jul 20 06:23:18 PM PDT 24
Peak memory 206784 kb
Host smart-d9942f50-a2cf-48fd-8a92-adbc72d70773
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2761949604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.2761949604
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1169465529
Short name T2676
Test name
Test status
Simulation time 192621828 ps
CPU time 0.89 seconds
Started Jul 20 06:22:55 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206652 kb
Host smart-cb5f8cda-bdf8-403f-9e45-50ff97d6219a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11694
65529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1169465529
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.150632693
Short name T1095
Test name
Test status
Simulation time 184246453 ps
CPU time 0.9 seconds
Started Jul 20 06:22:48 PM PDT 24
Finished Jul 20 06:22:52 PM PDT 24
Peak memory 206672 kb
Host smart-51b9807c-36bc-4415-9298-d0b13671ae25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15063
2693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.150632693
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2615485447
Short name T1650
Test name
Test status
Simulation time 529116553 ps
CPU time 1.56 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206788 kb
Host smart-271682c7-abb3-4375-9d83-1f44ab63b698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26154
85447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2615485447
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.3726389453
Short name T366
Test name
Test status
Simulation time 1085739152 ps
CPU time 2.53 seconds
Started Jul 20 06:22:52 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206736 kb
Host smart-3afc7ce0-9a5a-4b1a-93dd-55f6f1fcd18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37263
89453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.3726389453
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.2624300452
Short name T1680
Test name
Test status
Simulation time 8620296882 ps
CPU time 17.27 seconds
Started Jul 20 06:22:53 PM PDT 24
Finished Jul 20 06:23:14 PM PDT 24
Peak memory 206904 kb
Host smart-8cf6bdb8-c617-466c-8826-5babe2bda26c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26243
00452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.2624300452
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.1154192759
Short name T377
Test name
Test status
Simulation time 334857432 ps
CPU time 1.24 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206700 kb
Host smart-b38e5cf0-8506-4e19-b5f7-cad2daa26483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11541
92759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.1154192759
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.2876789136
Short name T1241
Test name
Test status
Simulation time 142921694 ps
CPU time 0.81 seconds
Started Jul 20 06:22:49 PM PDT 24
Finished Jul 20 06:22:53 PM PDT 24
Peak memory 206640 kb
Host smart-4cb6176d-fae4-486c-bfb3-e803e8fa0763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28767
89136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.2876789136
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.550143120
Short name T1326
Test name
Test status
Simulation time 40526905 ps
CPU time 0.67 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206628 kb
Host smart-bddba02a-3dea-47ad-ac91-2c6770c278cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55014
3120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.550143120
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3074628422
Short name T1130
Test name
Test status
Simulation time 1047914794 ps
CPU time 2.22 seconds
Started Jul 20 06:22:52 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206744 kb
Host smart-d2c36c30-840b-42b5-b7ce-936a08fdf2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
28422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3074628422
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.3050479201
Short name T2030
Test name
Test status
Simulation time 197025224 ps
CPU time 1.33 seconds
Started Jul 20 06:22:49 PM PDT 24
Finished Jul 20 06:22:53 PM PDT 24
Peak memory 206720 kb
Host smart-57f92224-9abf-43de-a31f-81e98e9cea6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30504
79201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.3050479201
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1473683517
Short name T801
Test name
Test status
Simulation time 215928057 ps
CPU time 0.84 seconds
Started Jul 20 06:22:53 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206636 kb
Host smart-38abcdd6-e0f6-464c-94cc-f5328aff3aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14736
83517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1473683517
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1919626186
Short name T478
Test name
Test status
Simulation time 161134297 ps
CPU time 0.81 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206696 kb
Host smart-189ee987-38b1-4bb0-bebf-59db2f5ccc1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19196
26186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1919626186
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.915421028
Short name T2124
Test name
Test status
Simulation time 251610870 ps
CPU time 0.92 seconds
Started Jul 20 06:22:52 PM PDT 24
Finished Jul 20 06:22:56 PM PDT 24
Peak memory 206644 kb
Host smart-3002427a-2f5c-4ca4-be9c-fbb3d372bfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91542
1028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.915421028
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.2330783204
Short name T1894
Test name
Test status
Simulation time 8278287348 ps
CPU time 69.39 seconds
Started Jul 20 06:22:55 PM PDT 24
Finished Jul 20 06:24:07 PM PDT 24
Peak memory 206816 kb
Host smart-f10f51c3-de87-4e04-bff3-8abacd5478ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23307
83204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.2330783204
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.3195046686
Short name T110
Test name
Test status
Simulation time 237158908 ps
CPU time 0.88 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206700 kb
Host smart-6c8fbc36-71de-4d11-b732-9897c7a8ff64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31950
46686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.3195046686
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.3361239947
Short name T595
Test name
Test status
Simulation time 23268222228 ps
CPU time 24.8 seconds
Started Jul 20 06:22:52 PM PDT 24
Finished Jul 20 06:23:21 PM PDT 24
Peak memory 206668 kb
Host smart-7293edd7-0f58-4c74-93f3-a1f5c6065e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33612
39947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.3361239947
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.2125919940
Short name T728
Test name
Test status
Simulation time 3296080406 ps
CPU time 4.03 seconds
Started Jul 20 06:22:50 PM PDT 24
Finished Jul 20 06:22:58 PM PDT 24
Peak memory 206720 kb
Host smart-bf355487-c442-4833-98fa-b823cc59a99a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21259
19940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.2125919940
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.46237448
Short name T416
Test name
Test status
Simulation time 9114675514 ps
CPU time 80 seconds
Started Jul 20 06:22:54 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206928 kb
Host smart-410d5e53-0e1e-4e64-90dc-d9526b558022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46237
448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.46237448
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.2959720514
Short name T1252
Test name
Test status
Simulation time 5712414474 ps
CPU time 41.64 seconds
Started Jul 20 06:22:52 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206816 kb
Host smart-0ef45c43-6de7-4b40-8136-d407828723c2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2959720514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.2959720514
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.324242850
Short name T2413
Test name
Test status
Simulation time 283325793 ps
CPU time 0.96 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206640 kb
Host smart-b4fb406b-bc15-446c-88fb-3387567fe87a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=324242850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.324242850
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2414395851
Short name T358
Test name
Test status
Simulation time 225063336 ps
CPU time 0.88 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206588 kb
Host smart-22b51062-0d9b-41c9-9509-7af8dc6efa06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24143
95851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2414395851
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3292545658
Short name T949
Test name
Test status
Simulation time 4980044896 ps
CPU time 35.91 seconds
Started Jul 20 06:22:57 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206860 kb
Host smart-a9f663c8-cbfe-4262-acac-8ceb60ae1743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32925
45658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3292545658
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1428944157
Short name T1460
Test name
Test status
Simulation time 5970145016 ps
CPU time 165.55 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:25:45 PM PDT 24
Peak memory 206848 kb
Host smart-29d6295f-7314-4813-a024-97b5ad02c9cf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1428944157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1428944157
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.383436053
Short name T1949
Test name
Test status
Simulation time 153096915 ps
CPU time 0.76 seconds
Started Jul 20 06:22:57 PM PDT 24
Finished Jul 20 06:22:59 PM PDT 24
Peak memory 206664 kb
Host smart-c1b76bac-d68e-4a54-b77e-80ac1341b553
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=383436053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.383436053
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.771724944
Short name T2274
Test name
Test status
Simulation time 187167599 ps
CPU time 0.77 seconds
Started Jul 20 06:22:57 PM PDT 24
Finished Jul 20 06:23:00 PM PDT 24
Peak memory 206640 kb
Host smart-b96c9a28-b5b8-43b2-b013-e53a4bb22fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77172
4944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.771724944
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.1972262674
Short name T1227
Test name
Test status
Simulation time 177703716 ps
CPU time 0.92 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206652 kb
Host smart-f64f569d-50ff-4f3d-be43-5ab0411a4662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19722
62674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.1972262674
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.1151145325
Short name T436
Test name
Test status
Simulation time 182105287 ps
CPU time 0.89 seconds
Started Jul 20 06:23:03 PM PDT 24
Finished Jul 20 06:23:05 PM PDT 24
Peak memory 206080 kb
Host smart-2e786cd8-d06a-42c3-a2da-b58d5d487796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11511
45325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.1151145325
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.205081818
Short name T2647
Test name
Test status
Simulation time 175327744 ps
CPU time 0.82 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206648 kb
Host smart-39d416ef-3c8b-4953-9644-f3f91ee313e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20508
1818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.205081818
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.237627231
Short name T2038
Test name
Test status
Simulation time 195918057 ps
CPU time 0.81 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206640 kb
Host smart-014c4fe6-fed9-4316-8229-85423ec79539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23762
7231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.237627231
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.567813118
Short name T456
Test name
Test status
Simulation time 227279081 ps
CPU time 1.01 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206652 kb
Host smart-07f99076-8dd7-4622-80d4-dfd958d46e48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=567813118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.567813118
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.814641958
Short name T1473
Test name
Test status
Simulation time 144439006 ps
CPU time 0.74 seconds
Started Jul 20 06:23:04 PM PDT 24
Finished Jul 20 06:23:05 PM PDT 24
Peak memory 206652 kb
Host smart-07f91102-0433-45b9-a67d-7652aa21b407
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81464
1958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.814641958
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1015219128
Short name T1212
Test name
Test status
Simulation time 69982426 ps
CPU time 0.69 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206624 kb
Host smart-70e7eb7f-fa38-4d65-8371-1f02c7de7284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10152
19128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1015219128
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1051491599
Short name T1194
Test name
Test status
Simulation time 15753008918 ps
CPU time 33.67 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206912 kb
Host smart-6a4259b4-955d-4138-9fac-9b0d5d801ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10514
91599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1051491599
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.3377288169
Short name T2014
Test name
Test status
Simulation time 175245747 ps
CPU time 0.82 seconds
Started Jul 20 06:23:03 PM PDT 24
Finished Jul 20 06:23:04 PM PDT 24
Peak memory 206672 kb
Host smart-c5c40ee2-8286-4587-b54c-4cdb81f6ca33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33772
88169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.3377288169
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.140973275
Short name T1372
Test name
Test status
Simulation time 201618685 ps
CPU time 0.87 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206656 kb
Host smart-7f548c2d-7a5a-4fab-a15c-9435aaff571e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14097
3275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.140973275
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3378392001
Short name T1275
Test name
Test status
Simulation time 184615737 ps
CPU time 0.86 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206656 kb
Host smart-85cf0950-e966-42c0-918a-1ab5734302a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33783
92001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3378392001
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.2161675282
Short name T2653
Test name
Test status
Simulation time 170811437 ps
CPU time 0.8 seconds
Started Jul 20 06:23:01 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206632 kb
Host smart-56ae7587-3220-45e9-b403-cf976c002064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21616
75282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.2161675282
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.4116674170
Short name T1137
Test name
Test status
Simulation time 142240727 ps
CPU time 0.81 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206640 kb
Host smart-eab1f0cf-d783-4cba-b531-a42f0a65aba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41166
74170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.4116674170
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.3354717135
Short name T153
Test name
Test status
Simulation time 148145589 ps
CPU time 0.81 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:00 PM PDT 24
Peak memory 206648 kb
Host smart-2174729b-c510-4695-86c4-4f9bf04420e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33547
17135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.3354717135
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1799905070
Short name T942
Test name
Test status
Simulation time 150197941 ps
CPU time 0.75 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206652 kb
Host smart-fdac9dc1-402f-4a63-8630-c01f004fe675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17999
05070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1799905070
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1309522124
Short name T346
Test name
Test status
Simulation time 186851096 ps
CPU time 0.83 seconds
Started Jul 20 06:23:03 PM PDT 24
Finished Jul 20 06:23:04 PM PDT 24
Peak memory 206648 kb
Host smart-e2b64ab9-d707-4a19-b910-a8ce79ec3c1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
22124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1309522124
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.2839656179
Short name T2617
Test name
Test status
Simulation time 3451906096 ps
CPU time 25.12 seconds
Started Jul 20 06:23:01 PM PDT 24
Finished Jul 20 06:23:27 PM PDT 24
Peak memory 206932 kb
Host smart-af3d8554-9cbf-4b9f-bc43-edde8a0f402a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2839656179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.2839656179
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.2963609060
Short name T1884
Test name
Test status
Simulation time 198430493 ps
CPU time 0.88 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206632 kb
Host smart-8442724a-76cc-42ee-ba2e-e76b57885fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29636
09060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.2963609060
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1177644771
Short name T1598
Test name
Test status
Simulation time 192621423 ps
CPU time 0.9 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206652 kb
Host smart-9555f949-4562-447e-8cdd-c5d884db6ec9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
44771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1177644771
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2167019984
Short name T1038
Test name
Test status
Simulation time 1052021854 ps
CPU time 2.34 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206768 kb
Host smart-a2b12469-85df-4744-853b-0cfbc2675925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21670
19984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2167019984
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.1519327654
Short name T630
Test name
Test status
Simulation time 4505491366 ps
CPU time 42.81 seconds
Started Jul 20 06:23:03 PM PDT 24
Finished Jul 20 06:23:47 PM PDT 24
Peak memory 206928 kb
Host smart-87b0d834-cbc4-4292-be26-25620569575e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15193
27654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.1519327654
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.3397353693
Short name T1278
Test name
Test status
Simulation time 3563473141 ps
CPU time 4.24 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:06 PM PDT 24
Peak memory 206720 kb
Host smart-d96abb7f-4070-4843-9e46-12cee315a901
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3397353693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.3397353693
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.1636238314
Short name T2063
Test name
Test status
Simulation time 13467783255 ps
CPU time 14.35 seconds
Started Jul 20 06:23:03 PM PDT 24
Finished Jul 20 06:23:19 PM PDT 24
Peak memory 206460 kb
Host smart-cf24c589-8da9-44f0-89b0-9734b12b4120
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1636238314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.1636238314
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.1351083129
Short name T12
Test name
Test status
Simulation time 23417004140 ps
CPU time 26.22 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:28 PM PDT 24
Peak memory 206776 kb
Host smart-1f5f33fc-65c3-4c7c-8835-34bb12c3a9db
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1351083129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.1351083129
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1980595871
Short name T2680
Test name
Test status
Simulation time 147595703 ps
CPU time 0.76 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206652 kb
Host smart-77f5fe3c-8508-4fb1-86e5-9de82b9ae231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19805
95871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1980595871
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.2242873825
Short name T687
Test name
Test status
Simulation time 165378100 ps
CPU time 0.82 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206656 kb
Host smart-6791c4ac-46bf-4715-a143-9e4ed2002eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22428
73825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.2242873825
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.978959613
Short name T1079
Test name
Test status
Simulation time 343624588 ps
CPU time 1.25 seconds
Started Jul 20 06:22:59 PM PDT 24
Finished Jul 20 06:23:02 PM PDT 24
Peak memory 206652 kb
Host smart-f11ae07e-c727-482f-96ad-df72f491f525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97895
9613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.978959613
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.521174153
Short name T2142
Test name
Test status
Simulation time 727671312 ps
CPU time 1.93 seconds
Started Jul 20 06:23:02 PM PDT 24
Finished Jul 20 06:23:05 PM PDT 24
Peak memory 206816 kb
Host smart-c80e71c0-1745-4473-a7af-09a567728130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52117
4153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.521174153
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3795735907
Short name T1143
Test name
Test status
Simulation time 15464178487 ps
CPU time 29.5 seconds
Started Jul 20 06:23:00 PM PDT 24
Finished Jul 20 06:23:32 PM PDT 24
Peak memory 206844 kb
Host smart-115a801e-9144-4da9-a07d-9af142e20636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37957
35907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3795735907
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.996255079
Short name T1971
Test name
Test status
Simulation time 456043692 ps
CPU time 1.3 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:01 PM PDT 24
Peak memory 206652 kb
Host smart-155ddf65-f116-4e4c-8d0f-8cbeea188a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99625
5079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.996255079
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.4223377136
Short name T817
Test name
Test status
Simulation time 146217869 ps
CPU time 0.79 seconds
Started Jul 20 06:22:58 PM PDT 24
Finished Jul 20 06:23:00 PM PDT 24
Peak memory 206652 kb
Host smart-7c354228-eb34-4aa6-a8f6-bd0b8760809f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
77136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.4223377136
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2677600598
Short name T2672
Test name
Test status
Simulation time 41878302 ps
CPU time 0.66 seconds
Started Jul 20 06:23:04 PM PDT 24
Finished Jul 20 06:23:05 PM PDT 24
Peak memory 206624 kb
Host smart-ee98b7ae-4f40-47ee-8279-bb13f93db5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26776
00598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2677600598
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3605971288
Short name T1049
Test name
Test status
Simulation time 935494316 ps
CPU time 2.24 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206800 kb
Host smart-fcba3b02-0899-45e3-88da-6ae81893f81e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36059
71288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3605971288
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.321146907
Short name T32
Test name
Test status
Simulation time 182624704 ps
CPU time 1.51 seconds
Started Jul 20 06:23:07 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206728 kb
Host smart-b72bc573-f161-4e65-b270-a548a99b4834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32114
6907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.321146907
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.3051002521
Short name T1708
Test name
Test status
Simulation time 206115128 ps
CPU time 0.91 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206644 kb
Host smart-2f18ac8d-8e12-468a-af57-a5685647e699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30510
02521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.3051002521
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.2206414316
Short name T2376
Test name
Test status
Simulation time 165079043 ps
CPU time 0.8 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206656 kb
Host smart-de04bdbe-74ac-4a96-bd66-6161ccacc226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22064
14316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.2206414316
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.2383643244
Short name T2188
Test name
Test status
Simulation time 195708120 ps
CPU time 0.87 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206660 kb
Host smart-600233b0-a85d-4109-8c75-6eb93fdc958e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23836
43244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.2383643244
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.1890961749
Short name T2130
Test name
Test status
Simulation time 10549982542 ps
CPU time 296.83 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:28:04 PM PDT 24
Peak memory 206996 kb
Host smart-a243d97f-7c7b-4a21-b80e-79522ff23ff1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1890961749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.1890961749
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.2512193647
Short name T1891
Test name
Test status
Simulation time 5803027715 ps
CPU time 17.96 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:27 PM PDT 24
Peak memory 206852 kb
Host smart-e5ed52d3-524b-4d20-ad16-bd81857e7df2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25121
93647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.2512193647
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.935201099
Short name T1657
Test name
Test status
Simulation time 239571727 ps
CPU time 0.89 seconds
Started Jul 20 06:23:11 PM PDT 24
Finished Jul 20 06:23:12 PM PDT 24
Peak memory 206652 kb
Host smart-d5c7d03a-e34f-4c2a-8215-f5be9c4ea9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93520
1099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.935201099
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2862771824
Short name T2477
Test name
Test status
Simulation time 23326727237 ps
CPU time 29.83 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206756 kb
Host smart-755cafe4-03d3-4c0e-af73-7a47bbaa2e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28627
71824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2862771824
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.991898661
Short name T1057
Test name
Test status
Simulation time 3325425747 ps
CPU time 3.71 seconds
Started Jul 20 06:23:07 PM PDT 24
Finished Jul 20 06:23:12 PM PDT 24
Peak memory 206724 kb
Host smart-9d93e2a3-f121-4184-a2b5-6167c06b031a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99189
8661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.991898661
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.123978809
Short name T1918
Test name
Test status
Simulation time 7907405179 ps
CPU time 213 seconds
Started Jul 20 06:23:05 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206916 kb
Host smart-c844ec23-7eae-49e4-a969-627f0a4ad46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
8809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.123978809
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.1110342586
Short name T1591
Test name
Test status
Simulation time 4176783184 ps
CPU time 40.61 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:48 PM PDT 24
Peak memory 206840 kb
Host smart-819a8b7e-f779-42c5-a265-91d5d80a9139
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1110342586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.1110342586
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.3792190301
Short name T1885
Test name
Test status
Simulation time 228949335 ps
CPU time 0.96 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206652 kb
Host smart-3d1c14cf-0beb-4a94-9faf-b68e876e41d2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3792190301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.3792190301
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1703521848
Short name T85
Test name
Test status
Simulation time 276464947 ps
CPU time 0.92 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:07 PM PDT 24
Peak memory 206628 kb
Host smart-926867a8-576d-421f-9cc1-d0678f82de09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17035
21848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1703521848
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.198697980
Short name T1019
Test name
Test status
Simulation time 3590530806 ps
CPU time 34.71 seconds
Started Jul 20 06:23:11 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 206872 kb
Host smart-4a65fcff-632c-4234-ae0c-eb213193c9eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19869
7980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.198697980
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1149736058
Short name T1337
Test name
Test status
Simulation time 5108993343 ps
CPU time 44.29 seconds
Started Jul 20 06:23:07 PM PDT 24
Finished Jul 20 06:23:52 PM PDT 24
Peak memory 206864 kb
Host smart-2365e492-5244-4577-bf76-22bc5e77fd23
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1149736058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1149736058
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3176800759
Short name T1034
Test name
Test status
Simulation time 209169465 ps
CPU time 0.83 seconds
Started Jul 20 06:23:07 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206676 kb
Host smart-654efdce-b955-41c7-9d60-ccf2591c5183
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3176800759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3176800759
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.4293616657
Short name T2496
Test name
Test status
Simulation time 160981360 ps
CPU time 0.82 seconds
Started Jul 20 06:23:07 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206668 kb
Host smart-3d627614-641b-472c-91ab-14183d009357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42936
16657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.4293616657
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.2909593853
Short name T132
Test name
Test status
Simulation time 263651286 ps
CPU time 0.93 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:08 PM PDT 24
Peak memory 206652 kb
Host smart-fa88d44d-69c4-47c6-927f-44dfbfffe3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29095
93853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.2909593853
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.97032556
Short name T1659
Test name
Test status
Simulation time 180831860 ps
CPU time 0.89 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206640 kb
Host smart-1e374b79-7fbb-4b58-a174-a028753b45e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97032
556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.97032556
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.671501152
Short name T2001
Test name
Test status
Simulation time 179739520 ps
CPU time 0.81 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:08 PM PDT 24
Peak memory 206660 kb
Host smart-efd8c612-4683-49e5-bcb3-3082bbb1d84f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67150
1152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.671501152
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.180139631
Short name T2474
Test name
Test status
Simulation time 183176349 ps
CPU time 0.9 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206652 kb
Host smart-b6c9f795-166b-4708-b289-c935bf45a2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18013
9631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.180139631
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2778996193
Short name T1525
Test name
Test status
Simulation time 172871302 ps
CPU time 0.83 seconds
Started Jul 20 06:23:07 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206592 kb
Host smart-83492dd0-3e8e-4335-a037-f897db3e31a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27789
96193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2778996193
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.4148545587
Short name T736
Test name
Test status
Simulation time 219608909 ps
CPU time 0.98 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:23:16 PM PDT 24
Peak memory 206652 kb
Host smart-7a59aa63-37d0-40c9-95a8-288a0dd224a3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4148545587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.4148545587
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.2974064108
Short name T2223
Test name
Test status
Simulation time 164396177 ps
CPU time 0.78 seconds
Started Jul 20 06:23:05 PM PDT 24
Finished Jul 20 06:23:06 PM PDT 24
Peak memory 206652 kb
Host smart-1bfdffc6-42d9-4ca1-ad77-97d85524e57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29740
64108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.2974064108
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.231577817
Short name T1939
Test name
Test status
Simulation time 36494310 ps
CPU time 0.7 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:07 PM PDT 24
Peak memory 206652 kb
Host smart-5017a393-21a3-4800-8339-cc4e61b163f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23157
7817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.231577817
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.2059768988
Short name T611
Test name
Test status
Simulation time 19243209081 ps
CPU time 44.65 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:23:59 PM PDT 24
Peak memory 206952 kb
Host smart-08d23d11-a81c-43c4-aead-d58b1370a6a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20597
68988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.2059768988
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2673059033
Short name T2649
Test name
Test status
Simulation time 178684611 ps
CPU time 0.86 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206664 kb
Host smart-e2a3ae99-d924-4155-8822-862abf63a252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
59033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2673059033
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.3174658204
Short name T2569
Test name
Test status
Simulation time 241870501 ps
CPU time 0.96 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:08 PM PDT 24
Peak memory 206656 kb
Host smart-57c3b1d8-6c38-47d2-83e1-f626ac7bfa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31746
58204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.3174658204
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2442542597
Short name T2453
Test name
Test status
Simulation time 162251125 ps
CPU time 0.8 seconds
Started Jul 20 06:23:06 PM PDT 24
Finished Jul 20 06:23:07 PM PDT 24
Peak memory 206636 kb
Host smart-92189bb9-b33f-4983-b1cf-7551bddfb48f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24425
42597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2442542597
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.1692888352
Short name T1234
Test name
Test status
Simulation time 216760009 ps
CPU time 0.92 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:23:16 PM PDT 24
Peak memory 206648 kb
Host smart-3dc2a2af-d9d2-4580-8b2b-e076fc5c8244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16928
88352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.1692888352
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2650421354
Short name T2298
Test name
Test status
Simulation time 190493081 ps
CPU time 0.83 seconds
Started Jul 20 06:23:08 PM PDT 24
Finished Jul 20 06:23:10 PM PDT 24
Peak memory 206644 kb
Host smart-615eeaae-fd78-4024-8cf2-b7164b2e48fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26504
21354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2650421354
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1542918577
Short name T1104
Test name
Test status
Simulation time 171528443 ps
CPU time 0.79 seconds
Started Jul 20 06:23:07 PM PDT 24
Finished Jul 20 06:23:09 PM PDT 24
Peak memory 206644 kb
Host smart-aacd0c18-9e13-4a52-b41c-819972cc3e51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15429
18577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1542918577
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.1097095881
Short name T2065
Test name
Test status
Simulation time 162352474 ps
CPU time 0.82 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:17 PM PDT 24
Peak memory 206668 kb
Host smart-569c81a0-2f9a-4910-a909-c031aebb3468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10970
95881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.1097095881
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.2084526756
Short name T925
Test name
Test status
Simulation time 217654476 ps
CPU time 0.98 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:17 PM PDT 24
Peak memory 206644 kb
Host smart-12cdd1a5-c2f7-4239-80a7-3b28ff02615e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20845
26756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.2084526756
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.3258919189
Short name T1640
Test name
Test status
Simulation time 4367440855 ps
CPU time 122.22 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:25:18 PM PDT 24
Peak memory 206836 kb
Host smart-3508f6b0-0884-4fa5-b484-b7983527ba7d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3258919189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.3258919189
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3198716493
Short name T1077
Test name
Test status
Simulation time 161514112 ps
CPU time 0.85 seconds
Started Jul 20 06:23:12 PM PDT 24
Finished Jul 20 06:23:14 PM PDT 24
Peak memory 206652 kb
Host smart-3528ead9-89b8-4686-965a-6d49a11127fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31987
16493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3198716493
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.1176037278
Short name T2190
Test name
Test status
Simulation time 165063003 ps
CPU time 0.77 seconds
Started Jul 20 06:23:13 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206656 kb
Host smart-dee71038-8a75-4363-a5f3-7e656b6b4eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11760
37278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.1176037278
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3741501109
Short name T1874
Test name
Test status
Simulation time 280541341 ps
CPU time 1.04 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:23:20 PM PDT 24
Peak memory 206648 kb
Host smart-3f0c7212-dc7b-4d64-ae4f-c5dbe663ffb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37415
01109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3741501109
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.460094359
Short name T1313
Test name
Test status
Simulation time 4302315632 ps
CPU time 116.47 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:25:14 PM PDT 24
Peak memory 206976 kb
Host smart-a0fc8de1-5cb3-4d4c-945b-27b7a1465bf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46009
4359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.460094359
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.1205013908
Short name T604
Test name
Test status
Simulation time 74637153 ps
CPU time 0.71 seconds
Started Jul 20 06:23:25 PM PDT 24
Finished Jul 20 06:23:27 PM PDT 24
Peak memory 206708 kb
Host smart-c1531980-ddfd-4478-bed7-bdb49cf27efd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1205013908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.1205013908
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3061092175
Short name T2403
Test name
Test status
Simulation time 4004406200 ps
CPU time 5.21 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:22 PM PDT 24
Peak memory 206716 kb
Host smart-9f7e5759-9e16-4de7-9d06-a233c504db33
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3061092175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3061092175
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2459963854
Short name T500
Test name
Test status
Simulation time 13465906574 ps
CPU time 12.89 seconds
Started Jul 20 06:23:12 PM PDT 24
Finished Jul 20 06:23:25 PM PDT 24
Peak memory 206880 kb
Host smart-aac57166-4b03-436b-8444-6aa67a49322a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2459963854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2459963854
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.431635195
Short name T1669
Test name
Test status
Simulation time 23378992241 ps
CPU time 24.17 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:41 PM PDT 24
Peak memory 206780 kb
Host smart-48122617-5275-4992-b86d-02959dab4034
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=431635195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.431635195
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.534482498
Short name T2164
Test name
Test status
Simulation time 174204934 ps
CPU time 0.82 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206652 kb
Host smart-f50731b0-b93a-433d-b498-671c83befab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53448
2498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.534482498
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.775805541
Short name T102
Test name
Test status
Simulation time 164587236 ps
CPU time 0.81 seconds
Started Jul 20 06:23:19 PM PDT 24
Finished Jul 20 06:23:20 PM PDT 24
Peak memory 206656 kb
Host smart-c1f09a7f-96fb-40fc-8e10-43f8f4baf304
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77580
5541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.775805541
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.718989597
Short name T1513
Test name
Test status
Simulation time 213148233 ps
CPU time 0.95 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:18 PM PDT 24
Peak memory 206668 kb
Host smart-bea6ab42-a104-439c-98b4-a975dc8f131e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71898
9597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.718989597
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.708504093
Short name T867
Test name
Test status
Simulation time 1094899798 ps
CPU time 2.23 seconds
Started Jul 20 06:23:13 PM PDT 24
Finished Jul 20 06:23:16 PM PDT 24
Peak memory 206780 kb
Host smart-35dc3210-56b0-452b-928d-651553691728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70850
4093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.708504093
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.724215671
Short name T670
Test name
Test status
Simulation time 7651522109 ps
CPU time 13.75 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:23:31 PM PDT 24
Peak memory 206908 kb
Host smart-7b9f9eea-8e4f-4316-8a87-43b0aa789787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72421
5671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.724215671
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.1164202512
Short name T338
Test name
Test status
Simulation time 487837781 ps
CPU time 1.36 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:23:19 PM PDT 24
Peak memory 206660 kb
Host smart-3fb1e2a2-90c1-4c62-8644-7efab50a15cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
02512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.1164202512
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1769830130
Short name T1056
Test name
Test status
Simulation time 159129818 ps
CPU time 0.83 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:17 PM PDT 24
Peak memory 206632 kb
Host smart-a56d794b-edac-4282-a611-fc7315cc4222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17698
30130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1769830130
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3721731597
Short name T2155
Test name
Test status
Simulation time 36926499 ps
CPU time 0.65 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:18 PM PDT 24
Peak memory 206648 kb
Host smart-8a45718c-5061-450d-8bc9-06439174f8e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37217
31597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3721731597
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1797982098
Short name T1953
Test name
Test status
Simulation time 814590468 ps
CPU time 2.03 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:23:20 PM PDT 24
Peak memory 206716 kb
Host smart-ef73819a-bd79-4332-b1e2-c75e4264bcae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17979
82098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1797982098
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.943086514
Short name T174
Test name
Test status
Simulation time 311793925 ps
CPU time 2.13 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:18 PM PDT 24
Peak memory 206780 kb
Host smart-3c87db04-a40b-47fd-837e-48f4fb3e90c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94308
6514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.943086514
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2277046905
Short name T1036
Test name
Test status
Simulation time 249918856 ps
CPU time 0.91 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:23:18 PM PDT 24
Peak memory 206644 kb
Host smart-42b2786b-f2f1-4f94-8c2a-19784a983a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22770
46905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2277046905
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.3130468010
Short name T1286
Test name
Test status
Simulation time 133880451 ps
CPU time 0.79 seconds
Started Jul 20 06:23:19 PM PDT 24
Finished Jul 20 06:23:21 PM PDT 24
Peak memory 206652 kb
Host smart-8619d94b-a914-455f-a058-d3164d77fb1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31304
68010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.3130468010
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3276074865
Short name T2530
Test name
Test status
Simulation time 188957608 ps
CPU time 0.9 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:23:20 PM PDT 24
Peak memory 206652 kb
Host smart-ad54ce80-5215-48d4-9037-47114d068c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32760
74865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3276074865
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_invalid_sync.3332277616
Short name T1652
Test name
Test status
Simulation time 8920205856 ps
CPU time 78.1 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:24:36 PM PDT 24
Peak memory 206832 kb
Host smart-15aa4e66-7239-40f5-987f-f8f614649aaa
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3332277616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_invalid_sync.3332277616
Directory /workspace/22.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.2167367717
Short name T640
Test name
Test status
Simulation time 6857670195 ps
CPU time 24.11 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:23:42 PM PDT 24
Peak memory 206908 kb
Host smart-0b009ffb-431b-4088-9561-b857ad489971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21673
67717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.2167367717
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3570420454
Short name T1917
Test name
Test status
Simulation time 210444116 ps
CPU time 0.86 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:23:19 PM PDT 24
Peak memory 206764 kb
Host smart-9eb6ebe1-b246-4a8d-9cc2-2efefb1c155a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35704
20454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3570420454
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3151914761
Short name T1166
Test name
Test status
Simulation time 23326810863 ps
CPU time 22 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:23:40 PM PDT 24
Peak memory 206768 kb
Host smart-35a3c0d9-0bec-4390-b621-8f30eae3f795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31519
14761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3151914761
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1986361830
Short name T2578
Test name
Test status
Simulation time 3341100861 ps
CPU time 3.7 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:23:18 PM PDT 24
Peak memory 206732 kb
Host smart-83b62166-2f56-405a-8432-e9de30cca2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19863
61830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1986361830
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.1379424396
Short name T1098
Test name
Test status
Simulation time 8503727197 ps
CPU time 66.09 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 207036 kb
Host smart-09b75005-202c-45a7-b222-fd0b48d4817c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13794
24396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.1379424396
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.277979254
Short name T1634
Test name
Test status
Simulation time 4200911757 ps
CPU time 119.46 seconds
Started Jul 20 06:23:18 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206880 kb
Host smart-1b134fc5-69ba-4420-894c-43ef6f385a4f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=277979254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.277979254
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.3881720490
Short name T1782
Test name
Test status
Simulation time 288593215 ps
CPU time 1.16 seconds
Started Jul 20 06:23:16 PM PDT 24
Finished Jul 20 06:23:18 PM PDT 24
Peak memory 206640 kb
Host smart-45c8c059-fa70-445a-917e-edc765f528c9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3881720490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.3881720490
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3214462807
Short name T2440
Test name
Test status
Simulation time 186513809 ps
CPU time 0.85 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:23:19 PM PDT 24
Peak memory 206660 kb
Host smart-793fe76b-568d-493c-9e44-698a52338d77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32144
62807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3214462807
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2570517079
Short name T148
Test name
Test status
Simulation time 7372828717 ps
CPU time 64.28 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206904 kb
Host smart-70459157-9d90-4cad-93e1-0a3ae13953b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25705
17079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2570517079
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.759865088
Short name T554
Test name
Test status
Simulation time 7280688738 ps
CPU time 52.43 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206868 kb
Host smart-c3243610-bef2-4b3e-a461-8e367cb691a8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=759865088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.759865088
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.468577812
Short name T340
Test name
Test status
Simulation time 186673100 ps
CPU time 0.99 seconds
Started Jul 20 06:23:17 PM PDT 24
Finished Jul 20 06:23:19 PM PDT 24
Peak memory 206656 kb
Host smart-faedf308-0251-4988-9d49-061d09c05488
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=468577812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.468577812
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.4087511994
Short name T667
Test name
Test status
Simulation time 172601233 ps
CPU time 0.84 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:17 PM PDT 24
Peak memory 206636 kb
Host smart-e56461bf-3ffe-4151-ba92-32ca1d7d96ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40875
11994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.4087511994
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3004807004
Short name T131
Test name
Test status
Simulation time 181642220 ps
CPU time 0.81 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:23:15 PM PDT 24
Peak memory 206668 kb
Host smart-ad1314fb-b254-4b3d-9539-ac85822da6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30048
07004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3004807004
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.414734702
Short name T1205
Test name
Test status
Simulation time 203679470 ps
CPU time 0.83 seconds
Started Jul 20 06:23:15 PM PDT 24
Finished Jul 20 06:23:17 PM PDT 24
Peak memory 206592 kb
Host smart-2df02882-ed63-4bdb-afa9-70df13805fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41473
4702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.414734702
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1952657545
Short name T830
Test name
Test status
Simulation time 173383977 ps
CPU time 0.81 seconds
Started Jul 20 06:23:14 PM PDT 24
Finished Jul 20 06:23:16 PM PDT 24
Peak memory 206656 kb
Host smart-42c3cc49-7051-451a-86bf-d40923e7e417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19526
57545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1952657545
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.3213334417
Short name T1813
Test name
Test status
Simulation time 161738677 ps
CPU time 0.77 seconds
Started Jul 20 06:23:22 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 206644 kb
Host smart-c47bce42-e180-4242-803d-33b2300fd74b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32133
34417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.3213334417
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.2637036407
Short name T900
Test name
Test status
Simulation time 155554101 ps
CPU time 0.79 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206648 kb
Host smart-7a61b54d-5f51-4fe3-8a58-57860ee37c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26370
36407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.2637036407
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.121376998
Short name T1470
Test name
Test status
Simulation time 194796661 ps
CPU time 0.86 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:23:25 PM PDT 24
Peak memory 206664 kb
Host smart-bdf4c57e-77cf-41de-b9a9-4d42222ba316
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=121376998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.121376998
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.4140562647
Short name T182
Test name
Test status
Simulation time 176890152 ps
CPU time 0.83 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:27 PM PDT 24
Peak memory 206652 kb
Host smart-f66296bf-1169-40d4-bcfd-3462fc89eda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41405
62647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.4140562647
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.1621134543
Short name T1485
Test name
Test status
Simulation time 65390832 ps
CPU time 0.69 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:26 PM PDT 24
Peak memory 206644 kb
Host smart-aebb962f-e795-4678-a8c4-10b95a8df7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16211
34543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.1621134543
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3481328454
Short name T2383
Test name
Test status
Simulation time 6458095266 ps
CPU time 14.87 seconds
Started Jul 20 06:23:25 PM PDT 24
Finished Jul 20 06:23:42 PM PDT 24
Peak memory 206944 kb
Host smart-d0f57fba-805e-4647-ba71-5c14d7b9eb62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34813
28454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3481328454
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.2988432220
Short name T2079
Test name
Test status
Simulation time 172683040 ps
CPU time 0.79 seconds
Started Jul 20 06:23:22 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 206648 kb
Host smart-f5f8a86a-a1d8-42ef-8632-17c73427c70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29884
32220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.2988432220
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.1439812844
Short name T2656
Test name
Test status
Simulation time 253110395 ps
CPU time 0.9 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:23:25 PM PDT 24
Peak memory 206648 kb
Host smart-7475f34e-c02d-4c61-ab6d-9e18268b497b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14398
12844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.1439812844
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2065982368
Short name T1340
Test name
Test status
Simulation time 192669911 ps
CPU time 0.87 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:23:33 PM PDT 24
Peak memory 206616 kb
Host smart-513abc64-5b21-4483-b0ee-437d12c3b76a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20659
82368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2065982368
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.335829333
Short name T682
Test name
Test status
Simulation time 202010961 ps
CPU time 0.85 seconds
Started Jul 20 06:23:26 PM PDT 24
Finished Jul 20 06:23:28 PM PDT 24
Peak memory 206420 kb
Host smart-24989753-4065-41fb-b742-4b447e6ed56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33582
9333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.335829333
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.958755726
Short name T2088
Test name
Test status
Simulation time 151248147 ps
CPU time 0.78 seconds
Started Jul 20 06:23:22 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 206656 kb
Host smart-9640dfa4-477a-4565-aed2-ff4bd6751fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95875
5726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.958755726
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2486886804
Short name T1922
Test name
Test status
Simulation time 162831453 ps
CPU time 0.81 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:26 PM PDT 24
Peak memory 206632 kb
Host smart-de41aaab-b139-47f8-a22e-fc2124b94cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24868
86804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2486886804
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.3135237749
Short name T1093
Test name
Test status
Simulation time 181014459 ps
CPU time 0.76 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206648 kb
Host smart-30a79e49-32b2-4cac-bc29-5c795d07b8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31352
37749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.3135237749
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.40938921
Short name T1320
Test name
Test status
Simulation time 224116833 ps
CPU time 0.91 seconds
Started Jul 20 06:23:22 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 206640 kb
Host smart-31df1ffd-dc8e-4777-89b5-e42716858915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40938
921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.40938921
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.957686008
Short name T793
Test name
Test status
Simulation time 4709386067 ps
CPU time 35.33 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:24:01 PM PDT 24
Peak memory 206912 kb
Host smart-5357ccbc-3337-4a93-98c6-ea8b53fdc557
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=957686008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.957686008
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.1052698108
Short name T1253
Test name
Test status
Simulation time 184526663 ps
CPU time 0.88 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:23:26 PM PDT 24
Peak memory 206644 kb
Host smart-31ba609b-214a-4a51-8e01-5bbe676a840d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10526
98108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.1052698108
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.830875316
Short name T331
Test name
Test status
Simulation time 171633897 ps
CPU time 0.8 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:27 PM PDT 24
Peak memory 206648 kb
Host smart-f2f4b3a0-2b8c-408d-98d8-1e0286f982bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83087
5316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.830875316
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.134334227
Short name T2394
Test name
Test status
Simulation time 521779548 ps
CPU time 1.36 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:23:27 PM PDT 24
Peak memory 206632 kb
Host smart-d2ff2919-ac83-4bc8-a0e7-360a393e6777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13433
4227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.134334227
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.1982218500
Short name T1484
Test name
Test status
Simulation time 4991927050 ps
CPU time 137.78 seconds
Started Jul 20 06:23:21 PM PDT 24
Finished Jul 20 06:25:40 PM PDT 24
Peak memory 206860 kb
Host smart-27791f07-6255-4a43-9b77-0b4d5e4299d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19822
18500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.1982218500
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.1192003790
Short name T1335
Test name
Test status
Simulation time 31396733 ps
CPU time 0.66 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206700 kb
Host smart-8f114e42-6f7d-4959-be60-e37b8902f65f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1192003790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.1192003790
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3358212172
Short name T2176
Test name
Test status
Simulation time 3795493353 ps
CPU time 4.36 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:23:29 PM PDT 24
Peak memory 206864 kb
Host smart-0cc6b782-b4c0-481e-9291-9f0d9a88af4e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3358212172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3358212172
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.2680522633
Short name T2545
Test name
Test status
Simulation time 13427049151 ps
CPU time 16.1 seconds
Started Jul 20 06:23:26 PM PDT 24
Finished Jul 20 06:23:43 PM PDT 24
Peak memory 206872 kb
Host smart-1f990a64-f544-4da9-a314-ac6c5c6fa614
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2680522633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.2680522633
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.207773497
Short name T16
Test name
Test status
Simulation time 23488139941 ps
CPU time 25.3 seconds
Started Jul 20 06:23:26 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206928 kb
Host smart-31cb4463-ac91-4214-99a0-72dd8ac70af6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=207773497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.207773497
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3836250012
Short name T2170
Test name
Test status
Simulation time 163714963 ps
CPU time 0.8 seconds
Started Jul 20 06:23:21 PM PDT 24
Finished Jul 20 06:23:23 PM PDT 24
Peak memory 206648 kb
Host smart-4e96c233-e64c-47eb-8667-14c9f5ceb9bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38362
50012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3836250012
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2846966651
Short name T2267
Test name
Test status
Simulation time 148562265 ps
CPU time 0.78 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:26 PM PDT 24
Peak memory 206660 kb
Host smart-6d9c8a89-0c12-4ea7-8d59-a7a6de00c2ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28469
66651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2846966651
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2867116292
Short name T101
Test name
Test status
Simulation time 162515491 ps
CPU time 0.79 seconds
Started Jul 20 06:23:21 PM PDT 24
Finished Jul 20 06:23:23 PM PDT 24
Peak memory 206632 kb
Host smart-a180d354-ce4c-46b0-8cc0-34510b764097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28671
16292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2867116292
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2879647901
Short name T885
Test name
Test status
Simulation time 521467452 ps
CPU time 1.29 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:23:25 PM PDT 24
Peak memory 206652 kb
Host smart-29d3cb5a-e4b3-4e80-8415-e57b17d2c91f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796
47901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2879647901
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.4128990553
Short name T669
Test name
Test status
Simulation time 6453973134 ps
CPU time 14.25 seconds
Started Jul 20 06:23:22 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206908 kb
Host smart-32499b97-8138-428a-8113-fd357731ca5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41289
90553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.4128990553
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.85616187
Short name T424
Test name
Test status
Simulation time 374822445 ps
CPU time 1.21 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206652 kb
Host smart-2f97b0c8-40db-41b9-a8dd-2a2113a2a99b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85616
187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.85616187
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.43217427
Short name T459
Test name
Test status
Simulation time 152386090 ps
CPU time 0.77 seconds
Started Jul 20 06:23:21 PM PDT 24
Finished Jul 20 06:23:22 PM PDT 24
Peak memory 206640 kb
Host smart-fad72edf-c4b2-4a5f-840c-18373ed1d8bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43217
427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.43217427
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3244879984
Short name T791
Test name
Test status
Simulation time 40779015 ps
CPU time 0.67 seconds
Started Jul 20 06:23:23 PM PDT 24
Finished Jul 20 06:23:25 PM PDT 24
Peak memory 206644 kb
Host smart-00d8c329-c159-412e-8f1a-5089fa5266f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32448
79984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3244879984
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.874251611
Short name T1001
Test name
Test status
Simulation time 993338164 ps
CPU time 2.35 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206796 kb
Host smart-aec4dd59-3efb-4d0c-82f2-91ed7eb7d67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87425
1611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.874251611
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2631774555
Short name T1180
Test name
Test status
Simulation time 175726047 ps
CPU time 2.18 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:28 PM PDT 24
Peak memory 206736 kb
Host smart-8176d5c7-7e74-4dd2-9b8f-85152b74c2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26317
74555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2631774555
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.750861166
Short name T1305
Test name
Test status
Simulation time 219709056 ps
CPU time 0.87 seconds
Started Jul 20 06:23:25 PM PDT 24
Finished Jul 20 06:23:28 PM PDT 24
Peak memory 206628 kb
Host smart-fb003a78-d82b-49fc-a297-dd64e79e2c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75086
1166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.750861166
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.870808649
Short name T944
Test name
Test status
Simulation time 170993418 ps
CPU time 0.78 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:23:33 PM PDT 24
Peak memory 206548 kb
Host smart-176aca31-bd88-4377-a825-c1e3cffc1d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87080
8649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.870808649
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1075031992
Short name T2737
Test name
Test status
Simulation time 237938081 ps
CPU time 0.95 seconds
Started Jul 20 06:23:22 PM PDT 24
Finished Jul 20 06:23:24 PM PDT 24
Peak memory 206656 kb
Host smart-e6d51762-0578-4ab4-a964-a4d826d93559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10750
31992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1075031992
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3646490535
Short name T1803
Test name
Test status
Simulation time 5081253880 ps
CPU time 137.78 seconds
Started Jul 20 06:23:26 PM PDT 24
Finished Jul 20 06:25:45 PM PDT 24
Peak memory 206696 kb
Host smart-5a77399d-be96-4367-8396-b77c4ad590a7
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3646490535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3646490535
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2127995188
Short name T2291
Test name
Test status
Simulation time 217902363 ps
CPU time 0.89 seconds
Started Jul 20 06:23:25 PM PDT 24
Finished Jul 20 06:23:28 PM PDT 24
Peak memory 206656 kb
Host smart-eb266f50-5bac-4895-9e8d-bdb2ca789556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21279
95188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2127995188
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.3306973310
Short name T1217
Test name
Test status
Simulation time 23299445534 ps
CPU time 24.61 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:50 PM PDT 24
Peak memory 206760 kb
Host smart-dddc9147-6628-45da-8ec9-ac3d1e5f3992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33069
73310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.3306973310
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.421170598
Short name T849
Test name
Test status
Simulation time 3283085015 ps
CPU time 4.1 seconds
Started Jul 20 06:23:24 PM PDT 24
Finished Jul 20 06:23:30 PM PDT 24
Peak memory 206720 kb
Host smart-aaac43c6-dc98-4782-a981-ae792f16d7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42117
0598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.421170598
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3664954469
Short name T392
Test name
Test status
Simulation time 6173108405 ps
CPU time 58.94 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:24:32 PM PDT 24
Peak memory 206880 kb
Host smart-d7fcb8b5-bbfc-4595-9c96-ff81dfedd07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36649
54469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3664954469
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1077109614
Short name T1960
Test name
Test status
Simulation time 2712417667 ps
CPU time 20.27 seconds
Started Jul 20 06:23:34 PM PDT 24
Finished Jul 20 06:23:58 PM PDT 24
Peak memory 206844 kb
Host smart-5a272364-f24e-4152-9f62-4dd9aa37959d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1077109614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1077109614
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.4233257347
Short name T2667
Test name
Test status
Simulation time 242631206 ps
CPU time 0.87 seconds
Started Jul 20 06:23:33 PM PDT 24
Finished Jul 20 06:23:38 PM PDT 24
Peak memory 206652 kb
Host smart-0e8f9f58-849d-41f1-87b4-0f3549b6e193
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4233257347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.4233257347
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.4176717562
Short name T882
Test name
Test status
Simulation time 200154142 ps
CPU time 0.87 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206648 kb
Host smart-1423f6ab-1e38-4f74-9c05-4b8dfc2cd18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41767
17562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.4176717562
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.64368468
Short name T1248
Test name
Test status
Simulation time 4363582949 ps
CPU time 120.56 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:25:34 PM PDT 24
Peak memory 206840 kb
Host smart-a49f607a-56b7-46f8-ab38-b95d14e8cce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64368
468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.64368468
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.2116920409
Short name T1769
Test name
Test status
Simulation time 6772496149 ps
CPU time 185.89 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:26:41 PM PDT 24
Peak memory 206880 kb
Host smart-3dba0da4-b078-440a-a815-030fa8298daf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2116920409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.2116920409
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.2287197505
Short name T1400
Test name
Test status
Simulation time 179274925 ps
CPU time 0.79 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206640 kb
Host smart-e229a95d-feb5-4c11-9cb0-a7a4955d2507
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2287197505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.2287197505
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3645614704
Short name T319
Test name
Test status
Simulation time 170040324 ps
CPU time 0.76 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206660 kb
Host smart-c11735dd-1148-402b-af61-34c9338aa5c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36456
14704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3645614704
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.2364551863
Short name T116
Test name
Test status
Simulation time 199901378 ps
CPU time 0.86 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206700 kb
Host smart-0c315566-d7e0-48f2-b9ce-0b8f6a8f37a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23645
51863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.2364551863
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.668141208
Short name T934
Test name
Test status
Simulation time 228198863 ps
CPU time 0.9 seconds
Started Jul 20 06:23:34 PM PDT 24
Finished Jul 20 06:23:38 PM PDT 24
Peak memory 206648 kb
Host smart-a2f59d54-4056-4ba1-a80a-6ccae585d34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66814
1208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.668141208
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2165526312
Short name T2198
Test name
Test status
Simulation time 206645905 ps
CPU time 0.79 seconds
Started Jul 20 06:23:33 PM PDT 24
Finished Jul 20 06:23:38 PM PDT 24
Peak memory 206592 kb
Host smart-a9c44a02-1724-4707-8421-bb1fcfe89fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21655
26312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2165526312
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3331987412
Short name T1940
Test name
Test status
Simulation time 221394027 ps
CPU time 0.86 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:23:32 PM PDT 24
Peak memory 206636 kb
Host smart-e7662fb9-06c4-433e-a108-bba040c2a0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33319
87412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3331987412
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.2861084001
Short name T439
Test name
Test status
Simulation time 153240504 ps
CPU time 0.8 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:34 PM PDT 24
Peak memory 206676 kb
Host smart-0d145455-290a-4096-a42a-a2296d3f7ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28610
84001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.2861084001
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.3431045648
Short name T1216
Test name
Test status
Simulation time 230614442 ps
CPU time 0.93 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206648 kb
Host smart-4912f21c-331c-4419-8a98-793f7e21aa7b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3431045648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.3431045648
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1172378754
Short name T702
Test name
Test status
Simulation time 146307207 ps
CPU time 0.82 seconds
Started Jul 20 06:23:33 PM PDT 24
Finished Jul 20 06:23:38 PM PDT 24
Peak memory 206656 kb
Host smart-7af4cf63-7daa-4d90-98d8-adc874ff89ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
78754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1172378754
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3161094796
Short name T1584
Test name
Test status
Simulation time 91065646 ps
CPU time 0.71 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206628 kb
Host smart-0bde3516-26b1-46e8-bcc1-df6dbde56bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31610
94796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3161094796
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2717196777
Short name T1568
Test name
Test status
Simulation time 7463592119 ps
CPU time 15.92 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206912 kb
Host smart-7a508428-88ca-4110-953d-4f77480f4c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27171
96777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2717196777
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.2095192596
Short name T620
Test name
Test status
Simulation time 211286435 ps
CPU time 0.88 seconds
Started Jul 20 06:23:35 PM PDT 24
Finished Jul 20 06:23:39 PM PDT 24
Peak memory 206648 kb
Host smart-e06f10e7-7013-4a41-ba53-2cc2b05ab60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20951
92596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.2095192596
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.2411537586
Short name T2483
Test name
Test status
Simulation time 192241349 ps
CPU time 0.81 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206648 kb
Host smart-34666262-b97a-4bb6-9d2e-830205bd1e6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24115
37586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.2411537586
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4108865298
Short name T446
Test name
Test status
Simulation time 213767213 ps
CPU time 0.91 seconds
Started Jul 20 06:23:34 PM PDT 24
Finished Jul 20 06:23:39 PM PDT 24
Peak memory 206648 kb
Host smart-85651430-0945-4cae-b0b0-3766864efe11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41088
65298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4108865298
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2488029285
Short name T1643
Test name
Test status
Simulation time 168541888 ps
CPU time 0.84 seconds
Started Jul 20 06:23:39 PM PDT 24
Finished Jul 20 06:23:40 PM PDT 24
Peak memory 206652 kb
Host smart-64721d55-c93f-41e8-9f18-38b9f70db414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24880
29285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2488029285
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.3828960914
Short name T811
Test name
Test status
Simulation time 178618913 ps
CPU time 0.8 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206652 kb
Host smart-19d48260-11ba-4d92-848b-26bd05f9383a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38289
60914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.3828960914
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.3898592478
Short name T1810
Test name
Test status
Simulation time 153874187 ps
CPU time 0.78 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206628 kb
Host smart-08eb4d9b-edd2-4386-8c4b-e34c5369fdd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38985
92478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.3898592478
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3211686240
Short name T2432
Test name
Test status
Simulation time 158204016 ps
CPU time 0.84 seconds
Started Jul 20 06:23:34 PM PDT 24
Finished Jul 20 06:23:38 PM PDT 24
Peak memory 206648 kb
Host smart-a1066dce-90b4-4220-8b7b-418a2a4ebe4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
86240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3211686240
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.3768973202
Short name T1825
Test name
Test status
Simulation time 249851174 ps
CPU time 0.93 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206652 kb
Host smart-74cd73d0-86c2-4734-ab22-fc5e365fe5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37689
73202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.3768973202
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2469477556
Short name T1186
Test name
Test status
Simulation time 4075557835 ps
CPU time 32.7 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:24:08 PM PDT 24
Peak memory 206820 kb
Host smart-390e6bbe-833b-4713-9ffc-f6694a076456
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2469477556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2469477556
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.745128870
Short name T946
Test name
Test status
Simulation time 190653848 ps
CPU time 0.88 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206660 kb
Host smart-da3daac5-092d-4796-9e07-97e2e431770a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74512
8870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.745128870
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3693440158
Short name T1156
Test name
Test status
Simulation time 212648257 ps
CPU time 0.84 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206652 kb
Host smart-8a9aa295-368e-4ff8-8f98-761167a610a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36934
40158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3693440158
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.966403011
Short name T2513
Test name
Test status
Simulation time 324218946 ps
CPU time 1.05 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206652 kb
Host smart-38a18f05-8eff-47c2-a054-c20a724e7b1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96640
3011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.966403011
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.2488700708
Short name T945
Test name
Test status
Simulation time 5748991304 ps
CPU time 56.05 seconds
Started Jul 20 06:23:35 PM PDT 24
Finished Jul 20 06:24:34 PM PDT 24
Peak memory 206868 kb
Host smart-aced877a-3012-40aa-922c-1f8f1809ecf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887
00708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.2488700708
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2648158064
Short name T1798
Test name
Test status
Simulation time 50927386 ps
CPU time 0.69 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:44 PM PDT 24
Peak memory 206720 kb
Host smart-5c182a9d-2b80-47ae-ba98-b147817a1f31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2648158064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2648158064
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1761011499
Short name T217
Test name
Test status
Simulation time 3976425670 ps
CPU time 4.65 seconds
Started Jul 20 06:23:33 PM PDT 24
Finished Jul 20 06:23:42 PM PDT 24
Peak memory 206804 kb
Host smart-74a0c254-5b9c-4827-9b06-d12a2a4059af
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1761011499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.1761011499
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.242825195
Short name T744
Test name
Test status
Simulation time 13378534098 ps
CPU time 15.08 seconds
Started Jul 20 06:23:35 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206868 kb
Host smart-cd442bed-41fd-484e-9984-c5584b3a2c92
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=242825195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.242825195
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.931085895
Short name T956
Test name
Test status
Simulation time 23395062788 ps
CPU time 26.29 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:24:02 PM PDT 24
Peak memory 206776 kb
Host smart-feecb2fb-2d20-4563-91d1-3b7287690958
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=931085895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.931085895
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1762384677
Short name T1740
Test name
Test status
Simulation time 173833294 ps
CPU time 0.82 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206652 kb
Host smart-cbc3686f-5910-434f-81c9-ff73b42b47a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623
84677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1762384677
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.18683953
Short name T967
Test name
Test status
Simulation time 146157653 ps
CPU time 0.73 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:37 PM PDT 24
Peak memory 206660 kb
Host smart-1e88c742-a766-4b8a-856e-e129cbb67d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18683
953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.18683953
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2475784979
Short name T2041
Test name
Test status
Simulation time 408066909 ps
CPU time 1.3 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206648 kb
Host smart-0213db9f-7f85-43c2-8b1f-d9ca38b1c4f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24757
84979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2475784979
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.2801115944
Short name T432
Test name
Test status
Simulation time 635256740 ps
CPU time 1.6 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:23:38 PM PDT 24
Peak memory 206772 kb
Host smart-9f33082f-5e9c-4d6c-a182-fe45975e9b33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28011
15944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.2801115944
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3433705453
Short name T1739
Test name
Test status
Simulation time 17758985887 ps
CPU time 40.44 seconds
Started Jul 20 06:23:32 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206912 kb
Host smart-488e89ce-5678-42fb-9bb6-a33272700e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34337
05453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3433705453
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.59150147
Short name T497
Test name
Test status
Simulation time 348386420 ps
CPU time 1.21 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206640 kb
Host smart-27bc2571-421e-4627-9b11-4eade05540fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59150
147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.59150147
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.3774900680
Short name T2467
Test name
Test status
Simulation time 140821219 ps
CPU time 0.81 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206652 kb
Host smart-089212a2-6f29-48c6-858d-4146f23b416f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37749
00680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.3774900680
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1775714392
Short name T1638
Test name
Test status
Simulation time 31446913 ps
CPU time 0.66 seconds
Started Jul 20 06:23:39 PM PDT 24
Finished Jul 20 06:23:40 PM PDT 24
Peak memory 206648 kb
Host smart-848fb63f-0d91-43bb-a086-30868df54521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17757
14392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1775714392
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2973339264
Short name T933
Test name
Test status
Simulation time 906079231 ps
CPU time 2.26 seconds
Started Jul 20 06:23:33 PM PDT 24
Finished Jul 20 06:23:39 PM PDT 24
Peak memory 206716 kb
Host smart-b79b17d1-ab14-4dc0-8d95-002a77dac180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29733
39264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2973339264
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1015567829
Short name T1343
Test name
Test status
Simulation time 177476972 ps
CPU time 1.27 seconds
Started Jul 20 06:23:31 PM PDT 24
Finished Jul 20 06:23:35 PM PDT 24
Peak memory 206768 kb
Host smart-58528d9a-47ab-480d-917f-2d8f12746d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10155
67829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1015567829
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1706054182
Short name T108
Test name
Test status
Simulation time 175303882 ps
CPU time 0.81 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:23:33 PM PDT 24
Peak memory 206660 kb
Host smart-995eca03-2726-4512-afac-318add897a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17060
54182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1706054182
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.1149043750
Short name T2287
Test name
Test status
Simulation time 148066366 ps
CPU time 0.76 seconds
Started Jul 20 06:23:33 PM PDT 24
Finished Jul 20 06:23:38 PM PDT 24
Peak memory 206648 kb
Host smart-cf3ca2b3-4cf4-4621-bfa8-2df34577c017
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11490
43750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.1149043750
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.1985600549
Short name T1193
Test name
Test status
Simulation time 156407870 ps
CPU time 0.79 seconds
Started Jul 20 06:23:35 PM PDT 24
Finished Jul 20 06:23:39 PM PDT 24
Peak memory 206648 kb
Host smart-69af36b2-c426-4531-878f-12443e96ea6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19856
00549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.1985600549
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.1362023497
Short name T1797
Test name
Test status
Simulation time 5460737285 ps
CPU time 41.77 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206852 kb
Host smart-1c10aec6-1f1b-459c-84eb-90df80d1744c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1362023497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.1362023497
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2871142246
Short name T1101
Test name
Test status
Simulation time 5195790352 ps
CPU time 43.32 seconds
Started Jul 20 06:23:34 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206904 kb
Host smart-264e988e-c864-4356-b3b2-cd8957da265d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28711
42246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2871142246
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.743225367
Short name T487
Test name
Test status
Simulation time 196248316 ps
CPU time 0.88 seconds
Started Jul 20 06:23:35 PM PDT 24
Finished Jul 20 06:23:39 PM PDT 24
Peak memory 206648 kb
Host smart-20b743bc-0eec-426d-b224-6bf9248c0c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74322
5367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.743225367
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1729819567
Short name T536
Test name
Test status
Simulation time 23306026002 ps
CPU time 25.1 seconds
Started Jul 20 06:23:33 PM PDT 24
Finished Jul 20 06:24:02 PM PDT 24
Peak memory 206776 kb
Host smart-8a2108c3-68bd-4e2b-a041-b6dc9798ce72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17298
19567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1729819567
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.931598501
Short name T1655
Test name
Test status
Simulation time 3297770435 ps
CPU time 4.18 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:23:36 PM PDT 24
Peak memory 206708 kb
Host smart-0341af44-33a1-4950-8bc2-d346f325cafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93159
8501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.931598501
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.4141638488
Short name T1804
Test name
Test status
Simulation time 13335549031 ps
CPU time 356.07 seconds
Started Jul 20 06:23:30 PM PDT 24
Finished Jul 20 06:29:29 PM PDT 24
Peak memory 207048 kb
Host smart-8562f580-24c0-474e-9324-5150294c12ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
38488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.4141638488
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.726789178
Short name T365
Test name
Test status
Simulation time 2875105948 ps
CPU time 81.01 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:25:06 PM PDT 24
Peak memory 206924 kb
Host smart-cfb09c2a-ce7b-48ad-ab2e-0caac82fc3f7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=726789178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.726789178
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1585006023
Short name T737
Test name
Test status
Simulation time 290956909 ps
CPU time 1.03 seconds
Started Jul 20 06:23:45 PM PDT 24
Finished Jul 20 06:23:50 PM PDT 24
Peak memory 206656 kb
Host smart-21005be3-5c61-48e0-bc4e-d61e252ff366
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1585006023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1585006023
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.2271060188
Short name T2009
Test name
Test status
Simulation time 217717303 ps
CPU time 0.87 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:45 PM PDT 24
Peak memory 206652 kb
Host smart-7d51a90d-5c99-42f6-a64a-cc00412c48a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22710
60188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.2271060188
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3529054696
Short name T763
Test name
Test status
Simulation time 4477087783 ps
CPU time 124.22 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:25:51 PM PDT 24
Peak memory 206864 kb
Host smart-f9b72b5f-bf10-4f35-93a4-ea26f65299f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35290
54696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3529054696
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.3568685344
Short name T345
Test name
Test status
Simulation time 3541351719 ps
CPU time 34.75 seconds
Started Jul 20 06:23:40 PM PDT 24
Finished Jul 20 06:24:16 PM PDT 24
Peak memory 206904 kb
Host smart-80c1e0ff-5566-4480-9a16-f38b34547652
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3568685344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.3568685344
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.3052852965
Short name T2335
Test name
Test status
Simulation time 172583167 ps
CPU time 0.87 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:45 PM PDT 24
Peak memory 206668 kb
Host smart-0cffa49a-747b-4022-b9c4-757c5fab7cea
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3052852965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.3052852965
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.4067988538
Short name T824
Test name
Test status
Simulation time 156257258 ps
CPU time 0.81 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:48 PM PDT 24
Peak memory 206652 kb
Host smart-0e14789f-c082-45c0-ba64-04ade8f37727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40679
88538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.4067988538
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.1366952881
Short name T2487
Test name
Test status
Simulation time 212924335 ps
CPU time 0.86 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 206648 kb
Host smart-ebc396a8-9e4b-4729-a836-792a7ecd5357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13669
52881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.1366952881
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.307741488
Short name T574
Test name
Test status
Simulation time 197276475 ps
CPU time 0.84 seconds
Started Jul 20 06:23:40 PM PDT 24
Finished Jul 20 06:23:41 PM PDT 24
Peak memory 206760 kb
Host smart-f634e380-9627-4403-99c0-b9d463fa22d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30774
1488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.307741488
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1040559127
Short name T679
Test name
Test status
Simulation time 266036011 ps
CPU time 0.88 seconds
Started Jul 20 06:23:40 PM PDT 24
Finished Jul 20 06:23:41 PM PDT 24
Peak memory 206648 kb
Host smart-8e0a6cb4-5836-45bf-9e37-190ff90b447e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10405
59127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1040559127
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.441800079
Short name T1842
Test name
Test status
Simulation time 170527672 ps
CPU time 0.78 seconds
Started Jul 20 06:23:41 PM PDT 24
Finished Jul 20 06:23:43 PM PDT 24
Peak memory 206656 kb
Host smart-5650a4fd-0d38-4698-9d72-6a1d5ab4404e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44180
0079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.441800079
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2806681985
Short name T2233
Test name
Test status
Simulation time 198308662 ps
CPU time 0.83 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:23:47 PM PDT 24
Peak memory 206652 kb
Host smart-a010b7f3-ecb8-4bd7-8f24-038ae48c6fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28066
81985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2806681985
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.852076551
Short name T2357
Test name
Test status
Simulation time 207983118 ps
CPU time 0.89 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206652 kb
Host smart-7a9fd900-6e2b-412d-8b42-d4378184dc93
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=852076551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.852076551
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.3541276847
Short name T656
Test name
Test status
Simulation time 146847406 ps
CPU time 0.79 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:23:47 PM PDT 24
Peak memory 206652 kb
Host smart-d8b2bf30-670b-4733-bcf8-8b7bb55fe6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35412
76847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.3541276847
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.4003385419
Short name T2542
Test name
Test status
Simulation time 33982608 ps
CPU time 0.63 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 206636 kb
Host smart-9b3ca426-83f0-4ab6-a8f5-d01d3ea8c724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40033
85419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.4003385419
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.1417054943
Short name T1902
Test name
Test status
Simulation time 17293184654 ps
CPU time 39.61 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:24:26 PM PDT 24
Peak memory 206868 kb
Host smart-3784caa0-75b3-4f54-97d7-e805a2135fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14170
54943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.1417054943
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.3303537233
Short name T2296
Test name
Test status
Simulation time 204294549 ps
CPU time 0.83 seconds
Started Jul 20 06:23:40 PM PDT 24
Finished Jul 20 06:23:41 PM PDT 24
Peak memory 206664 kb
Host smart-dd3e09c0-136b-493f-921f-e1d3a758ea04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33035
37233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.3303537233
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.4020220481
Short name T1106
Test name
Test status
Simulation time 174458402 ps
CPU time 0.81 seconds
Started Jul 20 06:23:40 PM PDT 24
Finished Jul 20 06:23:42 PM PDT 24
Peak memory 206748 kb
Host smart-84ac3c85-f268-4716-9834-15dad4f40f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40202
20481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.4020220481
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.2292808401
Short name T2559
Test name
Test status
Simulation time 157738020 ps
CPU time 0.82 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:23:47 PM PDT 24
Peak memory 206640 kb
Host smart-446b8b82-d6bb-4f76-912f-5411f8316eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
08401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.2292808401
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3525417010
Short name T2123
Test name
Test status
Simulation time 193659199 ps
CPU time 0.83 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 206652 kb
Host smart-cd8e4fd5-3fec-43da-ad2a-79221d4b7b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254
17010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3525417010
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3334518457
Short name T1557
Test name
Test status
Simulation time 136604019 ps
CPU time 0.73 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:48 PM PDT 24
Peak memory 206604 kb
Host smart-62058153-ad7c-4249-9c4f-8432f60f9165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33345
18457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3334518457
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.3031865772
Short name T1353
Test name
Test status
Simulation time 155102788 ps
CPU time 0.82 seconds
Started Jul 20 06:23:41 PM PDT 24
Finished Jul 20 06:23:44 PM PDT 24
Peak memory 206648 kb
Host smart-dec73120-f274-41ea-99d5-ce105a54014f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30318
65772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.3031865772
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.4242628250
Short name T1
Test name
Test status
Simulation time 152218914 ps
CPU time 0.82 seconds
Started Jul 20 06:23:45 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206644 kb
Host smart-ff708f5e-c961-48db-bbfe-448e39691e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42426
28250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.4242628250
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.3727426807
Short name T765
Test name
Test status
Simulation time 236294380 ps
CPU time 0.98 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206636 kb
Host smart-0b35d938-9a85-47b7-9fa7-17852588f8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37274
26807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.3727426807
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.3743148621
Short name T1361
Test name
Test status
Simulation time 6172808015 ps
CPU time 45.71 seconds
Started Jul 20 06:23:45 PM PDT 24
Finished Jul 20 06:24:34 PM PDT 24
Peak memory 206800 kb
Host smart-96b50ab2-9196-4514-a296-27caa8835503
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3743148621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.3743148621
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2722233208
Short name T2385
Test name
Test status
Simulation time 169217420 ps
CPU time 0.81 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 206632 kb
Host smart-5c38f7c3-7b9e-4986-8e3f-ebad863ce8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27222
33208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2722233208
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1347422719
Short name T399
Test name
Test status
Simulation time 182336028 ps
CPU time 0.84 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206648 kb
Host smart-8684813b-d28e-42e9-95d8-90f39dba4020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13474
22719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1347422719
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.2359203351
Short name T1771
Test name
Test status
Simulation time 1145278508 ps
CPU time 2.74 seconds
Started Jul 20 06:23:41 PM PDT 24
Finished Jul 20 06:23:44 PM PDT 24
Peak memory 206776 kb
Host smart-50d043b6-226c-4fd2-b1af-0d5bee19558d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23592
03351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.2359203351
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.1564885882
Short name T2206
Test name
Test status
Simulation time 7383569450 ps
CPU time 212.04 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206896 kb
Host smart-b6543a7d-3d5e-46c3-b459-7712c5a65b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15648
85882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.1564885882
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.929478992
Short name T2510
Test name
Test status
Simulation time 44380673 ps
CPU time 0.79 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206668 kb
Host smart-63cec921-53b9-4b8c-a6db-eec3402e4088
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=929478992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.929478992
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.618952077
Short name T1429
Test name
Test status
Simulation time 3816214677 ps
CPU time 4.92 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:50 PM PDT 24
Peak memory 206808 kb
Host smart-9eede6dc-bec7-4a49-9cc0-40221f682f3e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=618952077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.618952077
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3115735275
Short name T1681
Test name
Test status
Simulation time 13352146043 ps
CPU time 13.71 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:24:01 PM PDT 24
Peak memory 206868 kb
Host smart-a1012966-fb5f-4f45-9b74-047494b31edb
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3115735275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3115735275
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.690196881
Short name T673
Test name
Test status
Simulation time 190944511 ps
CPU time 0.89 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 206652 kb
Host smart-83d9d260-9943-4de6-b9b7-eeca4188a328
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69019
6881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.690196881
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1597942840
Short name T2688
Test name
Test status
Simulation time 162353520 ps
CPU time 0.76 seconds
Started Jul 20 06:23:41 PM PDT 24
Finished Jul 20 06:23:42 PM PDT 24
Peak memory 206652 kb
Host smart-ae247fde-ba44-4456-93b3-0441a5ae6dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15979
42840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1597942840
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.115264784
Short name T2365
Test name
Test status
Simulation time 161685526 ps
CPU time 0.8 seconds
Started Jul 20 06:23:39 PM PDT 24
Finished Jul 20 06:23:41 PM PDT 24
Peak memory 206656 kb
Host smart-670525a9-a3e1-4744-90a8-06895cd21977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11526
4784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.115264784
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.1975543405
Short name T531
Test name
Test status
Simulation time 548461363 ps
CPU time 1.55 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:23:47 PM PDT 24
Peak memory 206656 kb
Host smart-c4774402-89d2-473b-94e4-2b478016a6e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
43405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.1975543405
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.3270996146
Short name T806
Test name
Test status
Simulation time 501873105 ps
CPU time 1.48 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:45 PM PDT 24
Peak memory 206660 kb
Host smart-7da1007d-7513-43b4-82c7-4cc1ac15cc9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32709
96146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.3270996146
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.2258707105
Short name T1553
Test name
Test status
Simulation time 145597547 ps
CPU time 0.74 seconds
Started Jul 20 06:23:45 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206648 kb
Host smart-8e1e8ad1-d19b-430e-9089-76c32227cc4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22587
07105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.2258707105
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.3210129312
Short name T706
Test name
Test status
Simulation time 41754753 ps
CPU time 0.67 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:23:50 PM PDT 24
Peak memory 206620 kb
Host smart-4a640a93-3151-4fe3-aa1c-437fba0af4be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32101
29312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.3210129312
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.4175747680
Short name T1751
Test name
Test status
Simulation time 893957445 ps
CPU time 2.19 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206720 kb
Host smart-8d33c5eb-d6b9-489d-a689-3fbf7518be89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41757
47680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.4175747680
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3067963123
Short name T1867
Test name
Test status
Simulation time 175453098 ps
CPU time 1.49 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206448 kb
Host smart-76ad8b8d-f0fc-42eb-91c7-e1f095980092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30679
63123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3067963123
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.2510676163
Short name T2648
Test name
Test status
Simulation time 167894229 ps
CPU time 0.91 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:23:47 PM PDT 24
Peak memory 206588 kb
Host smart-0ca66196-0513-4f3d-b2a2-395b3d77f4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25106
76163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.2510676163
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.1653350600
Short name T522
Test name
Test status
Simulation time 178009696 ps
CPU time 0.83 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:44 PM PDT 24
Peak memory 206652 kb
Host smart-4c5286d2-2d27-4a0d-b5e0-c8091188c277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16533
50600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.1653350600
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.322385307
Short name T1554
Test name
Test status
Simulation time 215515949 ps
CPU time 0.97 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:48 PM PDT 24
Peak memory 206652 kb
Host smart-e00469ea-bcf1-45f3-93b3-831c2ac0bb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32238
5307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.322385307
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.3804967101
Short name T98
Test name
Test status
Simulation time 7026683093 ps
CPU time 194.89 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:27:02 PM PDT 24
Peak memory 206876 kb
Host smart-a7cb13ef-737a-49bd-971f-4824ea8e3100
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3804967101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.3804967101
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1381616065
Short name T388
Test name
Test status
Simulation time 5942215835 ps
CPU time 51.02 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:24:41 PM PDT 24
Peak memory 206648 kb
Host smart-dfda3c15-0969-4016-b9b3-1cedc1d66d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13816
16065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1381616065
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2895407988
Short name T804
Test name
Test status
Simulation time 212557132 ps
CPU time 0.91 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206656 kb
Host smart-05bd2b67-dcb2-483f-aca6-908c0d7cd3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28954
07988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2895407988
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.76354308
Short name T2515
Test name
Test status
Simulation time 23352642184 ps
CPU time 21.38 seconds
Started Jul 20 06:23:45 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206756 kb
Host smart-75a5ea47-e7ae-4132-892b-b6ee469b85a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76354
308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.76354308
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1744161412
Short name T2533
Test name
Test status
Simulation time 3291563345 ps
CPU time 3.81 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:54 PM PDT 24
Peak memory 206724 kb
Host smart-05ef7954-f100-49d2-a875-28ec51fb6677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17441
61412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1744161412
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.2838554508
Short name T633
Test name
Test status
Simulation time 9314769436 ps
CPU time 66.02 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206968 kb
Host smart-9c3e3769-0f66-4c72-a4b8-4a4c0d0867a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28385
54508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.2838554508
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.420233629
Short name T1270
Test name
Test status
Simulation time 4225625127 ps
CPU time 30.26 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206912 kb
Host smart-7217df5c-7233-4f09-9311-ed67e870b322
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=420233629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.420233629
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.2661345307
Short name T1733
Test name
Test status
Simulation time 246168418 ps
CPU time 0.91 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206648 kb
Host smart-32686da4-62d0-4691-8d8e-a6ae3024e801
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2661345307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.2661345307
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1569891180
Short name T24
Test name
Test status
Simulation time 228169133 ps
CPU time 0.94 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:23:50 PM PDT 24
Peak memory 206696 kb
Host smart-2ff4de79-0da4-4f0f-8ed4-e0bcfa1d7642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15698
91180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1569891180
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.19755103
Short name T1947
Test name
Test status
Simulation time 5644435416 ps
CPU time 156.26 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:26:26 PM PDT 24
Peak memory 206876 kb
Host smart-8d00d92f-f133-4ce8-a655-3e233b7966e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.19755103
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.645315906
Short name T1440
Test name
Test status
Simulation time 3693282508 ps
CPU time 26.54 seconds
Started Jul 20 06:23:47 PM PDT 24
Finished Jul 20 06:24:16 PM PDT 24
Peak memory 206892 kb
Host smart-e6eba898-ec01-4b90-8404-81e4e55106de
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=645315906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.645315906
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2115747836
Short name T464
Test name
Test status
Simulation time 191476195 ps
CPU time 0.86 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:48 PM PDT 24
Peak memory 206656 kb
Host smart-f6b6c07e-0fa4-43c3-bfc5-2b202ee87dfc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2115747836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2115747836
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2625836569
Short name T1734
Test name
Test status
Simulation time 153780172 ps
CPU time 0.87 seconds
Started Jul 20 06:23:46 PM PDT 24
Finished Jul 20 06:23:50 PM PDT 24
Peak memory 206636 kb
Host smart-5b0cfd5a-d3a2-490a-8db2-9bb1e38855cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26258
36569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2625836569
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2615224667
Short name T1158
Test name
Test status
Simulation time 192065245 ps
CPU time 0.83 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:48 PM PDT 24
Peak memory 206656 kb
Host smart-1a564d02-df95-4b63-8666-b9decf66c94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26152
24667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2615224667
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.505889574
Short name T1263
Test name
Test status
Simulation time 164537044 ps
CPU time 0.83 seconds
Started Jul 20 06:23:45 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206636 kb
Host smart-736450b1-4e51-453a-8492-e45df5187a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50588
9574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.505889574
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.481258447
Short name T2253
Test name
Test status
Simulation time 236331763 ps
CPU time 0.83 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206648 kb
Host smart-afeff42f-1b84-4e17-a510-078e7ebf6ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48125
8447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.481258447
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3849182739
Short name T1839
Test name
Test status
Simulation time 178855701 ps
CPU time 0.85 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206624 kb
Host smart-49ec6bb1-434b-4ccd-91ce-3d1a20eb848a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38491
82739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3849182739
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.520103085
Short name T2666
Test name
Test status
Simulation time 147903296 ps
CPU time 0.84 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206644 kb
Host smart-b4610126-c487-4c4e-90ea-3549e08a307d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52010
3085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.520103085
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.4236262603
Short name T82
Test name
Test status
Simulation time 236620095 ps
CPU time 1.02 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206664 kb
Host smart-447bc178-de41-40cc-8506-df63db680d3e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4236262603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.4236262603
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1547993869
Short name T2493
Test name
Test status
Simulation time 137762366 ps
CPU time 0.76 seconds
Started Jul 20 06:23:41 PM PDT 24
Finished Jul 20 06:23:43 PM PDT 24
Peak memory 206652 kb
Host smart-1e4301c7-3696-46b8-9740-89b4e2160d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15479
93869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1547993869
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.1839861624
Short name T38
Test name
Test status
Simulation time 45421829 ps
CPU time 0.71 seconds
Started Jul 20 06:23:42 PM PDT 24
Finished Jul 20 06:23:46 PM PDT 24
Peak memory 206644 kb
Host smart-4d72814b-a26e-4605-b2d6-c233aeef2f43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18398
61624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.1839861624
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.176026277
Short name T2501
Test name
Test status
Simulation time 9836418567 ps
CPU time 21.64 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:24:08 PM PDT 24
Peak memory 206892 kb
Host smart-5ca6cdfd-ede5-4394-af8f-3bea0e69aec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17602
6277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.176026277
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1354925700
Short name T2008
Test name
Test status
Simulation time 189015779 ps
CPU time 0.87 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:52 PM PDT 24
Peak memory 206664 kb
Host smart-7c46d90e-de44-40ad-94a5-584a9b3a82e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13549
25700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1354925700
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.3874926347
Short name T1838
Test name
Test status
Simulation time 158771061 ps
CPU time 0.83 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206660 kb
Host smart-dad18709-6b1c-4dd3-94f3-1b82160a0ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38749
26347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.3874926347
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3842914002
Short name T992
Test name
Test status
Simulation time 175746137 ps
CPU time 0.84 seconds
Started Jul 20 06:23:43 PM PDT 24
Finished Jul 20 06:23:47 PM PDT 24
Peak memory 206660 kb
Host smart-780e5b8d-dc51-4c65-a149-e2a7b81cbd10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38429
14002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3842914002
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.744761647
Short name T1507
Test name
Test status
Simulation time 184223089 ps
CPU time 0.8 seconds
Started Jul 20 06:23:48 PM PDT 24
Finished Jul 20 06:23:51 PM PDT 24
Peak memory 206656 kb
Host smart-a477c160-485c-4842-bc8a-c0e32a348188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74476
1647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.744761647
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.269073146
Short name T844
Test name
Test status
Simulation time 197090828 ps
CPU time 0.8 seconds
Started Jul 20 06:23:45 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206656 kb
Host smart-ded2ffa3-09ec-4331-a0a3-b8dcb71b9e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26907
3146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.269073146
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.95364482
Short name T1443
Test name
Test status
Simulation time 148180300 ps
CPU time 0.78 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206656 kb
Host smart-12137109-f2a2-4b69-a1da-2f1888a09ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95364
482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.95364482
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.1496025563
Short name T499
Test name
Test status
Simulation time 142182883 ps
CPU time 0.79 seconds
Started Jul 20 06:23:44 PM PDT 24
Finished Jul 20 06:23:49 PM PDT 24
Peak memory 206656 kb
Host smart-c4aac3d9-e1ea-4265-bc14-de734f3a0c6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14960
25563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.1496025563
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.3511972495
Short name T964
Test name
Test status
Simulation time 242541199 ps
CPU time 0.93 seconds
Started Jul 20 06:23:56 PM PDT 24
Finished Jul 20 06:23:58 PM PDT 24
Peak memory 206632 kb
Host smart-84a6f181-bcd5-45a1-aaa6-a83d7b1f5757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35119
72495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.3511972495
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.875732412
Short name T704
Test name
Test status
Simulation time 3645695152 ps
CPU time 24.91 seconds
Started Jul 20 06:23:55 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206900 kb
Host smart-c8ac9535-7098-48b4-bdc9-138b842a8ee8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=875732412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.875732412
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.429106166
Short name T2076
Test name
Test status
Simulation time 199604229 ps
CPU time 0.88 seconds
Started Jul 20 06:23:56 PM PDT 24
Finished Jul 20 06:23:58 PM PDT 24
Peak memory 206608 kb
Host smart-cee53d2b-7933-4e4d-8605-be6bf866dd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42910
6166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.429106166
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2015939094
Short name T360
Test name
Test status
Simulation time 177116536 ps
CPU time 0.81 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:23:54 PM PDT 24
Peak memory 206652 kb
Host smart-f8d76c4d-aa77-46c7-931f-e7b74e7ba567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20159
39094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2015939094
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.4059069570
Short name T919
Test name
Test status
Simulation time 260904222 ps
CPU time 0.96 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:23:56 PM PDT 24
Peak memory 206644 kb
Host smart-f32ba699-125d-4acf-a0c7-22c0b3f5ad53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40590
69570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.4059069570
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.952197073
Short name T2194
Test name
Test status
Simulation time 3829585422 ps
CPU time 36.76 seconds
Started Jul 20 06:23:55 PM PDT 24
Finished Jul 20 06:24:33 PM PDT 24
Peak memory 206868 kb
Host smart-bb224590-8505-45e8-a0f1-e5f1c462e4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95219
7073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.952197073
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.4027544814
Short name T1294
Test name
Test status
Simulation time 60739289 ps
CPU time 0.7 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:24:12 PM PDT 24
Peak memory 206712 kb
Host smart-8499280b-3a01-4605-830d-7c09d346080a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4027544814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.4027544814
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.3414428081
Short name T2522
Test name
Test status
Simulation time 4388188838 ps
CPU time 5.93 seconds
Started Jul 20 06:23:54 PM PDT 24
Finished Jul 20 06:24:02 PM PDT 24
Peak memory 206864 kb
Host smart-19f387c1-b37e-4271-b123-b44897deba5f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3414428081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.3414428081
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.921714640
Short name T1039
Test name
Test status
Simulation time 13379035954 ps
CPU time 13.43 seconds
Started Jul 20 06:23:59 PM PDT 24
Finished Jul 20 06:24:13 PM PDT 24
Peak memory 206756 kb
Host smart-4a6d910b-92bf-45dc-9b9a-579f2b1212b5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=921714640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.921714640
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1640525324
Short name T616
Test name
Test status
Simulation time 23338586040 ps
CPU time 24.28 seconds
Started Jul 20 06:23:53 PM PDT 24
Finished Jul 20 06:24:19 PM PDT 24
Peak memory 206784 kb
Host smart-ecaa93d0-9665-407a-9fb1-746faced15c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1640525324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1640525324
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.762501145
Short name T2696
Test name
Test status
Simulation time 160275688 ps
CPU time 0.77 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206596 kb
Host smart-7f75fdaf-7d90-4009-aace-6f436576304b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76250
1145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.762501145
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.1877275318
Short name T1608
Test name
Test status
Simulation time 146798750 ps
CPU time 0.78 seconds
Started Jul 20 06:23:59 PM PDT 24
Finished Jul 20 06:24:01 PM PDT 24
Peak memory 206656 kb
Host smart-c95e3a5f-9a80-4730-b543-9851883c9859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18772
75318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.1877275318
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.640142642
Short name T66
Test name
Test status
Simulation time 230092229 ps
CPU time 0.98 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:23:55 PM PDT 24
Peak memory 206644 kb
Host smart-b9e0b727-22f8-46a2-acf3-54356d7ccaf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64014
2642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.640142642
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_device_address.1078706156
Short name T719
Test name
Test status
Simulation time 23060040176 ps
CPU time 44.44 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206852 kb
Host smart-4e90ac10-5d1a-46a9-8474-2abe88c87482
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10787
06156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.1078706156
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.2295086345
Short name T2140
Test name
Test status
Simulation time 364142013 ps
CPU time 1.2 seconds
Started Jul 20 06:23:59 PM PDT 24
Finished Jul 20 06:24:01 PM PDT 24
Peak memory 206652 kb
Host smart-0300e0a7-3607-4469-8c3a-58b624303f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22950
86345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.2295086345
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.1400980096
Short name T694
Test name
Test status
Simulation time 137538745 ps
CPU time 0.78 seconds
Started Jul 20 06:23:54 PM PDT 24
Finished Jul 20 06:23:56 PM PDT 24
Peak memory 206652 kb
Host smart-c9a299d3-d548-4b4e-a485-0c497cdc3615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14009
80096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.1400980096
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.386712677
Short name T1582
Test name
Test status
Simulation time 42946636 ps
CPU time 0.7 seconds
Started Jul 20 06:24:00 PM PDT 24
Finished Jul 20 06:24:01 PM PDT 24
Peak memory 206644 kb
Host smart-7cc9f132-7485-4372-ab6c-06c9e8492105
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38671
2677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.386712677
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.941844754
Short name T2023
Test name
Test status
Simulation time 828455846 ps
CPU time 2.27 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:23:55 PM PDT 24
Peak memory 206728 kb
Host smart-d513792e-a7cf-4f7b-9093-bb09b6ce5deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94184
4754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.941844754
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.350945713
Short name T1501
Test name
Test status
Simulation time 220175782 ps
CPU time 1.46 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:23:55 PM PDT 24
Peak memory 206788 kb
Host smart-5593eda0-240b-4faf-a055-5f9c61bf5768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35094
5713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.350945713
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.1900567244
Short name T1035
Test name
Test status
Simulation time 228134850 ps
CPU time 1.03 seconds
Started Jul 20 06:23:56 PM PDT 24
Finished Jul 20 06:23:58 PM PDT 24
Peak memory 206624 kb
Host smart-69d0f5b5-b3a3-4e42-81ed-8067ea06349f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19005
67244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.1900567244
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1480877325
Short name T1244
Test name
Test status
Simulation time 145267400 ps
CPU time 0.78 seconds
Started Jul 20 06:23:56 PM PDT 24
Finished Jul 20 06:23:58 PM PDT 24
Peak memory 206652 kb
Host smart-82907f40-807d-456f-8771-3e5b4ba3730d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14808
77325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1480877325
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.1270351387
Short name T1389
Test name
Test status
Simulation time 175695812 ps
CPU time 0.83 seconds
Started Jul 20 06:23:49 PM PDT 24
Finished Jul 20 06:23:52 PM PDT 24
Peak memory 206700 kb
Host smart-b3f99909-5d80-4343-a811-1647656c2130
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12703
51387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.1270351387
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_iso_retraction.706219885
Short name T1784
Test name
Test status
Simulation time 8320397117 ps
CPU time 26.29 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:24:19 PM PDT 24
Peak memory 206840 kb
Host smart-b1519ff2-3699-4b9a-95bd-bf11d9807bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70621
9885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_iso_retraction.706219885
Directory /workspace/26.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.1560734632
Short name T479
Test name
Test status
Simulation time 181165795 ps
CPU time 0.79 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:23:54 PM PDT 24
Peak memory 206644 kb
Host smart-3616621c-603f-444e-b897-628aeb6541d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15607
34632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.1560734632
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.2865392700
Short name T1125
Test name
Test status
Simulation time 23336410947 ps
CPU time 24.45 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:24:18 PM PDT 24
Peak memory 206772 kb
Host smart-89298ac8-87f3-448b-ae36-3b257d152885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28653
92700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.2865392700
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2509986523
Short name T1029
Test name
Test status
Simulation time 3323274569 ps
CPU time 4.25 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:23:59 PM PDT 24
Peak memory 206724 kb
Host smart-d381f732-9411-4607-8747-f9a25849dc88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25099
86523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2509986523
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.844858836
Short name T1269
Test name
Test status
Simulation time 10646249962 ps
CPU time 297.93 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:28:51 PM PDT 24
Peak memory 206964 kb
Host smart-d55f52a0-33ba-4d47-b02e-af75c0882e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84485
8836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.844858836
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3989591744
Short name T980
Test name
Test status
Simulation time 5901258725 ps
CPU time 163.17 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206852 kb
Host smart-4492a298-cbe9-41ee-93c9-bcc23ca12e40
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3989591744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3989591744
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3071487009
Short name T958
Test name
Test status
Simulation time 258642523 ps
CPU time 0.95 seconds
Started Jul 20 06:23:54 PM PDT 24
Finished Jul 20 06:23:56 PM PDT 24
Peak memory 206648 kb
Host smart-1e0a1e61-500f-416e-9d7a-e56bbea48c71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3071487009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3071487009
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.2764485630
Short name T872
Test name
Test status
Simulation time 193450140 ps
CPU time 0.93 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:23:55 PM PDT 24
Peak memory 206656 kb
Host smart-556ea3aa-4066-4ecd-9b7d-15ffb0b4c3b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27644
85630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.2764485630
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.2995968769
Short name T795
Test name
Test status
Simulation time 4494952780 ps
CPU time 123.28 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:25:58 PM PDT 24
Peak memory 206848 kb
Host smart-9e6e16d1-2cad-4a45-8378-5f51fe8a52a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29959
68769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.2995968769
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.1992556549
Short name T2472
Test name
Test status
Simulation time 4670375427 ps
CPU time 128.61 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:26:03 PM PDT 24
Peak memory 206864 kb
Host smart-f278875a-6f7c-41b3-9f27-ed566a2bf61d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1992556549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.1992556549
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.4244628651
Short name T968
Test name
Test status
Simulation time 184114543 ps
CPU time 0.88 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206672 kb
Host smart-6728a641-9af4-42ae-ad5a-06d48ec2a497
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4244628651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.4244628651
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.2740649557
Short name T693
Test name
Test status
Simulation time 145225721 ps
CPU time 0.8 seconds
Started Jul 20 06:23:52 PM PDT 24
Finished Jul 20 06:23:56 PM PDT 24
Peak memory 206656 kb
Host smart-b452302b-5968-42f6-9832-61ec69379126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27406
49557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.2740649557
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.1867057867
Short name T2743
Test name
Test status
Simulation time 230380675 ps
CPU time 0.89 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206652 kb
Host smart-0f01129e-c171-48e5-b510-f1bc49897fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18670
57867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.1867057867
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.13688523
Short name T1562
Test name
Test status
Simulation time 186200114 ps
CPU time 0.79 seconds
Started Jul 20 06:24:00 PM PDT 24
Finished Jul 20 06:24:01 PM PDT 24
Peak memory 206648 kb
Host smart-273880f2-34b9-40e6-a666-382ed846dd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13688
523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.13688523
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.2621104427
Short name T1547
Test name
Test status
Simulation time 157063034 ps
CPU time 0.8 seconds
Started Jul 20 06:23:59 PM PDT 24
Finished Jul 20 06:24:01 PM PDT 24
Peak memory 206652 kb
Host smart-626c1f60-8f5a-48ef-a9f9-de076080f26f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26211
04427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.2621104427
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.2767123566
Short name T1288
Test name
Test status
Simulation time 192424196 ps
CPU time 0.81 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:23:54 PM PDT 24
Peak memory 206628 kb
Host smart-48773d3d-710b-4e75-aea9-3a52a590fc68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27671
23566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.2767123566
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.751217233
Short name T1325
Test name
Test status
Simulation time 153235578 ps
CPU time 0.79 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206656 kb
Host smart-b6337c6a-a5b8-4f09-9ee1-e2dba9f11971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75121
7233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.751217233
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1625714615
Short name T510
Test name
Test status
Simulation time 232450594 ps
CPU time 1.02 seconds
Started Jul 20 06:23:54 PM PDT 24
Finished Jul 20 06:23:56 PM PDT 24
Peak memory 206656 kb
Host smart-7e3a403f-bbeb-4149-a369-6f5840203a15
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1625714615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1625714615
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2569276521
Short name T1068
Test name
Test status
Simulation time 151395182 ps
CPU time 0.83 seconds
Started Jul 20 06:23:56 PM PDT 24
Finished Jul 20 06:23:58 PM PDT 24
Peak memory 206664 kb
Host smart-a51df4cb-8fbe-4063-9f0c-268a873451a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25692
76521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2569276521
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3091178964
Short name T2029
Test name
Test status
Simulation time 45392455 ps
CPU time 0.68 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:23:54 PM PDT 24
Peak memory 206628 kb
Host smart-8cf5e705-4db7-48a2-a3f9-009345c19988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30911
78964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3091178964
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.1904647487
Short name T1375
Test name
Test status
Simulation time 13586546140 ps
CPU time 31.23 seconds
Started Jul 20 06:23:50 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206868 kb
Host smart-f4d3d289-3e68-4187-bb98-5a161a962be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19046
47487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.1904647487
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.239013016
Short name T2392
Test name
Test status
Simulation time 204901646 ps
CPU time 0.87 seconds
Started Jul 20 06:23:51 PM PDT 24
Finished Jul 20 06:23:55 PM PDT 24
Peak memory 206648 kb
Host smart-9522eba5-fb36-4eae-9e70-1b53cee360d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23901
3016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.239013016
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3489305369
Short name T1100
Test name
Test status
Simulation time 209393891 ps
CPU time 0.87 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206648 kb
Host smart-ef7827d0-45a4-44a7-8eac-cac73be3b030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
05369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3489305369
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.29021598
Short name T2731
Test name
Test status
Simulation time 289080556 ps
CPU time 0.94 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206660 kb
Host smart-398f9e40-a733-42d0-bef6-7057826859da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29021
598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.29021598
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.412652074
Short name T2382
Test name
Test status
Simulation time 205451407 ps
CPU time 0.86 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:24:12 PM PDT 24
Peak memory 206604 kb
Host smart-1f75bbe2-046b-4b0a-9960-e11889aef42d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41265
2074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.412652074
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.3651902297
Short name T777
Test name
Test status
Simulation time 182288046 ps
CPU time 0.79 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206636 kb
Host smart-01942126-72da-4ad4-a803-065dda472aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36519
02297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.3651902297
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1657434931
Short name T525
Test name
Test status
Simulation time 145769978 ps
CPU time 0.77 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:08 PM PDT 24
Peak memory 206632 kb
Host smart-a99ee95c-999d-4219-a51f-972a14fa23d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16574
34931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1657434931
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.3424334495
Short name T461
Test name
Test status
Simulation time 147025103 ps
CPU time 0.78 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206620 kb
Host smart-2ed99514-3274-4539-835b-73b857ee3746
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34243
34495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.3424334495
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.2120562058
Short name T774
Test name
Test status
Simulation time 191661320 ps
CPU time 0.87 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:13 PM PDT 24
Peak memory 206660 kb
Host smart-8d56eb01-5f34-4f5d-a8eb-78c0c7e60f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21205
62058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.2120562058
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.3973851168
Short name T902
Test name
Test status
Simulation time 4800683512 ps
CPU time 134.74 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:26:21 PM PDT 24
Peak memory 206860 kb
Host smart-1642083c-0ca1-4cbd-ae57-50af82f30b9e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3973851168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.3973851168
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.2403781700
Short name T1456
Test name
Test status
Simulation time 178169126 ps
CPU time 0.82 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:07 PM PDT 24
Peak memory 206624 kb
Host smart-2b5ab9e5-ef12-47b3-afe7-9ab753f31e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24037
81700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.2403781700
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2326238757
Short name T1997
Test name
Test status
Simulation time 180559279 ps
CPU time 0.86 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:08 PM PDT 24
Peak memory 206644 kb
Host smart-0888de41-9ad8-4d1b-b562-eb0beeb4b000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23262
38757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2326238757
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.4098807572
Short name T2144
Test name
Test status
Simulation time 590874915 ps
CPU time 1.49 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:07 PM PDT 24
Peak memory 206632 kb
Host smart-73da4431-8066-44c6-aff6-50e0ae28dbd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40988
07572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.4098807572
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.159309554
Short name T1302
Test name
Test status
Simulation time 4676457089 ps
CPU time 33.77 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206848 kb
Host smart-5fb8cee7-076e-42b1-b4d6-db312251413c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15930
9554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.159309554
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.1037197797
Short name T1317
Test name
Test status
Simulation time 41676209 ps
CPU time 0.67 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:15 PM PDT 24
Peak memory 206632 kb
Host smart-891eb45f-917c-4ef2-b3cd-48515b573632
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1037197797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.1037197797
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.4241424143
Short name T1930
Test name
Test status
Simulation time 4341013935 ps
CPU time 5.69 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:15 PM PDT 24
Peak memory 206836 kb
Host smart-a35a2073-4162-4ddb-82b5-152ba2ab8273
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4241424143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.4241424143
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.825514599
Short name T1037
Test name
Test status
Simulation time 13407465881 ps
CPU time 15.2 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206792 kb
Host smart-58c60c3f-45e2-4251-a399-7a86698ccbb4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=825514599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.825514599
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1964263569
Short name T710
Test name
Test status
Simulation time 23392979625 ps
CPU time 24.29 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:33 PM PDT 24
Peak memory 206852 kb
Host smart-dd8e36d4-fe73-481f-8766-74d626bba1c9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1964263569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1964263569
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.697204781
Short name T1573
Test name
Test status
Simulation time 167772763 ps
CPU time 0.85 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206592 kb
Host smart-2279a80d-2d0f-4cd8-b10c-2c376220d84e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69720
4781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.697204781
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.1407361629
Short name T796
Test name
Test status
Simulation time 155607204 ps
CPU time 0.79 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:07 PM PDT 24
Peak memory 206660 kb
Host smart-c02fd6dd-330c-477b-a6ae-79bd8bd4aaa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
61629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.1407361629
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3864924263
Short name T931
Test name
Test status
Simulation time 563588892 ps
CPU time 1.4 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206652 kb
Host smart-4363ba54-158c-46e9-aac3-824aa81c8b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38649
24263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3864924263
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.3772069335
Short name T437
Test name
Test status
Simulation time 22939612647 ps
CPU time 42.39 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206920 kb
Host smart-6d75f090-4717-4d6b-8da2-a1e97cd5b073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37720
69335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.3772069335
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.1242768724
Short name T2577
Test name
Test status
Simulation time 404017923 ps
CPU time 1.25 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:11 PM PDT 24
Peak memory 206652 kb
Host smart-613298cb-cf4c-4c17-968e-9211bab1aa1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12427
68724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.1242768724
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.2316739619
Short name T2258
Test name
Test status
Simulation time 150759958 ps
CPU time 0.78 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206656 kb
Host smart-b21b18f8-2cb9-4c17-bb22-ba95c0c280c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23167
39619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.2316739619
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.320330414
Short name T864
Test name
Test status
Simulation time 46383450 ps
CPU time 0.73 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206640 kb
Host smart-49e4985d-e6b1-4434-bb42-956a098a4c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32033
0414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.320330414
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3106717144
Short name T362
Test name
Test status
Simulation time 866020001 ps
CPU time 2.19 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206740 kb
Host smart-f0bfc4d1-bd35-4d41-9e70-f18ae7300344
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
17144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3106717144
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.586357151
Short name T723
Test name
Test status
Simulation time 270553630 ps
CPU time 1.68 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206728 kb
Host smart-984b4c19-fb00-4610-b824-dd0699d3e95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58635
7151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.586357151
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.738893353
Short name T1494
Test name
Test status
Simulation time 215491712 ps
CPU time 0.93 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:24:12 PM PDT 24
Peak memory 206644 kb
Host smart-b5bce24a-ab97-44ee-a67b-6a9a4da3216b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73889
3353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.738893353
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.2687050125
Short name T721
Test name
Test status
Simulation time 138274600 ps
CPU time 0.76 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:24:12 PM PDT 24
Peak memory 206620 kb
Host smart-975fe165-83f4-4259-a2e1-74f33b74e62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26870
50125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.2687050125
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.1876476886
Short name T2585
Test name
Test status
Simulation time 283331296 ps
CPU time 0.93 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:07 PM PDT 24
Peak memory 206628 kb
Host smart-d35c4d25-189f-4eda-aab8-626b29e83f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18764
76886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.1876476886
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.256457231
Short name T1138
Test name
Test status
Simulation time 9472202111 ps
CPU time 75.31 seconds
Started Jul 20 06:24:12 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206904 kb
Host smart-f657c9d5-a5d8-4652-a87f-43b1858c3a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25645
7231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.256457231
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3271432931
Short name T2571
Test name
Test status
Simulation time 178318458 ps
CPU time 0.81 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:06 PM PDT 24
Peak memory 206656 kb
Host smart-6d653a0a-bc1a-4265-9701-97b330b1af67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32714
32931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3271432931
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3124722533
Short name T1422
Test name
Test status
Simulation time 23327979858 ps
CPU time 22.57 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206888 kb
Host smart-226ca831-5285-4abf-8fb8-6ba332a88fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31247
22533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3124722533
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.3128426038
Short name T2544
Test name
Test status
Simulation time 3326414952 ps
CPU time 3.96 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206720 kb
Host smart-a4cedaba-08b8-4793-aa0b-404021ce3161
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31284
26038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.3128426038
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.287821058
Short name T1346
Test name
Test status
Simulation time 8898676982 ps
CPU time 89.17 seconds
Started Jul 20 06:24:04 PM PDT 24
Finished Jul 20 06:25:34 PM PDT 24
Peak memory 206964 kb
Host smart-6c24bf75-8fe0-4522-953c-f88df5392f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28782
1058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.287821058
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.3740600081
Short name T734
Test name
Test status
Simulation time 7045708906 ps
CPU time 52.54 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206876 kb
Host smart-e9631589-3bcc-4646-852f-326959fbce34
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3740600081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.3740600081
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.4153397773
Short name T1576
Test name
Test status
Simulation time 302852696 ps
CPU time 0.99 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206652 kb
Host smart-97ce8cbb-834a-4157-b360-cf1ca3a5b969
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4153397773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.4153397773
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.3605478042
Short name T632
Test name
Test status
Simulation time 205093848 ps
CPU time 0.88 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206652 kb
Host smart-d0f40620-acb5-470f-b4af-3316a9e4caba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36054
78042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.3605478042
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.88065980
Short name T2359
Test name
Test status
Simulation time 3806712574 ps
CPU time 100.84 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:25:53 PM PDT 24
Peak memory 206880 kb
Host smart-04c28ec5-c4aa-4faa-bea9-7bf80d7a2582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88065
980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.88065980
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.1146337815
Short name T1615
Test name
Test status
Simulation time 5347507756 ps
CPU time 149.22 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:26:40 PM PDT 24
Peak memory 206844 kb
Host smart-1731e093-e5fc-48ae-b0cf-4183965ae330
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1146337815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.1146337815
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.835763763
Short name T1088
Test name
Test status
Simulation time 151436899 ps
CPU time 0.75 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206664 kb
Host smart-771af0be-14d6-4a20-8dae-c29edd08c29c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=835763763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.835763763
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.2741324516
Short name T2256
Test name
Test status
Simulation time 183098376 ps
CPU time 0.83 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:16 PM PDT 24
Peak memory 206652 kb
Host smart-c00ad37a-ebe1-4e5f-8145-1173978ae0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
24516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.2741324516
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.1566340262
Short name T2370
Test name
Test status
Simulation time 235248903 ps
CPU time 0.85 seconds
Started Jul 20 06:24:05 PM PDT 24
Finished Jul 20 06:24:06 PM PDT 24
Peak memory 206700 kb
Host smart-3c27a957-f70d-4909-8325-8091359ff3b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15663
40262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.1566340262
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3535831823
Short name T2300
Test name
Test status
Simulation time 181731520 ps
CPU time 0.87 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206672 kb
Host smart-fe83d983-0ab1-41c5-8975-3c24b2847979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35358
31823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3535831823
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3111837559
Short name T1274
Test name
Test status
Simulation time 200859883 ps
CPU time 0.85 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206664 kb
Host smart-077bd421-0eeb-45ba-9a07-1ac8a6967579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31118
37559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3111837559
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2863199926
Short name T1351
Test name
Test status
Simulation time 164697628 ps
CPU time 0.81 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:24:12 PM PDT 24
Peak memory 206624 kb
Host smart-46469f7e-d02f-4b5c-bd16-e14cbc7931ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28631
99926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2863199926
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.624186334
Short name T168
Test name
Test status
Simulation time 161377042 ps
CPU time 0.78 seconds
Started Jul 20 06:24:10 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206388 kb
Host smart-e6a62b82-02f7-4c2f-9031-cda99a35ee6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62418
6334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.624186334
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2105381207
Short name T18
Test name
Test status
Simulation time 192165991 ps
CPU time 0.87 seconds
Started Jul 20 06:24:06 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206652 kb
Host smart-d41d4817-d2fa-4dda-be4f-a67113c090c0
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2105381207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2105381207
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2179268170
Short name T515
Test name
Test status
Simulation time 141573436 ps
CPU time 0.77 seconds
Started Jul 20 06:24:10 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206464 kb
Host smart-5e3560a6-0c37-4934-a518-245cc53b94ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21792
68170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2179268170
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.2172836839
Short name T2374
Test name
Test status
Simulation time 32844047 ps
CPU time 0.66 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:11 PM PDT 24
Peak memory 206620 kb
Host smart-9361de2b-7449-4604-9c21-14cd00f4dc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21728
36839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.2172836839
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.3809868804
Short name T1489
Test name
Test status
Simulation time 8610337609 ps
CPU time 19.77 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 215140 kb
Host smart-cb0fb85f-258e-4298-9019-5edf1264579e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38098
68804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.3809868804
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.2806231483
Short name T1569
Test name
Test status
Simulation time 176492568 ps
CPU time 0.84 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206656 kb
Host smart-69c2c272-af3e-43b8-8318-f04b7b1f93b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28062
31483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.2806231483
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.86230077
Short name T1572
Test name
Test status
Simulation time 184326098 ps
CPU time 0.83 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206660 kb
Host smart-d51f3526-3beb-4e21-9233-5170bf17835d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86230
077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.86230077
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.1372560104
Short name T2238
Test name
Test status
Simulation time 279907821 ps
CPU time 0.94 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206648 kb
Host smart-18582e6d-5b70-4bf4-9415-84fe5cd414c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13725
60104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.1372560104
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.2508073298
Short name T1693
Test name
Test status
Simulation time 179363645 ps
CPU time 0.87 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:16 PM PDT 24
Peak memory 206648 kb
Host smart-ab3b5183-fe49-49aa-a8b0-3e05df35634a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25080
73298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.2508073298
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.1121950419
Short name T1461
Test name
Test status
Simulation time 173645272 ps
CPU time 0.85 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:16 PM PDT 24
Peak memory 206648 kb
Host smart-3eb3d391-e60c-419e-a898-eae2ace07f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
50419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.1121950419
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3673845937
Short name T1702
Test name
Test status
Simulation time 158998592 ps
CPU time 0.81 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206640 kb
Host smart-77288a6d-1094-47a1-9d3f-deeb03d87ce9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36738
45937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3673845937
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.1724407619
Short name T1369
Test name
Test status
Simulation time 226589763 ps
CPU time 0.88 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206640 kb
Host smart-93b87f2c-f86a-4876-abbb-3d6bf7d46fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17244
07619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.1724407619
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1988588882
Short name T1789
Test name
Test status
Simulation time 296819199 ps
CPU time 1.01 seconds
Started Jul 20 06:24:10 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206640 kb
Host smart-d9e6c62c-5f6b-4ed3-8dad-86738ff5f0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19885
88882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1988588882
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3098743368
Short name T1332
Test name
Test status
Simulation time 6158844513 ps
CPU time 58.25 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206892 kb
Host smart-38e31106-df9c-4741-97cc-6ff2b756e891
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3098743368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3098743368
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.1293054685
Short name T1920
Test name
Test status
Simulation time 159442782 ps
CPU time 0.81 seconds
Started Jul 20 06:24:07 PM PDT 24
Finished Jul 20 06:24:10 PM PDT 24
Peak memory 206652 kb
Host smart-a387f270-9786-4566-97e2-f675640d21ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12930
54685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.1293054685
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.847002157
Short name T323
Test name
Test status
Simulation time 182974880 ps
CPU time 0.82 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206636 kb
Host smart-bcf83207-b207-42ab-8f9d-183c5b68b446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84700
2157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.847002157
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.4117641757
Short name T2531
Test name
Test status
Simulation time 579956277 ps
CPU time 1.53 seconds
Started Jul 20 06:24:10 PM PDT 24
Finished Jul 20 06:24:15 PM PDT 24
Peak memory 206628 kb
Host smart-dcd5d608-38cc-4ef8-b304-c855ad05ecc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41176
41757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.4117641757
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.1398320528
Short name T167
Test name
Test status
Simulation time 5654953382 ps
CPU time 38.83 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:54 PM PDT 24
Peak memory 206820 kb
Host smart-bb4f2ea5-595a-4483-a29d-b59f184c6054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13983
20528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.1398320528
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.1221364606
Short name T631
Test name
Test status
Simulation time 30761405 ps
CPU time 0.67 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206672 kb
Host smart-d5e479e5-0d0c-496c-b2f4-6c7023105da2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1221364606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.1221364606
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.1829613858
Short name T10
Test name
Test status
Simulation time 3837437172 ps
CPU time 4.75 seconds
Started Jul 20 06:24:12 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206716 kb
Host smart-589b4956-444d-4bc8-a139-1212231f9ad6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1829613858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.1829613858
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.3004239791
Short name T1986
Test name
Test status
Simulation time 13383530555 ps
CPU time 16.21 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 206784 kb
Host smart-20f7f8ac-c4bd-475c-9d26-e16050bbca1a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3004239791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.3004239791
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.83946135
Short name T13
Test name
Test status
Simulation time 23366274921 ps
CPU time 22.56 seconds
Started Jul 20 06:24:10 PM PDT 24
Finished Jul 20 06:24:36 PM PDT 24
Peak memory 206772 kb
Host smart-3284c532-d698-4ffe-86b3-a25633124edf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=83946135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.83946135
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.1617504852
Short name T672
Test name
Test status
Simulation time 213350686 ps
CPU time 0.83 seconds
Started Jul 20 06:24:10 PM PDT 24
Finished Jul 20 06:24:14 PM PDT 24
Peak memory 206656 kb
Host smart-1b596b07-9558-44ac-bff9-543f1165ebb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16175
04852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.1617504852
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.3052226909
Short name T1682
Test name
Test status
Simulation time 158843909 ps
CPU time 0.77 seconds
Started Jul 20 06:24:10 PM PDT 24
Finished Jul 20 06:24:15 PM PDT 24
Peak memory 206660 kb
Host smart-cd4efd85-eff7-42a9-a45b-776923f31fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
26909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.3052226909
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2228853324
Short name T2682
Test name
Test status
Simulation time 456293622 ps
CPU time 1.43 seconds
Started Jul 20 06:24:12 PM PDT 24
Finished Jul 20 06:24:18 PM PDT 24
Peak memory 206644 kb
Host smart-6f723b54-175b-4e1a-b996-038ede4bc162
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22288
53324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2228853324
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.3338932940
Short name T2395
Test name
Test status
Simulation time 794777932 ps
CPU time 1.87 seconds
Started Jul 20 06:24:11 PM PDT 24
Finished Jul 20 06:24:16 PM PDT 24
Peak memory 206760 kb
Host smart-199919c0-9251-41ce-acd8-fae3546b69f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33389
32940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.3338932940
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.3890758700
Short name T1191
Test name
Test status
Simulation time 6931781823 ps
CPU time 12.99 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206924 kb
Host smart-8456e3ea-d601-4f37-bd6f-383caaff53e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38907
58700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.3890758700
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.73665995
Short name T769
Test name
Test status
Simulation time 514589204 ps
CPU time 1.42 seconds
Started Jul 20 06:24:12 PM PDT 24
Finished Jul 20 06:24:18 PM PDT 24
Peak memory 206648 kb
Host smart-cb14b6cc-1576-4aa5-98fe-ebd4ed60e2f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73665
995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.73665995
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.2441148271
Short name T1418
Test name
Test status
Simulation time 147983215 ps
CPU time 0.82 seconds
Started Jul 20 06:24:08 PM PDT 24
Finished Jul 20 06:24:13 PM PDT 24
Peak memory 206668 kb
Host smart-c3c51051-e634-4e38-8537-1c77ec724120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24411
48271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.2441148271
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.3895638247
Short name T569
Test name
Test status
Simulation time 43408259 ps
CPU time 0.65 seconds
Started Jul 20 06:24:09 PM PDT 24
Finished Jul 20 06:24:13 PM PDT 24
Peak memory 206640 kb
Host smart-565db1b5-2c46-449c-bf53-ae74ba0af5d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38956
38247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.3895638247
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.1078584912
Short name T1407
Test name
Test status
Simulation time 974472000 ps
CPU time 2.31 seconds
Started Jul 20 06:24:13 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206796 kb
Host smart-2ca9074b-33db-4efd-8f1e-6732d67765ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10785
84912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.1078584912
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.3417313979
Short name T2655
Test name
Test status
Simulation time 196778583 ps
CPU time 1.49 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206664 kb
Host smart-fbe4b8b0-2b0d-4253-8bed-482f9962954c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34173
13979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.3417313979
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.2122726186
Short name T1118
Test name
Test status
Simulation time 222615687 ps
CPU time 0.87 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:19 PM PDT 24
Peak memory 206536 kb
Host smart-9aec3ed3-62bc-42cc-86e4-04349f275a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
26186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.2122726186
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.61143919
Short name T560
Test name
Test status
Simulation time 135721726 ps
CPU time 0.8 seconds
Started Jul 20 06:24:13 PM PDT 24
Finished Jul 20 06:24:18 PM PDT 24
Peak memory 206644 kb
Host smart-9d4515b5-0b6f-4669-91f1-b5e9337c50af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61143
919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.61143919
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3274353447
Short name T2240
Test name
Test status
Simulation time 167610563 ps
CPU time 0.84 seconds
Started Jul 20 06:24:13 PM PDT 24
Finished Jul 20 06:24:18 PM PDT 24
Peak memory 206652 kb
Host smart-aa99e592-4eae-4583-b24f-31291560b8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32743
53447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3274353447
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.2386481946
Short name T246
Test name
Test status
Simulation time 12902182850 ps
CPU time 111.16 seconds
Started Jul 20 06:24:13 PM PDT 24
Finished Jul 20 06:26:08 PM PDT 24
Peak memory 206920 kb
Host smart-14f28541-7f84-470b-ad84-9a3840ea1a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23864
81946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.2386481946
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.3590422118
Short name T970
Test name
Test status
Simulation time 175019251 ps
CPU time 0.8 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206656 kb
Host smart-3a0e7753-6382-4d45-a2bf-61c9a704411c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35904
22118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.3590422118
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.68056187
Short name T660
Test name
Test status
Simulation time 23343386687 ps
CPU time 25.46 seconds
Started Jul 20 06:24:17 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206752 kb
Host smart-a499f5b6-6f76-45ea-8630-1cece28a3dfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68056
187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.68056187
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3696434517
Short name T1596
Test name
Test status
Simulation time 3335110825 ps
CPU time 3.64 seconds
Started Jul 20 06:24:20 PM PDT 24
Finished Jul 20 06:24:27 PM PDT 24
Peak memory 206716 kb
Host smart-d46b1f26-2e77-47b6-ab63-e0148c35da1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36964
34517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3696434517
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.991928914
Short name T463
Test name
Test status
Simulation time 8570522711 ps
CPU time 235.52 seconds
Started Jul 20 06:24:15 PM PDT 24
Finished Jul 20 06:28:14 PM PDT 24
Peak memory 206940 kb
Host smart-dcab2e7e-b3b4-400f-98b1-4e0042fa0c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99192
8914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.991928914
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3805593120
Short name T1224
Test name
Test status
Simulation time 3939245170 ps
CPU time 26.71 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:49 PM PDT 24
Peak memory 206876 kb
Host smart-31629e4d-279b-43e7-94d8-d216b7550dc6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3805593120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3805593120
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.682823581
Short name T1663
Test name
Test status
Simulation time 264961141 ps
CPU time 1.03 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206616 kb
Host smart-df9d6d6a-0b9c-4070-8c52-886ec3a0d33d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=682823581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.682823581
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.3890124324
Short name T343
Test name
Test status
Simulation time 186211575 ps
CPU time 0.88 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:19 PM PDT 24
Peak memory 206652 kb
Host smart-9993c51c-7fc8-43a4-9901-7d0a8de45512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38901
24324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.3890124324
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3153176889
Short name T740
Test name
Test status
Simulation time 5874538954 ps
CPU time 40.83 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206920 kb
Host smart-3077ede6-f7e0-4529-8dee-25cfac61f151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31531
76889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3153176889
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3298829119
Short name T2397
Test name
Test status
Simulation time 5717308463 ps
CPU time 165.73 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206880 kb
Host smart-a1279975-a943-4b40-adce-5c0634b46473
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3298829119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3298829119
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.1041580809
Short name T983
Test name
Test status
Simulation time 161011660 ps
CPU time 0.85 seconds
Started Jul 20 06:24:15 PM PDT 24
Finished Jul 20 06:24:19 PM PDT 24
Peak memory 206660 kb
Host smart-5715ce2e-693c-4105-8a45-c365316048a2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1041580809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.1041580809
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.2526716785
Short name T1852
Test name
Test status
Simulation time 155767995 ps
CPU time 0.79 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206696 kb
Host smart-1008a730-4a19-493b-966c-35a2efb58fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25267
16785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.2526716785
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.2653730544
Short name T118
Test name
Test status
Simulation time 178916477 ps
CPU time 0.87 seconds
Started Jul 20 06:24:15 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206644 kb
Host smart-60e830e8-05d7-45a9-a7cd-6fced3457821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26537
30544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.2653730544
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.3117979478
Short name T1127
Test name
Test status
Simulation time 171011154 ps
CPU time 0.87 seconds
Started Jul 20 06:24:18 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206652 kb
Host smart-546e2d2d-8aa5-4b23-8d4a-d64ab64a3bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31179
79478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.3117979478
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1658977398
Short name T391
Test name
Test status
Simulation time 186097200 ps
CPU time 0.85 seconds
Started Jul 20 06:24:18 PM PDT 24
Finished Jul 20 06:24:22 PM PDT 24
Peak memory 206652 kb
Host smart-a22892bc-7458-428a-8c4c-488a02470375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16589
77398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1658977398
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.720798246
Short name T2219
Test name
Test status
Simulation time 171402588 ps
CPU time 0.81 seconds
Started Jul 20 06:24:17 PM PDT 24
Finished Jul 20 06:24:22 PM PDT 24
Peak memory 206644 kb
Host smart-7e120776-d13b-4f27-a07d-c9330f8ef6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72079
8246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.720798246
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.1632946989
Short name T2503
Test name
Test status
Simulation time 203787068 ps
CPU time 0.85 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206652 kb
Host smart-469d7cd0-1c4b-4f9d-9461-dc1f6b747ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16329
46989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.1632946989
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3043953971
Short name T2325
Test name
Test status
Simulation time 173252785 ps
CPU time 0.89 seconds
Started Jul 20 06:24:22 PM PDT 24
Finished Jul 20 06:24:25 PM PDT 24
Peak memory 206648 kb
Host smart-fdd71270-ac5b-4bb0-b32c-4a4d57ae6744
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3043953971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3043953971
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1649425811
Short name T899
Test name
Test status
Simulation time 133482684 ps
CPU time 0.79 seconds
Started Jul 20 06:24:12 PM PDT 24
Finished Jul 20 06:24:17 PM PDT 24
Peak memory 206644 kb
Host smart-bfedbb47-cfa0-4df0-8e10-965b375574a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16494
25811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1649425811
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.3322830050
Short name T26
Test name
Test status
Simulation time 69106052 ps
CPU time 0.68 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206648 kb
Host smart-08c42fdb-75e8-4047-b9fb-83e8397918a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
30050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.3322830050
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.359707230
Short name T274
Test name
Test status
Simulation time 15965999949 ps
CPU time 33.59 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206908 kb
Host smart-3ac6a9a1-dc1f-4fce-a59b-f65c5820e21e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35970
7230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.359707230
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2694844234
Short name T204
Test name
Test status
Simulation time 173550049 ps
CPU time 0.81 seconds
Started Jul 20 06:24:20 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206652 kb
Host smart-e3d22abd-ee83-4e2a-beb8-9c1b41aae0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
44234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2694844234
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1468249886
Short name T1196
Test name
Test status
Simulation time 214388562 ps
CPU time 0.89 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206664 kb
Host smart-0284a98f-3d3e-4475-8bf9-a611561bcbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14682
49886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1468249886
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3225637018
Short name T1064
Test name
Test status
Simulation time 174537594 ps
CPU time 0.8 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206660 kb
Host smart-4aa38c14-006f-4c7b-9f45-60e8e7549ba1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32256
37018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3225637018
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.3548578153
Short name T2393
Test name
Test status
Simulation time 138032188 ps
CPU time 0.79 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206624 kb
Host smart-28ecaf7a-eb00-4c99-b106-2bd15ac1657e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35485
78153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.3548578153
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.1724952143
Short name T838
Test name
Test status
Simulation time 146766798 ps
CPU time 0.77 seconds
Started Jul 20 06:24:15 PM PDT 24
Finished Jul 20 06:24:19 PM PDT 24
Peak memory 206636 kb
Host smart-ecc11ed9-1648-42ab-98dd-70a97f711d6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17249
52143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.1724952143
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3487943417
Short name T2178
Test name
Test status
Simulation time 145553419 ps
CPU time 0.8 seconds
Started Jul 20 06:24:20 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206648 kb
Host smart-54141916-bd40-4cc2-8c0a-dc628b5cec31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34879
43417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3487943417
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.3519465080
Short name T2108
Test name
Test status
Simulation time 148180097 ps
CPU time 0.82 seconds
Started Jul 20 06:24:17 PM PDT 24
Finished Jul 20 06:24:22 PM PDT 24
Peak memory 206628 kb
Host smart-48a9f98d-457b-4a5a-96c5-1032b39d5237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35194
65080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.3519465080
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.1424594051
Short name T2042
Test name
Test status
Simulation time 213973624 ps
CPU time 0.96 seconds
Started Jul 20 06:24:18 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206616 kb
Host smart-a29d8082-e4f6-40db-acdd-74899582910a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14245
94051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.1424594051
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.174777085
Short name T2478
Test name
Test status
Simulation time 5272842187 ps
CPU time 150.89 seconds
Started Jul 20 06:24:20 PM PDT 24
Finished Jul 20 06:26:54 PM PDT 24
Peak memory 206916 kb
Host smart-8c3ef01c-0724-43b8-8980-1a561734e8f5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=174777085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.174777085
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1824428480
Short name T2616
Test name
Test status
Simulation time 185136374 ps
CPU time 0.82 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206652 kb
Host smart-8ca2093c-86f9-4534-bc51-2ec5443728f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18244
28480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1824428480
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.2036018577
Short name T2429
Test name
Test status
Simulation time 177365416 ps
CPU time 0.82 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206672 kb
Host smart-6fddf508-e2b8-471d-9384-c8c51130de4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20360
18577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.2036018577
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.4256800580
Short name T2134
Test name
Test status
Simulation time 1062706399 ps
CPU time 2.2 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:22 PM PDT 24
Peak memory 206776 kb
Host smart-1c93ca49-1f64-4b38-affb-ebaf4a1a0687
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42568
00580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.4256800580
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.246208902
Short name T2654
Test name
Test status
Simulation time 41186901 ps
CPU time 0.67 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206692 kb
Host smart-20082978-bd77-4525-914c-96aeecd439a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=246208902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.246208902
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1998220272
Short name T473
Test name
Test status
Simulation time 4410922743 ps
CPU time 5.73 seconds
Started Jul 20 06:24:15 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206716 kb
Host smart-c52b72b4-7e5f-4319-8c20-7ff7b4a9ac45
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1998220272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1998220272
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.3607192093
Short name T2733
Test name
Test status
Simulation time 13342281828 ps
CPU time 15.26 seconds
Started Jul 20 06:24:21 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206696 kb
Host smart-4b825078-4750-4012-a7b0-e63f73953f71
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3607192093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.3607192093
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3796177070
Short name T600
Test name
Test status
Simulation time 23411990585 ps
CPU time 26.36 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206784 kb
Host smart-8620b47e-e0a2-4190-b2d4-97e68cf1bdac
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3796177070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3796177070
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.2716781503
Short name T1829
Test name
Test status
Simulation time 186854473 ps
CPU time 0.85 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:19 PM PDT 24
Peak memory 206648 kb
Host smart-4b9e5153-91a3-410a-b566-d170781f0007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27167
81503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.2716781503
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3007187219
Short name T1723
Test name
Test status
Simulation time 197313402 ps
CPU time 0.8 seconds
Started Jul 20 06:24:18 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206660 kb
Host smart-cfaafcc4-e562-4098-9c8d-44c47e899805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30071
87219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3007187219
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3437277849
Short name T2180
Test name
Test status
Simulation time 476721688 ps
CPU time 1.41 seconds
Started Jul 20 06:24:19 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206644 kb
Host smart-e03c45fe-b956-43ce-a138-77fcdb566d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34372
77849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3437277849
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2144760880
Short name T2747
Test name
Test status
Simulation time 1211490262 ps
CPU time 2.85 seconds
Started Jul 20 06:24:18 PM PDT 24
Finished Jul 20 06:24:25 PM PDT 24
Peak memory 206740 kb
Host smart-43d2fcf4-1c99-40f9-9016-f8bdc92e3bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21447
60880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2144760880
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.2674559929
Short name T671
Test name
Test status
Simulation time 11054563804 ps
CPU time 21.03 seconds
Started Jul 20 06:24:20 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206900 kb
Host smart-5a151018-d17a-4190-a1a1-cb5940bc130e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26745
59929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.2674559929
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.613312881
Short name T680
Test name
Test status
Simulation time 411653268 ps
CPU time 1.25 seconds
Started Jul 20 06:24:21 PM PDT 24
Finished Jul 20 06:24:25 PM PDT 24
Peak memory 206652 kb
Host smart-14a29a1e-184e-4ded-8af3-47b4e6774dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61331
2881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.613312881
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.931202437
Short name T2614
Test name
Test status
Simulation time 166379068 ps
CPU time 0.83 seconds
Started Jul 20 06:24:17 PM PDT 24
Finished Jul 20 06:24:22 PM PDT 24
Peak memory 206604 kb
Host smart-62773858-4b79-4af1-98f0-88b0de20cb9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93120
2437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.931202437
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2748030691
Short name T2416
Test name
Test status
Simulation time 38057029 ps
CPU time 0.69 seconds
Started Jul 20 06:24:21 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 206304 kb
Host smart-21335717-1d04-42d3-be84-5df066f58fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27480
30691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2748030691
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.780271752
Short name T1040
Test name
Test status
Simulation time 969080326 ps
CPU time 2.49 seconds
Started Jul 20 06:24:17 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206712 kb
Host smart-37c19513-f2bf-4bd8-b991-4e56ba43d80d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78027
1752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.780271752
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.468636533
Short name T2436
Test name
Test status
Simulation time 182216879 ps
CPU time 1.75 seconds
Started Jul 20 06:24:15 PM PDT 24
Finished Jul 20 06:24:21 PM PDT 24
Peak memory 206792 kb
Host smart-795fc2d0-d0ca-4acd-8301-1dc00d614686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46863
6533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.468636533
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1389030032
Short name T2679
Test name
Test status
Simulation time 174199634 ps
CPU time 0.81 seconds
Started Jul 20 06:24:14 PM PDT 24
Finished Jul 20 06:24:18 PM PDT 24
Peak memory 206640 kb
Host smart-64208332-98c9-404a-ac6c-940d5a39d241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890
30032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1389030032
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.3129517226
Short name T904
Test name
Test status
Simulation time 170969363 ps
CPU time 0.78 seconds
Started Jul 20 06:24:17 PM PDT 24
Finished Jul 20 06:24:22 PM PDT 24
Peak memory 206648 kb
Host smart-4cc6bbae-65e5-4a4d-8548-fc70d496b8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31295
17226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.3129517226
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3694210361
Short name T2377
Test name
Test status
Simulation time 208501968 ps
CPU time 0.9 seconds
Started Jul 20 06:24:18 PM PDT 24
Finished Jul 20 06:24:23 PM PDT 24
Peak memory 206624 kb
Host smart-ebac4bf5-5738-48e7-bfb7-f036080b4d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36942
10361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3694210361
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.2420805681
Short name T1463
Test name
Test status
Simulation time 13980684733 ps
CPU time 43.19 seconds
Started Jul 20 06:24:15 PM PDT 24
Finished Jul 20 06:25:02 PM PDT 24
Peak memory 206836 kb
Host smart-3a2a00cb-b8b1-498a-9028-879469df2fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24208
05681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.2420805681
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.2101170368
Short name T2465
Test name
Test status
Simulation time 185851499 ps
CPU time 0.84 seconds
Started Jul 20 06:24:16 PM PDT 24
Finished Jul 20 06:24:20 PM PDT 24
Peak memory 206656 kb
Host smart-53841ab9-468d-444e-9513-1ee09d486ce8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21011
70368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.2101170368
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.3181633213
Short name T462
Test name
Test status
Simulation time 23331779924 ps
CPU time 27.78 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206776 kb
Host smart-b006e312-9f23-4367-bed2-518419be08b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31816
33213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.3181633213
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.4158264918
Short name T1102
Test name
Test status
Simulation time 3287808345 ps
CPU time 3.73 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206716 kb
Host smart-48d58db3-dc42-4b0f-9d2e-a7cbdb38a986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41582
64918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.4158264918
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1336831954
Short name T1223
Test name
Test status
Simulation time 7399820200 ps
CPU time 201.29 seconds
Started Jul 20 06:24:23 PM PDT 24
Finished Jul 20 06:27:47 PM PDT 24
Peak memory 206940 kb
Host smart-25f83580-1823-4f98-b206-5ecf1cabcda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13368
31954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1336831954
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1940325983
Short name T1466
Test name
Test status
Simulation time 5593912820 ps
CPU time 39.93 seconds
Started Jul 20 06:24:23 PM PDT 24
Finished Jul 20 06:25:06 PM PDT 24
Peak memory 207012 kb
Host smart-128624a7-cb78-4593-a5ba-e8d7ede55e3c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1940325983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1940325983
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.4002588584
Short name T2412
Test name
Test status
Simulation time 237472447 ps
CPU time 0.87 seconds
Started Jul 20 06:24:23 PM PDT 24
Finished Jul 20 06:24:27 PM PDT 24
Peak memory 206656 kb
Host smart-fb60b1f6-de47-4304-8369-a04e231f647b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4002588584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.4002588584
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.940762625
Short name T1611
Test name
Test status
Simulation time 196484555 ps
CPU time 0.88 seconds
Started Jul 20 06:24:27 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 206660 kb
Host smart-f5d21404-5c92-4869-be89-1af91e94c204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94076
2625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.940762625
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3836118267
Short name T2448
Test name
Test status
Simulation time 5043246519 ps
CPU time 46.96 seconds
Started Jul 20 06:24:22 PM PDT 24
Finished Jul 20 06:25:12 PM PDT 24
Peak memory 206952 kb
Host smart-56898e50-7896-4472-94cb-d951529894d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38361
18267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3836118267
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.386528288
Short name T2160
Test name
Test status
Simulation time 6360445736 ps
CPU time 186.24 seconds
Started Jul 20 06:24:24 PM PDT 24
Finished Jul 20 06:27:33 PM PDT 24
Peak memory 206868 kb
Host smart-a136f70c-3a17-424d-9f3c-4a16e922b80c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=386528288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.386528288
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1723092926
Short name T2350
Test name
Test status
Simulation time 198824104 ps
CPU time 0.81 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206652 kb
Host smart-19cbf24f-2aca-450b-b997-077b93caf0fd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1723092926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1723092926
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.1203268044
Short name T2681
Test name
Test status
Simulation time 142810199 ps
CPU time 0.76 seconds
Started Jul 20 06:24:27 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 206656 kb
Host smart-d105601b-0645-45f8-9ea9-ad5b6b50a971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12032
68044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.1203268044
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.160983900
Short name T2408
Test name
Test status
Simulation time 214786761 ps
CPU time 0.86 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206660 kb
Host smart-e85812c1-7f43-4db6-90ad-39c3dba82bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16098
3900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.160983900
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2845364143
Short name T509
Test name
Test status
Simulation time 214582295 ps
CPU time 0.83 seconds
Started Jul 20 06:24:24 PM PDT 24
Finished Jul 20 06:24:28 PM PDT 24
Peak memory 206652 kb
Host smart-60033dda-af82-40c2-821a-077e6fbdc000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28453
64143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2845364143
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.2712947662
Short name T1254
Test name
Test status
Simulation time 180014961 ps
CPU time 0.79 seconds
Started Jul 20 06:24:24 PM PDT 24
Finished Jul 20 06:24:28 PM PDT 24
Peak memory 206664 kb
Host smart-92c5a8ea-cbe0-4a53-8fce-92f7e725f0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27129
47662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.2712947662
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3816479132
Short name T1004
Test name
Test status
Simulation time 169894394 ps
CPU time 0.85 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206660 kb
Host smart-b42a5828-03ae-4ef3-85bf-b5276f7d47b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38164
79132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3816479132
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.97306827
Short name T1536
Test name
Test status
Simulation time 149279484 ps
CPU time 0.76 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206632 kb
Host smart-fde4b257-5c7e-49e0-ac0a-9fb870e70a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97306
827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.97306827
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1734429104
Short name T1820
Test name
Test status
Simulation time 236153457 ps
CPU time 0.95 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206652 kb
Host smart-dad95732-4ecb-4973-b12f-cf90096c028a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1734429104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1734429104
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.3495867905
Short name T739
Test name
Test status
Simulation time 144058273 ps
CPU time 0.8 seconds
Started Jul 20 06:24:27 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 206540 kb
Host smart-3a28366b-ba44-4a42-a314-913ee393b6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34958
67905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.3495867905
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.2530739646
Short name T2161
Test name
Test status
Simulation time 58174469 ps
CPU time 0.69 seconds
Started Jul 20 06:24:26 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206636 kb
Host smart-9803a114-85ea-4f63-9ef5-4be81b994e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25307
39646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.2530739646
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.138445399
Short name T1444
Test name
Test status
Simulation time 13396609637 ps
CPU time 27.4 seconds
Started Jul 20 06:24:26 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206900 kb
Host smart-883cb89f-29e0-42ea-8559-43b82c0705c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13844
5399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.138445399
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.4224344168
Short name T998
Test name
Test status
Simulation time 189124621 ps
CPU time 0.91 seconds
Started Jul 20 06:24:27 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 206656 kb
Host smart-651af530-bfbf-4b3d-bb91-53af47fb6317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42243
44168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.4224344168
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.3534721714
Short name T768
Test name
Test status
Simulation time 233123627 ps
CPU time 0.92 seconds
Started Jul 20 06:24:29 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206660 kb
Host smart-37e5a264-9a43-4986-8443-2385d8c3b50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35347
21714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.3534721714
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.3002143033
Short name T2031
Test name
Test status
Simulation time 202912463 ps
CPU time 0.86 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206652 kb
Host smart-be27865a-ff88-4c55-b1a5-cb20869e71bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30021
43033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.3002143033
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.453775845
Short name T1721
Test name
Test status
Simulation time 184271013 ps
CPU time 0.82 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206644 kb
Host smart-7d2fd324-bb09-4267-a5b5-77e08ad9599f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45377
5845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.453775845
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.3563262413
Short name T924
Test name
Test status
Simulation time 156680028 ps
CPU time 0.77 seconds
Started Jul 20 06:24:26 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206644 kb
Host smart-8ce4f0a2-2ea8-425b-a019-00876f5acd7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35632
62413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.3563262413
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.51499501
Short name T1390
Test name
Test status
Simulation time 150078469 ps
CPU time 0.77 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:28 PM PDT 24
Peak memory 206636 kb
Host smart-e7f2a467-776e-4d08-9a2a-ac663918f17b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51499
501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.51499501
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3990027455
Short name T808
Test name
Test status
Simulation time 167725563 ps
CPU time 0.82 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206592 kb
Host smart-67d9b79e-fe76-4a60-9bb6-36a52bc56b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
27455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3990027455
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2782829095
Short name T2431
Test name
Test status
Simulation time 213640364 ps
CPU time 0.9 seconds
Started Jul 20 06:24:24 PM PDT 24
Finished Jul 20 06:24:28 PM PDT 24
Peak memory 206648 kb
Host smart-ab755640-b1dc-49d6-8032-f4a97a53f11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27828
29095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2782829095
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3139935256
Short name T2697
Test name
Test status
Simulation time 4848354322 ps
CPU time 45.82 seconds
Started Jul 20 06:24:24 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206908 kb
Host smart-5aac06f2-b1df-42b6-9553-082e9d26e508
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3139935256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3139935256
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.48874018
Short name T2162
Test name
Test status
Simulation time 180297100 ps
CPU time 0.81 seconds
Started Jul 20 06:24:24 PM PDT 24
Finished Jul 20 06:24:28 PM PDT 24
Peak memory 206648 kb
Host smart-0597b8be-21c4-4144-a66c-3b5aba676d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48874
018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.48874018
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.2598486669
Short name T1285
Test name
Test status
Simulation time 151422831 ps
CPU time 0.78 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206656 kb
Host smart-d6e8e288-45d2-4e74-8ad4-f5439b8c4618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25984
86669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.2598486669
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.1484835698
Short name T1802
Test name
Test status
Simulation time 1263630555 ps
CPU time 2.7 seconds
Started Jul 20 06:24:24 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 206780 kb
Host smart-89ac2282-8bec-41a1-84f6-dadb1069d11e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14848
35698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.1484835698
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.2487478326
Short name T920
Test name
Test status
Simulation time 4148250004 ps
CPU time 41.66 seconds
Started Jul 20 06:24:26 PM PDT 24
Finished Jul 20 06:25:10 PM PDT 24
Peak memory 206860 kb
Host smart-d4946059-a52d-4d9d-a769-49d0d9fd77e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
78326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.2487478326
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.4054403268
Short name T1968
Test name
Test status
Simulation time 41455946 ps
CPU time 0.66 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:19:36 PM PDT 24
Peak memory 206840 kb
Host smart-8e9a02df-f73e-4a18-9407-fdb80e165b8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4054403268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.4054403268
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.3308849274
Short name T691
Test name
Test status
Simulation time 4041227102 ps
CPU time 4.37 seconds
Started Jul 20 06:19:08 PM PDT 24
Finished Jul 20 06:19:13 PM PDT 24
Peak memory 206756 kb
Host smart-b2bfd59a-2cd7-49b4-98bc-0f5ca03b9b88
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3308849274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.3308849274
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.642231831
Short name T2367
Test name
Test status
Simulation time 13362404730 ps
CPU time 12.55 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:23 PM PDT 24
Peak memory 206752 kb
Host smart-9c3ff037-5ebf-4225-ab65-0fa87f13c354
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=642231831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.642231831
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.4243705494
Short name T1963
Test name
Test status
Simulation time 23416160607 ps
CPU time 21.64 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:32 PM PDT 24
Peak memory 206932 kb
Host smart-64adf27a-88d7-4994-b2d9-c50bee809112
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4243705494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.4243705494
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1149075628
Short name T1117
Test name
Test status
Simulation time 151875410 ps
CPU time 0.82 seconds
Started Jul 20 06:19:14 PM PDT 24
Finished Jul 20 06:19:16 PM PDT 24
Peak memory 206644 kb
Host smart-f5239fcd-a8b8-404e-9287-c4d5d40f5443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11490
75628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1149075628
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.852409033
Short name T53
Test name
Test status
Simulation time 139924153 ps
CPU time 0.79 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:11 PM PDT 24
Peak memory 206632 kb
Host smart-4b9dbcb6-b915-482e-9f91-2c51e67af318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85240
9033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.852409033
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.342436228
Short name T2548
Test name
Test status
Simulation time 203228432 ps
CPU time 0.86 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:10 PM PDT 24
Peak memory 206652 kb
Host smart-3f4abfde-0da6-46cb-8c14-52744bbfc391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34243
6228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.342436228
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3382985930
Short name T2587
Test name
Test status
Simulation time 241099549 ps
CPU time 1.02 seconds
Started Jul 20 06:19:11 PM PDT 24
Finished Jul 20 06:19:13 PM PDT 24
Peak memory 206652 kb
Host smart-bd69085c-5ff0-4af9-b747-5621255a5bbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33829
85930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3382985930
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.2064769459
Short name T593
Test name
Test status
Simulation time 1233422979 ps
CPU time 2.88 seconds
Started Jul 20 06:19:09 PM PDT 24
Finished Jul 20 06:19:14 PM PDT 24
Peak memory 206804 kb
Host smart-8f7600a6-22d1-467d-b7be-9238c03dbc88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20647
69459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.2064769459
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.3179911194
Short name T95
Test name
Test status
Simulation time 17953669595 ps
CPU time 34.5 seconds
Started Jul 20 06:19:16 PM PDT 24
Finished Jul 20 06:19:51 PM PDT 24
Peak memory 206924 kb
Host smart-36256dcb-146d-43ee-a8ce-b8b192ef00b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31799
11194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.3179911194
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.3129585699
Short name T1519
Test name
Test status
Simulation time 443280821 ps
CPU time 1.31 seconds
Started Jul 20 06:19:14 PM PDT 24
Finished Jul 20 06:19:16 PM PDT 24
Peak memory 206700 kb
Host smart-2a8d3d9c-e9ec-479f-9d72-8753dce0954d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31295
85699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.3129585699
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2904705200
Short name T619
Test name
Test status
Simulation time 166815185 ps
CPU time 0.78 seconds
Started Jul 20 06:19:16 PM PDT 24
Finished Jul 20 06:19:18 PM PDT 24
Peak memory 206652 kb
Host smart-bff842ba-5748-461e-8792-0341dbc440f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29047
05200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2904705200
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1608062172
Short name T1055
Test name
Test status
Simulation time 93475608 ps
CPU time 0.7 seconds
Started Jul 20 06:19:16 PM PDT 24
Finished Jul 20 06:19:19 PM PDT 24
Peak memory 206636 kb
Host smart-8935fba2-1123-4e4d-85f5-13142401a1dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16080
62172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1608062172
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.2686481241
Short name T1497
Test name
Test status
Simulation time 772410287 ps
CPU time 1.82 seconds
Started Jul 20 06:19:14 PM PDT 24
Finished Jul 20 06:19:17 PM PDT 24
Peak memory 206716 kb
Host smart-d0e0a189-b6de-4e10-93d8-404791a749b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26864
81241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.2686481241
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1949300692
Short name T1071
Test name
Test status
Simulation time 297614203 ps
CPU time 1.79 seconds
Started Jul 20 06:19:18 PM PDT 24
Finished Jul 20 06:19:21 PM PDT 24
Peak memory 206724 kb
Host smart-ecc60b0d-450b-426a-b0f4-1505aa6abac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19493
00692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1949300692
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.381449456
Short name T1996
Test name
Test status
Simulation time 83188055350 ps
CPU time 115.92 seconds
Started Jul 20 06:19:15 PM PDT 24
Finished Jul 20 06:21:12 PM PDT 24
Peak memory 206888 kb
Host smart-57a2604f-04c4-4d3b-99ff-7f76d5dbb7c7
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=381449456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.381449456
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.873613036
Short name T1498
Test name
Test status
Simulation time 108390667755 ps
CPU time 133.5 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:21:28 PM PDT 24
Peak memory 206936 kb
Host smart-60831cff-08b8-4909-8e3b-2041e68d72fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873613036 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.873613036
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.1981863215
Short name T584
Test name
Test status
Simulation time 120097207990 ps
CPU time 146.9 seconds
Started Jul 20 06:19:17 PM PDT 24
Finished Jul 20 06:21:45 PM PDT 24
Peak memory 206932 kb
Host smart-08c9e5df-0edd-415b-8144-81a03a36943d
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1981863215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.1981863215
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1247278712
Short name T1992
Test name
Test status
Simulation time 84966990872 ps
CPU time 122.67 seconds
Started Jul 20 06:19:15 PM PDT 24
Finished Jul 20 06:21:19 PM PDT 24
Peak memory 206936 kb
Host smart-a5c2cbd5-eb8a-47bf-bb15-ae90d95798ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247278712 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1247278712
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.89494738
Short name T1299
Test name
Test status
Simulation time 118122636993 ps
CPU time 146.9 seconds
Started Jul 20 06:19:17 PM PDT 24
Finished Jul 20 06:21:45 PM PDT 24
Peak memory 206668 kb
Host smart-ec82871c-3c7d-4f65-80f6-136d8fb7d95c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89494
738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.89494738
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1684310889
Short name T1163
Test name
Test status
Simulation time 214442401 ps
CPU time 0.88 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:19:15 PM PDT 24
Peak memory 206640 kb
Host smart-451d7797-1c36-4816-97e8-06c0017c5e36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16843
10889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1684310889
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2237163044
Short name T2373
Test name
Test status
Simulation time 135337911 ps
CPU time 0.76 seconds
Started Jul 20 06:19:15 PM PDT 24
Finished Jul 20 06:19:17 PM PDT 24
Peak memory 206644 kb
Host smart-2235661d-97a2-4b86-a85e-5c050307683b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22371
63044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2237163044
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.444938926
Short name T2312
Test name
Test status
Simulation time 204588118 ps
CPU time 0.89 seconds
Started Jul 20 06:19:12 PM PDT 24
Finished Jul 20 06:19:15 PM PDT 24
Peak memory 206624 kb
Host smart-1630964f-6a00-4816-b3c5-7b431daf47db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44493
8926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.444938926
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3726013651
Short name T209
Test name
Test status
Simulation time 6669308988 ps
CPU time 62.38 seconds
Started Jul 20 06:19:15 PM PDT 24
Finished Jul 20 06:20:18 PM PDT 24
Peak memory 206912 kb
Host smart-7d4c8243-9ba1-4bba-9491-7381384ab041
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3726013651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3726013651
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.3312909893
Short name T1128
Test name
Test status
Simulation time 7280563429 ps
CPU time 62.92 seconds
Started Jul 20 06:19:14 PM PDT 24
Finished Jul 20 06:20:19 PM PDT 24
Peak memory 206904 kb
Host smart-78d039e8-cfd8-4e7a-87d9-26c7d77c788e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33129
09893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.3312909893
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.4217933562
Short name T1934
Test name
Test status
Simulation time 245344423 ps
CPU time 0.97 seconds
Started Jul 20 06:19:16 PM PDT 24
Finished Jul 20 06:19:19 PM PDT 24
Peak memory 206652 kb
Host smart-f5cac68c-03d2-4b65-9d51-dd17fd25953e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42179
33562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.4217933562
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3260439303
Short name T321
Test name
Test status
Simulation time 23346023037 ps
CPU time 23.05 seconds
Started Jul 20 06:19:14 PM PDT 24
Finished Jul 20 06:19:39 PM PDT 24
Peak memory 206776 kb
Host smart-910cae50-4221-4b9c-907b-91a58b0a23f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32604
39303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3260439303
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2988354954
Short name T831
Test name
Test status
Simulation time 3326060866 ps
CPU time 3.87 seconds
Started Jul 20 06:19:14 PM PDT 24
Finished Jul 20 06:19:19 PM PDT 24
Peak memory 206712 kb
Host smart-4c060beb-722f-4b9c-87d0-e3e551ceb90e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29883
54954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2988354954
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.2277295641
Short name T2437
Test name
Test status
Simulation time 8174752380 ps
CPU time 81.16 seconds
Started Jul 20 06:19:16 PM PDT 24
Finished Jul 20 06:20:38 PM PDT 24
Peak memory 206940 kb
Host smart-4b9219a2-5535-4a83-b403-70310cdb43dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22772
95641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.2277295641
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.4205161197
Short name T1754
Test name
Test status
Simulation time 4085815630 ps
CPU time 28.63 seconds
Started Jul 20 06:19:17 PM PDT 24
Finished Jul 20 06:19:47 PM PDT 24
Peak memory 206656 kb
Host smart-4acd0daf-99c4-4919-8aad-1a06ddfbde70
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4205161197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.4205161197
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.2808853335
Short name T1592
Test name
Test status
Simulation time 248217452 ps
CPU time 0.96 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:19:15 PM PDT 24
Peak memory 206640 kb
Host smart-46c1c8ac-531c-41b6-a760-545185f6f888
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2808853335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.2808853335
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.3008103251
Short name T629
Test name
Test status
Simulation time 204319815 ps
CPU time 0.89 seconds
Started Jul 20 06:19:16 PM PDT 24
Finished Jul 20 06:19:18 PM PDT 24
Peak memory 206656 kb
Host smart-1d155fae-cc0f-4a02-851c-c7afaa90be75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30081
03251 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.3008103251
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2427824894
Short name T466
Test name
Test status
Simulation time 5254250815 ps
CPU time 36.37 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:19:51 PM PDT 24
Peak memory 206928 kb
Host smart-5a5971c8-9f96-4810-bcfa-9a4eb3d611e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
24894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2427824894
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.56225740
Short name T887
Test name
Test status
Simulation time 4238465747 ps
CPU time 34.02 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:19:48 PM PDT 24
Peak memory 206852 kb
Host smart-6e092f01-8df9-48b1-8318-b7cea4b8e1aa
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=56225740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.56225740
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.534110661
Short name T1359
Test name
Test status
Simulation time 158341830 ps
CPU time 0.79 seconds
Started Jul 20 06:19:16 PM PDT 24
Finished Jul 20 06:19:19 PM PDT 24
Peak memory 206656 kb
Host smart-7059a9b6-a55a-47f9-bc41-04160e592adb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=534110661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.534110661
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.813337273
Short name T715
Test name
Test status
Simulation time 143704864 ps
CPU time 0.79 seconds
Started Jul 20 06:19:24 PM PDT 24
Finished Jul 20 06:19:26 PM PDT 24
Peak memory 206628 kb
Host smart-9400b60e-4ca1-4833-938c-a62661dcf057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81333
7273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.813337273
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.524944322
Short name T111
Test name
Test status
Simulation time 208443269 ps
CPU time 0.96 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:28 PM PDT 24
Peak memory 206656 kb
Host smart-0ebff0e9-f088-413c-a241-efb43b7f2acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52494
4322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.524944322
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1303210027
Short name T1756
Test name
Test status
Simulation time 208319818 ps
CPU time 0.86 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:28 PM PDT 24
Peak memory 206652 kb
Host smart-6a87642a-83d8-49a4-a06f-064a2526a917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13032
10027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1303210027
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3395989348
Short name T1818
Test name
Test status
Simulation time 189114547 ps
CPU time 0.81 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:28 PM PDT 24
Peak memory 206660 kb
Host smart-fd02a975-aa2e-47b7-b89d-d815255351d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33959
89348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3395989348
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1385400655
Short name T1309
Test name
Test status
Simulation time 159664757 ps
CPU time 0.78 seconds
Started Jul 20 06:19:26 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 206640 kb
Host smart-c5e3efbc-b9bb-450c-85ff-7bc7b5aeaefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13854
00655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1385400655
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.4209382544
Short name T1033
Test name
Test status
Simulation time 190881121 ps
CPU time 0.81 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:27 PM PDT 24
Peak memory 206648 kb
Host smart-6c716967-8112-4c80-bdae-317318dc9d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42093
82544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.4209382544
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.473093195
Short name T327
Test name
Test status
Simulation time 236326501 ps
CPU time 0.95 seconds
Started Jul 20 06:19:22 PM PDT 24
Finished Jul 20 06:19:24 PM PDT 24
Peak memory 206660 kb
Host smart-91d47e37-b2c7-45e6-9fc3-6ba0a4b2e32c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=473093195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.473093195
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.3844975032
Short name T192
Test name
Test status
Simulation time 215853279 ps
CPU time 0.97 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 206652 kb
Host smart-0a86b64a-d02f-4965-b96a-2fb3391c8ec2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38449
75032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.3844975032
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.1057822141
Short name T1929
Test name
Test status
Simulation time 163488723 ps
CPU time 0.79 seconds
Started Jul 20 06:19:24 PM PDT 24
Finished Jul 20 06:19:25 PM PDT 24
Peak memory 206632 kb
Host smart-2c7c1b17-17ef-49d6-b420-0f4e0bfb58b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10578
22141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.1057822141
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1639983847
Short name T1246
Test name
Test status
Simulation time 56231324 ps
CPU time 0.66 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:26 PM PDT 24
Peak memory 206628 kb
Host smart-2dfc8bd4-0f76-4397-bc89-a81da1f46f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16399
83847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1639983847
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.3699617900
Short name T2650
Test name
Test status
Simulation time 15208879133 ps
CPU time 34.1 seconds
Started Jul 20 06:19:24 PM PDT 24
Finished Jul 20 06:19:59 PM PDT 24
Peak memory 215084 kb
Host smart-4eda88b0-9ad9-4fc7-a11e-5b6a04a83a55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36996
17900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.3699617900
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3283896254
Short name T1530
Test name
Test status
Simulation time 194532489 ps
CPU time 0.87 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:28 PM PDT 24
Peak memory 206660 kb
Host smart-35874ee1-8924-4734-9171-6630c68c703d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32838
96254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3283896254
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.3736423366
Short name T2505
Test name
Test status
Simulation time 225974569 ps
CPU time 0.94 seconds
Started Jul 20 06:19:24 PM PDT 24
Finished Jul 20 06:19:26 PM PDT 24
Peak memory 206700 kb
Host smart-c8e80089-7ac1-492c-9bf6-308929dc74e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37364
23366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.3736423366
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3097067723
Short name T1969
Test name
Test status
Simulation time 8529950158 ps
CPU time 225.04 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:23:11 PM PDT 24
Peak memory 206956 kb
Host smart-7892f2df-405c-4dcb-879c-e3b4f53a3749
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3097067723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3097067723
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2147728265
Short name T996
Test name
Test status
Simulation time 4366259485 ps
CPU time 109.64 seconds
Started Jul 20 06:19:26 PM PDT 24
Finished Jul 20 06:21:18 PM PDT 24
Peak memory 206944 kb
Host smart-09498a9a-d72b-4d7c-a883-806d75a492b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2147728265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2147728265
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.4092905000
Short name T180
Test name
Test status
Simulation time 14418514939 ps
CPU time 301.87 seconds
Started Jul 20 06:19:22 PM PDT 24
Finished Jul 20 06:24:24 PM PDT 24
Peak memory 207028 kb
Host smart-ac5dbf7f-6232-4b07-8535-87a31ec0fe21
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4092905000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.4092905000
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.484213661
Short name T881
Test name
Test status
Simulation time 228718434 ps
CPU time 0.86 seconds
Started Jul 20 06:19:26 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 206660 kb
Host smart-e2dad5e8-18db-4873-9652-61f291fa2f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48421
3661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.484213661
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.1044718870
Short name T1184
Test name
Test status
Simulation time 194039967 ps
CPU time 0.84 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:27 PM PDT 24
Peak memory 206648 kb
Host smart-c337d116-dae8-4b24-b98e-095f1beb973d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10447
18870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.1044718870
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3662349340
Short name T1303
Test name
Test status
Simulation time 208698609 ps
CPU time 0.81 seconds
Started Jul 20 06:19:24 PM PDT 24
Finished Jul 20 06:19:25 PM PDT 24
Peak memory 206648 kb
Host smart-bb2f43bb-0d4a-49c8-969d-997730861fab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36623
49340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3662349340
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.4129259765
Short name T2106
Test name
Test status
Simulation time 167485524 ps
CPU time 0.84 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:27 PM PDT 24
Peak memory 206656 kb
Host smart-0a2676aa-ffee-4e34-99c2-7b18be990102
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41292
59765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.4129259765
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3532917943
Short name T184
Test name
Test status
Simulation time 637665478 ps
CPU time 1.41 seconds
Started Jul 20 06:19:36 PM PDT 24
Finished Jul 20 06:19:38 PM PDT 24
Peak memory 225560 kb
Host smart-98de2059-b4b1-4d3c-afd8-61f91d9dfda6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3532917943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3532917943
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.1046081256
Short name T63
Test name
Test status
Simulation time 421152604 ps
CPU time 1.25 seconds
Started Jul 20 06:19:26 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 206608 kb
Host smart-f87138ce-5743-4d14-9f6f-0ebd3c1c1230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10460
81256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.1046081256
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.967289705
Short name T1074
Test name
Test status
Simulation time 213943653 ps
CPU time 0.9 seconds
Started Jul 20 06:19:25 PM PDT 24
Finished Jul 20 06:19:28 PM PDT 24
Peak memory 206656 kb
Host smart-85519eab-e6b9-4037-8055-a39f62e30072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96728
9705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.967289705
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.51785142
Short name T1371
Test name
Test status
Simulation time 164417752 ps
CPU time 0.78 seconds
Started Jul 20 06:19:24 PM PDT 24
Finished Jul 20 06:19:26 PM PDT 24
Peak memory 206656 kb
Host smart-52e4f0be-f51c-4f89-93be-c1b89d6b1578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51785
142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.51785142
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.3984337703
Short name T2602
Test name
Test status
Simulation time 172880001 ps
CPU time 0.83 seconds
Started Jul 20 06:19:26 PM PDT 24
Finished Jul 20 06:19:29 PM PDT 24
Peak memory 206652 kb
Host smart-f3bc5bc1-41b6-4f8d-86a1-cc955bd5a3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39843
37703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.3984337703
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1223686773
Short name T2732
Test name
Test status
Simulation time 207490668 ps
CPU time 0.87 seconds
Started Jul 20 06:19:23 PM PDT 24
Finished Jul 20 06:19:24 PM PDT 24
Peak memory 206652 kb
Host smart-ec742414-facd-4265-9706-bd2edcc47ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12236
86773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1223686773
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3320673491
Short name T832
Test name
Test status
Simulation time 4100305349 ps
CPU time 37.86 seconds
Started Jul 20 06:19:28 PM PDT 24
Finished Jul 20 06:20:07 PM PDT 24
Peak memory 206868 kb
Host smart-fc245eb4-25ce-4787-a19f-4a1e439b139c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3320673491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3320673491
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.223664294
Short name T326
Test name
Test status
Simulation time 222115203 ps
CPU time 0.92 seconds
Started Jul 20 06:19:29 PM PDT 24
Finished Jul 20 06:19:31 PM PDT 24
Peak memory 206660 kb
Host smart-c983a6a3-f0b9-48e1-8a9d-d51321ef446f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366
4294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.223664294
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.237812646
Short name T1815
Test name
Test status
Simulation time 146970787 ps
CPU time 0.8 seconds
Started Jul 20 06:19:24 PM PDT 24
Finished Jul 20 06:19:26 PM PDT 24
Peak memory 206656 kb
Host smart-3ce83116-5a04-4641-a5c0-5809b0a12f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23781
2646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.237812646
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3137104309
Short name T1354
Test name
Test status
Simulation time 387875450 ps
CPU time 1.15 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:35 PM PDT 24
Peak memory 206648 kb
Host smart-6f72f008-cfea-4eb7-a3bd-d855c58b9ce5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31371
04309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3137104309
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.4221002509
Short name T1279
Test name
Test status
Simulation time 7316258767 ps
CPU time 208.14 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206836 kb
Host smart-1a3a89b4-af50-4f5e-9fac-3253fafb2339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42210
02509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.4221002509
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_timeout_missing_host_handshake.2431532707
Short name T1403
Test name
Test status
Simulation time 159906803 ps
CPU time 0.79 seconds
Started Jul 20 06:19:13 PM PDT 24
Finished Jul 20 06:19:15 PM PDT 24
Peak memory 206740 kb
Host smart-6dadb112-fddc-4fbf-bffa-1c779215eb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24315
32707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_timeout_missing_host_handshake.2431532707
Directory /workspace/3.usbdev_timeout_missing_host_handshake/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.2290895726
Short name T2582
Test name
Test status
Simulation time 44704090 ps
CPU time 0.67 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:40 PM PDT 24
Peak memory 206704 kb
Host smart-676bace0-7d3c-43f3-8270-edabb62f5926
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2290895726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.2290895726
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.2425245207
Short name T2662
Test name
Test status
Simulation time 3471917604 ps
CPU time 4.1 seconds
Started Jul 20 06:24:26 PM PDT 24
Finished Jul 20 06:24:32 PM PDT 24
Peak memory 206716 kb
Host smart-df8c2a7e-3e88-43b6-828e-89fd08f6572e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2425245207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.2425245207
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.730070984
Short name T2452
Test name
Test status
Simulation time 13419179568 ps
CPU time 15.57 seconds
Started Jul 20 06:24:27 PM PDT 24
Finished Jul 20 06:24:45 PM PDT 24
Peak memory 206756 kb
Host smart-5d6be86f-a1ed-47fc-bae3-0e6958d1e9b1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=730070984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.730070984
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.4104629246
Short name T997
Test name
Test status
Simulation time 23347764961 ps
CPU time 23.81 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:51 PM PDT 24
Peak memory 206780 kb
Host smart-97fa47f3-7325-4f18-a3fa-c4c63eec4467
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4104629246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.4104629246
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.546125094
Short name T1948
Test name
Test status
Simulation time 160410706 ps
CPU time 0.86 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:28 PM PDT 24
Peak memory 206656 kb
Host smart-be18be95-3705-4d6d-8a9d-cdb2eff63553
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54612
5094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.546125094
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2430363110
Short name T2349
Test name
Test status
Simulation time 142309925 ps
CPU time 0.76 seconds
Started Jul 20 06:24:28 PM PDT 24
Finished Jul 20 06:24:31 PM PDT 24
Peak memory 206656 kb
Host smart-6703b576-bd9c-46b4-98bd-b40257a34420
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24303
63110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2430363110
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.1156017627
Short name T1912
Test name
Test status
Simulation time 217449955 ps
CPU time 0.89 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206640 kb
Host smart-d2b809f7-ec26-4782-bf45-e89e593600f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11560
17627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.1156017627
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2353208585
Short name T2570
Test name
Test status
Simulation time 814000740 ps
CPU time 1.95 seconds
Started Jul 20 06:24:25 PM PDT 24
Finished Jul 20 06:24:30 PM PDT 24
Peak memory 206800 kb
Host smart-50fc532f-6ff7-47b3-a27f-382e79dca4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23532
08585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2353208585
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.521808138
Short name T2154
Test name
Test status
Simulation time 21504703982 ps
CPU time 40.33 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206900 kb
Host smart-1829ab29-c874-4dbb-9aef-946b339c7edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52180
8138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.521808138
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3649932541
Short name T2624
Test name
Test status
Simulation time 489903719 ps
CPU time 1.4 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206652 kb
Host smart-17997861-1b3c-43f2-8b05-9b57a25a864d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36499
32541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3649932541
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.393511820
Short name T2326
Test name
Test status
Simulation time 155751732 ps
CPU time 0.84 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206648 kb
Host smart-cda7ce60-a270-4b38-9a1c-7e7a61d23daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39351
1820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.393511820
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.4051694302
Short name T396
Test name
Test status
Simulation time 41621538 ps
CPU time 0.67 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:41 PM PDT 24
Peak memory 206644 kb
Host smart-05d0a7d8-97ee-47a7-8377-0991dd056c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40516
94302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.4051694302
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.2638604358
Short name T317
Test name
Test status
Simulation time 750166318 ps
CPU time 1.93 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206724 kb
Host smart-f266430d-8d98-4c0a-b51a-5a4e97021f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26386
04358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.2638604358
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.2450229358
Short name T2637
Test name
Test status
Simulation time 217908047 ps
CPU time 1.44 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:37 PM PDT 24
Peak memory 206804 kb
Host smart-543c9a86-415e-4d83-8cba-ea5e62de8a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24502
29358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.2450229358
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.3510594842
Short name T1152
Test name
Test status
Simulation time 228352666 ps
CPU time 0.9 seconds
Started Jul 20 06:24:33 PM PDT 24
Finished Jul 20 06:24:34 PM PDT 24
Peak memory 206648 kb
Host smart-dded2149-a4d7-4d68-a0f9-0901e3b7ecd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35105
94842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.3510594842
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.631511035
Short name T1153
Test name
Test status
Simulation time 161908941 ps
CPU time 0.79 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:41 PM PDT 24
Peak memory 206624 kb
Host smart-a08d4f34-92e9-43e3-9e97-e693ecf00382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63151
1035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.631511035
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.2442684564
Short name T2692
Test name
Test status
Simulation time 202780990 ps
CPU time 0.86 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206676 kb
Host smart-0ae54acc-2963-4875-a3e5-46a38fea6280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24426
84564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.2442684564
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.531027503
Short name T2473
Test name
Test status
Simulation time 7038966316 ps
CPU time 50.41 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206928 kb
Host smart-048c3e47-6d06-40bd-b2ef-c1fbe558fd23
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=531027503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.531027503
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_iso_retraction.1280148174
Short name T1172
Test name
Test status
Simulation time 4652133364 ps
CPU time 14.57 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:51 PM PDT 24
Peak memory 206868 kb
Host smart-c23c1575-5517-4d9a-b486-67d54353843a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12801
48174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_iso_retraction.1280148174
Directory /workspace/30.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1882494167
Short name T1612
Test name
Test status
Simulation time 158490924 ps
CPU time 0.78 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:40 PM PDT 24
Peak memory 206644 kb
Host smart-0051d878-bb0e-4dda-90b9-5cae415442b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18824
94167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1882494167
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3746282884
Short name T1645
Test name
Test status
Simulation time 23277252795 ps
CPU time 21.68 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206776 kb
Host smart-c7b98159-0e3c-480b-9071-080958f13ef8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37462
82884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3746282884
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.727243987
Short name T1229
Test name
Test status
Simulation time 3346686349 ps
CPU time 4.51 seconds
Started Jul 20 06:24:40 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206712 kb
Host smart-4446a639-cae6-4f03-b8f6-058b4896a418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72724
3987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.727243987
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.4162394323
Short name T2381
Test name
Test status
Simulation time 12469275309 ps
CPU time 86.78 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:26:09 PM PDT 24
Peak memory 206920 kb
Host smart-e782d951-6360-408f-92bb-8bf69404ef76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41623
94323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.4162394323
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.357026391
Short name T1445
Test name
Test status
Simulation time 3052083745 ps
CPU time 29.09 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:25:07 PM PDT 24
Peak memory 206904 kb
Host smart-0efc3d06-9a7d-49ec-b24c-ebed436ae630
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=357026391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.357026391
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.3469594003
Short name T2451
Test name
Test status
Simulation time 236016808 ps
CPU time 0.88 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:37 PM PDT 24
Peak memory 206652 kb
Host smart-9b7e41ce-28ef-49a0-8a18-0c98466ed445
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3469594003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.3469594003
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.2196456425
Short name T2186
Test name
Test status
Simulation time 186550665 ps
CPU time 0.88 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:36 PM PDT 24
Peak memory 206648 kb
Host smart-12164df3-ca72-491b-8f52-8477d08bd829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21964
56425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.2196456425
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.888010658
Short name T151
Test name
Test status
Simulation time 6277904180 ps
CPU time 170.14 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:27:33 PM PDT 24
Peak memory 206864 kb
Host smart-9584d872-0b95-48e2-b6e0-80146b894b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88801
0658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.888010658
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.2668374877
Short name T978
Test name
Test status
Simulation time 6385735756 ps
CPU time 60.56 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:25:39 PM PDT 24
Peak memory 206896 kb
Host smart-0638c66e-089e-49b4-a6a5-48d801010c34
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2668374877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.2668374877
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1009448731
Short name T2701
Test name
Test status
Simulation time 153262078 ps
CPU time 0.79 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:36 PM PDT 24
Peak memory 206664 kb
Host smart-ed01fee4-8083-46c9-8ab5-e8a6bfa84f9f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1009448731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1009448731
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.2309907656
Short name T2078
Test name
Test status
Simulation time 150668683 ps
CPU time 0.76 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206652 kb
Host smart-9c7d6f0e-8717-4335-9f50-8a44ff290592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23099
07656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.2309907656
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3760675490
Short name T113
Test name
Test status
Simulation time 192586849 ps
CPU time 0.89 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206644 kb
Host smart-c4071f1d-a94a-4bd3-8237-d678afb6f8fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37606
75490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3760675490
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.1318825294
Short name T840
Test name
Test status
Simulation time 238297447 ps
CPU time 0.87 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206656 kb
Host smart-8601d53a-f944-4ed8-b683-3087e6f35ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13188
25294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.1318825294
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3138454207
Short name T1013
Test name
Test status
Simulation time 149275416 ps
CPU time 0.82 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:42 PM PDT 24
Peak memory 206652 kb
Host smart-7433d530-104e-4718-9875-d89e65fb0fad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31384
54207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3138454207
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2881989812
Short name T1230
Test name
Test status
Simulation time 155252528 ps
CPU time 0.74 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206656 kb
Host smart-678d3675-a39d-485e-94ec-a8c8e63f4dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28819
89812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2881989812
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.2374773746
Short name T2562
Test name
Test status
Simulation time 151499206 ps
CPU time 0.81 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206624 kb
Host smart-2a07b096-5b25-4a39-a7c9-a0e002d3c9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23747
73746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.2374773746
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1993450507
Short name T1834
Test name
Test status
Simulation time 212128205 ps
CPU time 0.86 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:38 PM PDT 24
Peak memory 206660 kb
Host smart-3df983e1-9fc6-47d8-914e-99009cc8259c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1993450507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1993450507
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.161534613
Short name T44
Test name
Test status
Simulation time 142739940 ps
CPU time 0.73 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206624 kb
Host smart-da170d9f-5f8b-4dab-8f63-6069aca9f74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16153
4613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.161534613
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1478806670
Short name T973
Test name
Test status
Simulation time 37375825 ps
CPU time 0.69 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206640 kb
Host smart-428a53a3-b0f8-4b4b-bc9e-41af25034ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14788
06670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1478806670
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1580527772
Short name T1618
Test name
Test status
Simulation time 6611438462 ps
CPU time 14.67 seconds
Started Jul 20 06:24:34 PM PDT 24
Finished Jul 20 06:24:49 PM PDT 24
Peak memory 206880 kb
Host smart-20fc9096-f297-4bed-868e-ec3be9b1ab70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15805
27772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1580527772
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.2605155742
Short name T1745
Test name
Test status
Simulation time 158974242 ps
CPU time 0.79 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:38 PM PDT 24
Peak memory 206696 kb
Host smart-c3c4fbf4-a4f2-4390-92a8-fdbb4d37cf70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26051
55742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.2605155742
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1935023181
Short name T754
Test name
Test status
Simulation time 239795423 ps
CPU time 0.94 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:42 PM PDT 24
Peak memory 206660 kb
Host smart-d184412e-12a2-4395-b802-ec0ee16269f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19350
23181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1935023181
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.3323379858
Short name T974
Test name
Test status
Simulation time 174859755 ps
CPU time 0.79 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206648 kb
Host smart-021de48d-bee0-4429-add8-a73f65afdf44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33233
79858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.3323379858
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1659073235
Short name T430
Test name
Test status
Simulation time 198440957 ps
CPU time 0.88 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:41 PM PDT 24
Peak memory 206628 kb
Host smart-1f806465-dc24-4d95-8ff5-2c4c53a9a90b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
73235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1659073235
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2282227604
Short name T825
Test name
Test status
Simulation time 132242354 ps
CPU time 0.77 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206652 kb
Host smart-4874a8af-0653-496b-85c4-4a40ca07321a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22822
27604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2282227604
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.1865289778
Short name T1409
Test name
Test status
Simulation time 149719554 ps
CPU time 0.75 seconds
Started Jul 20 06:24:40 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206628 kb
Host smart-a66965d5-3a47-4836-b8b6-0cf81c099233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18652
89778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.1865289778
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.3121090972
Short name T1021
Test name
Test status
Simulation time 145654691 ps
CPU time 0.75 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:40 PM PDT 24
Peak memory 206656 kb
Host smart-2023b5d6-bbca-4815-9cac-d2eb0742cd93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31210
90972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.3121090972
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.512037229
Short name T1544
Test name
Test status
Simulation time 239439112 ps
CPU time 0.96 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:36 PM PDT 24
Peak memory 206644 kb
Host smart-be050eee-6edb-443a-88b1-6449be87b070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51203
7229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.512037229
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2291646994
Short name T370
Test name
Test status
Simulation time 4302287928 ps
CPU time 42.99 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:25:24 PM PDT 24
Peak memory 206912 kb
Host smart-a5c4ffc6-0fbb-45d4-b643-8511d58a660f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2291646994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2291646994
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3662496979
Short name T147
Test name
Test status
Simulation time 181764533 ps
CPU time 0.81 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206600 kb
Host smart-701df763-3ba5-4e01-9045-f4f22399ea01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36624
96979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3662496979
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.511795189
Short name T1980
Test name
Test status
Simulation time 168630423 ps
CPU time 0.83 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:24:39 PM PDT 24
Peak memory 206656 kb
Host smart-d98a4fbc-7f5f-4545-a3f8-049242c40335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51179
5189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.511795189
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.2182296696
Short name T2573
Test name
Test status
Simulation time 464065771 ps
CPU time 1.37 seconds
Started Jul 20 06:24:40 PM PDT 24
Finished Jul 20 06:24:45 PM PDT 24
Peak memory 206628 kb
Host smart-1078871a-5108-48f8-8100-05663d522c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21822
96696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.2182296696
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.3800810948
Short name T2464
Test name
Test status
Simulation time 5337257782 ps
CPU time 50.55 seconds
Started Jul 20 06:24:36 PM PDT 24
Finished Jul 20 06:25:28 PM PDT 24
Peak memory 206868 kb
Host smart-8dbee7f7-c048-486c-88c4-664161784eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38008
10948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.3800810948
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.2339547980
Short name T1421
Test name
Test status
Simulation time 66475770 ps
CPU time 0.67 seconds
Started Jul 20 06:24:47 PM PDT 24
Finished Jul 20 06:24:49 PM PDT 24
Peak memory 206652 kb
Host smart-6956362a-2b2e-46ae-879d-8489c91c6feb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2339547980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.2339547980
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3773884004
Short name T1542
Test name
Test status
Simulation time 3735504581 ps
CPU time 4.35 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:45 PM PDT 24
Peak memory 206808 kb
Host smart-26f948c4-79b9-4310-ba4d-cad8f93869de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3773884004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3773884004
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.1941166462
Short name T2338
Test name
Test status
Simulation time 13377085834 ps
CPU time 14.39 seconds
Started Jul 20 06:24:33 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206776 kb
Host smart-cce0da0b-1bc5-436c-83d4-028f2bb237d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1941166462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.1941166462
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.4149008424
Short name T1631
Test name
Test status
Simulation time 23472354475 ps
CPU time 27.1 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:25:08 PM PDT 24
Peak memory 206784 kb
Host smart-a5ec5f89-9777-43a5-9e76-ce0e29214a96
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4149008424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.4149008424
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.3561033852
Short name T2101
Test name
Test status
Simulation time 154068442 ps
CPU time 0.82 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:41 PM PDT 24
Peak memory 206628 kb
Host smart-c3ba1168-9306-4a2b-aed5-7ac5052e0e48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35610
33852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.3561033852
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.639136361
Short name T1873
Test name
Test status
Simulation time 163137773 ps
CPU time 0.79 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206656 kb
Host smart-55032c10-3de9-43fe-93d5-93b4eb0254aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63913
6361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.639136361
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.4238076890
Short name T2235
Test name
Test status
Simulation time 353864369 ps
CPU time 1.28 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:24:41 PM PDT 24
Peak memory 206568 kb
Host smart-60192e92-c9f0-4eb0-a276-9546a0029181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
76890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.4238076890
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.1901584564
Short name T1999
Test name
Test status
Simulation time 586474487 ps
CPU time 1.45 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206652 kb
Host smart-5f259e14-9e89-4a3c-9ed7-09242241bbd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19015
84564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.1901584564
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.313978641
Short name T28
Test name
Test status
Simulation time 21955729008 ps
CPU time 41.12 seconds
Started Jul 20 06:24:37 PM PDT 24
Finished Jul 20 06:25:21 PM PDT 24
Peak memory 206844 kb
Host smart-e570205f-5ce8-4953-9469-1bd8866527c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31397
8641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.313978641
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.267478341
Short name T1136
Test name
Test status
Simulation time 374879031 ps
CPU time 1.28 seconds
Started Jul 20 06:24:41 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206644 kb
Host smart-b221af92-72e3-4632-bf7a-fa361f182210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26747
8341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.267478341
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.3010680091
Short name T1984
Test name
Test status
Simulation time 178266477 ps
CPU time 0.84 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:24:44 PM PDT 24
Peak memory 206644 kb
Host smart-c0ee486e-10ff-43fa-9276-031225467ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30106
80091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.3010680091
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2222079176
Short name T2579
Test name
Test status
Simulation time 45372506 ps
CPU time 0.64 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:42 PM PDT 24
Peak memory 206608 kb
Host smart-e1cece98-9516-44a9-a499-f70ab1748528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22220
79176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2222079176
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2698891935
Short name T2595
Test name
Test status
Simulation time 905365355 ps
CPU time 2.3 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:24:45 PM PDT 24
Peak memory 206788 kb
Host smart-e3d43d3b-7006-4dc0-a4f7-067bd4c2bc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26988
91935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2698891935
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.691285321
Short name T1219
Test name
Test status
Simulation time 241922892 ps
CPU time 1.69 seconds
Started Jul 20 06:24:35 PM PDT 24
Finished Jul 20 06:24:38 PM PDT 24
Peak memory 206744 kb
Host smart-577c14f5-75a7-4386-b97c-94fff63680c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69128
5321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.691285321
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.82273395
Short name T877
Test name
Test status
Simulation time 193920475 ps
CPU time 0.82 seconds
Started Jul 20 06:24:41 PM PDT 24
Finished Jul 20 06:24:45 PM PDT 24
Peak memory 206636 kb
Host smart-a2f49c60-44d5-4e87-9172-cf4cb525b5e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82273
395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.82273395
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.1505102814
Short name T626
Test name
Test status
Simulation time 196129813 ps
CPU time 0.82 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:43 PM PDT 24
Peak memory 206648 kb
Host smart-52a37b2f-81ba-4786-8cab-cea814ff3ca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15051
02814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.1505102814
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3747439432
Short name T1938
Test name
Test status
Simulation time 185483763 ps
CPU time 0.86 seconds
Started Jul 20 06:24:38 PM PDT 24
Finished Jul 20 06:24:42 PM PDT 24
Peak memory 206660 kb
Host smart-9e83e0c2-5d5f-4791-ad7c-a76eabd11575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37474
39432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3747439432
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.343244179
Short name T1312
Test name
Test status
Simulation time 6404730104 ps
CPU time 53.18 seconds
Started Jul 20 06:24:41 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206896 kb
Host smart-fd2f71a0-4086-4e4f-ba89-014c81cc4a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34324
4179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.343244179
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.4086588550
Short name T2673
Test name
Test status
Simulation time 240391048 ps
CPU time 0.99 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206580 kb
Host smart-f414137a-12f9-4a11-8c95-188b23086381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40865
88550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.4086588550
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.909957065
Short name T592
Test name
Test status
Simulation time 23304468085 ps
CPU time 22.92 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206784 kb
Host smart-186a34ab-912b-46c2-a1b4-dabdd6062391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90995
7065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.909957065
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.2677536764
Short name T1543
Test name
Test status
Simulation time 3371480108 ps
CPU time 4.45 seconds
Started Jul 20 06:24:41 PM PDT 24
Finished Jul 20 06:24:50 PM PDT 24
Peak memory 206724 kb
Host smart-aa22b3e7-56f8-4f9e-9122-27bdad2d70d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26775
36764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.2677536764
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2793759678
Short name T1531
Test name
Test status
Simulation time 8139528805 ps
CPU time 72.22 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:25:58 PM PDT 24
Peak memory 206932 kb
Host smart-630aab4d-2ff7-448e-afa7-f105303312c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27937
59678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2793759678
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.1541811696
Short name T2657
Test name
Test status
Simulation time 6678227708 ps
CPU time 63.79 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:25:50 PM PDT 24
Peak memory 206848 kb
Host smart-3628156b-87b0-4369-8c53-ff3b7fea2f0a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1541811696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.1541811696
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.3971922170
Short name T1356
Test name
Test status
Simulation time 290276944 ps
CPU time 0.93 seconds
Started Jul 20 06:24:41 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206640 kb
Host smart-de1d9f7b-a356-4af2-bfcc-56f1a61c7ae4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3971922170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.3971922170
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.1249342374
Short name T1081
Test name
Test status
Simulation time 209858776 ps
CPU time 0.89 seconds
Started Jul 20 06:24:41 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206656 kb
Host smart-5c7154ab-f2d6-4f2a-99eb-5a202f1d4fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12493
42374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.1249342374
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3700329344
Short name T238
Test name
Test status
Simulation time 5085779894 ps
CPU time 37.25 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:25:23 PM PDT 24
Peak memory 206928 kb
Host smart-7b2ddcc3-f69d-4718-bc0f-3bc2f177a41e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37003
29344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3700329344
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.237488477
Short name T1972
Test name
Test status
Simulation time 5494872115 ps
CPU time 145.68 seconds
Started Jul 20 06:24:39 PM PDT 24
Finished Jul 20 06:27:08 PM PDT 24
Peak memory 206864 kb
Host smart-06910711-0c5a-4a9f-ab53-fc14ef61bfae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=237488477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.237488477
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.178732977
Short name T2242
Test name
Test status
Simulation time 174458294 ps
CPU time 0.78 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206656 kb
Host smart-643cbfa6-908c-480d-89da-25dc17a8f59d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=178732977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.178732977
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.282121018
Short name T2265
Test name
Test status
Simulation time 155966816 ps
CPU time 0.77 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206656 kb
Host smart-431b16b8-47c9-4002-8d15-1dbf1dbf9050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28212
1018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.282121018
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.3777398189
Short name T96
Test name
Test status
Simulation time 162990661 ps
CPU time 0.81 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206652 kb
Host smart-0c8047d6-7b3f-4e09-9173-95f73b50367b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37773
98189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.3777398189
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1711990840
Short name T1173
Test name
Test status
Simulation time 151120187 ps
CPU time 0.81 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206648 kb
Host smart-b60eab2e-436a-4680-808d-1e77d1067d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17119
90840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1711990840
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.498745306
Short name T2098
Test name
Test status
Simulation time 191874384 ps
CPU time 0.83 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206636 kb
Host smart-29ad728f-b85a-4aab-b7d0-1ce7a03c11c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49874
5306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.498745306
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.3290340129
Short name T166
Test name
Test status
Simulation time 178486615 ps
CPU time 0.79 seconds
Started Jul 20 06:24:46 PM PDT 24
Finished Jul 20 06:24:49 PM PDT 24
Peak memory 206664 kb
Host smart-42016a8f-ed8d-4f6f-a4ba-3d1e832e5e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32903
40129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.3290340129
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2311890628
Short name T2003
Test name
Test status
Simulation time 210964772 ps
CPU time 0.92 seconds
Started Jul 20 06:24:44 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206616 kb
Host smart-7df15bf8-2f4b-43cd-8954-4eef61874de3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2311890628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2311890628
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.1492359643
Short name T2201
Test name
Test status
Simulation time 147804613 ps
CPU time 0.84 seconds
Started Jul 20 06:24:52 PM PDT 24
Finished Jul 20 06:24:55 PM PDT 24
Peak memory 206644 kb
Host smart-2dced68d-3b8b-4175-99a8-98bab2fc5423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14923
59643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.1492359643
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3941143580
Short name T1453
Test name
Test status
Simulation time 65149212 ps
CPU time 0.7 seconds
Started Jul 20 06:24:47 PM PDT 24
Finished Jul 20 06:24:49 PM PDT 24
Peak memory 206644 kb
Host smart-0fac8d76-04c5-4759-9452-dc991e31ef82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39411
43580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3941143580
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.2068338554
Short name T1377
Test name
Test status
Simulation time 14977712517 ps
CPU time 31.17 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 207000 kb
Host smart-59e8e9c8-261d-4039-a4d4-d0b682b558f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20683
38554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.2068338554
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.492287597
Short name T892
Test name
Test status
Simulation time 156028419 ps
CPU time 0.76 seconds
Started Jul 20 06:24:46 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206660 kb
Host smart-c95750ab-465d-45f9-85c6-9cfde9295f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49228
7597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.492287597
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3145172773
Short name T1091
Test name
Test status
Simulation time 204675169 ps
CPU time 0.86 seconds
Started Jul 20 06:24:44 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206488 kb
Host smart-3ae145e0-d887-49bb-ae18-3a4fa9d391f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31451
72773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3145172773
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.3236985204
Short name T1732
Test name
Test status
Simulation time 234730693 ps
CPU time 0.89 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206652 kb
Host smart-23b9cbbd-7d1e-487e-9a98-98ebf33d3535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32369
85204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.3236985204
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.4075658501
Short name T312
Test name
Test status
Simulation time 215879125 ps
CPU time 0.86 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:55 PM PDT 24
Peak memory 206652 kb
Host smart-3f629552-6205-4568-9cb6-5ace8fbe95a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40756
58501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.4075658501
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.482765640
Short name T408
Test name
Test status
Simulation time 149474106 ps
CPU time 0.74 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206632 kb
Host smart-b0eab635-498b-4b9a-86ee-eaf225fbd389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48276
5640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.482765640
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.125774567
Short name T2066
Test name
Test status
Simulation time 149212375 ps
CPU time 0.76 seconds
Started Jul 20 06:24:45 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206648 kb
Host smart-e0b8a411-8afb-4143-9321-0795060bff89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
4567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.125774567
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4133178055
Short name T1007
Test name
Test status
Simulation time 143598511 ps
CPU time 0.81 seconds
Started Jul 20 06:24:44 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206416 kb
Host smart-9a66b7e6-64ae-4b3f-af54-7b0a8ee78e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41331
78055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4133178055
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3101936380
Short name T690
Test name
Test status
Simulation time 185976063 ps
CPU time 0.84 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206616 kb
Host smart-69f08430-2f11-4ee6-b703-2e27271b8132
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31019
36380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3101936380
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.3354705381
Short name T2010
Test name
Test status
Simulation time 4263451472 ps
CPU time 40.32 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:25:26 PM PDT 24
Peak memory 206836 kb
Host smart-4f048aed-e331-4e04-ada8-534183a6d56b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3354705381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.3354705381
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.4058273934
Short name T2105
Test name
Test status
Simulation time 196549618 ps
CPU time 0.9 seconds
Started Jul 20 06:24:41 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206632 kb
Host smart-47d73cb5-d8a7-4f25-a343-c3d3b2e24d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40582
73934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.4058273934
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3375957882
Short name T2096
Test name
Test status
Simulation time 171504470 ps
CPU time 0.79 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206624 kb
Host smart-88bb84f2-14c7-4590-8900-e436bd4fbdfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33759
57882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3375957882
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.402736274
Short name T1624
Test name
Test status
Simulation time 326877971 ps
CPU time 1.13 seconds
Started Jul 20 06:24:44 PM PDT 24
Finished Jul 20 06:24:48 PM PDT 24
Peak memory 206632 kb
Host smart-49ade530-92d1-4cdc-9566-5ef1070d34df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40273
6274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.402736274
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1815371506
Short name T1555
Test name
Test status
Simulation time 3241659185 ps
CPU time 92.63 seconds
Started Jul 20 06:24:40 PM PDT 24
Finished Jul 20 06:26:17 PM PDT 24
Peak memory 206884 kb
Host smart-0c3af13a-045a-4fe3-b2c3-88e58b2261df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18153
71506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1815371506
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.330709310
Short name T1012
Test name
Test status
Simulation time 67685520 ps
CPU time 0.71 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206696 kb
Host smart-24fcfae2-185d-4428-a426-72b0e038de74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=330709310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.330709310
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.141598278
Short name T542
Test name
Test status
Simulation time 3708231058 ps
CPU time 4.49 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:24:50 PM PDT 24
Peak memory 206692 kb
Host smart-0f79e5b5-67a1-49f2-b4b4-798e67ecceff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=141598278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.141598278
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.1625514923
Short name T833
Test name
Test status
Simulation time 13430572763 ps
CPU time 13.47 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206936 kb
Host smart-06d5f50f-f7f5-44b8-aa15-8df1f4039531
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1625514923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.1625514923
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3737865261
Short name T2745
Test name
Test status
Simulation time 23405152594 ps
CPU time 27.67 seconds
Started Jul 20 06:24:43 PM PDT 24
Finished Jul 20 06:25:14 PM PDT 24
Peak memory 206748 kb
Host smart-37902769-5fa7-4259-aec8-aac53da59813
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3737865261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3737865261
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2389995310
Short name T1872
Test name
Test status
Simulation time 206312414 ps
CPU time 0.82 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:24:46 PM PDT 24
Peak memory 206652 kb
Host smart-84fcb174-4e7d-43e2-8e22-567d0a9640df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23899
95310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2389995310
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.951663490
Short name T1085
Test name
Test status
Simulation time 152676746 ps
CPU time 0.78 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:52 PM PDT 24
Peak memory 206656 kb
Host smart-8b86ae22-59f2-4b71-8f8c-33c1e9ee2324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95166
3490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.951663490
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1271750492
Short name T1668
Test name
Test status
Simulation time 369513894 ps
CPU time 1.29 seconds
Started Jul 20 06:24:42 PM PDT 24
Finished Jul 20 06:24:47 PM PDT 24
Peak memory 206644 kb
Host smart-39b5c887-6a9b-4ee1-9d4e-9839ee12a232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12717
50492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1271750492
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1537116940
Short name T596
Test name
Test status
Simulation time 596567329 ps
CPU time 1.53 seconds
Started Jul 20 06:24:59 PM PDT 24
Finished Jul 20 06:25:02 PM PDT 24
Peak memory 206556 kb
Host smart-8eb8c511-321f-4442-8d5c-6ef6572767a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15371
16940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1537116940
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.605981378
Short name T731
Test name
Test status
Simulation time 6738378221 ps
CPU time 14.61 seconds
Started Jul 20 06:24:52 PM PDT 24
Finished Jul 20 06:25:07 PM PDT 24
Peak memory 206880 kb
Host smart-46598b7c-8b40-4d82-bbb8-71438329961e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60598
1378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.605981378
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.3894033500
Short name T353
Test name
Test status
Simulation time 503903560 ps
CPU time 1.5 seconds
Started Jul 20 06:24:59 PM PDT 24
Finished Jul 20 06:25:02 PM PDT 24
Peak memory 206652 kb
Host smart-168f056a-3f3b-48b8-8589-3267d3d2b7d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38940
33500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.3894033500
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.1472759726
Short name T1726
Test name
Test status
Simulation time 148789867 ps
CPU time 0.79 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:25:00 PM PDT 24
Peak memory 206644 kb
Host smart-a5fb4e20-3f2e-499f-be52-74af65c67f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14727
59726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.1472759726
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.2109524445
Short name T2643
Test name
Test status
Simulation time 35991759 ps
CPU time 0.65 seconds
Started Jul 20 06:24:52 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206640 kb
Host smart-6355bba6-28ad-434b-980a-a6d95e450678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21095
24445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.2109524445
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.3648052369
Short name T423
Test name
Test status
Simulation time 946676318 ps
CPU time 2.26 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206772 kb
Host smart-b608f5e5-f077-4bc2-ae5c-826b52199111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36480
52369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.3648052369
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3099415074
Short name T1941
Test name
Test status
Simulation time 230076382 ps
CPU time 1.42 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206792 kb
Host smart-f376bbdf-4f15-4429-9d14-a8dd4bcea503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30994
15074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3099415074
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.4276668341
Short name T1044
Test name
Test status
Simulation time 170388587 ps
CPU time 0.85 seconds
Started Jul 20 06:24:57 PM PDT 24
Finished Jul 20 06:25:01 PM PDT 24
Peak memory 206648 kb
Host smart-0cddc93c-a96c-420f-8baf-4554dc120828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42766
68341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.4276668341
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.2092076454
Short name T883
Test name
Test status
Simulation time 143084678 ps
CPU time 0.78 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206652 kb
Host smart-d36f69de-ed54-4c12-a1fb-ed46c069e557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20920
76454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.2092076454
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2060198549
Short name T2727
Test name
Test status
Simulation time 217347778 ps
CPU time 0.87 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206700 kb
Host smart-50be09f8-f2f5-429e-bd54-73b5fbb85fec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20601
98549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2060198549
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.3682003317
Short name T1835
Test name
Test status
Simulation time 5753797991 ps
CPU time 168.96 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:27:48 PM PDT 24
Peak memory 206904 kb
Host smart-b3cd8f2b-9942-48c9-9930-476ee8b3af41
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3682003317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.3682003317
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.2205288367
Short name T2538
Test name
Test status
Simulation time 161264292 ps
CPU time 0.82 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206648 kb
Host smart-e74275d9-65b5-42ef-b739-d215a8fd9b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22052
88367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.2205288367
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.2874408723
Short name T1240
Test name
Test status
Simulation time 23341295803 ps
CPU time 22.53 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:25:22 PM PDT 24
Peak memory 206772 kb
Host smart-1eb8e5cc-f0d2-4ca6-9b98-9a18013e4b04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28744
08723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.2874408723
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.173976568
Short name T1931
Test name
Test status
Simulation time 3285315828 ps
CPU time 4.28 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206720 kb
Host smart-2ff66ec9-7e70-4b32-83a2-6e705d7e6257
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17397
6568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.173976568
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1971571787
Short name T1026
Test name
Test status
Simulation time 13362556431 ps
CPU time 128.56 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206904 kb
Host smart-43fba4cb-daea-45a5-a811-7d75fdb0d5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
71787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1971571787
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.4179909893
Short name T2710
Test name
Test status
Simulation time 4630862395 ps
CPU time 33.91 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:25:29 PM PDT 24
Peak memory 206852 kb
Host smart-4f86f81f-feaf-4d27-8675-b152bd855127
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4179909893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.4179909893
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.289729968
Short name T23
Test name
Test status
Simulation time 260350068 ps
CPU time 0.93 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206668 kb
Host smart-cec0d989-b8d8-4510-95d1-0b8164fc300a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=289729968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.289729968
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.1652826293
Short name T333
Test name
Test status
Simulation time 194796257 ps
CPU time 0.88 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206636 kb
Host smart-cae23056-1b13-4ea5-87b6-07bd65bb2290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16528
26293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.1652826293
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.104137105
Short name T449
Test name
Test status
Simulation time 5052721225 ps
CPU time 36.68 seconds
Started Jul 20 06:25:00 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206852 kb
Host smart-e172ef3b-052e-4ddd-82c2-64b71021048a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10413
7105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.104137105
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1017367024
Short name T2147
Test name
Test status
Simulation time 5258004005 ps
CPU time 48.82 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:25:47 PM PDT 24
Peak memory 206896 kb
Host smart-4e997968-7076-4c4a-99ad-d91d1494ef5a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1017367024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1017367024
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.861626003
Short name T1352
Test name
Test status
Simulation time 179959249 ps
CPU time 0.86 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206640 kb
Host smart-229a6380-86b6-4940-8877-60eed00b7cde
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=861626003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.861626003
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3506341132
Short name T922
Test name
Test status
Simulation time 156667726 ps
CPU time 0.8 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206656 kb
Host smart-359838ec-f280-418e-b2d3-6ccc22d27567
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35063
41132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3506341132
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2897497570
Short name T127
Test name
Test status
Simulation time 243889399 ps
CPU time 1 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206592 kb
Host smart-dd874632-f215-4692-975a-569d8917257a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28974
97570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2897497570
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.348717485
Short name T1590
Test name
Test status
Simulation time 195147778 ps
CPU time 0.87 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206648 kb
Host smart-a9fa719b-ba39-4356-9b92-bad344f30852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34871
7485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.348717485
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.162710037
Short name T963
Test name
Test status
Simulation time 160639031 ps
CPU time 0.82 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206668 kb
Host smart-32395b96-a90f-4334-9bb6-adb597921079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16271
0037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.162710037
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.3796441774
Short name T2641
Test name
Test status
Simulation time 194144318 ps
CPU time 0.81 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206652 kb
Host smart-96c21201-5c83-4d83-933b-13c6e0c0c70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37964
41774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.3796441774
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3332218318
Short name T2341
Test name
Test status
Simulation time 148520499 ps
CPU time 0.8 seconds
Started Jul 20 06:24:57 PM PDT 24
Finished Jul 20 06:25:01 PM PDT 24
Peak memory 206608 kb
Host smart-7e68cba7-d860-465d-98a6-2b1fa8628b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33322
18318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3332218318
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.1150791750
Short name T1788
Test name
Test status
Simulation time 243382882 ps
CPU time 0.95 seconds
Started Jul 20 06:24:59 PM PDT 24
Finished Jul 20 06:25:02 PM PDT 24
Peak memory 206652 kb
Host smart-7fe4a889-d60a-43fb-bfb8-462e0db1fc6c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1150791750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.1150791750
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.4228879259
Short name T1713
Test name
Test status
Simulation time 147251849 ps
CPU time 0.76 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206632 kb
Host smart-ab87492f-506b-4f9f-902c-d8e443887b1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42288
79259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.4228879259
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1182323225
Short name T1705
Test name
Test status
Simulation time 49577967 ps
CPU time 0.67 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206616 kb
Host smart-b341da2c-5686-492a-91c9-dd61beeae31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11823
23225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1182323225
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.967902993
Short name T276
Test name
Test status
Simulation time 17838067575 ps
CPU time 39.7 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:25:39 PM PDT 24
Peak memory 206948 kb
Host smart-ceba7d71-0494-4b0d-b0af-d4d67c20ce4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96790
2993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.967902993
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1753746053
Short name T1605
Test name
Test status
Simulation time 154177781 ps
CPU time 0.81 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206652 kb
Host smart-0f62f494-e58d-4b99-ac56-3215ec5d46ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17537
46053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1753746053
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3262482756
Short name T815
Test name
Test status
Simulation time 226349144 ps
CPU time 0.91 seconds
Started Jul 20 06:24:52 PM PDT 24
Finished Jul 20 06:24:54 PM PDT 24
Peak memory 206628 kb
Host smart-7569b7c7-5fae-407c-bcd0-6d72cbffc956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32624
82756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3262482756
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.3096106197
Short name T1457
Test name
Test status
Simulation time 205524913 ps
CPU time 0.89 seconds
Started Jul 20 06:24:52 PM PDT 24
Finished Jul 20 06:24:54 PM PDT 24
Peak memory 206648 kb
Host smart-32780969-26d9-41a1-acfd-cf41b2977296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30961
06197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.3096106197
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1682006821
Short name T2110
Test name
Test status
Simulation time 184739095 ps
CPU time 0.89 seconds
Started Jul 20 06:24:50 PM PDT 24
Finished Jul 20 06:24:51 PM PDT 24
Peak memory 206632 kb
Host smart-ba8e0cd1-dffb-48f6-86dc-6155722c0e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16820
06821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1682006821
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1219987653
Short name T2360
Test name
Test status
Simulation time 138118371 ps
CPU time 0.76 seconds
Started Jul 20 06:24:59 PM PDT 24
Finished Jul 20 06:25:01 PM PDT 24
Peak memory 206652 kb
Host smart-cae8271d-2a11-4887-9bff-1f5afa149baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12199
87653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1219987653
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.1561189849
Short name T822
Test name
Test status
Simulation time 162920554 ps
CPU time 0.78 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206648 kb
Host smart-cfc29b75-c099-4e02-a630-7d5997d31a5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15611
89849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.1561189849
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1167014260
Short name T1142
Test name
Test status
Simulation time 156525709 ps
CPU time 0.79 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206652 kb
Host smart-7a99b857-5ce3-4976-9c12-279d039188d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
14260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1167014260
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3625337578
Short name T1045
Test name
Test status
Simulation time 235109253 ps
CPU time 0.94 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206644 kb
Host smart-e6e8401c-46f6-4a0b-b6e8-3672cc2e8e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36253
37578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3625337578
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.4037353192
Short name T1394
Test name
Test status
Simulation time 4930318039 ps
CPU time 35.71 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206812 kb
Host smart-a2f91d8b-9cd5-4a20-8424-decbe4a553f8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4037353192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.4037353192
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.3751431153
Short name T532
Test name
Test status
Simulation time 186663237 ps
CPU time 0.85 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206636 kb
Host smart-88169ffe-9d7c-4503-9302-b14efb20e948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37514
31153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.3751431153
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1030108804
Short name T776
Test name
Test status
Simulation time 216894994 ps
CPU time 0.91 seconds
Started Jul 20 06:24:56 PM PDT 24
Finished Jul 20 06:25:00 PM PDT 24
Peak memory 206660 kb
Host smart-7eefd29e-5fb7-46b7-88b4-b4c4cf47759d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
08804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1030108804
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.2052450842
Short name T435
Test name
Test status
Simulation time 640911732 ps
CPU time 1.69 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206640 kb
Host smart-b1190236-6398-4a52-a5b1-f4e0b32c4d73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20524
50842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.2052450842
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.547579121
Short name T2396
Test name
Test status
Simulation time 3345010855 ps
CPU time 24.56 seconds
Started Jul 20 06:24:55 PM PDT 24
Finished Jul 20 06:25:23 PM PDT 24
Peak memory 206860 kb
Host smart-eb48e2ca-ce3e-494e-b0b2-d23c96555f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54757
9121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.547579121
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.4165910760
Short name T2534
Test name
Test status
Simulation time 39911138 ps
CPU time 0.69 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206700 kb
Host smart-4fca9d43-b17b-4ebb-8772-885f5de3062a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4165910760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.4165910760
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1989777663
Short name T468
Test name
Test status
Simulation time 4105404777 ps
CPU time 4.96 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206716 kb
Host smart-a4887f5d-54ff-480f-aae4-902c136e60ff
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1989777663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1989777663
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3187843067
Short name T1003
Test name
Test status
Simulation time 13308006142 ps
CPU time 12.11 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:25:04 PM PDT 24
Peak memory 206872 kb
Host smart-9580cf1b-7633-4866-b085-3f04f79517ff
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3187843067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3187843067
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1754832212
Short name T1639
Test name
Test status
Simulation time 23516379560 ps
CPU time 24.13 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:25:20 PM PDT 24
Peak memory 206868 kb
Host smart-6d50cceb-b302-4e51-9a86-5785c1752b67
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1754832212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1754832212
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.3904780487
Short name T2389
Test name
Test status
Simulation time 144659554 ps
CPU time 0.82 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206660 kb
Host smart-27c079ad-ba81-44dd-8d18-43e9b8aeddea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39047
80487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.3904780487
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3839469874
Short name T961
Test name
Test status
Simulation time 160572757 ps
CPU time 0.8 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206632 kb
Host smart-dd74c3b1-c770-4729-a0ad-2a57921df031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38394
69874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3839469874
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3387101481
Short name T2118
Test name
Test status
Simulation time 522825160 ps
CPU time 1.56 seconds
Started Jul 20 06:24:51 PM PDT 24
Finished Jul 20 06:24:53 PM PDT 24
Peak memory 206788 kb
Host smart-18f2dfc5-ec5b-4c4c-a4e9-0f29b9a0fc0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33871
01481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3387101481
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3810665163
Short name T2094
Test name
Test status
Simulation time 1086653757 ps
CPU time 2.67 seconds
Started Jul 20 06:24:59 PM PDT 24
Finished Jul 20 06:25:03 PM PDT 24
Peak memory 206668 kb
Host smart-1601b960-7c7e-4ca1-aa27-0ed5fb7fee99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38106
65163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3810665163
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3256364700
Short name T1951
Test name
Test status
Simulation time 13249994212 ps
CPU time 28.36 seconds
Started Jul 20 06:24:54 PM PDT 24
Finished Jul 20 06:25:26 PM PDT 24
Peak memory 206924 kb
Host smart-2ede708f-124c-4b6a-88ad-fa56baeb8aed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32563
64700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3256364700
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.14651145
Short name T2266
Test name
Test status
Simulation time 494178757 ps
CPU time 1.61 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:58 PM PDT 24
Peak memory 206640 kb
Host smart-2ed87214-caf9-4235-adca-b2f31749957e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651
145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.14651145
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.4239170966
Short name T2659
Test name
Test status
Simulation time 151896034 ps
CPU time 0.78 seconds
Started Jul 20 06:24:53 PM PDT 24
Finished Jul 20 06:24:56 PM PDT 24
Peak memory 206656 kb
Host smart-742c9a79-62db-4561-be74-3ae8dcf2b237
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42391
70966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.4239170966
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1037241431
Short name T800
Test name
Test status
Simulation time 72463411 ps
CPU time 0.7 seconds
Started Jul 20 06:25:12 PM PDT 24
Finished Jul 20 06:25:18 PM PDT 24
Peak memory 206648 kb
Host smart-52ebb095-cb4a-479d-b8e4-c7fd40458720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372
41431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1037241431
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1111966452
Short name T926
Test name
Test status
Simulation time 746820618 ps
CPU time 1.95 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:15 PM PDT 24
Peak memory 206844 kb
Host smart-c4f235d2-10ee-45d6-84cc-386ab035de53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11119
66452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1111966452
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.3909615728
Short name T1617
Test name
Test status
Simulation time 297673002 ps
CPU time 1.91 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:15 PM PDT 24
Peak memory 206796 kb
Host smart-84fe232f-4fa3-4a8d-83c2-c3b5b1c6ef72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39096
15728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.3909615728
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.491744023
Short name T2320
Test name
Test status
Simulation time 191424727 ps
CPU time 0.91 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206644 kb
Host smart-240bc8f2-438c-40d7-b2bc-be70e89899eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49174
4023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.491744023
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.1270267870
Short name T2589
Test name
Test status
Simulation time 156306052 ps
CPU time 0.77 seconds
Started Jul 20 06:25:07 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206656 kb
Host smart-67cdb454-be30-4086-a40e-7b4da792f6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12702
67870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.1270267870
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.723395218
Short name T1919
Test name
Test status
Simulation time 187203078 ps
CPU time 0.88 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206592 kb
Host smart-7a5689b1-31bd-46bd-a40b-aeefd24bd02f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72339
5218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.723395218
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2626190916
Short name T375
Test name
Test status
Simulation time 6149627203 ps
CPU time 23.34 seconds
Started Jul 20 06:25:06 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206820 kb
Host smart-054119c0-19c1-4242-80b3-30d3fe4f9002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26261
90916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2626190916
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.1889098240
Short name T975
Test name
Test status
Simulation time 175835630 ps
CPU time 0.79 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206648 kb
Host smart-90608bd4-408e-4505-82dd-d12cccdbbd22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18890
98240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1889098240
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2164410052
Short name T1629
Test name
Test status
Simulation time 23281652869 ps
CPU time 22.52 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:34 PM PDT 24
Peak memory 206776 kb
Host smart-2867b33d-c3a4-4436-bd81-43dd87c2fed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21644
10052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2164410052
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1187981708
Short name T240
Test name
Test status
Simulation time 3333600445 ps
CPU time 4.08 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:23 PM PDT 24
Peak memory 206708 kb
Host smart-beaeaaa3-7512-45a6-af4c-1297860c4427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11879
81708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1187981708
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.244736751
Short name T1289
Test name
Test status
Simulation time 7350789161 ps
CPU time 193.96 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:28:25 PM PDT 24
Peak memory 206960 kb
Host smart-5392d49f-ca41-4d73-92cd-6cb4b5b1cd4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24473
6751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.244736751
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.1229165505
Short name T158
Test name
Test status
Simulation time 3607607226 ps
CPU time 97.68 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:26:52 PM PDT 24
Peak memory 206824 kb
Host smart-15384de2-78f8-4a23-841a-ee61e897acda
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1229165505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.1229165505
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.2930913250
Short name T2546
Test name
Test status
Simulation time 236845641 ps
CPU time 0.88 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206644 kb
Host smart-0f3d872a-93e3-4062-b389-2a6bdb141da7
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2930913250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.2930913250
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2739038948
Short name T1339
Test name
Test status
Simulation time 193306385 ps
CPU time 0.92 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:12 PM PDT 24
Peak memory 206644 kb
Host smart-0206d927-7b97-4a9b-b55e-cf3f4631fc75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390
38948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2739038948
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.4242769154
Short name T1197
Test name
Test status
Simulation time 6022800542 ps
CPU time 168.7 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 206836 kb
Host smart-58de0d60-39c1-4c88-a5f2-8a8dd9168714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
69154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.4242769154
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.2331658945
Short name T2047
Test name
Test status
Simulation time 5152618193 ps
CPU time 136.08 seconds
Started Jul 20 06:25:06 PM PDT 24
Finished Jul 20 06:27:22 PM PDT 24
Peak memory 206956 kb
Host smart-cde920c9-73f3-44bc-a22f-2ff9e662acae
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2331658945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.2331658945
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3441213856
Short name T561
Test name
Test status
Simulation time 177437534 ps
CPU time 0.85 seconds
Started Jul 20 06:25:12 PM PDT 24
Finished Jul 20 06:25:18 PM PDT 24
Peak memory 206652 kb
Host smart-6a067516-49a8-47f6-be6d-ea6e8822e62d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3441213856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3441213856
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3559778624
Short name T1414
Test name
Test status
Simulation time 156446442 ps
CPU time 0.76 seconds
Started Jul 20 06:25:06 PM PDT 24
Finished Jul 20 06:25:07 PM PDT 24
Peak memory 206656 kb
Host smart-0528caf7-c7d8-4731-aa82-60b87e23c341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35597
78624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3559778624
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.2551537547
Short name T513
Test name
Test status
Simulation time 178164716 ps
CPU time 0.9 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:14 PM PDT 24
Peak memory 206652 kb
Host smart-20ff2d03-0d97-45e2-8dc7-54c54ae4fe4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25515
37547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.2551537547
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.3638301309
Short name T1602
Test name
Test status
Simulation time 193868290 ps
CPU time 0.83 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206636 kb
Host smart-1cdde57c-f92d-468f-b7f5-243cbcaf46e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36383
01309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.3638301309
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.3149237750
Short name T1908
Test name
Test status
Simulation time 160174188 ps
CPU time 0.8 seconds
Started Jul 20 06:25:07 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206636 kb
Host smart-ba085ec7-3cbf-4324-8f8e-3fb4afe4113e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31492
37750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.3149237750
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2240973908
Short name T908
Test name
Test status
Simulation time 153048910 ps
CPU time 0.81 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:15 PM PDT 24
Peak memory 206648 kb
Host smart-757afe3a-5711-4067-bc21-ad7ee8f89e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22409
73908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2240973908
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.3889347825
Short name T83
Test name
Test status
Simulation time 226907522 ps
CPU time 0.98 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:20 PM PDT 24
Peak memory 206592 kb
Host smart-d489eb0e-f989-4fe7-9ffa-06ff842028b5
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3889347825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.3889347825
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.2965347584
Short name T2630
Test name
Test status
Simulation time 193056618 ps
CPU time 0.78 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206656 kb
Host smart-a03389fd-5bae-452b-bd22-3ba1802fec4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29653
47584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.2965347584
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.3100845385
Short name T1067
Test name
Test status
Simulation time 41702367 ps
CPU time 0.7 seconds
Started Jul 20 06:25:07 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206636 kb
Host smart-9c9d618a-5284-497f-9034-40344ae2a295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31008
45385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.3100845385
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.990841740
Short name T1116
Test name
Test status
Simulation time 7403248552 ps
CPU time 17.51 seconds
Started Jul 20 06:25:06 PM PDT 24
Finished Jul 20 06:25:25 PM PDT 24
Peak memory 206904 kb
Host smart-706b665c-fd05-426b-b72d-9f7813968762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99084
1740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.990841740
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.253734931
Short name T460
Test name
Test status
Simulation time 161876427 ps
CPU time 0.83 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206648 kb
Host smart-50de291d-c290-4b2d-b3ee-4f25a3d9b97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25373
4931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.253734931
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3802241735
Short name T341
Test name
Test status
Simulation time 215810885 ps
CPU time 0.9 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206648 kb
Host smart-acbca715-1ad6-458c-8d12-c1601170da9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38022
41735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3802241735
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.1120450543
Short name T1262
Test name
Test status
Simulation time 162851043 ps
CPU time 0.85 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:25:21 PM PDT 24
Peak memory 206656 kb
Host smart-7e64c1d1-3f63-42ed-9553-fe9cdffcd8f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11204
50543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.1120450543
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.4056943134
Short name T1915
Test name
Test status
Simulation time 194554831 ps
CPU time 0.84 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206592 kb
Host smart-b80d4f1e-98d7-4360-9135-95fa451828d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40569
43134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.4056943134
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.775335878
Short name T75
Test name
Test status
Simulation time 218246338 ps
CPU time 0.89 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206628 kb
Host smart-6e9fad31-18c4-42dd-a738-ec282f4db888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77533
5878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.775335878
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.1132068548
Short name T929
Test name
Test status
Simulation time 152988989 ps
CPU time 0.8 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206624 kb
Host smart-c9e63142-3f33-44a9-990d-1c773ba3489b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
68548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.1132068548
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3713780677
Short name T355
Test name
Test status
Simulation time 146837824 ps
CPU time 0.73 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206656 kb
Host smart-89a34cb9-9366-4bf4-b355-d62bb10552f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37137
80677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3713780677
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2600423317
Short name T1041
Test name
Test status
Simulation time 216884977 ps
CPU time 1.02 seconds
Started Jul 20 06:25:07 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206640 kb
Host smart-ff5f33a7-3840-4c4d-b22a-44525f176cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26004
23317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2600423317
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2018865419
Short name T819
Test name
Test status
Simulation time 4450991435 ps
CPU time 120.67 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206772 kb
Host smart-e4ffa88a-eca6-460c-a6f6-ff11efcfcc83
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2018865419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2018865419
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1525909639
Short name T2027
Test name
Test status
Simulation time 180623505 ps
CPU time 0.84 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:12 PM PDT 24
Peak memory 206652 kb
Host smart-b01081d9-2bca-4629-a44f-4e9fb4f8de66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15259
09639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1525909639
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3224832213
Short name T386
Test name
Test status
Simulation time 171703166 ps
CPU time 0.81 seconds
Started Jul 20 06:25:12 PM PDT 24
Finished Jul 20 06:25:18 PM PDT 24
Peak memory 206644 kb
Host smart-25cb1e90-3d04-4ed7-ae33-accb9b82cbfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32248
32213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3224832213
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.757169539
Short name T788
Test name
Test status
Simulation time 1259512931 ps
CPU time 3.03 seconds
Started Jul 20 06:25:07 PM PDT 24
Finished Jul 20 06:25:12 PM PDT 24
Peak memory 206820 kb
Host smart-100f8ced-f531-4dfb-82bb-ba9bf7c5f0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75716
9539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.757169539
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1094694712
Short name T2143
Test name
Test status
Simulation time 4311766956 ps
CPU time 32.17 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:45 PM PDT 24
Peak memory 206936 kb
Host smart-dba4a46e-fb59-43a8-ae25-157d9d662177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10946
94712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1094694712
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.255540030
Short name T2013
Test name
Test status
Simulation time 49103305 ps
CPU time 0.74 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206700 kb
Host smart-f22f7b2b-0cc1-4e3c-bfb8-7f6cc92c48ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=255540030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.255540030
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.461760504
Short name T2691
Test name
Test status
Simulation time 4167646662 ps
CPU time 6.01 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:17 PM PDT 24
Peak memory 206716 kb
Host smart-dea5c828-d233-4d25-8d7b-83084ba7ae1c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=461760504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.461760504
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.833880949
Short name T1273
Test name
Test status
Simulation time 23337215908 ps
CPU time 24.19 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206784 kb
Host smart-d4dcd275-ddff-4fae-a9eb-42edf1541715
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=833880949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.833880949
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.2789070148
Short name T918
Test name
Test status
Simulation time 180206691 ps
CPU time 0.84 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:25:21 PM PDT 24
Peak memory 206336 kb
Host smart-0791bf93-3d03-4dfe-b276-91600b03a193
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27890
70148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.2789070148
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.1080386461
Short name T1364
Test name
Test status
Simulation time 176163960 ps
CPU time 0.82 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:17 PM PDT 24
Peak memory 206648 kb
Host smart-c36d5a8f-9dfa-4127-a86f-5095c162b5e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
86461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.1080386461
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.4108714171
Short name T1454
Test name
Test status
Simulation time 302432198 ps
CPU time 1.09 seconds
Started Jul 20 06:25:16 PM PDT 24
Finished Jul 20 06:25:23 PM PDT 24
Peak memory 206640 kb
Host smart-3f73d0ce-cf4b-474f-b821-86644bb4a351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41087
14171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.4108714171
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3248050776
Short name T1744
Test name
Test status
Simulation time 472466277 ps
CPU time 1.28 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:12 PM PDT 24
Peak memory 206652 kb
Host smart-251e02be-cf03-4382-be6b-64548ecd1397
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32480
50776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3248050776
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.1498414885
Short name T494
Test name
Test status
Simulation time 15470996001 ps
CPU time 29.41 seconds
Started Jul 20 06:25:07 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206844 kb
Host smart-83e03338-4716-45c6-ba78-d9a7a3750926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14984
14885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.1498414885
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.2475801241
Short name T2502
Test name
Test status
Simulation time 400706685 ps
CPU time 1.23 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206652 kb
Host smart-a6c09863-2bf5-4327-8f04-478a6fd31c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24758
01241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.2475801241
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.3142884008
Short name T1689
Test name
Test status
Simulation time 162659934 ps
CPU time 0.81 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:15 PM PDT 24
Peak memory 206652 kb
Host smart-f5ff6f39-bcc7-48ca-a866-9bcdb9d9cbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31428
84008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.3142884008
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.3452955918
Short name T1078
Test name
Test status
Simulation time 48200169 ps
CPU time 0.7 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206644 kb
Host smart-f0462f6c-7782-45ff-ac2d-18a20c499b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
55918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.3452955918
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.2206685761
Short name T2345
Test name
Test status
Simulation time 985785340 ps
CPU time 2.42 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:24 PM PDT 24
Peak memory 206800 kb
Host smart-eb7bae14-ef1e-4921-8355-12995f111f9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22066
85761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.2206685761
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3818660934
Short name T1860
Test name
Test status
Simulation time 201980969 ps
CPU time 1.43 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206796 kb
Host smart-7239fb62-b941-4249-8e9e-c575a43150e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38186
60934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3818660934
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2983823036
Short name T2231
Test name
Test status
Simulation time 220058156 ps
CPU time 0.83 seconds
Started Jul 20 06:25:07 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206656 kb
Host smart-a0b37e4d-2a7b-41fe-8126-c70187761e1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29838
23036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2983823036
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3306629772
Short name T2334
Test name
Test status
Simulation time 135984995 ps
CPU time 0.74 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:26 PM PDT 24
Peak memory 206096 kb
Host smart-1c38deda-d655-45b9-9f86-cbce94cb2c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33066
29772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3306629772
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.2360174375
Short name T1133
Test name
Test status
Simulation time 190162022 ps
CPU time 0.91 seconds
Started Jul 20 06:25:32 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206652 kb
Host smart-ef6426a6-3f16-48bf-b73d-4400949e8c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23601
74375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.2360174375
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2724974214
Short name T1316
Test name
Test status
Simulation time 7540177715 ps
CPU time 68.27 seconds
Started Jul 20 06:25:08 PM PDT 24
Finished Jul 20 06:26:19 PM PDT 24
Peak memory 206824 kb
Host smart-257e0dd0-0e71-49a3-92eb-f89711e8fa19
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2724974214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2724974214
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.3920063835
Short name T503
Test name
Test status
Simulation time 13724219820 ps
CPU time 43.12 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:59 PM PDT 24
Peak memory 206924 kb
Host smart-198365f6-1095-4d83-b761-f958e58a2dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39200
63835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.3920063835
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3068183519
Short name T2015
Test name
Test status
Simulation time 261682644 ps
CPU time 1.03 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206592 kb
Host smart-a124635c-48f4-4411-806f-8a129a4301f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30681
83519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3068183519
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.1806373732
Short name T938
Test name
Test status
Simulation time 23299496238 ps
CPU time 20.52 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:44 PM PDT 24
Peak memory 206776 kb
Host smart-20bace77-945a-4417-b0c4-3cc10536631e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18063
73732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.1806373732
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.4273851313
Short name T1792
Test name
Test status
Simulation time 3297291152 ps
CPU time 3.56 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:17 PM PDT 24
Peak memory 206708 kb
Host smart-05e63c29-17c1-49aa-a608-7ed032c5bd07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42738
51313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.4273851313
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.3350433149
Short name T2333
Test name
Test status
Simulation time 8636551568 ps
CPU time 242.51 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:29:24 PM PDT 24
Peak memory 206924 kb
Host smart-b76e12dc-79b2-49cc-a7d8-2b37096f397c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33504
33149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.3350433149
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1947235524
Short name T1318
Test name
Test status
Simulation time 5317278497 ps
CPU time 39.11 seconds
Started Jul 20 06:25:14 PM PDT 24
Finished Jul 20 06:25:59 PM PDT 24
Peak memory 206848 kb
Host smart-de525f7e-344d-4c5e-9470-7e49a6a170d8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1947235524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1947235524
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.3443621932
Short name T1895
Test name
Test status
Simulation time 291240382 ps
CPU time 0.94 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:25:29 PM PDT 24
Peak memory 206400 kb
Host smart-f686b3cc-b4a6-4752-afaa-96e15cd9a18a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3443621932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.3443621932
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.940062519
Short name T309
Test name
Test status
Simulation time 195553470 ps
CPU time 0.89 seconds
Started Jul 20 06:25:30 PM PDT 24
Finished Jul 20 06:25:35 PM PDT 24
Peak memory 206652 kb
Host smart-0ebcb3df-9041-47e7-8e7b-f894fa309ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94006
2519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.940062519
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3663219618
Short name T2567
Test name
Test status
Simulation time 4159626317 ps
CPU time 30.69 seconds
Started Jul 20 06:25:16 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206860 kb
Host smart-b9993d30-7762-4eef-a064-a10745232c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36632
19618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3663219618
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3528799275
Short name T1823
Test name
Test status
Simulation time 4134122116 ps
CPU time 38.85 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:55 PM PDT 24
Peak memory 206856 kb
Host smart-2d4dd80b-8717-4af7-88d8-40869b9391f4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3528799275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3528799275
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.3364874623
Short name T2588
Test name
Test status
Simulation time 169845580 ps
CPU time 0.82 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:25 PM PDT 24
Peak memory 206656 kb
Host smart-a4354a9c-2467-49f8-8f23-730e7497ee20
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3364874623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.3364874623
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.1737695809
Short name T1464
Test name
Test status
Simulation time 161165095 ps
CPU time 0.76 seconds
Started Jul 20 06:25:16 PM PDT 24
Finished Jul 20 06:25:22 PM PDT 24
Peak memory 206648 kb
Host smart-77bd9f73-2471-4edc-aaae-774861622d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17376
95809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.1737695809
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1629291839
Short name T121
Test name
Test status
Simulation time 238540952 ps
CPU time 0.89 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:26 PM PDT 24
Peak memory 206652 kb
Host smart-8212a924-326c-49cf-89f9-e26add226258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16292
91839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1629291839
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.524191943
Short name T1080
Test name
Test status
Simulation time 181315402 ps
CPU time 0.86 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:17 PM PDT 24
Peak memory 206648 kb
Host smart-880dc42c-7737-4d92-b6b8-cec6906b3526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52419
1943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.524191943
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.3011046852
Short name T1065
Test name
Test status
Simulation time 152980749 ps
CPU time 0.77 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:14 PM PDT 24
Peak memory 206660 kb
Host smart-0d374f36-c480-4155-8fa5-5a61ea066364
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30110
46852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.3011046852
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.3766031993
Short name T99
Test name
Test status
Simulation time 226580564 ps
CPU time 0.88 seconds
Started Jul 20 06:25:22 PM PDT 24
Finished Jul 20 06:25:28 PM PDT 24
Peak memory 206660 kb
Host smart-137e28c8-88fd-403e-8e6d-c21914b0ed8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
31993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.3766031993
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.735990014
Short name T526
Test name
Test status
Simulation time 149793627 ps
CPU time 0.77 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:25 PM PDT 24
Peak memory 206656 kb
Host smart-b50721f7-4ef0-4701-89a8-5ddbbeac3f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73599
0014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.735990014
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.929098629
Short name T1821
Test name
Test status
Simulation time 253859937 ps
CPU time 0.94 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:25:21 PM PDT 24
Peak memory 206656 kb
Host smart-2cd7e3cd-dde4-4d1f-806d-68347a016c8c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=929098629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.929098629
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2871362583
Short name T2340
Test name
Test status
Simulation time 161073067 ps
CPU time 0.79 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:25:22 PM PDT 24
Peak memory 206644 kb
Host smart-2379a141-5166-48e3-a552-224158fb7cb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28713
62583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2871362583
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.1051410508
Short name T1921
Test name
Test status
Simulation time 71323980 ps
CPU time 0.67 seconds
Started Jul 20 06:25:18 PM PDT 24
Finished Jul 20 06:25:24 PM PDT 24
Peak memory 206648 kb
Host smart-abcc7bc6-870e-4a36-beee-d98332691549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10514
10508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.1051410508
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1544252757
Short name T1370
Test name
Test status
Simulation time 11402346365 ps
CPU time 24.01 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:48 PM PDT 24
Peak memory 206952 kb
Host smart-412d2972-cd65-4b24-960e-f5d6b162b319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15442
52757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1544252757
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.818389182
Short name T544
Test name
Test status
Simulation time 158957244 ps
CPU time 0.81 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206660 kb
Host smart-75de23ac-bf96-496c-86a8-42bf7c2fe3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81838
9182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.818389182
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.2428537729
Short name T2262
Test name
Test status
Simulation time 230614893 ps
CPU time 0.92 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206596 kb
Host smart-979414a7-3af5-4afc-843b-e39f9488c154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24285
37729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.2428537729
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1846906057
Short name T1114
Test name
Test status
Simulation time 181885287 ps
CPU time 0.81 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206652 kb
Host smart-fe3e3765-a06a-4601-b9e1-740040c64997
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
06057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1846906057
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.1152859550
Short name T2720
Test name
Test status
Simulation time 253027514 ps
CPU time 0.86 seconds
Started Jul 20 06:25:17 PM PDT 24
Finished Jul 20 06:25:24 PM PDT 24
Peak memory 206648 kb
Host smart-9a2fe68f-9742-476a-930d-3bf75091b3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11528
59550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.1152859550
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3720425928
Short name T2491
Test name
Test status
Simulation time 158760098 ps
CPU time 0.86 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206632 kb
Host smart-7211c26a-7309-447c-9be2-0c2c36820810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37204
25928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3720425928
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3210592628
Short name T634
Test name
Test status
Simulation time 152095887 ps
CPU time 0.81 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:26 PM PDT 24
Peak memory 206648 kb
Host smart-a665cc6f-5a3d-4be4-b4d7-92dc9329461f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32105
92628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3210592628
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.1303063708
Short name T2081
Test name
Test status
Simulation time 155156044 ps
CPU time 0.81 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:15 PM PDT 24
Peak memory 206640 kb
Host smart-44b3276e-238a-42f6-8fd2-9618648aeaef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13030
63708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.1303063708
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.1429165665
Short name T2598
Test name
Test status
Simulation time 188998831 ps
CPU time 0.84 seconds
Started Jul 20 06:25:17 PM PDT 24
Finished Jul 20 06:25:24 PM PDT 24
Peak memory 206644 kb
Host smart-c4a62c63-5550-443b-9bda-882d1f4eb010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14291
65665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.1429165665
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.2580471321
Short name T1061
Test name
Test status
Simulation time 5112340562 ps
CPU time 143.27 seconds
Started Jul 20 06:25:27 PM PDT 24
Finished Jul 20 06:27:55 PM PDT 24
Peak memory 206836 kb
Host smart-7dc732ee-4d69-4361-95e5-428e2678e6d3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2580471321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.2580471321
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.2731961800
Short name T1793
Test name
Test status
Simulation time 194972761 ps
CPU time 0.82 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:25:29 PM PDT 24
Peak memory 206652 kb
Host smart-7d7c44a3-860a-4303-879f-eb2ba5e68925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27319
61800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.2731961800
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.3544535304
Short name T1448
Test name
Test status
Simulation time 151580162 ps
CPU time 0.78 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206660 kb
Host smart-70370fe3-45fe-4813-8a40-8c7caa7b2c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35445
35304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.3544535304
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.1540909407
Short name T977
Test name
Test status
Simulation time 999685415 ps
CPU time 2.13 seconds
Started Jul 20 06:25:06 PM PDT 24
Finished Jul 20 06:25:09 PM PDT 24
Peak memory 206760 kb
Host smart-cadefe16-2a6b-42da-af23-e30461468551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15409
09407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.1540909407
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.108838094
Short name T495
Test name
Test status
Simulation time 5816313067 ps
CPU time 160.92 seconds
Started Jul 20 06:25:17 PM PDT 24
Finished Jul 20 06:28:04 PM PDT 24
Peak memory 206860 kb
Host smart-05205d65-ff40-400e-b116-f938724553a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10883
8094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.108838094
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2651492167
Short name T1024
Test name
Test status
Simulation time 36941070 ps
CPU time 0.63 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:25:28 PM PDT 24
Peak memory 206656 kb
Host smart-ad07c862-7636-4e28-a9b6-a1272d7990cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2651492167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2651492167
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.801694913
Short name T1812
Test name
Test status
Simulation time 4038504674 ps
CPU time 4.66 seconds
Started Jul 20 06:25:17 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206752 kb
Host smart-43734f6f-d376-421d-bddd-7dc154a12db1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=801694913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.801694913
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.851506166
Short name T588
Test name
Test status
Simulation time 13542244554 ps
CPU time 12.87 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206872 kb
Host smart-00e16772-bcf1-49d5-aae2-5929568d3a68
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=851506166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.851506166
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.2251663755
Short name T1843
Test name
Test status
Simulation time 23332786131 ps
CPU time 23.63 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206780 kb
Host smart-76694ee3-fc03-4c52-acbf-d00fb83f739f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2251663755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.2251663755
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2459215169
Short name T2675
Test name
Test status
Simulation time 178799948 ps
CPU time 0.9 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206596 kb
Host smart-fc98dfaa-7d99-4e9d-809a-762f8181fdb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24592
15169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2459215169
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2966847728
Short name T797
Test name
Test status
Simulation time 157653431 ps
CPU time 0.78 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:13 PM PDT 24
Peak memory 206664 kb
Host smart-3f3ed686-3455-47a7-8ef6-0f93236e1241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29668
47728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2966847728
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.694608440
Short name T107
Test name
Test status
Simulation time 550888233 ps
CPU time 1.52 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206720 kb
Host smart-c36909f4-084e-4c58-911b-461eca9a9912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69460
8440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.694608440
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.689274636
Short name T1272
Test name
Test status
Simulation time 584184521 ps
CPU time 1.44 seconds
Started Jul 20 06:25:17 PM PDT 24
Finished Jul 20 06:25:24 PM PDT 24
Peak memory 206644 kb
Host smart-78a9ac65-db0d-4f7c-b74c-0889e9a85d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68927
4636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.689274636
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.3651807351
Short name T2209
Test name
Test status
Simulation time 10351735125 ps
CPU time 20.68 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206912 kb
Host smart-ff4d3d60-cc7c-4b63-b2b9-039b7f4fc4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36518
07351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.3651807351
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.2625932168
Short name T676
Test name
Test status
Simulation time 320427568 ps
CPU time 1.1 seconds
Started Jul 20 06:25:20 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206652 kb
Host smart-ee9ead4a-037f-48a7-927c-c8fef87e9631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26259
32168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.2625932168
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.1680836003
Short name T1714
Test name
Test status
Simulation time 143895709 ps
CPU time 0.85 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:19 PM PDT 24
Peak memory 206624 kb
Host smart-e5fcb63c-8f55-471b-abd5-d04f1aca3fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
36003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.1680836003
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3769034174
Short name T420
Test name
Test status
Simulation time 39781664 ps
CPU time 0.71 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206592 kb
Host smart-98aa5fe7-f722-4776-9ce4-e50cc76c863d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37690
34174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3769034174
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3005907588
Short name T1848
Test name
Test status
Simulation time 911769270 ps
CPU time 2.39 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:25:20 PM PDT 24
Peak memory 206464 kb
Host smart-73b3267d-d88d-445f-b7ad-15ef434894d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30059
07588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3005907588
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.1013006493
Short name T735
Test name
Test status
Simulation time 312043150 ps
CPU time 1.66 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206736 kb
Host smart-1d3678d7-0a10-4560-b326-f746651d56df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10130
06493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.1013006493
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.3124115011
Short name T548
Test name
Test status
Simulation time 190807948 ps
CPU time 0.84 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206640 kb
Host smart-6a87c87d-a9b3-4403-906a-1552de44f0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31241
15011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.3124115011
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.1992727581
Short name T109
Test name
Test status
Simulation time 167071278 ps
CPU time 0.81 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:25:16 PM PDT 24
Peak memory 206660 kb
Host smart-416a42b7-47d2-4878-97d9-58929734f126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19927
27581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.1992727581
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.1715275879
Short name T1684
Test name
Test status
Simulation time 186116473 ps
CPU time 0.84 seconds
Started Jul 20 06:25:21 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206636 kb
Host smart-47bacc3b-4bc9-4ed2-a282-eaa458ea4e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17152
75879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.1715275879
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.1068885378
Short name T1594
Test name
Test status
Simulation time 5139776513 ps
CPU time 46.23 seconds
Started Jul 20 06:25:13 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206816 kb
Host smart-fcf47a6e-777d-4c7b-af2d-94067fce33cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10688
85378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.1068885378
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.280338978
Short name T404
Test name
Test status
Simulation time 223221785 ps
CPU time 0.88 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:17 PM PDT 24
Peak memory 206624 kb
Host smart-5fe7a219-3178-44aa-a191-86a3a9527026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28033
8978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.280338978
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.954561530
Short name T1107
Test name
Test status
Simulation time 23322659903 ps
CPU time 23.1 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:25:39 PM PDT 24
Peak memory 206748 kb
Host smart-511126e2-b1c3-4ed9-90b6-fafd16d9ce08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95456
1530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.954561530
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2600344389
Short name T783
Test name
Test status
Simulation time 3280715721 ps
CPU time 3.79 seconds
Started Jul 20 06:25:09 PM PDT 24
Finished Jul 20 06:25:18 PM PDT 24
Peak memory 206728 kb
Host smart-631064ab-7fe3-4802-ab59-2b508782d2e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26003
44389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2600344389
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.580451172
Short name T591
Test name
Test status
Simulation time 10253658027 ps
CPU time 75.15 seconds
Started Jul 20 06:25:10 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206936 kb
Host smart-92649c7e-8b1e-481e-9706-d2b322ad99d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58045
1172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.580451172
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.2221430662
Short name T1880
Test name
Test status
Simulation time 6983118560 ps
CPU time 49.81 seconds
Started Jul 20 06:25:11 PM PDT 24
Finished Jul 20 06:26:06 PM PDT 24
Peak memory 206892 kb
Host smart-ae799c40-99a4-42d9-b244-d71ffac121bf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2221430662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.2221430662
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.902432786
Short name T1928
Test name
Test status
Simulation time 238459639 ps
CPU time 0.89 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:25:29 PM PDT 24
Peak memory 206596 kb
Host smart-f334e0b3-f5a2-4b1c-8851-4b57b009f6d2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=902432786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.902432786
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1495510392
Short name T1271
Test name
Test status
Simulation time 189351375 ps
CPU time 0.9 seconds
Started Jul 20 06:25:16 PM PDT 24
Finished Jul 20 06:25:23 PM PDT 24
Peak memory 206660 kb
Host smart-d478e612-b647-4029-8425-1a71cea2488b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14955
10392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1495510392
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.596515694
Short name T2615
Test name
Test status
Simulation time 5539209748 ps
CPU time 153.75 seconds
Started Jul 20 06:25:14 PM PDT 24
Finished Jul 20 06:27:53 PM PDT 24
Peak memory 206872 kb
Host smart-435d1d1c-9b62-4142-80be-50329dfb8cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59651
5694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.596515694
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.4158006165
Short name T985
Test name
Test status
Simulation time 5459673119 ps
CPU time 153.37 seconds
Started Jul 20 06:25:36 PM PDT 24
Finished Jul 20 06:28:12 PM PDT 24
Peak memory 206832 kb
Host smart-854c45e7-0e39-4307-90ff-71ae03d1f692
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4158006165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.4158006165
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.581028495
Short name T2446
Test name
Test status
Simulation time 169748345 ps
CPU time 0.81 seconds
Started Jul 20 06:25:20 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206652 kb
Host smart-1cc66e47-fa32-425d-b153-590f29751456
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=581028495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.581028495
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.4172070684
Short name T543
Test name
Test status
Simulation time 148857376 ps
CPU time 0.74 seconds
Started Jul 20 06:25:14 PM PDT 24
Finished Jul 20 06:25:20 PM PDT 24
Peak memory 206648 kb
Host smart-6a3f8242-29cd-43a6-9372-c904c4965f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41720
70684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.4172070684
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.617200015
Short name T1276
Test name
Test status
Simulation time 240791188 ps
CPU time 0.92 seconds
Started Jul 20 06:25:20 PM PDT 24
Finished Jul 20 06:25:26 PM PDT 24
Peak memory 206656 kb
Host smart-29d25a8e-7f01-4287-ac13-efa50f3d7a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61720
0015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.617200015
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.616515561
Short name T2626
Test name
Test status
Simulation time 181691504 ps
CPU time 0.84 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:25:22 PM PDT 24
Peak memory 206656 kb
Host smart-611f930f-67d5-4577-8c07-719b5bd16e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61651
5561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.616515561
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.4129150452
Short name T1124
Test name
Test status
Simulation time 202726718 ps
CPU time 0.84 seconds
Started Jul 20 06:25:17 PM PDT 24
Finished Jul 20 06:25:24 PM PDT 24
Peak memory 206652 kb
Host smart-c20aa469-9493-4675-809e-35cc38963941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41291
50452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.4129150452
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.550947814
Short name T1641
Test name
Test status
Simulation time 180127871 ps
CPU time 0.84 seconds
Started Jul 20 06:25:21 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206608 kb
Host smart-b38cbb5a-5c96-42ef-8f29-c78f0aacad79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55094
7814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.550947814
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.1386198989
Short name T1391
Test name
Test status
Simulation time 146601042 ps
CPU time 0.76 seconds
Started Jul 20 06:25:39 PM PDT 24
Finished Jul 20 06:25:40 PM PDT 24
Peak memory 206636 kb
Host smart-675513fd-b499-49ee-b5c5-43a90615db02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13861
98989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.1386198989
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.3231260064
Short name T896
Test name
Test status
Simulation time 182357217 ps
CPU time 0.89 seconds
Started Jul 20 06:25:39 PM PDT 24
Finished Jul 20 06:25:41 PM PDT 24
Peak memory 206636 kb
Host smart-91c79304-3d41-423a-a2a5-7b232efaac33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3231260064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.3231260064
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1135614144
Short name T1988
Test name
Test status
Simulation time 147911189 ps
CPU time 0.77 seconds
Started Jul 20 06:25:39 PM PDT 24
Finished Jul 20 06:25:41 PM PDT 24
Peak memory 206628 kb
Host smart-7fed4244-ca92-47af-8d2c-ab5c2e072a1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11356
14144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1135614144
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2968419339
Short name T1201
Test name
Test status
Simulation time 34149660 ps
CPU time 0.68 seconds
Started Jul 20 06:25:16 PM PDT 24
Finished Jul 20 06:25:22 PM PDT 24
Peak memory 206600 kb
Host smart-8e22b4c6-583c-46c2-a620-f4c3b5ca1d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29684
19339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2968419339
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1971578874
Short name T242
Test name
Test status
Simulation time 7015344577 ps
CPU time 15.38 seconds
Started Jul 20 06:25:16 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206952 kb
Host smart-3efd2d32-edb3-4b3f-9630-e5d667a2d550
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
78874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1971578874
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.4029543526
Short name T498
Test name
Test status
Simulation time 247568472 ps
CPU time 0.93 seconds
Started Jul 20 06:25:25 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206640 kb
Host smart-df65d6bf-d7e8-4957-9200-8255167e5313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40295
43526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.4029543526
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.3644766940
Short name T1092
Test name
Test status
Simulation time 227878477 ps
CPU time 0.88 seconds
Started Jul 20 06:25:21 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206628 kb
Host smart-a5937394-0453-4120-be54-1e2990640224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36447
66940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.3644766940
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2233866169
Short name T1692
Test name
Test status
Simulation time 175128125 ps
CPU time 0.8 seconds
Started Jul 20 06:25:26 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206628 kb
Host smart-b5b85e24-b42c-4af0-8d65-e98814c6447e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22338
66169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2233866169
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.984442743
Short name T2706
Test name
Test status
Simulation time 217417724 ps
CPU time 0.88 seconds
Started Jul 20 06:25:21 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206600 kb
Host smart-89678809-02a6-4d4b-9e5e-bc29978ccef2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98444
2743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.984442743
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3084944902
Short name T1053
Test name
Test status
Simulation time 139858877 ps
CPU time 0.7 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:25 PM PDT 24
Peak memory 206608 kb
Host smart-52369151-94f3-43e1-b8e0-9ab53a65cf46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30849
44902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3084944902
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.2197085915
Short name T1616
Test name
Test status
Simulation time 147164121 ps
CPU time 0.74 seconds
Started Jul 20 06:25:36 PM PDT 24
Finished Jul 20 06:25:39 PM PDT 24
Peak memory 206632 kb
Host smart-bf547187-a4f3-4c6f-8993-2ef2fe8e2801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21970
85915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.2197085915
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.449895831
Short name T1452
Test name
Test status
Simulation time 180903450 ps
CPU time 0.77 seconds
Started Jul 20 06:25:16 PM PDT 24
Finished Jul 20 06:25:22 PM PDT 24
Peak memory 206656 kb
Host smart-5a9ed0ac-5aeb-405d-be3d-63cad06f9e84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44989
5831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.449895831
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.1460326839
Short name T778
Test name
Test status
Simulation time 222796882 ps
CPU time 0.91 seconds
Started Jul 20 06:25:20 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206652 kb
Host smart-32dfe9f3-6841-4d73-9d2f-be13f27b9fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14603
26839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.1460326839
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.3388059672
Short name T1964
Test name
Test status
Simulation time 4410855684 ps
CPU time 29.99 seconds
Started Jul 20 06:25:19 PM PDT 24
Finished Jul 20 06:25:55 PM PDT 24
Peak memory 206856 kb
Host smart-8ec6c8af-96ae-475f-b4af-173d82e39cac
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3388059672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.3388059672
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.2983610363
Short name T566
Test name
Test status
Simulation time 183087231 ps
CPU time 0.89 seconds
Started Jul 20 06:25:14 PM PDT 24
Finished Jul 20 06:25:20 PM PDT 24
Peak memory 206628 kb
Host smart-6af9cf16-8537-4a60-a443-3cff44fe735c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29836
10363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.2983610363
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.226073817
Short name T913
Test name
Test status
Simulation time 175604231 ps
CPU time 0.78 seconds
Started Jul 20 06:25:20 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206640 kb
Host smart-745a1769-b718-4a96-ae6c-eea8bba4261a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22607
3817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.226073817
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.2285251467
Short name T1833
Test name
Test status
Simulation time 1083695591 ps
CPU time 2.29 seconds
Started Jul 20 06:25:22 PM PDT 24
Finished Jul 20 06:25:29 PM PDT 24
Peak memory 206728 kb
Host smart-f7b74a31-019f-45f3-9fd4-152c5e9aa7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22852
51467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.2285251467
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2988127820
Short name T708
Test name
Test status
Simulation time 5806079730 ps
CPU time 160.29 seconds
Started Jul 20 06:25:15 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 206864 kb
Host smart-3ada667a-5e5c-48f2-bda0-cdc5b6a3c148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29881
27820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2988127820
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.3116339560
Short name T403
Test name
Test status
Simulation time 58897697 ps
CPU time 0.69 seconds
Started Jul 20 06:25:36 PM PDT 24
Finished Jul 20 06:25:39 PM PDT 24
Peak memory 206696 kb
Host smart-7cbbeaca-0ebc-4301-a1b1-3a415062ced3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3116339560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.3116339560
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.2748866661
Short name T2207
Test name
Test status
Simulation time 13335772343 ps
CPU time 12.67 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:25:41 PM PDT 24
Peak memory 206744 kb
Host smart-e972e531-11ff-41cb-b9b7-9fe52e32d206
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2748866661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.2748866661
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1183184556
Short name T1767
Test name
Test status
Simulation time 23336192565 ps
CPU time 28.1 seconds
Started Jul 20 06:25:30 PM PDT 24
Finished Jul 20 06:26:02 PM PDT 24
Peak memory 206756 kb
Host smart-bda4eb07-9818-4dea-89f3-7ec2b92042a4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1183184556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.1183184556
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.2875559144
Short name T2280
Test name
Test status
Simulation time 193692698 ps
CPU time 0.84 seconds
Started Jul 20 06:25:21 PM PDT 24
Finished Jul 20 06:25:27 PM PDT 24
Peak memory 206636 kb
Host smart-62fa70e4-d8b9-487c-9d11-d34fb36d811d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28755
59144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.2875559144
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.867432828
Short name T2230
Test name
Test status
Simulation time 145653443 ps
CPU time 0.77 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206660 kb
Host smart-a8d138aa-12e3-480a-a4be-12d5219c69f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86743
2828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.867432828
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.2070680724
Short name T2167
Test name
Test status
Simulation time 199384664 ps
CPU time 0.92 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206652 kb
Host smart-db4f5d9d-a453-4691-a2b7-6279dfc60002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20706
80724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.2070680724
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.3986815764
Short name T2356
Test name
Test status
Simulation time 494240317 ps
CPU time 1.45 seconds
Started Jul 20 06:25:26 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206652 kb
Host smart-67ce8710-666a-4b82-9978-5f93ab4a6074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39868
15764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.3986815764
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2307773265
Short name T1032
Test name
Test status
Simulation time 12209495505 ps
CPU time 22.67 seconds
Started Jul 20 06:25:25 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206852 kb
Host smart-17cd5eaf-0d00-4149-bfec-4bff8687474b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23077
73265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2307773265
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.348554641
Short name T539
Test name
Test status
Simulation time 430249067 ps
CPU time 1.4 seconds
Started Jul 20 06:25:31 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206644 kb
Host smart-bf73a6e7-4c42-49b2-b3be-cbd36501d063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34855
4641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.348554641
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.2406113229
Short name T809
Test name
Test status
Simulation time 199917514 ps
CPU time 0.82 seconds
Started Jul 20 06:25:31 PM PDT 24
Finished Jul 20 06:25:35 PM PDT 24
Peak memory 206656 kb
Host smart-f9cf8de6-994a-4808-a967-47278a406c1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24061
13229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.2406113229
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2064928034
Short name T893
Test name
Test status
Simulation time 49108864 ps
CPU time 0.66 seconds
Started Jul 20 06:25:27 PM PDT 24
Finished Jul 20 06:25:33 PM PDT 24
Peak memory 206624 kb
Host smart-9a25ad05-fabf-4fc4-ab1b-ae64876e54a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20649
28034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2064928034
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.2611663053
Short name T2415
Test name
Test status
Simulation time 765492405 ps
CPU time 1.99 seconds
Started Jul 20 06:25:28 PM PDT 24
Finished Jul 20 06:25:35 PM PDT 24
Peak memory 206692 kb
Host smart-95cc10e2-48c4-4b2b-88b9-079294bf5887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26116
63053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.2611663053
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.4102114890
Short name T2103
Test name
Test status
Simulation time 197321157 ps
CPU time 1.63 seconds
Started Jul 20 06:25:30 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206712 kb
Host smart-8508d03b-4c93-4921-9f9d-c26827abcbba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41021
14890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.4102114890
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.1593638772
Short name T853
Test name
Test status
Simulation time 235396354 ps
CPU time 0.93 seconds
Started Jul 20 06:25:25 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206644 kb
Host smart-64f6b230-eeae-489e-b3fe-0eddfa88c668
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15936
38772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.1593638772
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1937483149
Short name T2658
Test name
Test status
Simulation time 137230186 ps
CPU time 0.76 seconds
Started Jul 20 06:25:31 PM PDT 24
Finished Jul 20 06:25:35 PM PDT 24
Peak memory 206640 kb
Host smart-4419db4b-35ff-4716-bdac-8667798098a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19374
83149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1937483149
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.704666008
Short name T1533
Test name
Test status
Simulation time 245564530 ps
CPU time 0.91 seconds
Started Jul 20 06:25:27 PM PDT 24
Finished Jul 20 06:25:33 PM PDT 24
Peak memory 206652 kb
Host smart-bf32c408-0460-42b9-9e1e-a77efbbba7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70466
6008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.704666008
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2190499252
Short name T427
Test name
Test status
Simulation time 3804333628 ps
CPU time 13.66 seconds
Started Jul 20 06:25:28 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206900 kb
Host smart-875a9f78-1430-4668-b87d-342b917c3fff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21904
99252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2190499252
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.185452208
Short name T2590
Test name
Test status
Simulation time 241230081 ps
CPU time 0.92 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206636 kb
Host smart-a2a6be82-1fa6-438a-a257-e4e566dec1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18545
2208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.185452208
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.2359916713
Short name T2028
Test name
Test status
Simulation time 23313435801 ps
CPU time 21.56 seconds
Started Jul 20 06:25:27 PM PDT 24
Finished Jul 20 06:25:53 PM PDT 24
Peak memory 206744 kb
Host smart-631ca3a0-a7c9-4055-b671-cc2a32e9804f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23599
16713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.2359916713
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.2886906877
Short name T707
Test name
Test status
Simulation time 3344437110 ps
CPU time 3.87 seconds
Started Jul 20 06:25:32 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206724 kb
Host smart-85a1d0bb-9a78-42f6-aeaa-8042dd8ebd99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28869
06877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.2886906877
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.3079320664
Short name T450
Test name
Test status
Simulation time 5605272207 ps
CPU time 52.82 seconds
Started Jul 20 06:25:22 PM PDT 24
Finished Jul 20 06:26:19 PM PDT 24
Peak memory 206904 kb
Host smart-3d0f948e-c48a-4a6a-b7de-9ae596db8280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30793
20664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.3079320664
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.2848759459
Short name T764
Test name
Test status
Simulation time 5312025975 ps
CPU time 52.4 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:26:21 PM PDT 24
Peak memory 206896 kb
Host smart-d063d294-1b76-4364-ae3f-2b3911388a10
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2848759459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.2848759459
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.618267148
Short name T2150
Test name
Test status
Simulation time 269165652 ps
CPU time 0.98 seconds
Started Jul 20 06:25:30 PM PDT 24
Finished Jul 20 06:25:34 PM PDT 24
Peak memory 206592 kb
Host smart-ce3da0f5-1886-47e4-8d41-1a5accb69383
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=618267148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.618267148
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.1884685949
Short name T1764
Test name
Test status
Simulation time 258273149 ps
CPU time 0.91 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206188 kb
Host smart-39aa5c8a-73cd-4888-9772-cee4829e9d9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18846
85949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.1884685949
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.1150015376
Short name T1115
Test name
Test status
Simulation time 4155407625 ps
CPU time 110.03 seconds
Started Jul 20 06:25:32 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206868 kb
Host smart-40e82f72-676c-482c-ae5c-62e7ccb1f81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11500
15376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.1150015376
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.3992462455
Short name T2420
Test name
Test status
Simulation time 3356998640 ps
CPU time 30.28 seconds
Started Jul 20 06:25:31 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206820 kb
Host smart-b6d9e50d-d72e-475c-aac3-1a8ac9e5e57f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3992462455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.3992462455
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.3284319884
Short name T1850
Test name
Test status
Simulation time 157176027 ps
CPU time 0.8 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206108 kb
Host smart-e438eb65-2cce-4c77-a1a3-29ba93fc126e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3284319884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.3284319884
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.2517277115
Short name T1447
Test name
Test status
Simulation time 150790863 ps
CPU time 0.81 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206652 kb
Host smart-43b0f76e-308c-420d-9d02-39b5630e7520
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25172
77115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.2517277115
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.122857789
Short name T1198
Test name
Test status
Simulation time 178166090 ps
CPU time 0.79 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206648 kb
Host smart-0c5957a4-5186-44a6-9bb8-12b24605b966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12285
7789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.122857789
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.3695368130
Short name T2486
Test name
Test status
Simulation time 152579919 ps
CPU time 0.77 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:25:28 PM PDT 24
Peak memory 206632 kb
Host smart-8310e010-be14-4856-9bab-c2ee6b12819d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36953
68130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.3695368130
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.4040287754
Short name T827
Test name
Test status
Simulation time 164396413 ps
CPU time 0.84 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206652 kb
Host smart-6747cd07-62e9-4915-98e8-113b574a5225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40402
87754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.4040287754
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3354627742
Short name T2543
Test name
Test status
Simulation time 255884117 ps
CPU time 0.98 seconds
Started Jul 20 06:25:25 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206648 kb
Host smart-8a4c1f64-f994-4340-acde-8128b9b63f32
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3354627742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3354627742
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.1890457388
Short name T1614
Test name
Test status
Simulation time 189957017 ps
CPU time 0.85 seconds
Started Jul 20 06:25:28 PM PDT 24
Finished Jul 20 06:25:33 PM PDT 24
Peak memory 206632 kb
Host smart-9ebe7e8f-d182-459d-aaae-5ba8b106abbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18904
57388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.1890457388
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.2569332622
Short name T2685
Test name
Test status
Simulation time 42100599 ps
CPU time 0.67 seconds
Started Jul 20 06:25:24 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206652 kb
Host smart-30cbf86d-1c5e-4c73-b014-1e86c6a54a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25693
32622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.2569332622
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.4104449357
Short name T2519
Test name
Test status
Simulation time 19526912988 ps
CPU time 40.97 seconds
Started Jul 20 06:25:26 PM PDT 24
Finished Jul 20 06:26:12 PM PDT 24
Peak memory 206928 kb
Host smart-8916f89f-ccb1-407a-821e-bd75d5e88df8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41044
49357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.4104449357
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.975115160
Short name T1087
Test name
Test status
Simulation time 195099704 ps
CPU time 0.82 seconds
Started Jul 20 06:25:26 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206660 kb
Host smart-6a536bd2-6b0e-46d6-9161-87978a6a9e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97511
5160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.975115160
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.704731070
Short name T1388
Test name
Test status
Simulation time 221697519 ps
CPU time 0.96 seconds
Started Jul 20 06:25:26 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206660 kb
Host smart-592fd54a-8888-4c22-b5d0-99410560c0e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70473
1070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.704731070
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.2723337275
Short name T1923
Test name
Test status
Simulation time 223009198 ps
CPU time 0.91 seconds
Started Jul 20 06:25:31 PM PDT 24
Finished Jul 20 06:25:35 PM PDT 24
Peak memory 206644 kb
Host smart-dc57b456-29ba-487c-a0f3-6258f8655a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27233
37275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.2723337275
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.166068091
Short name T2516
Test name
Test status
Simulation time 188692859 ps
CPU time 0.88 seconds
Started Jul 20 06:25:26 PM PDT 24
Finished Jul 20 06:25:32 PM PDT 24
Peak memory 206624 kb
Host smart-690c69b9-c6dc-44a5-ba27-929f1e57acfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16606
8091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.166068091
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.988261223
Short name T74
Test name
Test status
Simulation time 206723621 ps
CPU time 0.86 seconds
Started Jul 20 06:25:25 PM PDT 24
Finished Jul 20 06:25:30 PM PDT 24
Peak memory 206640 kb
Host smart-38b1f7ca-595a-4518-be53-e4b3c23aad2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98826
1223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.988261223
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.873315598
Short name T2126
Test name
Test status
Simulation time 165959504 ps
CPU time 0.79 seconds
Started Jul 20 06:25:23 PM PDT 24
Finished Jul 20 06:25:29 PM PDT 24
Peak memory 206660 kb
Host smart-5b140b31-9ab5-4782-96d8-40045a281ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87331
5598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.873315598
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1030335438
Short name T2020
Test name
Test status
Simulation time 160500623 ps
CPU time 0.81 seconds
Started Jul 20 06:25:22 PM PDT 24
Finished Jul 20 06:25:28 PM PDT 24
Peak memory 206696 kb
Host smart-bbbce4ef-3bf1-4144-aa65-8224afbea46f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10303
35438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1030335438
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2026277270
Short name T2138
Test name
Test status
Simulation time 197267654 ps
CPU time 0.88 seconds
Started Jul 20 06:25:32 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206620 kb
Host smart-4cba4063-3c17-4b18-b6ac-029b3fbc1f44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262
77270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2026277270
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.299450649
Short name T490
Test name
Test status
Simulation time 3529313559 ps
CPU time 36.35 seconds
Started Jul 20 06:25:31 PM PDT 24
Finished Jul 20 06:26:11 PM PDT 24
Peak memory 206924 kb
Host smart-3b0bd9af-f123-4f6f-9539-130303cc5ff3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=299450649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.299450649
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.3442995725
Short name T580
Test name
Test status
Simulation time 171983331 ps
CPU time 0.88 seconds
Started Jul 20 06:25:28 PM PDT 24
Finished Jul 20 06:25:33 PM PDT 24
Peak memory 206628 kb
Host smart-957d597f-431c-4a46-98b4-11756e0ca3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34429
95725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.3442995725
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.3468163372
Short name T2380
Test name
Test status
Simulation time 159300507 ps
CPU time 0.77 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206648 kb
Host smart-d1089d3a-2709-4b72-8147-1465f060e3c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34681
63372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.3468163372
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.4205470608
Short name T389
Test name
Test status
Simulation time 490774093 ps
CPU time 1.38 seconds
Started Jul 20 06:25:25 PM PDT 24
Finished Jul 20 06:25:31 PM PDT 24
Peak memory 206656 kb
Host smart-918d49ce-5a85-4c4e-b515-c2b0b6d3301d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42054
70608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.4205470608
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.858246131
Short name T557
Test name
Test status
Simulation time 6388434747 ps
CPU time 49.27 seconds
Started Jul 20 06:25:27 PM PDT 24
Finished Jul 20 06:26:21 PM PDT 24
Peak memory 206848 kb
Host smart-b002bd09-ad92-4fb6-874b-492112ab50cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85824
6131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.858246131
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.4289398859
Short name T2025
Test name
Test status
Simulation time 47626798 ps
CPU time 0.69 seconds
Started Jul 20 06:25:42 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206704 kb
Host smart-002db9fa-f288-4076-a44d-201e32ba9cb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4289398859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.4289398859
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.1670312683
Short name T1266
Test name
Test status
Simulation time 3727846495 ps
CPU time 4.29 seconds
Started Jul 20 06:25:27 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206852 kb
Host smart-59b02b64-51fc-48b6-8394-85c9e83dfcea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1670312683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.1670312683
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.2661480788
Short name T2236
Test name
Test status
Simulation time 13366353478 ps
CPU time 12.63 seconds
Started Jul 20 06:25:34 PM PDT 24
Finished Jul 20 06:25:49 PM PDT 24
Peak memory 206780 kb
Host smart-411a4f7b-4c57-4418-ac53-3db40918f9db
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2661480788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.2661480788
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1376104517
Short name T2158
Test name
Test status
Simulation time 23397552511 ps
CPU time 27.06 seconds
Started Jul 20 06:25:31 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206756 kb
Host smart-ed638ec4-c931-4b15-9eb3-46b02999de08
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1376104517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.1376104517
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3971846681
Short name T2612
Test name
Test status
Simulation time 166936333 ps
CPU time 0.8 seconds
Started Jul 20 06:25:37 PM PDT 24
Finished Jul 20 06:25:40 PM PDT 24
Peak memory 206656 kb
Host smart-e52f8985-bcf8-4d34-99af-111c3486523a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39718
46681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3971846681
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.1427213452
Short name T31
Test name
Test status
Simulation time 145288447 ps
CPU time 0.82 seconds
Started Jul 20 06:25:35 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206648 kb
Host smart-b79aeb71-c4bf-4b30-ab39-1df1dd3d939c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14272
13452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.1427213452
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2882363823
Short name T2113
Test name
Test status
Simulation time 439637200 ps
CPU time 1.39 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206628 kb
Host smart-42a8de03-cefc-42d7-bab2-6e9f43a142a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
63823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2882363823
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.4023042954
Short name T1567
Test name
Test status
Simulation time 1624285489 ps
CPU time 3.58 seconds
Started Jul 20 06:25:37 PM PDT 24
Finished Jul 20 06:25:42 PM PDT 24
Peak memory 206772 kb
Host smart-9a4afcef-c94c-4d25-b661-ab96c37e3fd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40230
42954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.4023042954
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.2956543933
Short name T1190
Test name
Test status
Simulation time 13595330179 ps
CPU time 29.4 seconds
Started Jul 20 06:25:36 PM PDT 24
Finished Jul 20 06:26:07 PM PDT 24
Peak memory 206928 kb
Host smart-cad092ac-5b59-4cb0-8906-1ec9160508e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29565
43933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.2956543933
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.1509999406
Short name T880
Test name
Test status
Simulation time 473694197 ps
CPU time 1.57 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:44 PM PDT 24
Peak memory 206652 kb
Host smart-90b98b40-f78f-48be-86d0-999ee8bb2a3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15099
99406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.1509999406
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3561410460
Short name T2574
Test name
Test status
Simulation time 156775823 ps
CPU time 0.78 seconds
Started Jul 20 06:25:37 PM PDT 24
Finished Jul 20 06:25:39 PM PDT 24
Peak memory 206628 kb
Host smart-f45c92de-c353-490b-aa2a-a5225fa73bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35614
10460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3561410460
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.2676428835
Short name T772
Test name
Test status
Simulation time 34670515 ps
CPU time 0.68 seconds
Started Jul 20 06:25:35 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206644 kb
Host smart-f1d7dc70-1bd1-4123-bd53-034d12dc82bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26764
28835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.2676428835
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.1304545668
Short name T585
Test name
Test status
Simulation time 912096151 ps
CPU time 2.09 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206716 kb
Host smart-a8829703-74fc-47de-8b25-349e7f37d0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13045
45668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.1304545668
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.1852450157
Short name T2527
Test name
Test status
Simulation time 315571119 ps
CPU time 2.22 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:43 PM PDT 24
Peak memory 206144 kb
Host smart-cebbccb2-1a4c-4a41-8cf7-41869747f657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18524
50157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.1852450157
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.386083856
Short name T1529
Test name
Test status
Simulation time 204925961 ps
CPU time 0.89 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206644 kb
Host smart-d020a263-bd85-4106-b12a-d85fb3ecbf4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38608
3856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.386083856
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.2408241159
Short name T1005
Test name
Test status
Simulation time 210648614 ps
CPU time 0.84 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:43 PM PDT 24
Peak memory 206640 kb
Host smart-27ab79e0-9c4b-41e1-94ac-840f0b20b82d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24082
41159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.2408241159
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.2585055856
Short name T666
Test name
Test status
Simulation time 187876594 ps
CPU time 0.83 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206652 kb
Host smart-1f82db17-da75-48d6-8d9e-b7826e9432d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25850
55856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.2585055856
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.103016396
Short name T2699
Test name
Test status
Simulation time 8241367378 ps
CPU time 24.66 seconds
Started Jul 20 06:25:35 PM PDT 24
Finished Jul 20 06:26:02 PM PDT 24
Peak memory 206884 kb
Host smart-7e0097b3-b062-44c3-872a-d92eb16df9e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10301
6396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.103016396
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.2207767022
Short name T2375
Test name
Test status
Simulation time 211211745 ps
CPU time 0.85 seconds
Started Jul 20 06:25:35 PM PDT 24
Finished Jul 20 06:25:38 PM PDT 24
Peak memory 206656 kb
Host smart-a47e3be3-0f57-41b3-8853-83a87a4f5646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22077
67022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.2207767022
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.497977571
Short name T1328
Test name
Test status
Simulation time 23338552634 ps
CPU time 23.73 seconds
Started Jul 20 06:25:37 PM PDT 24
Finished Jul 20 06:26:02 PM PDT 24
Peak memory 206732 kb
Host smart-e81446c3-7277-4fd7-8a8c-e2672e34da70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49797
7571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.497977571
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.3257031462
Short name T271
Test name
Test status
Simulation time 3270115725 ps
CPU time 4.55 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:40 PM PDT 24
Peak memory 206716 kb
Host smart-28fe1259-6c30-40b7-a68d-2f3eeae9b464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32570
31462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.3257031462
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.125629704
Short name T1916
Test name
Test status
Simulation time 6729343156 ps
CPU time 194.15 seconds
Started Jul 20 06:25:32 PM PDT 24
Finished Jul 20 06:28:49 PM PDT 24
Peak memory 206932 kb
Host smart-918c2934-f167-4ea5-93d9-ec3af9e288d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
9704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.125629704
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.2569755066
Short name T2260
Test name
Test status
Simulation time 4363906930 ps
CPU time 113.58 seconds
Started Jul 20 06:25:34 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 206840 kb
Host smart-1d29f6f7-ec14-43f1-b2e0-c7022041eae3
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2569755066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.2569755066
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3584542826
Short name T2663
Test name
Test status
Simulation time 258135771 ps
CPU time 0.97 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:43 PM PDT 24
Peak memory 206652 kb
Host smart-500a9c30-3e97-426c-8651-7c64e42d3311
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3584542826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3584542826
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.1340917355
Short name T1896
Test name
Test status
Simulation time 188846869 ps
CPU time 0.85 seconds
Started Jul 20 06:25:33 PM PDT 24
Finished Jul 20 06:25:36 PM PDT 24
Peak memory 206660 kb
Host smart-d344fe19-42f5-452a-9e33-6ee56d3b20c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13409
17355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.1340917355
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.4269799871
Short name T581
Test name
Test status
Simulation time 6657489826 ps
CPU time 184.96 seconds
Started Jul 20 06:25:38 PM PDT 24
Finished Jul 20 06:28:44 PM PDT 24
Peak memory 206860 kb
Host smart-09aaae72-7373-42a9-9368-2543ee80715d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42697
99871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.4269799871
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.705886861
Short name T2470
Test name
Test status
Simulation time 5342539253 ps
CPU time 40.93 seconds
Started Jul 20 06:25:35 PM PDT 24
Finished Jul 20 06:26:18 PM PDT 24
Peak memory 206852 kb
Host smart-9fffeecb-a1a4-4651-b636-0f9d309acf22
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=705886861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.705886861
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.769513565
Short name T722
Test name
Test status
Simulation time 217353711 ps
CPU time 0.95 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:42 PM PDT 24
Peak memory 206016 kb
Host smart-4788bbbf-d6bc-43a2-90f8-21bf8c279b7f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=769513565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.769513565
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.2542964741
Short name T2509
Test name
Test status
Simulation time 208803089 ps
CPU time 0.83 seconds
Started Jul 20 06:25:34 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206652 kb
Host smart-a5999dc2-a889-404e-861c-708cfcb95e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25429
64741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.2542964741
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.2872860873
Short name T141
Test name
Test status
Simulation time 211867428 ps
CPU time 0.87 seconds
Started Jul 20 06:25:37 PM PDT 24
Finished Jul 20 06:25:40 PM PDT 24
Peak memory 206652 kb
Host smart-f6b5ad4e-9c1c-4327-9fea-2e0ebf6a0419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28728
60873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.2872860873
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.1215927673
Short name T971
Test name
Test status
Simulation time 225637041 ps
CPU time 0.96 seconds
Started Jul 20 06:25:38 PM PDT 24
Finished Jul 20 06:25:40 PM PDT 24
Peak memory 206652 kb
Host smart-d22158a8-8562-4f7d-9b5b-ed0ac3c934c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12159
27673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.1215927673
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.2111466986
Short name T405
Test name
Test status
Simulation time 199172096 ps
CPU time 0.85 seconds
Started Jul 20 06:25:36 PM PDT 24
Finished Jul 20 06:25:39 PM PDT 24
Peak memory 206632 kb
Host smart-ec779d15-0013-49e1-9676-f240c513b272
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21114
66986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.2111466986
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.2692163239
Short name T2120
Test name
Test status
Simulation time 159318378 ps
CPU time 0.77 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:42 PM PDT 24
Peak memory 206652 kb
Host smart-e713281e-efae-48de-a105-029f97c765b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26921
63239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.2692163239
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.657378253
Short name T425
Test name
Test status
Simulation time 159775222 ps
CPU time 0.81 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:42 PM PDT 24
Peak memory 206648 kb
Host smart-f34a99de-7239-4cec-a003-a7f614ac1d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65737
8253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.657378253
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.3004532282
Short name T2592
Test name
Test status
Simulation time 266201774 ps
CPU time 1.04 seconds
Started Jul 20 06:25:34 PM PDT 24
Finished Jul 20 06:25:37 PM PDT 24
Peak memory 206640 kb
Host smart-6c7640e7-0ce5-4853-9247-f475d3f859b1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3004532282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.3004532282
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.4026208489
Short name T203
Test name
Test status
Simulation time 146632019 ps
CPU time 0.78 seconds
Started Jul 20 06:25:39 PM PDT 24
Finished Jul 20 06:25:41 PM PDT 24
Peak memory 206632 kb
Host smart-bd7d0dac-9dcf-49e9-89d0-eb6f16dcb946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40262
08489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.4026208489
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1088142164
Short name T1635
Test name
Test status
Simulation time 41577424 ps
CPU time 0.7 seconds
Started Jul 20 06:25:45 PM PDT 24
Finished Jul 20 06:25:48 PM PDT 24
Peak memory 205812 kb
Host smart-fab947d7-83f9-4926-8bbb-173062c5b495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10881
42164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1088142164
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.885613256
Short name T249
Test name
Test status
Simulation time 11442515868 ps
CPU time 25.22 seconds
Started Jul 20 06:25:45 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206872 kb
Host smart-e3628c98-3fb1-46e1-9685-5a987a1839ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88561
3256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.885613256
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.2551999327
Short name T457
Test name
Test status
Simulation time 163051045 ps
CPU time 0.87 seconds
Started Jul 20 06:25:45 PM PDT 24
Finished Jul 20 06:25:48 PM PDT 24
Peak memory 205860 kb
Host smart-9731fdf9-0dae-401d-a6bb-aabb8d908658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25519
99327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.2551999327
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.2279242999
Short name T1233
Test name
Test status
Simulation time 285913172 ps
CPU time 0.94 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:25:44 PM PDT 24
Peak memory 206676 kb
Host smart-9a3355d1-5893-486a-8632-42bc52c75207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22792
42999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.2279242999
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.2091261132
Short name T1583
Test name
Test status
Simulation time 215399522 ps
CPU time 0.88 seconds
Started Jul 20 06:25:46 PM PDT 24
Finished Jul 20 06:25:49 PM PDT 24
Peak memory 206656 kb
Host smart-3effd7fd-8feb-4f08-8e1b-c327f2b72927
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20912
61132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.2091261132
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1933831277
Short name T3
Test name
Test status
Simulation time 182214272 ps
CPU time 0.82 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206548 kb
Host smart-c8a424b1-153e-4490-8559-012468c01e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19338
31277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1933831277
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.809963321
Short name T1606
Test name
Test status
Simulation time 155726554 ps
CPU time 0.76 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:25:51 PM PDT 24
Peak memory 206652 kb
Host smart-efbd9643-4fb3-4007-99b7-8dab304ac072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80996
3321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.809963321
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.2220400470
Short name T1687
Test name
Test status
Simulation time 214079038 ps
CPU time 0.85 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206652 kb
Host smart-47cb878c-968b-4deb-8536-7f8e33c992b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22204
00470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.2220400470
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2707771778
Short name T874
Test name
Test status
Simulation time 147756662 ps
CPU time 0.8 seconds
Started Jul 20 06:25:44 PM PDT 24
Finished Jul 20 06:25:48 PM PDT 24
Peak memory 206656 kb
Host smart-108a13c9-6ea1-4e19-a05e-adb405e2ad8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27077
71778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2707771778
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.3151451655
Short name T474
Test name
Test status
Simulation time 258845496 ps
CPU time 0.97 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206648 kb
Host smart-63c2acbb-9793-4b8d-bc96-37694b192992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31514
51655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.3151451655
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.4163498050
Short name T1110
Test name
Test status
Simulation time 3947682448 ps
CPU time 36.61 seconds
Started Jul 20 06:25:44 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206864 kb
Host smart-373417d3-8abb-4231-8d7b-3d9e79e08923
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4163498050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.4163498050
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.294471813
Short name T839
Test name
Test status
Simulation time 203204999 ps
CPU time 0.87 seconds
Started Jul 20 06:25:46 PM PDT 24
Finished Jul 20 06:25:49 PM PDT 24
Peak memory 206648 kb
Host smart-bc11f1ea-60c6-49c6-a64c-535912b993b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
1813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.294471813
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.189203405
Short name T1864
Test name
Test status
Simulation time 172121320 ps
CPU time 0.82 seconds
Started Jul 20 06:25:42 PM PDT 24
Finished Jul 20 06:25:45 PM PDT 24
Peak memory 206624 kb
Host smart-7130c7f3-c5d1-46af-ad41-de604ea014fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18920
3405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.189203405
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.2799163046
Short name T1994
Test name
Test status
Simulation time 1117785158 ps
CPU time 2.18 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:25:45 PM PDT 24
Peak memory 206776 kb
Host smart-57de02b2-ff66-4dbe-9f2e-8fd97e560a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27991
63046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.2799163046
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.349288652
Short name T1488
Test name
Test status
Simulation time 7086078650 ps
CPU time 68.25 seconds
Started Jul 20 06:25:44 PM PDT 24
Finished Jul 20 06:26:55 PM PDT 24
Peak memory 206912 kb
Host smart-c4095888-503a-495c-a278-fb48ad578593
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34928
8652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.349288652
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.2645487409
Short name T1159
Test name
Test status
Simulation time 69196796 ps
CPU time 0.69 seconds
Started Jul 20 06:25:49 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206704 kb
Host smart-438b6f72-3d15-4337-96db-829bdfcb8213
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2645487409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.2645487409
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.1933933911
Short name T1577
Test name
Test status
Simulation time 3658969300 ps
CPU time 4.68 seconds
Started Jul 20 06:25:44 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206836 kb
Host smart-6e3e2f4e-1fde-4447-a47c-80d941f7913d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1933933911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.1933933911
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.148605097
Short name T2354
Test name
Test status
Simulation time 13370081848 ps
CPU time 12.69 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:58 PM PDT 24
Peak memory 206848 kb
Host smart-a98c56eb-1842-4728-a3c7-e61f56df6545
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=148605097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.148605097
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1508165481
Short name T2449
Test name
Test status
Simulation time 23438116527 ps
CPU time 27.55 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206732 kb
Host smart-49ff2c79-b173-4bc4-a859-2250670041db
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1508165481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1508165481
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.628468296
Short name T1954
Test name
Test status
Simulation time 191254330 ps
CPU time 0.96 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:25:45 PM PDT 24
Peak memory 206656 kb
Host smart-0413af7f-e734-4027-a28a-86e2f95f3974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62846
8296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.628468296
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.753902345
Short name T2297
Test name
Test status
Simulation time 180725669 ps
CPU time 0.9 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206656 kb
Host smart-44a58662-6281-48c2-8bad-3578dbac24db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75390
2345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.753902345
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.4074408407
Short name T2117
Test name
Test status
Simulation time 509867404 ps
CPU time 1.48 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206692 kb
Host smart-7dba39a3-db74-4da6-88f7-a3d1593618d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40744
08407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.4074408407
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.3338642277
Short name T105
Test name
Test status
Simulation time 1418363018 ps
CPU time 2.99 seconds
Started Jul 20 06:25:42 PM PDT 24
Finished Jul 20 06:25:48 PM PDT 24
Peak memory 206752 kb
Host smart-a195cd17-7ac6-4931-b11f-17e0aed36a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33386
42277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.3338642277
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.1431616118
Short name T1405
Test name
Test status
Simulation time 10230284619 ps
CPU time 22.03 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206908 kb
Host smart-51de929a-d975-449d-97fe-9c18adad9e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14316
16118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.1431616118
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.4243079174
Short name T1678
Test name
Test status
Simulation time 474042096 ps
CPU time 1.33 seconds
Started Jul 20 06:25:44 PM PDT 24
Finished Jul 20 06:25:48 PM PDT 24
Peak memory 206628 kb
Host smart-ed4cb806-d6f0-4f36-888c-eb4de671ba22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42430
79174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.4243079174
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.63373682
Short name T1881
Test name
Test status
Simulation time 142155907 ps
CPU time 0.74 seconds
Started Jul 20 06:25:45 PM PDT 24
Finished Jul 20 06:25:49 PM PDT 24
Peak memory 206644 kb
Host smart-a8eb8fdf-b20d-441b-8f97-71fcbe7d814d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63373
682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.63373682
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.2395079880
Short name T1486
Test name
Test status
Simulation time 91798699 ps
CPU time 0.72 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:25:51 PM PDT 24
Peak memory 206648 kb
Host smart-22a813ed-8684-4af8-9424-a92d402d3e49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23950
79880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.2395079880
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.3999228099
Short name T1398
Test name
Test status
Simulation time 899081236 ps
CPU time 2.13 seconds
Started Jul 20 06:25:45 PM PDT 24
Finished Jul 20 06:25:49 PM PDT 24
Peak memory 206736 kb
Host smart-41ba48d1-b538-4fbf-bd75-3d5368d4b8a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39992
28099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.3999228099
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.2018305199
Short name T470
Test name
Test status
Simulation time 238646436 ps
CPU time 1.66 seconds
Started Jul 20 06:25:42 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206840 kb
Host smart-45e82e8c-ab36-434d-8043-67410a6ee13a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20183
05199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.2018305199
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.1229250638
Short name T2339
Test name
Test status
Simulation time 272222335 ps
CPU time 0.96 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206644 kb
Host smart-4ad3b726-5f44-4ce2-8cc2-f89738473f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12292
50638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.1229250638
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.3325351443
Short name T1962
Test name
Test status
Simulation time 150637540 ps
CPU time 0.79 seconds
Started Jul 20 06:25:47 PM PDT 24
Finished Jul 20 06:25:51 PM PDT 24
Peak memory 206664 kb
Host smart-b778da17-7ca9-4c6d-aaad-9605b84153a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33253
51443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.3325351443
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2611810243
Short name T1691
Test name
Test status
Simulation time 188732325 ps
CPU time 0.85 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:43 PM PDT 24
Peak memory 206660 kb
Host smart-5ddc1dec-b6bf-4553-afba-eef5f984cbc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
10243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2611810243
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3652720361
Short name T2183
Test name
Test status
Simulation time 165132252 ps
CPU time 0.82 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:43 PM PDT 24
Peak memory 206656 kb
Host smart-ee60fcc3-b6df-4c1a-980e-3f7ef7c0b7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
20361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3652720361
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.2914307390
Short name T1258
Test name
Test status
Simulation time 23322208562 ps
CPU time 26.45 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:26:10 PM PDT 24
Peak memory 206768 kb
Host smart-1c360cd3-3088-4d7b-89d6-154e11619b89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29143
07390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.2914307390
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.1970380684
Short name T1830
Test name
Test status
Simulation time 3306996524 ps
CPU time 3.52 seconds
Started Jul 20 06:25:47 PM PDT 24
Finished Jul 20 06:25:53 PM PDT 24
Peak memory 206732 kb
Host smart-363481c8-e081-45d6-bb3c-d3fbe9b6b90d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19703
80684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.1970380684
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.3719091003
Short name T2299
Test name
Test status
Simulation time 12286299448 ps
CPU time 350.41 seconds
Started Jul 20 06:25:47 PM PDT 24
Finished Jul 20 06:31:40 PM PDT 24
Peak memory 206892 kb
Host smart-46738205-1a09-4d0c-9a3b-f5987e994eba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37190
91003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.3719091003
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.128224475
Short name T2702
Test name
Test status
Simulation time 7280304945 ps
CPU time 71.02 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:26:54 PM PDT 24
Peak memory 206844 kb
Host smart-1c0f290d-1bd2-4489-ba81-80790dfb30f2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=128224475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.128224475
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1662069005
Short name T807
Test name
Test status
Simulation time 240312462 ps
CPU time 0.88 seconds
Started Jul 20 06:25:42 PM PDT 24
Finished Jul 20 06:25:45 PM PDT 24
Peak memory 206644 kb
Host smart-669ef214-1429-4bbb-ab59-b2d446579ae1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1662069005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1662069005
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2075863512
Short name T785
Test name
Test status
Simulation time 186397500 ps
CPU time 0.85 seconds
Started Jul 20 06:25:40 PM PDT 24
Finished Jul 20 06:25:42 PM PDT 24
Peak memory 206656 kb
Host smart-8ac325ab-1d1e-4643-93c9-34b4d6893040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20758
63512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2075863512
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.4217903190
Short name T1816
Test name
Test status
Simulation time 4032653405 ps
CPU time 106.88 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 206804 kb
Host smart-b67cbe4d-0e52-4f8d-bbfd-a2ced3b10535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42179
03190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.4217903190
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2930668971
Short name T2581
Test name
Test status
Simulation time 5662124656 ps
CPU time 40.01 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:26:23 PM PDT 24
Peak memory 206896 kb
Host smart-68fee1cc-a6c1-43f7-a78c-43f4a86c2029
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2930668971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2930668971
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1018502612
Short name T1523
Test name
Test status
Simulation time 166865219 ps
CPU time 0.93 seconds
Started Jul 20 06:25:46 PM PDT 24
Finished Jul 20 06:25:49 PM PDT 24
Peak memory 206656 kb
Host smart-fe2c18cb-f0b4-4251-96a9-e60ffa8606d1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1018502612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1018502612
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3148234886
Short name T556
Test name
Test status
Simulation time 149250588 ps
CPU time 0.79 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:25:44 PM PDT 24
Peak memory 206656 kb
Host smart-bf1a974f-d013-4deb-bdae-8e98a9bcfaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31482
34886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3148234886
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.1501606332
Short name T130
Test name
Test status
Simulation time 159232550 ps
CPU time 0.79 seconds
Started Jul 20 06:25:44 PM PDT 24
Finished Jul 20 06:25:47 PM PDT 24
Peak memory 206660 kb
Host smart-9ec038ec-aab0-43cd-93da-fd9230515974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15016
06332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.1501606332
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3347435263
Short name T1887
Test name
Test status
Simulation time 186999255 ps
CPU time 0.82 seconds
Started Jul 20 06:25:45 PM PDT 24
Finished Jul 20 06:25:49 PM PDT 24
Peak memory 206652 kb
Host smart-12e819bb-df12-4f2f-bb8c-8916f7ab7df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33474
35263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3347435263
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.2899828645
Short name T1008
Test name
Test status
Simulation time 172048651 ps
CPU time 0.8 seconds
Started Jul 20 06:25:47 PM PDT 24
Finished Jul 20 06:25:50 PM PDT 24
Peak memory 206636 kb
Host smart-68947b60-f220-4a94-94e2-7b9859eb5d66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28998
28645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.2899828645
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.37902736
Short name T618
Test name
Test status
Simulation time 154945025 ps
CPU time 0.8 seconds
Started Jul 20 06:25:46 PM PDT 24
Finished Jul 20 06:25:50 PM PDT 24
Peak memory 206640 kb
Host smart-2c423e2e-6f7e-464e-88a6-40ac64231e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37902
736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.37902736
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.1768087407
Short name T1809
Test name
Test status
Simulation time 160610159 ps
CPU time 0.79 seconds
Started Jul 20 06:25:41 PM PDT 24
Finished Jul 20 06:25:44 PM PDT 24
Peak memory 206652 kb
Host smart-148d4b6c-e856-4fdd-ad7b-1e16bc6e1f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17680
87407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.1768087407
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.2129271953
Short name T1089
Test name
Test status
Simulation time 224650987 ps
CPU time 0.88 seconds
Started Jul 20 06:25:44 PM PDT 24
Finished Jul 20 06:25:48 PM PDT 24
Peak memory 206636 kb
Host smart-5858b33f-66e5-44c3-b337-ce3bb0f3ab38
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2129271953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.2129271953
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1903059615
Short name T1242
Test name
Test status
Simulation time 169416013 ps
CPU time 0.85 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206648 kb
Host smart-dcfd6648-7c46-4ecd-be9b-80754da734d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19030
59615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1903059615
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2808550459
Short name T1319
Test name
Test status
Simulation time 56431189 ps
CPU time 0.7 seconds
Started Jul 20 06:25:43 PM PDT 24
Finished Jul 20 06:25:46 PM PDT 24
Peak memory 206632 kb
Host smart-06d6e90b-e1f8-4f3e-b189-42b46bbc935b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28085
50459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2808550459
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.941210210
Short name T247
Test name
Test status
Simulation time 8023648858 ps
CPU time 18.9 seconds
Started Jul 20 06:25:46 PM PDT 24
Finished Jul 20 06:26:08 PM PDT 24
Peak memory 206848 kb
Host smart-7838425c-b9f4-4484-be99-d8399472d32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94121
0210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.941210210
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3703318031
Short name T1858
Test name
Test status
Simulation time 194831667 ps
CPU time 0.88 seconds
Started Jul 20 06:25:46 PM PDT 24
Finished Jul 20 06:25:50 PM PDT 24
Peak memory 206624 kb
Host smart-664eb690-4e16-484b-9475-309de673f55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37033
18031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3703318031
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.949905247
Short name T1126
Test name
Test status
Simulation time 179975510 ps
CPU time 0.84 seconds
Started Jul 20 06:25:49 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206656 kb
Host smart-c6fa4586-3d37-44a1-a8fa-ebc6605048ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94990
5247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.949905247
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3815105115
Short name T1290
Test name
Test status
Simulation time 191928090 ps
CPU time 0.85 seconds
Started Jul 20 06:25:52 PM PDT 24
Finished Jul 20 06:25:54 PM PDT 24
Peak memory 206696 kb
Host smart-9b1f7f26-e76d-4575-87b9-32f5d79aadb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38151
05115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3815105115
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3888270001
Short name T760
Test name
Test status
Simulation time 173606091 ps
CPU time 0.83 seconds
Started Jul 20 06:25:49 PM PDT 24
Finished Jul 20 06:25:51 PM PDT 24
Peak memory 206632 kb
Host smart-084ad930-8498-48a3-b701-df85cea699ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38882
70001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3888270001
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3445588206
Short name T1578
Test name
Test status
Simulation time 167516632 ps
CPU time 0.81 seconds
Started Jul 20 06:25:49 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206632 kb
Host smart-2b5b301d-42bb-4680-a30e-86036b64aa32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34455
88206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3445588206
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.601317417
Short name T421
Test name
Test status
Simulation time 173552962 ps
CPU time 0.88 seconds
Started Jul 20 06:25:53 PM PDT 24
Finished Jul 20 06:25:55 PM PDT 24
Peak memory 206652 kb
Host smart-ab7feac6-053f-48c0-b71d-34f62ef4d1f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60131
7417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.601317417
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.2700109231
Short name T2405
Test name
Test status
Simulation time 217627602 ps
CPU time 0.9 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:25:51 PM PDT 24
Peak memory 206636 kb
Host smart-f0cb517d-0cbc-469b-a2ba-b7ee24f7c10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27001
09231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.2700109231
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3420994963
Short name T2346
Test name
Test status
Simulation time 236255690 ps
CPU time 0.97 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:25:51 PM PDT 24
Peak memory 206640 kb
Host smart-c2f4f5ad-abc8-4d2c-9a79-74a692864663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34209
94963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3420994963
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.546257015
Short name T2270
Test name
Test status
Simulation time 4917756722 ps
CPU time 130.99 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 206860 kb
Host smart-4c715148-c3a5-4321-a23b-0d65dea00306
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=546257015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.546257015
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.3928316575
Short name T2234
Test name
Test status
Simulation time 159629957 ps
CPU time 0.76 seconds
Started Jul 20 06:25:50 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206632 kb
Host smart-37e7f101-9a56-4248-8ea0-041ecec94522
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39283
16575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.3928316575
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.234346105
Short name T952
Test name
Test status
Simulation time 159076864 ps
CPU time 0.78 seconds
Started Jul 20 06:25:50 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206640 kb
Host smart-6befc90e-c402-4533-961f-3d3ed5aec439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23434
6105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.234346105
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2730896265
Short name T2599
Test name
Test status
Simulation time 672867761 ps
CPU time 1.65 seconds
Started Jul 20 06:25:52 PM PDT 24
Finished Jul 20 06:25:55 PM PDT 24
Peak memory 206800 kb
Host smart-66651ae2-b63b-48f4-80fd-8d89883841c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27308
96265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2730896265
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.4057136841
Short name T2037
Test name
Test status
Simulation time 5845761674 ps
CPU time 39.85 seconds
Started Jul 20 06:25:54 PM PDT 24
Finished Jul 20 06:26:34 PM PDT 24
Peak memory 206804 kb
Host smart-5d165194-bb05-4b33-8092-1549619b0433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40571
36841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.4057136841
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1490115196
Short name T1749
Test name
Test status
Simulation time 43876803 ps
CPU time 0.69 seconds
Started Jul 20 06:26:01 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206696 kb
Host smart-ea168e5c-5362-426b-b7d9-57ae37ea5a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1490115196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1490115196
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1603828106
Short name T2434
Test name
Test status
Simulation time 4310192708 ps
CPU time 5.95 seconds
Started Jul 20 06:25:55 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206780 kb
Host smart-10ebbe88-ad38-4e16-8dc0-43ac0c6cb143
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1603828106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1603828106
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.988536455
Short name T1164
Test name
Test status
Simulation time 13374492082 ps
CPU time 13.02 seconds
Started Jul 20 06:25:52 PM PDT 24
Finished Jul 20 06:26:06 PM PDT 24
Peak memory 206876 kb
Host smart-c9bf51c0-9d45-4f75-a273-0d51a9447b92
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=988536455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.988536455
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.3725890639
Short name T527
Test name
Test status
Simulation time 23399367515 ps
CPU time 22.88 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206920 kb
Host smart-03b2613c-fae4-495b-b759-40856da0d92c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3725890639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.3725890639
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1908957271
Short name T1009
Test name
Test status
Simulation time 203842299 ps
CPU time 0.93 seconds
Started Jul 20 06:25:48 PM PDT 24
Finished Jul 20 06:25:52 PM PDT 24
Peak memory 206668 kb
Host smart-20b0acaa-3d99-4155-9cd1-5c66775383af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19089
57271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1908957271
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.1975081293
Short name T1517
Test name
Test status
Simulation time 150755124 ps
CPU time 0.79 seconds
Started Jul 20 06:25:55 PM PDT 24
Finished Jul 20 06:25:56 PM PDT 24
Peak memory 206632 kb
Host smart-70bc9da7-c1f6-4076-bb21-816044638459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750
81293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.1975081293
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.4063056353
Short name T2611
Test name
Test status
Simulation time 448085338 ps
CPU time 1.47 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:26:00 PM PDT 24
Peak memory 206636 kb
Host smart-514a4386-9114-4fbb-b402-c7a98d477457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40630
56353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.4063056353
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.1474656968
Short name T1967
Test name
Test status
Simulation time 543917942 ps
CPU time 1.54 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206624 kb
Host smart-0597465f-9b6f-432d-af18-ada43c48ef41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14746
56968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.1474656968
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.1244270311
Short name T568
Test name
Test status
Simulation time 7363473142 ps
CPU time 13 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206908 kb
Host smart-5dc3a97d-4920-4e76-8f00-f88558d33fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12442
70311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.1244270311
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.3481723869
Short name T570
Test name
Test status
Simulation time 465145255 ps
CPU time 1.4 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206648 kb
Host smart-ea1283e8-6995-465d-a9b5-48bd2d5e2421
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34817
23869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.3481723869
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.2407730044
Short name T46
Test name
Test status
Simulation time 181918374 ps
CPU time 0.81 seconds
Started Jul 20 06:26:01 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206668 kb
Host smart-3fe5bf1a-40e8-40ce-b645-5cc7dd05e4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24077
30044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.2407730044
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.3569387175
Short name T866
Test name
Test status
Simulation time 43970336 ps
CPU time 0.66 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:25:58 PM PDT 24
Peak memory 206644 kb
Host smart-df1b08ec-ddf4-4437-8a3a-2295cc7e32d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35693
87175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.3569387175
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.127261724
Short name T1154
Test name
Test status
Simulation time 838782707 ps
CPU time 2.33 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206752 kb
Host smart-67f993b1-b91a-49ad-86f4-fa730d11dfda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12726
1724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.127261724
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3211475514
Short name T1357
Test name
Test status
Simulation time 294608250 ps
CPU time 1.63 seconds
Started Jul 20 06:26:04 PM PDT 24
Finished Jul 20 06:26:08 PM PDT 24
Peak memory 206736 kb
Host smart-55429f59-b802-41de-94e2-f5bb50cbfbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32114
75514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3211475514
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.4022924155
Short name T2468
Test name
Test status
Simulation time 208669314 ps
CPU time 0.83 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:25:58 PM PDT 24
Peak memory 206644 kb
Host smart-414f905a-01b6-4232-b656-02c19c9efb84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40229
24155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.4022924155
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.3179078214
Short name T2511
Test name
Test status
Simulation time 142656296 ps
CPU time 0.84 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:25:58 PM PDT 24
Peak memory 206672 kb
Host smart-0020782a-68b4-4894-b0d5-56110afada52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31790
78214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.3179078214
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2778844075
Short name T1794
Test name
Test status
Simulation time 215412805 ps
CPU time 0.96 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:26:11 PM PDT 24
Peak memory 206652 kb
Host smart-322c203b-fb3c-4f34-8a36-57f711917fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27788
44075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2778844075
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.1609034239
Short name T2257
Test name
Test status
Simulation time 5385974734 ps
CPU time 16.77 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:16 PM PDT 24
Peak memory 206912 kb
Host smart-b5002d42-ad1e-49fc-8575-88b6986843ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16090
34239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.1609034239
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.273465837
Short name T1218
Test name
Test status
Simulation time 169488484 ps
CPU time 0.81 seconds
Started Jul 20 06:26:03 PM PDT 24
Finished Jul 20 06:26:06 PM PDT 24
Peak memory 206644 kb
Host smart-0fa17c65-99ad-4483-a949-ad044a7ff166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27346
5837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.273465837
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.171427893
Short name T508
Test name
Test status
Simulation time 23285764186 ps
CPU time 23.06 seconds
Started Jul 20 06:25:53 PM PDT 24
Finished Jul 20 06:26:17 PM PDT 24
Peak memory 206764 kb
Host smart-84beff01-8bf7-4904-8bd6-0b52057dbd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17142
7893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.171427893
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.1470405890
Short name T2215
Test name
Test status
Simulation time 3339863289 ps
CPU time 3.76 seconds
Started Jul 20 06:26:03 PM PDT 24
Finished Jul 20 06:26:09 PM PDT 24
Peak memory 206712 kb
Host smart-f9aaceef-a287-4d62-b94a-552de59e5754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14704
05890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.1470405890
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.1972519553
Short name T1604
Test name
Test status
Simulation time 7411591765 ps
CPU time 67.34 seconds
Started Jul 20 06:25:56 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206900 kb
Host smart-8e303861-bdab-41dd-bb42-c7d2297c90e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19725
19553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.1972519553
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.2813182492
Short name T2305
Test name
Test status
Simulation time 5219186216 ps
CPU time 142.19 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:28:25 PM PDT 24
Peak memory 206836 kb
Host smart-211531ab-3e23-42d7-bcf2-5ee663c7febd
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2813182492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.2813182492
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.370994196
Short name T398
Test name
Test status
Simulation time 290561523 ps
CPU time 1.01 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:25:59 PM PDT 24
Peak memory 206644 kb
Host smart-0581c4da-9b4c-432d-ab0e-36681ab66016
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=370994196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.370994196
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3741882412
Short name T729
Test name
Test status
Simulation time 254505014 ps
CPU time 0.98 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206656 kb
Host smart-92c0564d-4e46-4908-81ac-a48ccc19a033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37418
82412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3741882412
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3856678904
Short name T712
Test name
Test status
Simulation time 3263453546 ps
CPU time 90.72 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:27:32 PM PDT 24
Peak memory 206840 kb
Host smart-8c5e3afe-47d8-4f74-89f4-07b0da3f2b86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38566
78904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3856678904
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3249616764
Short name T829
Test name
Test status
Simulation time 4074747866 ps
CPU time 28.82 seconds
Started Jul 20 06:26:04 PM PDT 24
Finished Jul 20 06:26:35 PM PDT 24
Peak memory 206908 kb
Host smart-c47b83f6-63a1-4ce2-ba69-602eec439150
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3249616764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3249616764
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2962059923
Short name T1679
Test name
Test status
Simulation time 168250327 ps
CPU time 0.83 seconds
Started Jul 20 06:26:04 PM PDT 24
Finished Jul 20 06:26:07 PM PDT 24
Peak memory 206652 kb
Host smart-bb585464-3a1b-4b3c-bec9-97d67d429a98
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2962059923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2962059923
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.1641785273
Short name T1783
Test name
Test status
Simulation time 143145806 ps
CPU time 0.77 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:03 PM PDT 24
Peak memory 206656 kb
Host smart-47b88b6f-8c82-4d97-83e6-79de80746c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16417
85273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.1641785273
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.286936402
Short name T123
Test name
Test status
Simulation time 186354667 ps
CPU time 0.83 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:02 PM PDT 24
Peak memory 206624 kb
Host smart-700cadd0-815f-420d-b7ad-eab2b19e9483
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28693
6402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.286936402
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.729750216
Short name T1341
Test name
Test status
Simulation time 178948161 ps
CPU time 0.87 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206644 kb
Host smart-8229014b-2bcc-4e79-96dd-8174a2dd15f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72975
0216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.729750216
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.2827591060
Short name T1295
Test name
Test status
Simulation time 211611015 ps
CPU time 0.87 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206652 kb
Host smart-78a74c3e-0441-4e52-b2ca-c449047b74f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28275
91060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.2827591060
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.1052532076
Short name T2191
Test name
Test status
Simulation time 214180380 ps
CPU time 0.89 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206656 kb
Host smart-2bbcd082-8d10-4c6a-aa22-7435ece6abd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10525
32076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.1052532076
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.3639843073
Short name T2424
Test name
Test status
Simulation time 152750261 ps
CPU time 0.8 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:25:59 PM PDT 24
Peak memory 206644 kb
Host smart-41717bfd-6fc3-49d3-a933-78db026cdb9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36398
43073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.3639843073
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.2840872101
Short name T1416
Test name
Test status
Simulation time 221553059 ps
CPU time 1.01 seconds
Started Jul 20 06:26:01 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206644 kb
Host smart-ef449eee-5030-435a-baa3-89e8da790c59
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2840872101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.2840872101
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1849565447
Short name T2409
Test name
Test status
Simulation time 151736820 ps
CPU time 0.76 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206644 kb
Host smart-85ccf19d-9115-4b1a-a264-c76c1c7fb6f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18495
65447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1849565447
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.3112377250
Short name T962
Test name
Test status
Simulation time 45843043 ps
CPU time 0.68 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:09 PM PDT 24
Peak memory 206648 kb
Host smart-a562b22d-6e8a-475c-aece-90a5baa3a8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31123
77250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.3112377250
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.1694941126
Short name T471
Test name
Test status
Simulation time 10629012043 ps
CPU time 24.32 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206928 kb
Host smart-6efa752f-f34a-4540-9ded-2d15115125cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16949
41126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.1694941126
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.2596777141
Short name T732
Test name
Test status
Simulation time 181264135 ps
CPU time 0.81 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206696 kb
Host smart-09baae9c-f45e-4e79-9174-c1a11fd5a452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25967
77141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.2596777141
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.1615190928
Short name T1636
Test name
Test status
Simulation time 208587478 ps
CPU time 0.85 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206652 kb
Host smart-27ce83aa-92b1-4b86-90c2-813cd7577773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16151
90928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.1615190928
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.633062798
Short name T2563
Test name
Test status
Simulation time 207703473 ps
CPU time 0.87 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:02 PM PDT 24
Peak memory 206656 kb
Host smart-caae31a7-1709-459a-a9b2-b0217e0a5987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63306
2798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.633062798
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2887333002
Short name T742
Test name
Test status
Simulation time 189680493 ps
CPU time 0.91 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:03 PM PDT 24
Peak memory 206632 kb
Host smart-e7846b7c-1a46-4ab1-afb2-14660e401170
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28873
33002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2887333002
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4174934000
Short name T1727
Test name
Test status
Simulation time 156173690 ps
CPU time 0.78 seconds
Started Jul 20 06:26:01 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206640 kb
Host smart-0c69c5d3-f592-4634-855e-8fbb81d870c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41749
34000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4174934000
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1177600161
Short name T205
Test name
Test status
Simulation time 145950577 ps
CPU time 0.78 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:00 PM PDT 24
Peak memory 206636 kb
Host smart-22a8b905-8d95-4cd6-9541-a6e289d220ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11776
00161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1177600161
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1295316406
Short name T1404
Test name
Test status
Simulation time 177257844 ps
CPU time 0.86 seconds
Started Jul 20 06:25:56 PM PDT 24
Finished Jul 20 06:25:57 PM PDT 24
Peak memory 206648 kb
Host smart-93243c3b-14c9-464a-b2e2-d69fed01d6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12953
16406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1295316406
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.2780506199
Short name T400
Test name
Test status
Simulation time 226199183 ps
CPU time 1.03 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206644 kb
Host smart-a9a8f064-7f78-4275-96b7-342a5a29dc36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27805
06199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.2780506199
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.240825362
Short name T2281
Test name
Test status
Simulation time 5413646422 ps
CPU time 54.35 seconds
Started Jul 20 06:26:04 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206924 kb
Host smart-9898bf3b-a5f3-4aa7-9705-829fb3ab6be6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=240825362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.240825362
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.527488364
Short name T1283
Test name
Test status
Simulation time 175956993 ps
CPU time 0.84 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:00 PM PDT 24
Peak memory 206660 kb
Host smart-ff4c7b09-95fb-4501-ad8d-8b6b5ce30b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52748
8364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.527488364
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1850564401
Short name T1478
Test name
Test status
Simulation time 174638088 ps
CPU time 0.83 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206652 kb
Host smart-6130f94e-5c17-4e42-a9c8-3dde3bc2e1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18505
64401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1850564401
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.1395513099
Short name T1877
Test name
Test status
Simulation time 364215119 ps
CPU time 1.14 seconds
Started Jul 20 06:26:01 PM PDT 24
Finished Jul 20 06:26:05 PM PDT 24
Peak memory 206628 kb
Host smart-4c23b5cf-e26f-4e0f-8829-be391813989f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13955
13099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.1395513099
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.394782745
Short name T384
Test name
Test status
Simulation time 4954355705 ps
CPU time 48.71 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:50 PM PDT 24
Peak memory 206920 kb
Host smart-3e00d2a4-35b5-464c-b71b-2b8a13e8e5ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39478
2745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.394782745
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2771474922
Short name T1703
Test name
Test status
Simulation time 52048545 ps
CPU time 0.73 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:05 PM PDT 24
Peak memory 206672 kb
Host smart-67b8529f-c66c-4839-a4f1-ef901ce940b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2771474922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2771474922
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.383668694
Short name T2368
Test name
Test status
Simulation time 4179077328 ps
CPU time 5.71 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:40 PM PDT 24
Peak memory 206836 kb
Host smart-60e8396b-c9cf-46fd-921c-a434e2dd8777
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=383668694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.383668694
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1493079436
Short name T861
Test name
Test status
Simulation time 13397682604 ps
CPU time 13.21 seconds
Started Jul 20 06:19:32 PM PDT 24
Finished Jul 20 06:19:46 PM PDT 24
Peak memory 206696 kb
Host smart-54b8a438-1221-4c21-bc75-1cdcd0346c3b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1493079436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1493079436
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.3349550723
Short name T695
Test name
Test status
Simulation time 23305510210 ps
CPU time 23.19 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:57 PM PDT 24
Peak memory 206784 kb
Host smart-d74c7165-9110-47ed-b3fe-60a8e89b8e0d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3349550723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.3349550723
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.1023444793
Short name T1408
Test name
Test status
Simulation time 187798407 ps
CPU time 0.77 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:19:36 PM PDT 24
Peak memory 206664 kb
Host smart-4588e490-0a73-459b-9331-7779cc1e8ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10234
44793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.1023444793
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3669803156
Short name T57
Test name
Test status
Simulation time 193645205 ps
CPU time 0.91 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:35 PM PDT 24
Peak memory 206656 kb
Host smart-a87e7e9e-8b90-496f-85bd-5f9daa8b4009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36698
03156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3669803156
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.4289213720
Short name T88
Test name
Test status
Simulation time 134667580 ps
CPU time 0.78 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:34 PM PDT 24
Peak memory 206696 kb
Host smart-c4502d09-6c6d-4660-81ac-1962720df958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42892
13720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.4289213720
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3231057634
Short name T1761
Test name
Test status
Simulation time 151337320 ps
CPU time 0.81 seconds
Started Jul 20 06:19:31 PM PDT 24
Finished Jul 20 06:19:33 PM PDT 24
Peak memory 206656 kb
Host smart-7c6230ce-e0d6-4e2c-b22a-713d455f8df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32310
57634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3231057634
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1621665191
Short name T419
Test name
Test status
Simulation time 246293475 ps
CPU time 0.98 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:35 PM PDT 24
Peak memory 206644 kb
Host smart-b93928d5-7454-42c5-ad3a-91e118cc0f3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
65191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1621665191
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.4071674043
Short name T1436
Test name
Test status
Simulation time 825458599 ps
CPU time 2.2 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:19:37 PM PDT 24
Peak memory 206868 kb
Host smart-bd9db202-d5b1-449e-89c5-9ed3fe06c5cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40716
74043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.4071674043
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1985872173
Short name T1849
Test name
Test status
Simulation time 12106953288 ps
CPU time 21.94 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:19:57 PM PDT 24
Peak memory 206928 kb
Host smart-92bda7c9-11bc-4f19-9027-6d73e538f870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19858
72173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1985872173
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1155794542
Short name T745
Test name
Test status
Simulation time 386511493 ps
CPU time 1.2 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:35 PM PDT 24
Peak memory 206656 kb
Host smart-67cce23a-82ee-4603-8c15-239ca106b013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11557
94542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1155794542
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2233979405
Short name T2148
Test name
Test status
Simulation time 137570681 ps
CPU time 0.77 seconds
Started Jul 20 06:19:35 PM PDT 24
Finished Jul 20 06:19:37 PM PDT 24
Peak memory 206656 kb
Host smart-ba2e6086-cfd5-49dc-80b4-184e16d3992e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22339
79405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2233979405
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2771690148
Short name T2205
Test name
Test status
Simulation time 52174593 ps
CPU time 0.67 seconds
Started Jul 20 06:19:32 PM PDT 24
Finished Jul 20 06:19:34 PM PDT 24
Peak memory 206648 kb
Host smart-285088b3-6d16-457c-9d20-4655d67b752f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27716
90148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2771690148
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3357870042
Short name T1048
Test name
Test status
Simulation time 935698629 ps
CPU time 2.35 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:19:38 PM PDT 24
Peak memory 206732 kb
Host smart-99f35d5f-5831-4070-ab8c-d1a2fbae78a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33578
70042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3357870042
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.2024295288
Short name T1561
Test name
Test status
Simulation time 209585658 ps
CPU time 1.88 seconds
Started Jul 20 06:19:29 PM PDT 24
Finished Jul 20 06:19:32 PM PDT 24
Peak memory 206732 kb
Host smart-487048c1-5c3f-4dda-a567-57637ff691d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20242
95288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.2024295288
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.4026299987
Short name T1221
Test name
Test status
Simulation time 115192869839 ps
CPU time 156.66 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:22:12 PM PDT 24
Peak memory 206844 kb
Host smart-50d95cad-717a-406f-82f9-ef65a02a63f2
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4026299987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.4026299987
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.395703580
Short name T2507
Test name
Test status
Simulation time 121233331958 ps
CPU time 185.93 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206864 kb
Host smart-e4cd2275-3d26-41d2-9188-3bdbeab88998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395703580 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.395703580
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.2735831913
Short name T1235
Test name
Test status
Simulation time 106126385813 ps
CPU time 145.9 seconds
Started Jul 20 06:19:31 PM PDT 24
Finished Jul 20 06:21:58 PM PDT 24
Peak memory 206868 kb
Host smart-efa2b34e-b999-43fc-a992-552919fffa67
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2735831913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.2735831913
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.2698374735
Short name T368
Test name
Test status
Simulation time 114199760439 ps
CPU time 152.44 seconds
Started Jul 20 06:19:31 PM PDT 24
Finished Jul 20 06:22:05 PM PDT 24
Peak memory 206872 kb
Host smart-73952622-8e7d-4914-9046-96bfdeca21d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698374735 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.2698374735
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2326855471
Short name T1876
Test name
Test status
Simulation time 84164383588 ps
CPU time 100.64 seconds
Started Jul 20 06:19:32 PM PDT 24
Finished Jul 20 06:21:14 PM PDT 24
Peak memory 206868 kb
Host smart-2d968d51-189e-40bc-84e1-0c250a8215c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23268
55471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2326855471
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.3708792521
Short name T1255
Test name
Test status
Simulation time 218325946 ps
CPU time 0.96 seconds
Started Jul 20 06:19:33 PM PDT 24
Finished Jul 20 06:19:35 PM PDT 24
Peak memory 206660 kb
Host smart-73fec186-cee5-4731-afba-3af07d30d365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37087
92521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.3708792521
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.716248478
Short name T870
Test name
Test status
Simulation time 149436762 ps
CPU time 0.77 seconds
Started Jul 20 06:19:34 PM PDT 24
Finished Jul 20 06:19:36 PM PDT 24
Peak memory 206644 kb
Host smart-12cb4425-8802-4ea1-90b9-dcd4ec8140ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71624
8478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.716248478
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.861939311
Short name T948
Test name
Test status
Simulation time 171790109 ps
CPU time 0.82 seconds
Started Jul 20 06:19:44 PM PDT 24
Finished Jul 20 06:19:45 PM PDT 24
Peak memory 206636 kb
Host smart-74555e7c-3941-4ce6-9ebb-6cb080f6be11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86193
9311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.861939311
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.1375241796
Short name T1674
Test name
Test status
Simulation time 5029592946 ps
CPU time 37.61 seconds
Started Jul 20 06:19:41 PM PDT 24
Finished Jul 20 06:20:19 PM PDT 24
Peak memory 206920 kb
Host smart-63384a56-ef82-46ed-ab25-fb8dcba0938f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13752
41796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.1375241796
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2560669765
Short name T910
Test name
Test status
Simulation time 204309575 ps
CPU time 0.92 seconds
Started Jul 20 06:19:42 PM PDT 24
Finished Jul 20 06:19:43 PM PDT 24
Peak memory 206652 kb
Host smart-a06a4555-ee93-4cea-89b2-70f072e4c75a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25606
69765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2560669765
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.182478124
Short name T1449
Test name
Test status
Simulation time 23289726339 ps
CPU time 24.09 seconds
Started Jul 20 06:19:43 PM PDT 24
Finished Jul 20 06:20:08 PM PDT 24
Peak memory 206732 kb
Host smart-88eab8f5-f796-41f1-a989-4d2aba1424c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
8124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.182478124
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.1546081306
Short name T1868
Test name
Test status
Simulation time 3303101505 ps
CPU time 4.31 seconds
Started Jul 20 06:19:43 PM PDT 24
Finished Jul 20 06:19:48 PM PDT 24
Peak memory 206720 kb
Host smart-4ac1d2c1-c835-4930-bfd4-df9325e70a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15460
81306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.1546081306
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.2206635999
Short name T489
Test name
Test status
Simulation time 8380466967 ps
CPU time 217.03 seconds
Started Jul 20 06:19:43 PM PDT 24
Finished Jul 20 06:23:21 PM PDT 24
Peak memory 206924 kb
Host smart-accd1467-cc32-4e91-b1a7-edb6f047bbd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22066
35999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.2206635999
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.4004779310
Short name T1836
Test name
Test status
Simulation time 4802945720 ps
CPU time 131.31 seconds
Started Jul 20 06:19:44 PM PDT 24
Finished Jul 20 06:21:56 PM PDT 24
Peak memory 206832 kb
Host smart-223494d1-40a1-45a1-ab44-bb7b6cd8a2b9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4004779310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.4004779310
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.2636822412
Short name T2498
Test name
Test status
Simulation time 247420748 ps
CPU time 0.9 seconds
Started Jul 20 06:19:41 PM PDT 24
Finished Jul 20 06:19:42 PM PDT 24
Peak memory 206748 kb
Host smart-5e189a84-33a2-4506-ac8c-2a21d7133265
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2636822412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.2636822412
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.1701762819
Short name T324
Test name
Test status
Simulation time 192507869 ps
CPU time 0.93 seconds
Started Jul 20 06:19:42 PM PDT 24
Finished Jul 20 06:19:44 PM PDT 24
Peak memory 206700 kb
Host smart-4a2420f0-f135-4ab6-8779-4b43c85bdfb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17017
62819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.1701762819
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.600819996
Short name T1671
Test name
Test status
Simulation time 6944841122 ps
CPU time 49.89 seconds
Started Jul 20 06:19:44 PM PDT 24
Finished Jul 20 06:20:34 PM PDT 24
Peak memory 206872 kb
Host smart-7db2e8d6-273d-492b-9ce7-3887406ac1cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60081
9996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.600819996
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.609087487
Short name T1204
Test name
Test status
Simulation time 5805971383 ps
CPU time 41.63 seconds
Started Jul 20 06:19:42 PM PDT 24
Finished Jul 20 06:20:25 PM PDT 24
Peak memory 206916 kb
Host smart-be4dde5c-e49c-40eb-95fb-f41b64ab358c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=609087487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.609087487
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1504486420
Short name T376
Test name
Test status
Simulation time 168467212 ps
CPU time 0.78 seconds
Started Jul 20 06:19:44 PM PDT 24
Finished Jul 20 06:19:45 PM PDT 24
Peak memory 206648 kb
Host smart-578579b8-9858-4f39-8ee1-ff0180f31d48
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1504486420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1504486420
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.1513094493
Short name T1795
Test name
Test status
Simulation time 149009011 ps
CPU time 0.81 seconds
Started Jul 20 06:19:43 PM PDT 24
Finished Jul 20 06:19:45 PM PDT 24
Peak memory 206648 kb
Host smart-8bc03c6c-ca01-413e-a759-bb4ab74ce489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15130
94493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.1513094493
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.3167796196
Short name T1993
Test name
Test status
Simulation time 241639242 ps
CPU time 0.99 seconds
Started Jul 20 06:19:42 PM PDT 24
Finished Jul 20 06:19:44 PM PDT 24
Peak memory 206648 kb
Host smart-24ff41f4-a1b3-4ee2-893d-91acbe36404d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31677
96196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.3167796196
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2100823025
Short name T431
Test name
Test status
Simulation time 208437172 ps
CPU time 0.84 seconds
Started Jul 20 06:19:43 PM PDT 24
Finished Jul 20 06:19:45 PM PDT 24
Peak memory 206636 kb
Host smart-c49571c4-aff1-422f-835d-dc4cfa795c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21008
23025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2100823025
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.3590673212
Short name T1666
Test name
Test status
Simulation time 165836059 ps
CPU time 0.8 seconds
Started Jul 20 06:19:42 PM PDT 24
Finished Jul 20 06:19:44 PM PDT 24
Peak memory 206652 kb
Host smart-9751d03a-101b-49de-a7b9-a493827a896c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35906
73212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.3590673212
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.2274381082
Short name T1936
Test name
Test status
Simulation time 160180747 ps
CPU time 0.78 seconds
Started Jul 20 06:19:46 PM PDT 24
Finished Jul 20 06:19:47 PM PDT 24
Peak memory 206660 kb
Host smart-72297031-4d70-4f25-8286-f0b853000cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22743
81082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.2274381082
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.717036468
Short name T1746
Test name
Test status
Simulation time 144996107 ps
CPU time 0.77 seconds
Started Jul 20 06:19:40 PM PDT 24
Finished Jul 20 06:19:42 PM PDT 24
Peak memory 206624 kb
Host smart-e190c275-8b41-4c26-a8cf-18384586bcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71703
6468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.717036468
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.2675139784
Short name T1694
Test name
Test status
Simulation time 250813356 ps
CPU time 0.96 seconds
Started Jul 20 06:19:49 PM PDT 24
Finished Jul 20 06:19:50 PM PDT 24
Peak memory 206656 kb
Host smart-13fae5c1-b464-48c1-b47b-8f0931e71a01
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2675139784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.2675139784
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.564768614
Short name T613
Test name
Test status
Simulation time 196974279 ps
CPU time 0.9 seconds
Started Jul 20 06:20:01 PM PDT 24
Finished Jul 20 06:20:04 PM PDT 24
Peak memory 206660 kb
Host smart-9158349d-dd7b-4dbe-8308-82d1b2fd0d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56476
8614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.564768614
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2247975346
Short name T818
Test name
Test status
Simulation time 195416552 ps
CPU time 0.85 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:04 PM PDT 24
Peak memory 206276 kb
Host smart-61e55fc6-65c7-4c49-b05e-736b250d19c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22479
75346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2247975346
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.718556376
Short name T1648
Test name
Test status
Simulation time 66491559 ps
CPU time 0.68 seconds
Started Jul 20 06:19:47 PM PDT 24
Finished Jul 20 06:19:49 PM PDT 24
Peak memory 206620 kb
Host smart-d5c86309-f83c-46dd-8d08-f24d7985794e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71855
6376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.718556376
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.1336103570
Short name T1956
Test name
Test status
Simulation time 11646314265 ps
CPU time 27.45 seconds
Started Jul 20 06:19:53 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206880 kb
Host smart-3e68d9a4-692b-4674-815d-74eac7e1eca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13361
03570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.1336103570
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.932423323
Short name T2021
Test name
Test status
Simulation time 162378460 ps
CPU time 0.82 seconds
Started Jul 20 06:19:50 PM PDT 24
Finished Jul 20 06:19:52 PM PDT 24
Peak memory 206656 kb
Host smart-34830581-d8be-4d4d-bd62-56633e39ec41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93242
3323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.932423323
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2384251796
Short name T1334
Test name
Test status
Simulation time 178506919 ps
CPU time 0.81 seconds
Started Jul 20 06:19:53 PM PDT 24
Finished Jul 20 06:19:55 PM PDT 24
Peak memory 206652 kb
Host smart-4c2bdc9b-1534-49ee-b531-eb2eb0c212de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23842
51796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2384251796
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.292001877
Short name T617
Test name
Test status
Simulation time 4447906419 ps
CPU time 125.18 seconds
Started Jul 20 06:19:52 PM PDT 24
Finished Jul 20 06:21:59 PM PDT 24
Peak memory 206920 kb
Host smart-1477ffba-200e-412c-9435-93fada9db1e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=292001877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.292001877
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2385397801
Short name T1737
Test name
Test status
Simulation time 11306727216 ps
CPU time 307.42 seconds
Started Jul 20 06:19:50 PM PDT 24
Finished Jul 20 06:24:59 PM PDT 24
Peak memory 206960 kb
Host smart-40dbd4fa-5d94-4d0b-af3e-2258116a73e5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2385397801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2385397801
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.3300916629
Short name T2661
Test name
Test status
Simulation time 16318705572 ps
CPU time 339.77 seconds
Started Jul 20 06:19:54 PM PDT 24
Finished Jul 20 06:25:35 PM PDT 24
Peak memory 206940 kb
Host smart-e34f2c17-30d7-4741-a223-2342184bd65a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3300916629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.3300916629
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.2945499894
Short name T2584
Test name
Test status
Simulation time 196369022 ps
CPU time 0.83 seconds
Started Jul 20 06:19:49 PM PDT 24
Finished Jul 20 06:19:50 PM PDT 24
Peak memory 206664 kb
Host smart-690bab0a-b2c2-4e88-9acd-bbdd0eff0f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29454
99894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.2945499894
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3826415869
Short name T863
Test name
Test status
Simulation time 156438374 ps
CPU time 0.78 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 206648 kb
Host smart-8cbfda3f-f235-453b-ac13-46918a198302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38264
15869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3826415869
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3788531705
Short name T2586
Test name
Test status
Simulation time 224251458 ps
CPU time 0.87 seconds
Started Jul 20 06:19:54 PM PDT 24
Finished Jul 20 06:19:56 PM PDT 24
Peak memory 206652 kb
Host smart-58bb134a-3c0d-488b-afeb-d55442265c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37885
31705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3788531705
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.3829524691
Short name T78
Test name
Test status
Simulation time 171497612 ps
CPU time 0.81 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 206648 kb
Host smart-dff692fd-8acc-4abf-8873-ef4c251583da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38295
24691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.3829524691
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.2662150525
Short name T185
Test name
Test status
Simulation time 769612270 ps
CPU time 1.56 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:54 PM PDT 24
Peak memory 225552 kb
Host smart-e5b0a0c3-4567-44a4-9189-bf359269be9c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2662150525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.2662150525
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.82686774
Short name T61
Test name
Test status
Simulation time 361005667 ps
CPU time 1.17 seconds
Started Jul 20 06:19:53 PM PDT 24
Finished Jul 20 06:19:56 PM PDT 24
Peak memory 206648 kb
Host smart-0d9c9467-0483-4408-bda6-c0e040912754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82686
774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.82686774
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.3671454752
Short name T2561
Test name
Test status
Simulation time 335514924 ps
CPU time 1.03 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:05 PM PDT 24
Peak memory 206604 kb
Host smart-ce0afe29-c096-4bf7-aa15-95e70b1d7a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36714
54752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.3671454752
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2313373044
Short name T2174
Test name
Test status
Simulation time 166276677 ps
CPU time 0.84 seconds
Started Jul 20 06:19:54 PM PDT 24
Finished Jul 20 06:19:56 PM PDT 24
Peak memory 206640 kb
Host smart-1df3d438-9328-42d3-9e4d-8b08c93da715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23133
73044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2313373044
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3735767703
Short name T1399
Test name
Test status
Simulation time 193781124 ps
CPU time 0.8 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 206652 kb
Host smart-7f5d8868-8b4f-4046-8434-69307774a070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37357
67703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3735767703
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1219969863
Short name T1096
Test name
Test status
Simulation time 250249233 ps
CPU time 0.95 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 206648 kb
Host smart-5f8967ae-8938-419a-81cd-379edb8180c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12199
69863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1219969863
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.2197353988
Short name T169
Test name
Test status
Simulation time 4993358851 ps
CPU time 45.96 seconds
Started Jul 20 06:19:50 PM PDT 24
Finished Jul 20 06:20:38 PM PDT 24
Peak memory 206888 kb
Host smart-d1a29d75-3fe1-40ce-a641-21ed10006ff2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2197353988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.2197353988
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.2119104791
Short name T2458
Test name
Test status
Simulation time 196422523 ps
CPU time 0.82 seconds
Started Jul 20 06:19:49 PM PDT 24
Finished Jul 20 06:19:51 PM PDT 24
Peak memory 206668 kb
Host smart-753cb394-845b-4d75-a67e-bf466b4d738c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21191
04791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.2119104791
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.3780977779
Short name T1446
Test name
Test status
Simulation time 165891129 ps
CPU time 0.76 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 206780 kb
Host smart-68e85c66-45d0-4f2f-8149-df5c7738b79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
77779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.3780977779
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.3742991667
Short name T1239
Test name
Test status
Simulation time 1124380614 ps
CPU time 2.3 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:54 PM PDT 24
Peak memory 206776 kb
Host smart-a078cb6c-8982-4176-98f8-0daf9489edf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37429
91667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.3742991667
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.4167470755
Short name T492
Test name
Test status
Simulation time 3390284882 ps
CPU time 96.79 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:21:29 PM PDT 24
Peak memory 206848 kb
Host smart-f6da6ee7-bfef-4740-8664-e3d281c2ac4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41674
70755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.4167470755
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.1022617814
Short name T2061
Test name
Test status
Simulation time 8880377150 ps
CPU time 156.22 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:22:40 PM PDT 24
Peak memory 206940 kb
Host smart-b3fb4fb8-ab1f-4326-b8b9-e6cfdc2dd398
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1022617814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.1022617814
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3909710788
Short name T1480
Test name
Test status
Simulation time 48975457 ps
CPU time 0.71 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206808 kb
Host smart-7838d8b1-35d6-4beb-929e-3b902b00bfce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3909710788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3909710788
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3663669597
Short name T1807
Test name
Test status
Simulation time 4276394242 ps
CPU time 4.94 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:08 PM PDT 24
Peak memory 206808 kb
Host smart-3f163d51-8e2a-4cd8-8215-74ecfb484f6e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3663669597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3663669597
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.306776122
Short name T1950
Test name
Test status
Simulation time 13379857253 ps
CPU time 12.39 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206892 kb
Host smart-69657523-6379-42f7-b6ca-6519333399ea
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=306776122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.306776122
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.1397399863
Short name T624
Test name
Test status
Simulation time 23335267379 ps
CPU time 24.92 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:28 PM PDT 24
Peak memory 206764 kb
Host smart-325c26dc-7c9e-4499-9d2b-0b7a3e198575
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1397399863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.1397399863
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2576626863
Short name T1998
Test name
Test status
Simulation time 164841897 ps
CPU time 0.83 seconds
Started Jul 20 06:26:00 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206644 kb
Host smart-0c918140-16df-4d27-bf5d-a944ceeffb49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25766
26863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2576626863
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.71114964
Short name T2011
Test name
Test status
Simulation time 144902658 ps
CPU time 0.83 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:03 PM PDT 24
Peak memory 206652 kb
Host smart-71e59fa5-97fa-418d-ab9d-70946761d426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71114
964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.71114964
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3053593598
Short name T2050
Test name
Test status
Simulation time 445009749 ps
CPU time 1.47 seconds
Started Jul 20 06:26:02 PM PDT 24
Finished Jul 20 06:26:06 PM PDT 24
Peak memory 206692 kb
Host smart-5f9e0745-ea1b-406a-9c80-a6013c629321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30535
93598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3053593598
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2352320062
Short name T104
Test name
Test status
Simulation time 1217015215 ps
CPU time 2.79 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:26:01 PM PDT 24
Peak memory 206740 kb
Host smart-b537ded7-632a-4b85-904c-b6311381c963
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23523
20062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2352320062
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2101766933
Short name T981
Test name
Test status
Simulation time 19944291928 ps
CPU time 36.41 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206900 kb
Host smart-8c94481f-0e60-4aab-980f-66bdf66ec978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21017
66933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2101766933
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.3149988
Short name T2072
Test name
Test status
Simulation time 414464390 ps
CPU time 1.27 seconds
Started Jul 20 06:25:58 PM PDT 24
Finished Jul 20 06:26:02 PM PDT 24
Peak memory 206656 kb
Host smart-5512f804-17f8-49aa-a330-b9d3915b530a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31499
88 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.3149988
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.2044366092
Short name T1660
Test name
Test status
Simulation time 139794768 ps
CPU time 0.8 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:03 PM PDT 24
Peak memory 206652 kb
Host smart-ba07986e-945f-4254-a06e-3c05c7bf373b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20443
66092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.2044366092
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.328516183
Short name T453
Test name
Test status
Simulation time 36381716 ps
CPU time 0.67 seconds
Started Jul 20 06:25:57 PM PDT 24
Finished Jul 20 06:25:59 PM PDT 24
Peak memory 206584 kb
Host smart-f2f4a3c8-f157-43b7-8a5b-6ab6b0f63e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32851
6183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.328516183
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.4281532820
Short name T17
Test name
Test status
Simulation time 663337922 ps
CPU time 1.71 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:26:11 PM PDT 24
Peak memory 206800 kb
Host smart-44b8a201-6d86-48db-b700-aa3728cdcb45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42815
32820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.4281532820
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.142066472
Short name T714
Test name
Test status
Simulation time 320404713 ps
CPU time 2.01 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:04 PM PDT 24
Peak memory 206792 kb
Host smart-4d3ee71b-5c3b-4a4b-88b7-316f6a385834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14206
6472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.142066472
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1553981352
Short name T1481
Test name
Test status
Simulation time 168472292 ps
CPU time 0.87 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:10 PM PDT 24
Peak memory 206648 kb
Host smart-5a2623bd-b50d-4c15-b649-32e2a21a8658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15539
81352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1553981352
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.1572163521
Short name T2116
Test name
Test status
Simulation time 158524335 ps
CPU time 0.8 seconds
Started Jul 20 06:26:13 PM PDT 24
Finished Jul 20 06:26:15 PM PDT 24
Peak memory 206652 kb
Host smart-38f97d83-c0e7-4407-829f-6f03684530ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
63521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.1572163521
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.2302362520
Short name T379
Test name
Test status
Simulation time 260000559 ps
CPU time 0.96 seconds
Started Jul 20 06:26:10 PM PDT 24
Finished Jul 20 06:26:12 PM PDT 24
Peak memory 206624 kb
Host smart-84b36455-b02b-4480-a3af-782243e51033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23023
62520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.2302362520
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2965632550
Short name T1131
Test name
Test status
Simulation time 6250715601 ps
CPU time 43.45 seconds
Started Jul 20 06:25:59 PM PDT 24
Finished Jul 20 06:26:46 PM PDT 24
Peak memory 207020 kb
Host smart-dd109c61-6531-486a-8808-dc4d250221c0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2965632550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2965632550
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.2821590892
Short name T746
Test name
Test status
Simulation time 10781530447 ps
CPU time 36.68 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:46 PM PDT 24
Peak memory 206852 kb
Host smart-9c68a283-2de6-44f4-b67d-be489eaba901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28215
90892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.2821590892
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.2342197697
Short name T1338
Test name
Test status
Simulation time 230595542 ps
CPU time 0.89 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:09 PM PDT 24
Peak memory 206664 kb
Host smart-6d912bbf-fec7-4062-8708-d628f7856946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23421
97697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.2342197697
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.3022232610
Short name T524
Test name
Test status
Simulation time 23280643223 ps
CPU time 27.44 seconds
Started Jul 20 06:26:13 PM PDT 24
Finished Jul 20 06:26:42 PM PDT 24
Peak memory 206772 kb
Host smart-78fec3c4-59ba-48ec-ba2c-eb79cd03c56d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30222
32610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.3022232610
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3014940566
Short name T2353
Test name
Test status
Simulation time 3301927368 ps
CPU time 3.57 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206708 kb
Host smart-71ddd17a-e0a1-4e8f-932c-7011eb996141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30149
40566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3014940566
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.899746966
Short name T2309
Test name
Test status
Simulation time 13605740712 ps
CPU time 380.36 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:32:33 PM PDT 24
Peak memory 206944 kb
Host smart-bc18a1af-c7aa-46a3-af2a-46a77001bd55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89974
6966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.899746966
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.2280270538
Short name T643
Test name
Test status
Simulation time 6524220725 ps
CPU time 181.76 seconds
Started Jul 20 06:26:12 PM PDT 24
Finished Jul 20 06:29:16 PM PDT 24
Peak memory 206820 kb
Host smart-e4a7d0a5-710b-4b86-81ce-ede47bfaa796
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2280270538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.2280270538
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.992446089
Short name T1719
Test name
Test status
Simulation time 240824141 ps
CPU time 0.93 seconds
Started Jul 20 06:26:04 PM PDT 24
Finished Jul 20 06:26:07 PM PDT 24
Peak memory 206644 kb
Host smart-33c1aea8-36a7-4565-bebc-43e338d09cc8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=992446089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.992446089
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.3122435747
Short name T1210
Test name
Test status
Simulation time 212204060 ps
CPU time 0.86 seconds
Started Jul 20 06:26:10 PM PDT 24
Finished Jul 20 06:26:12 PM PDT 24
Peak memory 206592 kb
Host smart-5c083803-b3df-4d9f-9ba1-973ef8632199
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31224
35747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.3122435747
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.2134977651
Short name T2192
Test name
Test status
Simulation time 5446296261 ps
CPU time 147.45 seconds
Started Jul 20 06:26:15 PM PDT 24
Finished Jul 20 06:28:43 PM PDT 24
Peak memory 206864 kb
Host smart-d4abb317-0f60-47c5-a362-9b738e844778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21349
77651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.2134977651
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.887644266
Short name T2112
Test name
Test status
Simulation time 7880021957 ps
CPU time 76.2 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:27:26 PM PDT 24
Peak memory 206868 kb
Host smart-83a25154-f695-4425-8a0f-c4f575d16774
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=887644266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.887644266
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.3893834291
Short name T21
Test name
Test status
Simulation time 171949879 ps
CPU time 0.78 seconds
Started Jul 20 06:26:13 PM PDT 24
Finished Jul 20 06:26:15 PM PDT 24
Peak memory 206636 kb
Host smart-65d5e0ed-d921-423a-ae17-9e8d4ffcb121
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3893834291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.3893834291
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3207340229
Short name T2284
Test name
Test status
Simulation time 210591664 ps
CPU time 0.81 seconds
Started Jul 20 06:26:12 PM PDT 24
Finished Jul 20 06:26:15 PM PDT 24
Peak memory 206660 kb
Host smart-496a36ab-0aa6-4275-a9bb-6f7f96f8bcb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
40229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3207340229
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.926060259
Short name T1424
Test name
Test status
Simulation time 319309368 ps
CPU time 0.96 seconds
Started Jul 20 06:26:12 PM PDT 24
Finished Jul 20 06:26:15 PM PDT 24
Peak memory 206672 kb
Host smart-e89a5b84-4248-4aee-8ba4-0b6433509be4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92606
0259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.926060259
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.3409520925
Short name T1438
Test name
Test status
Simulation time 157287797 ps
CPU time 0.88 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:10 PM PDT 24
Peak memory 206648 kb
Host smart-443e14f4-0bc8-4c4d-9c3a-1064dfd55f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34095
20925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.3409520925
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.768180610
Short name T29
Test name
Test status
Simulation time 150028224 ps
CPU time 0.78 seconds
Started Jul 20 06:26:06 PM PDT 24
Finished Jul 20 06:26:08 PM PDT 24
Peak memory 206656 kb
Host smart-101769a1-76dc-45d9-bab7-d943fe9c59af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76818
0610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.768180610
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.920275379
Short name T1425
Test name
Test status
Simulation time 226757263 ps
CPU time 0.86 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:26:14 PM PDT 24
Peak memory 206772 kb
Host smart-cb8f6a02-1d20-4c6f-a7cf-5dfa2a66fba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92027
5379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.920275379
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.933687392
Short name T2638
Test name
Test status
Simulation time 148536872 ps
CPU time 0.8 seconds
Started Jul 20 06:26:10 PM PDT 24
Finished Jul 20 06:26:12 PM PDT 24
Peak memory 206648 kb
Host smart-ece6b64c-aebb-4b94-bea0-9aeffcd12b3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93368
7392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.933687392
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.3278876359
Short name T655
Test name
Test status
Simulation time 302064635 ps
CPU time 1.07 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206628 kb
Host smart-f19ee2e4-3473-440e-a827-c95aa74c093d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3278876359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.3278876359
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.957229445
Short name T1259
Test name
Test status
Simulation time 143929843 ps
CPU time 0.77 seconds
Started Jul 20 06:26:10 PM PDT 24
Finished Jul 20 06:26:12 PM PDT 24
Peak memory 206752 kb
Host smart-c44d5c65-3b44-4bb9-9ed5-2c15c46681d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95722
9445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.957229445
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.2009475065
Short name T2196
Test name
Test status
Simulation time 77525481 ps
CPU time 0.72 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206636 kb
Host smart-d01ed7fe-f342-4eee-a72c-7d86defe925a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20094
75065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.2009475065
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.395802048
Short name T1430
Test name
Test status
Simulation time 20661780175 ps
CPU time 49.93 seconds
Started Jul 20 06:26:06 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 206940 kb
Host smart-c4fa3681-00fb-45da-9cc5-e1a9568c1392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39580
2048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.395802048
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2577919900
Short name T2175
Test name
Test status
Simulation time 218245574 ps
CPU time 0.87 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:10 PM PDT 24
Peak memory 206660 kb
Host smart-b876b387-2136-4bdd-b3d4-80b9cb501268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25779
19900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2577919900
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.2421749815
Short name T960
Test name
Test status
Simulation time 189145004 ps
CPU time 0.85 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:10 PM PDT 24
Peak memory 206644 kb
Host smart-e9b0ada2-78ca-41e7-84be-ba67e3c094cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24217
49815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.2421749815
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.1584906977
Short name T2168
Test name
Test status
Simulation time 195709831 ps
CPU time 0.86 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:26:11 PM PDT 24
Peak memory 206648 kb
Host smart-d577a36a-c6c5-47d2-a77a-e11505756e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15849
06977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.1584906977
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.629049338
Short name T1432
Test name
Test status
Simulation time 169833181 ps
CPU time 0.91 seconds
Started Jul 20 06:26:14 PM PDT 24
Finished Jul 20 06:26:17 PM PDT 24
Peak memory 206652 kb
Host smart-e8d0f0ec-8d3e-4d7a-8460-530bc057320c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62904
9338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.629049338
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.394319983
Short name T1433
Test name
Test status
Simulation time 240253352 ps
CPU time 0.85 seconds
Started Jul 20 06:26:12 PM PDT 24
Finished Jul 20 06:26:15 PM PDT 24
Peak memory 206652 kb
Host smart-b8a78c03-f43e-4bed-9755-f290dc851761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39431
9983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.394319983
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.2138881902
Short name T2052
Test name
Test status
Simulation time 171322351 ps
CPU time 0.8 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206620 kb
Host smart-91de1a21-de57-4c7e-b73a-39dc295c3146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21388
81902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.2138881902
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.338332446
Short name T1906
Test name
Test status
Simulation time 178681845 ps
CPU time 0.82 seconds
Started Jul 20 06:26:13 PM PDT 24
Finished Jul 20 06:26:15 PM PDT 24
Peak memory 206672 kb
Host smart-784e1253-c6e2-4a8b-8ff3-39cf2e7078db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33833
2446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.338332446
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.1591857491
Short name T2244
Test name
Test status
Simulation time 258839945 ps
CPU time 0.95 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206644 kb
Host smart-40682eb9-564c-4d15-be50-852b427165cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15918
57491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.1591857491
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.884164603
Short name T2087
Test name
Test status
Simulation time 6171886861 ps
CPU time 171.67 seconds
Started Jul 20 06:26:09 PM PDT 24
Finished Jul 20 06:29:02 PM PDT 24
Peak memory 206868 kb
Host smart-6774ff26-78d1-44de-a6de-323d07f044fd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=884164603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.884164603
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2936946278
Short name T639
Test name
Test status
Simulation time 206603706 ps
CPU time 0.84 seconds
Started Jul 20 06:26:09 PM PDT 24
Finished Jul 20 06:26:11 PM PDT 24
Peak memory 206660 kb
Host smart-a0157d02-38c6-45bd-bfc0-7c93ecd69df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29369
46278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2936946278
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.118469173
Short name T1521
Test name
Test status
Simulation time 152870528 ps
CPU time 0.75 seconds
Started Jul 20 06:26:10 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206760 kb
Host smart-5548135a-56b5-43f3-86e3-b4eb087621a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11846
9173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.118469173
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.365027282
Short name T2172
Test name
Test status
Simulation time 1028432772 ps
CPU time 2.37 seconds
Started Jul 20 06:26:07 PM PDT 24
Finished Jul 20 06:26:11 PM PDT 24
Peak memory 206800 kb
Host smart-96c1de56-a740-4a42-8859-6d1e09253432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36502
7282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.365027282
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1320761285
Short name T2734
Test name
Test status
Simulation time 3933061205 ps
CPU time 28.39 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:26:38 PM PDT 24
Peak memory 206928 kb
Host smart-eb16f96c-76b9-4840-be97-8f180e10ec68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13207
61285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1320761285
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.2180742089
Short name T2060
Test name
Test status
Simulation time 48297372 ps
CPU time 0.71 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206724 kb
Host smart-96cbf228-5f5c-4b25-b11a-ff9c4080a54d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2180742089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.2180742089
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.573518800
Short name T1047
Test name
Test status
Simulation time 3942734791 ps
CPU time 5.16 seconds
Started Jul 20 06:26:12 PM PDT 24
Finished Jul 20 06:26:19 PM PDT 24
Peak memory 206692 kb
Host smart-9d637402-8fe5-4967-8174-44168922daf6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=573518800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.573518800
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.471625885
Short name T1505
Test name
Test status
Simulation time 13425844603 ps
CPU time 12.12 seconds
Started Jul 20 06:26:06 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206780 kb
Host smart-15cafe18-f67f-4a8b-9819-7073dd57fcb7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=471625885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.471625885
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2095364885
Short name T2728
Test name
Test status
Simulation time 23389699073 ps
CPU time 26.88 seconds
Started Jul 20 06:26:09 PM PDT 24
Finished Jul 20 06:26:38 PM PDT 24
Peak memory 206764 kb
Host smart-3a65aa25-7d29-426e-9c71-0e3b2a6a7f62
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2095364885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2095364885
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2993484186
Short name T2651
Test name
Test status
Simulation time 188959594 ps
CPU time 0.86 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:19 PM PDT 24
Peak memory 206652 kb
Host smart-138b5895-d1b2-430b-897f-9f88db5e29c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29934
84186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2993484186
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2386143657
Short name T2283
Test name
Test status
Simulation time 139270968 ps
CPU time 0.77 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206756 kb
Host smart-4431287d-6aa0-4f29-b6ad-7ce471a29954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23861
43657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2386143657
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.1473411843
Short name T937
Test name
Test status
Simulation time 296238194 ps
CPU time 1.12 seconds
Started Jul 20 06:26:08 PM PDT 24
Finished Jul 20 06:26:11 PM PDT 24
Peak memory 206636 kb
Host smart-0bf13b64-a4ff-4c3d-a53c-8e009af6b578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14734
11843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.1473411843
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.1774761887
Short name T1589
Test name
Test status
Simulation time 830693970 ps
CPU time 2.08 seconds
Started Jul 20 06:26:04 PM PDT 24
Finished Jul 20 06:26:08 PM PDT 24
Peak memory 206788 kb
Host smart-02d97834-58fb-4cae-a1e1-a171f1a4479f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17747
61887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.1774761887
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2369900032
Short name T1540
Test name
Test status
Simulation time 12597942734 ps
CPU time 25.19 seconds
Started Jul 20 06:26:05 PM PDT 24
Finished Jul 20 06:26:32 PM PDT 24
Peak memory 206908 kb
Host smart-e524a54a-9b44-4d80-bf14-fbd92266ac5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23699
00032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2369900032
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.2910190669
Short name T339
Test name
Test status
Simulation time 488262439 ps
CPU time 1.56 seconds
Started Jul 20 06:26:12 PM PDT 24
Finished Jul 20 06:26:16 PM PDT 24
Peak memory 206652 kb
Host smart-ea9d4b34-699f-4362-a816-c2c4c386eee8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29101
90669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.2910190669
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1752423707
Short name T1770
Test name
Test status
Simulation time 159472209 ps
CPU time 0.75 seconds
Started Jul 20 06:26:05 PM PDT 24
Finished Jul 20 06:26:08 PM PDT 24
Peak memory 206600 kb
Host smart-b352d69b-f35f-4420-969e-003e97b54e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17524
23707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1752423707
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.523445780
Short name T2443
Test name
Test status
Simulation time 52604840 ps
CPU time 0.68 seconds
Started Jul 20 06:26:10 PM PDT 24
Finished Jul 20 06:26:12 PM PDT 24
Peak memory 206644 kb
Host smart-eafd6ad1-9549-4eae-aa60-255aacbda2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52344
5780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.523445780
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2341112765
Short name T1711
Test name
Test status
Simulation time 849301556 ps
CPU time 2.18 seconds
Started Jul 20 06:26:10 PM PDT 24
Finished Jul 20 06:26:13 PM PDT 24
Peak memory 206744 kb
Host smart-476ec034-4455-4120-9132-d5ab220d8ed6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23411
12765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2341112765
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.656612932
Short name T2083
Test name
Test status
Simulation time 317486488 ps
CPU time 1.74 seconds
Started Jul 20 06:26:11 PM PDT 24
Finished Jul 20 06:26:15 PM PDT 24
Peak memory 206752 kb
Host smart-34847d38-e593-44e5-9050-9fbda958327e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65661
2932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.656612932
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.1582671247
Short name T2741
Test name
Test status
Simulation time 233702924 ps
CPU time 0.87 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206652 kb
Host smart-97abf441-70b2-4d2c-8a3e-66bbb2bc5d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15826
71247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.1582671247
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1420265649
Short name T761
Test name
Test status
Simulation time 143644805 ps
CPU time 0.74 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:35 PM PDT 24
Peak memory 206640 kb
Host smart-624eb3f2-a779-4b65-94d5-a2ac8188b6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14202
65649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1420265649
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.4207079447
Short name T2352
Test name
Test status
Simulation time 153648712 ps
CPU time 0.78 seconds
Started Jul 20 06:26:14 PM PDT 24
Finished Jul 20 06:26:16 PM PDT 24
Peak memory 206656 kb
Host smart-e7dc4967-4065-4ac0-8a04-3e38971e6446
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42070
79447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.4207079447
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.1953321329
Short name T1853
Test name
Test status
Simulation time 12082697880 ps
CPU time 39.46 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206876 kb
Host smart-7885113f-795f-46e0-a91e-1ae86565a50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19533
21329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.1953321329
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.287344346
Short name T1882
Test name
Test status
Simulation time 202132472 ps
CPU time 0.86 seconds
Started Jul 20 06:26:20 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206652 kb
Host smart-ab8e5f41-1d35-4972-8dfa-9d2abf3faacd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28734
4346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.287344346
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.584515814
Short name T2388
Test name
Test status
Simulation time 23287639398 ps
CPU time 30.98 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:52 PM PDT 24
Peak memory 206776 kb
Host smart-a34d31a1-3d3e-420a-a2ca-6bb86dd6b6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58451
5814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.584515814
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.2560600349
Short name T741
Test name
Test status
Simulation time 3281915075 ps
CPU time 4.23 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206708 kb
Host smart-9a77ff14-35d9-41b9-9e99-5273236b5b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25606
00349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.2560600349
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.611742352
Short name T1015
Test name
Test status
Simulation time 6557667942 ps
CPU time 174.94 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:29:12 PM PDT 24
Peak memory 206952 kb
Host smart-51d97205-2c82-4efb-aab3-14d80da5f86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61174
2352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.611742352
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.3437743302
Short name T873
Test name
Test status
Simulation time 5455735804 ps
CPU time 51.09 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206844 kb
Host smart-1ad591d8-25d9-4cb9-ad82-f9d4d145a11b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3437743302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.3437743302
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.351856643
Short name T2435
Test name
Test status
Simulation time 243080185 ps
CPU time 0.92 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206656 kb
Host smart-345049b8-efce-4bb0-933c-0c6839f7f1d4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=351856643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.351856643
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.1567593015
Short name T1847
Test name
Test status
Simulation time 226483118 ps
CPU time 0.89 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206644 kb
Host smart-ecc79e1a-8243-489f-adab-71512f5b04ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15675
93015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.1567593015
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.1783344947
Short name T1779
Test name
Test status
Simulation time 3311099511 ps
CPU time 23.17 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:41 PM PDT 24
Peak memory 206908 kb
Host smart-fb8e34c2-a639-4f36-bb4f-169c5b192d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17833
44947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.1783344947
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2364365389
Short name T1141
Test name
Test status
Simulation time 5397158670 ps
CPU time 38.46 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206816 kb
Host smart-8d958545-8106-45ce-b328-d0e0e44046cd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2364365389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2364365389
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.2737377033
Short name T2239
Test name
Test status
Simulation time 156419460 ps
CPU time 0.8 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:26:23 PM PDT 24
Peak memory 206648 kb
Host smart-4086d0d6-06f5-44b9-b3a4-eb86b5a6f185
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2737377033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.2737377033
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2420717851
Short name T2639
Test name
Test status
Simulation time 185219662 ps
CPU time 0.81 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:19 PM PDT 24
Peak memory 206664 kb
Host smart-e8595e32-4bf0-4cfc-8976-a21fb74cbc7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24207
17851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2420717851
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.40853518
Short name T124
Test name
Test status
Simulation time 217878693 ps
CPU time 0.91 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206648 kb
Host smart-486babe2-ccea-4f0a-8824-ddb95c05029e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40853
518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.40853518
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.2172873459
Short name T2327
Test name
Test status
Simulation time 216901305 ps
CPU time 0.93 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:21 PM PDT 24
Peak memory 206648 kb
Host smart-a8f69bfc-786b-49ae-9167-0721742b38b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21728
73459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.2172873459
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.1391915423
Short name T662
Test name
Test status
Simulation time 152419023 ps
CPU time 0.79 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:21 PM PDT 24
Peak memory 206644 kb
Host smart-a88b89eb-1d46-4437-bf2e-9b70d5d44749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13919
15423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.1391915423
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.1930885543
Short name T1985
Test name
Test status
Simulation time 243191458 ps
CPU time 0.85 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206636 kb
Host smart-e055fb40-6295-46f2-afbc-edba996d686e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19308
85543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.1930885543
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.306957
Short name T1129
Test name
Test status
Simulation time 153856935 ps
CPU time 0.79 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:26:23 PM PDT 24
Peak memory 206604 kb
Host smart-5e14a68c-cfff-4f1b-bcc2-c765196ac231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30695
7 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.306957
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.271732777
Short name T555
Test name
Test status
Simulation time 249767247 ps
CPU time 0.98 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206652 kb
Host smart-981caa5a-d28e-45d5-8d0c-9b7a6ee6e8d6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=271732777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.271732777
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.2105844710
Short name T1072
Test name
Test status
Simulation time 171450170 ps
CPU time 0.78 seconds
Started Jul 20 06:26:15 PM PDT 24
Finished Jul 20 06:26:17 PM PDT 24
Peak memory 206640 kb
Host smart-0da0d6d7-7907-42b3-9440-4ba795335e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21058
44710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.2105844710
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3138797196
Short name T969
Test name
Test status
Simulation time 74681869 ps
CPU time 0.71 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206628 kb
Host smart-2bfb0057-11f7-42ff-87c5-0381b97afe47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31387
97196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3138797196
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.233467176
Short name T2694
Test name
Test status
Simulation time 8842674892 ps
CPU time 20 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:41 PM PDT 24
Peak memory 206944 kb
Host smart-06e7ed3c-cff5-4319-bb8e-de9dbf4117c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23346
7176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.233467176
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.1633323809
Short name T528
Test name
Test status
Simulation time 171559088 ps
CPU time 0.83 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206632 kb
Host smart-a803a3f1-976e-4b0e-8ce9-74cd2131fd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16333
23809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.1633323809
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.3945883935
Short name T917
Test name
Test status
Simulation time 206263996 ps
CPU time 0.82 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206652 kb
Host smart-79c3c513-5d68-49c7-8b4f-6adfbdae0f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39458
83935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.3945883935
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.23872496
Short name T1366
Test name
Test status
Simulation time 207728129 ps
CPU time 0.81 seconds
Started Jul 20 06:26:25 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206640 kb
Host smart-da89cea0-266e-4684-9ffa-0dd05cf9f871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23872
496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.23872496
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.1569627049
Short name T738
Test name
Test status
Simulation time 181440821 ps
CPU time 0.83 seconds
Started Jul 20 06:26:15 PM PDT 24
Finished Jul 20 06:26:17 PM PDT 24
Peak memory 206636 kb
Host smart-01d4201b-6137-41ec-8dba-b233c607db6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15696
27049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.1569627049
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.1251174825
Short name T2521
Test name
Test status
Simulation time 153938886 ps
CPU time 0.81 seconds
Started Jul 20 06:26:15 PM PDT 24
Finished Jul 20 06:26:17 PM PDT 24
Peak memory 206636 kb
Host smart-79726cd4-39cd-4a43-8ca7-3982cf07c865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12511
74825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.1251174825
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.1948599748
Short name T1145
Test name
Test status
Simulation time 179539714 ps
CPU time 0.84 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206660 kb
Host smart-871106d4-6116-45c4-bafa-f63867df5762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19485
99748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.1948599748
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.2122936865
Short name T2575
Test name
Test status
Simulation time 246367340 ps
CPU time 0.86 seconds
Started Jul 20 06:26:20 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206644 kb
Host smart-eb1dc48a-fae5-414c-906e-f86eb509d66d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
36865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.2122936865
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.3187060373
Short name T901
Test name
Test status
Simulation time 235398088 ps
CPU time 0.9 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:21 PM PDT 24
Peak memory 206652 kb
Host smart-5dcea4cb-b0d7-4144-80d9-cadb6e57df64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31870
60373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.3187060373
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.2783888308
Short name T1345
Test name
Test status
Simulation time 6266064845 ps
CPU time 180.1 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:29:22 PM PDT 24
Peak memory 206836 kb
Host smart-0db40d43-6b9b-44b3-8e12-ae4dcc043ee6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2783888308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.2783888308
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.2381329382
Short name T2677
Test name
Test status
Simulation time 158038189 ps
CPU time 0.8 seconds
Started Jul 20 06:26:20 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206628 kb
Host smart-0167248a-a00b-498d-87ce-b704e61cbe8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23813
29382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.2381329382
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.2281011025
Short name T1413
Test name
Test status
Simulation time 162600199 ps
CPU time 0.78 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206636 kb
Host smart-3aa30c0a-d1fe-4574-800c-5e1cb71ebc9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22810
11025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.2281011025
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.888071814
Short name T1670
Test name
Test status
Simulation time 405288553 ps
CPU time 1.3 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206640 kb
Host smart-664c0ba7-b92c-46fb-9779-19faf5cbb3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88807
1814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.888071814
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.2179830811
Short name T484
Test name
Test status
Simulation time 4261757061 ps
CPU time 41.25 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206836 kb
Host smart-075f7da6-843d-4a18-9b5d-4abdcbcbe3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21798
30811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.2179830811
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.420245733
Short name T176
Test name
Test status
Simulation time 48597679 ps
CPU time 0.67 seconds
Started Jul 20 06:26:25 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206624 kb
Host smart-319bf0a9-8231-48fd-8a7a-5171da10a720
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=420245733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.420245733
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1083188785
Short name T936
Test name
Test status
Simulation time 4392202945 ps
CPU time 5.52 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:28 PM PDT 24
Peak memory 206752 kb
Host smart-e5bef21d-3e6b-441a-996f-c67fa7e6e974
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1083188785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1083188785
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.4183116097
Short name T2275
Test name
Test status
Simulation time 13369406886 ps
CPU time 13.38 seconds
Started Jul 20 06:26:20 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206776 kb
Host smart-cdd4fc56-f76d-4f90-bca3-b35d7e3bbb44
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4183116097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.4183116097
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.3801781692
Short name T2264
Test name
Test status
Simulation time 23413126308 ps
CPU time 26.3 seconds
Started Jul 20 06:26:23 PM PDT 24
Finished Jul 20 06:26:51 PM PDT 24
Peak memory 206804 kb
Host smart-b49845f1-cc60-4db2-b8f1-b3aebd3edda2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3801781692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.3801781692
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.947205210
Short name T590
Test name
Test status
Simulation time 180881500 ps
CPU time 0.79 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206660 kb
Host smart-162c4c8e-79f0-488e-8bb1-ef31b5483ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94720
5210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.947205210
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.373224618
Short name T2556
Test name
Test status
Simulation time 139039189 ps
CPU time 0.78 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206636 kb
Host smart-70e387ca-f1d7-44cb-9a80-69fd10165e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37322
4618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.373224618
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1166072201
Short name T1376
Test name
Test status
Simulation time 450765246 ps
CPU time 1.4 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206644 kb
Host smart-ee9b2f8b-7509-4772-8201-c06478eac4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11660
72201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1166072201
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3042154323
Short name T2166
Test name
Test status
Simulation time 432572782 ps
CPU time 1.25 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:19 PM PDT 24
Peak memory 206744 kb
Host smart-70a06495-8d8b-4a37-8c08-4fa661f37c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30421
54323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3042154323
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.1107824425
Short name T2729
Test name
Test status
Simulation time 9638737891 ps
CPU time 19.25 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:41 PM PDT 24
Peak memory 206736 kb
Host smart-4837973a-fcad-4a0a-9c62-cab730b138e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11078
24425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.1107824425
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.1555671681
Short name T709
Test name
Test status
Simulation time 517595934 ps
CPU time 1.5 seconds
Started Jul 20 06:26:21 PM PDT 24
Finished Jul 20 06:26:25 PM PDT 24
Peak memory 206696 kb
Host smart-3a548e22-2c20-4856-a1de-5f1e0d451559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15556
71681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.1555671681
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3591147939
Short name T2664
Test name
Test status
Simulation time 169913165 ps
CPU time 0.78 seconds
Started Jul 20 06:26:21 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206648 kb
Host smart-63959d33-e587-404b-bb14-ea92747c69f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35911
47939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3591147939
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.974751491
Short name T373
Test name
Test status
Simulation time 77623363 ps
CPU time 0.68 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206648 kb
Host smart-60e7871d-720a-41c6-a906-4f20643d0fd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97475
1491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.974751491
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.2636495223
Short name T990
Test name
Test status
Simulation time 965605998 ps
CPU time 2.45 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:26:25 PM PDT 24
Peak memory 206776 kb
Host smart-c16e3fb7-b3db-4cb9-8287-a2cb57fcd1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26364
95223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.2636495223
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.2755183471
Short name T2090
Test name
Test status
Simulation time 250939825 ps
CPU time 1.52 seconds
Started Jul 20 06:26:28 PM PDT 24
Finished Jul 20 06:26:32 PM PDT 24
Peak memory 206736 kb
Host smart-eb5bfe42-9fb0-45ec-a01c-e2976f23e829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27551
83471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.2755183471
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.2552416191
Short name T1796
Test name
Test status
Simulation time 196996470 ps
CPU time 0.88 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:23 PM PDT 24
Peak memory 206472 kb
Host smart-9d238f1b-7cd0-4299-a1ce-6ba3ae8c5609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25524
16191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.2552416191
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.4246440298
Short name T445
Test name
Test status
Simulation time 143700784 ps
CPU time 0.76 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206668 kb
Host smart-690dfd68-049a-4c0a-bd4c-c19590e9ee8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42464
40298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.4246440298
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.2980334110
Short name T2046
Test name
Test status
Simulation time 191912760 ps
CPU time 0.84 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206636 kb
Host smart-ccb1c3a4-4191-4bee-8a2f-8d91f6eccbc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29803
34110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.2980334110
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.109733882
Short name T2102
Test name
Test status
Simulation time 6889427293 ps
CPU time 21.7 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:43 PM PDT 24
Peak memory 206856 kb
Host smart-1617bbbc-6467-4403-b056-ba964ea912f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10973
3882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.109733882
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.819236463
Short name T1189
Test name
Test status
Simulation time 253781348 ps
CPU time 0.9 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:20 PM PDT 24
Peak memory 206644 kb
Host smart-3eb2cd7c-1800-46f2-9740-7c12bfa7074a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81923
6463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.819236463
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.1278519457
Short name T1256
Test name
Test status
Simulation time 23323549340 ps
CPU time 22.77 seconds
Started Jul 20 06:26:18 PM PDT 24
Finished Jul 20 06:26:45 PM PDT 24
Peak memory 206776 kb
Host smart-5adfa9a3-dc54-4e2f-98ee-8296d36af0cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12785
19457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.1278519457
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2280634888
Short name T2084
Test name
Test status
Simulation time 3301979085 ps
CPU time 4.13 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:25 PM PDT 24
Peak memory 206724 kb
Host smart-71aad1e2-fb2d-471f-8ce4-de02e331f626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22806
34888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2280634888
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.4035530259
Short name T935
Test name
Test status
Simulation time 9491659795 ps
CPU time 251.1 seconds
Started Jul 20 06:26:20 PM PDT 24
Finished Jul 20 06:30:34 PM PDT 24
Peak memory 206900 kb
Host smart-f7419afb-b7c7-46c9-ad3e-fbb14c6db339
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40355
30259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.4035530259
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.609955584
Short name T1378
Test name
Test status
Simulation time 4270398305 ps
CPU time 32.05 seconds
Started Jul 20 06:26:22 PM PDT 24
Finished Jul 20 06:26:56 PM PDT 24
Peak memory 206880 kb
Host smart-b5fcb01f-a2de-43b5-9f84-b1b6faa4231b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=609955584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.609955584
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.2833819094
Short name T1665
Test name
Test status
Simulation time 244993098 ps
CPU time 0.97 seconds
Started Jul 20 06:26:29 PM PDT 24
Finished Jul 20 06:26:33 PM PDT 24
Peak memory 206640 kb
Host smart-eb886076-9ea8-4e81-85e8-cb21bbb8311e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2833819094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.2833819094
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.720802550
Short name T2093
Test name
Test status
Simulation time 193660393 ps
CPU time 0.89 seconds
Started Jul 20 06:26:17 PM PDT 24
Finished Jul 20 06:26:22 PM PDT 24
Peak memory 206640 kb
Host smart-72f9ca1e-65e6-44fe-adf1-67fb56c16f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72080
2550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.720802550
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1452584295
Short name T995
Test name
Test status
Simulation time 5637832085 ps
CPU time 163.63 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:29:06 PM PDT 24
Peak memory 206864 kb
Host smart-841d1937-7a36-4fa4-b60f-2a9d3a9a1f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14525
84295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1452584295
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.179831454
Short name T2427
Test name
Test status
Simulation time 5430789709 ps
CPU time 40.31 seconds
Started Jul 20 06:26:20 PM PDT 24
Finished Jul 20 06:27:03 PM PDT 24
Peak memory 206844 kb
Host smart-8d7254cf-cf90-457e-b230-f3d2d3e1322e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=179831454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.179831454
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3941378191
Short name T2324
Test name
Test status
Simulation time 179802906 ps
CPU time 0.81 seconds
Started Jul 20 06:26:21 PM PDT 24
Finished Jul 20 06:26:25 PM PDT 24
Peak memory 206656 kb
Host smart-466a4149-4a85-44e1-a8b4-85741512bab6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3941378191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3941378191
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3751536631
Short name T1134
Test name
Test status
Simulation time 193005605 ps
CPU time 0.8 seconds
Started Jul 20 06:26:20 PM PDT 24
Finished Jul 20 06:26:24 PM PDT 24
Peak memory 206660 kb
Host smart-8541fd09-fdec-445f-a1b2-02d1060bacca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37515
36631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3751536631
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.3727298923
Short name T142
Test name
Test status
Simulation time 217400256 ps
CPU time 0.83 seconds
Started Jul 20 06:26:19 PM PDT 24
Finished Jul 20 06:26:23 PM PDT 24
Peak memory 206644 kb
Host smart-00534d68-e946-4933-8ebe-8b0aa0433d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37272
98923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.3727298923
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.2712657305
Short name T2045
Test name
Test status
Simulation time 192161234 ps
CPU time 0.84 seconds
Started Jul 20 06:26:16 PM PDT 24
Finished Jul 20 06:26:19 PM PDT 24
Peak memory 206656 kb
Host smart-49538a4f-9cac-4ccf-a1e1-0f02f2cd0b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27126
57305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.2712657305
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.3966478709
Short name T1406
Test name
Test status
Simulation time 206768933 ps
CPU time 0.89 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206628 kb
Host smart-081a5e65-6df1-4f70-84da-f4ef81ccad25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39664
78709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.3966478709
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.4242712538
Short name T2318
Test name
Test status
Simulation time 177374892 ps
CPU time 0.83 seconds
Started Jul 20 06:26:25 PM PDT 24
Finished Jul 20 06:26:28 PM PDT 24
Peak memory 206668 kb
Host smart-e04eb643-a3bc-406e-8190-af4389dd37f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427
12538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.4242712538
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2598028867
Short name T2306
Test name
Test status
Simulation time 168030590 ps
CPU time 0.78 seconds
Started Jul 20 06:26:24 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206640 kb
Host smart-630ae006-bb74-40af-8ee0-bfb2b83d72bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25980
28867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2598028867
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.2179836391
Short name T1541
Test name
Test status
Simulation time 256641887 ps
CPU time 1 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206496 kb
Host smart-4124c521-01fe-4699-b970-382f0d883fb8
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2179836391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.2179836391
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.120531119
Short name T1981
Test name
Test status
Simulation time 141042114 ps
CPU time 0.8 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:37 PM PDT 24
Peak memory 206632 kb
Host smart-d4863729-dbae-45d0-83bd-c97c135f0c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12053
1119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.120531119
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.3493521427
Short name T25
Test name
Test status
Simulation time 53004487 ps
CPU time 0.66 seconds
Started Jul 20 06:26:25 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206636 kb
Host smart-c40b6a8d-18c0-4ef8-aa11-c4db5c66d549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34935
21427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.3493521427
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.2850943496
Short name T1805
Test name
Test status
Simulation time 9332761776 ps
CPU time 21.3 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:57 PM PDT 24
Peak memory 206868 kb
Host smart-6ccfce8a-c196-4597-9622-7457e906e9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28509
43496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.2850943496
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.463282830
Short name T2005
Test name
Test status
Simulation time 173158325 ps
CPU time 0.81 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206596 kb
Host smart-1d205597-454c-410c-a7f5-d78826a166ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46328
2830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.463282830
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.959617848
Short name T2399
Test name
Test status
Simulation time 163302825 ps
CPU time 0.95 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206636 kb
Host smart-1478a526-db4c-4581-ad90-e1f8ea368b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95961
7848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.959617848
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2711319898
Short name T1840
Test name
Test status
Simulation time 230687065 ps
CPU time 0.95 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:35 PM PDT 24
Peak memory 206656 kb
Host smart-e9272de5-6d74-4336-abaa-17d4e10e8eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27113
19898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2711319898
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1826354338
Short name T2605
Test name
Test status
Simulation time 162007787 ps
CPU time 0.82 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206592 kb
Host smart-5058332f-f754-4a60-a1ae-59d8f73722f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
54338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1826354338
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.2994066595
Short name T688
Test name
Test status
Simulation time 181293502 ps
CPU time 0.83 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206632 kb
Host smart-cf3123bd-33bf-492f-848a-cd4897f27a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29940
66595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.2994066595
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.979580885
Short name T1826
Test name
Test status
Simulation time 169368470 ps
CPU time 0.82 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:26:34 PM PDT 24
Peak memory 206624 kb
Host smart-d09c9e93-9d0f-431e-8a3f-d21265a082fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97958
0885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.979580885
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.758620989
Short name T2122
Test name
Test status
Simulation time 168506744 ps
CPU time 0.84 seconds
Started Jul 20 06:26:24 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206648 kb
Host smart-95613997-779e-4d42-b859-05ac1a083058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75862
0989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.758620989
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.855243282
Short name T1701
Test name
Test status
Simulation time 225125280 ps
CPU time 0.92 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:26:33 PM PDT 24
Peak memory 206632 kb
Host smart-80b51173-6308-4121-b955-0fbca504a574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85524
3282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.855243282
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.3006615797
Short name T1178
Test name
Test status
Simulation time 3525420960 ps
CPU time 94.8 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:28:07 PM PDT 24
Peak memory 206768 kb
Host smart-dd53c3cf-5207-4f3e-9885-c4e75e1d3fec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3006615797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.3006615797
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.3989749664
Short name T727
Test name
Test status
Simulation time 187242688 ps
CPU time 0.81 seconds
Started Jul 20 06:26:29 PM PDT 24
Finished Jul 20 06:26:32 PM PDT 24
Peak memory 206656 kb
Host smart-b9faa534-3ee0-4542-a58c-9840baf47060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39897
49664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.3989749664
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3326268450
Short name T1586
Test name
Test status
Simulation time 163756366 ps
CPU time 0.84 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206700 kb
Host smart-ee6d44c1-13c0-4f0c-b71d-420c2a262f7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33262
68450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3326268450
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.3767831563
Short name T857
Test name
Test status
Simulation time 810607822 ps
CPU time 2.07 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:31 PM PDT 24
Peak memory 206724 kb
Host smart-2d94bfc0-be6b-4034-9e54-3a05fae5ce9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37678
31563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.3767831563
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.1365851961
Short name T537
Test name
Test status
Simulation time 4568887125 ps
CPU time 31.99 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206872 kb
Host smart-24f14e68-b3b8-431c-a646-f2a6afb0a79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13658
51961 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.1365851961
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.718721992
Short name T177
Test name
Test status
Simulation time 40571586 ps
CPU time 0.68 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206692 kb
Host smart-687cc0e0-d6fd-42af-8651-a30274db53dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=718721992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.718721992
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.1202805286
Short name T828
Test name
Test status
Simulation time 3390282303 ps
CPU time 4.39 seconds
Started Jul 20 06:26:35 PM PDT 24
Finished Jul 20 06:26:43 PM PDT 24
Peak memory 206712 kb
Host smart-e44e5aff-3ba0-4329-bef4-7efd3fc46e80
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1202805286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.1202805286
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.1374197785
Short name T2514
Test name
Test status
Simulation time 13347924370 ps
CPU time 14.08 seconds
Started Jul 20 06:26:33 PM PDT 24
Finished Jul 20 06:26:51 PM PDT 24
Peak memory 206828 kb
Host smart-15d04cdb-3728-4dbd-9776-29d8f0052015
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1374197785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.1374197785
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.4065905791
Short name T1759
Test name
Test status
Simulation time 23350340725 ps
CPU time 25.57 seconds
Started Jul 20 06:26:29 PM PDT 24
Finished Jul 20 06:26:57 PM PDT 24
Peak memory 206748 kb
Host smart-15391e48-90ca-4ca0-ad92-7c168da10798
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4065905791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.4065905791
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.1566928903
Short name T2628
Test name
Test status
Simulation time 176592261 ps
CPU time 0.83 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206700 kb
Host smart-695fde79-f80a-464f-b7cf-71a129077d19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15669
28903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.1566928903
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1966512946
Short name T1539
Test name
Test status
Simulation time 163328203 ps
CPU time 0.74 seconds
Started Jul 20 06:26:37 PM PDT 24
Finished Jul 20 06:26:40 PM PDT 24
Peak memory 206652 kb
Host smart-86a91b06-cc71-4352-bd09-4d98bfdc3c5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19665
12946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1966512946
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.3357528431
Short name T1944
Test name
Test status
Simulation time 417272122 ps
CPU time 1.38 seconds
Started Jul 20 06:26:24 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206632 kb
Host smart-50baa772-28cd-4419-8820-1f38e8605bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33575
28431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.3357528431
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3049348428
Short name T1383
Test name
Test status
Simulation time 666806624 ps
CPU time 1.79 seconds
Started Jul 20 06:26:33 PM PDT 24
Finished Jul 20 06:26:38 PM PDT 24
Peak memory 206704 kb
Host smart-69d87499-918d-40fc-8bf2-2569bf7d45d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30493
48428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3049348428
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.2396418676
Short name T1597
Test name
Test status
Simulation time 19988795480 ps
CPU time 35.67 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206808 kb
Host smart-df405fe0-7d66-4460-8bf5-fc105cfc6dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23964
18676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.2396418676
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.1361898586
Short name T485
Test name
Test status
Simulation time 498977716 ps
CPU time 1.54 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206672 kb
Host smart-3064518d-f199-4869-b6a8-aab514f14022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13618
98586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.1361898586
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.122734375
Short name T447
Test name
Test status
Simulation time 205017925 ps
CPU time 0.83 seconds
Started Jul 20 06:26:28 PM PDT 24
Finished Jul 20 06:26:31 PM PDT 24
Peak memory 206656 kb
Host smart-d150dd2d-7634-49a4-bfd7-36007f7cdaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12273
4375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.122734375
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.3415397583
Short name T2329
Test name
Test status
Simulation time 38331694 ps
CPU time 0.63 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206556 kb
Host smart-6c34cf04-aa87-4940-ba97-18d03a50cd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34153
97583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.3415397583
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.540258641
Short name T535
Test name
Test status
Simulation time 803313382 ps
CPU time 1.95 seconds
Started Jul 20 06:26:25 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206728 kb
Host smart-e05b56f6-301c-461c-9827-716d97cdf893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54025
8641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.540258641
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.165610509
Short name T2678
Test name
Test status
Simulation time 320286727 ps
CPU time 1.77 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:37 PM PDT 24
Peak memory 206720 kb
Host smart-b4f79077-21c7-46dc-b8b8-e7118cd4b1c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16561
0509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.165610509
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2235508392
Short name T2137
Test name
Test status
Simulation time 177243551 ps
CPU time 0.78 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:26:34 PM PDT 24
Peak memory 206652 kb
Host smart-c93d647a-b323-420f-a5ca-6be15f7a7cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22355
08392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2235508392
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.3718436716
Short name T884
Test name
Test status
Simulation time 156358305 ps
CPU time 0.8 seconds
Started Jul 20 06:26:24 PM PDT 24
Finished Jul 20 06:26:26 PM PDT 24
Peak memory 206660 kb
Host smart-7cffd654-0379-4b12-a3c0-8f3f2035998c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37184
36716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.3718436716
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.3310448815
Short name T1514
Test name
Test status
Simulation time 229497280 ps
CPU time 0.9 seconds
Started Jul 20 06:26:37 PM PDT 24
Finished Jul 20 06:26:40 PM PDT 24
Peak memory 206648 kb
Host smart-569f99d2-17c7-4524-9ea0-574e138f2023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33104
48815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.3310448815
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2990402382
Short name T1560
Test name
Test status
Simulation time 200400127 ps
CPU time 0.91 seconds
Started Jul 20 06:26:24 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206664 kb
Host smart-3f1f7953-37a3-4119-9d7d-431014c5b9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29904
02382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2990402382
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.109194481
Short name T1355
Test name
Test status
Simulation time 23311890340 ps
CPU time 23.1 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:53 PM PDT 24
Peak memory 206760 kb
Host smart-6b21100d-33d0-4264-97b9-6030400a74f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10919
4481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.109194481
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2660384022
Short name T2627
Test name
Test status
Simulation time 3339881412 ps
CPU time 4.23 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206572 kb
Host smart-78be5484-f41b-4ab7-9685-2dd25048363b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26603
84022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2660384022
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2770051369
Short name T383
Test name
Test status
Simulation time 8693880612 ps
CPU time 62.44 seconds
Started Jul 20 06:26:24 PM PDT 24
Finished Jul 20 06:27:28 PM PDT 24
Peak memory 206900 kb
Host smart-361b3dcf-89cc-4113-9bf8-0423c9ecb6a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27700
51369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2770051369
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.539991949
Short name T1261
Test name
Test status
Simulation time 3040580816 ps
CPU time 85.49 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:28:02 PM PDT 24
Peak memory 206816 kb
Host smart-103785ba-27f7-4ad1-bd8e-7f4729749a64
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=539991949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.539991949
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.3681098098
Short name T322
Test name
Test status
Simulation time 235876630 ps
CPU time 0.98 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206648 kb
Host smart-51cade93-2a40-4cc5-9213-d6ac02466051
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3681098098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.3681098098
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2240387741
Short name T328
Test name
Test status
Simulation time 185635932 ps
CPU time 0.86 seconds
Started Jul 20 06:26:29 PM PDT 24
Finished Jul 20 06:26:32 PM PDT 24
Peak memory 206620 kb
Host smart-2b4061df-6816-4d7e-84ba-1053b400c67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22403
87741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2240387741
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2006606341
Short name T428
Test name
Test status
Simulation time 3487355544 ps
CPU time 32.84 seconds
Started Jul 20 06:26:24 PM PDT 24
Finished Jul 20 06:26:59 PM PDT 24
Peak memory 206840 kb
Host smart-51c9dead-76ab-415a-a605-fd597dc406c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20066
06341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2006606341
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.394568110
Short name T1027
Test name
Test status
Simulation time 4626525090 ps
CPU time 129.45 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:28:41 PM PDT 24
Peak memory 206852 kb
Host smart-e9f61ac9-2175-46c8-8c54-aaea9a7604ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=394568110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.394568110
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.2791495337
Short name T814
Test name
Test status
Simulation time 152371238 ps
CPU time 0.86 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206656 kb
Host smart-9a67aaf1-75b2-4d8a-bcc9-574310312437
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2791495337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.2791495337
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.30900176
Short name T2091
Test name
Test status
Simulation time 188914166 ps
CPU time 0.8 seconds
Started Jul 20 06:26:29 PM PDT 24
Finished Jul 20 06:26:32 PM PDT 24
Peak memory 206640 kb
Host smart-295d563f-25a2-4e46-8388-1ac455f8fa60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30900
176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.30900176
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.3862394111
Short name T136
Test name
Test status
Simulation time 224635904 ps
CPU time 0.89 seconds
Started Jul 20 06:26:23 PM PDT 24
Finished Jul 20 06:26:26 PM PDT 24
Peak memory 206656 kb
Host smart-20130d78-b3cd-4d10-9fa7-d37e0c4b6d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38623
94111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.3862394111
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.1587312637
Short name T1083
Test name
Test status
Simulation time 186289518 ps
CPU time 0.86 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206652 kb
Host smart-15c9a838-7318-4e33-b2f9-9acc6c8680a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
12637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.1587312637
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2598368868
Short name T999
Test name
Test status
Simulation time 166310758 ps
CPU time 0.84 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206656 kb
Host smart-2ca6032c-a0c3-4726-83bf-cb86505afe1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25983
68868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2598368868
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.176836320
Short name T2097
Test name
Test status
Simulation time 187348336 ps
CPU time 0.89 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206540 kb
Host smart-49b31565-edbf-4fdc-a49b-fa3a7ade2fa2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17683
6320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.176836320
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3137957761
Short name T906
Test name
Test status
Simulation time 184876907 ps
CPU time 0.84 seconds
Started Jul 20 06:26:28 PM PDT 24
Finished Jul 20 06:26:31 PM PDT 24
Peak memory 206664 kb
Host smart-d39216b7-a2ea-4823-814a-57ff2df9510a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31379
57761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3137957761
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.297441791
Short name T467
Test name
Test status
Simulation time 220299653 ps
CPU time 0.92 seconds
Started Jul 20 06:26:25 PM PDT 24
Finished Jul 20 06:26:27 PM PDT 24
Peak memory 206664 kb
Host smart-a476d252-bc48-4976-9162-1f0349cb27ba
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=297441791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.297441791
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.2647802943
Short name T2625
Test name
Test status
Simulation time 174697801 ps
CPU time 0.77 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206652 kb
Host smart-b2c1f48d-8c4d-41e5-a1fe-947dd2522a46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26478
02943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.2647802943
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3105094819
Short name T1866
Test name
Test status
Simulation time 81424623 ps
CPU time 0.67 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206632 kb
Host smart-0630062d-44e9-4d12-affc-a882842e3f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31050
94819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3105094819
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.676995169
Short name T243
Test name
Test status
Simulation time 15731631089 ps
CPU time 33.28 seconds
Started Jul 20 06:26:36 PM PDT 24
Finished Jul 20 06:27:13 PM PDT 24
Peak memory 206956 kb
Host smart-730eb45e-14a6-486c-aeec-425dfa3f1575
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67699
5169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.676995169
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.496303667
Short name T1069
Test name
Test status
Simulation time 178922618 ps
CPU time 0.83 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206660 kb
Host smart-6c363cc3-1ceb-4280-be8a-4571c959a182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49630
3667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.496303667
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.1282473211
Short name T1904
Test name
Test status
Simulation time 208997750 ps
CPU time 0.85 seconds
Started Jul 20 06:26:35 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206648 kb
Host smart-70dfedcd-124a-41cc-a117-e5b038875813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12824
73211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.1282473211
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2018169396
Short name T336
Test name
Test status
Simulation time 177193808 ps
CPU time 0.8 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:26:33 PM PDT 24
Peak memory 206652 kb
Host smart-a1a1af5b-27dd-47c9-998b-321d1287a8d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20181
69396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2018169396
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2503485129
Short name T1336
Test name
Test status
Simulation time 208572499 ps
CPU time 0.95 seconds
Started Jul 20 06:26:38 PM PDT 24
Finished Jul 20 06:26:41 PM PDT 24
Peak memory 206648 kb
Host smart-7995824b-50c9-4de4-a80b-bd6363d452b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034
85129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2503485129
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.2276529454
Short name T2551
Test name
Test status
Simulation time 163518546 ps
CPU time 0.88 seconds
Started Jul 20 06:26:28 PM PDT 24
Finished Jul 20 06:26:32 PM PDT 24
Peak memory 206648 kb
Host smart-9e15d9e6-0eff-4cbb-a7a4-1cad39907922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22765
29454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.2276529454
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.677781183
Short name T748
Test name
Test status
Simulation time 146663460 ps
CPU time 0.76 seconds
Started Jul 20 06:26:26 PM PDT 24
Finished Jul 20 06:26:29 PM PDT 24
Peak memory 206652 kb
Host smart-310f5fc5-2116-4174-883d-cf7c6b1af30e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67778
1183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.677781183
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.3509778834
Short name T720
Test name
Test status
Simulation time 151057310 ps
CPU time 0.8 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:26:30 PM PDT 24
Peak memory 206664 kb
Host smart-1d396d4b-2d00-4138-a022-19363c873ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35097
78834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.3509778834
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1190901911
Short name T698
Test name
Test status
Simulation time 249281602 ps
CPU time 1.03 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:26:33 PM PDT 24
Peak memory 206648 kb
Host smart-eb03fd01-f5bb-4ec1-8271-a8f981159df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909
01911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1190901911
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.318635084
Short name T2146
Test name
Test status
Simulation time 4111310289 ps
CPU time 37.16 seconds
Started Jul 20 06:26:27 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206920 kb
Host smart-409fc5d6-f3f2-4836-b237-36fc0dd2fec3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=318635084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.318635084
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3680543739
Short name T607
Test name
Test status
Simulation time 159764070 ps
CPU time 0.84 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:34 PM PDT 24
Peak memory 206636 kb
Host smart-f7dc2331-342a-4fc9-9665-992aff90da82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36805
43739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3680543739
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.380402294
Short name T1765
Test name
Test status
Simulation time 195104925 ps
CPU time 0.81 seconds
Started Jul 20 06:26:45 PM PDT 24
Finished Jul 20 06:26:48 PM PDT 24
Peak memory 206628 kb
Host smart-810f57af-36a7-488e-b7bb-c40a4ea01059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38040
2294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.380402294
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1955163852
Short name T2040
Test name
Test status
Simulation time 961712509 ps
CPU time 2.06 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:37 PM PDT 24
Peak memory 206784 kb
Host smart-dbefe053-52a3-49c9-b380-04a366e10bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19551
63852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1955163852
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.1885886774
Short name T753
Test name
Test status
Simulation time 3802559104 ps
CPU time 28.28 seconds
Started Jul 20 06:26:46 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206900 kb
Host smart-db0e432a-64b2-4e1c-a7bb-8d131e5b1072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18858
86774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.1885886774
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3628770582
Short name T1945
Test name
Test status
Simulation time 44885359 ps
CPU time 0.72 seconds
Started Jul 20 06:26:41 PM PDT 24
Finished Jul 20 06:26:43 PM PDT 24
Peak memory 206688 kb
Host smart-423d0346-88d4-4ccd-92a0-076854fa5620
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3628770582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3628770582
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.3003070635
Short name T2057
Test name
Test status
Simulation time 4061251311 ps
CPU time 4.66 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206872 kb
Host smart-a1d0041a-c8a6-4add-9b61-0bd8bb1418ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3003070635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.3003070635
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.1085944630
Short name T583
Test name
Test status
Simulation time 13318298804 ps
CPU time 14.6 seconds
Started Jul 20 06:26:45 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206940 kb
Host smart-bba2f464-699f-4052-964a-9b448673459f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1085944630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.1085944630
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.563098027
Short name T1564
Test name
Test status
Simulation time 23341844895 ps
CPU time 21.72 seconds
Started Jul 20 06:26:34 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206896 kb
Host smart-1916fe2a-caae-4a4d-a73f-db4ee052394a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=563098027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.563098027
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.4198838299
Short name T2049
Test name
Test status
Simulation time 159202723 ps
CPU time 0.81 seconds
Started Jul 20 06:26:40 PM PDT 24
Finished Jul 20 06:26:42 PM PDT 24
Peak memory 206664 kb
Host smart-96f6099f-0633-420d-8563-33b919d34830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41988
38299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.4198838299
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3551978891
Short name T1995
Test name
Test status
Simulation time 209450196 ps
CPU time 0.85 seconds
Started Jul 20 06:26:36 PM PDT 24
Finished Jul 20 06:26:40 PM PDT 24
Peak memory 206660 kb
Host smart-28fcb51f-5dd8-4a81-9f0c-f2cb731d871c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35519
78891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3551978891
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2651956670
Short name T1625
Test name
Test status
Simulation time 308091004 ps
CPU time 1.15 seconds
Started Jul 20 06:26:37 PM PDT 24
Finished Jul 20 06:26:41 PM PDT 24
Peak memory 206652 kb
Host smart-e41abc7f-1ef3-4f3a-a8ab-ebab6f5e5af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26519
56670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2651956670
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1587379972
Short name T813
Test name
Test status
Simulation time 341551016 ps
CPU time 1.01 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:35 PM PDT 24
Peak memory 206660 kb
Host smart-394216cd-f01c-4245-8fd9-82e97a8d13aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15873
79972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1587379972
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.27699277
Short name T2620
Test name
Test status
Simulation time 12098554469 ps
CPU time 23.3 seconds
Started Jul 20 06:26:43 PM PDT 24
Finished Jul 20 06:27:08 PM PDT 24
Peak memory 206920 kb
Host smart-2b9fe0c8-e17b-4fbe-981d-4ba225d6009e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27699
277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.27699277
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3294605454
Short name T2135
Test name
Test status
Simulation time 425258417 ps
CPU time 1.31 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:37 PM PDT 24
Peak memory 206648 kb
Host smart-5c605e6a-f436-47a3-a5e5-b4ae14205883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32946
05454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3294605454
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.3920712993
Short name T1315
Test name
Test status
Simulation time 181346091 ps
CPU time 0.77 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:37 PM PDT 24
Peak memory 206640 kb
Host smart-b57a74da-ec25-462f-a882-8978a1102502
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39207
12993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.3920712993
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1615532834
Short name T820
Test name
Test status
Simulation time 35668653 ps
CPU time 0.64 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206652 kb
Host smart-3976a12d-f938-4bd1-bf4a-3af45da6ac3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16155
32834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1615532834
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1228078614
Short name T1066
Test name
Test status
Simulation time 1015597312 ps
CPU time 2.2 seconds
Started Jul 20 06:26:43 PM PDT 24
Finished Jul 20 06:26:47 PM PDT 24
Peak memory 206776 kb
Host smart-75d3d819-f56c-4b58-9dc4-2305a21a3b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12280
78614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1228078614
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2784081517
Short name T1546
Test name
Test status
Simulation time 207103441 ps
CPU time 1.21 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:35 PM PDT 24
Peak memory 206780 kb
Host smart-6459876a-0594-4cd8-ac9e-fe12777673fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27840
81517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2784081517
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.1915407609
Short name T2216
Test name
Test status
Simulation time 216688316 ps
CPU time 0.87 seconds
Started Jul 20 06:26:35 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206648 kb
Host smart-29a88a7d-aaa2-4633-9689-5070585b2f08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19154
07609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.1915407609
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.455008291
Short name T2576
Test name
Test status
Simulation time 140753380 ps
CPU time 0.81 seconds
Started Jul 20 06:26:34 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206648 kb
Host smart-7acb0789-9aaa-48e3-b804-b5948497d663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45500
8291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.455008291
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.3151305401
Short name T422
Test name
Test status
Simulation time 185754114 ps
CPU time 0.85 seconds
Started Jul 20 06:26:44 PM PDT 24
Finished Jul 20 06:26:47 PM PDT 24
Peak memory 206656 kb
Host smart-3c67c68f-a0f6-4f38-b4dd-a6bbf00ce348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31513
05401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.3151305401
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_invalid_sync.3579452246
Short name T699
Test name
Test status
Simulation time 5348164812 ps
CPU time 39.88 seconds
Started Jul 20 06:26:36 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206932 kb
Host smart-244218a8-f1af-46be-b733-a91271064e49
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3579452246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_invalid_sync.3579452246
Directory /workspace/44.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.3311052922
Short name T1520
Test name
Test status
Simulation time 7849267484 ps
CPU time 23.38 seconds
Started Jul 20 06:26:34 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206848 kb
Host smart-b0bb0111-6819-4c4e-8f67-0521d08b5a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33110
52922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.3311052922
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.30170017
Short name T1642
Test name
Test status
Simulation time 210262320 ps
CPU time 0.9 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:26:34 PM PDT 24
Peak memory 206636 kb
Host smart-a7b00bf6-e063-479f-99d5-214fee528a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30170
017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.30170017
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.555603427
Short name T181
Test name
Test status
Simulation time 23317319169 ps
CPU time 24.18 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 206760 kb
Host smart-2cac46c0-6edd-4ace-8c00-c952264998f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55560
3427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.555603427
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1869744331
Short name T382
Test name
Test status
Simulation time 3326659246 ps
CPU time 4.04 seconds
Started Jul 20 06:26:41 PM PDT 24
Finished Jul 20 06:26:47 PM PDT 24
Peak memory 206688 kb
Host smart-9954e0da-8808-45f6-9890-2fa969e76fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18697
44331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1869744331
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.331016853
Short name T940
Test name
Test status
Simulation time 5761568082 ps
CPU time 54.19 seconds
Started Jul 20 06:26:46 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 206924 kb
Host smart-1c4be16a-22e2-4051-b6b1-d9e97065c5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33101
6853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.331016853
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.2549044089
Short name T1362
Test name
Test status
Simulation time 7335381044 ps
CPU time 67.99 seconds
Started Jul 20 06:26:30 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 206844 kb
Host smart-90755c92-95e1-4fce-b728-fc17075e3770
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2549044089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.2549044089
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.2924801781
Short name T1296
Test name
Test status
Simulation time 285979984 ps
CPU time 0.93 seconds
Started Jul 20 06:26:36 PM PDT 24
Finished Jul 20 06:26:44 PM PDT 24
Peak memory 206656 kb
Host smart-74b7c38d-0e66-4a48-969d-af5837ef3e3b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2924801781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.2924801781
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.3990017078
Short name T563
Test name
Test status
Simulation time 204711923 ps
CPU time 0.85 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206624 kb
Host smart-38f824e9-f91b-4f73-884c-36d1c38cbdff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39900
17078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.3990017078
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.1751348903
Short name T1550
Test name
Test status
Simulation time 5885636554 ps
CPU time 57 seconds
Started Jul 20 06:26:36 PM PDT 24
Finished Jul 20 06:27:36 PM PDT 24
Peak memory 206912 kb
Host smart-fc3acc34-abe4-495e-b4f4-18fba9d1d436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17513
48903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.1751348903
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1141487133
Short name T1028
Test name
Test status
Simulation time 6052859752 ps
CPU time 156.86 seconds
Started Jul 20 06:26:42 PM PDT 24
Finished Jul 20 06:29:21 PM PDT 24
Peak memory 206852 kb
Host smart-d94bf58c-3fed-484b-89f1-8760bfa701ff
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1141487133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1141487133
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.2927137587
Short name T1367
Test name
Test status
Simulation time 155247446 ps
CPU time 0.77 seconds
Started Jul 20 06:26:31 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206652 kb
Host smart-ce1cf420-b638-4803-bdcb-4336d998432a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2927137587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.2927137587
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.2431723525
Short name T1851
Test name
Test status
Simulation time 180825516 ps
CPU time 0.85 seconds
Started Jul 20 06:26:35 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206648 kb
Host smart-84a476ac-0fa0-4d3a-bb34-cdb8932d3b8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24317
23525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.2431723525
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.3184337335
Short name T144
Test name
Test status
Simulation time 178469751 ps
CPU time 0.85 seconds
Started Jul 20 06:26:39 PM PDT 24
Finished Jul 20 06:26:41 PM PDT 24
Peak memory 206660 kb
Host smart-c1983fe7-32a7-49bc-8402-059cfc600393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31843
37335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.3184337335
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.1554244074
Short name T2492
Test name
Test status
Simulation time 184901056 ps
CPU time 0.86 seconds
Started Jul 20 06:26:33 PM PDT 24
Finished Jul 20 06:26:38 PM PDT 24
Peak memory 206652 kb
Host smart-1d9de1b6-a844-4b5c-8dd7-4ccf446c94a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15542
44074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.1554244074
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.162946290
Short name T2128
Test name
Test status
Simulation time 181505039 ps
CPU time 0.81 seconds
Started Jul 20 06:26:35 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206652 kb
Host smart-c8f75b74-b359-41c5-a8a8-1341d4572ab8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16294
6290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.162946290
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3498271782
Short name T1073
Test name
Test status
Simulation time 161029762 ps
CPU time 0.81 seconds
Started Jul 20 06:26:34 PM PDT 24
Finished Jul 20 06:26:38 PM PDT 24
Peak memory 206656 kb
Host smart-e20cb8e3-5728-48da-b171-3a2029c2ab85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34982
71782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3498271782
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2053892848
Short name T2342
Test name
Test status
Simulation time 164892995 ps
CPU time 0.76 seconds
Started Jul 20 06:26:34 PM PDT 24
Finished Jul 20 06:26:38 PM PDT 24
Peak memory 206544 kb
Host smart-bfa4cd1b-38b5-4e14-976d-ff960e7f36ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20538
92848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2053892848
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.3742261073
Short name T2406
Test name
Test status
Simulation time 183082242 ps
CPU time 0.85 seconds
Started Jul 20 06:26:34 PM PDT 24
Finished Jul 20 06:26:39 PM PDT 24
Peak memory 206656 kb
Host smart-da6d7934-6776-4e41-b69c-b99207bfb43f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3742261073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.3742261073
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1848369582
Short name T183
Test name
Test status
Simulation time 169917597 ps
CPU time 0.8 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:36 PM PDT 24
Peak memory 206644 kb
Host smart-d7281e17-b19c-4146-a4ec-c87f8ab1c674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18483
69582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1848369582
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.2587930992
Short name T2698
Test name
Test status
Simulation time 41077991 ps
CPU time 0.68 seconds
Started Jul 20 06:26:32 PM PDT 24
Finished Jul 20 06:26:37 PM PDT 24
Peak memory 206660 kb
Host smart-2e93300b-65d8-4ecf-8e57-0f093bbea7b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25879
30992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.2587930992
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.729346465
Short name T1716
Test name
Test status
Simulation time 9439695987 ps
CPU time 21.75 seconds
Started Jul 20 06:26:44 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206912 kb
Host smart-02bbc0f1-bea0-4e12-bab5-bac9cd4aa239
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72934
6465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.729346465
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.2504022678
Short name T1157
Test name
Test status
Simulation time 150949116 ps
CPU time 0.78 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:26:49 PM PDT 24
Peak memory 206652 kb
Host smart-db5292fa-b2bf-4a55-af09-d8a583ce3fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25040
22678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.2504022678
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1461649627
Short name T1579
Test name
Test status
Simulation time 175913819 ps
CPU time 0.88 seconds
Started Jul 20 06:26:44 PM PDT 24
Finished Jul 20 06:26:46 PM PDT 24
Peak memory 206636 kb
Host smart-ebaf78f4-5c23-48d5-867a-20cccf5372f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14616
49627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1461649627
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.620909571
Short name T955
Test name
Test status
Simulation time 209105047 ps
CPU time 0.89 seconds
Started Jul 20 06:26:48 PM PDT 24
Finished Jul 20 06:26:50 PM PDT 24
Peak memory 206648 kb
Host smart-93f90c4a-c054-46f1-bb97-67b9a5ffe383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62090
9571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.620909571
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1453626014
Short name T1526
Test name
Test status
Simulation time 176641810 ps
CPU time 0.92 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:57 PM PDT 24
Peak memory 206648 kb
Host smart-d93dce42-8a82-463e-a90c-aacf5993e962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14536
26014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1453626014
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.3118407390
Short name T2674
Test name
Test status
Simulation time 170444567 ps
CPU time 0.83 seconds
Started Jul 20 06:26:45 PM PDT 24
Finished Jul 20 06:26:47 PM PDT 24
Peak memory 206632 kb
Host smart-2e4fbdf1-603a-4ed2-9267-e963423e7fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31184
07390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.3118407390
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.3677098344
Short name T1729
Test name
Test status
Simulation time 155031750 ps
CPU time 0.78 seconds
Started Jul 20 06:26:48 PM PDT 24
Finished Jul 20 06:26:50 PM PDT 24
Peak memory 206656 kb
Host smart-859ae70e-b4c1-437f-be42-5456060d2391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36770
98344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.3677098344
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.73077796
Short name T2107
Test name
Test status
Simulation time 150044317 ps
CPU time 0.8 seconds
Started Jul 20 06:26:49 PM PDT 24
Finished Jul 20 06:26:51 PM PDT 24
Peak memory 206656 kb
Host smart-50d41ccb-ad95-46f6-bd2e-8b27c792ae34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73077
796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.73077796
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.258167776
Short name T530
Test name
Test status
Simulation time 259373245 ps
CPU time 0.95 seconds
Started Jul 20 06:26:41 PM PDT 24
Finished Jul 20 06:26:44 PM PDT 24
Peak memory 206640 kb
Host smart-02593dc2-d14b-4a3f-b486-61bd20ffdd7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25816
7776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.258167776
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1608890515
Short name T798
Test name
Test status
Simulation time 3653808094 ps
CPU time 33.75 seconds
Started Jul 20 06:26:50 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206812 kb
Host smart-1bdb7f05-2ff7-49d3-a912-476dd62aa494
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1608890515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1608890515
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.1497035115
Short name T2073
Test name
Test status
Simulation time 219365457 ps
CPU time 0.82 seconds
Started Jul 20 06:26:48 PM PDT 24
Finished Jul 20 06:26:50 PM PDT 24
Peak memory 206624 kb
Host smart-c92a6727-e71f-4e2f-8ce5-0ea404545c7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14970
35115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.1497035115
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.1119431963
Short name T638
Test name
Test status
Simulation time 176353051 ps
CPU time 0.77 seconds
Started Jul 20 06:26:43 PM PDT 24
Finished Jul 20 06:26:45 PM PDT 24
Peak memory 206656 kb
Host smart-fdfcab18-7aa8-4a77-a199-08f8b021c32d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11194
31963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.1119431963
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2857429396
Short name T493
Test name
Test status
Simulation time 314670741 ps
CPU time 1.01 seconds
Started Jul 20 06:26:43 PM PDT 24
Finished Jul 20 06:26:46 PM PDT 24
Peak memory 206656 kb
Host smart-56a57183-56d3-45b6-bdc7-a1cdfa524e53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28574
29396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2857429396
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.3713802310
Short name T1943
Test name
Test status
Simulation time 4274228830 ps
CPU time 37.78 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:27:26 PM PDT 24
Peak memory 206860 kb
Host smart-1bf77b6e-9089-499c-bdf7-d2aca7199907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37138
02310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.3713802310
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3602403300
Short name T912
Test name
Test status
Simulation time 63594059 ps
CPU time 0.65 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:05 PM PDT 24
Peak memory 206716 kb
Host smart-6b06be3b-2902-471e-be57-a1b3906b15a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3602403300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3602403300
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.732775249
Short name T642
Test name
Test status
Simulation time 3932444803 ps
CPU time 5.52 seconds
Started Jul 20 06:26:41 PM PDT 24
Finished Jul 20 06:26:49 PM PDT 24
Peak memory 206692 kb
Host smart-c116fa1d-6148-421b-ba43-9587b0796b62
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=732775249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.732775249
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3002067185
Short name T914
Test name
Test status
Simulation time 13333618012 ps
CPU time 13.05 seconds
Started Jul 20 06:26:41 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206788 kb
Host smart-28f9e7fb-0392-4c11-a014-7ce7b96dc6cd
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3002067185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3002067185
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.639778130
Short name T1477
Test name
Test status
Simulation time 23303505260 ps
CPU time 21.4 seconds
Started Jul 20 06:26:44 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206876 kb
Host smart-f42f8fa0-28d6-4aba-bdd8-10bf6da76b81
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=639778130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.639778130
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.1338537065
Short name T2247
Test name
Test status
Simulation time 151473549 ps
CPU time 0.8 seconds
Started Jul 20 06:26:49 PM PDT 24
Finished Jul 20 06:26:52 PM PDT 24
Peak memory 206628 kb
Host smart-d23b5453-d81d-4bc2-9f22-79bf6b563ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
37065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.1338537065
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3340529501
Short name T2596
Test name
Test status
Simulation time 149785022 ps
CPU time 0.79 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:26:49 PM PDT 24
Peak memory 206628 kb
Host smart-1ca86d5f-e708-4216-9275-9081ae6adc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33405
29501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3340529501
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.940373105
Short name T1599
Test name
Test status
Simulation time 250600309 ps
CPU time 1.05 seconds
Started Jul 20 06:26:53 PM PDT 24
Finished Jul 20 06:26:55 PM PDT 24
Peak memory 206664 kb
Host smart-212a714f-f004-4842-b491-129010a3fc13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94037
3105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.940373105
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.3282948639
Short name T697
Test name
Test status
Simulation time 758441085 ps
CPU time 1.9 seconds
Started Jul 20 06:26:49 PM PDT 24
Finished Jul 20 06:26:53 PM PDT 24
Peak memory 206780 kb
Host smart-f29a0ed3-5cb9-4179-9a5e-3a6b41791c99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
48639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.3282948639
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.117812912
Short name T2315
Test name
Test status
Simulation time 12676257035 ps
CPU time 24.37 seconds
Started Jul 20 06:26:42 PM PDT 24
Finished Jul 20 06:27:08 PM PDT 24
Peak memory 206868 kb
Host smart-82a7d4f5-104f-4f89-864b-75af4dcc94b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11781
2912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.117812912
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.3498685055
Short name T2043
Test name
Test status
Simulation time 420595203 ps
CPU time 1.21 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:26:50 PM PDT 24
Peak memory 206652 kb
Host smart-3ca91e4c-14b5-493d-9b60-efba7eb9908a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34986
85055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.3498685055
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.380469107
Short name T2289
Test name
Test status
Simulation time 217331059 ps
CPU time 0.84 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:26:49 PM PDT 24
Peak memory 206656 kb
Host smart-8954c8fc-8688-4aee-b02b-6c22d168566d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38046
9107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.380469107
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.1309864156
Short name T2512
Test name
Test status
Simulation time 36805940 ps
CPU time 0.68 seconds
Started Jul 20 06:26:48 PM PDT 24
Finished Jul 20 06:26:50 PM PDT 24
Peak memory 206616 kb
Host smart-0fb9a50a-b00f-42a0-a40b-99ea85ba5752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13098
64156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.1309864156
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3958558923
Short name T2460
Test name
Test status
Simulation time 832316685 ps
CPU time 2 seconds
Started Jul 20 06:26:43 PM PDT 24
Finished Jul 20 06:26:47 PM PDT 24
Peak memory 206788 kb
Host smart-fae749be-99ff-4472-956e-979abceeccd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39585
58923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3958558923
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.1714127806
Short name T2086
Test name
Test status
Simulation time 236305991 ps
CPU time 2.22 seconds
Started Jul 20 06:26:42 PM PDT 24
Finished Jul 20 06:26:46 PM PDT 24
Peak memory 206736 kb
Host smart-9d934b37-81b0-4377-8282-6ad6da0c1f7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17141
27806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.1714127806
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.556818558
Short name T658
Test name
Test status
Simulation time 229902794 ps
CPU time 0.85 seconds
Started Jul 20 06:26:46 PM PDT 24
Finished Jul 20 06:26:48 PM PDT 24
Peak memory 206644 kb
Host smart-c9e32fae-339f-439f-a55b-fdf3812d8137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55681
8558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.556818558
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.1857711203
Short name T751
Test name
Test status
Simulation time 178323962 ps
CPU time 0.78 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:56 PM PDT 24
Peak memory 206652 kb
Host smart-21ba120a-05b9-453c-a687-73671f0b07e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18577
11203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.1857711203
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2640705323
Short name T2131
Test name
Test status
Simulation time 249988456 ps
CPU time 1.01 seconds
Started Jul 20 06:26:50 PM PDT 24
Finished Jul 20 06:26:52 PM PDT 24
Peak memory 206648 kb
Host smart-47b8ee69-6f4c-4e4a-9d97-02b2da51a671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26407
05323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2640705323
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.105025203
Short name T1698
Test name
Test status
Simulation time 11630305039 ps
CPU time 47.28 seconds
Started Jul 20 06:26:45 PM PDT 24
Finished Jul 20 06:27:33 PM PDT 24
Peak memory 206928 kb
Host smart-935b2e4f-4f11-4ab4-8908-67bd751a350b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502
5203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.105025203
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2843103101
Short name T1082
Test name
Test status
Simulation time 218637123 ps
CPU time 0.87 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:56 PM PDT 24
Peak memory 206628 kb
Host smart-fdcf0027-3ac5-450d-828c-8fad0c234137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28431
03101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2843103101
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.2563805925
Short name T2735
Test name
Test status
Simulation time 23346098457 ps
CPU time 27.89 seconds
Started Jul 20 06:26:48 PM PDT 24
Finished Jul 20 06:27:18 PM PDT 24
Peak memory 206784 kb
Host smart-2e7f181a-eb05-4624-8e4e-46a5a995e9d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25638
05925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.2563805925
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.4089667501
Short name T2738
Test name
Test status
Simulation time 3314652614 ps
CPU time 3.81 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:26:52 PM PDT 24
Peak memory 206720 kb
Host smart-e16d5680-943f-48f5-81b6-34e49a5285b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40896
67501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.4089667501
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3178843654
Short name T2631
Test name
Test status
Simulation time 14366486264 ps
CPU time 404.04 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:33:33 PM PDT 24
Peak memory 206952 kb
Host smart-59cc6f86-57b3-4e9e-b5cf-f7c7b6bc7632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31788
43654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3178843654
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2024949854
Short name T1140
Test name
Test status
Simulation time 8213165835 ps
CPU time 232.85 seconds
Started Jul 20 06:26:47 PM PDT 24
Finished Jul 20 06:30:42 PM PDT 24
Peak memory 206848 kb
Host smart-ee9ee8e1-e040-4ff0-903a-08b02c6d3c47
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2024949854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2024949854
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.2535638283
Short name T558
Test name
Test status
Simulation time 288220264 ps
CPU time 0.95 seconds
Started Jul 20 06:26:56 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 206628 kb
Host smart-099b8415-1d11-48a7-a141-a4259192abb4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2535638283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.2535638283
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.132004937
Short name T1228
Test name
Test status
Simulation time 195424860 ps
CPU time 0.85 seconds
Started Jul 20 06:26:50 PM PDT 24
Finished Jul 20 06:26:52 PM PDT 24
Peak memory 206592 kb
Host smart-9640a8c8-dca5-4a39-ad38-4292cc2bded1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13200
4937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.132004937
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.904978127
Short name T2243
Test name
Test status
Simulation time 5635736832 ps
CPU time 156.79 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:29:38 PM PDT 24
Peak memory 206568 kb
Host smart-73f8b554-47d6-45db-a684-a7141c7aad1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90497
8127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.904978127
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.53159319
Short name T1192
Test name
Test status
Simulation time 6917410038 ps
CPU time 50.19 seconds
Started Jul 20 06:26:51 PM PDT 24
Finished Jul 20 06:27:42 PM PDT 24
Peak memory 206912 kb
Host smart-c033284a-c3c4-44ee-aed4-2d088f9d478a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=53159319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.53159319
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.1786812821
Short name T2402
Test name
Test status
Simulation time 153539341 ps
CPU time 0.8 seconds
Started Jul 20 06:26:56 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 206660 kb
Host smart-e4465c6e-e9ab-4f3b-818a-52710fb51376
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1786812821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.1786812821
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.2033829297
Short name T1959
Test name
Test status
Simulation time 141901263 ps
CPU time 0.74 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206640 kb
Host smart-b626869d-3920-414d-9110-d081ea5a18a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20338
29297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.2033829297
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1171123291
Short name T137
Test name
Test status
Simulation time 205728488 ps
CPU time 0.9 seconds
Started Jul 20 06:26:51 PM PDT 24
Finished Jul 20 06:26:53 PM PDT 24
Peak memory 206652 kb
Host smart-99dbbcf5-c1e7-43c5-b715-698f079d174b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
23291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1171123291
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.2238572116
Short name T1459
Test name
Test status
Simulation time 200471595 ps
CPU time 0.88 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:26:59 PM PDT 24
Peak memory 206656 kb
Host smart-b2205bda-bf15-4dfd-a72d-76c05fd4e9f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22385
72116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.2238572116
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.4150959718
Short name T1556
Test name
Test status
Simulation time 173419626 ps
CPU time 0.8 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:02 PM PDT 24
Peak memory 206668 kb
Host smart-148ebf8a-b5a7-44e9-9a00-0646b428a7ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
59718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.4150959718
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.3895458933
Short name T2273
Test name
Test status
Simulation time 181705395 ps
CPU time 0.82 seconds
Started Jul 20 06:26:56 PM PDT 24
Finished Jul 20 06:26:57 PM PDT 24
Peak memory 206628 kb
Host smart-11152fdd-62aa-42c9-a1a9-c5eb8803f3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38954
58933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.3895458933
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3927092427
Short name T441
Test name
Test status
Simulation time 166481442 ps
CPU time 0.81 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206656 kb
Host smart-728c4961-e7f4-490d-9d78-1a52f57e652d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39270
92427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3927092427
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.2359575767
Short name T1311
Test name
Test status
Simulation time 227564057 ps
CPU time 0.97 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:26:59 PM PDT 24
Peak memory 206640 kb
Host smart-6d5b7547-6835-4203-aeae-989c75d6df17
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2359575767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.2359575767
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2575479852
Short name T2704
Test name
Test status
Simulation time 143558904 ps
CPU time 0.79 seconds
Started Jul 20 06:26:54 PM PDT 24
Finished Jul 20 06:26:55 PM PDT 24
Peak memory 206644 kb
Host smart-55c88463-25bc-4630-ae38-3277767c569b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25754
79852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2575479852
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.2899403292
Short name T1658
Test name
Test status
Simulation time 68307829 ps
CPU time 0.68 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:57 PM PDT 24
Peak memory 206744 kb
Host smart-6edf29b4-df75-43ba-889b-a6ec1ce0d4a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28994
03292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.2899403292
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2139534452
Short name T2332
Test name
Test status
Simulation time 9458894528 ps
CPU time 23.7 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:27:22 PM PDT 24
Peak memory 206892 kb
Host smart-73bdbbd6-abe8-42e6-96f3-7b487f7d00e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21395
34452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2139534452
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.55058581
Short name T55
Test name
Test status
Simulation time 177297301 ps
CPU time 0.81 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:26:59 PM PDT 24
Peak memory 206664 kb
Host smart-dccf3ea5-de4d-4e72-94bd-38a6373726c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55058
581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.55058581
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1393221792
Short name T2145
Test name
Test status
Simulation time 245009091 ps
CPU time 0.93 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206628 kb
Host smart-d7b5d501-ddb1-4769-a375-9c1cf316940f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13932
21792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1393221792
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.3305855029
Short name T1686
Test name
Test status
Simulation time 236494048 ps
CPU time 0.9 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206656 kb
Host smart-8d58afa1-25ff-437d-baf3-2c78856fda3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33058
55029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.3305855029
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.755272722
Short name T1010
Test name
Test status
Simulation time 161919856 ps
CPU time 0.9 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206620 kb
Host smart-bb16d25d-0a46-47ec-bceb-5bf787d996b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75527
2722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.755272722
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.4122651949
Short name T409
Test name
Test status
Simulation time 141503461 ps
CPU time 0.74 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206652 kb
Host smart-93f842f5-52af-4d2b-9dfa-47489d0cf233
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41226
51949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.4122651949
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.853475447
Short name T1420
Test name
Test status
Simulation time 147229487 ps
CPU time 0.87 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206640 kb
Host smart-e2da1b16-1df0-49d0-90d1-22fd46c66954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85347
5447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.853475447
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.487637664
Short name T959
Test name
Test status
Simulation time 179112728 ps
CPU time 0.83 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206640 kb
Host smart-79bf13ab-e77a-4e68-9605-15c0a2b9e3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48763
7664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.487637664
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.249105474
Short name T1892
Test name
Test status
Simulation time 252520510 ps
CPU time 0.9 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206660 kb
Host smart-5c730dc7-d43c-47c8-b1c0-4c71b2d5c43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24910
5474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.249105474
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2341978465
Short name T1989
Test name
Test status
Simulation time 6017398249 ps
CPU time 43.47 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:48 PM PDT 24
Peak memory 206920 kb
Host smart-67d76c6c-c09a-4863-8aac-89d5209b325f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2341978465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2341978465
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.827270573
Short name T414
Test name
Test status
Simulation time 185699635 ps
CPU time 0.8 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:56 PM PDT 24
Peak memory 206640 kb
Host smart-00054f03-71a0-4b21-ad74-4076eeef684b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82727
0573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.827270573
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.386371173
Short name T1900
Test name
Test status
Simulation time 180043202 ps
CPU time 0.81 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206628 kb
Host smart-40e8f53d-69d8-40a2-9e31-66aed13db2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38637
1173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.386371173
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.41639408
Short name T1419
Test name
Test status
Simulation time 270164648 ps
CPU time 1 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206660 kb
Host smart-ab8fbdac-049b-424a-888e-d8141bbaf45c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41639
408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.41639408
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.756128982
Short name T415
Test name
Test status
Simulation time 5191335705 ps
CPU time 36.3 seconds
Started Jul 20 06:26:54 PM PDT 24
Finished Jul 20 06:27:31 PM PDT 24
Peak memory 206892 kb
Host smart-735217de-916c-4828-9885-11e1810feac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75612
8982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.756128982
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.1609547817
Short name T1386
Test name
Test status
Simulation time 39183368 ps
CPU time 0.68 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206708 kb
Host smart-0d22c306-27b1-4439-abd9-5aa6538ee9f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1609547817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.1609547817
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2727607926
Short name T923
Test name
Test status
Simulation time 4041952209 ps
CPU time 4.77 seconds
Started Jul 20 06:27:22 PM PDT 24
Finished Jul 20 06:27:28 PM PDT 24
Peak memory 206720 kb
Host smart-78f226d9-ba68-42fd-8c24-6d76832c4bfb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2727607926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2727607926
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.2728076759
Short name T1307
Test name
Test status
Simulation time 13369421615 ps
CPU time 13.18 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206792 kb
Host smart-4181bf0d-ca69-4db4-90bd-e4720f6e47f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2728076759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.2728076759
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.4176231004
Short name T501
Test name
Test status
Simulation time 23403768316 ps
CPU time 25.79 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:28 PM PDT 24
Peak memory 206776 kb
Host smart-703cd7fa-32b3-462d-bcd4-99189b060034
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4176231004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.4176231004
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.811601479
Short name T1897
Test name
Test status
Simulation time 191001607 ps
CPU time 0.87 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:00 PM PDT 24
Peak memory 206660 kb
Host smart-bc2709a3-aa0c-4517-ab76-f577308d76b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81160
1479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.811601479
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.999574833
Short name T2457
Test name
Test status
Simulation time 156705312 ps
CPU time 0.77 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:26:59 PM PDT 24
Peak memory 206640 kb
Host smart-43361214-ea0e-4e01-a77c-e474184389d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99957
4833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.999574833
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.724809559
Short name T1580
Test name
Test status
Simulation time 674961223 ps
CPU time 1.9 seconds
Started Jul 20 06:27:03 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206736 kb
Host smart-78d80c31-5f78-47f5-8fbb-a13df8fa50e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72480
9559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.724809559
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1839420016
Short name T1778
Test name
Test status
Simulation time 351188729 ps
CPU time 1.16 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206640 kb
Host smart-f471b105-3938-47dc-b421-4ee2040759b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18394
20016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1839420016
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.1080385324
Short name T444
Test name
Test status
Simulation time 14246995068 ps
CPU time 24.25 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206492 kb
Host smart-fe5d1f67-0494-407a-b9d8-f97567dd95a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
85324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.1080385324
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.3907184654
Short name T1700
Test name
Test status
Simulation time 333245166 ps
CPU time 1.16 seconds
Started Jul 20 06:27:01 PM PDT 24
Finished Jul 20 06:27:05 PM PDT 24
Peak memory 206648 kb
Host smart-dd7d097f-86da-4dd6-8f5d-f955622371ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
84654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.3907184654
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.927548229
Short name T438
Test name
Test status
Simulation time 182681847 ps
CPU time 0.87 seconds
Started Jul 20 06:27:03 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206656 kb
Host smart-fe88dfba-9fae-4302-b593-edef23524980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92754
8229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.927548229
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2767838790
Short name T1109
Test name
Test status
Simulation time 44343802 ps
CPU time 0.65 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206648 kb
Host smart-45c630db-05cb-46ab-88f7-c783ab7dc44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27678
38790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2767838790
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3432747554
Short name T344
Test name
Test status
Simulation time 886431914 ps
CPU time 1.92 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 206736 kb
Host smart-5d493732-dc68-45d1-99eb-767b158f9fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34327
47554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3432747554
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2560515583
Short name T2026
Test name
Test status
Simulation time 172112446 ps
CPU time 1.8 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206736 kb
Host smart-10e56ef6-38a1-4ff4-8c7f-2ae75fa0f295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25605
15583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2560515583
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.2619710819
Short name T1175
Test name
Test status
Simulation time 238432387 ps
CPU time 0.94 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206644 kb
Host smart-564e17b8-f1ca-47df-a028-288da98ba8d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26197
10819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.2619710819
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3304222525
Short name T2712
Test name
Test status
Simulation time 154961741 ps
CPU time 0.75 seconds
Started Jul 20 06:26:56 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 206648 kb
Host smart-51a66777-e1d9-4786-9379-73cbbbc27edb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33042
22525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3304222525
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.3335330749
Short name T868
Test name
Test status
Simulation time 295208787 ps
CPU time 1.08 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206644 kb
Host smart-dacc0889-2e5a-41ad-8375-300b1eb7d93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33353
30749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.3335330749
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.3213234825
Short name T1651
Test name
Test status
Simulation time 6037024084 ps
CPU time 21.69 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 206864 kb
Host smart-2b30d15f-0155-4433-a7d7-1b8173e455f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32132
34825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.3213234825
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1786056273
Short name T1220
Test name
Test status
Simulation time 223396322 ps
CPU time 0.89 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:02 PM PDT 24
Peak memory 206656 kb
Host smart-28fd60ef-0d80-4d11-92fb-8a2afaf2cc48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17860
56273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1786056273
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.751749256
Short name T2386
Test name
Test status
Simulation time 23362800718 ps
CPU time 20.87 seconds
Started Jul 20 06:26:57 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206756 kb
Host smart-1dc75166-ad43-427d-aad7-b587816f6e5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75174
9256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.751749256
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.536559586
Short name T2461
Test name
Test status
Simulation time 3348817118 ps
CPU time 3.74 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206716 kb
Host smart-09a847d0-aab6-4928-9368-078dc0368598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53655
9586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.536559586
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.3310529144
Short name T2591
Test name
Test status
Simulation time 13407723287 ps
CPU time 124.97 seconds
Started Jul 20 06:27:04 PM PDT 24
Finished Jul 20 06:29:11 PM PDT 24
Peak memory 206920 kb
Host smart-fec90b94-d16e-4543-8f7b-dc6cabc08db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33105
29144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.3310529144
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2879930495
Short name T2499
Test name
Test status
Simulation time 3628645247 ps
CPU time 96.81 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:28:38 PM PDT 24
Peak memory 206852 kb
Host smart-759bbd8e-5457-4f2c-a472-6e504d630175
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2879930495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2879930495
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.742752851
Short name T599
Test name
Test status
Simulation time 242176694 ps
CPU time 0.89 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206660 kb
Host smart-c05ca9c8-642b-44e3-bc7c-0b059105a301
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=742752851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.742752851
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.2653495920
Short name T1975
Test name
Test status
Simulation time 186318142 ps
CPU time 0.86 seconds
Started Jul 20 06:26:53 PM PDT 24
Finished Jul 20 06:26:55 PM PDT 24
Peak memory 206648 kb
Host smart-a5826765-3c4d-442c-b1aa-7d9b19eef049
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26534
95920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.2653495920
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.1405271791
Short name T1023
Test name
Test status
Simulation time 5159639042 ps
CPU time 140.42 seconds
Started Jul 20 06:27:04 PM PDT 24
Finished Jul 20 06:29:27 PM PDT 24
Peak memory 206868 kb
Host smart-58d18704-6ee6-45c1-a5a2-018514f7833d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14052
71791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.1405271791
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.912474332
Short name T834
Test name
Test status
Simulation time 4936750379 ps
CPU time 128.03 seconds
Started Jul 20 06:26:54 PM PDT 24
Finished Jul 20 06:29:02 PM PDT 24
Peak memory 206888 kb
Host smart-0b65a5b1-9b53-4811-b1ca-4f1012593fa9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=912474332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.912474332
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.4125513721
Short name T308
Test name
Test status
Simulation time 161656443 ps
CPU time 0.86 seconds
Started Jul 20 06:26:56 PM PDT 24
Finished Jul 20 06:26:58 PM PDT 24
Peak memory 206656 kb
Host smart-073ea261-ad10-45cc-a95d-b48a1cb52965
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4125513721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.4125513721
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.4164905925
Short name T2249
Test name
Test status
Simulation time 135917290 ps
CPU time 0.77 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:57 PM PDT 24
Peak memory 206656 kb
Host smart-81c0c9fc-8f5c-495f-9827-3bb693cfe41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
05925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.4164905925
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1471187337
Short name T117
Test name
Test status
Simulation time 201771197 ps
CPU time 0.88 seconds
Started Jul 20 06:27:13 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206652 kb
Host smart-d4d2d368-6743-47eb-ad44-c85d9fca9ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14711
87337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1471187337
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.3795229656
Short name T394
Test name
Test status
Simulation time 162085394 ps
CPU time 0.75 seconds
Started Jul 20 06:26:55 PM PDT 24
Finished Jul 20 06:26:57 PM PDT 24
Peak memory 206664 kb
Host smart-efde8f1e-7d24-4d09-8466-7d7720b1fdd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37952
29656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.3795229656
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.68940185
Short name T2006
Test name
Test status
Simulation time 198481592 ps
CPU time 0.89 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:03 PM PDT 24
Peak memory 206656 kb
Host smart-7a6551bb-f268-476e-b2b9-56ae53d95740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68940
185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.68940185
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.2142820508
Short name T2092
Test name
Test status
Simulation time 147382740 ps
CPU time 0.76 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206656 kb
Host smart-272f4add-23ea-48f1-9643-9b3ea712f110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21428
20508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.2142820508
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1107473756
Short name T943
Test name
Test status
Simulation time 180074117 ps
CPU time 0.8 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206652 kb
Host smart-f7a2ad13-c130-4c5e-b881-768469d11c73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
73756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1107473756
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.1922542830
Short name T372
Test name
Test status
Simulation time 233602576 ps
CPU time 1.02 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:03 PM PDT 24
Peak memory 206648 kb
Host smart-9005ab59-21b1-41bd-aac9-8b92317be18c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1922542830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.1922542830
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.3104907380
Short name T718
Test name
Test status
Simulation time 158461529 ps
CPU time 0.79 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206580 kb
Host smart-9f6ca9a7-dcac-42f6-becf-51bd5f12ffb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31049
07380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.3104907380
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.680258752
Short name T701
Test name
Test status
Simulation time 36916650 ps
CPU time 0.69 seconds
Started Jul 20 06:27:01 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206600 kb
Host smart-16c0a160-269c-4638-af98-1fb87764f584
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68025
8752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.680258752
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.4195397249
Short name T91
Test name
Test status
Simulation time 21532219475 ps
CPU time 53.85 seconds
Started Jul 20 06:26:56 PM PDT 24
Finished Jul 20 06:27:51 PM PDT 24
Peak memory 206880 kb
Host smart-87e64494-d592-405c-aff2-989ae89411b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41953
97249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.4195397249
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.3521613913
Short name T1171
Test name
Test status
Simulation time 171087909 ps
CPU time 0.86 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206624 kb
Host smart-089dd3cd-fc82-47ad-85dd-69053ac1c94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35216
13913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.3521613913
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.580908555
Short name T1911
Test name
Test status
Simulation time 225502458 ps
CPU time 0.93 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 206412 kb
Host smart-56eb9e5e-3c5d-4080-a9e5-8f20ce02adc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58090
8555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.580908555
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.2052998739
Short name T2321
Test name
Test status
Simulation time 169563091 ps
CPU time 0.81 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206616 kb
Host smart-3a02942b-d279-473e-bb45-996532c60326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20529
98739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.2052998739
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1984370351
Short name T678
Test name
Test status
Simulation time 163278785 ps
CPU time 0.8 seconds
Started Jul 20 06:27:04 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206644 kb
Host smart-c9c1daa1-9548-4075-ba16-45925e20ef37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19843
70351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1984370351
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.171459941
Short name T1455
Test name
Test status
Simulation time 180325837 ps
CPU time 0.84 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206636 kb
Host smart-46ed23db-4765-428a-9f12-401012cfd624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17145
9941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.171459941
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3209521293
Short name T2255
Test name
Test status
Simulation time 188348275 ps
CPU time 0.82 seconds
Started Jul 20 06:27:03 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206652 kb
Host smart-487f113c-372c-4689-9257-a3ae2c5455ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095
21293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3209521293
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.2625729257
Short name T2016
Test name
Test status
Simulation time 172072496 ps
CPU time 0.84 seconds
Started Jul 20 06:27:01 PM PDT 24
Finished Jul 20 06:27:05 PM PDT 24
Peak memory 206632 kb
Host smart-a8bfaebb-a32a-4d93-aa8c-bcf02abe7fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26257
29257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.2625729257
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.518855433
Short name T2129
Test name
Test status
Simulation time 221165445 ps
CPU time 0.92 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206644 kb
Host smart-55812476-6bc1-4ae6-b3eb-5fbe2ea66a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51885
5433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.518855433
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.513811301
Short name T1348
Test name
Test status
Simulation time 5170085723 ps
CPU time 140.04 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:29:32 PM PDT 24
Peak memory 206864 kb
Host smart-1ebc24c5-4320-482c-ab51-e64b26320ca6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=513811301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.513811301
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.2306535111
Short name T443
Test name
Test status
Simulation time 185922336 ps
CPU time 0.81 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:04 PM PDT 24
Peak memory 206644 kb
Host smart-c9369634-cfc5-4955-82c8-d774bbb2e62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23065
35111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.2306535111
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.724208247
Short name T380
Test name
Test status
Simulation time 235005448 ps
CPU time 0.88 seconds
Started Jul 20 06:27:05 PM PDT 24
Finished Jul 20 06:27:08 PM PDT 24
Peak memory 206652 kb
Host smart-981fd6ad-4bd0-4cca-8278-54f0aaa917aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72420
8247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.724208247
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.941095610
Short name T610
Test name
Test status
Simulation time 725159867 ps
CPU time 1.68 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 206800 kb
Host smart-a64a05f5-f259-4967-bb7b-6044ed13a4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94109
5610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.941095610
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.677281169
Short name T758
Test name
Test status
Simulation time 7734417859 ps
CPU time 53.7 seconds
Started Jul 20 06:27:05 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 206848 kb
Host smart-8f800dfd-0c72-4fa7-a3be-e4990991a2e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67728
1169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.677281169
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.3385603825
Short name T1330
Test name
Test status
Simulation time 36307305 ps
CPU time 0.67 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206700 kb
Host smart-5fcc524f-71b3-40a2-b3c4-982068fbd8a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3385603825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.3385603825
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.258836020
Short name T1966
Test name
Test status
Simulation time 3436966493 ps
CPU time 3.91 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:13 PM PDT 24
Peak memory 206676 kb
Host smart-7f7d8158-b50e-4582-afca-a30e9e85e20c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=258836020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.258836020
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.145994553
Short name T767
Test name
Test status
Simulation time 13325919821 ps
CPU time 16.69 seconds
Started Jul 20 06:27:01 PM PDT 24
Finished Jul 20 06:27:20 PM PDT 24
Peak memory 206772 kb
Host smart-518e497d-f75a-4224-99eb-cddaf9dcfa3c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=145994553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.145994553
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1417704120
Short name T965
Test name
Test status
Simulation time 23386267116 ps
CPU time 21.47 seconds
Started Jul 20 06:27:01 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206856 kb
Host smart-46927afc-8635-438d-86b3-ef0b38717533
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1417704120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1417704120
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.591954354
Short name T898
Test name
Test status
Simulation time 187215589 ps
CPU time 0.84 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206660 kb
Host smart-e0de45da-c624-478e-b3c7-d386a8e87b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59195
4354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.591954354
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1276168464
Short name T512
Test name
Test status
Simulation time 214238946 ps
CPU time 0.83 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206648 kb
Host smart-9b3f96c0-9a43-49fb-85a6-3c6f5086f36c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12761
68464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1276168464
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.3129404586
Short name T1932
Test name
Test status
Simulation time 396114279 ps
CPU time 1.18 seconds
Started Jul 20 06:27:05 PM PDT 24
Finished Jul 20 06:27:09 PM PDT 24
Peak memory 206648 kb
Host smart-d63ec0e6-0b5f-44b0-ab47-a04e7c152756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31294
04586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.3129404586
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.60362763
Short name T387
Test name
Test status
Simulation time 486608863 ps
CPU time 1.42 seconds
Started Jul 20 06:27:03 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206636 kb
Host smart-3804d62a-88e8-4162-964a-4d14a6087d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60362
763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.60362763
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.954152828
Short name T455
Test name
Test status
Simulation time 22409445892 ps
CPU time 38.54 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 206924 kb
Host smart-f3a7a816-d98f-47e9-b248-85cff1840a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95415
2828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.954152828
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1905081419
Short name T480
Test name
Test status
Simulation time 343081868 ps
CPU time 1.13 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:03 PM PDT 24
Peak memory 206660 kb
Host smart-ad135fc2-960a-4815-876b-752e2a820c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19050
81419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1905081419
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.429639776
Short name T939
Test name
Test status
Simulation time 147712561 ps
CPU time 0.77 seconds
Started Jul 20 06:27:12 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 206664 kb
Host smart-ca22d272-37ed-4bad-a71d-0398de2170bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42963
9776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.429639776
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1927805628
Short name T771
Test name
Test status
Simulation time 38887853 ps
CPU time 0.64 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206660 kb
Host smart-2ab8de40-b008-4254-8444-afa279764c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19278
05628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1927805628
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.2150708951
Short name T1237
Test name
Test status
Simulation time 883149317 ps
CPU time 2.29 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206772 kb
Host smart-952264d7-6baf-47c9-bb16-eb875b6701a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21507
08951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.2150708951
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.2416419290
Short name T1264
Test name
Test status
Simulation time 172564175 ps
CPU time 1.25 seconds
Started Jul 20 06:27:13 PM PDT 24
Finished Jul 20 06:27:18 PM PDT 24
Peak memory 206724 kb
Host smart-69da96d9-ffda-48ea-88c5-5f077dba24a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24164
19290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.2416419290
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3178093539
Short name T2419
Test name
Test status
Simulation time 173267907 ps
CPU time 0.8 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 206568 kb
Host smart-7d3e7e45-f5be-410c-a828-0fbf4089e54d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31780
93539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3178093539
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4217877836
Short name T1511
Test name
Test status
Simulation time 149137808 ps
CPU time 0.79 seconds
Started Jul 20 06:27:13 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206648 kb
Host smart-458eb0be-7811-4907-a896-dc27e616069f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42178
77836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4217877836
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1346203975
Short name T529
Test name
Test status
Simulation time 172868485 ps
CPU time 0.83 seconds
Started Jul 20 06:27:11 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 206648 kb
Host smart-8d05e6de-1bb8-4443-9be3-80ac2956fc4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13462
03975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1346203975
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.3887697560
Short name T1889
Test name
Test status
Simulation time 7978533072 ps
CPU time 217.95 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:30:47 PM PDT 24
Peak memory 206848 kb
Host smart-1c037fa3-20f8-492c-b78c-ad30e9276b6b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3887697560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.3887697560
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.258339715
Short name T90
Test name
Test status
Simulation time 8055285193 ps
CPU time 72.98 seconds
Started Jul 20 06:27:12 PM PDT 24
Finished Jul 20 06:28:29 PM PDT 24
Peak memory 206924 kb
Host smart-69af705c-ee87-4f8b-a89c-dd63ca88c0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25833
9715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.258339715
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.4043938507
Short name T1898
Test name
Test status
Simulation time 214882962 ps
CPU time 0.91 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:12 PM PDT 24
Peak memory 206652 kb
Host smart-5a268441-07c1-444f-8503-006d44127aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40439
38507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.4043938507
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.2275523837
Short name T2033
Test name
Test status
Simulation time 23310518513 ps
CPU time 23.4 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:35 PM PDT 24
Peak memory 206760 kb
Host smart-507b7b3c-f196-4fb6-99a1-e07a3915098f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22755
23837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.2275523837
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1057716688
Short name T2246
Test name
Test status
Simulation time 3287874631 ps
CPU time 4.23 seconds
Started Jul 20 06:26:59 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206716 kb
Host smart-34c9c748-e6c7-41de-ae76-377e3eeb7630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577
16688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1057716688
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.518070766
Short name T2684
Test name
Test status
Simulation time 8204001007 ps
CPU time 234.13 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:31:08 PM PDT 24
Peak memory 206960 kb
Host smart-9a432f92-f254-4b92-baa7-825b7d1b25ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51807
0766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.518070766
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2324835362
Short name T1393
Test name
Test status
Simulation time 5150755881 ps
CPU time 142.42 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:29:34 PM PDT 24
Peak memory 206864 kb
Host smart-fb8630f7-1cca-4156-bfd0-6203c2f4d3e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2324835362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2324835362
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.285515830
Short name T1957
Test name
Test status
Simulation time 241798383 ps
CPU time 0.9 seconds
Started Jul 20 06:27:01 PM PDT 24
Finished Jul 20 06:27:05 PM PDT 24
Peak memory 206644 kb
Host smart-9c9fd719-2516-4c35-9a08-a7b92a6989b1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=285515830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.285515830
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.3101324282
Short name T2450
Test name
Test status
Simulation time 205468213 ps
CPU time 0.91 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206664 kb
Host smart-d4adbdbd-2c3b-44db-852f-8c895a83ec53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31013
24282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.3101324282
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.3024861476
Short name T2555
Test name
Test status
Simulation time 3248502836 ps
CPU time 31 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:34 PM PDT 24
Peak memory 206840 kb
Host smart-f14da715-bbd1-4fae-8a08-dc4f199ffc1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30248
61476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.3024861476
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3826247771
Short name T1207
Test name
Test status
Simulation time 4419535828 ps
CPU time 30.64 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:27:44 PM PDT 24
Peak memory 206912 kb
Host smart-54695fae-a4f0-45a3-a008-ecfa39413f0e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3826247771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3826247771
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.3951091719
Short name T803
Test name
Test status
Simulation time 160535468 ps
CPU time 0.79 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206660 kb
Host smart-28b6d647-363b-40aa-a212-a486ae11bbd6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3951091719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.3951091719
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.3469611195
Short name T1926
Test name
Test status
Simulation time 213831303 ps
CPU time 0.84 seconds
Started Jul 20 06:27:00 PM PDT 24
Finished Jul 20 06:27:03 PM PDT 24
Peak memory 206648 kb
Host smart-7b0c8b19-83b9-413a-b3a9-316196c459c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34696
11195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.3469611195
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1689649606
Short name T2633
Test name
Test status
Simulation time 230012880 ps
CPU time 0.88 seconds
Started Jul 20 06:27:02 PM PDT 24
Finished Jul 20 06:27:06 PM PDT 24
Peak memory 206648 kb
Host smart-5d801e1a-1bb1-4e1e-bd62-04ed4dacd4bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16896
49606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1689649606
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3284983810
Short name T538
Test name
Test status
Simulation time 169945934 ps
CPU time 0.8 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206652 kb
Host smart-cdc3381a-6fae-43d3-beae-56c53cbbcdd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32849
83810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3284983810
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.2041859245
Short name T2328
Test name
Test status
Simulation time 197176013 ps
CPU time 0.8 seconds
Started Jul 20 06:27:11 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 206652 kb
Host smart-40278cf3-5de4-4a26-9e89-d9807aea78b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20418
59245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.2041859245
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.4022617247
Short name T1000
Test name
Test status
Simulation time 207251184 ps
CPU time 0.87 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:27:14 PM PDT 24
Peak memory 206600 kb
Host smart-26d7e80b-4ae7-4471-93a8-83dd84bb5ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
17247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.4022617247
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.225230029
Short name T152
Test name
Test status
Simulation time 148654618 ps
CPU time 0.81 seconds
Started Jul 20 06:26:58 PM PDT 24
Finished Jul 20 06:27:01 PM PDT 24
Peak memory 206660 kb
Host smart-35cc6623-366e-4235-986a-074df99f2f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22523
0029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.225230029
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1770514916
Short name T1662
Test name
Test status
Simulation time 249747359 ps
CPU time 1.01 seconds
Started Jul 20 06:27:05 PM PDT 24
Finished Jul 20 06:27:08 PM PDT 24
Peak memory 206648 kb
Host smart-1c57725a-4939-4a72-831c-5691c9c2e898
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1770514916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1770514916
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.552540040
Short name T2012
Test name
Test status
Simulation time 147490705 ps
CPU time 0.78 seconds
Started Jul 20 06:27:12 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 206652 kb
Host smart-52c693d4-035c-4b7d-b0b4-94a3ebcf7ad4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55254
0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.552540040
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.850116237
Short name T1257
Test name
Test status
Simulation time 57922581 ps
CPU time 0.68 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206652 kb
Host smart-c3b936f8-63c9-47e8-9041-d10ce0adba85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85011
6237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.850116237
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3873467070
Short name T534
Test name
Test status
Simulation time 7441437430 ps
CPU time 15.94 seconds
Started Jul 20 06:27:21 PM PDT 24
Finished Jul 20 06:27:39 PM PDT 24
Peak memory 206900 kb
Host smart-b88d2e7d-d104-492f-861b-94a038b4826f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38734
67070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3873467070
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3055098223
Short name T1306
Test name
Test status
Simulation time 174910173 ps
CPU time 0.87 seconds
Started Jul 20 06:27:05 PM PDT 24
Finished Jul 20 06:27:09 PM PDT 24
Peak memory 206660 kb
Host smart-fba005e2-9e0b-4508-a0b1-8fa0acf35c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30550
98223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3055098223
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2151494282
Short name T1373
Test name
Test status
Simulation time 164342091 ps
CPU time 0.8 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206636 kb
Host smart-c7ec6f46-d6d8-489f-af03-ae29b78a5f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21514
94282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2151494282
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.1399620047
Short name T314
Test name
Test status
Simulation time 178793972 ps
CPU time 0.79 seconds
Started Jul 20 06:27:05 PM PDT 24
Finished Jul 20 06:27:09 PM PDT 24
Peak memory 206740 kb
Host smart-71f4a943-9ccb-46a1-976f-c6d35087d4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13996
20047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.1399620047
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.1488593154
Short name T1151
Test name
Test status
Simulation time 168987353 ps
CPU time 0.79 seconds
Started Jul 20 06:27:04 PM PDT 24
Finished Jul 20 06:27:08 PM PDT 24
Peak memory 206632 kb
Host smart-b385995d-5fa4-4750-b7b9-025ab0489f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14885
93154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.1488593154
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2375923667
Short name T1570
Test name
Test status
Simulation time 211274380 ps
CPU time 0.83 seconds
Started Jul 20 06:27:04 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206652 kb
Host smart-a918da4b-9270-48c5-9447-2ebe7e9af96e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23759
23667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2375923667
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3958181119
Short name T1535
Test name
Test status
Simulation time 189080413 ps
CPU time 0.8 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206648 kb
Host smart-1cb4d89d-472a-4c9d-a555-c17c635f11ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39581
81119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3958181119
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.1962379104
Short name T2705
Test name
Test status
Simulation time 178921480 ps
CPU time 0.79 seconds
Started Jul 20 06:27:04 PM PDT 24
Finished Jul 20 06:27:07 PM PDT 24
Peak memory 206656 kb
Host smart-601a1b64-6432-46e1-8274-792379605210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19623
79104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.1962379104
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.608442944
Short name T2379
Test name
Test status
Simulation time 207709639 ps
CPU time 0.91 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 206588 kb
Host smart-cdff14f3-7233-4fff-9be0-fb93971d6380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60844
2944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.608442944
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.3772011424
Short name T773
Test name
Test status
Simulation time 4075527627 ps
CPU time 30.64 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:59 PM PDT 24
Peak memory 206752 kb
Host smart-7db38d11-db2e-4bd1-bf70-27064eed9585
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3772011424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.3772011424
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.2247470381
Short name T1814
Test name
Test status
Simulation time 166529724 ps
CPU time 0.84 seconds
Started Jul 20 06:27:12 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206656 kb
Host smart-8fc87bb8-8886-4a29-9396-a17417133073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22474
70381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.2247470381
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3458122921
Short name T1585
Test name
Test status
Simulation time 251761545 ps
CPU time 0.9 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206652 kb
Host smart-4e166895-51f4-4633-b2d9-b3e362da22da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34581
22921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3458122921
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1413189105
Short name T1314
Test name
Test status
Simulation time 1200649636 ps
CPU time 2.5 seconds
Started Jul 20 06:27:11 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206792 kb
Host smart-9d1034f9-1625-4bcd-b8a3-cb147c020ff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14131
89105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1413189105
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.1933377892
Short name T1545
Test name
Test status
Simulation time 3444784263 ps
CPU time 23.58 seconds
Started Jul 20 06:27:12 PM PDT 24
Finished Jul 20 06:27:40 PM PDT 24
Peak memory 206908 kb
Host smart-c5c1f5df-7b28-41de-a76a-3a9cc33ca43d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19333
77892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.1933377892
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.1002281042
Short name T1822
Test name
Test status
Simulation time 36105019 ps
CPU time 0.67 seconds
Started Jul 20 06:27:18 PM PDT 24
Finished Jul 20 06:27:22 PM PDT 24
Peak memory 206680 kb
Host smart-2bda1f1b-c84a-4cd4-a6f6-c282033861a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1002281042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.1002281042
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.1013854583
Short name T547
Test name
Test status
Simulation time 4033194638 ps
CPU time 5.12 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206872 kb
Host smart-ef891c40-93ae-4921-ac7d-c22858eae5f8
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1013854583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.1013854583
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3406719968
Short name T1428
Test name
Test status
Simulation time 13304325870 ps
CPU time 12.64 seconds
Started Jul 20 06:27:11 PM PDT 24
Finished Jul 20 06:27:27 PM PDT 24
Peak memory 206936 kb
Host smart-86eb16ac-ddd7-4e1e-9b8e-9eb35376b438
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3406719968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3406719968
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.3919974818
Short name T190
Test name
Test status
Simulation time 23379967318 ps
CPU time 21.93 seconds
Started Jul 20 06:27:12 PM PDT 24
Finished Jul 20 06:27:38 PM PDT 24
Peak memory 206868 kb
Host smart-63ba6d9f-b719-4bf4-95af-a3bc14dbcd2d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3919974818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.3919974818
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.483952408
Short name T1058
Test name
Test status
Simulation time 176214969 ps
CPU time 0.84 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206648 kb
Host smart-3e738d2b-2752-4065-9273-4891af8ebd6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48395
2408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.483952408
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.1601773069
Short name T34
Test name
Test status
Simulation time 161114033 ps
CPU time 0.82 seconds
Started Jul 20 06:27:17 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206660 kb
Host smart-9cb02062-cfff-4757-9eec-74df8d3845ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16017
73069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.1601773069
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.21764234
Short name T627
Test name
Test status
Simulation time 229779593 ps
CPU time 0.92 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206664 kb
Host smart-0bac5a53-5bd0-477d-866e-4799215c6794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21764
234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.21764234
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3540799599
Short name T2004
Test name
Test status
Simulation time 1321635078 ps
CPU time 2.8 seconds
Started Jul 20 06:27:05 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206820 kb
Host smart-4969871c-cbe3-4ca6-a079-391bfbacdb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35407
99599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3540799599
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.2879344699
Short name T2085
Test name
Test status
Simulation time 8714747762 ps
CPU time 14.94 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:41 PM PDT 24
Peak memory 206852 kb
Host smart-eaae5b5e-d9fa-422c-b59b-0f8f3d170cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28793
44699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.2879344699
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.4015409119
Short name T947
Test name
Test status
Simulation time 400363478 ps
CPU time 1.28 seconds
Started Jul 20 06:27:13 PM PDT 24
Finished Jul 20 06:27:18 PM PDT 24
Peak memory 206636 kb
Host smart-1c3700ee-c62b-4d16-9121-38e30f94c8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40154
09119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.4015409119
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.214317954
Short name T757
Test name
Test status
Simulation time 131826532 ps
CPU time 0.8 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206656 kb
Host smart-7b7d2309-b8e5-484b-adfc-5330bd2672f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21431
7954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.214317954
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3718413815
Short name T1451
Test name
Test status
Simulation time 66372337 ps
CPU time 0.7 seconds
Started Jul 20 06:27:22 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206644 kb
Host smart-d1a9435b-5f2e-4bd5-af57-303b7b66271f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37184
13815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3718413815
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.853333126
Short name T1161
Test name
Test status
Simulation time 1024583553 ps
CPU time 2.04 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:17 PM PDT 24
Peak memory 206744 kb
Host smart-6ab16dd0-04e1-41a9-97ba-474cd3a5a1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85333
3126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.853333126
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.2867991498
Short name T875
Test name
Test status
Simulation time 187563882 ps
CPU time 1.17 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206792 kb
Host smart-334247ad-9d70-48b8-9b40-28a117080af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28679
91498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.2867991498
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.3732176992
Short name T1381
Test name
Test status
Simulation time 174852962 ps
CPU time 0.82 seconds
Started Jul 20 06:27:06 PM PDT 24
Finished Jul 20 06:27:10 PM PDT 24
Peak memory 206644 kb
Host smart-1d221117-44a2-4abd-b51f-46d5bd9c39ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37321
76992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.3732176992
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.4245024831
Short name T1831
Test name
Test status
Simulation time 145511266 ps
CPU time 0.75 seconds
Started Jul 20 06:27:14 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206648 kb
Host smart-864963ef-0553-4040-b30c-993eedb94317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42450
24831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.4245024831
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.918047849
Short name T1710
Test name
Test status
Simulation time 279087924 ps
CPU time 0.96 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:12 PM PDT 24
Peak memory 206628 kb
Host smart-4e4915ed-ecb3-46e1-b1ef-dfff90b6a36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91804
7849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.918047849
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.3495284516
Short name T417
Test name
Test status
Simulation time 4405235894 ps
CPU time 44.54 seconds
Started Jul 20 06:27:12 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 206896 kb
Host smart-7538277b-7044-4ebb-a62e-3bf8230d8030
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34952
84516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.3495284516
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.2119378739
Short name T1213
Test name
Test status
Simulation time 222607784 ps
CPU time 0.9 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206652 kb
Host smart-91085a14-78d5-477d-960c-d3095d712143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21193
78739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.2119378739
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.3316973303
Short name T1243
Test name
Test status
Simulation time 23363713681 ps
CPU time 21.06 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:49 PM PDT 24
Peak memory 206696 kb
Host smart-6fc0d0e3-1078-4e35-a101-7bee0b287a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33169
73303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.3316973303
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.1964347039
Short name T1017
Test name
Test status
Simulation time 3359709119 ps
CPU time 3.58 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 206720 kb
Host smart-22e171d7-8cbe-4cee-9de9-be94c88f41d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19643
47039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.1964347039
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.471286391
Short name T2185
Test name
Test status
Simulation time 8537760679 ps
CPU time 64.84 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:28:24 PM PDT 24
Peak memory 206912 kb
Host smart-53908574-c676-4e70-bb24-7a01c939a7ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47128
6391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.471286391
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.3598733436
Short name T1718
Test name
Test status
Simulation time 3275207204 ps
CPU time 85.12 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:28:38 PM PDT 24
Peak memory 206888 kb
Host smart-92320742-ce07-460f-b7cf-261aec458842
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3598733436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.3598733436
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.1444507968
Short name T1688
Test name
Test status
Simulation time 261187774 ps
CPU time 1.01 seconds
Started Jul 20 06:27:11 PM PDT 24
Finished Jul 20 06:27:16 PM PDT 24
Peak memory 206656 kb
Host smart-c87a1add-f7f9-4cfd-9075-ddff7af7443f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1444507968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.1444507968
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1306821409
Short name T1374
Test name
Test status
Simulation time 260883472 ps
CPU time 0.88 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206664 kb
Host smart-00d7029c-d836-4ef3-8ab0-f5f0e24e53ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13068
21409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1306821409
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.460950774
Short name T2121
Test name
Test status
Simulation time 3392463315 ps
CPU time 25.15 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:53 PM PDT 24
Peak memory 206808 kb
Host smart-9e238af8-cc9e-44e5-b3eb-2797475a3186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46095
0774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.460950774
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.269657559
Short name T1987
Test name
Test status
Simulation time 4307226592 ps
CPU time 39.64 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:27:53 PM PDT 24
Peak memory 206872 kb
Host smart-e955c2b9-6b5b-47c1-9e52-4969741bdcbb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=269657559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.269657559
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.1556308082
Short name T465
Test name
Test status
Simulation time 153509149 ps
CPU time 0.85 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206664 kb
Host smart-da422058-dbe5-4861-8679-1a8dc1e2a920
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1556308082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.1556308082
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.1799244075
Short name T315
Test name
Test status
Simulation time 139859901 ps
CPU time 0.78 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206644 kb
Host smart-f091eab6-26f9-422e-a0bc-28e91719f29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17992
44075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.1799244075
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.655281782
Short name T135
Test name
Test status
Simulation time 211545970 ps
CPU time 0.88 seconds
Started Jul 20 06:27:19 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 206700 kb
Host smart-219fc5e1-e6a6-4a60-9bf4-9d239addff88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65528
1782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.655281782
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2246756777
Short name T2719
Test name
Test status
Simulation time 156736215 ps
CPU time 0.78 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 206596 kb
Host smart-9ac0f4e1-be4c-4912-b339-a575a5fd438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22467
56777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2246756777
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.3122261905
Short name T482
Test name
Test status
Simulation time 165710957 ps
CPU time 0.84 seconds
Started Jul 20 06:27:26 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 206584 kb
Host smart-a5686ea2-5ab8-421a-8e5e-7a6ac494d7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31222
61905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.3122261905
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3843210899
Short name T1322
Test name
Test status
Simulation time 154928154 ps
CPU time 0.76 seconds
Started Jul 20 06:27:16 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206644 kb
Host smart-53446524-dbd1-4c4f-85a0-c38f6b63be48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38432
10899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3843210899
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.355054772
Short name T2195
Test name
Test status
Simulation time 172554752 ps
CPU time 0.8 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:13 PM PDT 24
Peak memory 206644 kb
Host smart-0463a27a-a172-4676-a787-0600fc6ddecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
4772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.355054772
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.3735973806
Short name T371
Test name
Test status
Simulation time 232624297 ps
CPU time 0.98 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206648 kb
Host smart-7ba49fc0-9337-4f6c-a0ae-6372f1d00099
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3735973806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.3735973806
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2365469261
Short name T644
Test name
Test status
Simulation time 153506299 ps
CPU time 0.78 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:12 PM PDT 24
Peak memory 206648 kb
Host smart-44744e04-fa66-4eb1-8eb8-cb101c0591b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23654
69261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2365469261
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.4160930241
Short name T1469
Test name
Test status
Simulation time 118117300 ps
CPU time 0.71 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:11 PM PDT 24
Peak memory 206632 kb
Host smart-aa05d6a5-88ee-47ee-914d-724a6e045d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41609
30241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.4160930241
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.1583014111
Short name T689
Test name
Test status
Simulation time 7642026861 ps
CPU time 17.93 seconds
Started Jul 20 06:27:07 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 206936 kb
Host smart-fed4b904-9112-497a-9d2a-7bb74faf9e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15830
14111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.1583014111
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.3445446097
Short name T2119
Test name
Test status
Simulation time 176484255 ps
CPU time 0.88 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:27:14 PM PDT 24
Peak memory 206624 kb
Host smart-b2ccea28-24ea-4a5d-83d6-35d488552722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34454
46097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.3445446097
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.3188395601
Short name T332
Test name
Test status
Simulation time 216599896 ps
CPU time 0.89 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206668 kb
Host smart-7d5549aa-fe58-41ce-94a2-19483de43b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31883
95601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.3188395601
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2878175862
Short name T2371
Test name
Test status
Simulation time 239371934 ps
CPU time 0.88 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:13 PM PDT 24
Peak memory 206652 kb
Host smart-5d57cc20-1618-4109-89dd-4a2fb6f5b028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28781
75862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2878175862
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.76151026
Short name T514
Test name
Test status
Simulation time 189016129 ps
CPU time 0.88 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:20 PM PDT 24
Peak memory 206632 kb
Host smart-e74e7ed9-651c-4f77-a023-449bc4c346e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76151
026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.76151026
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.4137839452
Short name T2378
Test name
Test status
Simulation time 145153571 ps
CPU time 0.77 seconds
Started Jul 20 06:27:08 PM PDT 24
Finished Jul 20 06:27:12 PM PDT 24
Peak memory 206636 kb
Host smart-44858667-7932-476e-a2c7-125ef5a42b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41378
39452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.4137839452
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3779736532
Short name T434
Test name
Test status
Simulation time 150744542 ps
CPU time 0.76 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:20 PM PDT 24
Peak memory 206648 kb
Host smart-d7d7a7d7-ee66-4590-9b8c-4d5a711dfecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37797
36532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3779736532
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.3106772876
Short name T1799
Test name
Test status
Simulation time 158223897 ps
CPU time 0.8 seconds
Started Jul 20 06:27:09 PM PDT 24
Finished Jul 20 06:27:14 PM PDT 24
Peak memory 206660 kb
Host smart-df8db501-66cd-44f5-a9f6-509eb3bd13c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
72876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.3106772876
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2992080847
Short name T663
Test name
Test status
Simulation time 214705300 ps
CPU time 0.89 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:27:15 PM PDT 24
Peak memory 206664 kb
Host smart-68f077a8-c170-46e2-b920-18c3f0d3cc7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29920
80847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2992080847
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.1766332854
Short name T2425
Test name
Test status
Simulation time 6417178727 ps
CPU time 170.82 seconds
Started Jul 20 06:27:10 PM PDT 24
Finished Jul 20 06:30:06 PM PDT 24
Peak memory 206836 kb
Host smart-905d689a-818a-4988-8cae-e0088830cb33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1766332854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.1766332854
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.2744172196
Short name T653
Test name
Test status
Simulation time 213222142 ps
CPU time 0.86 seconds
Started Jul 20 06:27:25 PM PDT 24
Finished Jul 20 06:27:28 PM PDT 24
Peak memory 206656 kb
Host smart-69766b6b-842a-4baf-acd5-2d2f148c0d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27441
72196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.2744172196
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.50917545
Short name T575
Test name
Test status
Simulation time 211619950 ps
CPU time 0.91 seconds
Started Jul 20 06:27:17 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206640 kb
Host smart-b9b574b9-daad-4892-ad84-8a8bcbab9e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50917
545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.50917545
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.655483396
Short name T313
Test name
Test status
Simulation time 1148620907 ps
CPU time 2.32 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:22 PM PDT 24
Peak memory 206768 kb
Host smart-4e76c084-58c1-4a19-a09a-82d6db58d062
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65548
3396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.655483396
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.1750467785
Short name T869
Test name
Test status
Simulation time 4692108636 ps
CPU time 129.68 seconds
Started Jul 20 06:27:22 PM PDT 24
Finished Jul 20 06:29:34 PM PDT 24
Peak memory 206864 kb
Host smart-e553379d-e8f0-4f0a-9d77-9be176d418f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17504
67785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.1750467785
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3033076765
Short name T1801
Test name
Test status
Simulation time 44109114 ps
CPU time 0.67 seconds
Started Jul 20 06:27:25 PM PDT 24
Finished Jul 20 06:27:31 PM PDT 24
Peak memory 206708 kb
Host smart-895d9537-3e05-4017-bee3-8d88f0542c38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3033076765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3033076765
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.4256546051
Short name T14
Test name
Test status
Simulation time 4256181159 ps
CPU time 5.5 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:31 PM PDT 24
Peak memory 206660 kb
Host smart-6fb0ac1b-f368-4f6a-806f-a458c817dec9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4256546051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.4256546051
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.988379763
Short name T1160
Test name
Test status
Simulation time 13354976000 ps
CPU time 11.86 seconds
Started Jul 20 06:27:17 PM PDT 24
Finished Jul 20 06:27:32 PM PDT 24
Peak memory 206948 kb
Host smart-5d08dbe5-880a-4c29-b45d-4e1d9c21319f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=988379763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.988379763
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.4035614203
Short name T2619
Test name
Test status
Simulation time 23314063468 ps
CPU time 24.27 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:44 PM PDT 24
Peak memory 206880 kb
Host smart-b2a9fb35-58f7-41eb-a87e-3f902f0fff71
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4035614203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.4035614203
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3932646396
Short name T652
Test name
Test status
Simulation time 166724353 ps
CPU time 0.78 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206656 kb
Host smart-552afb08-b173-4130-8138-8a359edd8403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39326
46396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3932646396
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.2373058112
Short name T608
Test name
Test status
Simulation time 146199794 ps
CPU time 0.77 seconds
Started Jul 20 06:27:19 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 206656 kb
Host smart-b1a69347-eaf2-4f96-819d-14a834ff217f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23730
58112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.2373058112
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2472512536
Short name T1961
Test name
Test status
Simulation time 380557539 ps
CPU time 1.22 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:20 PM PDT 24
Peak memory 206636 kb
Host smart-6cb095f8-7f32-4010-b73d-2cf145d20631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24725
12536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2472512536
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.2121542626
Short name T1695
Test name
Test status
Simulation time 909517258 ps
CPU time 2.14 seconds
Started Jul 20 06:27:25 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 206780 kb
Host smart-15dd40be-2e44-482b-82f8-6d7a1fd8c83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215
42626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.2121542626
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.877120727
Short name T789
Test name
Test status
Simulation time 15927347012 ps
CPU time 28.27 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:51 PM PDT 24
Peak memory 206868 kb
Host smart-5d60e643-cb54-4b00-81a7-d7f81747da12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87712
0727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.877120727
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.1360089028
Short name T2549
Test name
Test status
Simulation time 341062647 ps
CPU time 1.18 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206648 kb
Host smart-a8cd3e91-e2ed-40ec-b256-c14976e3f3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600
89028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.1360089028
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.612460840
Short name T2212
Test name
Test status
Simulation time 181407128 ps
CPU time 0.79 seconds
Started Jul 20 06:27:22 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206640 kb
Host smart-02c8c233-bd3f-4d67-9374-2014d0c66aab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61246
0840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.612460840
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.3771597726
Short name T664
Test name
Test status
Simulation time 104081036 ps
CPU time 0.69 seconds
Started Jul 20 06:27:14 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206648 kb
Host smart-da43d013-7f1d-466b-950f-5a96f86f409f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37715
97726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.3771597726
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.2348811043
Short name T836
Test name
Test status
Simulation time 1003964908 ps
CPU time 2.14 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:24 PM PDT 24
Peak memory 206800 kb
Host smart-77836653-d523-4bbc-b423-5aa3d8870d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23488
11043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.2348811043
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.444679633
Short name T802
Test name
Test status
Simulation time 219781137 ps
CPU time 1.39 seconds
Started Jul 20 06:27:17 PM PDT 24
Finished Jul 20 06:27:22 PM PDT 24
Peak memory 206800 kb
Host smart-b1295619-40e6-4c75-9c0a-f5e954222d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44467
9633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.444679633
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2865941487
Short name T1601
Test name
Test status
Simulation time 177222019 ps
CPU time 0.83 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 206648 kb
Host smart-c58fc93d-3492-4d08-831a-3038e83875a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28659
41487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2865941487
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3895020773
Short name T2221
Test name
Test status
Simulation time 147173901 ps
CPU time 0.78 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:27 PM PDT 24
Peak memory 206632 kb
Host smart-3befa22e-8653-41db-b1ea-a7bcb0b07259
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38950
20773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3895020773
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.867276469
Short name T504
Test name
Test status
Simulation time 203122981 ps
CPU time 0.92 seconds
Started Jul 20 06:27:16 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206640 kb
Host smart-13a3671e-f9a8-43ee-93de-2348e398af7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86727
6469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.867276469
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.3694816119
Short name T637
Test name
Test status
Simulation time 6826578851 ps
CPU time 56.74 seconds
Started Jul 20 06:27:21 PM PDT 24
Finished Jul 20 06:28:20 PM PDT 24
Peak memory 206924 kb
Host smart-f9f5af73-8677-4809-af75-0e607df8035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
16119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.3694816119
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.843690979
Short name T2193
Test name
Test status
Simulation time 206920159 ps
CPU time 0.88 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:27 PM PDT 24
Peak memory 206628 kb
Host smart-d5b4c73e-de6c-4701-8dc3-371611020833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84369
0979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.843690979
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.2131541698
Short name T1587
Test name
Test status
Simulation time 23413490359 ps
CPU time 22.81 seconds
Started Jul 20 06:27:21 PM PDT 24
Finished Jul 20 06:27:46 PM PDT 24
Peak memory 206784 kb
Host smart-66cb1b63-9847-4c35-9897-39277fda613e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21315
41698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.2131541698
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.2171709748
Short name T1559
Test name
Test status
Simulation time 3296532466 ps
CPU time 3.49 seconds
Started Jul 20 06:27:15 PM PDT 24
Finished Jul 20 06:27:22 PM PDT 24
Peak memory 206724 kb
Host smart-9942accc-8f03-41fe-aa75-0efa2bafdabb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21717
09748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.2171709748
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.736659171
Short name T2218
Test name
Test status
Simulation time 7708315861 ps
CPU time 71.9 seconds
Started Jul 20 06:27:17 PM PDT 24
Finished Jul 20 06:28:32 PM PDT 24
Peak memory 206896 kb
Host smart-a810a4f9-dcb8-4b1c-826d-8adb1562077a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73665
9171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.736659171
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.508948795
Short name T2537
Test name
Test status
Simulation time 4716495458 ps
CPU time 44.54 seconds
Started Jul 20 06:27:13 PM PDT 24
Finished Jul 20 06:28:01 PM PDT 24
Peak memory 206884 kb
Host smart-6d71e6e0-f926-47cd-ba64-4d30a2f5558c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=508948795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.508948795
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.2996398062
Short name T573
Test name
Test status
Simulation time 261184649 ps
CPU time 0.89 seconds
Started Jul 20 06:27:16 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206648 kb
Host smart-e3635b57-5478-418c-800c-4c2a87886beb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2996398062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.2996398062
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.1396103728
Short name T1251
Test name
Test status
Simulation time 198322779 ps
CPU time 0.84 seconds
Started Jul 20 06:27:14 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206648 kb
Host smart-43e30c0b-0930-4c9a-bc09-06ce43f6bda4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13961
03728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.1396103728
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2576567797
Short name T429
Test name
Test status
Simulation time 5818921764 ps
CPU time 159.54 seconds
Started Jul 20 06:27:19 PM PDT 24
Finished Jul 20 06:30:01 PM PDT 24
Peak memory 206868 kb
Host smart-4ca61f1c-c6d9-41d4-993b-053532acfac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25765
67797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2576567797
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.663281441
Short name T1103
Test name
Test status
Simulation time 4129998822 ps
CPU time 28.3 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:50 PM PDT 24
Peak memory 206864 kb
Host smart-2ce68ec4-170e-4e23-a383-d2eb45ac5300
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=663281441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.663281441
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.2362080796
Short name T2528
Test name
Test status
Simulation time 150895355 ps
CPU time 0.81 seconds
Started Jul 20 06:27:16 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206644 kb
Host smart-0d4f1fe2-0be6-4b7e-bda8-6434b5a59773
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2362080796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.2362080796
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.236591331
Short name T1527
Test name
Test status
Simulation time 195362774 ps
CPU time 0.86 seconds
Started Jul 20 06:27:16 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206648 kb
Host smart-02020991-66cd-48b7-81c7-31069affb499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23659
1331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.236591331
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.3482217794
Short name T114
Test name
Test status
Simulation time 232457592 ps
CPU time 0.87 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:26 PM PDT 24
Peak memory 206648 kb
Host smart-bfe210f1-400d-4b35-8fdd-2caf8b5ffee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34822
17794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.3482217794
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.3192176315
Short name T35
Test name
Test status
Simulation time 185920247 ps
CPU time 0.8 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 205980 kb
Host smart-e24af8bf-bccf-44f4-8063-284c5f99971f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31921
76315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.3192176315
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.3738687426
Short name T1731
Test name
Test status
Simulation time 173353794 ps
CPU time 0.8 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 205932 kb
Host smart-03cf576b-314a-463d-a2ba-4554fc09a8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37386
87426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.3738687426
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3466124458
Short name T2430
Test name
Test status
Simulation time 172577205 ps
CPU time 0.8 seconds
Started Jul 20 06:27:14 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206652 kb
Host smart-f5109e1e-e561-487b-93ae-15145fab0097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34661
24458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3466124458
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2470222882
Short name T2438
Test name
Test status
Simulation time 172179614 ps
CPU time 0.77 seconds
Started Jul 20 06:27:14 PM PDT 24
Finished Jul 20 06:27:19 PM PDT 24
Peak memory 206652 kb
Host smart-0143286c-aff4-4d7b-bdce-19c98d8dc090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24702
22882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2470222882
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3137303422
Short name T890
Test name
Test status
Simulation time 209989801 ps
CPU time 0.9 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 206640 kb
Host smart-30b5d61d-aee4-40fb-90f8-39824394b4a9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3137303422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3137303422
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2575246064
Short name T2018
Test name
Test status
Simulation time 142304930 ps
CPU time 0.79 seconds
Started Jul 20 06:27:20 PM PDT 24
Finished Jul 20 06:27:23 PM PDT 24
Peak memory 206644 kb
Host smart-93076f01-8f4d-4569-9adf-7920b4503946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25752
46064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2575246064
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.2521384829
Short name T207
Test name
Test status
Simulation time 124966079 ps
CPU time 0.79 seconds
Started Jul 20 06:27:16 PM PDT 24
Finished Jul 20 06:27:21 PM PDT 24
Peak memory 206628 kb
Host smart-943a5ee1-a9f6-43bf-bc14-0082f9fb91f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25213
84829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.2521384829
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.636642447
Short name T1537
Test name
Test status
Simulation time 16689854631 ps
CPU time 39.3 seconds
Started Jul 20 06:27:17 PM PDT 24
Finished Jul 20 06:28:00 PM PDT 24
Peak memory 206904 kb
Host smart-c4b4d624-8bba-4c2f-9f47-7ba80a7d2a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63664
2447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.636642447
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.1896432789
Short name T364
Test name
Test status
Simulation time 164392740 ps
CPU time 0.77 seconds
Started Jul 20 06:27:21 PM PDT 24
Finished Jul 20 06:27:24 PM PDT 24
Peak memory 206596 kb
Host smart-bd0a5fd7-45bb-4f44-ae5a-969b192e114b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18964
32789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.1896432789
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.2989766780
Short name T1476
Test name
Test status
Simulation time 224732027 ps
CPU time 0.97 seconds
Started Jul 20 06:27:22 PM PDT 24
Finished Jul 20 06:27:25 PM PDT 24
Peak memory 206636 kb
Host smart-59d4999b-5334-48b1-a61d-318f0579d8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29897
66780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.2989766780
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3882351609
Short name T1991
Test name
Test status
Simulation time 203094949 ps
CPU time 0.88 seconds
Started Jul 20 06:27:31 PM PDT 24
Finished Jul 20 06:27:33 PM PDT 24
Peak memory 206660 kb
Host smart-f1e16c55-349d-4481-aa8f-0220743dc2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38823
51609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3882351609
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.3474893131
Short name T724
Test name
Test status
Simulation time 195871090 ps
CPU time 0.88 seconds
Started Jul 20 06:27:27 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 206640 kb
Host smart-c8649214-c6f9-4af6-896a-57536fa6351e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34748
93131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.3474893131
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.4157539583
Short name T549
Test name
Test status
Simulation time 134895918 ps
CPU time 0.78 seconds
Started Jul 20 06:27:23 PM PDT 24
Finished Jul 20 06:27:26 PM PDT 24
Peak memory 206628 kb
Host smart-4f5d58cb-db7d-4d11-aa7b-c396793dadac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41575
39583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.4157539583
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.175857127
Short name T567
Test name
Test status
Simulation time 155886995 ps
CPU time 0.83 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:27 PM PDT 24
Peak memory 206648 kb
Host smart-a18c04e6-a9fa-4dbc-ae8e-3c1c34e79f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17585
7127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.175857127
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.2088377407
Short name T2232
Test name
Test status
Simulation time 157388621 ps
CPU time 0.81 seconds
Started Jul 20 06:27:35 PM PDT 24
Finished Jul 20 06:27:37 PM PDT 24
Peak memory 206652 kb
Host smart-88fe8ba8-4c98-4b7b-8bd4-a8033302c4d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20883
77407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.2088377407
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.186512827
Short name T685
Test name
Test status
Simulation time 190793539 ps
CPU time 0.91 seconds
Started Jul 20 06:27:27 PM PDT 24
Finished Jul 20 06:27:30 PM PDT 24
Peak memory 206640 kb
Host smart-8f18623c-2c86-4e8f-aa8b-3b30c3d693ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18651
2827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.186512827
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2596850059
Short name T1238
Test name
Test status
Simulation time 2947718176 ps
CPU time 28.48 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:56 PM PDT 24
Peak memory 206920 kb
Host smart-dc33f8b4-8390-4e40-a956-90d64a8a6291
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2596850059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2596850059
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.78892383
Short name T1927
Test name
Test status
Simulation time 150517325 ps
CPU time 0.77 seconds
Started Jul 20 06:27:24 PM PDT 24
Finished Jul 20 06:27:28 PM PDT 24
Peak memory 206656 kb
Host smart-821cbee5-b266-4a4a-9670-517f3886ec90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78892
383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.78892383
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.406102814
Short name T311
Test name
Test status
Simulation time 175823003 ps
CPU time 0.82 seconds
Started Jul 20 06:27:30 PM PDT 24
Finished Jul 20 06:27:32 PM PDT 24
Peak memory 206644 kb
Host smart-dc0ada1b-2057-4baa-8e05-34b1ecfc52d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40610
2814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.406102814
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.308160895
Short name T335
Test name
Test status
Simulation time 782379334 ps
CPU time 1.77 seconds
Started Jul 20 06:27:25 PM PDT 24
Finished Jul 20 06:27:29 PM PDT 24
Peak memory 206788 kb
Host smart-d2bc934b-84c0-406b-8640-c03a93aea77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30816
0895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.308160895
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1810213965
Short name T1108
Test name
Test status
Simulation time 3600001554 ps
CPU time 34.82 seconds
Started Jul 20 06:27:25 PM PDT 24
Finished Jul 20 06:28:02 PM PDT 24
Peak memory 206924 kb
Host smart-9ac27972-1422-480b-a7a9-d5d893226906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18102
13965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1810213965
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.2575092269
Short name T433
Test name
Test status
Simulation time 35161979 ps
CPU time 0.73 seconds
Started Jul 20 06:20:10 PM PDT 24
Finished Jul 20 06:20:12 PM PDT 24
Peak memory 206700 kb
Host smart-081edd4d-fbc3-4e66-8e99-1a3286c307e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2575092269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.2575092269
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.2406587057
Short name T1974
Test name
Test status
Simulation time 4386022992 ps
CPU time 5.85 seconds
Started Jul 20 06:19:52 PM PDT 24
Finished Jul 20 06:20:00 PM PDT 24
Peak memory 206828 kb
Host smart-5c713564-a04a-4295-b7c6-d7056688bccb
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2406587057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.2406587057
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.2119793799
Short name T2302
Test name
Test status
Simulation time 13353829531 ps
CPU time 12.54 seconds
Started Jul 20 06:19:53 PM PDT 24
Finished Jul 20 06:20:07 PM PDT 24
Peak memory 206752 kb
Host smart-af1af80b-33c0-41f1-a936-e80b15425557
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2119793799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.2119793799
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.224982866
Short name T601
Test name
Test status
Simulation time 23312548932 ps
CPU time 23 seconds
Started Jul 20 06:19:48 PM PDT 24
Finished Jul 20 06:20:11 PM PDT 24
Peak memory 206888 kb
Host smart-b452a75b-817b-4062-b771-a9078534f326
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=224982866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.224982866
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1929326920
Short name T1750
Test name
Test status
Simulation time 210770398 ps
CPU time 0.86 seconds
Started Jul 20 06:19:52 PM PDT 24
Finished Jul 20 06:19:54 PM PDT 24
Peak memory 206656 kb
Host smart-1da01495-0a75-4507-ac60-24e665961e00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19293
26920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1929326920
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.3868951888
Short name T517
Test name
Test status
Simulation time 151756838 ps
CPU time 0.77 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:53 PM PDT 24
Peak memory 206660 kb
Host smart-7226018d-01af-4497-ba45-e22e41027e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38689
51888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.3868951888
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.2793040590
Short name T2469
Test name
Test status
Simulation time 290401828 ps
CPU time 1.01 seconds
Started Jul 20 06:19:52 PM PDT 24
Finished Jul 20 06:19:55 PM PDT 24
Peak memory 206644 kb
Host smart-d55b8f24-50c4-4796-bdc8-b75701662cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27930
40590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.2793040590
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.2071950002
Short name T865
Test name
Test status
Simulation time 1210830402 ps
CPU time 2.74 seconds
Started Jul 20 06:19:48 PM PDT 24
Finished Jul 20 06:19:52 PM PDT 24
Peak memory 206792 kb
Host smart-1f43641c-8d01-40d1-98d0-84072f667d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20719
50002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.2071950002
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.190894610
Short name T2149
Test name
Test status
Simulation time 14475019693 ps
CPU time 27.22 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:31 PM PDT 24
Peak memory 206428 kb
Host smart-29f5795d-4546-4f46-a432-589002882641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19089
4610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.190894610
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1964764052
Short name T1298
Test name
Test status
Simulation time 358643757 ps
CPU time 1.22 seconds
Started Jul 20 06:19:51 PM PDT 24
Finished Jul 20 06:19:54 PM PDT 24
Peak memory 206656 kb
Host smart-f54749bb-2cc0-456e-b0c6-d12d11639a91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19647
64052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1964764052
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.426999529
Short name T2295
Test name
Test status
Simulation time 169872193 ps
CPU time 0.78 seconds
Started Jul 20 06:19:52 PM PDT 24
Finished Jul 20 06:19:54 PM PDT 24
Peak memory 206648 kb
Host smart-4d38d0ec-7c30-4b73-ac44-d81cfebaa3da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42699
9529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.426999529
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.4213130292
Short name T1905
Test name
Test status
Simulation time 99700797 ps
CPU time 0.73 seconds
Started Jul 20 06:19:53 PM PDT 24
Finished Jul 20 06:19:55 PM PDT 24
Peak memory 206644 kb
Host smart-0892cb01-eba4-45a1-9a2e-d4d1271ebd1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42131
30292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.4213130292
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.3391516321
Short name T1084
Test name
Test status
Simulation time 791925228 ps
CPU time 2.09 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:06 PM PDT 24
Peak memory 206748 kb
Host smart-f04b7bf6-e777-413c-92a8-b8532535fe67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33915
16321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.3391516321
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.242411563
Short name T2364
Test name
Test status
Simulation time 235342109 ps
CPU time 1.67 seconds
Started Jul 20 06:19:53 PM PDT 24
Finished Jul 20 06:19:56 PM PDT 24
Peak memory 206796 kb
Host smart-d129364d-3769-40a0-9cca-597eab7f1077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24241
1563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.242411563
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3241418831
Short name T533
Test name
Test status
Simulation time 178693409 ps
CPU time 0.83 seconds
Started Jul 20 06:20:03 PM PDT 24
Finished Jul 20 06:20:06 PM PDT 24
Peak memory 206628 kb
Host smart-bbbfe63b-5905-467a-b2de-f43626838144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32414
18831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3241418831
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.2319113306
Short name T1883
Test name
Test status
Simulation time 159465542 ps
CPU time 0.78 seconds
Started Jul 20 06:20:01 PM PDT 24
Finished Jul 20 06:20:04 PM PDT 24
Peak memory 206620 kb
Host smart-f39f9c1c-df02-4efc-9a03-35cc7e098d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23191
13306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.2319113306
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.1328575227
Short name T1123
Test name
Test status
Simulation time 213794029 ps
CPU time 0.86 seconds
Started Jul 20 06:19:59 PM PDT 24
Finished Jul 20 06:20:01 PM PDT 24
Peak memory 206660 kb
Host smart-1aed16ba-75b8-4ea4-8309-d5f6048b86e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13285
75227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.1328575227
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.4091508787
Short name T2665
Test name
Test status
Simulation time 6235510703 ps
CPU time 182.8 seconds
Started Jul 20 06:19:59 PM PDT 24
Finished Jul 20 06:23:03 PM PDT 24
Peak memory 206884 kb
Host smart-51e9b7ef-3504-410e-af99-a40a0dd4274f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4091508787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.4091508787
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.1618480179
Short name T2471
Test name
Test status
Simulation time 5902775744 ps
CPU time 21.62 seconds
Started Jul 20 06:20:01 PM PDT 24
Finished Jul 20 06:20:24 PM PDT 24
Peak memory 206868 kb
Host smart-8beeccde-285f-4dd5-9b08-168d73472793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16184
80179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.1618480179
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.3797103642
Short name T1208
Test name
Test status
Simulation time 202349448 ps
CPU time 0.88 seconds
Started Jul 20 06:20:00 PM PDT 24
Finished Jul 20 06:20:03 PM PDT 24
Peak memory 206652 kb
Host smart-bcb48e89-64bf-4894-a711-8265c932faff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37971
03642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.3797103642
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.276810476
Short name T1509
Test name
Test status
Simulation time 23317984663 ps
CPU time 22.84 seconds
Started Jul 20 06:19:59 PM PDT 24
Finished Jul 20 06:20:23 PM PDT 24
Peak memory 206776 kb
Host smart-f3ee3a42-84b9-4818-80dd-eaa5f1097f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27681
0476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.276810476
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.2503164743
Short name T2272
Test name
Test status
Simulation time 3285738334 ps
CPU time 3.81 seconds
Started Jul 20 06:19:59 PM PDT 24
Finished Jul 20 06:20:04 PM PDT 24
Peak memory 206712 kb
Host smart-a3c4f31a-bc3a-414a-8aac-7f798162dd54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25031
64743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.2503164743
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.3021768607
Short name T2089
Test name
Test status
Simulation time 9231791532 ps
CPU time 265.6 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:24:29 PM PDT 24
Peak memory 206952 kb
Host smart-ddedfc10-0470-4079-b8d7-8e66a1b21398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30217
68607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.3021768607
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.1711656381
Short name T1869
Test name
Test status
Simulation time 5906698410 ps
CPU time 40.56 seconds
Started Jul 20 06:19:57 PM PDT 24
Finished Jul 20 06:20:38 PM PDT 24
Peak memory 206912 kb
Host smart-80c75756-8e13-4c1c-8574-731565c68569
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1711656381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.1711656381
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.2823477678
Short name T2524
Test name
Test status
Simulation time 239653046 ps
CPU time 0.99 seconds
Started Jul 20 06:20:00 PM PDT 24
Finished Jul 20 06:20:03 PM PDT 24
Peak memory 206640 kb
Host smart-c82468d1-b6a1-4684-9281-058af9e750db
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2823477678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.2823477678
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.4224052848
Short name T1321
Test name
Test status
Simulation time 190223781 ps
CPU time 0.84 seconds
Started Jul 20 06:20:03 PM PDT 24
Finished Jul 20 06:20:05 PM PDT 24
Peak memory 206640 kb
Host smart-5387d241-663c-4a0a-99f4-e33e43f3d0ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42240
52848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.4224052848
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.1606994312
Short name T2115
Test name
Test status
Simulation time 3465077167 ps
CPU time 31.69 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:36 PM PDT 24
Peak memory 206868 kb
Host smart-7bbb5a4f-f010-4934-afe8-9091d4467894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16069
94312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.1606994312
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1580026872
Short name T855
Test name
Test status
Simulation time 4664685157 ps
CPU time 34.76 seconds
Started Jul 20 06:19:59 PM PDT 24
Finished Jul 20 06:20:34 PM PDT 24
Peak memory 206896 kb
Host smart-ef9160e2-2435-4ffe-9aa1-d806da8a87de
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1580026872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1580026872
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1613572100
Short name T1435
Test name
Test status
Simulation time 164969302 ps
CPU time 0.81 seconds
Started Jul 20 06:19:58 PM PDT 24
Finished Jul 20 06:20:00 PM PDT 24
Peak memory 206648 kb
Host smart-12506a5c-4c3b-4c86-b74b-b02ea327fcf4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1613572100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1613572100
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.341368219
Short name T2372
Test name
Test status
Simulation time 217405275 ps
CPU time 0.85 seconds
Started Jul 20 06:20:00 PM PDT 24
Finished Jul 20 06:20:02 PM PDT 24
Peak memory 206696 kb
Host smart-c7bc97a3-0247-4d0e-b3e5-cf056855c9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34136
8219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.341368219
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.26502957
Short name T140
Test name
Test status
Simulation time 163265426 ps
CPU time 0.79 seconds
Started Jul 20 06:19:58 PM PDT 24
Finished Jul 20 06:19:59 PM PDT 24
Peak memory 206648 kb
Host smart-89d858cf-dd56-4f47-903a-26dcec0b0622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26502
957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.26502957
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3406409790
Short name T1215
Test name
Test status
Simulation time 172221707 ps
CPU time 0.82 seconds
Started Jul 20 06:20:00 PM PDT 24
Finished Jul 20 06:20:01 PM PDT 24
Peak memory 206632 kb
Host smart-ba7ff04a-a392-408a-9e6c-e236db512655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34064
09790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3406409790
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.1053594134
Short name T2726
Test name
Test status
Simulation time 184714943 ps
CPU time 0.93 seconds
Started Jul 20 06:20:00 PM PDT 24
Finished Jul 20 06:20:02 PM PDT 24
Peak memory 206660 kb
Host smart-d4b0d35c-4f26-41c1-929b-e54367e3c39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10535
94134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.1053594134
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.4009535405
Short name T2024
Test name
Test status
Simulation time 172968747 ps
CPU time 0.88 seconds
Started Jul 20 06:20:00 PM PDT 24
Finished Jul 20 06:20:02 PM PDT 24
Peak memory 206648 kb
Host smart-acd7393e-0a7b-486f-93d2-ffc49e78e37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40095
35405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.4009535405
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1532492935
Short name T2454
Test name
Test status
Simulation time 197293402 ps
CPU time 0.8 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:04 PM PDT 24
Peak memory 206640 kb
Host smart-58cc2bed-56bf-4141-8240-0f325ff3fedf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15324
92935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1532492935
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.2631334581
Short name T2398
Test name
Test status
Simulation time 210103669 ps
CPU time 0.94 seconds
Started Jul 20 06:19:59 PM PDT 24
Finished Jul 20 06:20:00 PM PDT 24
Peak memory 206656 kb
Host smart-c406871c-2ece-423f-9549-c9e7a798ab4b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2631334581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.2631334581
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.2166617406
Short name T1397
Test name
Test status
Simulation time 145788856 ps
CPU time 0.78 seconds
Started Jul 20 06:20:00 PM PDT 24
Finished Jul 20 06:20:02 PM PDT 24
Peak memory 206640 kb
Host smart-c3b1cf07-6ee9-49ad-ac2e-dff7af16b0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21666
17406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.2166617406
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.2094220614
Short name T2609
Test name
Test status
Simulation time 58443150 ps
CPU time 0.69 seconds
Started Jul 20 06:20:01 PM PDT 24
Finished Jul 20 06:20:04 PM PDT 24
Peak memory 206652 kb
Host smart-6e4d0fa8-054c-41e3-b89f-7ba8833e2d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20942
20614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.2094220614
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3182087855
Short name T1630
Test name
Test status
Simulation time 9394657575 ps
CPU time 23.91 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:27 PM PDT 24
Peak memory 206908 kb
Host smart-77db0a29-b9e9-4ec7-ab34-40429de9d52d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31820
87855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3182087855
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.4083546622
Short name T1859
Test name
Test status
Simulation time 194825940 ps
CPU time 0.84 seconds
Started Jul 20 06:20:01 PM PDT 24
Finished Jul 20 06:20:03 PM PDT 24
Peak memory 206660 kb
Host smart-00b445fe-52eb-4f14-b90b-808d4d6caa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40835
46622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.4083546622
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.767835655
Short name T171
Test name
Test status
Simulation time 5852657624 ps
CPU time 57.38 seconds
Started Jul 20 06:20:09 PM PDT 24
Finished Jul 20 06:21:08 PM PDT 24
Peak memory 206864 kb
Host smart-fb79b482-e187-4547-9539-7bac3d76536b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=767835655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.767835655
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.2660486988
Short name T1280
Test name
Test status
Simulation time 8884854741 ps
CPU time 56.03 seconds
Started Jul 20 06:20:06 PM PDT 24
Finished Jul 20 06:21:03 PM PDT 24
Peak memory 206884 kb
Host smart-fccb0a7d-34d4-4ebc-8634-c4ac7a46008d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2660486988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.2660486988
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3474407201
Short name T850
Test name
Test status
Simulation time 17538446100 ps
CPU time 376.75 seconds
Started Jul 20 06:20:10 PM PDT 24
Finished Jul 20 06:26:28 PM PDT 24
Peak memory 206932 kb
Host smart-f2a9ff9f-7d8b-4b8d-9a91-1b3beaad3edb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3474407201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3474407201
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.1365736756
Short name T1649
Test name
Test status
Simulation time 315234509 ps
CPU time 0.95 seconds
Started Jul 20 06:20:02 PM PDT 24
Finished Jul 20 06:20:05 PM PDT 24
Peak memory 206648 kb
Host smart-e2543a1e-1ba8-4cca-bbab-8a93419c256c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13657
36756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.1365736756
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.1815998224
Short name T2059
Test name
Test status
Simulation time 185517853 ps
CPU time 0.8 seconds
Started Jul 20 06:20:09 PM PDT 24
Finished Jul 20 06:20:12 PM PDT 24
Peak memory 206628 kb
Host smart-cde66037-6538-42e7-b873-c91ee78c906b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18159
98224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.1815998224
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.15769579
Short name T2565
Test name
Test status
Simulation time 171344823 ps
CPU time 0.81 seconds
Started Jul 20 06:20:09 PM PDT 24
Finished Jul 20 06:20:12 PM PDT 24
Peak memory 206656 kb
Host smart-f283a720-ecef-4cd4-b901-6223ac8f1c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15769
579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.15769579
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.954131261
Short name T1504
Test name
Test status
Simulation time 240587271 ps
CPU time 0.88 seconds
Started Jul 20 06:20:07 PM PDT 24
Finished Jul 20 06:20:09 PM PDT 24
Peak memory 206632 kb
Host smart-721a4c91-c63d-4766-9af9-63e2b8ad2819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95413
1261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.954131261
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.4257771838
Short name T2439
Test name
Test status
Simulation time 150461557 ps
CPU time 0.79 seconds
Started Jul 20 06:20:16 PM PDT 24
Finished Jul 20 06:20:18 PM PDT 24
Peak memory 206608 kb
Host smart-a582e800-5b06-4397-87a3-121270c97bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42577
71838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.4257771838
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.2119902525
Short name T1475
Test name
Test status
Simulation time 263065428 ps
CPU time 0.95 seconds
Started Jul 20 06:20:09 PM PDT 24
Finished Jul 20 06:20:12 PM PDT 24
Peak memory 206620 kb
Host smart-b0647059-892f-4885-aaa4-b10e1a08f0d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21199
02525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.2119902525
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.1005981324
Short name T842
Test name
Test status
Simulation time 6208177908 ps
CPU time 45.59 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206820 kb
Host smart-f3d49b33-ea62-4834-abb3-9f5effd26511
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1005981324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.1005981324
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.99080553
Short name T879
Test name
Test status
Simulation time 194840956 ps
CPU time 0.85 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:10 PM PDT 24
Peak memory 206628 kb
Host smart-539fd085-6736-4ab4-b18f-05ebd4b9fe6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99080
553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.99080553
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.44176620
Short name T871
Test name
Test status
Simulation time 153367767 ps
CPU time 0.77 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:10 PM PDT 24
Peak memory 206652 kb
Host smart-139694a2-7124-4853-a945-0db850bded96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44176
620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.44176620
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.3016241327
Short name T2322
Test name
Test status
Simulation time 330353324 ps
CPU time 1.1 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:10 PM PDT 24
Peak memory 206656 kb
Host smart-4ee14bab-fee0-49b7-b94e-bd6900f62b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30162
41327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.3016241327
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.1249156682
Short name T1551
Test name
Test status
Simulation time 5600893215 ps
CPU time 151.11 seconds
Started Jul 20 06:20:06 PM PDT 24
Finished Jul 20 06:22:38 PM PDT 24
Peak memory 206852 kb
Host smart-77340284-95b9-4709-b946-c0f84bf24765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12491
56682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.1249156682
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1611791623
Short name T2199
Test name
Test status
Simulation time 36385468 ps
CPU time 0.67 seconds
Started Jul 20 06:20:24 PM PDT 24
Finished Jul 20 06:20:25 PM PDT 24
Peak memory 206632 kb
Host smart-2c2af25c-9a4e-415b-944b-2d0db88a54c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1611791623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1611791623
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.244218855
Short name T1893
Test name
Test status
Simulation time 3830845051 ps
CPU time 4.45 seconds
Started Jul 20 06:20:07 PM PDT 24
Finished Jul 20 06:20:13 PM PDT 24
Peak memory 206812 kb
Host smart-b1f9f93b-0cf5-4365-baca-780673449856
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=244218855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.244218855
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.879530893
Short name T792
Test name
Test status
Simulation time 13527610348 ps
CPU time 13.4 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:23 PM PDT 24
Peak memory 206900 kb
Host smart-4d80acb3-a2bd-4ea5-bf71-c00c5dad23c3
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=879530893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.879530893
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.471909717
Short name T2713
Test name
Test status
Simulation time 23407310107 ps
CPU time 21.52 seconds
Started Jul 20 06:20:06 PM PDT 24
Finished Jul 20 06:20:28 PM PDT 24
Peak memory 206872 kb
Host smart-511463b0-3303-4904-b0e5-e304d2e9ce0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=471909717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.471909717
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1248308063
Short name T1528
Test name
Test status
Simulation time 177984909 ps
CPU time 0.8 seconds
Started Jul 20 06:20:06 PM PDT 24
Finished Jul 20 06:20:08 PM PDT 24
Peak memory 206704 kb
Host smart-e03ca4c1-16cd-4d93-92e2-5b41c7ac9374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12483
08063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1248308063
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.359651299
Short name T979
Test name
Test status
Simulation time 186579502 ps
CPU time 0.82 seconds
Started Jul 20 06:20:16 PM PDT 24
Finished Jul 20 06:20:18 PM PDT 24
Peak memory 206620 kb
Host smart-bfaecdb9-4a61-40b7-a8fc-21109a9030ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35965
1299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.359651299
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.4039721335
Short name T2400
Test name
Test status
Simulation time 640333917 ps
CPU time 1.72 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:11 PM PDT 24
Peak memory 206788 kb
Host smart-50500fe8-867e-4d5b-9ae2-43603e74b432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40397
21335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.4039721335
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2513943129
Short name T1844
Test name
Test status
Simulation time 559626981 ps
CPU time 1.54 seconds
Started Jul 20 06:20:07 PM PDT 24
Finished Jul 20 06:20:10 PM PDT 24
Peak memory 206648 kb
Host smart-7546b0ba-7587-4387-a855-bc0df2307950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25139
43129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2513943129
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.3547552151
Short name T1492
Test name
Test status
Simulation time 5535766151 ps
CPU time 11.94 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206828 kb
Host smart-7b1e6090-4ac1-4395-9872-ce3f0a99b6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35475
52151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.3547552151
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.894037006
Short name T1715
Test name
Test status
Simulation time 398909516 ps
CPU time 1.19 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:11 PM PDT 24
Peak memory 206632 kb
Host smart-d813cc30-83f8-46f7-86af-c04aff4c6df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89403
7006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.894037006
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2944977520
Short name T2288
Test name
Test status
Simulation time 133547263 ps
CPU time 0.75 seconds
Started Jul 20 06:20:09 PM PDT 24
Finished Jul 20 06:20:11 PM PDT 24
Peak memory 206660 kb
Host smart-7982f160-f86a-4354-bf10-777dc9d0894c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29449
77520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2944977520
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.2339009014
Short name T552
Test name
Test status
Simulation time 43799999 ps
CPU time 0.71 seconds
Started Jul 20 06:20:10 PM PDT 24
Finished Jul 20 06:20:12 PM PDT 24
Peak memory 206640 kb
Host smart-432d66c6-0ff6-4b28-8075-870d6afd3565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23390
09014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.2339009014
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1181471841
Short name T2179
Test name
Test status
Simulation time 984325960 ps
CPU time 2.25 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:12 PM PDT 24
Peak memory 206788 kb
Host smart-9588818b-7d66-4b60-a673-c87e8a391c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11814
71841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1181471841
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.3286275049
Short name T1415
Test name
Test status
Simulation time 335917695 ps
CPU time 2.26 seconds
Started Jul 20 06:20:16 PM PDT 24
Finished Jul 20 06:20:19 PM PDT 24
Peak memory 206704 kb
Host smart-3715dd2c-8a02-4599-99c6-87a1e6377113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32862
75049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.3286275049
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3384917658
Short name T2683
Test name
Test status
Simulation time 177119396 ps
CPU time 0.89 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:11 PM PDT 24
Peak memory 206644 kb
Host smart-2c089e8d-4cbc-443a-8c80-c063ac63d302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33849
17658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3384917658
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.2241637025
Short name T1722
Test name
Test status
Simulation time 152025057 ps
CPU time 0.77 seconds
Started Jul 20 06:20:10 PM PDT 24
Finished Jul 20 06:20:13 PM PDT 24
Peak memory 206652 kb
Host smart-e8778f54-7097-42aa-b3e4-43f451fbab04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22416
37025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.2241637025
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2782613685
Short name T374
Test name
Test status
Simulation time 189256900 ps
CPU time 0.87 seconds
Started Jul 20 06:20:17 PM PDT 24
Finished Jul 20 06:20:19 PM PDT 24
Peak memory 206620 kb
Host smart-2b9149a3-80d9-4392-a315-2302c622c62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27826
13685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2782613685
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.112162025
Short name T2075
Test name
Test status
Simulation time 5625718525 ps
CPU time 40.07 seconds
Started Jul 20 06:20:07 PM PDT 24
Finished Jul 20 06:20:49 PM PDT 24
Peak memory 206852 kb
Host smart-51574a51-1fb4-4958-873b-24991879c1be
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=112162025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.112162025
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2548299189
Short name T2497
Test name
Test status
Simulation time 213174828 ps
CPU time 0.87 seconds
Started Jul 20 06:20:10 PM PDT 24
Finished Jul 20 06:20:12 PM PDT 24
Peak memory 206652 kb
Host smart-000845ac-8b4b-451d-81be-ed9a721c30bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25482
99189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2548299189
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.4041547052
Short name T2214
Test name
Test status
Simulation time 23310911450 ps
CPU time 23.98 seconds
Started Jul 20 06:20:10 PM PDT 24
Finished Jul 20 06:20:35 PM PDT 24
Peak memory 206780 kb
Host smart-15488913-3573-4e53-8ae4-da5f884301f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40415
47052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.4041547052
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.2986713720
Short name T1817
Test name
Test status
Simulation time 3269285097 ps
CPU time 3.7 seconds
Started Jul 20 06:20:10 PM PDT 24
Finished Jul 20 06:20:16 PM PDT 24
Peak memory 206716 kb
Host smart-4d9f6110-8c7f-400f-9ce8-f19b601e6830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29867
13720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.2986713720
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.686491523
Short name T579
Test name
Test status
Simulation time 13278430241 ps
CPU time 121.67 seconds
Started Jul 20 06:20:09 PM PDT 24
Finished Jul 20 06:22:13 PM PDT 24
Peak memory 206928 kb
Host smart-da8bd448-37dc-4895-9493-030272053949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68649
1523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.686491523
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3500086399
Short name T907
Test name
Test status
Simulation time 5794142040 ps
CPU time 166.03 seconds
Started Jul 20 06:20:07 PM PDT 24
Finished Jul 20 06:22:54 PM PDT 24
Peak memory 206860 kb
Host smart-c2b2bd30-08ef-4c9b-bfda-e4c07ba9ec27
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3500086399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3500086399
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3359710579
Short name T1292
Test name
Test status
Simulation time 305216640 ps
CPU time 0.95 seconds
Started Jul 20 06:20:08 PM PDT 24
Finished Jul 20 06:20:11 PM PDT 24
Peak memory 206644 kb
Host smart-c43b812b-4b60-4a55-94f0-2d39c5d6de28
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3359710579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3359710579
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.1970518046
Short name T703
Test name
Test status
Simulation time 201196076 ps
CPU time 0.83 seconds
Started Jul 20 06:20:14 PM PDT 24
Finished Jul 20 06:20:15 PM PDT 24
Peak memory 206644 kb
Host smart-e81e4554-c8ac-4ae4-a1b4-1d242fd9c2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19705
18046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.1970518046
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.1799488226
Short name T2441
Test name
Test status
Simulation time 4428909357 ps
CPU time 33.16 seconds
Started Jul 20 06:20:18 PM PDT 24
Finished Jul 20 06:20:52 PM PDT 24
Peak memory 206872 kb
Host smart-83b407f4-0485-4cea-968c-7d995381f24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17994
88226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.1799488226
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.1528792641
Short name T1182
Test name
Test status
Simulation time 3651705210 ps
CPU time 25.74 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:46 PM PDT 24
Peak memory 206872 kb
Host smart-7b3322a4-0e0a-49de-9f2c-7092b1d9b85d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1528792641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.1528792641
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.3622662907
Short name T272
Test name
Test status
Simulation time 157235404 ps
CPU time 0.87 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206644 kb
Host smart-45e26c61-cd0d-45b0-a02f-0d70f70336c8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3622662907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.3622662907
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.392528104
Short name T1300
Test name
Test status
Simulation time 176555389 ps
CPU time 0.87 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:21 PM PDT 24
Peak memory 206648 kb
Host smart-4a649a4f-611a-48c6-bb96-9b54d5abc31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39252
8104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.392528104
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.3273415568
Short name T2224
Test name
Test status
Simulation time 170334048 ps
CPU time 0.86 seconds
Started Jul 20 06:20:17 PM PDT 24
Finished Jul 20 06:20:18 PM PDT 24
Peak memory 206656 kb
Host smart-cf0a2e57-c569-4a74-8721-25ef98b14bb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32734
15568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.3273415568
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2466756468
Short name T903
Test name
Test status
Simulation time 149532857 ps
CPU time 0.83 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:21 PM PDT 24
Peak memory 206648 kb
Host smart-0c1b767d-c525-4e18-99d1-f6e1613b75d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24667
56468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2466756468
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.2833707347
Short name T2208
Test name
Test status
Simulation time 173778931 ps
CPU time 0.82 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206748 kb
Host smart-d047f44c-f99d-4774-b30f-5a6385b67b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28337
07347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.2833707347
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.1307164161
Short name T843
Test name
Test status
Simulation time 242587998 ps
CPU time 0.9 seconds
Started Jul 20 06:20:21 PM PDT 24
Finished Jul 20 06:20:23 PM PDT 24
Peak memory 206636 kb
Host smart-11f08cc6-8b16-42bd-8922-909efd9b3514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13071
64161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.1307164161
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.133193972
Short name T2475
Test name
Test status
Simulation time 145474968 ps
CPU time 0.8 seconds
Started Jul 20 06:20:23 PM PDT 24
Finished Jul 20 06:20:24 PM PDT 24
Peak memory 206640 kb
Host smart-8bb92df8-a5ef-4ce2-8a64-08f249e1b156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13319
3972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.133193972
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.2294837408
Short name T350
Test name
Test status
Simulation time 206796017 ps
CPU time 1.03 seconds
Started Jul 20 06:20:18 PM PDT 24
Finished Jul 20 06:20:21 PM PDT 24
Peak memory 206660 kb
Host smart-989cc0bb-294b-4c93-a8a1-8d6ec560035d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2294837408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.2294837408
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.3956692924
Short name T1344
Test name
Test status
Simulation time 151621375 ps
CPU time 0.79 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206648 kb
Host smart-afd49514-ac54-4931-9661-b880866ce15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39566
92924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.3956692924
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.3198286952
Short name T2055
Test name
Test status
Simulation time 39330248 ps
CPU time 0.66 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:21 PM PDT 24
Peak memory 206656 kb
Host smart-190cf270-7d09-462f-ad69-e77b9ec7ed15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31982
86952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.3198286952
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.1305327028
Short name T2407
Test name
Test status
Simulation time 15930894856 ps
CPU time 37.92 seconds
Started Jul 20 06:20:17 PM PDT 24
Finished Jul 20 06:20:56 PM PDT 24
Peak memory 206960 kb
Host smart-1f12164f-d43e-463a-a2db-3630b19718a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13053
27028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.1305327028
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.4263960672
Short name T502
Test name
Test status
Simulation time 185506758 ps
CPU time 0.82 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206644 kb
Host smart-665db881-a8ce-46a8-b0dc-5a52c588c755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42639
60672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.4263960672
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.633124283
Short name T2361
Test name
Test status
Simulation time 163202507 ps
CPU time 0.84 seconds
Started Jul 20 06:20:17 PM PDT 24
Finished Jul 20 06:20:19 PM PDT 24
Peak memory 206652 kb
Host smart-c9a13a13-8278-4b0c-93df-b096a3fe51a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63312
4283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.633124283
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.940001833
Short name T1717
Test name
Test status
Simulation time 9220132065 ps
CPU time 46.32 seconds
Started Jul 20 06:20:20 PM PDT 24
Finished Jul 20 06:21:08 PM PDT 24
Peak memory 206896 kb
Host smart-20f578b8-b6ee-4b29-95ef-9838d41f9fa0
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=940001833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.940001833
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.2702585078
Short name T2479
Test name
Test status
Simulation time 11357830253 ps
CPU time 204.68 seconds
Started Jul 20 06:20:18 PM PDT 24
Finished Jul 20 06:23:44 PM PDT 24
Peak memory 206928 kb
Host smart-eaa8ddf4-ad2b-43f1-ba82-8a8be2c08a14
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2702585078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.2702585078
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.1508730550
Short name T1870
Test name
Test status
Simulation time 12549852037 ps
CPU time 238.84 seconds
Started Jul 20 06:20:15 PM PDT 24
Finished Jul 20 06:24:15 PM PDT 24
Peak memory 206968 kb
Host smart-cfb8dfb8-e261-4440-a33a-c8157c063d19
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1508730550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.1508730550
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.2881380292
Short name T770
Test name
Test status
Simulation time 226191851 ps
CPU time 0.89 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206508 kb
Host smart-e7a4e7f0-5f0b-462c-8aff-2bb34d445f56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28813
80292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.2881380292
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1724868217
Short name T1483
Test name
Test status
Simulation time 177648950 ps
CPU time 0.93 seconds
Started Jul 20 06:20:17 PM PDT 24
Finished Jul 20 06:20:19 PM PDT 24
Peak memory 206696 kb
Host smart-755fd3a0-d209-41ab-bad4-0266b8457e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
68217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1724868217
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3862129709
Short name T1441
Test name
Test status
Simulation time 258981524 ps
CPU time 0.93 seconds
Started Jul 20 06:20:15 PM PDT 24
Finished Jul 20 06:20:16 PM PDT 24
Peak memory 206664 kb
Host smart-47bf689a-0a41-4f31-9b3e-f792dda826c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38621
29709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3862129709
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1336695330
Short name T668
Test name
Test status
Simulation time 153846577 ps
CPU time 0.81 seconds
Started Jul 20 06:20:20 PM PDT 24
Finished Jul 20 06:20:22 PM PDT 24
Peak memory 206640 kb
Host smart-a3c12ef6-39c2-4bc5-983d-342bd239b131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13366
95330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1336695330
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.3317145417
Short name T390
Test name
Test status
Simulation time 159092585 ps
CPU time 0.82 seconds
Started Jul 20 06:20:18 PM PDT 24
Finished Jul 20 06:20:20 PM PDT 24
Peak memory 206652 kb
Host smart-1b021d88-f570-4507-8bdb-ba78120a8682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
45417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.3317145417
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.923570405
Short name T2715
Test name
Test status
Simulation time 204130559 ps
CPU time 0.91 seconds
Started Jul 20 06:20:17 PM PDT 24
Finished Jul 20 06:20:18 PM PDT 24
Peak memory 206632 kb
Host smart-b9ee6173-dc49-4c83-9040-dddc69bfce3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92357
0405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.923570405
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.3138847992
Short name T2182
Test name
Test status
Simulation time 6181493924 ps
CPU time 175.62 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:23:17 PM PDT 24
Peak memory 206752 kb
Host smart-a8ff6495-5dd9-4d0b-97a0-25c8d59b9dde
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3138847992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.3138847992
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.3164443558
Short name T1977
Test name
Test status
Simulation time 216041870 ps
CPU time 0.87 seconds
Started Jul 20 06:20:18 PM PDT 24
Finished Jul 20 06:20:20 PM PDT 24
Peak memory 206652 kb
Host smart-06727205-8895-49d2-be62-1f78918a13a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31644
43558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.3164443558
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.67679430
Short name T1982
Test name
Test status
Simulation time 221459001 ps
CPU time 0.84 seconds
Started Jul 20 06:20:16 PM PDT 24
Finished Jul 20 06:20:18 PM PDT 24
Peak memory 206648 kb
Host smart-e74e7fda-9a02-4a01-8cb4-2c281c318561
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67679
430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.67679430
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.992210807
Short name T1549
Test name
Test status
Simulation time 204601143 ps
CPU time 0.89 seconds
Started Jul 20 06:20:16 PM PDT 24
Finished Jul 20 06:20:17 PM PDT 24
Peak memory 206632 kb
Host smart-57d252cb-1d53-4e35-a7f0-f31af433a225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99221
0807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.992210807
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3737969501
Short name T565
Test name
Test status
Simulation time 5107639517 ps
CPU time 35.29 seconds
Started Jul 20 06:20:19 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206812 kb
Host smart-f4d56ed5-2b5e-4cbe-bad3-578cd630708b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37379
69501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3737969501
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.1469266201
Short name T1781
Test name
Test status
Simulation time 37294502 ps
CPU time 0.66 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:20:33 PM PDT 24
Peak memory 206696 kb
Host smart-c3b08984-9473-4c96-bb50-b3e5088ba565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1469266201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.1469266201
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.152861248
Short name T7
Test name
Test status
Simulation time 4288032114 ps
CPU time 4.79 seconds
Started Jul 20 06:20:24 PM PDT 24
Finished Jul 20 06:20:30 PM PDT 24
Peak memory 206712 kb
Host smart-3aa8d6e0-fdad-46ff-be70-05d1a08b1e94
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=152861248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.152861248
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.3798228903
Short name T1753
Test name
Test status
Simulation time 13309092412 ps
CPU time 11.68 seconds
Started Jul 20 06:20:24 PM PDT 24
Finished Jul 20 06:20:36 PM PDT 24
Peak memory 206896 kb
Host smart-4439836e-8dc4-4a25-ad27-1eac48c85dc0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3798228903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.3798228903
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.425741357
Short name T686
Test name
Test status
Simulation time 23359310896 ps
CPU time 20.9 seconds
Started Jul 20 06:20:26 PM PDT 24
Finished Jul 20 06:20:48 PM PDT 24
Peak memory 206916 kb
Host smart-ab3f1404-21c1-46b3-bc2f-4fe6c524c1ce
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=425741357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.425741357
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2733067187
Short name T1412
Test name
Test status
Simulation time 147092723 ps
CPU time 0.8 seconds
Started Jul 20 06:20:24 PM PDT 24
Finished Jul 20 06:20:25 PM PDT 24
Peak memory 206644 kb
Host smart-3cb0155c-85c6-43d5-98c7-854d3e8d03df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27330
67187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2733067187
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.3301454218
Short name T2002
Test name
Test status
Simulation time 193865248 ps
CPU time 0.9 seconds
Started Jul 20 06:20:27 PM PDT 24
Finished Jul 20 06:20:29 PM PDT 24
Peak memory 206648 kb
Host smart-248fa4c0-7ef4-4463-ba30-29dd510cc46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33014
54218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.3301454218
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.604707523
Short name T2152
Test name
Test status
Simulation time 188219107 ps
CPU time 0.85 seconds
Started Jul 20 06:20:27 PM PDT 24
Finished Jul 20 06:20:29 PM PDT 24
Peak memory 206664 kb
Host smart-857f8b6f-5c4f-4cf6-9739-302d8427e9d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60470
7523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.604707523
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.2447998876
Short name T1760
Test name
Test status
Simulation time 1694030624 ps
CPU time 3.5 seconds
Started Jul 20 06:20:23 PM PDT 24
Finished Jul 20 06:20:27 PM PDT 24
Peak memory 206736 kb
Host smart-3a93c243-dc3b-4523-b7fc-af3ec14e0d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24479
98876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.2447998876
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.951742234
Short name T2310
Test name
Test status
Simulation time 21080577054 ps
CPU time 41.07 seconds
Started Jul 20 06:20:24 PM PDT 24
Finished Jul 20 06:21:06 PM PDT 24
Peak memory 206992 kb
Host smart-1c80c31d-73a7-4b59-b9f7-dee23a6f0bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95174
2234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.951742234
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.687701627
Short name T1515
Test name
Test status
Simulation time 303840324 ps
CPU time 1.26 seconds
Started Jul 20 06:20:25 PM PDT 24
Finished Jul 20 06:20:27 PM PDT 24
Peak memory 206624 kb
Host smart-11c8b894-aa40-41f5-bac1-7d450422a851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68770
1627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.687701627
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.314069340
Short name T1623
Test name
Test status
Simulation time 140734722 ps
CPU time 0.77 seconds
Started Jul 20 06:20:25 PM PDT 24
Finished Jul 20 06:20:26 PM PDT 24
Peak memory 206628 kb
Host smart-2a546c36-d81a-49fe-80be-945510d997e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31406
9340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.314069340
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.813616816
Short name T2390
Test name
Test status
Simulation time 36312010 ps
CPU time 0.67 seconds
Started Jul 20 06:20:25 PM PDT 24
Finished Jul 20 06:20:27 PM PDT 24
Peak memory 206644 kb
Host smart-723761f8-42e8-43b5-aaae-3134c720448f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81361
6816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.813616816
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.612479432
Short name T645
Test name
Test status
Simulation time 755929455 ps
CPU time 1.91 seconds
Started Jul 20 06:20:26 PM PDT 24
Finished Jul 20 06:20:29 PM PDT 24
Peak memory 206796 kb
Host smart-dad6ac9c-0904-4ad2-a7ba-34fafee5702e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61247
9432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.612479432
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.3880976678
Short name T589
Test name
Test status
Simulation time 259383826 ps
CPU time 1.32 seconds
Started Jul 20 06:20:25 PM PDT 24
Finished Jul 20 06:20:27 PM PDT 24
Peak memory 206864 kb
Host smart-417f2d88-3980-42c6-84a9-708a982e3349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
76678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.3880976678
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.3279357731
Short name T2504
Test name
Test status
Simulation time 162438625 ps
CPU time 0.79 seconds
Started Jul 20 06:20:26 PM PDT 24
Finished Jul 20 06:20:28 PM PDT 24
Peak memory 206652 kb
Host smart-0f48dd65-1242-47ba-86bf-4f0acce95177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32793
57731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.3279357731
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3014702325
Short name T2286
Test name
Test status
Simulation time 145590180 ps
CPU time 0.79 seconds
Started Jul 20 06:20:27 PM PDT 24
Finished Jul 20 06:20:28 PM PDT 24
Peak memory 206656 kb
Host smart-44e85c4e-ebb4-402e-b157-cec0e6874c49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30147
02325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3014702325
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.3114412509
Short name T1510
Test name
Test status
Simulation time 194204766 ps
CPU time 0.87 seconds
Started Jul 20 06:20:26 PM PDT 24
Finished Jul 20 06:20:28 PM PDT 24
Peak memory 206664 kb
Host smart-299e1d4c-e3c4-4fd6-8b06-e81ba72129a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31144
12509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.3114412509
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.1958447030
Short name T77
Test name
Test status
Simulation time 5231829353 ps
CPU time 151.96 seconds
Started Jul 20 06:20:23 PM PDT 24
Finished Jul 20 06:22:55 PM PDT 24
Peak memory 206892 kb
Host smart-e47a8d15-11b5-4efd-a1cb-6674ca915785
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1958447030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.1958447030
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2309354292
Short name T2157
Test name
Test status
Simulation time 6694648570 ps
CPU time 24.72 seconds
Started Jul 20 06:20:26 PM PDT 24
Finished Jul 20 06:20:52 PM PDT 24
Peak memory 206856 kb
Host smart-20f23f83-0a29-4ec2-842d-bc509f0a1a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23093
54292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2309354292
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2870414863
Short name T1245
Test name
Test status
Simulation time 267456253 ps
CPU time 0.95 seconds
Started Jul 20 06:20:25 PM PDT 24
Finished Jul 20 06:20:27 PM PDT 24
Peak memory 206628 kb
Host smart-52be2dbc-a193-43af-862f-91e0dd3ae10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28704
14863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2870414863
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.2221577008
Short name T1685
Test name
Test status
Simulation time 23372828764 ps
CPU time 30.35 seconds
Started Jul 20 06:20:27 PM PDT 24
Finished Jul 20 06:20:58 PM PDT 24
Peak memory 206752 kb
Host smart-5f811d45-c333-4e8a-95f2-72c5c3f09da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22215
77008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.2221577008
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1017976496
Short name T1518
Test name
Test status
Simulation time 3285108994 ps
CPU time 4.51 seconds
Started Jul 20 06:20:27 PM PDT 24
Finished Jul 20 06:20:32 PM PDT 24
Peak memory 206720 kb
Host smart-2fad3ee7-042e-4dd5-816f-47387e5023a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10179
76496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1017976496
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.1127951691
Short name T2481
Test name
Test status
Simulation time 6517377497 ps
CPU time 48.66 seconds
Started Jul 20 06:20:36 PM PDT 24
Finished Jul 20 06:21:26 PM PDT 24
Peak memory 206896 kb
Host smart-aaf1e70e-fd1b-4a01-a70b-883a0bc2e8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11279
51691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.1127951691
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1494549438
Short name T856
Test name
Test status
Simulation time 3258324008 ps
CPU time 29.95 seconds
Started Jul 20 06:20:40 PM PDT 24
Finished Jul 20 06:21:10 PM PDT 24
Peak memory 206900 kb
Host smart-52618cf9-d6db-493f-b336-c4aaefc25e6e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1494549438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1494549438
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.721164006
Short name T507
Test name
Test status
Simulation time 242725404 ps
CPU time 0.91 seconds
Started Jul 20 06:20:31 PM PDT 24
Finished Jul 20 06:20:33 PM PDT 24
Peak memory 206640 kb
Host smart-71fe8d99-e427-4e15-84ec-b932d2a4651b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=721164006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.721164006
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.462635646
Short name T2347
Test name
Test status
Simulation time 205327513 ps
CPU time 0.88 seconds
Started Jul 20 06:20:31 PM PDT 24
Finished Jul 20 06:20:32 PM PDT 24
Peak memory 206640 kb
Host smart-4fbe27b7-c616-4449-a0de-8dca1615b3c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46263
5646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.462635646
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.4146993995
Short name T2197
Test name
Test status
Simulation time 5599921782 ps
CPU time 38.77 seconds
Started Jul 20 06:20:33 PM PDT 24
Finished Jul 20 06:21:12 PM PDT 24
Peak memory 206964 kb
Host smart-98f50062-e27f-4fa7-8adc-1235f7badf2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41469
93995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.4146993995
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.3037816806
Short name T2366
Test name
Test status
Simulation time 7902279679 ps
CPU time 75.96 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:21:49 PM PDT 24
Peak memory 206868 kb
Host smart-9820d77a-0ffe-4947-b5e2-10353d3360eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3037816806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.3037816806
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.4174465001
Short name T2532
Test name
Test status
Simulation time 186379036 ps
CPU time 0.81 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:20:34 PM PDT 24
Peak memory 206672 kb
Host smart-532e0d0b-4075-48e8-b227-1d6c5dfbed43
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4174465001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.4174465001
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.1193426234
Short name T2290
Test name
Test status
Simulation time 148559674 ps
CPU time 0.77 seconds
Started Jul 20 06:20:41 PM PDT 24
Finished Jul 20 06:20:43 PM PDT 24
Peak memory 206464 kb
Host smart-4048103b-aef7-4508-a2b5-7b9d146d7e47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11934
26234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.1193426234
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.2864640837
Short name T115
Test name
Test status
Simulation time 158234596 ps
CPU time 0.77 seconds
Started Jul 20 06:20:36 PM PDT 24
Finished Jul 20 06:20:38 PM PDT 24
Peak memory 206660 kb
Host smart-98cea507-df05-4e3b-944e-3048cf6b6642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28646
40837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.2864640837
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.3322906241
Short name T418
Test name
Test status
Simulation time 174697350 ps
CPU time 0.79 seconds
Started Jul 20 06:20:33 PM PDT 24
Finished Jul 20 06:20:35 PM PDT 24
Peak memory 206648 kb
Host smart-0a534b6c-ced9-4710-8d2d-d1c2369033f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33229
06241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.3322906241
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.303309895
Short name T2100
Test name
Test status
Simulation time 176377748 ps
CPU time 0.84 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:20:33 PM PDT 24
Peak memory 206648 kb
Host smart-81356553-e5b3-4a93-99f6-f3930f04b07b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30330
9895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.303309895
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.55245107
Short name T1558
Test name
Test status
Simulation time 162674945 ps
CPU time 0.82 seconds
Started Jul 20 06:20:37 PM PDT 24
Finished Jul 20 06:20:38 PM PDT 24
Peak memory 206660 kb
Host smart-2a3cfbab-c669-4170-9c2b-4aa858c0ad97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55245
107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.55245107
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1995599805
Short name T442
Test name
Test status
Simulation time 159286646 ps
CPU time 0.86 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:20:33 PM PDT 24
Peak memory 206664 kb
Host smart-63276375-e9f0-497b-9ec0-824f06babc79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19955
99805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1995599805
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.2743401301
Short name T650
Test name
Test status
Simulation time 215635236 ps
CPU time 0.92 seconds
Started Jul 20 06:20:31 PM PDT 24
Finished Jul 20 06:20:33 PM PDT 24
Peak memory 206640 kb
Host smart-66744504-3171-4f63-86a7-cca64e862434
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2743401301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.2743401301
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.1311640965
Short name T854
Test name
Test status
Simulation time 141858060 ps
CPU time 0.74 seconds
Started Jul 20 06:20:33 PM PDT 24
Finished Jul 20 06:20:35 PM PDT 24
Peak memory 206656 kb
Host smart-23ca1532-0e13-4229-94ba-b645d44e3cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13116
40965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.1311640965
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3206997787
Short name T786
Test name
Test status
Simulation time 41967605 ps
CPU time 0.66 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:20:36 PM PDT 24
Peak memory 206632 kb
Host smart-8b323049-fa34-4835-8f7a-50f0ed196305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32069
97787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3206997787
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.4065658134
Short name T273
Test name
Test status
Simulation time 14112689981 ps
CPU time 30.48 seconds
Started Jul 20 06:20:40 PM PDT 24
Finished Jul 20 06:21:11 PM PDT 24
Peak memory 206896 kb
Host smart-41bbf4d1-a672-4471-8bd8-3ac1ea07d0a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40656
58134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.4065658134
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1332692068
Short name T759
Test name
Test status
Simulation time 205451153 ps
CPU time 0.85 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:20:33 PM PDT 24
Peak memory 206652 kb
Host smart-ada64e6b-0526-420f-8f99-aee8d89a4fba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13326
92068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1332692068
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.3367286996
Short name T1165
Test name
Test status
Simulation time 212630926 ps
CPU time 0.87 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:20:34 PM PDT 24
Peak memory 206648 kb
Host smart-db9ec1a4-967d-4e26-8339-978a9716f512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33672
86996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.3367286996
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.1649721976
Short name T2730
Test name
Test status
Simulation time 10026497521 ps
CPU time 54.72 seconds
Started Jul 20 06:20:33 PM PDT 24
Finished Jul 20 06:21:29 PM PDT 24
Peak memory 206956 kb
Host smart-1b190c2d-bc37-49d2-8ae0-86161ff46cd1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1649721976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.1649721976
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.716989876
Short name T163
Test name
Test status
Simulation time 8717253718 ps
CPU time 49.76 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:21:25 PM PDT 24
Peak memory 206844 kb
Host smart-62a5ff25-9e76-4007-8f2e-bcd58a230a47
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=716989876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.716989876
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2499805398
Short name T2336
Test name
Test status
Simulation time 22464638923 ps
CPU time 535.49 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:29:31 PM PDT 24
Peak memory 206932 kb
Host smart-33a9a253-ae5f-4f14-b2ef-a2ea98dd9341
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2499805398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2499805398
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.4254667758
Short name T2714
Test name
Test status
Simulation time 207306806 ps
CPU time 0.93 seconds
Started Jul 20 06:20:33 PM PDT 24
Finished Jul 20 06:20:35 PM PDT 24
Peak memory 206592 kb
Host smart-ae849231-fb64-41fa-b8fd-9bd97cf8faf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42546
67758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.4254667758
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.154245903
Short name T2404
Test name
Test status
Simulation time 178470680 ps
CPU time 0.87 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:20:36 PM PDT 24
Peak memory 206624 kb
Host smart-f96b1c91-78fd-4f22-9618-97035d271c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15424
5903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.154245903
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1931317500
Short name T622
Test name
Test status
Simulation time 140849767 ps
CPU time 0.77 seconds
Started Jul 20 06:20:41 PM PDT 24
Finished Jul 20 06:20:43 PM PDT 24
Peak memory 206448 kb
Host smart-4555ee65-7407-4f98-9421-a9f873e1b6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19313
17500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1931317500
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.3603436263
Short name T2064
Test name
Test status
Simulation time 202512608 ps
CPU time 0.82 seconds
Started Jul 20 06:20:35 PM PDT 24
Finished Jul 20 06:20:37 PM PDT 24
Peak memory 206636 kb
Host smart-17f496de-3a07-4f9d-ae36-026a26f5fec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36034
36263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.3603436263
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.2662887891
Short name T2529
Test name
Test status
Simulation time 164714624 ps
CPU time 0.77 seconds
Started Jul 20 06:20:40 PM PDT 24
Finished Jul 20 06:20:41 PM PDT 24
Peak memory 206640 kb
Host smart-878060be-c9ce-481a-a72c-ba4e9a869bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26628
87891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.2662887891
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3515764442
Short name T2572
Test name
Test status
Simulation time 225809624 ps
CPU time 0.89 seconds
Started Jul 20 06:20:35 PM PDT 24
Finished Jul 20 06:20:37 PM PDT 24
Peak memory 206644 kb
Host smart-4f491d2e-9fcc-45c9-9a79-5a77bbf0cfe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35157
64442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3515764442
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.252305508
Short name T1841
Test name
Test status
Simulation time 3066587385 ps
CPU time 21.2 seconds
Started Jul 20 06:20:35 PM PDT 24
Finished Jul 20 06:20:57 PM PDT 24
Peak memory 206932 kb
Host smart-0a7625f6-5667-4ccd-a7d1-0bd986d4f8d4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=252305508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.252305508
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.1451526365
Short name T2184
Test name
Test status
Simulation time 219495537 ps
CPU time 0.8 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:20:36 PM PDT 24
Peak memory 206636 kb
Host smart-ef53dc5e-f0b7-4dbb-b9f2-ecf3574b3fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14515
26365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.1451526365
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.2404721868
Short name T846
Test name
Test status
Simulation time 156382478 ps
CPU time 0.81 seconds
Started Jul 20 06:20:36 PM PDT 24
Finished Jul 20 06:20:38 PM PDT 24
Peak memory 206640 kb
Host smart-1e5517a1-e81d-4b5a-b966-c56ca4c4bcd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24047
21868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.2404721868
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3627950860
Short name T2593
Test name
Test status
Simulation time 328786754 ps
CPU time 1.04 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:20:36 PM PDT 24
Peak memory 206660 kb
Host smart-64760a1d-1b3c-43c7-b138-d5c0617920c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36279
50860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3627950860
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.3380570081
Short name T520
Test name
Test status
Simulation time 5864336605 ps
CPU time 55.88 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:21:31 PM PDT 24
Peak memory 206924 kb
Host smart-a39b023d-1afe-4937-92c7-98212bef0b70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33805
70081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.3380570081
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.760490978
Short name T1762
Test name
Test status
Simulation time 60615127 ps
CPU time 0.68 seconds
Started Jul 20 06:20:50 PM PDT 24
Finished Jul 20 06:20:51 PM PDT 24
Peak memory 206696 kb
Host smart-e202ea9b-c19e-4d91-9725-a821eee52688
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=760490978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.760490978
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2867503916
Short name T488
Test name
Test status
Simulation time 3809584570 ps
CPU time 4.57 seconds
Started Jul 20 06:20:32 PM PDT 24
Finished Jul 20 06:20:38 PM PDT 24
Peak memory 206692 kb
Host smart-2d6cbad4-0384-45d8-974a-1153419d055c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2867503916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.2867503916
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3900425156
Short name T659
Test name
Test status
Simulation time 13345221507 ps
CPU time 12.01 seconds
Started Jul 20 06:20:36 PM PDT 24
Finished Jul 20 06:20:49 PM PDT 24
Peak memory 206928 kb
Host smart-60c4b113-06ea-42e9-b562-eb69c84142a6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3900425156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3900425156
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.37109244
Short name T2526
Test name
Test status
Simulation time 23377614344 ps
CPU time 28.13 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:21:03 PM PDT 24
Peak memory 206844 kb
Host smart-fcb54d09-20b7-42e3-ad48-9dfa11259e27
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=37109244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.37109244
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.248031680
Short name T1699
Test name
Test status
Simulation time 170592324 ps
CPU time 0.79 seconds
Started Jul 20 06:20:35 PM PDT 24
Finished Jul 20 06:20:37 PM PDT 24
Peak memory 206644 kb
Host smart-7625358a-0cf1-4900-b429-98a29bd9c6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24803
1680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.248031680
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.861670038
Short name T2077
Test name
Test status
Simulation time 194462555 ps
CPU time 0.79 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:20:36 PM PDT 24
Peak memory 206780 kb
Host smart-3fb90dfc-0a95-466b-97fd-91de6379de2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86167
0038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.861670038
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.261192955
Short name T2580
Test name
Test status
Simulation time 451247040 ps
CPU time 1.49 seconds
Started Jul 20 06:20:30 PM PDT 24
Finished Jul 20 06:20:32 PM PDT 24
Peak memory 206760 kb
Host smart-72f14293-7359-4f66-8c64-f94c53b5677b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26119
2955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.261192955
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.389752946
Short name T2171
Test name
Test status
Simulation time 1307212960 ps
CPU time 2.93 seconds
Started Jul 20 06:20:36 PM PDT 24
Finished Jul 20 06:20:40 PM PDT 24
Peak memory 206736 kb
Host smart-caa5e688-d42b-467e-aba8-54bd7d35a22e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38975
2946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.389752946
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1688543128
Short name T1382
Test name
Test status
Simulation time 20653897536 ps
CPU time 39.16 seconds
Started Jul 20 06:20:34 PM PDT 24
Finished Jul 20 06:21:14 PM PDT 24
Peak memory 206896 kb
Host smart-b887cf49-cd9a-4c39-ac14-b30889b57d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16885
43128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1688543128
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1845367688
Short name T2608
Test name
Test status
Simulation time 406950366 ps
CPU time 1.29 seconds
Started Jul 20 06:20:44 PM PDT 24
Finished Jul 20 06:20:46 PM PDT 24
Peak memory 206652 kb
Host smart-6e15c18e-50cb-473f-825d-273964e35349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18453
67688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1845367688
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1534160799
Short name T2251
Test name
Test status
Simulation time 165781558 ps
CPU time 0.84 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:45 PM PDT 24
Peak memory 206656 kb
Host smart-c2e0fa23-2724-4b94-ae7c-e011ccf21c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15341
60799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1534160799
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.1113896300
Short name T889
Test name
Test status
Simulation time 38732202 ps
CPU time 0.62 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:44 PM PDT 24
Peak memory 206616 kb
Host smart-7acc413d-f4bb-42b3-9044-936210ebd4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11138
96300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.1113896300
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1516744022
Short name T1199
Test name
Test status
Simulation time 787307542 ps
CPU time 1.97 seconds
Started Jul 20 06:20:42 PM PDT 24
Finished Jul 20 06:20:44 PM PDT 24
Peak memory 206776 kb
Host smart-c50b3505-a2da-45e0-8be8-ef169600e010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15167
44022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1516744022
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.1916498561
Short name T1613
Test name
Test status
Simulation time 265258984 ps
CPU time 1.61 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:45 PM PDT 24
Peak memory 206796 kb
Host smart-cb768df2-9e2b-470b-837c-32b19af9ccaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19164
98561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.1916498561
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.1037124206
Short name T1758
Test name
Test status
Simulation time 197834520 ps
CPU time 0.92 seconds
Started Jul 20 06:20:42 PM PDT 24
Finished Jul 20 06:20:44 PM PDT 24
Peak memory 206632 kb
Host smart-a4cd610c-ffac-4aa7-81a9-3422a6075eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10371
24206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.1037124206
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.2937177714
Short name T1214
Test name
Test status
Simulation time 186567531 ps
CPU time 0.82 seconds
Started Jul 20 06:20:42 PM PDT 24
Finished Jul 20 06:20:43 PM PDT 24
Peak memory 206656 kb
Host smart-475fded7-8a67-4b4d-aff0-f9e7a5363354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29371
77714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.2937177714
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3914574649
Short name T1018
Test name
Test status
Simulation time 220957474 ps
CPU time 0.88 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:45 PM PDT 24
Peak memory 206652 kb
Host smart-6cf70ccc-a29a-456e-a2e5-51f013cb336c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39145
74649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3914574649
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.2089490125
Short name T210
Test name
Test status
Simulation time 7245357259 ps
CPU time 54.72 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:21:38 PM PDT 24
Peak memory 206876 kb
Host smart-c336a3e1-6777-4a2f-97d4-f3e1d1b452f5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2089490125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.2089490125
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.2408689016
Short name T2056
Test name
Test status
Simulation time 8990841837 ps
CPU time 71.52 seconds
Started Jul 20 06:20:45 PM PDT 24
Finished Jul 20 06:21:57 PM PDT 24
Peak memory 206840 kb
Host smart-bb8accf3-5634-4e04-bde1-6a34f7b58cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24086
89016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.2408689016
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2574222061
Short name T1232
Test name
Test status
Simulation time 217992326 ps
CPU time 0.89 seconds
Started Jul 20 06:20:42 PM PDT 24
Finished Jul 20 06:20:44 PM PDT 24
Peak memory 206648 kb
Host smart-734a466a-10e7-4cfc-8d8e-de0977c85ba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25742
22061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2574222061
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.516958291
Short name T747
Test name
Test status
Simulation time 23323661927 ps
CPU time 22.57 seconds
Started Jul 20 06:20:41 PM PDT 24
Finished Jul 20 06:21:03 PM PDT 24
Peak memory 206780 kb
Host smart-0df3763e-74cd-4616-b96f-80ad51454baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51695
8291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.516958291
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.701582798
Short name T342
Test name
Test status
Simulation time 3323623035 ps
CPU time 3.9 seconds
Started Jul 20 06:20:45 PM PDT 24
Finished Jul 20 06:20:50 PM PDT 24
Peak memory 206712 kb
Host smart-9f7ddcb4-18ca-4c3c-a2af-3a01d3be755e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70158
2798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.701582798
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3782653452
Short name T1059
Test name
Test status
Simulation time 8089395722 ps
CPU time 55.93 seconds
Started Jul 20 06:20:44 PM PDT 24
Finished Jul 20 06:21:40 PM PDT 24
Peak memory 206928 kb
Host smart-bd7a8c6d-c936-40c7-acb7-f74e8c7a2ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37826
53452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3782653452
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.958336082
Short name T162
Test name
Test status
Simulation time 6903352513 ps
CPU time 190 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:23:53 PM PDT 24
Peak memory 206864 kb
Host smart-3a609098-e024-4c4f-afe6-5709a69a20e7
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=958336082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.958336082
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.1431046827
Short name T1620
Test name
Test status
Simulation time 245530989 ps
CPU time 0.95 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:45 PM PDT 24
Peak memory 206648 kb
Host smart-fe774000-5a68-4fa1-9935-1976adb03c3a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1431046827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.1431046827
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3824474965
Short name T307
Test name
Test status
Simulation time 200849606 ps
CPU time 0.87 seconds
Started Jul 20 06:20:41 PM PDT 24
Finished Jul 20 06:20:42 PM PDT 24
Peak memory 206644 kb
Host smart-a86fa97c-cc5c-4d9f-a043-4dc1291b5493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38244
74965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3824474965
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.772932020
Short name T1287
Test name
Test status
Simulation time 5312514678 ps
CPU time 145.7 seconds
Started Jul 20 06:20:44 PM PDT 24
Finished Jul 20 06:23:11 PM PDT 24
Peak memory 206868 kb
Host smart-6f529c89-c201-4590-b3da-29f24263eb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77293
2020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.772932020
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2079037911
Short name T1914
Test name
Test status
Simulation time 6037122865 ps
CPU time 41.13 seconds
Started Jul 20 06:20:44 PM PDT 24
Finished Jul 20 06:21:26 PM PDT 24
Peak memory 206904 kb
Host smart-c34c65a7-80ba-451a-8c30-1f3216742b47
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2079037911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2079037911
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.2970340973
Short name T823
Test name
Test status
Simulation time 166249793 ps
CPU time 0.86 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:44 PM PDT 24
Peak memory 206672 kb
Host smart-b8dac42f-14a3-4147-93fd-5a851104461e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2970340973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.2970340973
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.469107287
Short name T1358
Test name
Test status
Simulation time 148927189 ps
CPU time 0.85 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:44 PM PDT 24
Peak memory 206644 kb
Host smart-c2c360b0-b37e-49b6-a750-d705026ef0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46910
7287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.469107287
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.2122039203
Short name T122
Test name
Test status
Simulation time 214103355 ps
CPU time 0.9 seconds
Started Jul 20 06:20:43 PM PDT 24
Finished Jul 20 06:20:45 PM PDT 24
Peak memory 206664 kb
Host smart-d3d9ef1a-fec3-4134-acb7-3bf3ea9c8afa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21220
39203 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.2122039203
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.414645289
Short name T1538
Test name
Test status
Simulation time 267910559 ps
CPU time 0.94 seconds
Started Jul 20 06:20:41 PM PDT 24
Finished Jul 20 06:20:43 PM PDT 24
Peak memory 206636 kb
Host smart-6ae6331f-13d9-433e-872d-ff4924220240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41464
5289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.414645289
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.2870639450
Short name T1168
Test name
Test status
Simulation time 163750046 ps
CPU time 0.83 seconds
Started Jul 20 06:20:44 PM PDT 24
Finished Jul 20 06:20:46 PM PDT 24
Peak memory 206644 kb
Host smart-88269097-b40f-4394-8208-33a93384cefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28706
39450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.2870639450
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3552810063
Short name T1284
Test name
Test status
Simulation time 178527683 ps
CPU time 0.8 seconds
Started Jul 20 06:20:53 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206608 kb
Host smart-fa488b9e-6800-4353-82e3-7374bbaa68d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35528
10063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3552810063
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.3608533124
Short name T1265
Test name
Test status
Simulation time 209634841 ps
CPU time 0.87 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:20:54 PM PDT 24
Peak memory 206660 kb
Host smart-b6ac3d86-6206-4e0b-8eb0-88fb160e0c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36085
33124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.3608533124
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.1803424264
Short name T1431
Test name
Test status
Simulation time 215633758 ps
CPU time 0.96 seconds
Started Jul 20 06:20:50 PM PDT 24
Finished Jul 20 06:20:52 PM PDT 24
Peak memory 206660 kb
Host smart-c117d57b-c9d0-42cc-abd9-7094074f08ab
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1803424264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.1803424264
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1169618846
Short name T1090
Test name
Test status
Simulation time 146444306 ps
CPU time 0.76 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:20:54 PM PDT 24
Peak memory 206632 kb
Host smart-4945bb27-dce5-4bf6-a823-a4729fd34557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11696
18846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1169618846
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.2763562312
Short name T984
Test name
Test status
Simulation time 40417152 ps
CPU time 0.64 seconds
Started Jul 20 06:20:53 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206604 kb
Host smart-64bbf6ca-8bae-49d3-aab3-00d0f02e1635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27635
62312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.2763562312
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2772923286
Short name T1741
Test name
Test status
Simulation time 24053636204 ps
CPU time 56.8 seconds
Started Jul 20 06:20:47 PM PDT 24
Finished Jul 20 06:21:44 PM PDT 24
Peak memory 215092 kb
Host smart-1046778d-905a-4e15-a718-73b986fab30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27729
23286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2772923286
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1197147337
Short name T1401
Test name
Test status
Simulation time 226855116 ps
CPU time 0.88 seconds
Started Jul 20 06:20:54 PM PDT 24
Finished Jul 20 06:20:56 PM PDT 24
Peak memory 206620 kb
Host smart-064a122c-f475-4ae1-b328-ada3f75a940c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11971
47337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1197147337
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.1213359918
Short name T1965
Test name
Test status
Simulation time 190710193 ps
CPU time 0.85 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:20:53 PM PDT 24
Peak memory 206652 kb
Host smart-d6dc695e-3ab7-4597-af3f-66a063fcfaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12133
59918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.1213359918
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.2632397718
Short name T576
Test name
Test status
Simulation time 13464373098 ps
CPU time 115.46 seconds
Started Jul 20 06:20:49 PM PDT 24
Finished Jul 20 06:22:45 PM PDT 24
Peak memory 206908 kb
Host smart-17ad5694-0dd3-4551-bb26-aa97bf5ac055
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2632397718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.2632397718
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.2541652081
Short name T1875
Test name
Test status
Simulation time 12896238789 ps
CPU time 247.45 seconds
Started Jul 20 06:20:49 PM PDT 24
Finished Jul 20 06:24:57 PM PDT 24
Peak memory 206928 kb
Host smart-53141777-c6a2-41d6-b11a-f4e713d626d5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2541652081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.2541652081
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.92549663
Short name T2722
Test name
Test status
Simulation time 11876030770 ps
CPU time 240.8 seconds
Started Jul 20 06:20:50 PM PDT 24
Finished Jul 20 06:24:52 PM PDT 24
Peak memory 206908 kb
Host smart-35dd2db0-be47-483b-aedc-bc5c6f14b2a3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=92549663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.92549663
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.2189000945
Short name T1508
Test name
Test status
Simulation time 192994278 ps
CPU time 0.85 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206644 kb
Host smart-c7440cea-4f0b-446d-96bf-74a2c7a835c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21890
00945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.2189000945
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.816902012
Short name T2165
Test name
Test status
Simulation time 189537447 ps
CPU time 0.83 seconds
Started Jul 20 06:20:49 PM PDT 24
Finished Jul 20 06:20:50 PM PDT 24
Peak memory 206644 kb
Host smart-da7fb1d1-82ed-4824-936d-f8d7f1d9d721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81690
2012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.816902012
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1674817241
Short name T1195
Test name
Test status
Simulation time 154233181 ps
CPU time 0.75 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:20:53 PM PDT 24
Peak memory 206628 kb
Host smart-d12f36b9-6c74-4798-bac4-355032215926
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16748
17241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1674817241
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.1862167825
Short name T2552
Test name
Test status
Simulation time 149427124 ps
CPU time 0.81 seconds
Started Jul 20 06:20:53 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206588 kb
Host smart-90f5a6b6-18a3-46f0-a1c2-4462a01e17df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18621
67825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.1862167825
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.480571816
Short name T1909
Test name
Test status
Simulation time 149290428 ps
CPU time 0.75 seconds
Started Jul 20 06:20:54 PM PDT 24
Finished Jul 20 06:20:56 PM PDT 24
Peak memory 206600 kb
Host smart-0ea6c961-eddf-420d-930c-407199cdcdf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48057
1816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.480571816
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.4144640518
Short name T572
Test name
Test status
Simulation time 237309581 ps
CPU time 0.91 seconds
Started Jul 20 06:20:54 PM PDT 24
Finished Jul 20 06:20:56 PM PDT 24
Peak memory 206612 kb
Host smart-884241e1-e359-4d55-ab78-74746b50c658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41446
40518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.4144640518
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.2456772965
Short name T1277
Test name
Test status
Simulation time 7221689370 ps
CPU time 197.53 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:24:09 PM PDT 24
Peak memory 206852 kb
Host smart-12bec3be-0f2e-41af-94f4-d0f8af0b3460
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2456772965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.2456772965
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.4148708100
Short name T1437
Test name
Test status
Simulation time 163828549 ps
CPU time 0.79 seconds
Started Jul 20 06:20:54 PM PDT 24
Finished Jul 20 06:20:56 PM PDT 24
Peak memory 206656 kb
Host smart-7a7c9f15-cd46-4cf6-932a-d6490a17a011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41487
08100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.4148708100
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.3727713374
Short name T848
Test name
Test status
Simulation time 164124337 ps
CPU time 0.78 seconds
Started Jul 20 06:20:49 PM PDT 24
Finished Jul 20 06:20:50 PM PDT 24
Peak memory 206640 kb
Host smart-df3b8327-6032-4b24-b9c6-fad875f5f78a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37277
13374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.3727713374
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.2439146535
Short name T2237
Test name
Test status
Simulation time 488877232 ps
CPU time 1.33 seconds
Started Jul 20 06:20:49 PM PDT 24
Finished Jul 20 06:20:51 PM PDT 24
Peak memory 206656 kb
Host smart-8e61bef1-ccbc-4477-baee-61a39583cd77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24391
46535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.2439146535
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.2071117734
Short name T1231
Test name
Test status
Simulation time 7460694096 ps
CPU time 212.84 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:24:26 PM PDT 24
Peak memory 206752 kb
Host smart-4c727704-c15e-4a5f-8ee4-2ab8bcd1ccab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20711
17734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.2071117734
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.3779239792
Short name T1736
Test name
Test status
Simulation time 33052858 ps
CPU time 0.64 seconds
Started Jul 20 06:20:55 PM PDT 24
Finished Jul 20 06:20:57 PM PDT 24
Peak memory 206700 kb
Host smart-d05894ff-da32-4306-b714-02bc4bc29826
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3779239792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.3779239792
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.1524390869
Short name T2560
Test name
Test status
Simulation time 4143172554 ps
CPU time 4.74 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:20:56 PM PDT 24
Peak memory 206692 kb
Host smart-165964f1-176d-479d-8c98-12d868197872
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1524390869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.1524390869
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.172521752
Short name T1619
Test name
Test status
Simulation time 13353614670 ps
CPU time 12.58 seconds
Started Jul 20 06:20:50 PM PDT 24
Finished Jul 20 06:21:04 PM PDT 24
Peak memory 206864 kb
Host smart-2f9a1586-6a3a-460b-a586-a0acfb12487d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=172521752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.172521752
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.83810177
Short name T2607
Test name
Test status
Simulation time 23322073114 ps
CPU time 29.79 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:21:22 PM PDT 24
Peak memory 206728 kb
Host smart-25a64b5c-1bf3-4e8e-9dc0-e5bdad65c96b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=83810177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.83810177
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.1820226738
Short name T2036
Test name
Test status
Simulation time 195136201 ps
CPU time 0.86 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:20:54 PM PDT 24
Peak memory 206600 kb
Host smart-f5e251bf-c653-408f-84fd-1329bf3f6b4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18202
26738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.1820226738
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.3002057321
Short name T1690
Test name
Test status
Simulation time 161020152 ps
CPU time 0.78 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:20:54 PM PDT 24
Peak memory 206528 kb
Host smart-0ae9dab8-74a0-4abb-81cd-f7692955fb4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30020
57321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.3002057321
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.688465609
Short name T894
Test name
Test status
Simulation time 421231171 ps
CPU time 1.27 seconds
Started Jul 20 06:20:54 PM PDT 24
Finished Jul 20 06:20:57 PM PDT 24
Peak memory 206620 kb
Host smart-a87ce23b-92ec-4f8a-912f-3e51fcdb1dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68846
5609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.688465609
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2413226993
Short name T103
Test name
Test status
Simulation time 682129173 ps
CPU time 1.6 seconds
Started Jul 20 06:20:53 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206788 kb
Host smart-6143f8ba-bcaf-4336-84a4-e2c0d5238822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24132
26993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2413226993
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.757626449
Short name T2151
Test name
Test status
Simulation time 22854388233 ps
CPU time 43.85 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:21:36 PM PDT 24
Peak memory 206852 kb
Host smart-bc1308bc-08ba-40dc-be1d-4e50699680f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75762
6449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.757626449
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3124623214
Short name T553
Test name
Test status
Simulation time 407061706 ps
CPU time 1.22 seconds
Started Jul 20 06:20:55 PM PDT 24
Finished Jul 20 06:20:57 PM PDT 24
Peak memory 206652 kb
Host smart-5f9ecb70-072b-482e-a0dd-97d17d192740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31246
23214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3124623214
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1686142988
Short name T1427
Test name
Test status
Simulation time 176649256 ps
CPU time 0.76 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:20:53 PM PDT 24
Peak memory 206656 kb
Host smart-17d4b530-f7d5-493c-8e7e-a72a7fe042d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16861
42988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1686142988
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.274135376
Short name T2222
Test name
Test status
Simulation time 35968244 ps
CPU time 0.68 seconds
Started Jul 20 06:20:51 PM PDT 24
Finished Jul 20 06:20:53 PM PDT 24
Peak memory 206640 kb
Host smart-49b22af8-e1f1-4d68-9555-89fb1d8afd64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27413
5376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.274135376
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.2414042310
Short name T1571
Test name
Test status
Simulation time 957286340 ps
CPU time 2.17 seconds
Started Jul 20 06:20:54 PM PDT 24
Finished Jul 20 06:20:58 PM PDT 24
Peak memory 206748 kb
Host smart-fb0e1ebd-4f34-4c0e-80f0-f32fc886ff4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24140
42310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.2414042310
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.546288600
Short name T385
Test name
Test status
Simulation time 227627857 ps
CPU time 1.32 seconds
Started Jul 20 06:20:53 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206788 kb
Host smart-6e4e0f57-aabc-4b63-8e06-a7d5ba74f6da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54628
8600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.546288600
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.750444481
Short name T454
Test name
Test status
Simulation time 202072023 ps
CPU time 0.87 seconds
Started Jul 20 06:20:53 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206600 kb
Host smart-894fac8c-1b49-4053-ad4b-79bca14b8c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75044
4481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.750444481
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.3526105360
Short name T2547
Test name
Test status
Simulation time 141288888 ps
CPU time 0.74 seconds
Started Jul 20 06:20:53 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206640 kb
Host smart-d6b63682-e6c2-44e8-ae6c-b82ed2a2da76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35261
05360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.3526105360
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.1526110525
Short name T1862
Test name
Test status
Simulation time 181670217 ps
CPU time 0.81 seconds
Started Jul 20 06:20:50 PM PDT 24
Finished Jul 20 06:20:51 PM PDT 24
Peak memory 206656 kb
Host smart-1e688304-8e8d-4858-8ea1-7e52ac47d9e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15261
10525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.1526110525
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.1755093679
Short name T448
Test name
Test status
Simulation time 9529493526 ps
CPU time 31.65 seconds
Started Jul 20 06:20:50 PM PDT 24
Finished Jul 20 06:21:22 PM PDT 24
Peak memory 206868 kb
Host smart-e8419106-b6d9-40ff-8f3c-a4bfc87f4931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17550
93679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.1755093679
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.1793406784
Short name T1387
Test name
Test status
Simulation time 229447263 ps
CPU time 0.9 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:20:55 PM PDT 24
Peak memory 206632 kb
Host smart-8694b53d-20cd-4c0e-ab7f-0fee53ac5eb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17934
06784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.1793406784
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.1933401113
Short name T1704
Test name
Test status
Simulation time 23291528654 ps
CPU time 22.5 seconds
Started Jul 20 06:20:52 PM PDT 24
Finished Jul 20 06:21:16 PM PDT 24
Peak memory 206748 kb
Host smart-74ad4903-eeb1-43fe-9bb4-700b46fb4356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19334
01113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.1933401113
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2045838693
Short name T1500
Test name
Test status
Simulation time 3281044271 ps
CPU time 3.86 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:21:02 PM PDT 24
Peak memory 206764 kb
Host smart-16a2275b-622d-4d12-a96c-fa0c816a0713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20458
38693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2045838693
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.2704800429
Short name T232
Test name
Test status
Simulation time 9647311340 ps
CPU time 271.93 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:25:33 PM PDT 24
Peak memory 207016 kb
Host smart-492633e7-2cc5-4b5b-b870-1317730bc703
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27048
00429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.2704800429
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.2493107101
Short name T1952
Test name
Test status
Simulation time 5053077216 ps
CPU time 147.91 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:23:26 PM PDT 24
Peak memory 206872 kb
Host smart-dd61ef6c-8066-478b-b7d2-3ff4b3f32270
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2493107101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.2493107101
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.1579735847
Short name T713
Test name
Test status
Simulation time 290873796 ps
CPU time 0.93 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:21:02 PM PDT 24
Peak memory 206660 kb
Host smart-3fbe0397-82d5-4429-b453-ed3095020fc3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1579735847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.1579735847
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3876571993
Short name T1225
Test name
Test status
Simulation time 194133134 ps
CPU time 0.89 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:00 PM PDT 24
Peak memory 206660 kb
Host smart-ffd558d3-baee-4757-91b2-037a692b7e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38765
71993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3876571993
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2835473198
Short name T1621
Test name
Test status
Simulation time 3548982489 ps
CPU time 34.82 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:35 PM PDT 24
Peak memory 206932 kb
Host smart-a677fa1f-db1b-4d89-a80f-dc9ca02bb9b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28354
73198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2835473198
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.2023120894
Short name T1147
Test name
Test status
Simulation time 3478770782 ps
CPU time 25.42 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:21:27 PM PDT 24
Peak memory 206868 kb
Host smart-9b762c9f-f5e1-4753-99ee-4d0924ca7116
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2023120894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.2023120894
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.3774681750
Short name T2566
Test name
Test status
Simulation time 153393598 ps
CPU time 0.83 seconds
Started Jul 20 06:20:57 PM PDT 24
Finished Jul 20 06:20:59 PM PDT 24
Peak memory 206656 kb
Host smart-6d2151f7-6410-4cb5-91f5-effae5e05ea7
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3774681750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.3774681750
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.1519941918
Short name T320
Test name
Test status
Simulation time 198973528 ps
CPU time 0.83 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:21:00 PM PDT 24
Peak memory 206660 kb
Host smart-c4e3bd98-8107-4c9a-ab62-6e22ae3493c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15199
41918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.1519941918
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1927205485
Short name T119
Test name
Test status
Simulation time 218513313 ps
CPU time 0.89 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:02 PM PDT 24
Peak memory 206748 kb
Host smart-a7b9bb3a-af8e-4c07-b471-cff3d0894e75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19272
05485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1927205485
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.2769351253
Short name T1766
Test name
Test status
Simulation time 188011117 ps
CPU time 0.86 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:01 PM PDT 24
Peak memory 206656 kb
Host smart-f37d9cc0-e2c4-434a-adca-9fb6dbb02b2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27693
51253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.2769351253
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.702988846
Short name T2539
Test name
Test status
Simulation time 222895160 ps
CPU time 0.85 seconds
Started Jul 20 06:21:02 PM PDT 24
Finished Jul 20 06:21:04 PM PDT 24
Peak memory 206648 kb
Host smart-40506182-04d6-434b-9392-5cab0c0f80ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70298
8846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.702988846
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.2752181007
Short name T2109
Test name
Test status
Simulation time 201152804 ps
CPU time 0.86 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:00 PM PDT 24
Peak memory 206636 kb
Host smart-1d81edf9-f51e-4278-99b4-bf0cfd5afa85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27521
81007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.2752181007
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.893847566
Short name T1368
Test name
Test status
Simulation time 155824690 ps
CPU time 0.81 seconds
Started Jul 20 06:21:01 PM PDT 24
Finished Jul 20 06:21:03 PM PDT 24
Peak memory 206640 kb
Host smart-a3f3bf13-8a12-4466-9403-82bf28390a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89384
7566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.893847566
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.2575780666
Short name T625
Test name
Test status
Simulation time 208250427 ps
CPU time 0.92 seconds
Started Jul 20 06:21:03 PM PDT 24
Finished Jul 20 06:21:05 PM PDT 24
Peak memory 206648 kb
Host smart-619427bf-b4d8-4b44-b1cd-b50b68120b55
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2575780666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.2575780666
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3721414180
Short name T1042
Test name
Test status
Simulation time 148116015 ps
CPU time 0.84 seconds
Started Jul 20 06:20:56 PM PDT 24
Finished Jul 20 06:20:58 PM PDT 24
Peak memory 206648 kb
Host smart-6760c7b0-db48-43d7-8404-90c1023a4985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37214
14180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3721414180
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.3126757011
Short name T780
Test name
Test status
Simulation time 41820065 ps
CPU time 0.65 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:00 PM PDT 24
Peak memory 206656 kb
Host smart-71258216-3db6-4871-b0e7-98363e09c8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31267
57011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.3126757011
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3645844214
Short name T275
Test name
Test status
Simulation time 8683471036 ps
CPU time 18.77 seconds
Started Jul 20 06:21:02 PM PDT 24
Finished Jul 20 06:21:21 PM PDT 24
Peak memory 206936 kb
Host smart-b38d4228-78e0-432d-b0c1-b10cee14d4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36458
44214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3645844214
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.202786114
Short name T1637
Test name
Test status
Simulation time 183920569 ps
CPU time 0.84 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:01 PM PDT 24
Peak memory 206656 kb
Host smart-f4b99ac2-47b8-499e-9b78-37f6e48806b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20278
6114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.202786114
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.4267292333
Short name T606
Test name
Test status
Simulation time 291870098 ps
CPU time 0.98 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:21:00 PM PDT 24
Peak memory 206664 kb
Host smart-526d04b8-3468-4add-af4e-6b39e7b3fd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
92333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.4267292333
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.687952586
Short name T1730
Test name
Test status
Simulation time 13936475038 ps
CPU time 300.56 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:26:02 PM PDT 24
Peak memory 206912 kb
Host smart-d96134af-7384-4723-a5bf-c74d4e71adae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=687952586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.687952586
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.551081639
Short name T2536
Test name
Test status
Simulation time 21615339699 ps
CPU time 523.01 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:29:44 PM PDT 24
Peak memory 206448 kb
Host smart-314ff642-6f80-467e-9da4-107a833c9a7c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=551081639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.551081639
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.3492394716
Short name T2520
Test name
Test status
Simulation time 169816315 ps
CPU time 0.78 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:20:59 PM PDT 24
Peak memory 206664 kb
Host smart-22ba90f2-80f1-4e95-b925-5563b7fc2cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34923
94716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.3492394716
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.3380330515
Short name T2
Test name
Test status
Simulation time 209194839 ps
CPU time 0.89 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:21:00 PM PDT 24
Peak memory 206648 kb
Host smart-5a147775-0bdd-4c50-8239-4863f30c19e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33803
30515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.3380330515
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.1313882562
Short name T92
Test name
Test status
Simulation time 155035048 ps
CPU time 0.81 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:01 PM PDT 24
Peak memory 206648 kb
Host smart-82bde9b9-22da-41d2-8763-054949eec210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13138
82562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.1313882562
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.1578833268
Short name T154
Test name
Test status
Simulation time 193936434 ps
CPU time 0.81 seconds
Started Jul 20 06:20:58 PM PDT 24
Finished Jul 20 06:20:59 PM PDT 24
Peak memory 206624 kb
Host smart-89d65754-572d-445d-b33a-ac16788bbbf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15788
33268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.1578833268
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3031902574
Short name T1030
Test name
Test status
Simulation time 154098507 ps
CPU time 0.85 seconds
Started Jul 20 06:21:03 PM PDT 24
Finished Jul 20 06:21:05 PM PDT 24
Peak memory 206636 kb
Host smart-b97aabd7-039f-44f4-9448-e7596047f996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30319
02574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3031902574
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.1132401401
Short name T2355
Test name
Test status
Simulation time 245378367 ps
CPU time 1.02 seconds
Started Jul 20 06:20:59 PM PDT 24
Finished Jul 20 06:21:01 PM PDT 24
Peak memory 206644 kb
Host smart-d32abd90-2fa2-475d-b123-f8114793dee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11324
01401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.1132401401
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2927666198
Short name T810
Test name
Test status
Simulation time 7001235985 ps
CPU time 64.27 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 206916 kb
Host smart-4a5e36a2-c452-410e-a0bf-141b2bb7f004
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2927666198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2927666198
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.1619437727
Short name T2348
Test name
Test status
Simulation time 152807147 ps
CPU time 0.79 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:21:02 PM PDT 24
Peak memory 206652 kb
Host smart-d7968e33-ef6d-4e7b-97e2-0de072e046df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16194
37727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.1619437727
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.529722693
Short name T1888
Test name
Test status
Simulation time 166917768 ps
CPU time 0.84 seconds
Started Jul 20 06:20:56 PM PDT 24
Finished Jul 20 06:20:58 PM PDT 24
Peak memory 206764 kb
Host smart-f8b4f7dc-192e-4dc8-851b-8e102c471ed0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52972
2693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.529722693
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.1348118211
Short name T665
Test name
Test status
Simulation time 1205947038 ps
CPU time 2.73 seconds
Started Jul 20 06:21:00 PM PDT 24
Finished Jul 20 06:21:04 PM PDT 24
Peak memory 206804 kb
Host smart-00e7105e-5e06-4685-9c61-87a046b5f486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13481
18211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.1348118211
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.2166721915
Short name T2263
Test name
Test status
Simulation time 7267988478 ps
CPU time 68.38 seconds
Started Jul 20 06:20:57 PM PDT 24
Finished Jul 20 06:22:06 PM PDT 24
Peak memory 206892 kb
Host smart-26d69b87-2d7e-4455-b357-53b0c0a3ecf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21667
21915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.2166721915
Directory /workspace/9.usbdev_streaming_out/latest
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