Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	166444	1		T1	2		T2	2		T3	2
all_values[1]	166444	1		T1	2		T2	2		T3	2
all_values[2]	166444	1		T1	2		T2	2		T3	2
all_values[3]	166444	1		T1	2		T2	2		T3	2
all_values[4]	166444	1		T1	2		T2	2		T3	2
all_values[5]	166444	1		T1	2		T2	2		T3	2
all_values[6]	166444	1		T1	2		T2	2		T3	2
all_values[7]	166444	1		T1	2		T2	2		T3	2
all_values[8]	166444	1		T1	2		T2	2		T3	2
all_values[9]	166444	1		T1	2		T2	2		T3	2
all_values[10]	166444	1		T1	2		T2	2		T3	2
all_values[11]	166444	1		T1	2		T2	2		T3	2
all_values[12]	166444	1		T1	2		T2	2		T3	2
all_values[13]	166444	1		T1	2		T2	2		T3	2
all_values[14]	166444	1		T1	2		T2	2		T3	2
all_values[15]	166444	1		T1	2		T2	2		T3	2
all_values[16]	166444	1		T1	2		T2	2		T3	2
all_values[17]	166444	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2989342	1		T1	36		T2	36		T3	36
auto[1]	6650	1		T27	14		T6	2		T7	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2991259	1		T1	36		T2	36		T3	36
auto[1]	4733	1		T197	118		T198	65		T199	78

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	165487	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	116	1		T197	1		T198	4		T199	3
all_values[0]	auto[1]	auto[0]	704	1		T23	3		T46	3		T47	4
all_values[0]	auto[1]	auto[1]	137	1		T197	3		T199	1		T273	3
all_values[1]	auto[0]	auto[0]	164655	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	143	1		T197	7		T198	4		T199	1
all_values[1]	auto[1]	auto[0]	1520	1		T27	14		T6	2		T7	2
all_values[1]	auto[1]	auto[1]	126	1		T197	1		T198	1		T199	3
all_values[2]	auto[0]	auto[0]	166063	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	124	1		T197	6		T198	3		T199	4
all_values[2]	auto[1]	auto[0]	115	1		T39	2		T40	2		T41	2
all_values[2]	auto[1]	auto[1]	142	1		T197	1		T198	1		T273	3
all_values[3]	auto[0]	auto[0]	164760	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	128	1		T197	1		T198	4		T199	2
all_values[3]	auto[1]	auto[0]	1413	1		T61	1395		T197	2		T272	1
all_values[3]	auto[1]	auto[1]	143	1		T197	5		T198	1		T199	3
all_values[4]	auto[0]	auto[0]	166150	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	132	1		T197	2		T198	4		T199	4
all_values[4]	auto[1]	auto[0]	22	1		T62	2		T273	2		T201	2
all_values[4]	auto[1]	auto[1]	140	1		T197	6		T198	1		T199	1
all_values[5]	auto[0]	auto[0]	166163	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	130	1		T197	2		T198	1		T273	1
all_values[5]	auto[1]	auto[0]	31	1		T197	1		T273	1		T201	1
all_values[5]	auto[1]	auto[1]	120	1		T197	5		T198	3		T199	4
all_values[6]	auto[0]	auto[0]	166156	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	142	1		T197	3		T199	5		T200	1
all_values[6]	auto[1]	auto[0]	29	1		T198	3		T273	3		T272	1
all_values[6]	auto[1]	auto[1]	117	1		T197	5		T200	3		T201	6
all_values[7]	auto[0]	auto[0]	166148	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	134	1		T197	5		T198	1		T273	4
all_values[7]	auto[1]	auto[0]	32	1		T48	2		T49	2		T50	2
all_values[7]	auto[1]	auto[1]	130	1		T197	3		T198	3		T199	3
all_values[8]	auto[0]	auto[0]	166142	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	126	1		T197	6		T198	3		T199	4
all_values[8]	auto[1]	auto[0]	31	1		T54	11		T198	1		T273	4
all_values[8]	auto[1]	auto[1]	145	1		T197	2		T199	1		T200	3
all_values[9]	auto[0]	auto[0]	166147	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	115	1		T199	4		T201	3		T274	2
all_values[9]	auto[1]	auto[0]	43	1		T45	5		T59	5		T60	5
all_values[9]	auto[1]	auto[1]	139	1		T273	3		T200	5		T201	4
all_values[10]	auto[0]	auto[0]	166155	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	138	1		T197	3		T200	1		T201	6
all_values[10]	auto[1]	auto[0]	29	1		T198	4		T199	2		T273	1
all_values[10]	auto[1]	auto[1]	122	1		T197	5		T199	3		T200	3
all_values[11]	auto[0]	auto[0]	166045	1		T1	2		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	158	1		T197	8		T198	3		T199	4
all_values[11]	auto[1]	auto[0]	118	1		T44	2		T66	2		T67	2
all_values[11]	auto[1]	auto[1]	123	1		T198	2		T199	1		T273	1
all_values[12]	auto[0]	auto[0]	166147	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	125	1		T197	6		T199	1		T200	3
all_values[12]	auto[1]	auto[0]	38	1		T69	3		T70	3		T71	3
all_values[12]	auto[1]	auto[1]	134	1		T198	5		T199	3		T273	3
all_values[13]	auto[0]	auto[0]	166158	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	123	1		T197	2		T198	1		T201	7
all_values[13]	auto[1]	auto[0]	27	1		T197	2		T199	1		T200	1
all_values[13]	auto[1]	auto[1]	136	1		T197	3		T198	4		T199	3
all_values[14]	auto[0]	auto[0]	166155	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	128	1		T197	4		T198	3		T199	1
all_values[14]	auto[1]	auto[0]	25	1		T197	1		T198	1		T274	1
all_values[14]	auto[1]	auto[1]	136	1		T197	1		T199	4		T200	1
all_values[15]	auto[0]	auto[0]	166149	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	139	1		T197	1		T198	3		T199	4
all_values[15]	auto[1]	auto[0]	25	1		T273	1		T274	3		T275	1
all_values[15]	auto[1]	auto[1]	131	1		T197	6		T198	1		T199	1
all_values[16]	auto[0]	auto[0]	166136	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	136	1		T197	3		T198	5		T199	4
all_values[16]	auto[1]	auto[0]	52	1		T43	8		T63	8		T64	8
all_values[16]	auto[1]	auto[1]	120	1		T197	5		T199	1		T200	1
all_values[17]	auto[0]	auto[0]	166152	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	137	1		T197	5		T198	4		T199	2
all_values[17]	auto[1]	auto[0]	37	1		T55	2		T197	1		T273	1
all_values[17]	auto[1]	auto[1]	118	1		T197	2		T199	3		T200	2