Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	166444	1		T1	2		T2	2		T3	2
all_pins[1]	166444	1		T1	2		T2	2		T3	2
all_pins[2]	166444	1		T1	2		T2	2		T3	2
all_pins[3]	166444	1		T1	2		T2	2		T3	2
all_pins[4]	166444	1		T1	2		T2	2		T3	2
all_pins[5]	166444	1		T1	2		T2	2		T3	2
all_pins[6]	166444	1		T1	2		T2	2		T3	2
all_pins[7]	166444	1		T1	2		T2	2		T3	2
all_pins[8]	166444	1		T1	2		T2	2		T3	2
all_pins[9]	166444	1		T1	2		T2	2		T3	2
all_pins[10]	166444	1		T1	2		T2	2		T3	2
all_pins[11]	166444	1		T1	2		T2	2		T3	2
all_pins[12]	166444	1		T1	2		T2	2		T3	2
all_pins[13]	166444	1		T1	2		T2	2		T3	2
all_pins[14]	166444	1		T1	2		T2	2		T3	2
all_pins[15]	166444	1		T1	2		T2	2		T3	2
all_pins[16]	166444	1		T1	2		T2	2		T3	2
all_pins[17]	166444	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	2993757	1		T1	36		T2	36		T3	36
values[0x1]	2235	1		T27	12		T6	1		T7	1
transitions[0x0=>0x1]	1964	1		T27	12		T6	1		T7	1
transitions[0x1=>0x0]	1979	1		T27	12		T6	1		T7	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	166335	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	109	1		T47	1		T276	1		T277	1
all_pins[0]	transitions[0x0=>0x1]	94	1		T47	1		T276	1		T277	1
all_pins[0]	transitions[0x1=>0x0]	988	1		T27	12		T6	1		T7	1
all_pins[1]	values[0x0]	165441	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1003	1		T27	12		T6	1		T7	1
all_pins[1]	transitions[0x0=>0x1]	991	1		T27	12		T6	1		T7	1
all_pins[1]	transitions[0x1=>0x0]	111	1		T39	1		T40	1		T41	1
all_pins[2]	values[0x0]	166321	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	123	1		T39	1		T40	1		T41	1
all_pins[2]	transitions[0x0=>0x1]	104	1		T39	1		T40	1		T41	1
all_pins[2]	transitions[0x1=>0x0]	46	1		T61	1		T197	1		T273	1
all_pins[3]	values[0x0]	166379	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	65	1		T61	1		T197	2		T273	1
all_pins[3]	transitions[0x0=>0x1]	45	1		T61	1		T197	1		T273	1
all_pins[3]	transitions[0x1=>0x0]	44	1		T62	1		T197	2		T198	1
all_pins[4]	values[0x0]	166380	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	64	1		T62	1		T197	3		T198	1
all_pins[4]	transitions[0x0=>0x1]	50	1		T62	1		T197	2		T198	1
all_pins[4]	transitions[0x1=>0x0]	44	1		T198	2		T199	2		T200	2
all_pins[5]	values[0x0]	166386	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	58	1		T197	1		T198	2		T199	2
all_pins[5]	transitions[0x0=>0x1]	47	1		T197	1		T198	2		T199	2
all_pins[5]	transitions[0x1=>0x0]	47	1		T197	3		T275	2		T278	1
all_pins[6]	values[0x0]	166386	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	58	1		T197	3		T201	2		T275	2
all_pins[6]	transitions[0x0=>0x1]	45	1		T197	3		T201	1		T275	2
all_pins[6]	transitions[0x1=>0x0]	45	1		T48	1		T49	1		T50	1
all_pins[7]	values[0x0]	166386	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	58	1		T48	1		T49	1		T50	1
all_pins[7]	transitions[0x0=>0x1]	44	1		T48	1		T49	1		T50	1
all_pins[7]	transitions[0x1=>0x0]	43	1		T54	1		T197	1		T199	1
all_pins[8]	values[0x0]	166387	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	57	1		T54	1		T197	1		T199	1
all_pins[8]	transitions[0x0=>0x1]	39	1		T54	1		T197	1		T199	1
all_pins[8]	transitions[0x1=>0x0]	58	1		T45	2		T59	2		T60	2
all_pins[9]	values[0x0]	166368	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	76	1		T45	2		T59	2		T60	2
all_pins[9]	transitions[0x0=>0x1]	61	1		T45	2		T59	2		T60	2
all_pins[9]	transitions[0x1=>0x0]	46	1		T197	2		T199	2		T274	5
all_pins[10]	values[0x0]	166383	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	61	1		T197	2		T199	2		T201	1
all_pins[10]	transitions[0x0=>0x1]	49	1		T197	2		T199	2		T201	1
all_pins[10]	transitions[0x1=>0x0]	99	1		T44	1		T66	1		T67	1
all_pins[11]	values[0x0]	166333	1		T1	2		T2	2		T3	2
all_pins[11]	values[0x1]	111	1		T44	1		T66	1		T67	1
all_pins[11]	transitions[0x0=>0x1]	102	1		T44	1		T66	1		T67	1
all_pins[11]	transitions[0x1=>0x0]	52	1		T69	1		T70	1		T71	1
all_pins[12]	values[0x0]	166383	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	61	1		T69	1		T70	1		T71	1
all_pins[12]	transitions[0x0=>0x1]	42	1		T69	1		T70	1		T71	1
all_pins[12]	transitions[0x1=>0x0]	52	1		T198	3		T273	1		T201	1
all_pins[13]	values[0x0]	166373	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	71	1		T198	3		T199	2		T273	3
all_pins[13]	transitions[0x0=>0x1]	56	1		T198	3		T199	2		T273	3
all_pins[13]	transitions[0x1=>0x0]	56	1		T197	1		T199	1		T201	2
all_pins[14]	values[0x0]	166373	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	71	1		T197	1		T199	1		T201	2
all_pins[14]	transitions[0x0=>0x1]	54	1		T201	2		T274	1		T275	2
all_pins[14]	transitions[0x1=>0x0]	45	1		T197	2		T198	1		T273	2
all_pins[15]	values[0x0]	166382	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	62	1		T197	3		T198	1		T199	1
all_pins[15]	transitions[0x0=>0x1]	50	1		T197	3		T198	1		T199	1
all_pins[15]	transitions[0x1=>0x0]	59	1		T43	4		T63	4		T64	4
all_pins[16]	values[0x0]	166373	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	71	1		T43	4		T63	4		T64	4
all_pins[16]	transitions[0x0=>0x1]	60	1		T43	4		T63	4		T64	4
all_pins[16]	transitions[0x1=>0x0]	45	1		T55	1		T199	1		T200	1
all_pins[17]	values[0x0]	166388	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	56	1		T55	1		T199	1		T200	2
all_pins[17]	transitions[0x0=>0x1]	31	1		T55	1		T274	1		T279	1
all_pins[17]	transitions[0x1=>0x0]	99	1		T47	1		T276	1		T277	1