Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.36 97.82 93.83 97.44 73.44 96.21 98.17 96.58


Total test records in report: 2862
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T2764 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1678317007 Jul 21 06:52:03 PM PDT 24 Jul 21 06:52:08 PM PDT 24 312159362 ps
T2765 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3388599098 Jul 21 06:52:08 PM PDT 24 Jul 21 06:52:10 PM PDT 24 169397490 ps
T233 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3071838392 Jul 21 06:52:09 PM PDT 24 Jul 21 06:52:15 PM PDT 24 1524210192 ps
T2766 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1630541996 Jul 21 06:52:02 PM PDT 24 Jul 21 06:52:06 PM PDT 24 219905836 ps
T284 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1327239540 Jul 21 06:52:11 PM PDT 24 Jul 21 06:52:12 PM PDT 24 34409246 ps
T2767 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.394052569 Jul 21 06:52:06 PM PDT 24 Jul 21 06:52:10 PM PDT 24 96670053 ps
T290 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.714007829 Jul 21 06:52:11 PM PDT 24 Jul 21 06:52:15 PM PDT 24 507232639 ps
T2768 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2641390367 Jul 21 06:52:24 PM PDT 24 Jul 21 06:52:26 PM PDT 24 256905437 ps
T2769 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.837189460 Jul 21 06:51:57 PM PDT 24 Jul 21 06:52:00 PM PDT 24 98154048 ps
T2770 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3567253576 Jul 21 06:52:07 PM PDT 24 Jul 21 06:52:09 PM PDT 24 71232945 ps
T2771 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.29239507 Jul 21 06:52:08 PM PDT 24 Jul 21 06:52:09 PM PDT 24 35676569 ps
T255 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1175186643 Jul 21 06:51:52 PM PDT 24 Jul 21 06:51:54 PM PDT 24 108954788 ps
T287 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.273961123 Jul 21 06:52:34 PM PDT 24 Jul 21 06:52:36 PM PDT 24 51484868 ps
T2772 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1087367155 Jul 21 06:52:26 PM PDT 24 Jul 21 06:52:28 PM PDT 24 61067546 ps
T2773 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3905544756 Jul 21 06:52:28 PM PDT 24 Jul 21 06:52:30 PM PDT 24 58778979 ps
T281 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2637135663 Jul 21 06:52:27 PM PDT 24 Jul 21 06:52:28 PM PDT 24 37141761 ps
T256 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3708312945 Jul 21 06:51:56 PM PDT 24 Jul 21 06:51:58 PM PDT 24 113437893 ps
T2774 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3189627163 Jul 21 06:52:00 PM PDT 24 Jul 21 06:52:05 PM PDT 24 103614592 ps
T2775 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.183516371 Jul 21 06:52:03 PM PDT 24 Jul 21 06:52:07 PM PDT 24 102961182 ps
T257 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1003568800 Jul 21 06:51:58 PM PDT 24 Jul 21 06:52:01 PM PDT 24 105610914 ps
T2776 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2593732290 Jul 21 06:52:27 PM PDT 24 Jul 21 06:52:28 PM PDT 24 38096367 ps
T282 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.54328225 Jul 21 06:52:25 PM PDT 24 Jul 21 06:52:26 PM PDT 24 46928276 ps
T258 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3729738672 Jul 21 06:52:10 PM PDT 24 Jul 21 06:52:14 PM PDT 24 342215538 ps
T2777 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.326903664 Jul 21 06:51:59 PM PDT 24 Jul 21 06:52:02 PM PDT 24 110322791 ps
T2778 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3164475089 Jul 21 06:52:10 PM PDT 24 Jul 21 06:52:12 PM PDT 24 111253617 ps
T2779 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1913657835 Jul 21 06:52:01 PM PDT 24 Jul 21 06:52:04 PM PDT 24 174034879 ps
T2780 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.640877890 Jul 21 06:52:20 PM PDT 24 Jul 21 06:52:21 PM PDT 24 71319694 ps
T2781 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3513711356 Jul 21 06:52:17 PM PDT 24 Jul 21 06:52:19 PM PDT 24 98587585 ps
T2782 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1943363774 Jul 21 06:52:08 PM PDT 24 Jul 21 06:52:12 PM PDT 24 252484048 ps
T2783 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1154114980 Jul 21 06:52:22 PM PDT 24 Jul 21 06:52:24 PM PDT 24 72261627 ps
T259 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4226165920 Jul 21 06:52:15 PM PDT 24 Jul 21 06:52:17 PM PDT 24 86493614 ps
T2784 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3970973298 Jul 21 06:52:15 PM PDT 24 Jul 21 06:52:17 PM PDT 24 89828129 ps
T2785 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4030843069 Jul 21 06:52:22 PM PDT 24 Jul 21 06:52:23 PM PDT 24 41152014 ps
T2786 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2233807179 Jul 21 06:52:27 PM PDT 24 Jul 21 06:52:28 PM PDT 24 49331768 ps
T2787 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.81313434 Jul 21 06:51:57 PM PDT 24 Jul 21 06:51:59 PM PDT 24 73923244 ps
T2788 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.99497791 Jul 21 06:52:04 PM PDT 24 Jul 21 06:52:06 PM PDT 24 31367289 ps
T2789 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2193718108 Jul 21 06:52:21 PM PDT 24 Jul 21 06:52:22 PM PDT 24 40498675 ps
T2790 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1351202606 Jul 21 06:52:29 PM PDT 24 Jul 21 06:52:30 PM PDT 24 32682357 ps
T2791 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1723293132 Jul 21 06:52:21 PM PDT 24 Jul 21 06:52:23 PM PDT 24 43618857 ps
T2792 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3584537165 Jul 21 06:52:23 PM PDT 24 Jul 21 06:52:24 PM PDT 24 40333049 ps
T2793 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2613639918 Jul 21 06:52:27 PM PDT 24 Jul 21 06:52:28 PM PDT 24 42317567 ps
T2794 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.209283806 Jul 21 06:52:00 PM PDT 24 Jul 21 06:52:02 PM PDT 24 108352642 ps
T2795 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1702943003 Jul 21 06:52:04 PM PDT 24 Jul 21 06:52:10 PM PDT 24 690892451 ps
T2796 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1621560758 Jul 21 06:52:00 PM PDT 24 Jul 21 06:52:05 PM PDT 24 524238316 ps
T2797 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1019349120 Jul 21 06:52:20 PM PDT 24 Jul 21 06:52:21 PM PDT 24 41620790 ps
T2798 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4070570926 Jul 21 06:52:06 PM PDT 24 Jul 21 06:52:08 PM PDT 24 103494728 ps
T2799 /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1563360472 Jul 21 06:52:17 PM PDT 24 Jul 21 06:52:19 PM PDT 24 159280008 ps
T2800 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4247125315 Jul 21 06:52:12 PM PDT 24 Jul 21 06:52:14 PM PDT 24 253785173 ps
T2801 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1121243074 Jul 21 06:51:55 PM PDT 24 Jul 21 06:51:58 PM PDT 24 275546073 ps
T2802 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3116190310 Jul 21 06:52:16 PM PDT 24 Jul 21 06:52:19 PM PDT 24 183004204 ps
T2803 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1488440227 Jul 21 06:52:14 PM PDT 24 Jul 21 06:52:17 PM PDT 24 106132188 ps
T2804 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.507286361 Jul 21 06:52:16 PM PDT 24 Jul 21 06:52:19 PM PDT 24 209342018 ps
T2805 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1546676352 Jul 21 06:52:15 PM PDT 24 Jul 21 06:52:17 PM PDT 24 33318467 ps
T291 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.782678540 Jul 21 06:52:17 PM PDT 24 Jul 21 06:52:22 PM PDT 24 858118847 ps
T2806 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.317504733 Jul 21 06:52:02 PM PDT 24 Jul 21 06:52:03 PM PDT 24 58650617 ps
T2807 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1972868815 Jul 21 06:52:02 PM PDT 24 Jul 21 06:52:07 PM PDT 24 200023372 ps
T2808 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2720878041 Jul 21 06:52:03 PM PDT 24 Jul 21 06:52:06 PM PDT 24 216603371 ps
T2809 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4136625415 Jul 21 06:51:59 PM PDT 24 Jul 21 06:52:05 PM PDT 24 810502024 ps
T2810 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.649788173 Jul 21 06:52:01 PM PDT 24 Jul 21 06:52:08 PM PDT 24 833757028 ps
T2811 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2067543724 Jul 21 06:52:21 PM PDT 24 Jul 21 06:52:22 PM PDT 24 99595737 ps
T2812 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2958488364 Jul 21 06:52:09 PM PDT 24 Jul 21 06:52:10 PM PDT 24 133218315 ps
T2813 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3698129286 Jul 21 06:51:54 PM PDT 24 Jul 21 06:51:56 PM PDT 24 137787866 ps
T2814 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2374403852 Jul 21 06:52:11 PM PDT 24 Jul 21 06:52:13 PM PDT 24 148932824 ps
T2815 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.950253966 Jul 21 06:51:57 PM PDT 24 Jul 21 06:52:00 PM PDT 24 195585345 ps
T2816 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3850667726 Jul 21 06:52:18 PM PDT 24 Jul 21 06:52:21 PM PDT 24 78669551 ps
T2817 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.113695413 Jul 21 06:52:26 PM PDT 24 Jul 21 06:52:27 PM PDT 24 36373818 ps
T2818 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2257799696 Jul 21 06:52:12 PM PDT 24 Jul 21 06:52:14 PM PDT 24 189403070 ps
T2819 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3958980760 Jul 21 06:52:03 PM PDT 24 Jul 21 06:52:07 PM PDT 24 244698429 ps
T2820 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4203918281 Jul 21 06:52:18 PM PDT 24 Jul 21 06:52:19 PM PDT 24 61213166 ps
T2821 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.869467933 Jul 21 06:52:04 PM PDT 24 Jul 21 06:52:06 PM PDT 24 45428549 ps
T2822 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1550109415 Jul 21 06:52:03 PM PDT 24 Jul 21 06:52:07 PM PDT 24 317954399 ps
T2823 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.281691050 Jul 21 06:52:27 PM PDT 24 Jul 21 06:52:28 PM PDT 24 49726418 ps
T2824 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3094336515 Jul 21 06:52:04 PM PDT 24 Jul 21 06:52:06 PM PDT 24 59885006 ps
T2825 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1471670663 Jul 21 06:52:02 PM PDT 24 Jul 21 06:52:05 PM PDT 24 323718285 ps
T2826 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2295552794 Jul 21 06:52:11 PM PDT 24 Jul 21 06:52:13 PM PDT 24 210537134 ps
T2827 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1345277141 Jul 21 06:52:16 PM PDT 24 Jul 21 06:52:17 PM PDT 24 42329307 ps
T2828 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.13368490 Jul 21 06:51:55 PM PDT 24 Jul 21 06:51:58 PM PDT 24 118171656 ps
T2829 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1497348269 Jul 21 06:51:58 PM PDT 24 Jul 21 06:52:00 PM PDT 24 78001580 ps
T2830 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2771196007 Jul 21 06:52:01 PM PDT 24 Jul 21 06:52:03 PM PDT 24 66681147 ps
T2831 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2309475389 Jul 21 06:52:07 PM PDT 24 Jul 21 06:52:08 PM PDT 24 101621004 ps
T2832 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3517005811 Jul 21 06:52:00 PM PDT 24 Jul 21 06:52:03 PM PDT 24 86212230 ps
T2833 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1357686448 Jul 21 06:52:05 PM PDT 24 Jul 21 06:52:07 PM PDT 24 32020692 ps
T293 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.122741785 Jul 21 06:52:18 PM PDT 24 Jul 21 06:52:24 PM PDT 24 804663947 ps
T2834 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4026369702 Jul 21 06:52:01 PM PDT 24 Jul 21 06:52:12 PM PDT 24 1059331466 ps
T2835 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2550766205 Jul 21 06:52:13 PM PDT 24 Jul 21 06:52:15 PM PDT 24 128338860 ps
T2836 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.592676322 Jul 21 06:52:15 PM PDT 24 Jul 21 06:52:19 PM PDT 24 228834351 ps
T2837 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2804191987 Jul 21 06:51:58 PM PDT 24 Jul 21 06:52:03 PM PDT 24 178906328 ps
T2838 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1784853774 Jul 21 06:52:00 PM PDT 24 Jul 21 06:52:03 PM PDT 24 80900415 ps
T2839 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2416693304 Jul 21 06:52:19 PM PDT 24 Jul 21 06:52:23 PM PDT 24 374957852 ps
T2840 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2223344960 Jul 21 06:52:13 PM PDT 24 Jul 21 06:52:15 PM PDT 24 34354962 ps
T2841 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.251250223 Jul 21 06:51:57 PM PDT 24 Jul 21 06:51:58 PM PDT 24 81626934 ps
T2842 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2610496608 Jul 21 06:52:28 PM PDT 24 Jul 21 06:52:30 PM PDT 24 57545613 ps
T2843 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1430999775 Jul 21 06:52:13 PM PDT 24 Jul 21 06:52:16 PM PDT 24 180743304 ps
T2844 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2320590279 Jul 21 06:52:07 PM PDT 24 Jul 21 06:52:10 PM PDT 24 102954947 ps
T2845 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3050866541 Jul 21 06:52:14 PM PDT 24 Jul 21 06:52:18 PM PDT 24 467969054 ps
T2846 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2727754670 Jul 21 06:52:12 PM PDT 24 Jul 21 06:52:14 PM PDT 24 71305088 ps
T2847 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3279210268 Jul 21 06:52:12 PM PDT 24 Jul 21 06:52:15 PM PDT 24 111715162 ps
T2848 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4144391373 Jul 21 06:52:10 PM PDT 24 Jul 21 06:52:12 PM PDT 24 53956739 ps
T2849 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3188593320 Jul 21 06:52:03 PM PDT 24 Jul 21 06:52:05 PM PDT 24 58233405 ps
T2850 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3255421871 Jul 21 06:51:57 PM PDT 24 Jul 21 06:52:00 PM PDT 24 106372026 ps
T2851 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3216769025 Jul 21 06:52:27 PM PDT 24 Jul 21 06:52:29 PM PDT 24 76182262 ps
T2852 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1628359097 Jul 21 06:52:13 PM PDT 24 Jul 21 06:52:15 PM PDT 24 51113406 ps
T2853 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3499289193 Jul 21 06:52:14 PM PDT 24 Jul 21 06:52:15 PM PDT 24 50911432 ps
T2854 /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3945587043 Jul 21 06:51:57 PM PDT 24 Jul 21 06:52:03 PM PDT 24 705595883 ps
T2855 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4240128184 Jul 21 06:51:51 PM PDT 24 Jul 21 06:51:58 PM PDT 24 748818658 ps
T2856 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.303137096 Jul 21 06:52:02 PM PDT 24 Jul 21 06:52:05 PM PDT 24 60821340 ps
T2857 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3837723076 Jul 21 06:51:57 PM PDT 24 Jul 21 06:52:03 PM PDT 24 736327957 ps
T2858 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3656969692 Jul 21 06:52:28 PM PDT 24 Jul 21 06:52:29 PM PDT 24 75773594 ps
T2859 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2834754891 Jul 21 06:51:57 PM PDT 24 Jul 21 06:52:00 PM PDT 24 185623012 ps
T2860 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1445127806 Jul 21 06:52:01 PM PDT 24 Jul 21 06:52:06 PM PDT 24 169562062 ps
T2861 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.866095060 Jul 21 06:52:12 PM PDT 24 Jul 21 06:52:14 PM PDT 24 42845595 ps
T2862 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2796859591 Jul 21 06:51:59 PM PDT 24 Jul 21 06:52:01 PM PDT 24 44270574 ps

Test location /workspace/coverage/default/24.usbdev_endpoint_access.4203132941
Short name T17
Test name
Test status
Simulation time 778986432 ps
CPU time 1.98 seconds
Started Jul 21 06:57:06 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206740 kb
Host smart-39f42be4-3a5e-4b69-8bcb-a0864a584b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42031
32941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.4203132941
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1224908113
Short name T201
Test name
Test status
Simulation time 60627976 ps
CPU time 0.72 seconds
Started Jul 21 06:51:55 PM PDT 24
Finished Jul 21 06:51:56 PM PDT 24
Peak memory 206304 kb
Host smart-1e5494f8-b5e7-4f7c-8e65-d76979bbc325
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1224908113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1224908113
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.3130048682
Short name T8
Test name
Test status
Simulation time 13536106760 ps
CPU time 12.49 seconds
Started Jul 21 06:53:25 PM PDT 24
Finished Jul 21 06:53:39 PM PDT 24
Peak memory 206856 kb
Host smart-155ce891-7653-4286-95b5-cae4218315a0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3130048682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.3130048682
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_device_address.535671350
Short name T3
Test name
Test status
Simulation time 16380875393 ps
CPU time 30.49 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:54:23 PM PDT 24
Peak memory 206848 kb
Host smart-686f67cc-8ec0-4139-85d2-0906230088a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53567
1350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.535671350
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.4096885137
Short name T237
Test name
Test status
Simulation time 832231701 ps
CPU time 5.19 seconds
Started Jul 21 06:52:08 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 206504 kb
Host smart-adaef4e2-3eb5-45a7-86a8-5368048f7059
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4096885137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.4096885137
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.3278922956
Short name T56
Test name
Test status
Simulation time 13378782151 ps
CPU time 277.03 seconds
Started Jul 21 06:53:38 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 207044 kb
Host smart-dd275797-733e-4801-81a3-a2d98916d098
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3278922956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.3278922956
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.705324842
Short name T199
Test name
Test status
Simulation time 40788480 ps
CPU time 0.68 seconds
Started Jul 21 06:52:22 PM PDT 24
Finished Jul 21 06:52:23 PM PDT 24
Peak memory 206344 kb
Host smart-b4681ab6-e7c4-4c02-a113-f2e41acabb94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=705324842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.705324842
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.12614669
Short name T87
Test name
Test status
Simulation time 233394779 ps
CPU time 0.92 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206684 kb
Host smart-b4154ea7-4a3a-4b48-ae54-cd7051bf9eab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12614
669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.12614669
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_iso_retraction.2846867507
Short name T79
Test name
Test status
Simulation time 4076428208 ps
CPU time 37.18 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:54:06 PM PDT 24
Peak memory 206912 kb
Host smart-ae67746a-07e0-4e70-a099-a0190501c69c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28468
67507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_iso_retraction.2846867507
Directory /workspace/4.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.2191735830
Short name T39
Test name
Test status
Simulation time 144630029 ps
CPU time 0.75 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206664 kb
Host smart-cc9f182a-ce41-4d8a-a1ab-a3759f2f2054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21917
35830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.2191735830
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.3239140087
Short name T186
Test name
Test status
Simulation time 447937310 ps
CPU time 1.41 seconds
Started Jul 21 06:52:51 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 224512 kb
Host smart-a78b3e81-1972-4a55-80e1-6cf408e3633d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3239140087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.3239140087
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3210278044
Short name T215
Test name
Test status
Simulation time 131559648 ps
CPU time 2.91 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:04 PM PDT 24
Peak memory 222804 kb
Host smart-503e004f-328d-4116-bac8-6945bb4267e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3210278044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3210278044
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.3073979440
Short name T97
Test name
Test status
Simulation time 260251754 ps
CPU time 1.09 seconds
Started Jul 21 06:56:31 PM PDT 24
Finished Jul 21 06:56:33 PM PDT 24
Peak memory 206708 kb
Host smart-62ab7e5b-91a8-4d79-9d7e-66619cf6eddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30739
79440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.3073979440
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.2565210149
Short name T131
Test name
Test status
Simulation time 203085371 ps
CPU time 0.88 seconds
Started Jul 21 06:52:47 PM PDT 24
Finished Jul 21 06:52:49 PM PDT 24
Peak memory 206704 kb
Host smart-fa34a6c8-71aa-40ec-8398-129e4ccc889c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25652
10149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.2565210149
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.1894665323
Short name T37
Test name
Test status
Simulation time 8857050104 ps
CPU time 220.47 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206956 kb
Host smart-6e77e609-a74a-494d-b8bb-08fd2c2c9203
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1894665323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.1894665323
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.3779210343
Short name T25
Test name
Test status
Simulation time 36825471 ps
CPU time 0.67 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:02 PM PDT 24
Peak memory 206672 kb
Host smart-880f2d48-7143-46d8-8a70-7ae136bbb398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37792
10343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.3779210343
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.2921511996
Short name T273
Test name
Test status
Simulation time 88904742 ps
CPU time 0.71 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:52:34 PM PDT 24
Peak memory 206312 kb
Host smart-f94db132-3370-46c5-af4e-f47dff12c78f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2921511996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.2921511996
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.4258452797
Short name T72
Test name
Test status
Simulation time 303993224 ps
CPU time 1.02 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:41 PM PDT 24
Peak memory 206664 kb
Host smart-1d339158-7979-4c3c-ab40-80ccfeac0e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42584
52797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.4258452797
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.1030835702
Short name T42
Test name
Test status
Simulation time 20191036593 ps
CPU time 21.23 seconds
Started Jul 21 06:52:36 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206752 kb
Host smart-d9ae39a1-f13f-4b74-b751-5c40c35109f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10308
35702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.1030835702
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2798563940
Short name T248
Test name
Test status
Simulation time 82541829 ps
CPU time 1.06 seconds
Started Jul 21 06:52:24 PM PDT 24
Finished Jul 21 06:52:25 PM PDT 24
Peak memory 206460 kb
Host smart-a9c2a45e-ce68-43e1-808e-ab4f3625394c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2798563940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2798563940
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.3905544756
Short name T2773
Test name
Test status
Simulation time 58778979 ps
CPU time 0.75 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:30 PM PDT 24
Peak memory 206316 kb
Host smart-d67a310e-062d-494b-898c-32592bf043ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3905544756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.3905544756
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.112081132
Short name T47
Test name
Test status
Simulation time 180781621 ps
CPU time 0.84 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206724 kb
Host smart-f025e888-bf76-43bc-a288-d9c698fa6e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11208
1132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.112081132
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.3157971837
Short name T439
Test name
Test status
Simulation time 178131583 ps
CPU time 0.77 seconds
Started Jul 21 06:55:48 PM PDT 24
Finished Jul 21 06:55:49 PM PDT 24
Peak memory 206688 kb
Host smart-9ddb4172-8b46-401c-a030-c0a6f6a803f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31579
71837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.3157971837
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.955461162
Short name T38
Test name
Test status
Simulation time 581916850 ps
CPU time 1.39 seconds
Started Jul 21 06:53:26 PM PDT 24
Finished Jul 21 06:53:28 PM PDT 24
Peak memory 206676 kb
Host smart-cbd30236-1a60-4d38-834b-2d704b9972e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95546
1162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.955461162
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2193718108
Short name T2789
Test name
Test status
Simulation time 40498675 ps
CPU time 0.68 seconds
Started Jul 21 06:52:21 PM PDT 24
Finished Jul 21 06:52:22 PM PDT 24
Peak memory 206300 kb
Host smart-3984bb65-4c1f-4862-aa8a-17d103ccae37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2193718108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2193718108
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.3035788751
Short name T64
Test name
Test status
Simulation time 464957646 ps
CPU time 1.41 seconds
Started Jul 21 06:52:31 PM PDT 24
Finished Jul 21 06:52:33 PM PDT 24
Peak memory 206720 kb
Host smart-30bab13d-aa89-434b-a241-221db2b50346
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30357
88751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.3035788751
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3834929679
Short name T288
Test name
Test status
Simulation time 386315799 ps
CPU time 2.81 seconds
Started Jul 21 06:51:54 PM PDT 24
Finished Jul 21 06:51:58 PM PDT 24
Peak memory 206468 kb
Host smart-61e3aafc-e701-4857-8928-728dc506bec9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3834929679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3834929679
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.1327239540
Short name T284
Test name
Test status
Simulation time 34409246 ps
CPU time 0.66 seconds
Started Jul 21 06:52:11 PM PDT 24
Finished Jul 21 06:52:12 PM PDT 24
Peak memory 206312 kb
Host smart-710e088e-fed2-4ad3-bed7-bdfcdfafd28e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1327239540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.1327239540
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.2896253362
Short name T538
Test name
Test status
Simulation time 48014317 ps
CPU time 0.75 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:52:51 PM PDT 24
Peak memory 206684 kb
Host smart-55846cbe-c459-4cff-96c6-d044b2996e20
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2896253362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.2896253362
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.2977206895
Short name T404
Test name
Test status
Simulation time 4207469343 ps
CPU time 5.83 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:48 PM PDT 24
Peak memory 206748 kb
Host smart-e3138e4c-ca40-42a7-a707-88de7536c485
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2977206895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.2977206895
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.183516371
Short name T2775
Test name
Test status
Simulation time 102961182 ps
CPU time 1.58 seconds
Started Jul 21 06:52:03 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 206512 kb
Host smart-a7e0f460-4cad-46e8-aaf0-3a06cb880e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=183516371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.183516371
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1699644486
Short name T157
Test name
Test status
Simulation time 8456656592 ps
CPU time 221.69 seconds
Started Jul 21 06:53:21 PM PDT 24
Finished Jul 21 06:57:04 PM PDT 24
Peak memory 207024 kb
Host smart-55df2b18-601e-4554-bfe9-88e5553f30ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1699644486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1699644486
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.668030626
Short name T51
Test name
Test status
Simulation time 451235525 ps
CPU time 1.48 seconds
Started Jul 21 06:52:51 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206680 kb
Host smart-22539bd3-82d7-4991-a7ed-e7f71fbffb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66803
0626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.668030626
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.3354440880
Short name T76
Test name
Test status
Simulation time 145495026 ps
CPU time 0.77 seconds
Started Jul 21 06:52:34 PM PDT 24
Finished Jul 21 06:52:35 PM PDT 24
Peak memory 206648 kb
Host smart-374d0848-323d-40b4-aa20-a91f37c21a50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33544
40880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.3354440880
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.574167882
Short name T138
Test name
Test status
Simulation time 4460984119 ps
CPU time 40.31 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:46 PM PDT 24
Peak memory 206960 kb
Host smart-0caceb6b-820c-4245-b157-9ad3c0a462f9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=574167882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.574167882
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.3957969204
Short name T270
Test name
Test status
Simulation time 641821350 ps
CPU time 3.14 seconds
Started Jul 21 06:51:56 PM PDT 24
Finished Jul 21 06:52:00 PM PDT 24
Peak memory 206584 kb
Host smart-f4290b36-239e-4187-825f-8db48d357486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3957969204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.3957969204
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.122741785
Short name T293
Test name
Test status
Simulation time 804663947 ps
CPU time 4.66 seconds
Started Jul 21 06:52:18 PM PDT 24
Finished Jul 21 06:52:24 PM PDT 24
Peak memory 206592 kb
Host smart-bd67832b-85cd-471c-af2f-af1901ae77eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=122741785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.122741785
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.782678540
Short name T291
Test name
Test status
Simulation time 858118847 ps
CPU time 4.6 seconds
Started Jul 21 06:52:17 PM PDT 24
Finished Jul 21 06:52:22 PM PDT 24
Peak memory 206592 kb
Host smart-902d0e61-eaa5-4cd6-bbda-37f162a79d81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=782678540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.782678540
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.4089623340
Short name T268
Test name
Test status
Simulation time 326340287 ps
CPU time 2.54 seconds
Started Jul 21 06:52:05 PM PDT 24
Finished Jul 21 06:52:09 PM PDT 24
Peak memory 206476 kb
Host smart-07e5ebf5-448b-454b-bf04-84acf846ea8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4089623340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.4089623340
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.4247691418
Short name T92
Test name
Test status
Simulation time 5760720561 ps
CPU time 39.72 seconds
Started Jul 21 06:56:22 PM PDT 24
Finished Jul 21 06:57:02 PM PDT 24
Peak memory 207000 kb
Host smart-3a1b66de-a8b1-4bae-8573-934fe25c52d6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4247691418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.4247691418
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.2771772414
Short name T34
Test name
Test status
Simulation time 62375651 ps
CPU time 0.69 seconds
Started Jul 21 06:56:45 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206648 kb
Host smart-8458521c-72ad-411d-8560-7d8132bd72f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27717
72414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.2771772414
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.3809521355
Short name T28
Test name
Test status
Simulation time 170403224 ps
CPU time 0.8 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206672 kb
Host smart-deafb961-a523-4879-93ca-6579f6f248fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38095
21355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.3809521355
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.193990236
Short name T2317
Test name
Test status
Simulation time 23290767095 ps
CPU time 26.95 seconds
Started Jul 21 06:55:00 PM PDT 24
Finished Jul 21 06:55:28 PM PDT 24
Peak memory 206788 kb
Host smart-fa4e6f31-6579-4ab5-993a-0c9f01bc066e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19399
0236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.193990236
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.3405100512
Short name T502
Test name
Test status
Simulation time 307650623 ps
CPU time 1.96 seconds
Started Jul 21 06:54:50 PM PDT 24
Finished Jul 21 06:54:52 PM PDT 24
Peak memory 206832 kb
Host smart-bdc93d38-33be-43fa-8b5c-8120105026ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34051
00512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.3405100512
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2762205760
Short name T147
Test name
Test status
Simulation time 157207507 ps
CPU time 0.8 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206668 kb
Host smart-200d1a00-75c8-4cb1-9a3b-8f28362b96d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27622
05760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2762205760
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.301382946
Short name T59
Test name
Test status
Simulation time 201565328 ps
CPU time 0.84 seconds
Started Jul 21 06:53:10 PM PDT 24
Finished Jul 21 06:53:12 PM PDT 24
Peak memory 206660 kb
Host smart-01cdd8cb-792f-400c-a0b9-83b3e0f55f8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30138
2946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.301382946
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.3071838392
Short name T233
Test name
Test status
Simulation time 1524210192 ps
CPU time 5.66 seconds
Started Jul 21 06:52:09 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206500 kb
Host smart-ea3faec9-2b99-4ca8-a58f-07b959c3c052
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3071838392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.3071838392
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.4020015157
Short name T55
Test name
Test status
Simulation time 151484037 ps
CPU time 0.79 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:30 PM PDT 24
Peak memory 206680 kb
Host smart-e000d626-10bc-4086-8c55-f3f23245c384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40200
15157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.4020015157
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3523636083
Short name T61
Test name
Test status
Simulation time 4168380413 ps
CPU time 8.8 seconds
Started Jul 21 06:52:33 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206900 kb
Host smart-4ea54026-1d0b-4d3f-acbd-49cdc26bd166
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35236
36083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3523636083
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1037238646
Short name T62
Test name
Test status
Simulation time 183557346 ps
CPU time 0.77 seconds
Started Jul 21 06:52:31 PM PDT 24
Finished Jul 21 06:52:32 PM PDT 24
Peak memory 206632 kb
Host smart-fb25575b-d696-48c1-be95-4d5c6ddd88dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10372
38646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1037238646
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.2305119542
Short name T54
Test name
Test status
Simulation time 275628123 ps
CPU time 1.01 seconds
Started Jul 21 06:52:37 PM PDT 24
Finished Jul 21 06:52:39 PM PDT 24
Peak memory 206684 kb
Host smart-077c051d-1668-4f9b-94fc-ba0baf355d43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23051
19542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.2305119542
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.758029990
Short name T70
Test name
Test status
Simulation time 177370105 ps
CPU time 0.86 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:41 PM PDT 24
Peak memory 206412 kb
Host smart-392169f5-50be-425d-a4e6-9a1c48e038f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75802
9990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.758029990
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.1035452822
Short name T49
Test name
Test status
Simulation time 173049224 ps
CPU time 0.86 seconds
Started Jul 21 06:52:44 PM PDT 24
Finished Jul 21 06:52:45 PM PDT 24
Peak memory 206652 kb
Host smart-efcae7ed-a2bb-4aea-86da-79635d743432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10354
52822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.1035452822
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2108115156
Short name T481
Test name
Test status
Simulation time 4735176568 ps
CPU time 42.27 seconds
Started Jul 21 06:56:04 PM PDT 24
Finished Jul 21 06:56:47 PM PDT 24
Peak memory 206904 kb
Host smart-0b061a03-2673-4c58-80a9-a9ad529511d5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2108115156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2108115156
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.326903664
Short name T2777
Test name
Test status
Simulation time 110322791 ps
CPU time 2.01 seconds
Started Jul 21 06:51:59 PM PDT 24
Finished Jul 21 06:52:02 PM PDT 24
Peak memory 206624 kb
Host smart-d688bb09-8d3d-47a9-9c64-6d53ad34fd5a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=326903664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.326903664
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.1786122984
Short name T129
Test name
Test status
Simulation time 196195548 ps
CPU time 0.81 seconds
Started Jul 21 06:52:37 PM PDT 24
Finished Jul 21 06:52:38 PM PDT 24
Peak memory 206688 kb
Host smart-5a1ae057-df2f-4a4f-8a67-2f7f81d00243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17861
22984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.1786122984
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.2645512566
Short name T2103
Test name
Test status
Simulation time 5828541355 ps
CPU time 166.28 seconds
Started Jul 21 06:52:47 PM PDT 24
Finished Jul 21 06:55:34 PM PDT 24
Peak memory 206880 kb
Host smart-22550d8c-9f47-4853-ab3b-3ca5b87cc143
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2645512566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.2645512566
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.4252982268
Short name T172
Test name
Test status
Simulation time 13708221711 ps
CPU time 277.59 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:57:29 PM PDT 24
Peak memory 207020 kb
Host smart-0ddf45c1-c9b0-448e-9bf6-b3042ab65d38
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4252982268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.4252982268
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2958031475
Short name T2058
Test name
Test status
Simulation time 246408601 ps
CPU time 0.89 seconds
Started Jul 21 06:54:52 PM PDT 24
Finished Jul 21 06:54:54 PM PDT 24
Peak memory 206668 kb
Host smart-b198c39a-eb92-4e6f-ac0c-ba70b4bb1486
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
31475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2958031475
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.1254180268
Short name T110
Test name
Test status
Simulation time 199020546 ps
CPU time 0.88 seconds
Started Jul 21 06:55:05 PM PDT 24
Finished Jul 21 06:55:06 PM PDT 24
Peak memory 206788 kb
Host smart-1c542c3a-7d87-4852-983c-724464cb2fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12541
80268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.1254180268
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.3650628569
Short name T1495
Test name
Test status
Simulation time 265438925 ps
CPU time 0.94 seconds
Started Jul 21 06:55:26 PM PDT 24
Finished Jul 21 06:55:27 PM PDT 24
Peak memory 206680 kb
Host smart-c520bcda-3af3-405e-9353-4ff3b123fc95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36506
28569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.3650628569
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.3893011078
Short name T2316
Test name
Test status
Simulation time 221729920 ps
CPU time 0.92 seconds
Started Jul 21 06:55:48 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206652 kb
Host smart-fc3ec231-acfb-4b67-92cb-7be3794117d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38930
11078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.3893011078
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2400888025
Short name T115
Test name
Test status
Simulation time 248923910 ps
CPU time 0.88 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206664 kb
Host smart-3052d2c1-5100-453e-9448-ffc4572a59a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24008
88025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2400888025
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.7445065
Short name T120
Test name
Test status
Simulation time 215309732 ps
CPU time 0.86 seconds
Started Jul 21 06:56:08 PM PDT 24
Finished Jul 21 06:56:09 PM PDT 24
Peak memory 206656 kb
Host smart-3b9241a7-ad3b-4963-a39c-8ce63daec275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74450
65 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.7445065
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.4177816656
Short name T112
Test name
Test status
Simulation time 166330873 ps
CPU time 0.82 seconds
Started Jul 21 06:56:14 PM PDT 24
Finished Jul 21 06:56:15 PM PDT 24
Peak memory 206680 kb
Host smart-d05c43bb-c595-4e05-95c2-e8815465f503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41778
16656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.4177816656
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3274158281
Short name T117
Test name
Test status
Simulation time 247468478 ps
CPU time 0.9 seconds
Started Jul 21 06:53:00 PM PDT 24
Finished Jul 21 06:53:02 PM PDT 24
Peak memory 206676 kb
Host smart-fc9de34e-f943-4082-ac59-62a8912561e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32741
58281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3274158281
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3397034192
Short name T114
Test name
Test status
Simulation time 206381446 ps
CPU time 0.88 seconds
Started Jul 21 06:58:11 PM PDT 24
Finished Jul 21 06:58:12 PM PDT 24
Peak memory 206664 kb
Host smart-8ced2334-fa41-473f-ba79-2984ff059c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33970
34192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3397034192
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.2710343041
Short name T123
Test name
Test status
Simulation time 227909233 ps
CPU time 0.89 seconds
Started Jul 21 06:59:21 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206708 kb
Host smart-41abd8e7-d9bc-4cb2-be76-565a1b125303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27103
43041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.2710343041
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_invalid_sync.1718824681
Short name T98
Test name
Test status
Simulation time 9557395306 ps
CPU time 66.71 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:02:00 PM PDT 24
Peak memory 206912 kb
Host smart-dbdb5122-d9c6-4822-8218-212d897eece4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1718824681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_invalid_sync.1718824681
Directory /workspace/49.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.3517005811
Short name T2832
Test name
Test status
Simulation time 86212230 ps
CPU time 1.94 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206524 kb
Host smart-4578a288-23c5-4fa8-a1fb-f1c1d853d17b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3517005811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.3517005811
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.3945587043
Short name T2854
Test name
Test status
Simulation time 705595883 ps
CPU time 4.67 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206440 kb
Host smart-f7528df9-0dfd-467f-86b2-6f3287341215
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3945587043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.3945587043
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3698129286
Short name T2813
Test name
Test status
Simulation time 137787866 ps
CPU time 0.96 seconds
Started Jul 21 06:51:54 PM PDT 24
Finished Jul 21 06:51:56 PM PDT 24
Peak memory 206340 kb
Host smart-757cdea1-2629-4ab7-bdd3-61455c26bb35
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3698129286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3698129286
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.3257853122
Short name T271
Test name
Test status
Simulation time 191442985 ps
CPU time 1.91 seconds
Started Jul 21 06:51:54 PM PDT 24
Finished Jul 21 06:51:57 PM PDT 24
Peak memory 214796 kb
Host smart-1152a183-3400-42ef-a09e-edd1f4680cc4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257853122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.3257853122
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.1143910703
Short name T254
Test name
Test status
Simulation time 134868627 ps
CPU time 0.95 seconds
Started Jul 21 06:51:52 PM PDT 24
Finished Jul 21 06:51:54 PM PDT 24
Peak memory 206292 kb
Host smart-4e88a5a8-7010-44a6-9258-2ebc305f1ef7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1143910703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.1143910703
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.209283806
Short name T2794
Test name
Test status
Simulation time 108352642 ps
CPU time 0.76 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:02 PM PDT 24
Peak memory 206328 kb
Host smart-06162ca3-ede9-4a15-81ed-9050ddfeb87e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=209283806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.209283806
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3708312945
Short name T256
Test name
Test status
Simulation time 113437893 ps
CPU time 1.46 seconds
Started Jul 21 06:51:56 PM PDT 24
Finished Jul 21 06:51:58 PM PDT 24
Peak memory 214792 kb
Host smart-bd440ada-c1b5-4ed8-bb17-8159cc1f01d8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3708312945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3708312945
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.4240128184
Short name T2855
Test name
Test status
Simulation time 748818658 ps
CPU time 5.05 seconds
Started Jul 21 06:51:51 PM PDT 24
Finished Jul 21 06:51:58 PM PDT 24
Peak memory 206368 kb
Host smart-3a3fcf20-25eb-42a0-914f-e5315756a374
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4240128184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.4240128184
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1843048037
Short name T192
Test name
Test status
Simulation time 256627030 ps
CPU time 1.55 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206504 kb
Host smart-6ad71434-6aed-41e9-8b3e-07500c9532d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1843048037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1843048037
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.950253966
Short name T2815
Test name
Test status
Simulation time 195585345 ps
CPU time 2.09 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:00 PM PDT 24
Peak memory 206364 kb
Host smart-bc5f2d80-8e30-4c1b-ac1f-e4ccea9ada9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=950253966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.950253966
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.4026369702
Short name T2834
Test name
Test status
Simulation time 1059331466 ps
CPU time 9.83 seconds
Started Jul 21 06:52:01 PM PDT 24
Finished Jul 21 06:52:12 PM PDT 24
Peak memory 206356 kb
Host smart-b690eab7-3fb0-4989-9c8b-32891670773f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4026369702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.4026369702
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.81313434
Short name T2787
Test name
Test status
Simulation time 73923244 ps
CPU time 0.85 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:51:59 PM PDT 24
Peak memory 206356 kb
Host smart-32338781-7b14-419d-9baf-304477fe69ee
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=81313434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.81313434
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3874640825
Short name T235
Test name
Test status
Simulation time 111657927 ps
CPU time 1.82 seconds
Started Jul 21 06:51:59 PM PDT 24
Finished Jul 21 06:52:01 PM PDT 24
Peak memory 214808 kb
Host smart-099e1cf5-3df4-4503-ab66-f35defc444c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874640825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3874640825
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.1497348269
Short name T2829
Test name
Test status
Simulation time 78001580 ps
CPU time 1.04 seconds
Started Jul 21 06:51:58 PM PDT 24
Finished Jul 21 06:52:00 PM PDT 24
Peak memory 206376 kb
Host smart-d989daa6-ebb7-430a-ab36-f7ce94a303de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1497348269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.1497348269
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.1175186643
Short name T255
Test name
Test status
Simulation time 108954788 ps
CPU time 1.4 seconds
Started Jul 21 06:51:52 PM PDT 24
Finished Jul 21 06:51:54 PM PDT 24
Peak memory 214764 kb
Host smart-4ee7b54a-9e35-4355-ab56-dbf61b242ff7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1175186643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.1175186643
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1121243074
Short name T2801
Test name
Test status
Simulation time 275546073 ps
CPU time 2.79 seconds
Started Jul 21 06:51:55 PM PDT 24
Finished Jul 21 06:51:58 PM PDT 24
Peak memory 206416 kb
Host smart-1029ee4c-9532-4927-8ec2-ddea4e9b5344
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1121243074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1121243074
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.1913657835
Short name T2779
Test name
Test status
Simulation time 174034879 ps
CPU time 1.66 seconds
Started Jul 21 06:52:01 PM PDT 24
Finished Jul 21 06:52:04 PM PDT 24
Peak memory 206560 kb
Host smart-b1ab3601-8eef-4b31-b9ce-27ef2d03d02b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1913657835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.1913657835
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3537373796
Short name T232
Test name
Test status
Simulation time 64660025 ps
CPU time 1.42 seconds
Started Jul 21 06:51:54 PM PDT 24
Finished Jul 21 06:51:57 PM PDT 24
Peak memory 206632 kb
Host smart-00d688a8-ea0f-4032-a4ae-d03842b195ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3537373796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3537373796
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3102218807
Short name T216
Test name
Test status
Simulation time 231835468 ps
CPU time 1.91 seconds
Started Jul 21 06:52:13 PM PDT 24
Finished Jul 21 06:52:16 PM PDT 24
Peak memory 214768 kb
Host smart-c5f89a5e-5992-4091-8833-a23f3ed9a258
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102218807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3102218807
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.2309475389
Short name T2831
Test name
Test status
Simulation time 101621004 ps
CPU time 0.85 seconds
Started Jul 21 06:52:07 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 206388 kb
Host smart-7f9f0b0f-b909-4ecb-8b0e-a86a5d75fb32
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2309475389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.2309475389
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.29239507
Short name T2771
Test name
Test status
Simulation time 35676569 ps
CPU time 0.66 seconds
Started Jul 21 06:52:08 PM PDT 24
Finished Jul 21 06:52:09 PM PDT 24
Peak memory 206304 kb
Host smart-ae28b812-8b79-4f07-975d-26db79eaef28
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=29239507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.29239507
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2295552794
Short name T2826
Test name
Test status
Simulation time 210537134 ps
CPU time 1.74 seconds
Started Jul 21 06:52:11 PM PDT 24
Finished Jul 21 06:52:13 PM PDT 24
Peak memory 206592 kb
Host smart-90862c42-508a-42b6-941a-39263f3ba07b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2295552794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2295552794
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1430999775
Short name T2843
Test name
Test status
Simulation time 180743304 ps
CPU time 2.18 seconds
Started Jul 21 06:52:13 PM PDT 24
Finished Jul 21 06:52:16 PM PDT 24
Peak memory 206484 kb
Host smart-06cee152-6f1d-4a5f-81a2-cbfc6e86987f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1430999775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1430999775
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.3310354163
Short name T217
Test name
Test status
Simulation time 202265941 ps
CPU time 2.15 seconds
Started Jul 21 06:52:11 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 214764 kb
Host smart-2a9b6463-972c-4836-b801-6df412ba2028
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310354163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.3310354163
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.3567253576
Short name T2770
Test name
Test status
Simulation time 71232945 ps
CPU time 0.83 seconds
Started Jul 21 06:52:07 PM PDT 24
Finished Jul 21 06:52:09 PM PDT 24
Peak memory 206384 kb
Host smart-61bc9ebf-03e2-4a50-a8c6-5f93a32d2e4b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3567253576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.3567253576
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2727754670
Short name T2846
Test name
Test status
Simulation time 71305088 ps
CPU time 0.68 seconds
Started Jul 21 06:52:12 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 206284 kb
Host smart-45abe935-422d-494d-9489-04eb8ec5dec0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2727754670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2727754670
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3164475089
Short name T2778
Test name
Test status
Simulation time 111253617 ps
CPU time 1.1 seconds
Started Jul 21 06:52:10 PM PDT 24
Finished Jul 21 06:52:12 PM PDT 24
Peak memory 206496 kb
Host smart-bf2f432d-563d-47fd-910f-f90c5accf69a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3164475089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3164475089
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.394052569
Short name T2767
Test name
Test status
Simulation time 96670053 ps
CPU time 2.69 seconds
Started Jul 21 06:52:06 PM PDT 24
Finished Jul 21 06:52:10 PM PDT 24
Peak memory 214720 kb
Host smart-4cfca797-5b09-41c3-b6d2-8b2be9f93f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=394052569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.394052569
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3486145392
Short name T289
Test name
Test status
Simulation time 563764900 ps
CPU time 2.97 seconds
Started Jul 21 06:52:08 PM PDT 24
Finished Jul 21 06:52:11 PM PDT 24
Peak memory 206520 kb
Host smart-715c4e62-f0ac-4084-9786-b55b4626b0c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3486145392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3486145392
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.1488440227
Short name T2803
Test name
Test status
Simulation time 106132188 ps
CPU time 2.48 seconds
Started Jul 21 06:52:14 PM PDT 24
Finished Jul 21 06:52:17 PM PDT 24
Peak memory 214752 kb
Host smart-12c1af9f-dd1b-4fe6-9759-4d4c45ba895b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488440227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.1488440227
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2655992652
Short name T261
Test name
Test status
Simulation time 63609153 ps
CPU time 0.82 seconds
Started Jul 21 06:52:13 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206280 kb
Host smart-eca08614-1859-4413-9995-22461ac344cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2655992652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2655992652
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.866095060
Short name T2861
Test name
Test status
Simulation time 42845595 ps
CPU time 0.64 seconds
Started Jul 21 06:52:12 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 206328 kb
Host smart-8c6176f6-0937-4aba-a2c5-f2b61689cdeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=866095060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.866095060
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2845315443
Short name T264
Test name
Test status
Simulation time 200148706 ps
CPU time 1.67 seconds
Started Jul 21 06:52:12 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206492 kb
Host smart-e3d311a7-edc6-4fc6-9eab-cabe0bfaff8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2845315443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2845315443
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1943363774
Short name T2782
Test name
Test status
Simulation time 252484048 ps
CPU time 3.15 seconds
Started Jul 21 06:52:08 PM PDT 24
Finished Jul 21 06:52:12 PM PDT 24
Peak memory 214764 kb
Host smart-64509d5d-3f29-42c6-8375-3582f7e050a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1943363774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1943363774
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.714007829
Short name T290
Test name
Test status
Simulation time 507232639 ps
CPU time 2.7 seconds
Started Jul 21 06:52:11 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206468 kb
Host smart-1605b6e0-759d-470f-b5bb-b79fe3843c23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=714007829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.714007829
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.4247125315
Short name T2800
Test name
Test status
Simulation time 253785173 ps
CPU time 2.01 seconds
Started Jul 21 06:52:12 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 214760 kb
Host smart-d4a17b54-6286-4d63-ab46-153008f1d49a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247125315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.4247125315
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1628359097
Short name T2852
Test name
Test status
Simulation time 51113406 ps
CPU time 0.92 seconds
Started Jul 21 06:52:13 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206328 kb
Host smart-1c912225-a66a-43b6-9221-5b931cfb1d07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1628359097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1628359097
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.2374403852
Short name T2814
Test name
Test status
Simulation time 148932824 ps
CPU time 1.31 seconds
Started Jul 21 06:52:11 PM PDT 24
Finished Jul 21 06:52:13 PM PDT 24
Peak memory 206424 kb
Host smart-d8540100-abb0-4680-b7af-d83f99cce1be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2374403852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.2374403852
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3279210268
Short name T2847
Test name
Test status
Simulation time 111715162 ps
CPU time 2.99 seconds
Started Jul 21 06:52:12 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 222228 kb
Host smart-a5e44626-7867-4b87-974b-6a5bddfc23d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3279210268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3279210268
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.1475769310
Short name T189
Test name
Test status
Simulation time 1345568175 ps
CPU time 5.91 seconds
Started Jul 21 06:52:15 PM PDT 24
Finished Jul 21 06:52:22 PM PDT 24
Peak memory 206592 kb
Host smart-f3a7073d-2594-451f-a670-f9a6ce7cd44a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1475769310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.1475769310
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3605594897
Short name T2762
Test name
Test status
Simulation time 67398872 ps
CPU time 1.61 seconds
Started Jul 21 06:52:12 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 214676 kb
Host smart-1f90e66b-0a37-41dc-bdd5-d365e9807485
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605594897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3605594897
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.3970973298
Short name T2784
Test name
Test status
Simulation time 89828129 ps
CPU time 0.95 seconds
Started Jul 21 06:52:15 PM PDT 24
Finished Jul 21 06:52:17 PM PDT 24
Peak memory 206380 kb
Host smart-678131a8-cb00-4077-bf97-aa1e65a52f14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3970973298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.3970973298
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.2223344960
Short name T2840
Test name
Test status
Simulation time 34354962 ps
CPU time 0.69 seconds
Started Jul 21 06:52:13 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206340 kb
Host smart-d2200096-8de4-4378-92cd-1fc096a576c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223344960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.2223344960
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2257799696
Short name T2818
Test name
Test status
Simulation time 189403070 ps
CPU time 1.21 seconds
Started Jul 21 06:52:12 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 206548 kb
Host smart-3a3b7022-caee-4a5f-a761-b15894e52a3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2257799696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2257799696
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2565552944
Short name T222
Test name
Test status
Simulation time 248707883 ps
CPU time 2.62 seconds
Started Jul 21 06:52:14 PM PDT 24
Finished Jul 21 06:52:17 PM PDT 24
Peak memory 214792 kb
Host smart-28d64e94-b8c6-48f9-bde9-c257881f622e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2565552944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2565552944
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3315433140
Short name T190
Test name
Test status
Simulation time 301174914 ps
CPU time 2.62 seconds
Started Jul 21 06:52:15 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 206564 kb
Host smart-ffe938a0-8729-4707-8a46-8d584808c8fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3315433140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3315433140
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3548855578
Short name T2758
Test name
Test status
Simulation time 88042749 ps
CPU time 2.15 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:20 PM PDT 24
Peak memory 214744 kb
Host smart-2e33d118-0d6b-4c0c-807a-70a62af3d3f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548855578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3548855578
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.4226165920
Short name T259
Test name
Test status
Simulation time 86493614 ps
CPU time 1.01 seconds
Started Jul 21 06:52:15 PM PDT 24
Finished Jul 21 06:52:17 PM PDT 24
Peak memory 206428 kb
Host smart-0b76acac-141c-4c14-ad99-1d90565fcf2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4226165920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.4226165920
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.3499289193
Short name T2853
Test name
Test status
Simulation time 50911432 ps
CPU time 0.72 seconds
Started Jul 21 06:52:14 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206336 kb
Host smart-68858775-9476-4886-8130-ce2e42798739
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3499289193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.3499289193
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2641390367
Short name T2768
Test name
Test status
Simulation time 256905437 ps
CPU time 1.94 seconds
Started Jul 21 06:52:24 PM PDT 24
Finished Jul 21 06:52:26 PM PDT 24
Peak memory 206548 kb
Host smart-1dca46b3-c82c-4859-b213-ae7844de4de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2641390367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2641390367
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.592676322
Short name T2836
Test name
Test status
Simulation time 228834351 ps
CPU time 2.43 seconds
Started Jul 21 06:52:15 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 206624 kb
Host smart-0e2ee24a-69f1-4db6-89b7-4b7f728a7580
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=592676322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.592676322
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.3050866541
Short name T2845
Test name
Test status
Simulation time 467969054 ps
CPU time 3.07 seconds
Started Jul 21 06:52:14 PM PDT 24
Finished Jul 21 06:52:18 PM PDT 24
Peak memory 206548 kb
Host smart-0e67b7f6-63f0-43fb-a602-6d742ef54b67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3050866541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.3050866541
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.2596868440
Short name T226
Test name
Test status
Simulation time 156710298 ps
CPU time 1.76 seconds
Started Jul 21 06:52:19 PM PDT 24
Finished Jul 21 06:52:21 PM PDT 24
Peak memory 223012 kb
Host smart-e2b281af-22cf-43c4-8f49-b34f113e102c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596868440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.2596868440
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2392937482
Short name T247
Test name
Test status
Simulation time 51946711 ps
CPU time 0.84 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:18 PM PDT 24
Peak memory 206336 kb
Host smart-7309b7d3-3e32-492a-8e04-7c1d34e4ae2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2392937482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2392937482
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.2067543724
Short name T2811
Test name
Test status
Simulation time 99595737 ps
CPU time 0.76 seconds
Started Jul 21 06:52:21 PM PDT 24
Finished Jul 21 06:52:22 PM PDT 24
Peak memory 206312 kb
Host smart-a6289d22-448f-4eb6-8d59-fa16d1e19020
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2067543724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.2067543724
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1563360472
Short name T2799
Test name
Test status
Simulation time 159280008 ps
CPU time 1.22 seconds
Started Jul 21 06:52:17 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 206592 kb
Host smart-6428e7f0-b8cd-462a-b648-fe8af26c428f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1563360472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1563360472
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.3850667726
Short name T2816
Test name
Test status
Simulation time 78669551 ps
CPU time 1.62 seconds
Started Jul 21 06:52:18 PM PDT 24
Finished Jul 21 06:52:21 PM PDT 24
Peak memory 206668 kb
Host smart-85ba36d7-f61b-492b-9b5d-232349faa54d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3850667726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.3850667726
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3513711356
Short name T2781
Test name
Test status
Simulation time 98587585 ps
CPU time 1.3 seconds
Started Jul 21 06:52:17 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 214752 kb
Host smart-ddb3110b-d6f1-4938-9b3b-37efb919d09e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513711356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.3513711356
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1345277141
Short name T2827
Test name
Test status
Simulation time 42329307 ps
CPU time 0.74 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:17 PM PDT 24
Peak memory 206340 kb
Host smart-c2cb26ec-a175-4aad-9784-9ba2394fdf94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1345277141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1345277141
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.507286361
Short name T2804
Test name
Test status
Simulation time 209342018 ps
CPU time 1.69 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 206604 kb
Host smart-5d22ece2-1a85-4c3a-a97f-7d1cbad73820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=507286361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.507286361
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.2229614856
Short name T227
Test name
Test status
Simulation time 119758461 ps
CPU time 2.48 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:20 PM PDT 24
Peak memory 206692 kb
Host smart-040383a1-b483-4313-a398-9cee7966567d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2229614856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.2229614856
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3699187523
Short name T236
Test name
Test status
Simulation time 125801388 ps
CPU time 1.26 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 214768 kb
Host smart-7f59b2b4-93c0-412d-9eac-76f08b232df4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699187523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3699187523
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.4203918281
Short name T2820
Test name
Test status
Simulation time 61213166 ps
CPU time 0.88 seconds
Started Jul 21 06:52:18 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 206372 kb
Host smart-27f34fde-a635-4e0c-a361-cacc394e1b51
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4203918281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.4203918281
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.1546676352
Short name T2805
Test name
Test status
Simulation time 33318467 ps
CPU time 0.66 seconds
Started Jul 21 06:52:15 PM PDT 24
Finished Jul 21 06:52:17 PM PDT 24
Peak memory 206288 kb
Host smart-cffd8eff-d44c-496b-8df4-a5ade8da3826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546676352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.1546676352
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.3116190310
Short name T2802
Test name
Test status
Simulation time 183004204 ps
CPU time 1.71 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 206576 kb
Host smart-f869812f-189a-4fdd-ab40-2396193dad95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3116190310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.3116190310
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.2068065952
Short name T230
Test name
Test status
Simulation time 278372609 ps
CPU time 3.43 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:21 PM PDT 24
Peak memory 222296 kb
Host smart-cb3b179f-e4c3-4b30-96ac-358c45795fbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2068065952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.2068065952
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.2416693304
Short name T2839
Test name
Test status
Simulation time 374957852 ps
CPU time 2.92 seconds
Started Jul 21 06:52:19 PM PDT 24
Finished Jul 21 06:52:23 PM PDT 24
Peak memory 206548 kb
Host smart-631098b9-d85d-43e0-9e7f-0f2b59cf0c4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2416693304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.2416693304
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.1154114980
Short name T2783
Test name
Test status
Simulation time 72261627 ps
CPU time 1.87 seconds
Started Jul 21 06:52:22 PM PDT 24
Finished Jul 21 06:52:24 PM PDT 24
Peak memory 214800 kb
Host smart-ed681114-09bd-42c8-9ebe-e7cb327918fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154114980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.1154114980
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1074126986
Short name T263
Test name
Test status
Simulation time 72488355 ps
CPU time 0.83 seconds
Started Jul 21 06:52:20 PM PDT 24
Finished Jul 21 06:52:21 PM PDT 24
Peak memory 206348 kb
Host smart-6c0e7657-c855-4005-8176-6c8d988adc8f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1074126986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1074126986
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.597647254
Short name T275
Test name
Test status
Simulation time 46748676 ps
CPU time 0.65 seconds
Started Jul 21 06:52:21 PM PDT 24
Finished Jul 21 06:52:22 PM PDT 24
Peak memory 206288 kb
Host smart-03de9709-1993-40f5-97c7-8ab624e991a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=597647254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.597647254
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2730333665
Short name T260
Test name
Test status
Simulation time 415405410 ps
CPU time 2.23 seconds
Started Jul 21 06:52:23 PM PDT 24
Finished Jul 21 06:52:25 PM PDT 24
Peak memory 206488 kb
Host smart-85e9bb67-1ed8-4d6d-a0d7-a894143014a5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2730333665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2730333665
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1013564167
Short name T225
Test name
Test status
Simulation time 75513258 ps
CPU time 1.85 seconds
Started Jul 21 06:52:16 PM PDT 24
Finished Jul 21 06:52:19 PM PDT 24
Peak memory 214752 kb
Host smart-a7bad2a3-b3dc-4064-8c96-53e75054e71f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1013564167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1013564167
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.4005247701
Short name T191
Test name
Test status
Simulation time 336471002 ps
CPU time 2.48 seconds
Started Jul 21 06:52:21 PM PDT 24
Finished Jul 21 06:52:24 PM PDT 24
Peak memory 206572 kb
Host smart-9969e1aa-2239-45fb-adae-01385bac8c90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4005247701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.4005247701
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2227096675
Short name T253
Test name
Test status
Simulation time 195654175 ps
CPU time 3.52 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:05 PM PDT 24
Peak memory 206512 kb
Host smart-93e82c6e-5016-4c0b-a9f0-4ddbab7f1269
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2227096675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2227096675
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.649788173
Short name T2810
Test name
Test status
Simulation time 833757028 ps
CPU time 6.22 seconds
Started Jul 21 06:52:01 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 206308 kb
Host smart-a42f4414-0f82-4079-9eb8-6bf9ca477f1d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=649788173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.649788173
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.251250223
Short name T2841
Test name
Test status
Simulation time 81626934 ps
CPU time 0.84 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:51:58 PM PDT 24
Peak memory 206296 kb
Host smart-ae873082-30c0-4838-bcee-df48af600890
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=251250223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.251250223
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.837189460
Short name T2769
Test name
Test status
Simulation time 98154048 ps
CPU time 1.32 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:00 PM PDT 24
Peak memory 214776 kb
Host smart-dbcb0fb0-0be2-405e-830d-414bc5a04a3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=837189460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev
_csr_mem_rw_with_rand_reset.837189460
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1784853774
Short name T2838
Test name
Test status
Simulation time 80900415 ps
CPU time 1.07 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206416 kb
Host smart-78149c53-3f9e-40ba-b6c0-3671aeb78b1a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1784853774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1784853774
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2796859591
Short name T2862
Test name
Test status
Simulation time 44270574 ps
CPU time 0.69 seconds
Started Jul 21 06:51:59 PM PDT 24
Finished Jul 21 06:52:01 PM PDT 24
Peak memory 206308 kb
Host smart-1a1eb701-b703-4d1d-898a-9ce7a1fd9bbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2796859591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2796859591
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.529645666
Short name T252
Test name
Test status
Simulation time 100927172 ps
CPU time 1.44 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:00 PM PDT 24
Peak memory 214684 kb
Host smart-630ebe33-9a2b-44c0-b69e-3e50f81c087d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=529645666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.529645666
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3837723076
Short name T2857
Test name
Test status
Simulation time 736327957 ps
CPU time 4.67 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206404 kb
Host smart-eb36cfa2-462b-4fe8-8704-3a3ded42ec6e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3837723076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3837723076
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.13368490
Short name T2828
Test name
Test status
Simulation time 118171656 ps
CPU time 1.6 seconds
Started Jul 21 06:51:55 PM PDT 24
Finished Jul 21 06:51:58 PM PDT 24
Peak memory 206516 kb
Host smart-ccc57345-9d1f-4257-b427-c5ff22a343e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=13368490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.13368490
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1678317007
Short name T2764
Test name
Test status
Simulation time 312159362 ps
CPU time 3.38 seconds
Started Jul 21 06:52:03 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 214840 kb
Host smart-56d60aa4-0081-48a4-a56a-e217f0600b27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1678317007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1678317007
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.2747822360
Short name T292
Test name
Test status
Simulation time 423749932 ps
CPU time 2.91 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:01 PM PDT 24
Peak memory 206504 kb
Host smart-e43a92f3-4e17-4997-863d-d06b947a82d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2747822360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.2747822360
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.54328225
Short name T282
Test name
Test status
Simulation time 46928276 ps
CPU time 0.74 seconds
Started Jul 21 06:52:25 PM PDT 24
Finished Jul 21 06:52:26 PM PDT 24
Peak memory 206300 kb
Host smart-177aaf90-ea3d-4b0b-b30f-c9ac35321f2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=54328225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.54328225
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.843275420
Short name T286
Test name
Test status
Simulation time 40320480 ps
CPU time 0.66 seconds
Started Jul 21 06:52:22 PM PDT 24
Finished Jul 21 06:52:23 PM PDT 24
Peak memory 206312 kb
Host smart-6d5f1137-a9c9-4269-a2cf-9603f0ab36fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=843275420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.843275420
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.1723293132
Short name T2791
Test name
Test status
Simulation time 43618857 ps
CPU time 0.67 seconds
Started Jul 21 06:52:21 PM PDT 24
Finished Jul 21 06:52:23 PM PDT 24
Peak memory 206260 kb
Host smart-71015969-d57d-436e-b99c-cf17d410c825
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1723293132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.1723293132
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1019349120
Short name T2797
Test name
Test status
Simulation time 41620790 ps
CPU time 0.68 seconds
Started Jul 21 06:52:20 PM PDT 24
Finished Jul 21 06:52:21 PM PDT 24
Peak memory 206380 kb
Host smart-035b6d24-7647-4c11-8e67-17c09b3c6157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1019349120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1019349120
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.640877890
Short name T2780
Test name
Test status
Simulation time 71319694 ps
CPU time 0.69 seconds
Started Jul 21 06:52:20 PM PDT 24
Finished Jul 21 06:52:21 PM PDT 24
Peak memory 206272 kb
Host smart-ff747062-d6bb-4927-8586-829a97851270
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=640877890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.640877890
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1676667308
Short name T272
Test name
Test status
Simulation time 42103389 ps
CPU time 0.69 seconds
Started Jul 21 06:52:23 PM PDT 24
Finished Jul 21 06:52:24 PM PDT 24
Peak memory 206300 kb
Host smart-156ce8a7-d1b0-4859-bb7c-4ea67c5dc892
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1676667308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1676667308
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.3584537165
Short name T2792
Test name
Test status
Simulation time 40333049 ps
CPU time 0.68 seconds
Started Jul 21 06:52:23 PM PDT 24
Finished Jul 21 06:52:24 PM PDT 24
Peak memory 206328 kb
Host smart-dabbe8db-b561-465f-a57f-b0b85999f1a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3584537165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.3584537165
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2233807179
Short name T2786
Test name
Test status
Simulation time 49331768 ps
CPU time 0.7 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:28 PM PDT 24
Peak memory 206248 kb
Host smart-45ecd28f-3bcb-4f58-b2d3-3953bc751f75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2233807179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2233807179
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.1003568800
Short name T257
Test name
Test status
Simulation time 105610914 ps
CPU time 1.94 seconds
Started Jul 21 06:51:58 PM PDT 24
Finished Jul 21 06:52:01 PM PDT 24
Peak memory 206472 kb
Host smart-856d63fd-6f17-4dbe-a1dd-bfd89329e256
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1003568800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.1003568800
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4136625415
Short name T2809
Test name
Test status
Simulation time 810502024 ps
CPU time 4.57 seconds
Started Jul 21 06:51:59 PM PDT 24
Finished Jul 21 06:52:05 PM PDT 24
Peak memory 206456 kb
Host smart-b657de58-b60d-414c-aca1-d8038e6b3750
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4136625415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4136625415
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.515528031
Short name T2757
Test name
Test status
Simulation time 140727298 ps
CPU time 0.86 seconds
Started Jul 21 06:51:59 PM PDT 24
Finished Jul 21 06:52:01 PM PDT 24
Peak memory 206324 kb
Host smart-9daa5e73-8555-4e3f-b9fa-c5eccf4e1924
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=515528031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.515528031
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2581789630
Short name T2760
Test name
Test status
Simulation time 116039438 ps
CPU time 2.5 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:04 PM PDT 24
Peak memory 214732 kb
Host smart-15efa2c3-e318-454b-ae63-1888490840d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581789630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2581789630
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.692478022
Short name T262
Test name
Test status
Simulation time 59571864 ps
CPU time 0.8 seconds
Started Jul 21 06:51:58 PM PDT 24
Finished Jul 21 06:51:59 PM PDT 24
Peak memory 206300 kb
Host smart-c2914333-1be9-4051-910b-9aa55196bc43
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=692478022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.692478022
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2383548165
Short name T274
Test name
Test status
Simulation time 36011960 ps
CPU time 0.68 seconds
Started Jul 21 06:52:07 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 206360 kb
Host smart-f47ed0d4-443f-4c04-82c3-d30f1d7fe4f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2383548165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2383548165
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.3255421871
Short name T2850
Test name
Test status
Simulation time 106372026 ps
CPU time 2.2 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:00 PM PDT 24
Peak memory 214800 kb
Host smart-1c391dd6-a1ba-4f04-8a36-ef6a74c9222e
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3255421871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.3255421871
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2804191987
Short name T2837
Test name
Test status
Simulation time 178906328 ps
CPU time 4.07 seconds
Started Jul 21 06:51:58 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206448 kb
Host smart-5f88efbf-0c20-4516-9352-8ed293ba3f03
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2804191987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2804191987
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2834754891
Short name T2859
Test name
Test status
Simulation time 185623012 ps
CPU time 1.67 seconds
Started Jul 21 06:51:57 PM PDT 24
Finished Jul 21 06:52:00 PM PDT 24
Peak memory 206508 kb
Host smart-7129b6a7-d799-4e8c-81a5-cb2aabc6b4ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2834754891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2834754891
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1550109415
Short name T2822
Test name
Test status
Simulation time 317954399 ps
CPU time 2.4 seconds
Started Jul 21 06:52:03 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 206540 kb
Host smart-cfc5e1dd-24a8-4103-943e-fa8b354a43c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1550109415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1550109415
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.4030843069
Short name T2785
Test name
Test status
Simulation time 41152014 ps
CPU time 0.67 seconds
Started Jul 21 06:52:22 PM PDT 24
Finished Jul 21 06:52:23 PM PDT 24
Peak memory 206312 kb
Host smart-f3ca9f02-95ea-4e5c-a1f8-0e849b1a2c10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4030843069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.4030843069
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2637135663
Short name T281
Test name
Test status
Simulation time 37141761 ps
CPU time 0.67 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:28 PM PDT 24
Peak memory 206304 kb
Host smart-75079aaa-6844-416f-a823-7206c15b7667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637135663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2637135663
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.3512277337
Short name T283
Test name
Test status
Simulation time 31697500 ps
CPU time 0.68 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:28 PM PDT 24
Peak memory 206260 kb
Host smart-8b41448e-5276-44b0-9fe3-ed0d495b1e0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3512277337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.3512277337
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2561519916
Short name T285
Test name
Test status
Simulation time 44825097 ps
CPU time 0.68 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:29 PM PDT 24
Peak memory 206308 kb
Host smart-f442fc57-cdc1-4a9f-aa97-7020aff281bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2561519916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2561519916
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.281691050
Short name T2823
Test name
Test status
Simulation time 49726418 ps
CPU time 0.66 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:28 PM PDT 24
Peak memory 206300 kb
Host smart-7469413f-df9d-4dec-90eb-6918fa703d0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=281691050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.281691050
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1351202606
Short name T2790
Test name
Test status
Simulation time 32682357 ps
CPU time 0.7 seconds
Started Jul 21 06:52:29 PM PDT 24
Finished Jul 21 06:52:30 PM PDT 24
Peak memory 206312 kb
Host smart-40439028-6e2f-4abc-9ea9-8e20dca3707c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1351202606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1351202606
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.113695413
Short name T2817
Test name
Test status
Simulation time 36373818 ps
CPU time 0.69 seconds
Started Jul 21 06:52:26 PM PDT 24
Finished Jul 21 06:52:27 PM PDT 24
Peak memory 206228 kb
Host smart-92343c19-6f47-440d-9419-849307f93429
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=113695413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.113695413
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.825234288
Short name T200
Test name
Test status
Simulation time 42753245 ps
CPU time 0.65 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:29 PM PDT 24
Peak memory 206332 kb
Host smart-638191bb-19e5-4a13-8fdd-2ef524a6dc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=825234288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.825234288
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.3729738672
Short name T258
Test name
Test status
Simulation time 342215538 ps
CPU time 3.63 seconds
Started Jul 21 06:52:10 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 206416 kb
Host smart-1ec7f075-ac4a-430a-ae89-130d0d4ffea7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3729738672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.3729738672
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3455062823
Short name T250
Test name
Test status
Simulation time 1205943752 ps
CPU time 9.08 seconds
Started Jul 21 06:52:03 PM PDT 24
Finished Jul 21 06:52:14 PM PDT 24
Peak memory 206376 kb
Host smart-04a79bcf-c260-405f-a6d7-34ee3c83acfa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3455062823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3455062823
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2771196007
Short name T2830
Test name
Test status
Simulation time 66681147 ps
CPU time 0.81 seconds
Started Jul 21 06:52:01 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206316 kb
Host smart-47b654d8-7141-4162-8054-368abb843398
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2771196007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2771196007
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3737644418
Short name T2763
Test name
Test status
Simulation time 158430866 ps
CPU time 1.46 seconds
Started Jul 21 06:52:01 PM PDT 24
Finished Jul 21 06:52:04 PM PDT 24
Peak memory 214780 kb
Host smart-13de9a31-ed44-47d2-9fbe-53e76d43badd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737644418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.3737644418
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.620681940
Short name T2761
Test name
Test status
Simulation time 61582496 ps
CPU time 0.93 seconds
Started Jul 21 06:52:06 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 206248 kb
Host smart-50f72034-e157-4e87-932e-7ad5d5a73eee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=620681940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.620681940
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3925998135
Short name T280
Test name
Test status
Simulation time 41735378 ps
CPU time 0.69 seconds
Started Jul 21 06:51:59 PM PDT 24
Finished Jul 21 06:52:01 PM PDT 24
Peak memory 206212 kb
Host smart-6b789a58-6fb8-4c85-bed6-ecdf30d7ddc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3925998135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3925998135
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.1972868815
Short name T2807
Test name
Test status
Simulation time 200023372 ps
CPU time 2.48 seconds
Started Jul 21 06:52:02 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 214852 kb
Host smart-9f537eb3-0695-4a34-b371-d5098f7375b7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1972868815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.1972868815
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1445127806
Short name T2860
Test name
Test status
Simulation time 169562062 ps
CPU time 3.86 seconds
Started Jul 21 06:52:01 PM PDT 24
Finished Jul 21 06:52:06 PM PDT 24
Peak memory 206436 kb
Host smart-fde78595-33b8-4a0e-8af5-56e576bae454
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1445127806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1445127806
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2172218944
Short name T265
Test name
Test status
Simulation time 112126158 ps
CPU time 0.99 seconds
Started Jul 21 06:52:06 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 206540 kb
Host smart-881e6ddc-46cb-4429-9e8f-e8bb8320309e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2172218944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2172218944
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3189627163
Short name T2774
Test name
Test status
Simulation time 103614592 ps
CPU time 2.9 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:05 PM PDT 24
Peak memory 214680 kb
Host smart-1fdb6c93-7479-4005-8786-3aea1b98a675
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3189627163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3189627163
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1621560758
Short name T2796
Test name
Test status
Simulation time 524238316 ps
CPU time 2.9 seconds
Started Jul 21 06:52:00 PM PDT 24
Finished Jul 21 06:52:05 PM PDT 24
Peak memory 206500 kb
Host smart-905322a7-f4af-4003-93ae-1fededf119e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1621560758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1621560758
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2613639918
Short name T2793
Test name
Test status
Simulation time 42317567 ps
CPU time 0.72 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:28 PM PDT 24
Peak memory 206380 kb
Host smart-e7d61ca8-0b4f-459d-9656-394bbad6130e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2613639918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2613639918
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2610496608
Short name T2842
Test name
Test status
Simulation time 57545613 ps
CPU time 0.68 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:30 PM PDT 24
Peak memory 206316 kb
Host smart-f0a09ca7-dae1-43a5-af1b-71bc76138de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2610496608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2610496608
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.1087367155
Short name T2772
Test name
Test status
Simulation time 61067546 ps
CPU time 0.7 seconds
Started Jul 21 06:52:26 PM PDT 24
Finished Jul 21 06:52:28 PM PDT 24
Peak memory 206308 kb
Host smart-c6b49996-120b-4398-a503-3e5cfd3a6ca7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1087367155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.1087367155
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3216769025
Short name T2851
Test name
Test status
Simulation time 76182262 ps
CPU time 0.72 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:29 PM PDT 24
Peak memory 206332 kb
Host smart-f09588e2-84bf-49cd-af32-d627b30389a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3216769025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3216769025
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3656969692
Short name T2858
Test name
Test status
Simulation time 75773594 ps
CPU time 0.69 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:29 PM PDT 24
Peak memory 206364 kb
Host smart-4e3bdcda-3933-4a45-aa4e-5dd77cb4a775
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3656969692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3656969692
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2593732290
Short name T2776
Test name
Test status
Simulation time 38096367 ps
CPU time 0.7 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:28 PM PDT 24
Peak memory 206296 kb
Host smart-a4dfda32-749b-42ac-aeb2-fec29033bbcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2593732290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2593732290
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1284621234
Short name T278
Test name
Test status
Simulation time 76984254 ps
CPU time 0.76 seconds
Started Jul 21 06:52:31 PM PDT 24
Finished Jul 21 06:52:33 PM PDT 24
Peak memory 206312 kb
Host smart-7a76ce5b-aa62-45dd-b157-ae641af336b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284621234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1284621234
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.1552359710
Short name T279
Test name
Test status
Simulation time 47450799 ps
CPU time 0.69 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:29 PM PDT 24
Peak memory 206308 kb
Host smart-a319df3b-e29b-4cc3-b47b-06cea72f93c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1552359710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.1552359710
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.1835570903
Short name T197
Test name
Test status
Simulation time 79317417 ps
CPU time 0.75 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:29 PM PDT 24
Peak memory 206292 kb
Host smart-eb00f38b-4d9b-473d-8f7c-eaf0d358b6b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1835570903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.1835570903
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.273961123
Short name T287
Test name
Test status
Simulation time 51484868 ps
CPU time 0.7 seconds
Started Jul 21 06:52:34 PM PDT 24
Finished Jul 21 06:52:36 PM PDT 24
Peak memory 206332 kb
Host smart-08a87492-e9dc-437d-be8c-6d9d29a2e30f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=273961123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.273961123
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.1630541996
Short name T2766
Test name
Test status
Simulation time 219905836 ps
CPU time 2.02 seconds
Started Jul 21 06:52:02 PM PDT 24
Finished Jul 21 06:52:06 PM PDT 24
Peak memory 214832 kb
Host smart-8debe27a-09c3-471b-bb66-e21885a0cabf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630541996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.1630541996
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.317504733
Short name T2806
Test name
Test status
Simulation time 58650617 ps
CPU time 0.85 seconds
Started Jul 21 06:52:02 PM PDT 24
Finished Jul 21 06:52:03 PM PDT 24
Peak memory 206280 kb
Host smart-3c4a7e52-3778-4b46-87ad-9a9e6bd52aee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=317504733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.317504733
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.99497791
Short name T2788
Test name
Test status
Simulation time 31367289 ps
CPU time 0.72 seconds
Started Jul 21 06:52:04 PM PDT 24
Finished Jul 21 06:52:06 PM PDT 24
Peak memory 206340 kb
Host smart-7d0aa7ed-c699-4892-ae41-02735e0a7258
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=99497791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.99497791
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.3958980760
Short name T2819
Test name
Test status
Simulation time 244698429 ps
CPU time 1.75 seconds
Started Jul 21 06:52:03 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 206444 kb
Host smart-e87f4e88-4fd4-48bd-addb-c4eab4946320
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3958980760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.3958980760
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.3300848170
Short name T229
Test name
Test status
Simulation time 285890444 ps
CPU time 3.07 seconds
Started Jul 21 06:52:09 PM PDT 24
Finished Jul 21 06:52:13 PM PDT 24
Peak memory 214884 kb
Host smart-6b8bf820-bc88-4e44-8f09-1ee066a30578
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3300848170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.3300848170
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.1471670663
Short name T2825
Test name
Test status
Simulation time 323718285 ps
CPU time 2.33 seconds
Started Jul 21 06:52:02 PM PDT 24
Finished Jul 21 06:52:05 PM PDT 24
Peak memory 206536 kb
Host smart-278426af-f33f-4a7d-b501-20acbada4616
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1471670663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.1471670663
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.766911178
Short name T228
Test name
Test status
Simulation time 120548514 ps
CPU time 2.38 seconds
Started Jul 21 06:52:02 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 214740 kb
Host smart-558b4e75-c876-48cc-b993-5ac737316521
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766911178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.766911178
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.504809658
Short name T251
Test name
Test status
Simulation time 87427138 ps
CPU time 0.92 seconds
Started Jul 21 06:52:02 PM PDT 24
Finished Jul 21 06:52:04 PM PDT 24
Peak memory 206312 kb
Host smart-e9ee78bd-a032-41d4-b897-a169920d8824
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=504809658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.504809658
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.869467933
Short name T2821
Test name
Test status
Simulation time 45428549 ps
CPU time 0.69 seconds
Started Jul 21 06:52:04 PM PDT 24
Finished Jul 21 06:52:06 PM PDT 24
Peak memory 206284 kb
Host smart-5490d0e6-f1c7-4932-959d-1e0d341f6375
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869467933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.869467933
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.4130366742
Short name T2759
Test name
Test status
Simulation time 116044061 ps
CPU time 1.17 seconds
Started Jul 21 06:52:10 PM PDT 24
Finished Jul 21 06:52:11 PM PDT 24
Peak memory 206440 kb
Host smart-539edf25-bc96-4e13-be72-d5b5c0afa13b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4130366742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.4130366742
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.1115308361
Short name T221
Test name
Test status
Simulation time 58504317 ps
CPU time 1.56 seconds
Started Jul 21 06:52:04 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 206612 kb
Host smart-b40d5c0d-fd1d-4bcd-8fe5-b5297e9147c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1115308361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.1115308361
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1702943003
Short name T2795
Test name
Test status
Simulation time 690892451 ps
CPU time 4.72 seconds
Started Jul 21 06:52:04 PM PDT 24
Finished Jul 21 06:52:10 PM PDT 24
Peak memory 206420 kb
Host smart-03ca9811-2887-4e26-bb93-d0b04b951c34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1702943003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1702943003
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.303137096
Short name T2856
Test name
Test status
Simulation time 60821340 ps
CPU time 1.31 seconds
Started Jul 21 06:52:02 PM PDT 24
Finished Jul 21 06:52:05 PM PDT 24
Peak memory 214744 kb
Host smart-d14b0436-804e-47d4-bd7a-f39cc4fa6d98
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303137096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev
_csr_mem_rw_with_rand_reset.303137096
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.3644244217
Short name T249
Test name
Test status
Simulation time 100133806 ps
CPU time 1.1 seconds
Started Jul 21 06:52:06 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 206492 kb
Host smart-9e9c6772-8eb5-47e4-9ed0-111169189fed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3644244217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.3644244217
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3188593320
Short name T2849
Test name
Test status
Simulation time 58233405 ps
CPU time 0.71 seconds
Started Jul 21 06:52:03 PM PDT 24
Finished Jul 21 06:52:05 PM PDT 24
Peak memory 206308 kb
Host smart-d0700a88-0a14-4675-b954-df843f7d37c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3188593320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3188593320
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2958488364
Short name T2812
Test name
Test status
Simulation time 133218315 ps
CPU time 1.14 seconds
Started Jul 21 06:52:09 PM PDT 24
Finished Jul 21 06:52:10 PM PDT 24
Peak memory 206464 kb
Host smart-10fe8f91-7f74-4330-a3cd-149b26060517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2958488364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2958488364
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4070570926
Short name T2798
Test name
Test status
Simulation time 103494728 ps
CPU time 1.31 seconds
Started Jul 21 06:52:06 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 206436 kb
Host smart-9b722f6d-3c3f-4496-9d10-12c78dba1f09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4070570926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4070570926
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2320590279
Short name T2844
Test name
Test status
Simulation time 102954947 ps
CPU time 2.66 seconds
Started Jul 21 06:52:07 PM PDT 24
Finished Jul 21 06:52:10 PM PDT 24
Peak memory 214776 kb
Host smart-6d7495e1-2130-43bc-9641-337b353a9d13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320590279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2320590279
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.3094336515
Short name T2824
Test name
Test status
Simulation time 59885006 ps
CPU time 0.85 seconds
Started Jul 21 06:52:04 PM PDT 24
Finished Jul 21 06:52:06 PM PDT 24
Peak memory 206388 kb
Host smart-83b3ae88-4e9e-404d-8c62-9b1c77cfebf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3094336515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.3094336515
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.1357686448
Short name T2833
Test name
Test status
Simulation time 32020692 ps
CPU time 0.71 seconds
Started Jul 21 06:52:05 PM PDT 24
Finished Jul 21 06:52:07 PM PDT 24
Peak memory 206212 kb
Host smart-6c68910b-a138-4422-8052-ab5f86fb514d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1357686448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.1357686448
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2720878041
Short name T2808
Test name
Test status
Simulation time 216603371 ps
CPU time 1.97 seconds
Started Jul 21 06:52:03 PM PDT 24
Finished Jul 21 06:52:06 PM PDT 24
Peak memory 206592 kb
Host smart-f95e3eb6-2498-490d-bb35-536213f3a9c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2720878041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2720878041
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3328887425
Short name T231
Test name
Test status
Simulation time 165514789 ps
CPU time 1.89 seconds
Started Jul 21 06:52:10 PM PDT 24
Finished Jul 21 06:52:13 PM PDT 24
Peak memory 214748 kb
Host smart-91dc1e28-24d8-4b6e-aebd-4f69529d1508
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328887425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.3328887425
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.4144391373
Short name T2848
Test name
Test status
Simulation time 53956739 ps
CPU time 0.9 seconds
Started Jul 21 06:52:10 PM PDT 24
Finished Jul 21 06:52:12 PM PDT 24
Peak memory 206508 kb
Host smart-220540ab-ab35-4311-a63f-06aa7d4bfddd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4144391373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.4144391373
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.936963108
Short name T198
Test name
Test status
Simulation time 56433245 ps
CPU time 0.68 seconds
Started Jul 21 06:52:07 PM PDT 24
Finished Jul 21 06:52:08 PM PDT 24
Peak memory 206320 kb
Host smart-6093eb2e-acbf-403d-bbac-5115549a04dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=936963108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.936963108
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3388599098
Short name T2765
Test name
Test status
Simulation time 169397490 ps
CPU time 1.67 seconds
Started Jul 21 06:52:08 PM PDT 24
Finished Jul 21 06:52:10 PM PDT 24
Peak memory 206560 kb
Host smart-ba0f6e67-9411-4cf5-ba8e-b777051d2469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3388599098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3388599098
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2550766205
Short name T2835
Test name
Test status
Simulation time 128338860 ps
CPU time 1.74 seconds
Started Jul 21 06:52:13 PM PDT 24
Finished Jul 21 06:52:15 PM PDT 24
Peak memory 206500 kb
Host smart-ba723b6f-4fa3-4dbf-9b8d-449d71c49210
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2550766205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2550766205
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.172090398
Short name T269
Test name
Test status
Simulation time 433004083 ps
CPU time 2.75 seconds
Started Jul 21 06:52:07 PM PDT 24
Finished Jul 21 06:52:11 PM PDT 24
Peak memory 206504 kb
Host smart-3233597e-1dbe-467c-8acd-64487126d963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=172090398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.172090398
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.3687622328
Short name T980
Test name
Test status
Simulation time 70946456 ps
CPU time 0.69 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:43 PM PDT 24
Peak memory 206736 kb
Host smart-a283d09a-54d7-44a8-8b63-094ac7189b0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3687622328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.3687622328
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.42048499
Short name T2369
Test name
Test status
Simulation time 4355008750 ps
CPU time 5.22 seconds
Started Jul 21 06:52:29 PM PDT 24
Finished Jul 21 06:52:35 PM PDT 24
Peak memory 206836 kb
Host smart-0b0c5558-b3d7-4aab-b880-5144638ae34b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=42048499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.42048499
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.408402795
Short name T2097
Test name
Test status
Simulation time 13360463632 ps
CPU time 11.91 seconds
Started Jul 21 06:52:26 PM PDT 24
Finished Jul 21 06:52:38 PM PDT 24
Peak memory 206868 kb
Host smart-9e5e6eda-2fa6-4096-b90c-1e92b9017877
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=408402795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.408402795
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.4274120993
Short name T1710
Test name
Test status
Simulation time 23306581446 ps
CPU time 23.03 seconds
Started Jul 21 06:52:28 PM PDT 24
Finished Jul 21 06:52:52 PM PDT 24
Peak memory 206780 kb
Host smart-d8497f81-71b5-4f0b-a23e-31a5287ec877
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4274120993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.4274120993
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.1291200766
Short name T239
Test name
Test status
Simulation time 144095157 ps
CPU time 0.76 seconds
Started Jul 21 06:52:27 PM PDT 24
Finished Jul 21 06:52:29 PM PDT 24
Peak memory 206656 kb
Host smart-8fa07873-1b73-452d-a09c-b4b0b32f2d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12912
00766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.1291200766
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.741579900
Short name T1619
Test name
Test status
Simulation time 143005561 ps
CPU time 0.8 seconds
Started Jul 21 06:52:33 PM PDT 24
Finished Jul 21 06:52:34 PM PDT 24
Peak memory 206680 kb
Host smart-3f188c33-fc9b-4bda-8d6f-b91ef65a77db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74157
9900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.741579900
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.4165965151
Short name T1925
Test name
Test status
Simulation time 603454175 ps
CPU time 1.71 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:52:35 PM PDT 24
Peak memory 206804 kb
Host smart-038b050d-11d0-408f-9004-de0db50c2ec6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41659
65151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.4165965151
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.1651058687
Short name T2383
Test name
Test status
Simulation time 1494824783 ps
CPU time 3.3 seconds
Started Jul 21 06:52:33 PM PDT 24
Finished Jul 21 06:52:37 PM PDT 24
Peak memory 206764 kb
Host smart-80ac8f17-4fcb-4ccc-bd01-37eada3a670e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16510
58687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.1651058687
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3928665443
Short name T2279
Test name
Test status
Simulation time 12557887999 ps
CPU time 21.41 seconds
Started Jul 21 06:52:31 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206844 kb
Host smart-2c5ea046-5c48-42d7-bfef-87a10b35c5a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39286
65443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3928665443
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.2048692833
Short name T717
Test name
Test status
Simulation time 398438001 ps
CPU time 1.19 seconds
Started Jul 21 06:52:30 PM PDT 24
Finished Jul 21 06:52:32 PM PDT 24
Peak memory 206676 kb
Host smart-f26b96f2-affc-4d3e-93b6-0a0d2cfc95cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
92833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.2048692833
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.836364985
Short name T608
Test name
Test status
Simulation time 157431926 ps
CPU time 0.8 seconds
Started Jul 21 06:52:33 PM PDT 24
Finished Jul 21 06:52:34 PM PDT 24
Peak memory 206664 kb
Host smart-906186c9-a736-4eec-a394-452c049aa777
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83636
4985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.836364985
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.375386955
Short name T1056
Test name
Test status
Simulation time 5122819497 ps
CPU time 126.25 seconds
Started Jul 21 06:52:34 PM PDT 24
Finished Jul 21 06:54:41 PM PDT 24
Peak memory 206904 kb
Host smart-31b881f6-b0d3-4883-91b9-303e9f3783be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37538
6955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.375386955
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.1828053073
Short name T1797
Test name
Test status
Simulation time 94952030 ps
CPU time 0.71 seconds
Started Jul 21 06:52:30 PM PDT 24
Finished Jul 21 06:52:31 PM PDT 24
Peak memory 206664 kb
Host smart-7adfa6da-3a4b-42d3-a21d-3d69554a6a82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18280
53073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.1828053073
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.2527901802
Short name T613
Test name
Test status
Simulation time 904986244 ps
CPU time 2.26 seconds
Started Jul 21 06:52:31 PM PDT 24
Finished Jul 21 06:52:34 PM PDT 24
Peak memory 206792 kb
Host smart-44f8bd3c-9054-4285-b303-a217160765d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25279
01802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.2527901802
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.1987445875
Short name T903
Test name
Test status
Simulation time 209743265 ps
CPU time 1.57 seconds
Started Jul 21 06:52:30 PM PDT 24
Finished Jul 21 06:52:32 PM PDT 24
Peak memory 206804 kb
Host smart-3a5210a9-1f15-4316-b876-cefb13d3f59e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19874
45875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.1987445875
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.3503909725
Short name T2328
Test name
Test status
Simulation time 86193057777 ps
CPU time 105.25 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:54:18 PM PDT 24
Peak memory 206996 kb
Host smart-05aeb249-a09a-48a2-9122-166e145351bc
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3503909725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.3503909725
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2596333635
Short name T416
Test name
Test status
Simulation time 91296507840 ps
CPU time 116.9 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:54:30 PM PDT 24
Peak memory 206972 kb
Host smart-4cb34924-5313-4056-9dec-08576fbee974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596333635 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2596333635
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.3373674148
Short name T534
Test name
Test status
Simulation time 102110739915 ps
CPU time 126.49 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:54:39 PM PDT 24
Peak memory 206856 kb
Host smart-b22b79ea-0c47-4e46-a3bb-610cc6e8bf3c
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3373674148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.3373674148
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.1139968755
Short name T2684
Test name
Test status
Simulation time 120175574013 ps
CPU time 162.47 seconds
Started Jul 21 06:52:31 PM PDT 24
Finished Jul 21 06:55:13 PM PDT 24
Peak memory 206880 kb
Host smart-4403d2c8-eb61-49b6-bfbf-7b321965ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139968755 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.1139968755
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.3194487565
Short name T334
Test name
Test status
Simulation time 109136667493 ps
CPU time 159.01 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:55:12 PM PDT 24
Peak memory 206916 kb
Host smart-a9d709d1-9c9a-4c67-af4b-a4a8f0eb3edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31944
87565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.3194487565
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1109799141
Short name T866
Test name
Test status
Simulation time 171763764 ps
CPU time 0.81 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:52:33 PM PDT 24
Peak memory 206676 kb
Host smart-89b04c1a-0c1e-4e7d-b041-fc499409ddb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11097
99141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1109799141
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.1315675949
Short name T2104
Test name
Test status
Simulation time 143689887 ps
CPU time 0.76 seconds
Started Jul 21 06:52:31 PM PDT 24
Finished Jul 21 06:52:32 PM PDT 24
Peak memory 206684 kb
Host smart-00d5b227-f46c-4515-96ea-0c9bd08eb0fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13156
75949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.1315675949
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.1647014245
Short name T485
Test name
Test status
Simulation time 216705326 ps
CPU time 0.9 seconds
Started Jul 21 06:52:32 PM PDT 24
Finished Jul 21 06:52:33 PM PDT 24
Peak memory 206656 kb
Host smart-c4056b38-3d1c-44e0-9074-a2d12cfcc92d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16470
14245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.1647014245
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_invalid_sync.2410947410
Short name T83
Test name
Test status
Simulation time 9744888468 ps
CPU time 267.47 seconds
Started Jul 21 06:52:33 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206892 kb
Host smart-face2cbc-ae4d-451d-bc7a-0c0123673c57
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2410947410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_sync.2410947410
Directory /workspace/0.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.843222804
Short name T2118
Test name
Test status
Simulation time 11697634566 ps
CPU time 39.81 seconds
Started Jul 21 06:52:30 PM PDT 24
Finished Jul 21 06:53:10 PM PDT 24
Peak memory 206900 kb
Host smart-d54c2ecf-746d-49c7-864e-b3d35f7f47e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84322
2804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.843222804
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.2533505832
Short name T1699
Test name
Test status
Simulation time 156937318 ps
CPU time 0.79 seconds
Started Jul 21 06:52:29 PM PDT 24
Finished Jul 21 06:52:30 PM PDT 24
Peak memory 206680 kb
Host smart-35426b13-1170-4a45-b5ba-2e9baa035cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25335
05832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.2533505832
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.205993063
Short name T63
Test name
Test status
Simulation time 489614546 ps
CPU time 1.5 seconds
Started Jul 21 06:52:34 PM PDT 24
Finished Jul 21 06:52:36 PM PDT 24
Peak memory 206680 kb
Host smart-ee6f3888-de9d-4c92-8cba-2e74b8811ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20599
3063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.205993063
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.1290921359
Short name T1267
Test name
Test status
Simulation time 23329107043 ps
CPU time 20.98 seconds
Started Jul 21 06:52:30 PM PDT 24
Finished Jul 21 06:52:52 PM PDT 24
Peak memory 206776 kb
Host smart-910c8679-bf05-4807-8450-ce3807d207f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12909
21359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.1290921359
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.2345377787
Short name T2362
Test name
Test status
Simulation time 3336725477 ps
CPU time 3.89 seconds
Started Jul 21 06:52:38 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206724 kb
Host smart-ddc1604a-2917-4d8e-a7aa-53b348eba42a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23453
77787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.2345377787
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.3369567918
Short name T738
Test name
Test status
Simulation time 10502793968 ps
CPU time 281.04 seconds
Started Jul 21 06:52:35 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206900 kb
Host smart-8934f590-9402-4615-90c6-e1f656ed7511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33695
67918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.3369567918
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.1508156349
Short name T1623
Test name
Test status
Simulation time 5304452620 ps
CPU time 143.08 seconds
Started Jul 21 06:52:36 PM PDT 24
Finished Jul 21 06:55:00 PM PDT 24
Peak memory 206908 kb
Host smart-6490adc9-8e3b-42cb-8476-3ea77d39ee75
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1508156349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.1508156349
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.419692533
Short name T1988
Test name
Test status
Simulation time 245764117 ps
CPU time 0.92 seconds
Started Jul 21 06:52:35 PM PDT 24
Finished Jul 21 06:52:37 PM PDT 24
Peak memory 206664 kb
Host smart-6b1589e1-7a7b-4dd3-a341-d9e9ebce6106
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=419692533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.419692533
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.2576719346
Short name T1792
Test name
Test status
Simulation time 191017766 ps
CPU time 0.85 seconds
Started Jul 21 06:52:35 PM PDT 24
Finished Jul 21 06:52:37 PM PDT 24
Peak memory 206680 kb
Host smart-0b10fbb0-78c2-438e-a014-a9e46e114f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25767
19346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.2576719346
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.2230907631
Short name T2377
Test name
Test status
Simulation time 6641196926 ps
CPU time 182.53 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:55:43 PM PDT 24
Peak memory 205740 kb
Host smart-4fb3f1c0-679d-4086-a107-a1bd561d4566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22309
07631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.2230907631
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.2791318761
Short name T593
Test name
Test status
Simulation time 5629199261 ps
CPU time 157.01 seconds
Started Jul 21 06:52:35 PM PDT 24
Finished Jul 21 06:55:13 PM PDT 24
Peak memory 206852 kb
Host smart-c1c33e51-4e92-4d57-94b7-6018657e72d4
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2791318761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.2791318761
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.1124849070
Short name T470
Test name
Test status
Simulation time 155116781 ps
CPU time 0.79 seconds
Started Jul 21 06:52:37 PM PDT 24
Finished Jul 21 06:52:39 PM PDT 24
Peak memory 206684 kb
Host smart-b34507eb-04dc-44ef-95b3-4d44b2537624
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1124849070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.1124849070
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.2639659885
Short name T1875
Test name
Test status
Simulation time 207602697 ps
CPU time 0.88 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206684 kb
Host smart-02548076-a21f-42c3-8f9a-db84aea3ced9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26396
59885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.2639659885
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2981720047
Short name T43
Test name
Test status
Simulation time 474433582 ps
CPU time 1.24 seconds
Started Jul 21 06:52:38 PM PDT 24
Finished Jul 21 06:52:40 PM PDT 24
Peak memory 206696 kb
Host smart-4ec142cd-469c-4d3f-b2eb-e9cffa629ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29817
20047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.2981720047
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.2887008088
Short name T2524
Test name
Test status
Simulation time 155493483 ps
CPU time 0.77 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:41 PM PDT 24
Peak memory 206648 kb
Host smart-c287c899-6e30-4104-9224-f557c9a95c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28870
08088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.2887008088
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.2805388441
Short name T1020
Test name
Test status
Simulation time 186778671 ps
CPU time 0.84 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206688 kb
Host smart-00aad339-678e-48c0-899e-7df53b165744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28053
88441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.2805388441
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.2884786988
Short name T1928
Test name
Test status
Simulation time 186822951 ps
CPU time 0.9 seconds
Started Jul 21 06:52:36 PM PDT 24
Finished Jul 21 06:52:37 PM PDT 24
Peak memory 206652 kb
Host smart-2a7aca58-a400-4ee0-833e-b0a2fbffcd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28847
86988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.2884786988
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.971483508
Short name T136
Test name
Test status
Simulation time 210215935 ps
CPU time 0.83 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:40 PM PDT 24
Peak memory 206652 kb
Host smart-6e15a466-b49f-4dae-a7b6-480ae43bb5f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97148
3508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.971483508
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.162763982
Short name T331
Test name
Test status
Simulation time 196736644 ps
CPU time 0.89 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:41 PM PDT 24
Peak memory 205776 kb
Host smart-f261a02f-43f2-4eca-9ee8-a3d6903550f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16276
3982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.162763982
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.2736863552
Short name T2648
Test name
Test status
Simulation time 190304824 ps
CPU time 0.87 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206652 kb
Host smart-69820d37-5e6d-4aaa-a328-64356dc922bc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2736863552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.2736863552
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.2959530092
Short name T1811
Test name
Test status
Simulation time 218220335 ps
CPU time 0.92 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206668 kb
Host smart-f96036c2-46e4-40f8-8c66-48d15f09ff14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29595
30092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.2959530092
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.714267685
Short name T2087
Test name
Test status
Simulation time 203090359 ps
CPU time 0.89 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:41 PM PDT 24
Peak memory 206652 kb
Host smart-94f88437-fc55-4881-b46f-9697f1c13393
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=714267685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.714267685
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.3005107176
Short name T193
Test name
Test status
Simulation time 234419854 ps
CPU time 0.91 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:41 PM PDT 24
Peak memory 206644 kb
Host smart-7c452b4b-a587-4810-bfab-ca3d736b35fc
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3005107176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.3005107176
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.1542839844
Short name T1468
Test name
Test status
Simulation time 40206566 ps
CPU time 0.68 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206632 kb
Host smart-e43d87e5-a6fd-4347-9495-aa4e6147a6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15428
39844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.1542839844
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.2718780488
Short name T234
Test name
Test status
Simulation time 23080754858 ps
CPU time 51.66 seconds
Started Jul 21 06:52:38 PM PDT 24
Finished Jul 21 06:53:30 PM PDT 24
Peak memory 206944 kb
Host smart-b4d94031-3a68-4f5d-a119-652927c8cd56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27187
80488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.2718780488
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.2493804003
Short name T656
Test name
Test status
Simulation time 224915771 ps
CPU time 0.84 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206660 kb
Host smart-ea688701-bdd1-4726-b3b4-cd3012a88cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24938
04003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.2493804003
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.2098094433
Short name T1615
Test name
Test status
Simulation time 234782620 ps
CPU time 0.86 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:43 PM PDT 24
Peak memory 206664 kb
Host smart-4bdfa4cb-c223-4d75-80f2-86de171c467e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20980
94433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.2098094433
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.4017461808
Short name T154
Test name
Test status
Simulation time 7833872746 ps
CPU time 107.52 seconds
Started Jul 21 06:52:36 PM PDT 24
Finished Jul 21 06:54:25 PM PDT 24
Peak memory 206952 kb
Host smart-4f79da7e-6e92-4ca0-bd0b-dc7390433916
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4017461808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.4017461808
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.1478675905
Short name T2007
Test name
Test status
Simulation time 16124069807 ps
CPU time 117.42 seconds
Started Jul 21 06:52:38 PM PDT 24
Finished Jul 21 06:54:36 PM PDT 24
Peak memory 206948 kb
Host smart-4f6d86d4-e25a-4839-a3c7-6e3a8f7db236
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1478675905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.1478675905
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.3006675045
Short name T429
Test name
Test status
Simulation time 233715343 ps
CPU time 0.89 seconds
Started Jul 21 06:52:37 PM PDT 24
Finished Jul 21 06:52:39 PM PDT 24
Peak memory 206680 kb
Host smart-75ff13ee-89e4-4038-bc6c-35d5f7fef03b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30066
75045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.3006675045
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1993009066
Short name T2093
Test name
Test status
Simulation time 185004606 ps
CPU time 0.92 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206664 kb
Host smart-dc631e4e-d7f1-4ccb-ae6a-69b8d2fafbc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19930
09066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1993009066
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.568613869
Short name T2583
Test name
Test status
Simulation time 160083451 ps
CPU time 0.77 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:43 PM PDT 24
Peak memory 206660 kb
Host smart-32fe8162-4c31-43e6-aac3-550a6424dd4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56861
3869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.568613869
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2189874233
Short name T203
Test name
Test status
Simulation time 696250841 ps
CPU time 1.54 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:43 PM PDT 24
Peak memory 224544 kb
Host smart-01907b6b-70a2-4455-bf5b-eaa351044a63
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2189874233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2189874233
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.3318566451
Short name T52
Test name
Test status
Simulation time 389218595 ps
CPU time 1.19 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206664 kb
Host smart-35e4b613-9ec3-4ad4-a300-8ff2812cb0fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33185
66451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.3318566451
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.544806341
Short name T930
Test name
Test status
Simulation time 379970073 ps
CPU time 1 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206612 kb
Host smart-9cb52d71-205c-479d-a94e-088aa0d4a8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54480
6341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.544806341
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.3285219409
Short name T2645
Test name
Test status
Simulation time 154516322 ps
CPU time 0.78 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206664 kb
Host smart-36f39c40-3d07-4266-a5ef-d2619970fed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32852
19409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.3285219409
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.16919527
Short name T558
Test name
Test status
Simulation time 168242728 ps
CPU time 0.77 seconds
Started Jul 21 06:52:38 PM PDT 24
Finished Jul 21 06:52:39 PM PDT 24
Peak memory 206640 kb
Host smart-1bdcfb64-38d3-4630-8702-362c0343b842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16919
527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.16919527
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.1811174183
Short name T1985
Test name
Test status
Simulation time 210575417 ps
CPU time 0.91 seconds
Started Jul 21 06:52:54 PM PDT 24
Finished Jul 21 06:52:56 PM PDT 24
Peak memory 206624 kb
Host smart-6838a75c-5111-4c3a-9ef3-b1fe582fdf39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18111
74183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.1811174183
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1854860213
Short name T4
Test name
Test status
Simulation time 5778216150 ps
CPU time 39.35 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:53:22 PM PDT 24
Peak memory 206876 kb
Host smart-6ae1017a-1e80-4127-82ac-e52302b5ddc6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1854860213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1854860213
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.650197627
Short name T1831
Test name
Test status
Simulation time 187692562 ps
CPU time 0.89 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:43 PM PDT 24
Peak memory 206672 kb
Host smart-f61508ec-8633-4d6f-840a-9b4281481278
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65019
7627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.650197627
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2780668110
Short name T1720
Test name
Test status
Simulation time 172737422 ps
CPU time 0.81 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:43 PM PDT 24
Peak memory 206664 kb
Host smart-10be923d-228b-43e6-b111-d214c44e6a43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27806
68110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2780668110
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.3736150208
Short name T1893
Test name
Test status
Simulation time 677003896 ps
CPU time 1.56 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:52:41 PM PDT 24
Peak memory 206776 kb
Host smart-ef74802a-c83d-4667-bd68-779599b2ff88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37361
50208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.3736150208
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.3533360664
Short name T830
Test name
Test status
Simulation time 6233141572 ps
CPU time 178.78 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:55:38 PM PDT 24
Peak memory 206900 kb
Host smart-dcc83713-ae0c-46bd-8cc1-d8f5ff5d60ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35333
60664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.3533360664
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.3421095112
Short name T162
Test name
Test status
Simulation time 12523398651 ps
CPU time 331.79 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 207012 kb
Host smart-e465ae9f-7409-4df7-bab9-f06d8294b41a
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3421095112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.3421095112
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.3395992088
Short name T1723
Test name
Test status
Simulation time 13436061962 ps
CPU time 13.74 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206768 kb
Host smart-86482e38-6967-4512-b570-9d4ebd39fbc2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3395992088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.3395992088
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.782499768
Short name T1050
Test name
Test status
Simulation time 23355510121 ps
CPU time 23.63 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:53:05 PM PDT 24
Peak memory 206804 kb
Host smart-8c384077-0845-4da9-af24-0d8697857bdf
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=782499768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.782499768
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.1804026641
Short name T1443
Test name
Test status
Simulation time 159606243 ps
CPU time 0.83 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206672 kb
Host smart-2197e134-2485-4fba-bcd7-a17d932676fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18040
26641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.1804026641
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.468022216
Short name T45
Test name
Test status
Simulation time 169946158 ps
CPU time 0.81 seconds
Started Jul 21 06:52:43 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206700 kb
Host smart-13961667-7746-429c-b835-2aee0191dbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46802
2216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.468022216
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.2044206237
Short name T1770
Test name
Test status
Simulation time 212207181 ps
CPU time 0.84 seconds
Started Jul 21 06:52:42 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206672 kb
Host smart-17cdef67-12fa-4635-a1c7-cd2f2a910c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20442
06237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.2044206237
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.1489975054
Short name T95
Test name
Test status
Simulation time 470457878 ps
CPU time 1.49 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:44 PM PDT 24
Peak memory 206704 kb
Host smart-8e42507b-073f-452b-920c-67c47e4700ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14899
75054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.1489975054
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.218911713
Short name T1048
Test name
Test status
Simulation time 412226344 ps
CPU time 1.1 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:52:47 PM PDT 24
Peak memory 206652 kb
Host smart-8fe62746-04de-40b6-893a-203f8d2f9ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21891
1713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.218911713
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.101646932
Short name T2131
Test name
Test status
Simulation time 17337054203 ps
CPU time 32.99 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:53:18 PM PDT 24
Peak memory 206880 kb
Host smart-73615c4f-4542-4af2-aad9-23891f23238a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
6932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.101646932
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.3556399316
Short name T2336
Test name
Test status
Simulation time 433882424 ps
CPU time 1.28 seconds
Started Jul 21 06:52:44 PM PDT 24
Finished Jul 21 06:52:45 PM PDT 24
Peak memory 206648 kb
Host smart-ab6891a8-1e1d-4cdd-8c2b-a1528c48af9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35563
99316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.3556399316
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.372669583
Short name T1801
Test name
Test status
Simulation time 143392938 ps
CPU time 0.76 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206652 kb
Host smart-39e96731-8e8a-4613-811e-55aae337c31d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37266
9583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.372669583
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.775985837
Short name T2420
Test name
Test status
Simulation time 39369652 ps
CPU time 0.66 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:42 PM PDT 24
Peak memory 206656 kb
Host smart-d825e323-fc0f-4bf6-b90c-2b29876a68d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77598
5837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.775985837
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1204630553
Short name T1318
Test name
Test status
Simulation time 889247783 ps
CPU time 1.89 seconds
Started Jul 21 06:52:40 PM PDT 24
Finished Jul 21 06:52:43 PM PDT 24
Peak memory 206780 kb
Host smart-46f498d3-74f7-4310-b1b1-78d6e498c2d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12046
30553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1204630553
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.2963346852
Short name T2230
Test name
Test status
Simulation time 355411270 ps
CPU time 2.2 seconds
Started Jul 21 06:52:41 PM PDT 24
Finished Jul 21 06:52:45 PM PDT 24
Peak memory 206720 kb
Host smart-84634240-028f-4459-a726-fb9da522f5be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29633
46852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.2963346852
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3899781348
Short name T526
Test name
Test status
Simulation time 93188719266 ps
CPU time 130.4 seconds
Started Jul 21 06:52:39 PM PDT 24
Finished Jul 21 06:54:51 PM PDT 24
Peak memory 206912 kb
Host smart-8084694f-95ce-4289-9354-630630bbb1c9
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3899781348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3899781348
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.249067539
Short name T695
Test name
Test status
Simulation time 91346318133 ps
CPU time 140.23 seconds
Started Jul 21 06:52:47 PM PDT 24
Finished Jul 21 06:55:08 PM PDT 24
Peak memory 206884 kb
Host smart-5e33f9b2-201f-4578-8957-07d207a7ba99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249067539 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.249067539
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2866222453
Short name T1638
Test name
Test status
Simulation time 92108367690 ps
CPU time 145.67 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:55:12 PM PDT 24
Peak memory 206924 kb
Host smart-8401a157-83e5-4d59-8017-5eab566162be
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2866222453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2866222453
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.447732472
Short name T1362
Test name
Test status
Simulation time 86026216763 ps
CPU time 120.2 seconds
Started Jul 21 06:52:44 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206892 kb
Host smart-e30fd071-6712-4c96-bb72-85910922fe1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447732472 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.447732472
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.1672929201
Short name T1729
Test name
Test status
Simulation time 103107532790 ps
CPU time 145.69 seconds
Started Jul 21 06:52:44 PM PDT 24
Finished Jul 21 06:55:11 PM PDT 24
Peak memory 206868 kb
Host smart-a80f1f26-40af-414f-8043-a9c70bcfd1ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16729
29201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.1672929201
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.1346337826
Short name T2146
Test name
Test status
Simulation time 176594885 ps
CPU time 0.76 seconds
Started Jul 21 06:52:46 PM PDT 24
Finished Jul 21 06:52:48 PM PDT 24
Peak memory 206656 kb
Host smart-9f7738c9-c082-41ac-b6ed-29fbe8e5e941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13463
37826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.1346337826
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.2246760457
Short name T823
Test name
Test status
Simulation time 186593114 ps
CPU time 0.8 seconds
Started Jul 21 06:52:51 PM PDT 24
Finished Jul 21 06:52:52 PM PDT 24
Peak memory 206664 kb
Host smart-5e3108c9-d620-402c-9b3d-af8c65f8566a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22467
60457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.2246760457
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.118908877
Short name T2090
Test name
Test status
Simulation time 309162167 ps
CPU time 0.99 seconds
Started Jul 21 06:52:46 PM PDT 24
Finished Jul 21 06:52:48 PM PDT 24
Peak memory 206676 kb
Host smart-4805fa0a-6394-4ed7-951e-8e7a2ce7fa2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11890
8877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.118908877
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.2664061898
Short name T699
Test name
Test status
Simulation time 6390955978 ps
CPU time 52.41 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:53:49 PM PDT 24
Peak memory 206936 kb
Host smart-371b42d3-30a3-4776-9edd-ff9e1c08312e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26640
61898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.2664061898
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.899656236
Short name T799
Test name
Test status
Simulation time 224456431 ps
CPU time 0.93 seconds
Started Jul 21 06:52:46 PM PDT 24
Finished Jul 21 06:52:48 PM PDT 24
Peak memory 206680 kb
Host smart-8aba4930-9ca8-4b15-8f92-49d21897b823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89965
6236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.899656236
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.3816579299
Short name T2083
Test name
Test status
Simulation time 23344369788 ps
CPU time 23.56 seconds
Started Jul 21 06:52:49 PM PDT 24
Finished Jul 21 06:53:13 PM PDT 24
Peak memory 206864 kb
Host smart-78385a33-9a59-4562-996c-99300edfdac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38165
79299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.3816579299
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.2160380066
Short name T2593
Test name
Test status
Simulation time 3315511738 ps
CPU time 3.63 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:52:49 PM PDT 24
Peak memory 206728 kb
Host smart-2c036912-169c-40df-bcdc-dd47151f309a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21603
80066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.2160380066
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.679155521
Short name T571
Test name
Test status
Simulation time 9812672638 ps
CPU time 272.49 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:57:19 PM PDT 24
Peak memory 206960 kb
Host smart-bbf08e00-4f50-40f8-bf09-ec687579c6cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67915
5521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.679155521
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2140429448
Short name T401
Test name
Test status
Simulation time 3852368610 ps
CPU time 98.12 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:54:25 PM PDT 24
Peak memory 206896 kb
Host smart-1096dc74-adc1-434b-ac50-848b6c609c1d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2140429448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2140429448
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.598325627
Short name T749
Test name
Test status
Simulation time 251367684 ps
CPU time 0.98 seconds
Started Jul 21 06:52:49 PM PDT 24
Finished Jul 21 06:52:50 PM PDT 24
Peak memory 206608 kb
Host smart-d3c7ff4d-2587-4d38-8ce3-9c8e00693683
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=598325627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.598325627
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.4252743439
Short name T1726
Test name
Test status
Simulation time 194262304 ps
CPU time 0.9 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:52:47 PM PDT 24
Peak memory 206680 kb
Host smart-73e376fb-576c-4162-8885-7f5c2c3775d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42527
43439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.4252743439
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.1848523082
Short name T2112
Test name
Test status
Simulation time 4556521491 ps
CPU time 120.54 seconds
Started Jul 21 06:52:44 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206876 kb
Host smart-0a286955-0445-4691-85dd-46d5de2b03a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18485
23082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.1848523082
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.1264383686
Short name T961
Test name
Test status
Simulation time 4650879971 ps
CPU time 127.32 seconds
Started Jul 21 06:52:47 PM PDT 24
Finished Jul 21 06:54:55 PM PDT 24
Peak memory 206876 kb
Host smart-4c1a797a-dcdc-408e-8b63-2c8996b329db
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1264383686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.1264383686
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.1300092274
Short name T790
Test name
Test status
Simulation time 155221183 ps
CPU time 0.8 seconds
Started Jul 21 06:52:47 PM PDT 24
Finished Jul 21 06:52:49 PM PDT 24
Peak memory 206664 kb
Host smart-4f250272-a041-4fa9-a0f9-23335638f802
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1300092274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.1300092274
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.1551928717
Short name T308
Test name
Test status
Simulation time 161709822 ps
CPU time 0.84 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206660 kb
Host smart-3e054b94-5f52-4113-8743-eff2a90d2029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15519
28717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.1551928717
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.356005481
Short name T1918
Test name
Test status
Simulation time 157354466 ps
CPU time 0.78 seconds
Started Jul 21 06:52:45 PM PDT 24
Finished Jul 21 06:52:47 PM PDT 24
Peak memory 206668 kb
Host smart-31cd74a1-39d8-4d61-bb2f-ec2c936022cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35600
5481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.356005481
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.3618307177
Short name T1135
Test name
Test status
Simulation time 177990923 ps
CPU time 0.79 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206668 kb
Host smart-e50b4bb9-c1b2-43ed-b842-2941b180d016
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36183
07177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.3618307177
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.362560465
Short name T2295
Test name
Test status
Simulation time 141782334 ps
CPU time 0.78 seconds
Started Jul 21 06:52:49 PM PDT 24
Finished Jul 21 06:52:50 PM PDT 24
Peak memory 206612 kb
Host smart-35011793-4a57-43be-b116-d7dce7e41a05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36256
0465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.362560465
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.3824716219
Short name T622
Test name
Test status
Simulation time 209373390 ps
CPU time 0.81 seconds
Started Jul 21 06:52:49 PM PDT 24
Finished Jul 21 06:52:51 PM PDT 24
Peak memory 206784 kb
Host smart-23ac22d2-9f2f-4660-abe6-379fac04457c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38247
16219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.3824716219
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.1475196860
Short name T2327
Test name
Test status
Simulation time 207320864 ps
CPU time 0.91 seconds
Started Jul 21 06:52:58 PM PDT 24
Finished Jul 21 06:53:00 PM PDT 24
Peak memory 206668 kb
Host smart-0edb7f3d-eac6-455e-856d-a6aa63ce123d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1475196860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.1475196860
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.1043751804
Short name T139
Test name
Test status
Simulation time 214474919 ps
CPU time 0.92 seconds
Started Jul 21 06:52:51 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206780 kb
Host smart-e7d29ddb-5ccb-4a27-b30d-a097d10da62e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
51804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.1043751804
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.3522302065
Short name T780
Test name
Test status
Simulation time 140519446 ps
CPU time 0.73 seconds
Started Jul 21 06:52:52 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206644 kb
Host smart-19803ba2-030e-4d3c-8098-76c349958a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35223
02065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.3522302065
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.2093736422
Short name T2690
Test name
Test status
Simulation time 48061639 ps
CPU time 0.67 seconds
Started Jul 21 06:53:01 PM PDT 24
Finished Jul 21 06:53:03 PM PDT 24
Peak memory 206404 kb
Host smart-dfd31db6-472f-430b-85ab-e2d47bab9db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
36422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.2093736422
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.1158142199
Short name T1848
Test name
Test status
Simulation time 21770366035 ps
CPU time 48.65 seconds
Started Jul 21 06:52:51 PM PDT 24
Finished Jul 21 06:53:41 PM PDT 24
Peak memory 206892 kb
Host smart-21aad6ea-fb6b-4b13-a9da-2ab7179b9ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11581
42199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.1158142199
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3756355708
Short name T1591
Test name
Test status
Simulation time 176220551 ps
CPU time 0.87 seconds
Started Jul 21 06:52:52 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206664 kb
Host smart-0dd946a0-f2a0-4911-9eea-309d1d7e994f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37563
55708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3756355708
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.1731670499
Short name T2168
Test name
Test status
Simulation time 190413905 ps
CPU time 0.85 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206664 kb
Host smart-7b81d72f-a172-478d-bbab-f3778d6e4736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17316
70499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.1731670499
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.3413429184
Short name T159
Test name
Test status
Simulation time 17300631162 ps
CPU time 115.16 seconds
Started Jul 21 06:52:49 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206924 kb
Host smart-99f204f4-c59c-4b30-acfb-c384b9a54100
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3413429184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.3413429184
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.1210089451
Short name T150
Test name
Test status
Simulation time 9231903189 ps
CPU time 62.31 seconds
Started Jul 21 06:52:58 PM PDT 24
Finished Jul 21 06:54:02 PM PDT 24
Peak memory 206944 kb
Host smart-5886e36f-c37a-4d4b-8daf-b3f8297f7bc9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1210089451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.1210089451
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.4242743106
Short name T1977
Test name
Test status
Simulation time 15957838209 ps
CPU time 340.1 seconds
Started Jul 21 06:52:51 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206936 kb
Host smart-d8629216-fb83-494a-a484-d18346e3403b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4242743106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.4242743106
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.790401386
Short name T2566
Test name
Test status
Simulation time 206185058 ps
CPU time 0.91 seconds
Started Jul 21 06:53:01 PM PDT 24
Finished Jul 21 06:53:03 PM PDT 24
Peak memory 206688 kb
Host smart-09f34d70-69ea-4362-9f23-7baf7d2f9702
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79040
1386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.790401386
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.2480399788
Short name T1725
Test name
Test status
Simulation time 162081637 ps
CPU time 0.8 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:52:52 PM PDT 24
Peak memory 206676 kb
Host smart-5d19d111-c4a9-492f-8481-2e628ab81201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24803
99788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.2480399788
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.1900642682
Short name T635
Test name
Test status
Simulation time 139866337 ps
CPU time 0.75 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:52:52 PM PDT 24
Peak memory 206676 kb
Host smart-6750eded-8e52-4956-ba1f-1e53787c9c5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19006
42682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.1900642682
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3795202450
Short name T71
Test name
Test status
Simulation time 199690166 ps
CPU time 0.91 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:52:51 PM PDT 24
Peak memory 206640 kb
Host smart-818848a4-f13e-4ae6-af7e-fa24cbc09ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37952
02450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3795202450
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.271227886
Short name T803
Test name
Test status
Simulation time 315957100 ps
CPU time 0.97 seconds
Started Jul 21 06:52:58 PM PDT 24
Finished Jul 21 06:53:00 PM PDT 24
Peak memory 206668 kb
Host smart-42a0c1e4-6a22-4eec-93a3-453e6f892d55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27122
7886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.271227886
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.1682887995
Short name T1716
Test name
Test status
Simulation time 195826664 ps
CPU time 0.86 seconds
Started Jul 21 06:52:58 PM PDT 24
Finished Jul 21 06:53:00 PM PDT 24
Peak memory 206660 kb
Host smart-bc0ab923-6073-484c-b29b-0e60d25c91b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16828
87995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.1682887995
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1185840219
Short name T86
Test name
Test status
Simulation time 159846207 ps
CPU time 0.77 seconds
Started Jul 21 06:52:51 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206600 kb
Host smart-b6d28171-9f68-40b1-861d-0cd1b3acb7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11858
40219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1185840219
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.2775949740
Short name T204
Test name
Test status
Simulation time 262892914 ps
CPU time 1.01 seconds
Started Jul 21 06:52:52 PM PDT 24
Finished Jul 21 06:52:54 PM PDT 24
Peak memory 206556 kb
Host smart-ac95ae0a-05f7-4928-a59a-8b2cf8c1629c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27759
49740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.2775949740
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.2448175789
Short name T1633
Test name
Test status
Simulation time 6145237462 ps
CPU time 43.26 seconds
Started Jul 21 06:53:01 PM PDT 24
Finished Jul 21 06:53:45 PM PDT 24
Peak memory 206904 kb
Host smart-9a4b56d9-2e89-4236-8f0a-f43326ea7483
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2448175789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.2448175789
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.2902082004
Short name T1709
Test name
Test status
Simulation time 197372234 ps
CPU time 0.82 seconds
Started Jul 21 06:52:53 PM PDT 24
Finished Jul 21 06:52:54 PM PDT 24
Peak memory 206652 kb
Host smart-92cd2cc3-e1ed-4530-a691-a4dc575f88d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29020
82004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.2902082004
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.203849536
Short name T2253
Test name
Test status
Simulation time 169538874 ps
CPU time 0.86 seconds
Started Jul 21 06:53:00 PM PDT 24
Finished Jul 21 06:53:02 PM PDT 24
Peak memory 206696 kb
Host smart-76228374-7fce-4f58-bf10-31c0490bd1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20384
9536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.203849536
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.2339468046
Short name T2603
Test name
Test status
Simulation time 569545083 ps
CPU time 1.5 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206672 kb
Host smart-7ee10be7-cb0c-45c3-9951-86a337b4bf06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23394
68046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.2339468046
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.2395515600
Short name T146
Test name
Test status
Simulation time 4333951292 ps
CPU time 38.26 seconds
Started Jul 21 06:52:52 PM PDT 24
Finished Jul 21 06:53:31 PM PDT 24
Peak memory 206832 kb
Host smart-8ec81395-f3f1-432d-9040-c62f32c56ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23955
15600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.2395515600
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.3509089373
Short name T1316
Test name
Test status
Simulation time 34313449 ps
CPU time 0.64 seconds
Started Jul 21 06:54:51 PM PDT 24
Finished Jul 21 06:54:52 PM PDT 24
Peak memory 206724 kb
Host smart-73b5efe1-8dfe-40cc-a138-791f3f2408fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3509089373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.3509089373
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.4004899
Short name T1112
Test name
Test status
Simulation time 3759174698 ps
CPU time 5.47 seconds
Started Jul 21 06:54:41 PM PDT 24
Finished Jul 21 06:54:47 PM PDT 24
Peak memory 206720 kb
Host smart-1495cd32-0974-462d-97c6-d19fa0afd9ac
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4004899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.4004899
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.2888670354
Short name T2373
Test name
Test status
Simulation time 13424847545 ps
CPU time 12.45 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:54:55 PM PDT 24
Peak memory 206760 kb
Host smart-56c33e89-d900-496f-a1d6-689268b18e08
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2888670354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.2888670354
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.700336255
Short name T1849
Test name
Test status
Simulation time 23397966535 ps
CPU time 26.3 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:55:10 PM PDT 24
Peak memory 206812 kb
Host smart-6d135944-fbf9-4448-a290-b7bc85a846f0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=700336255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.700336255
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.2911151945
Short name T2346
Test name
Test status
Simulation time 210466568 ps
CPU time 0.85 seconds
Started Jul 21 06:54:45 PM PDT 24
Finished Jul 21 06:54:47 PM PDT 24
Peak memory 206680 kb
Host smart-15c28233-12f0-43f4-a202-685ed24d2655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29111
51945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.2911151945
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3090405089
Short name T1862
Test name
Test status
Simulation time 186891493 ps
CPU time 0.86 seconds
Started Jul 21 06:54:44 PM PDT 24
Finished Jul 21 06:54:46 PM PDT 24
Peak memory 206684 kb
Host smart-097eaaf7-ce89-4d16-a4ac-efee5ea6c16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
05089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3090405089
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.3190855806
Short name T2284
Test name
Test status
Simulation time 216416213 ps
CPU time 0.89 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:54:44 PM PDT 24
Peak memory 206684 kb
Host smart-e67e2b6a-046e-489d-85f4-dbd177902490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31908
55806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.3190855806
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.2903408146
Short name T488
Test name
Test status
Simulation time 1551393295 ps
CPU time 3.42 seconds
Started Jul 21 06:54:43 PM PDT 24
Finished Jul 21 06:54:47 PM PDT 24
Peak memory 206772 kb
Host smart-40eb18f9-750b-4d71-8e25-124d622bf3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
08146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.2903408146
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.292126085
Short name T2364
Test name
Test status
Simulation time 19009694033 ps
CPU time 35.44 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206936 kb
Host smart-08d9eae6-0842-41e8-bb6e-c09f289d6dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29212
6085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.292126085
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3044144228
Short name T578
Test name
Test status
Simulation time 341033562 ps
CPU time 1.15 seconds
Started Jul 21 06:54:45 PM PDT 24
Finished Jul 21 06:54:46 PM PDT 24
Peak memory 206672 kb
Host smart-afcb47de-cadd-49d9-82b1-18430c87258b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30441
44228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3044144228
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.2357098509
Short name T512
Test name
Test status
Simulation time 140233788 ps
CPU time 0.75 seconds
Started Jul 21 06:54:41 PM PDT 24
Finished Jul 21 06:54:43 PM PDT 24
Peak memory 206672 kb
Host smart-ebd7b031-f6b2-429c-bee2-5051ec9beea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23570
98509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.2357098509
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.483932302
Short name T1173
Test name
Test status
Simulation time 34732270 ps
CPU time 0.68 seconds
Started Jul 21 06:54:41 PM PDT 24
Finished Jul 21 06:54:42 PM PDT 24
Peak memory 206620 kb
Host smart-a0303644-ea39-447d-b259-cadca32686b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48393
2302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.483932302
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.989942494
Short name T1287
Test name
Test status
Simulation time 882942195 ps
CPU time 2.02 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206700 kb
Host smart-56281c6d-bd92-49b5-8216-30a84355218b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98994
2494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.989942494
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2291805005
Short name T965
Test name
Test status
Simulation time 192737736 ps
CPU time 0.86 seconds
Started Jul 21 06:54:47 PM PDT 24
Finished Jul 21 06:54:49 PM PDT 24
Peak memory 206664 kb
Host smart-a87f57e0-2590-4932-b8d0-1b6cb5738a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22918
05005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2291805005
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3780974081
Short name T2283
Test name
Test status
Simulation time 152417373 ps
CPU time 0.76 seconds
Started Jul 21 06:54:48 PM PDT 24
Finished Jul 21 06:54:50 PM PDT 24
Peak memory 206672 kb
Host smart-bc59148f-9875-41f2-9bc1-4ec30a002271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37809
74081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3780974081
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.3287465143
Short name T1525
Test name
Test status
Simulation time 206204028 ps
CPU time 0.88 seconds
Started Jul 21 06:54:47 PM PDT 24
Finished Jul 21 06:54:49 PM PDT 24
Peak memory 206668 kb
Host smart-fc3999cc-57fb-4990-a56e-2ed8d34f8381
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32874
65143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.3287465143
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1943687949
Short name T743
Test name
Test status
Simulation time 7020587305 ps
CPU time 66.43 seconds
Started Jul 21 06:54:46 PM PDT 24
Finished Jul 21 06:55:54 PM PDT 24
Peak memory 206864 kb
Host smart-c1b38233-3b0c-4523-ae7b-469eb0db61c0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1943687949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1943687949
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_iso_retraction.3965335310
Short name T2501
Test name
Test status
Simulation time 13470197711 ps
CPU time 52.75 seconds
Started Jul 21 06:54:49 PM PDT 24
Finished Jul 21 06:55:43 PM PDT 24
Peak memory 206888 kb
Host smart-db7f1915-1120-4a5b-a01d-bd6d50a9710b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39653
35310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_iso_retraction.3965335310
Directory /workspace/10.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.824129745
Short name T1904
Test name
Test status
Simulation time 174137422 ps
CPU time 0.81 seconds
Started Jul 21 06:54:47 PM PDT 24
Finished Jul 21 06:54:48 PM PDT 24
Peak memory 206704 kb
Host smart-5000fcbb-5f62-4d90-8ad1-3bd870eb2820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82412
9745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.824129745
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.1653960167
Short name T2114
Test name
Test status
Simulation time 23321128433 ps
CPU time 24.52 seconds
Started Jul 21 06:54:47 PM PDT 24
Finished Jul 21 06:55:13 PM PDT 24
Peak memory 206816 kb
Host smart-215c3825-eeef-4ac5-ba98-cd4c881acfd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16539
60167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.1653960167
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.2475090465
Short name T300
Test name
Test status
Simulation time 3308394548 ps
CPU time 3.77 seconds
Started Jul 21 06:54:48 PM PDT 24
Finished Jul 21 06:54:52 PM PDT 24
Peak memory 206736 kb
Host smart-55c5e3d4-e093-4218-aeb5-660089eb1c8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24750
90465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.2475090465
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.3336253174
Short name T1728
Test name
Test status
Simulation time 7373553142 ps
CPU time 198.24 seconds
Started Jul 21 06:54:48 PM PDT 24
Finished Jul 21 06:58:07 PM PDT 24
Peak memory 206892 kb
Host smart-8aaf40fd-f684-4cf5-9a0e-35ad7c3f7ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33362
53174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.3336253174
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3940065974
Short name T2522
Test name
Test status
Simulation time 5850649191 ps
CPU time 58.72 seconds
Started Jul 21 06:54:49 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206952 kb
Host smart-d509aa31-0625-4e72-8d51-0b6c0fe74b17
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3940065974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3940065974
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.2097226789
Short name T1062
Test name
Test status
Simulation time 241685779 ps
CPU time 1.01 seconds
Started Jul 21 06:54:48 PM PDT 24
Finished Jul 21 06:54:50 PM PDT 24
Peak memory 206664 kb
Host smart-ced11651-4d61-451f-b0cd-0aff35612dc1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2097226789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.2097226789
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.3913320074
Short name T1041
Test name
Test status
Simulation time 184750682 ps
CPU time 0.91 seconds
Started Jul 21 06:54:48 PM PDT 24
Finished Jul 21 06:54:50 PM PDT 24
Peak memory 206660 kb
Host smart-2b92ad7a-2127-443b-bc68-cccd4ab61c50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39133
20074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.3913320074
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2146115560
Short name T1493
Test name
Test status
Simulation time 3835203614 ps
CPU time 27.54 seconds
Started Jul 21 06:54:46 PM PDT 24
Finished Jul 21 06:55:15 PM PDT 24
Peak memory 206864 kb
Host smart-8e6cbd3d-cd0c-4d13-84aa-636d71a4dcbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21461
15560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2146115560
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3711353400
Short name T1264
Test name
Test status
Simulation time 7204657039 ps
CPU time 51.66 seconds
Started Jul 21 06:54:47 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206860 kb
Host smart-1a4a108e-fd67-46af-8f9b-3406fd88d0e2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3711353400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3711353400
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.3307431380
Short name T1456
Test name
Test status
Simulation time 157788431 ps
CPU time 0.86 seconds
Started Jul 21 06:54:47 PM PDT 24
Finished Jul 21 06:54:49 PM PDT 24
Peak memory 206680 kb
Host smart-e958e768-caab-42cd-84cc-2c4309f84d21
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3307431380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.3307431380
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.1712813779
Short name T365
Test name
Test status
Simulation time 145843559 ps
CPU time 0.79 seconds
Started Jul 21 06:54:47 PM PDT 24
Finished Jul 21 06:54:49 PM PDT 24
Peak memory 206676 kb
Host smart-36914846-10bd-4798-a50d-77b5036873e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17128
13779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.1712813779
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.1848433698
Short name T386
Test name
Test status
Simulation time 205441633 ps
CPU time 0.9 seconds
Started Jul 21 06:54:55 PM PDT 24
Finished Jul 21 06:54:57 PM PDT 24
Peak memory 206648 kb
Host smart-56ed0f16-f8a1-4db7-b034-0346d601e4d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18484
33698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.1848433698
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2431866718
Short name T1090
Test name
Test status
Simulation time 169336154 ps
CPU time 0.81 seconds
Started Jul 21 06:54:51 PM PDT 24
Finished Jul 21 06:54:53 PM PDT 24
Peak memory 206676 kb
Host smart-570b0917-79f6-4f41-a938-4714e35ac5c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24318
66718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2431866718
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.1469105993
Short name T1286
Test name
Test status
Simulation time 185904682 ps
CPU time 0.82 seconds
Started Jul 21 06:54:51 PM PDT 24
Finished Jul 21 06:54:52 PM PDT 24
Peak memory 206656 kb
Host smart-c31601d3-0e9d-47a0-840d-c3d43b1c6b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14691
05993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.1469105993
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.4048518076
Short name T2016
Test name
Test status
Simulation time 147907161 ps
CPU time 0.79 seconds
Started Jul 21 06:54:51 PM PDT 24
Finished Jul 21 06:54:53 PM PDT 24
Peak memory 206672 kb
Host smart-45dbed94-1e6e-46ea-8eff-ccf94968e1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40485
18076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.4048518076
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.3107507227
Short name T1364
Test name
Test status
Simulation time 230695306 ps
CPU time 0.91 seconds
Started Jul 21 06:54:56 PM PDT 24
Finished Jul 21 06:54:57 PM PDT 24
Peak memory 206648 kb
Host smart-e78fd78f-058f-4fcc-887f-e57e90e3273c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3107507227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.3107507227
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.687347725
Short name T2355
Test name
Test status
Simulation time 149221396 ps
CPU time 0.77 seconds
Started Jul 21 06:55:00 PM PDT 24
Finished Jul 21 06:55:02 PM PDT 24
Peak memory 206688 kb
Host smart-ecb6af25-9ddb-49a1-b589-79fc0ecf62d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68734
7725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.687347725
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.706606229
Short name T2720
Test name
Test status
Simulation time 37246553 ps
CPU time 0.65 seconds
Started Jul 21 06:54:50 PM PDT 24
Finished Jul 21 06:54:51 PM PDT 24
Peak memory 206700 kb
Host smart-6d5c139d-597a-4e90-8787-b407041f56d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70660
6229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.706606229
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2767302313
Short name T1956
Test name
Test status
Simulation time 21785368421 ps
CPU time 52.2 seconds
Started Jul 21 06:54:53 PM PDT 24
Finished Jul 21 06:55:45 PM PDT 24
Peak memory 215164 kb
Host smart-b0bca0ef-1a62-4d90-b8de-9992cbae3dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
02313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2767302313
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3019453564
Short name T2498
Test name
Test status
Simulation time 219344826 ps
CPU time 0.85 seconds
Started Jul 21 06:54:52 PM PDT 24
Finished Jul 21 06:54:53 PM PDT 24
Peak memory 206684 kb
Host smart-1bf3e77f-186a-4727-a985-ab923e2e47d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30194
53564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3019453564
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.2339078175
Short name T1385
Test name
Test status
Simulation time 273882406 ps
CPU time 0.95 seconds
Started Jul 21 06:55:00 PM PDT 24
Finished Jul 21 06:55:02 PM PDT 24
Peak memory 206692 kb
Host smart-1b416217-ddab-44c9-9595-c28f8fa38331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23390
78175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.2339078175
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.3759790003
Short name T2329
Test name
Test status
Simulation time 290646459 ps
CPU time 0.95 seconds
Started Jul 21 06:54:55 PM PDT 24
Finished Jul 21 06:54:57 PM PDT 24
Peak memory 206648 kb
Host smart-cc06ffca-83d6-48fd-92ea-c9a9cf7e3925
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37597
90003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.3759790003
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.2909277565
Short name T1258
Test name
Test status
Simulation time 156683087 ps
CPU time 0.79 seconds
Started Jul 21 06:54:51 PM PDT 24
Finished Jul 21 06:54:52 PM PDT 24
Peak memory 206696 kb
Host smart-8e0367d3-d2e4-4fe7-9282-f2e43f092215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29092
77565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.2909277565
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.3490949617
Short name T1417
Test name
Test status
Simulation time 207068755 ps
CPU time 0.8 seconds
Started Jul 21 06:54:50 PM PDT 24
Finished Jul 21 06:54:51 PM PDT 24
Peak memory 206640 kb
Host smart-02ef8b70-a0e0-46f4-adc2-272ee321af48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
49617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.3490949617
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.4057986605
Short name T1544
Test name
Test status
Simulation time 172024525 ps
CPU time 0.78 seconds
Started Jul 21 06:54:52 PM PDT 24
Finished Jul 21 06:54:53 PM PDT 24
Peak memory 206700 kb
Host smart-70e78328-767d-4abb-be06-f760f6cdd9f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40579
86605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.4057986605
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.4281631352
Short name T580
Test name
Test status
Simulation time 149559478 ps
CPU time 0.81 seconds
Started Jul 21 06:54:53 PM PDT 24
Finished Jul 21 06:54:54 PM PDT 24
Peak memory 206632 kb
Host smart-b5ffbe3c-0a1f-4222-8b93-83292f1a4b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42816
31352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.4281631352
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1452024599
Short name T2150
Test name
Test status
Simulation time 264243363 ps
CPU time 0.88 seconds
Started Jul 21 06:54:59 PM PDT 24
Finished Jul 21 06:55:00 PM PDT 24
Peak memory 206688 kb
Host smart-883b6826-9b05-46df-930b-0d38be4f3d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14520
24599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1452024599
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.47797661
Short name T525
Test name
Test status
Simulation time 4424008551 ps
CPU time 122.36 seconds
Started Jul 21 06:54:52 PM PDT 24
Finished Jul 21 06:56:55 PM PDT 24
Peak memory 206884 kb
Host smart-7df7cd0e-cb52-40ce-88d5-674a03d19a52
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=47797661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.47797661
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.2696822334
Short name T1539
Test name
Test status
Simulation time 184473776 ps
CPU time 0.86 seconds
Started Jul 21 06:54:52 PM PDT 24
Finished Jul 21 06:54:54 PM PDT 24
Peak memory 206660 kb
Host smart-22ea37cc-6346-4632-bf57-407f4c6e38f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26968
22334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.2696822334
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1956077374
Short name T1319
Test name
Test status
Simulation time 175091146 ps
CPU time 0.78 seconds
Started Jul 21 06:54:51 PM PDT 24
Finished Jul 21 06:54:52 PM PDT 24
Peak memory 206680 kb
Host smart-5749e2dd-e321-4617-ac73-4dee9099ea7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19560
77374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1956077374
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.4027953705
Short name T1474
Test name
Test status
Simulation time 904527993 ps
CPU time 1.91 seconds
Started Jul 21 06:55:00 PM PDT 24
Finished Jul 21 06:55:02 PM PDT 24
Peak memory 206840 kb
Host smart-92671d5a-0fc2-4bd1-94f9-7a1aa9273e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40279
53705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.4027953705
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.665354308
Short name T2242
Test name
Test status
Simulation time 6730167941 ps
CPU time 46.44 seconds
Started Jul 21 06:54:53 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206848 kb
Host smart-48c58f16-113c-425f-8acd-cb6fe3ce53ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66535
4308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.665354308
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.3259385697
Short name T1961
Test name
Test status
Simulation time 48048985 ps
CPU time 0.73 seconds
Started Jul 21 06:55:07 PM PDT 24
Finished Jul 21 06:55:09 PM PDT 24
Peak memory 206704 kb
Host smart-e53cdc75-7fa5-4311-9531-9c30b0723b7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3259385697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.3259385697
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.911893320
Short name T687
Test name
Test status
Simulation time 3396592620 ps
CPU time 4.4 seconds
Started Jul 21 06:54:57 PM PDT 24
Finished Jul 21 06:55:02 PM PDT 24
Peak memory 206756 kb
Host smart-d6c45f0a-11b0-4f07-a8ce-43e40b699e0c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=911893320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.911893320
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.1431150299
Short name T735
Test name
Test status
Simulation time 13384943659 ps
CPU time 12.76 seconds
Started Jul 21 06:54:56 PM PDT 24
Finished Jul 21 06:55:09 PM PDT 24
Peak memory 206864 kb
Host smart-0a200d84-cdb7-4160-89b1-0acbaa9fe379
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1431150299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.1431150299
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.3522439910
Short name T2057
Test name
Test status
Simulation time 23401095940 ps
CPU time 23.94 seconds
Started Jul 21 06:54:57 PM PDT 24
Finished Jul 21 06:55:22 PM PDT 24
Peak memory 206804 kb
Host smart-5b865600-2546-4ee8-852b-9ece77662c4b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3522439910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.3522439910
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.1547572778
Short name T2070
Test name
Test status
Simulation time 153328362 ps
CPU time 0.8 seconds
Started Jul 21 06:54:57 PM PDT 24
Finished Jul 21 06:54:58 PM PDT 24
Peak memory 206680 kb
Host smart-bacbe5d1-fcec-4659-accc-ac8828ea366e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15475
72778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.1547572778
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3345982942
Short name T1993
Test name
Test status
Simulation time 154773331 ps
CPU time 0.78 seconds
Started Jul 21 06:54:56 PM PDT 24
Finished Jul 21 06:54:58 PM PDT 24
Peak memory 206684 kb
Host smart-0b5b3391-399c-4b82-a3b7-d3a3fea053cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33459
82942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3345982942
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.155484648
Short name T1999
Test name
Test status
Simulation time 317277621 ps
CPU time 1.16 seconds
Started Jul 21 06:54:57 PM PDT 24
Finished Jul 21 06:54:58 PM PDT 24
Peak memory 206648 kb
Host smart-5583313e-6c65-4ed2-9577-c1b77ee19f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15548
4648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.155484648
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.1614398682
Short name T395
Test name
Test status
Simulation time 954709307 ps
CPU time 2.23 seconds
Started Jul 21 06:54:58 PM PDT 24
Finished Jul 21 06:55:01 PM PDT 24
Peak memory 206792 kb
Host smart-2e988b13-7a43-457d-b9bd-d9b0e4a3b1ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16143
98682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.1614398682
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.1286272053
Short name T1276
Test name
Test status
Simulation time 13980288041 ps
CPU time 31.14 seconds
Started Jul 21 06:54:55 PM PDT 24
Finished Jul 21 06:55:27 PM PDT 24
Peak memory 206936 kb
Host smart-abfedaf4-551b-487a-b11d-8cf066df904a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12862
72053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.1286272053
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.1829747867
Short name T2
Test name
Test status
Simulation time 342963589 ps
CPU time 1.13 seconds
Started Jul 21 06:54:55 PM PDT 24
Finished Jul 21 06:54:57 PM PDT 24
Peak memory 206652 kb
Host smart-8c996e47-0330-4c83-b9c1-3e957c30d1f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18297
47867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.1829747867
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3139916824
Short name T2116
Test name
Test status
Simulation time 136498758 ps
CPU time 0.74 seconds
Started Jul 21 06:54:56 PM PDT 24
Finished Jul 21 06:54:57 PM PDT 24
Peak memory 206688 kb
Host smart-c8774603-c8d9-4560-b942-015d31dafbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31399
16824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3139916824
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.3577695669
Short name T2596
Test name
Test status
Simulation time 49285403 ps
CPU time 0.68 seconds
Started Jul 21 06:54:56 PM PDT 24
Finished Jul 21 06:54:58 PM PDT 24
Peak memory 206680 kb
Host smart-129b55d2-d322-47da-aa89-9d0af355bf9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35776
95669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.3577695669
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.3809275126
Short name T1339
Test name
Test status
Simulation time 973603242 ps
CPU time 2.24 seconds
Started Jul 21 06:54:57 PM PDT 24
Finished Jul 21 06:54:59 PM PDT 24
Peak memory 206808 kb
Host smart-afa90145-6701-40f6-babd-ce484a9abb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38092
75126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.3809275126
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.387425554
Short name T2452
Test name
Test status
Simulation time 190311147 ps
CPU time 2.15 seconds
Started Jul 21 06:55:04 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206796 kb
Host smart-b491c32f-e160-4329-bc70-d2bf72d01d1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38742
5554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.387425554
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.4096373590
Short name T2347
Test name
Test status
Simulation time 222883913 ps
CPU time 0.92 seconds
Started Jul 21 06:55:04 PM PDT 24
Finished Jul 21 06:55:05 PM PDT 24
Peak memory 206736 kb
Host smart-296ac87d-3a2c-4def-ab58-17fa0fe016be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40963
73590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.4096373590
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.1374981579
Short name T1299
Test name
Test status
Simulation time 182440098 ps
CPU time 0.84 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:03 PM PDT 24
Peak memory 206684 kb
Host smart-49cce4ad-e4e1-47b5-9afe-75551efec5c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13749
81579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.1374981579
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3047365647
Short name T1670
Test name
Test status
Simulation time 244903116 ps
CPU time 0.93 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:04 PM PDT 24
Peak memory 206696 kb
Host smart-db7bd685-774f-4c34-a026-3935d97dbe9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30473
65647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3047365647
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_invalid_sync.2804406913
Short name T1572
Test name
Test status
Simulation time 6977909548 ps
CPU time 50.42 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:52 PM PDT 24
Peak memory 206872 kb
Host smart-ede254cb-137b-401c-8075-16528e719def
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2804406913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_invalid_sync.2804406913
Directory /workspace/11.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.2872772468
Short name T81
Test name
Test status
Simulation time 12610630999 ps
CPU time 39.28 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:43 PM PDT 24
Peak memory 206852 kb
Host smart-4d1d7733-d339-474c-b3c6-f11a9ad50853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28727
72468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.2872772468
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.3277301652
Short name T524
Test name
Test status
Simulation time 177000236 ps
CPU time 0.81 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:04 PM PDT 24
Peak memory 206608 kb
Host smart-d9802997-f89b-469e-b3d6-f746a2317e29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32773
01652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.3277301652
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.3969023009
Short name T2740
Test name
Test status
Simulation time 3355530068 ps
CPU time 3.74 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206720 kb
Host smart-7766dff6-623b-4def-afd0-d8baad1c7279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39690
23009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.3969023009
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.3842127458
Short name T863
Test name
Test status
Simulation time 12777543724 ps
CPU time 99.79 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:56:43 PM PDT 24
Peak memory 206928 kb
Host smart-b6c616fc-8124-4cd1-bfc3-2a99e5333d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38421
27458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.3842127458
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.2257728840
Short name T659
Test name
Test status
Simulation time 5378461873 ps
CPU time 39.04 seconds
Started Jul 21 06:55:04 PM PDT 24
Finished Jul 21 06:55:44 PM PDT 24
Peak memory 206844 kb
Host smart-f4904eae-88f3-455a-9171-ed2d4d9e3478
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2257728840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.2257728840
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1155323742
Short name T1537
Test name
Test status
Simulation time 270131231 ps
CPU time 1 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:03 PM PDT 24
Peak memory 206692 kb
Host smart-e6f68f1c-dee3-45f0-8999-d6f0c4d74705
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1155323742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1155323742
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.1710604574
Short name T1323
Test name
Test status
Simulation time 182113164 ps
CPU time 0.86 seconds
Started Jul 21 06:55:05 PM PDT 24
Finished Jul 21 06:55:06 PM PDT 24
Peak memory 206680 kb
Host smart-860d08c2-e72a-4579-8534-c976455f5dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17106
04574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.1710604574
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.3052831036
Short name T1888
Test name
Test status
Simulation time 5570059937 ps
CPU time 53.31 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:55 PM PDT 24
Peak memory 206944 kb
Host smart-5ba43467-86a6-46dd-ac27-330da21c53b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30528
31036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.3052831036
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.2979323492
Short name T2728
Test name
Test status
Simulation time 2977965234 ps
CPU time 28.36 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:31 PM PDT 24
Peak memory 206912 kb
Host smart-d7cc79fc-6b00-4428-984a-9b3d404c8df9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2979323492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.2979323492
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3075964297
Short name T2486
Test name
Test status
Simulation time 152631172 ps
CPU time 0.79 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:02 PM PDT 24
Peak memory 206680 kb
Host smart-16e465a6-bfdf-41b9-a992-40e3349dce89
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3075964297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3075964297
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2203221954
Short name T1665
Test name
Test status
Simulation time 148040071 ps
CPU time 0.83 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:04 PM PDT 24
Peak memory 206652 kb
Host smart-c56ea060-2632-4d23-8f75-f17812a140ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22032
21954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2203221954
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2732462354
Short name T2692
Test name
Test status
Simulation time 151053175 ps
CPU time 0.8 seconds
Started Jul 21 06:55:03 PM PDT 24
Finished Jul 21 06:55:05 PM PDT 24
Peak memory 206672 kb
Host smart-ebab2485-522b-4892-a4b7-e90452688493
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27324
62354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2732462354
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.2894983288
Short name T2491
Test name
Test status
Simulation time 153968536 ps
CPU time 0.83 seconds
Started Jul 21 06:55:03 PM PDT 24
Finished Jul 21 06:55:05 PM PDT 24
Peak memory 206664 kb
Host smart-c57e86ae-8581-4cdb-97f2-1056fb6f0b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
83288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.2894983288
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3580643066
Short name T2503
Test name
Test status
Simulation time 219219765 ps
CPU time 0.85 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:03 PM PDT 24
Peak memory 206640 kb
Host smart-bfce298c-e088-45d5-a6e8-713d1ed7be33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35806
43066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3580643066
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.4182800563
Short name T1268
Test name
Test status
Simulation time 153388212 ps
CPU time 0.76 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:03 PM PDT 24
Peak memory 206664 kb
Host smart-3de3235b-a5bb-42ff-a152-99f107766ed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41828
00563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.4182800563
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.821798960
Short name T2340
Test name
Test status
Simulation time 256380383 ps
CPU time 0.95 seconds
Started Jul 21 06:55:01 PM PDT 24
Finished Jul 21 06:55:03 PM PDT 24
Peak memory 206680 kb
Host smart-dd34c01c-b7f0-4e5d-8efc-c7c6930a225b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=821798960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.821798960
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.3135486738
Short name T2623
Test name
Test status
Simulation time 149859589 ps
CPU time 0.77 seconds
Started Jul 21 06:55:03 PM PDT 24
Finished Jul 21 06:55:05 PM PDT 24
Peak memory 206672 kb
Host smart-b0131427-d210-4e1f-8744-2ff9c2337c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31354
86738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.3135486738
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.2932250818
Short name T1070
Test name
Test status
Simulation time 14447319711 ps
CPU time 31.02 seconds
Started Jul 21 06:55:00 PM PDT 24
Finished Jul 21 06:55:32 PM PDT 24
Peak memory 206944 kb
Host smart-b24a15bb-e65c-4822-98fa-ab0d356fa70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29322
50818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.2932250818
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2386590116
Short name T594
Test name
Test status
Simulation time 160228167 ps
CPU time 0.79 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:04 PM PDT 24
Peak memory 206612 kb
Host smart-fa6771da-2165-4680-b4f5-ce5760ac57ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23865
90116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2386590116
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.340148673
Short name T902
Test name
Test status
Simulation time 219101102 ps
CPU time 0.86 seconds
Started Jul 21 06:55:03 PM PDT 24
Finished Jul 21 06:55:05 PM PDT 24
Peak memory 206660 kb
Host smart-13ea58e4-c4ba-468d-afb0-b20ce19f6f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34014
8673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.340148673
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.2200179389
Short name T1227
Test name
Test status
Simulation time 223547964 ps
CPU time 0.9 seconds
Started Jul 21 06:55:02 PM PDT 24
Finished Jul 21 06:55:04 PM PDT 24
Peak memory 206664 kb
Host smart-4fc66d8d-ada0-462b-94a4-6806766181fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22001
79389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.2200179389
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.3231002881
Short name T2460
Test name
Test status
Simulation time 172862063 ps
CPU time 0.87 seconds
Started Jul 21 06:55:05 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206656 kb
Host smart-1d40425f-e9e4-4267-a56a-44e6127715b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32310
02881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.3231002881
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.158349768
Short name T897
Test name
Test status
Simulation time 211727954 ps
CPU time 0.95 seconds
Started Jul 21 06:55:06 PM PDT 24
Finished Jul 21 06:55:08 PM PDT 24
Peak memory 206712 kb
Host smart-c852135f-36df-4f37-b5e7-6aa13c7f38da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15834
9768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.158349768
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.131763914
Short name T2588
Test name
Test status
Simulation time 178202006 ps
CPU time 0.83 seconds
Started Jul 21 06:55:05 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206704 kb
Host smart-8567edf3-c78f-479d-bf25-354397d80f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13176
3914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.131763914
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1024832188
Short name T1876
Test name
Test status
Simulation time 217665193 ps
CPU time 0.81 seconds
Started Jul 21 06:55:06 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206660 kb
Host smart-4dfbdcc3-4a36-4f62-88f7-081ed2c354b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10248
32188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1024832188
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.1091584379
Short name T399
Test name
Test status
Simulation time 265589637 ps
CPU time 0.97 seconds
Started Jul 21 06:55:04 PM PDT 24
Finished Jul 21 06:55:06 PM PDT 24
Peak memory 206724 kb
Host smart-bcd4ecbb-130c-440c-a0f7-33a0d2744cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10915
84379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.1091584379
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.6395814
Short name T898
Test name
Test status
Simulation time 3236771795 ps
CPU time 22.98 seconds
Started Jul 21 06:55:07 PM PDT 24
Finished Jul 21 06:55:31 PM PDT 24
Peak memory 206880 kb
Host smart-c714b0a5-f698-4018-8f6e-6a8984a82833
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=6395814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.6395814
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.872005968
Short name T1088
Test name
Test status
Simulation time 158796335 ps
CPU time 0.77 seconds
Started Jul 21 06:55:04 PM PDT 24
Finished Jul 21 06:55:06 PM PDT 24
Peak memory 206652 kb
Host smart-ebe77eb9-a9ba-458a-8bdf-f5a288e19884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87200
5968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.872005968
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.3270049532
Short name T2015
Test name
Test status
Simulation time 180020158 ps
CPU time 0.79 seconds
Started Jul 21 06:55:16 PM PDT 24
Finished Jul 21 06:55:17 PM PDT 24
Peak memory 206680 kb
Host smart-1bfb6750-4949-45c8-8867-77e3c41999ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32700
49532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.3270049532
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.101269511
Short name T1197
Test name
Test status
Simulation time 204274019 ps
CPU time 0.92 seconds
Started Jul 21 06:55:06 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206656 kb
Host smart-3370f9cc-a50c-4a68-bb26-b2a2f9aa8186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10126
9511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.101269511
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3993313936
Short name T2038
Test name
Test status
Simulation time 7872479528 ps
CPU time 219.59 seconds
Started Jul 21 06:55:13 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206940 kb
Host smart-44bff6d1-c087-43cf-a1e3-8747c05a73ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39933
13936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3993313936
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.792606196
Short name T2413
Test name
Test status
Simulation time 42024981 ps
CPU time 0.7 seconds
Started Jul 21 06:55:22 PM PDT 24
Finished Jul 21 06:55:23 PM PDT 24
Peak memory 206704 kb
Host smart-c8784b40-349c-454e-8201-0264a6efc470
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=792606196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.792606196
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.3741128930
Short name T2511
Test name
Test status
Simulation time 3647765172 ps
CPU time 4.22 seconds
Started Jul 21 06:55:06 PM PDT 24
Finished Jul 21 06:55:11 PM PDT 24
Peak memory 206720 kb
Host smart-a60e95f6-51eb-4dbd-bef9-4751ed71d603
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3741128930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.3741128930
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.1130747082
Short name T775
Test name
Test status
Simulation time 13326716426 ps
CPU time 12.3 seconds
Started Jul 21 06:55:06 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206904 kb
Host smart-a9666fe3-3c6e-4dbc-9957-cde69bde0138
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1130747082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.1130747082
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.1494065038
Short name T184
Test name
Test status
Simulation time 23376722683 ps
CPU time 22.89 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:55:38 PM PDT 24
Peak memory 206816 kb
Host smart-c7cf1b1d-8c0b-40b3-8b80-902c3032031b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1494065038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.1494065038
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.2420773161
Short name T362
Test name
Test status
Simulation time 167775202 ps
CPU time 0.81 seconds
Started Jul 21 06:55:05 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206676 kb
Host smart-6241dae1-ee76-4355-b374-c93c2195b97c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24207
73161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.2420773161
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.1942388641
Short name T2756
Test name
Test status
Simulation time 158592060 ps
CPU time 0.75 seconds
Started Jul 21 06:55:06 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206696 kb
Host smart-710e428b-f4df-45d2-8308-d5122c56fcd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
88641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.1942388641
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.4278831085
Short name T864
Test name
Test status
Simulation time 506973541 ps
CPU time 1.58 seconds
Started Jul 21 06:55:05 PM PDT 24
Finished Jul 21 06:55:08 PM PDT 24
Peak memory 206764 kb
Host smart-97881313-71d6-49c8-9136-ee4287e5fe5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42788
31085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.4278831085
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.198609454
Short name T1735
Test name
Test status
Simulation time 995489593 ps
CPU time 2.21 seconds
Started Jul 21 06:55:07 PM PDT 24
Finished Jul 21 06:55:10 PM PDT 24
Peak memory 206748 kb
Host smart-0291fb5b-054d-46c0-9c59-1386dc307626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19860
9454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.198609454
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3605586844
Short name T2434
Test name
Test status
Simulation time 16074406170 ps
CPU time 30.02 seconds
Started Jul 21 06:55:06 PM PDT 24
Finished Jul 21 06:55:37 PM PDT 24
Peak memory 206896 kb
Host smart-b05ecefc-3ae8-423f-913c-4736e4710070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36055
86844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3605586844
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2698730235
Short name T2594
Test name
Test status
Simulation time 422494965 ps
CPU time 1.47 seconds
Started Jul 21 06:55:08 PM PDT 24
Finished Jul 21 06:55:10 PM PDT 24
Peak memory 206664 kb
Host smart-f13d69b6-4ba2-4ab6-9d54-8b546705310c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26987
30235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2698730235
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.3756028035
Short name T1271
Test name
Test status
Simulation time 167626548 ps
CPU time 0.79 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:55:16 PM PDT 24
Peak memory 206680 kb
Host smart-327f2ef7-7d06-4cf6-9ec9-032118f6d253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37560
28035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.3756028035
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.2042929705
Short name T1483
Test name
Test status
Simulation time 65499337 ps
CPU time 0.67 seconds
Started Jul 21 06:55:16 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206624 kb
Host smart-8b865593-3462-49a0-ab6e-e09bee6a043b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20429
29705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.2042929705
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.1667377924
Short name T2072
Test name
Test status
Simulation time 864481469 ps
CPU time 1.89 seconds
Started Jul 21 06:55:17 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206796 kb
Host smart-e68821e4-dddd-48f5-bf33-f57050f52b45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16673
77924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.1667377924
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1267755152
Short name T945
Test name
Test status
Simulation time 201943978 ps
CPU time 1.64 seconds
Started Jul 21 06:55:16 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206768 kb
Host smart-4d2e23ff-249e-4b66-b264-51d0c7531351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12677
55152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1267755152
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3251411089
Short name T2142
Test name
Test status
Simulation time 208160585 ps
CPU time 0.89 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:55:16 PM PDT 24
Peak memory 206684 kb
Host smart-e1ffee4a-2f0e-4e97-90b4-13bc27a8ae30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32514
11089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3251411089
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.3775886577
Short name T1683
Test name
Test status
Simulation time 140944593 ps
CPU time 0.81 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:55:16 PM PDT 24
Peak memory 206676 kb
Host smart-b9cbe461-fd39-4395-bb89-b395b79cfd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37758
86577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.3775886577
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.230503020
Short name T1094
Test name
Test status
Simulation time 243014981 ps
CPU time 1.04 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206684 kb
Host smart-aa3679bc-fa3b-4685-a72a-ab794c125c56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23050
3020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.230503020
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.3913430935
Short name T1765
Test name
Test status
Simulation time 7429379312 ps
CPU time 206.28 seconds
Started Jul 21 06:55:22 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206880 kb
Host smart-efb7594d-d229-462c-9baf-9c74866d6ffb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3913430935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.3913430935
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_iso_retraction.1189233983
Short name T1330
Test name
Test status
Simulation time 13120366643 ps
CPU time 46.63 seconds
Started Jul 21 06:55:22 PM PDT 24
Finished Jul 21 06:56:09 PM PDT 24
Peak memory 206956 kb
Host smart-61102308-f5c2-4294-aa8b-94c62bc5b246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11892
33983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_iso_retraction.1189233983
Directory /workspace/12.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.4104804042
Short name T2094
Test name
Test status
Simulation time 258981035 ps
CPU time 0.92 seconds
Started Jul 21 06:55:13 PM PDT 24
Finished Jul 21 06:55:15 PM PDT 24
Peak memory 206684 kb
Host smart-714f6650-2420-4c62-8deb-6bba57fe743b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41048
04042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.4104804042
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.3606016263
Short name T670
Test name
Test status
Simulation time 23309638323 ps
CPU time 23.03 seconds
Started Jul 21 06:55:15 PM PDT 24
Finished Jul 21 06:55:39 PM PDT 24
Peak memory 206804 kb
Host smart-f17ed413-40e0-4ad3-a177-ed421dceeaad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36060
16263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.3606016263
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.2686846459
Short name T1281
Test name
Test status
Simulation time 3335399398 ps
CPU time 4.01 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206748 kb
Host smart-a1b99fc4-6c8e-40b9-913e-53cd77c42cb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26868
46459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.2686846459
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.2616069963
Short name T2379
Test name
Test status
Simulation time 6413468187 ps
CPU time 171.38 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:58:07 PM PDT 24
Peak memory 206980 kb
Host smart-c10c24f2-7eb5-46ae-92a0-96f2c3adf9e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26160
69963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.2616069963
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2131134350
Short name T1634
Test name
Test status
Simulation time 5184820571 ps
CPU time 46.08 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206904 kb
Host smart-6a9a49c9-726c-42b8-bb71-cbb5f6bea828
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2131134350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2131134350
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1236397841
Short name T506
Test name
Test status
Simulation time 247416287 ps
CPU time 0.9 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:55:16 PM PDT 24
Peak memory 206656 kb
Host smart-ff5bdd60-9f63-4b1f-812b-43df123c06d3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1236397841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1236397841
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.1914884956
Short name T1391
Test name
Test status
Simulation time 240923665 ps
CPU time 0.9 seconds
Started Jul 21 06:55:13 PM PDT 24
Finished Jul 21 06:55:15 PM PDT 24
Peak memory 206676 kb
Host smart-be2c7d2c-7125-405e-8a51-0ce3ec4445b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19148
84956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.1914884956
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.385600215
Short name T1613
Test name
Test status
Simulation time 4204908006 ps
CPU time 117.33 seconds
Started Jul 21 06:55:20 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206864 kb
Host smart-c1924d89-8dfc-4b7d-9bbc-2c25da35d44c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38560
0215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.385600215
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1884022068
Short name T1307
Test name
Test status
Simulation time 8292004705 ps
CPU time 58.29 seconds
Started Jul 21 06:55:13 PM PDT 24
Finished Jul 21 06:56:12 PM PDT 24
Peak memory 206892 kb
Host smart-15165d17-8b88-4826-bcd3-a095f2a473a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1884022068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1884022068
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.3827996408
Short name T337
Test name
Test status
Simulation time 184541129 ps
CPU time 0.86 seconds
Started Jul 21 06:55:14 PM PDT 24
Finished Jul 21 06:55:16 PM PDT 24
Peak memory 206688 kb
Host smart-3777cee7-84ad-4bfb-8694-8d2be38c4d47
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3827996408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.3827996408
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.2288685451
Short name T2245
Test name
Test status
Simulation time 181168029 ps
CPU time 0.79 seconds
Started Jul 21 06:55:17 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206668 kb
Host smart-158df523-f047-49fb-95c4-04d74d1b2ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22886
85451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.2288685451
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.2807646787
Short name T1325
Test name
Test status
Simulation time 226708909 ps
CPU time 0.87 seconds
Started Jul 21 06:55:22 PM PDT 24
Finished Jul 21 06:55:23 PM PDT 24
Peak memory 206684 kb
Host smart-48a75ca2-d172-4fd5-b5fe-bb9e12ecb254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28076
46787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.2807646787
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.4166415592
Short name T1840
Test name
Test status
Simulation time 160684968 ps
CPU time 0.78 seconds
Started Jul 21 06:55:17 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206696 kb
Host smart-f7b1ce06-671c-48c1-bd8f-0c5675015d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41664
15592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.4166415592
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.597484347
Short name T1938
Test name
Test status
Simulation time 277269666 ps
CPU time 0.91 seconds
Started Jul 21 06:55:18 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206664 kb
Host smart-f30f1b9b-a2fb-4f63-bd94-5de3d6a8ac5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59748
4347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.597484347
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.3468338559
Short name T733
Test name
Test status
Simulation time 163712950 ps
CPU time 0.81 seconds
Started Jul 21 06:55:16 PM PDT 24
Finished Jul 21 06:55:17 PM PDT 24
Peak memory 206636 kb
Host smart-97c43d65-76e0-40f4-9745-0cdfedb084f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34683
38559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.3468338559
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1294824459
Short name T821
Test name
Test status
Simulation time 171899937 ps
CPU time 0.8 seconds
Started Jul 21 06:55:16 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206668 kb
Host smart-d3b0cdfd-e03a-409a-88f9-6cae5fd8719b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12948
24459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1294824459
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.2044000962
Short name T955
Test name
Test status
Simulation time 201142269 ps
CPU time 0.92 seconds
Started Jul 21 06:55:18 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206668 kb
Host smart-9fac5eff-f11c-43c6-9bca-316479a02ba3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2044000962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.2044000962
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.3282955653
Short name T1853
Test name
Test status
Simulation time 156451570 ps
CPU time 0.84 seconds
Started Jul 21 06:55:17 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206696 kb
Host smart-42bcbfd0-bfcc-4d1f-84d0-043c4ca9d691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32829
55653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.3282955653
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.3022851195
Short name T1608
Test name
Test status
Simulation time 44631125 ps
CPU time 0.69 seconds
Started Jul 21 06:55:17 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206640 kb
Host smart-6ea7bea5-bed6-440a-b070-25d004e7e79d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228
51195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.3022851195
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.2844500721
Short name T1649
Test name
Test status
Simulation time 18710299220 ps
CPU time 39.4 seconds
Started Jul 21 06:55:16 PM PDT 24
Finished Jul 21 06:55:56 PM PDT 24
Peak memory 215160 kb
Host smart-2c430527-f4a9-4142-a65e-6aa4709477c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28445
00721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.2844500721
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.1517362867
Short name T583
Test name
Test status
Simulation time 193751955 ps
CPU time 0.89 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206688 kb
Host smart-bc6f4536-44fa-4fe3-9a71-9ee1265e606b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15173
62867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.1517362867
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.1822958160
Short name T2248
Test name
Test status
Simulation time 217151331 ps
CPU time 0.91 seconds
Started Jul 21 06:55:15 PM PDT 24
Finished Jul 21 06:55:17 PM PDT 24
Peak memory 206680 kb
Host smart-24d4aa75-473c-4645-a550-a318a99444f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18229
58160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.1822958160
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.1667224964
Short name T734
Test name
Test status
Simulation time 218828775 ps
CPU time 0.84 seconds
Started Jul 21 06:55:15 PM PDT 24
Finished Jul 21 06:55:17 PM PDT 24
Peak memory 206688 kb
Host smart-96f833cf-6d64-4a71-aeb0-3511a73ac3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16672
24964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.1667224964
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.1279922633
Short name T929
Test name
Test status
Simulation time 198932171 ps
CPU time 0.85 seconds
Started Jul 21 06:55:18 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206664 kb
Host smart-926e9cbb-36e8-4655-9fa9-102c30ef053b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12799
22633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.1279922633
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.103705028
Short name T2010
Test name
Test status
Simulation time 137644270 ps
CPU time 0.76 seconds
Started Jul 21 06:55:17 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206636 kb
Host smart-c7c93233-705f-4981-986c-b7e085a81333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10370
5028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.103705028
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.2465141112
Short name T1109
Test name
Test status
Simulation time 169838237 ps
CPU time 0.83 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206684 kb
Host smart-960a663c-4a74-4c59-8eb2-a1c60f8497cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24651
41112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.2465141112
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1449630133
Short name T1920
Test name
Test status
Simulation time 169415649 ps
CPU time 0.89 seconds
Started Jul 21 06:55:16 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206672 kb
Host smart-2407070c-8a66-44c0-ae80-66a87a96aaf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14496
30133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1449630133
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.1393140210
Short name T1198
Test name
Test status
Simulation time 240794755 ps
CPU time 1.01 seconds
Started Jul 21 06:55:22 PM PDT 24
Finished Jul 21 06:55:23 PM PDT 24
Peak memory 206676 kb
Host smart-f055a7ba-06d8-4a0f-a224-4ff5018c6201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13931
40210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.1393140210
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.3177277710
Short name T1118
Test name
Test status
Simulation time 3615488646 ps
CPU time 33.36 seconds
Started Jul 21 06:55:17 PM PDT 24
Finished Jul 21 06:55:51 PM PDT 24
Peak memory 206844 kb
Host smart-c470f4da-6c91-4fac-ae07-28b03239cb33
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3177277710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.3177277710
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.839470086
Short name T1295
Test name
Test status
Simulation time 160064569 ps
CPU time 0.89 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:25 PM PDT 24
Peak memory 206676 kb
Host smart-8ca9069c-5036-4aff-9864-7906df19068d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83947
0086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.839470086
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1220414111
Short name T2169
Test name
Test status
Simulation time 149404552 ps
CPU time 0.77 seconds
Started Jul 21 06:55:20 PM PDT 24
Finished Jul 21 06:55:21 PM PDT 24
Peak memory 206668 kb
Host smart-2b2da11c-a15e-4038-8f6c-e43227ecfa9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12204
14111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1220414111
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3288657458
Short name T1905
Test name
Test status
Simulation time 961751011 ps
CPU time 2.34 seconds
Started Jul 21 06:55:19 PM PDT 24
Finished Jul 21 06:55:22 PM PDT 24
Peak memory 206796 kb
Host smart-9b7f20c5-ed76-496a-b00d-e6d611263aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32886
57458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3288657458
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.3601756799
Short name T1232
Test name
Test status
Simulation time 3211005445 ps
CPU time 89.9 seconds
Started Jul 21 06:55:19 PM PDT 24
Finished Jul 21 06:56:50 PM PDT 24
Peak memory 206936 kb
Host smart-2147dea5-7ad7-404d-91cb-e9f94545437d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36017
56799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.3601756799
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.396267360
Short name T1994
Test name
Test status
Simulation time 47664104 ps
CPU time 0.68 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:34 PM PDT 24
Peak memory 206716 kb
Host smart-e33ff7d2-875a-407d-a1f7-af433170a9b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=396267360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.396267360
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2439216705
Short name T1445
Test name
Test status
Simulation time 4290664447 ps
CPU time 5.46 seconds
Started Jul 21 06:55:19 PM PDT 24
Finished Jul 21 06:55:25 PM PDT 24
Peak memory 206836 kb
Host smart-fa072565-5106-40e6-9676-71cf71dc9dc7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2439216705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2439216705
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.2428696682
Short name T1092
Test name
Test status
Simulation time 13506815744 ps
CPU time 15.18 seconds
Started Jul 21 06:55:21 PM PDT 24
Finished Jul 21 06:55:36 PM PDT 24
Peak memory 206932 kb
Host smart-07fedd09-eb8a-4db2-902f-b84c94908163
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2428696682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.2428696682
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.312533562
Short name T2752
Test name
Test status
Simulation time 23402796055 ps
CPU time 22.59 seconds
Started Jul 21 06:55:19 PM PDT 24
Finished Jul 21 06:55:42 PM PDT 24
Peak memory 206960 kb
Host smart-c71af7fd-28f1-4d97-9e49-39a183a10544
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=312533562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.312533562
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.3260147483
Short name T2159
Test name
Test status
Simulation time 204919703 ps
CPU time 0.9 seconds
Started Jul 21 06:55:18 PM PDT 24
Finished Jul 21 06:55:20 PM PDT 24
Peak memory 206700 kb
Host smart-a815bc17-7528-4b47-9240-fcf4a97269a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32601
47483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.3260147483
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.371255774
Short name T1753
Test name
Test status
Simulation time 182148283 ps
CPU time 0.8 seconds
Started Jul 21 06:55:19 PM PDT 24
Finished Jul 21 06:55:20 PM PDT 24
Peak memory 206696 kb
Host smart-3ec14f3f-5a09-41c0-8516-4d328a237857
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37125
5774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.371255774
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2352067082
Short name T73
Test name
Test status
Simulation time 325330520 ps
CPU time 1.22 seconds
Started Jul 21 06:55:22 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206636 kb
Host smart-b7577afe-4770-493d-a73f-38428b43faa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23520
67082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2352067082
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3183563686
Short name T1033
Test name
Test status
Simulation time 979003133 ps
CPU time 2.17 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:26 PM PDT 24
Peak memory 206796 kb
Host smart-08a7c02a-9a9c-4035-83d7-929393807243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31835
63686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3183563686
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.1132088878
Short name T2472
Test name
Test status
Simulation time 20204267493 ps
CPU time 34.01 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:57 PM PDT 24
Peak memory 206388 kb
Host smart-d0177ccd-8dd6-4bd7-a4aa-7f0be917e574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11320
88878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.1132088878
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.693612132
Short name T1383
Test name
Test status
Simulation time 406709589 ps
CPU time 1.25 seconds
Started Jul 21 06:55:20 PM PDT 24
Finished Jul 21 06:55:21 PM PDT 24
Peak memory 206668 kb
Host smart-f686945b-e06c-4fb1-978b-e19586af0998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69361
2132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.693612132
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.1859130660
Short name T1051
Test name
Test status
Simulation time 208136546 ps
CPU time 0.81 seconds
Started Jul 21 06:55:19 PM PDT 24
Finished Jul 21 06:55:20 PM PDT 24
Peak memory 206652 kb
Host smart-a06ca76f-a7c6-40f5-b236-b350b5d58bfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18591
30660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.1859130660
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2491807690
Short name T1553
Test name
Test status
Simulation time 71926780 ps
CPU time 0.68 seconds
Started Jul 21 06:55:19 PM PDT 24
Finished Jul 21 06:55:20 PM PDT 24
Peak memory 206680 kb
Host smart-ee5fba09-f5c6-4902-96b4-67597d838694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24918
07690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2491807690
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.720055218
Short name T1755
Test name
Test status
Simulation time 847434833 ps
CPU time 2.26 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:25 PM PDT 24
Peak memory 206304 kb
Host smart-cecf76ef-f6cf-4989-9c34-381173470c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72005
5218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.720055218
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.1096889807
Short name T2534
Test name
Test status
Simulation time 177192287 ps
CPU time 2.16 seconds
Started Jul 21 06:55:21 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206880 kb
Host smart-dbc25bf3-224b-42a3-9b40-2a805c06e53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10968
89807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.1096889807
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.3705823561
Short name T1329
Test name
Test status
Simulation time 214645731 ps
CPU time 0.89 seconds
Started Jul 21 06:55:29 PM PDT 24
Finished Jul 21 06:55:30 PM PDT 24
Peak memory 206588 kb
Host smart-04c850ab-8631-4654-a3ce-cae549e10c09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37058
23561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.3705823561
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.2967599820
Short name T2474
Test name
Test status
Simulation time 145690828 ps
CPU time 0.8 seconds
Started Jul 21 06:55:25 PM PDT 24
Finished Jul 21 06:55:27 PM PDT 24
Peak memory 206680 kb
Host smart-b5ef309a-1efd-4bd3-bc9a-f02cb60b780e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29675
99820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.2967599820
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.1891038194
Short name T684
Test name
Test status
Simulation time 251919507 ps
CPU time 1.03 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:55:29 PM PDT 24
Peak memory 206696 kb
Host smart-ded28b1b-a737-4102-8421-b42b09d168e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18910
38194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.1891038194
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.3146965891
Short name T1097
Test name
Test status
Simulation time 8005007451 ps
CPU time 76.84 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206852 kb
Host smart-2aa250a7-3b83-487c-8f87-420f7a2dc534
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3146965891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.3146965891
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.2668455483
Short name T1210
Test name
Test status
Simulation time 9219903020 ps
CPU time 35.74 seconds
Started Jul 21 06:55:24 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206964 kb
Host smart-a98d6202-c8e5-491d-8df9-425651606e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26684
55483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.2668455483
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.3495444351
Short name T1303
Test name
Test status
Simulation time 182563401 ps
CPU time 0.79 seconds
Started Jul 21 06:55:25 PM PDT 24
Finished Jul 21 06:55:26 PM PDT 24
Peak memory 206664 kb
Host smart-24a4087a-0ad4-476a-8dc7-002094399629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34954
44351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.3495444351
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.38729835
Short name T1645
Test name
Test status
Simulation time 23367431227 ps
CPU time 22.93 seconds
Started Jul 21 06:55:26 PM PDT 24
Finished Jul 21 06:55:49 PM PDT 24
Peak memory 206788 kb
Host smart-d582a2a0-c964-4bb7-8816-2b855a87e4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38729
835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.38729835
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.3513855525
Short name T1005
Test name
Test status
Simulation time 3303392209 ps
CPU time 4.03 seconds
Started Jul 21 06:55:24 PM PDT 24
Finished Jul 21 06:55:28 PM PDT 24
Peak memory 206748 kb
Host smart-440aa619-d360-455d-a6d3-774b5ae75ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35138
55525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.3513855525
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.642442838
Short name T2188
Test name
Test status
Simulation time 10209351372 ps
CPU time 78.39 seconds
Started Jul 21 06:55:27 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206924 kb
Host smart-de23a743-a0cf-4be9-a50f-2994e5a797f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64244
2838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.642442838
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.378365778
Short name T1722
Test name
Test status
Simulation time 5134534582 ps
CPU time 141.08 seconds
Started Jul 21 06:55:24 PM PDT 24
Finished Jul 21 06:57:45 PM PDT 24
Peak memory 206864 kb
Host smart-d0e1b650-19d5-4121-b3bb-0caed0335c98
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=378365778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.378365778
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.2634002567
Short name T2167
Test name
Test status
Simulation time 280285583 ps
CPU time 0.92 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206624 kb
Host smart-9db8f578-30c8-4eb6-a8bd-2acb341f9849
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2634002567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.2634002567
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.3725364126
Short name T1779
Test name
Test status
Simulation time 254630564 ps
CPU time 0.92 seconds
Started Jul 21 06:55:24 PM PDT 24
Finished Jul 21 06:55:25 PM PDT 24
Peak memory 206664 kb
Host smart-4c7e47ca-e6e7-4770-aad5-633464f82e25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37253
64126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.3725364126
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.2201026832
Short name T966
Test name
Test status
Simulation time 4969941897 ps
CPU time 134.05 seconds
Started Jul 21 06:55:24 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206912 kb
Host smart-ff3ff364-1aed-49ce-b94f-9cc2c10e7fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22010
26832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.2201026832
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.1622316218
Short name T2449
Test name
Test status
Simulation time 4884598140 ps
CPU time 135.32 seconds
Started Jul 21 06:55:25 PM PDT 24
Finished Jul 21 06:57:41 PM PDT 24
Peak memory 206876 kb
Host smart-32e24536-382c-4d59-a2f4-2405798f9ac0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1622316218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.1622316218
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.2901820999
Short name T1672
Test name
Test status
Simulation time 157521907 ps
CPU time 0.78 seconds
Started Jul 21 06:55:24 PM PDT 24
Finished Jul 21 06:55:25 PM PDT 24
Peak memory 206680 kb
Host smart-15f29cd6-5b7d-4885-b303-3329fc4da1e8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2901820999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.2901820999
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.698693544
Short name T601
Test name
Test status
Simulation time 169086506 ps
CPU time 0.82 seconds
Started Jul 21 06:55:26 PM PDT 24
Finished Jul 21 06:55:27 PM PDT 24
Peak memory 206672 kb
Host smart-41f7a7a0-bdf2-43bd-a6fd-e7a453e9299b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69869
3544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.698693544
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.3538334757
Short name T88
Test name
Test status
Simulation time 196405217 ps
CPU time 0.91 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:25 PM PDT 24
Peak memory 206652 kb
Host smart-b9c6ee42-019b-4ec6-b880-980175b68c34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35383
34757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.3538334757
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3878770051
Short name T2067
Test name
Test status
Simulation time 166911151 ps
CPU time 0.78 seconds
Started Jul 21 06:55:25 PM PDT 24
Finished Jul 21 06:55:26 PM PDT 24
Peak memory 206632 kb
Host smart-277e8b09-bb11-46db-a4fe-c687337db7d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38787
70051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3878770051
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.2692651954
Short name T872
Test name
Test status
Simulation time 193005852 ps
CPU time 0.85 seconds
Started Jul 21 06:55:29 PM PDT 24
Finished Jul 21 06:55:31 PM PDT 24
Peak memory 206644 kb
Host smart-0d2f273f-8bff-4148-bf39-768f2c94092d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26926
51954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.2692651954
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.4165876533
Short name T1959
Test name
Test status
Simulation time 155806180 ps
CPU time 0.77 seconds
Started Jul 21 06:55:23 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206632 kb
Host smart-272cda8f-12b6-42fc-b5a9-e2b00e0be243
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41658
76533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.4165876533
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.3284447231
Short name T1137
Test name
Test status
Simulation time 261608394 ps
CPU time 1.04 seconds
Started Jul 21 06:55:29 PM PDT 24
Finished Jul 21 06:55:31 PM PDT 24
Peak memory 206576 kb
Host smart-91893889-9ea9-4dbf-8940-0c92fa94dff7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3284447231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.3284447231
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.768877565
Short name T2014
Test name
Test status
Simulation time 182812273 ps
CPU time 0.78 seconds
Started Jul 21 06:55:29 PM PDT 24
Finished Jul 21 06:55:30 PM PDT 24
Peak memory 206500 kb
Host smart-d267759d-f1d5-45f0-b1cc-13401a522e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76887
7565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.768877565
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.4124356965
Short name T2631
Test name
Test status
Simulation time 35316782 ps
CPU time 0.64 seconds
Started Jul 21 06:55:26 PM PDT 24
Finished Jul 21 06:55:27 PM PDT 24
Peak memory 206632 kb
Host smart-0cca43d5-b851-487c-ab43-75dbeaba35e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41243
56965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.4124356965
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.3049898665
Short name T946
Test name
Test status
Simulation time 15028757501 ps
CPU time 33.87 seconds
Started Jul 21 06:55:25 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206976 kb
Host smart-d62518dc-9228-4667-bd96-afee75a10ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30498
98665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.3049898665
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.2475560832
Short name T1297
Test name
Test status
Simulation time 180362101 ps
CPU time 0.87 seconds
Started Jul 21 06:55:27 PM PDT 24
Finished Jul 21 06:55:28 PM PDT 24
Peak memory 206656 kb
Host smart-990181a3-8470-4e9a-a6c6-08b5476a3db7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24755
60832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.2475560832
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.2264410123
Short name T1145
Test name
Test status
Simulation time 178299391 ps
CPU time 0.86 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:55:29 PM PDT 24
Peak memory 206660 kb
Host smart-1a0454a7-729d-428e-9db4-6b7b3645c9a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644
10123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.2264410123
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.1720810194
Short name T662
Test name
Test status
Simulation time 264697624 ps
CPU time 0.92 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206660 kb
Host smart-999dbc27-c7c3-4daf-83c4-580e92938fc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17208
10194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.1720810194
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.2446490199
Short name T2406
Test name
Test status
Simulation time 158722715 ps
CPU time 0.83 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:55:29 PM PDT 24
Peak memory 206672 kb
Host smart-62558685-a084-4ac4-a972-4dd92a6a75f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24464
90199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.2446490199
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.1910976586
Short name T584
Test name
Test status
Simulation time 252334493 ps
CPU time 0.87 seconds
Started Jul 21 06:55:26 PM PDT 24
Finished Jul 21 06:55:28 PM PDT 24
Peak memory 206692 kb
Host smart-861e043c-ab1a-4346-bb4e-873fc74adfd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19109
76586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.1910976586
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.1345234842
Short name T1589
Test name
Test status
Simulation time 166049824 ps
CPU time 0.79 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:55:29 PM PDT 24
Peak memory 206652 kb
Host smart-b5083353-d3cf-47e7-ad45-69c997b93375
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13452
34842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.1345234842
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.608870655
Short name T1408
Test name
Test status
Simulation time 166406460 ps
CPU time 0.76 seconds
Started Jul 21 06:55:27 PM PDT 24
Finished Jul 21 06:55:28 PM PDT 24
Peak memory 206684 kb
Host smart-6b689ef2-59d9-471d-9af0-41ce6e21e619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60887
0655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.608870655
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.59618895
Short name T1793
Test name
Test status
Simulation time 230793031 ps
CPU time 0.96 seconds
Started Jul 21 06:55:29 PM PDT 24
Finished Jul 21 06:55:31 PM PDT 24
Peak memory 206600 kb
Host smart-13fa7bb4-ce7d-42ae-b375-8a83e7a053c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59618
895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.59618895
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.2486766379
Short name T2140
Test name
Test status
Simulation time 7044918396 ps
CPU time 47.77 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206924 kb
Host smart-ab92e13e-bdfe-45c0-bf63-23645ebe89eb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2486766379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.2486766379
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1181220151
Short name T2691
Test name
Test status
Simulation time 174615118 ps
CPU time 0.86 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206640 kb
Host smart-c727e96c-15fd-4552-a03c-05ef50b6a941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11812
20151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1181220151
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.617674554
Short name T999
Test name
Test status
Simulation time 158647803 ps
CPU time 0.82 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:55:29 PM PDT 24
Peak memory 206680 kb
Host smart-cffe7c53-0ed0-4b82-ae8e-be4915661330
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61767
4554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.617674554
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.4077471383
Short name T745
Test name
Test status
Simulation time 337324885 ps
CPU time 1.06 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:34 PM PDT 24
Peak memory 206648 kb
Host smart-2a8ee192-40b6-46de-a417-fedf5de0822e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40774
71383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.4077471383
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.3778101936
Short name T880
Test name
Test status
Simulation time 5590220591 ps
CPU time 163.27 seconds
Started Jul 21 06:55:26 PM PDT 24
Finished Jul 21 06:58:11 PM PDT 24
Peak memory 206868 kb
Host smart-a021dcd8-968a-409d-8f09-37d3ef0e50c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37781
01936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.3778101936
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.1438875562
Short name T813
Test name
Test status
Simulation time 51303862 ps
CPU time 0.67 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:55:45 PM PDT 24
Peak memory 206744 kb
Host smart-10f09f40-259f-4ecf-b6b4-e0fa50d87b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1438875562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.1438875562
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.3532316715
Short name T2256
Test name
Test status
Simulation time 3887692289 ps
CPU time 4.4 seconds
Started Jul 21 06:55:27 PM PDT 24
Finished Jul 21 06:55:32 PM PDT 24
Peak memory 206832 kb
Host smart-425e881a-3234-47c1-9afd-2ec42d16cf9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3532316715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.3532316715
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2657115644
Short name T2301
Test name
Test status
Simulation time 13368771306 ps
CPU time 13.27 seconds
Started Jul 21 06:55:31 PM PDT 24
Finished Jul 21 06:55:44 PM PDT 24
Peak memory 206936 kb
Host smart-77f63e2d-edb8-4202-8684-616d91cddc74
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2657115644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2657115644
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.382426586
Short name T1360
Test name
Test status
Simulation time 23422087793 ps
CPU time 24.45 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:55:53 PM PDT 24
Peak memory 206812 kb
Host smart-71d2dd47-0c12-445e-a507-d6ba4fd9372e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=382426586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.382426586
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.2125066990
Short name T2368
Test name
Test status
Simulation time 216168113 ps
CPU time 0.82 seconds
Started Jul 21 06:55:28 PM PDT 24
Finished Jul 21 06:55:29 PM PDT 24
Peak memory 206708 kb
Host smart-52a6413d-16f9-4383-b6a8-e2941cc29fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21250
66990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.2125066990
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3900519790
Short name T2624
Test name
Test status
Simulation time 169710124 ps
CPU time 0.77 seconds
Started Jul 21 06:55:29 PM PDT 24
Finished Jul 21 06:55:31 PM PDT 24
Peak memory 206664 kb
Host smart-902623c0-f48c-476f-ba18-2658ad1a5db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39005
19790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3900519790
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.120492891
Short name T474
Test name
Test status
Simulation time 525785275 ps
CPU time 1.53 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206704 kb
Host smart-3617b73c-0d35-4219-8431-6e8e01b79022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12049
2891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.120492891
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.2266780523
Short name T1686
Test name
Test status
Simulation time 1274122421 ps
CPU time 3.07 seconds
Started Jul 21 06:55:36 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206748 kb
Host smart-682f4545-cc8c-44ee-9e65-36213ba3d78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22667
80523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.2266780523
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.807903843
Short name T941
Test name
Test status
Simulation time 11033572870 ps
CPU time 21.84 seconds
Started Jul 21 06:55:35 PM PDT 24
Finished Jul 21 06:55:57 PM PDT 24
Peak memory 206880 kb
Host smart-fd2befd4-60c4-4a37-808c-337f58f1afea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80790
3843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.807903843
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.2128056590
Short name T1582
Test name
Test status
Simulation time 592563081 ps
CPU time 1.58 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206680 kb
Host smart-99394bca-6eec-4e6e-bcaf-84c2feb7be53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21280
56590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.2128056590
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.3909104014
Short name T948
Test name
Test status
Simulation time 136986755 ps
CPU time 0.72 seconds
Started Jul 21 06:55:37 PM PDT 24
Finished Jul 21 06:55:38 PM PDT 24
Peak memory 206684 kb
Host smart-aad763d6-fab8-448e-b861-6fdfadcddafe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39091
04014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.3909104014
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.2612127395
Short name T1254
Test name
Test status
Simulation time 36246709 ps
CPU time 0.68 seconds
Started Jul 21 06:55:34 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206656 kb
Host smart-36ddbb7f-9597-4d29-8d27-db6ec90d90ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26121
27395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.2612127395
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.459133725
Short name T1428
Test name
Test status
Simulation time 821336928 ps
CPU time 1.99 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:36 PM PDT 24
Peak memory 206772 kb
Host smart-bc9a93c6-8d63-4ac7-af63-9e822450f224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45913
3725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.459133725
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.1979142050
Short name T2065
Test name
Test status
Simulation time 195077597 ps
CPU time 1.32 seconds
Started Jul 21 06:55:33 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206752 kb
Host smart-c766306d-bf7d-4f8d-8d11-9ba9519703d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19791
42050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.1979142050
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.482262715
Short name T341
Test name
Test status
Simulation time 162217143 ps
CPU time 0.79 seconds
Started Jul 21 06:55:34 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206648 kb
Host smart-ff7d91a4-a50b-4992-9fb6-b8e60ab78b9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48226
2715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.482262715
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3431828264
Short name T767
Test name
Test status
Simulation time 143409324 ps
CPU time 0.77 seconds
Started Jul 21 06:55:34 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206708 kb
Host smart-c66ce83a-11a6-42ca-9909-ac837b40d094
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34318
28264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3431828264
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.3739329714
Short name T639
Test name
Test status
Simulation time 233550093 ps
CPU time 0.92 seconds
Started Jul 21 06:55:35 PM PDT 24
Finished Jul 21 06:55:36 PM PDT 24
Peak memory 206672 kb
Host smart-70e7d99e-2015-4c2b-b9f2-b1d16ee375ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37393
29714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.3739329714
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.2257409219
Short name T617
Test name
Test status
Simulation time 6451141960 ps
CPU time 51.06 seconds
Started Jul 21 06:55:35 PM PDT 24
Finished Jul 21 06:56:26 PM PDT 24
Peak memory 206900 kb
Host smart-c6a47b21-4f5a-4a0c-90fa-04a9755d44e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22574
09219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.2257409219
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3363193613
Short name T2520
Test name
Test status
Simulation time 205479497 ps
CPU time 0.91 seconds
Started Jul 21 06:55:37 PM PDT 24
Finished Jul 21 06:55:39 PM PDT 24
Peak memory 206668 kb
Host smart-2553ece0-3523-4b46-866b-0dda8b15c1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33631
93613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3363193613
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.1841985040
Short name T798
Test name
Test status
Simulation time 23334732501 ps
CPU time 23.97 seconds
Started Jul 21 06:55:35 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206804 kb
Host smart-890377bf-5903-4a8c-850f-c776329b33af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18419
85040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.1841985040
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.1188081633
Short name T2386
Test name
Test status
Simulation time 3358136816 ps
CPU time 4.42 seconds
Started Jul 21 06:55:39 PM PDT 24
Finished Jul 21 06:55:44 PM PDT 24
Peak memory 206744 kb
Host smart-ba6b291e-7502-463d-ad40-7e27ad8bfeb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11880
81633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.1188081633
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.1719980610
Short name T773
Test name
Test status
Simulation time 11641645917 ps
CPU time 304.93 seconds
Started Jul 21 06:55:34 PM PDT 24
Finished Jul 21 07:00:40 PM PDT 24
Peak memory 206976 kb
Host smart-6b899a0a-7fce-4bc8-a288-07ad1803d3e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17199
80610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.1719980610
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.352432880
Short name T165
Test name
Test status
Simulation time 5802830470 ps
CPU time 55.88 seconds
Started Jul 21 06:55:40 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206860 kb
Host smart-624f6bfe-5112-4721-a870-ad9597ae0efb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=352432880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.352432880
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.3694307244
Short name T2063
Test name
Test status
Simulation time 230840356 ps
CPU time 0.93 seconds
Started Jul 21 06:55:41 PM PDT 24
Finished Jul 21 06:55:42 PM PDT 24
Peak memory 206660 kb
Host smart-640e3e9e-1c01-41ff-beb0-5536dc64d2ce
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3694307244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.3694307244
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.2376681319
Short name T1736
Test name
Test status
Simulation time 199865025 ps
CPU time 0.91 seconds
Started Jul 21 06:55:38 PM PDT 24
Finished Jul 21 06:55:39 PM PDT 24
Peak memory 206684 kb
Host smart-6cbd7a80-1a04-4f4b-960e-2f5ee301904a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23766
81319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.2376681319
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3815828235
Short name T1487
Test name
Test status
Simulation time 5542101322 ps
CPU time 50.73 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:56:35 PM PDT 24
Peak memory 206872 kb
Host smart-1cbdd9dc-5b5b-474d-b158-e959b48b5e33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38158
28235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3815828235
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.1849911069
Short name T1115
Test name
Test status
Simulation time 5013256885 ps
CPU time 46.85 seconds
Started Jul 21 06:55:37 PM PDT 24
Finished Jul 21 06:56:24 PM PDT 24
Peak memory 206824 kb
Host smart-d884fe2f-a860-4188-aec7-0c8563e0a8e2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1849911069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.1849911069
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1569077995
Short name T705
Test name
Test status
Simulation time 158815964 ps
CPU time 0.78 seconds
Started Jul 21 06:55:38 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206660 kb
Host smart-c64a0002-31d1-40c9-8e0b-fd22ad09882f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1569077995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1569077995
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.533780364
Short name T1191
Test name
Test status
Simulation time 155209306 ps
CPU time 0.78 seconds
Started Jul 21 06:55:38 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206656 kb
Host smart-d00ddd09-33c7-4d2d-9788-d2b884ae6904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53378
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.533780364
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.2070286221
Short name T106
Test name
Test status
Simulation time 262274492 ps
CPU time 0.95 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206684 kb
Host smart-06c54751-d881-4a36-84f2-9d35113e1639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20702
86221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.2070286221
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.707247091
Short name T1657
Test name
Test status
Simulation time 181761165 ps
CPU time 0.84 seconds
Started Jul 21 06:55:38 PM PDT 24
Finished Jul 21 06:55:39 PM PDT 24
Peak memory 206664 kb
Host smart-b6d40815-76ef-41d6-9971-037d63f63471
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70724
7091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.707247091
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.494108139
Short name T1979
Test name
Test status
Simulation time 152157205 ps
CPU time 0.8 seconds
Started Jul 21 06:55:40 PM PDT 24
Finished Jul 21 06:55:41 PM PDT 24
Peak memory 206676 kb
Host smart-803bebc0-256b-4293-8db3-c0214dbffd31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49410
8139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.494108139
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.2335897406
Short name T2590
Test name
Test status
Simulation time 216810116 ps
CPU time 0.88 seconds
Started Jul 21 06:55:40 PM PDT 24
Finished Jul 21 06:55:41 PM PDT 24
Peak memory 206660 kb
Host smart-dd42db10-bedf-4644-a91e-d55abad28d2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23358
97406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.2335897406
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.886936135
Short name T2634
Test name
Test status
Simulation time 174707610 ps
CPU time 0.77 seconds
Started Jul 21 06:55:39 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206656 kb
Host smart-efe33796-b40a-41d4-a371-0c951aa6b9f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88693
6135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.886936135
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.1741123717
Short name T2161
Test name
Test status
Simulation time 228678253 ps
CPU time 0.97 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:55:46 PM PDT 24
Peak memory 206680 kb
Host smart-191479fe-4a74-4850-bf78-44d2a12ad7ef
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1741123717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.1741123717
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.4008244634
Short name T1177
Test name
Test status
Simulation time 156523366 ps
CPU time 0.83 seconds
Started Jul 21 06:55:41 PM PDT 24
Finished Jul 21 06:55:42 PM PDT 24
Peak memory 206688 kb
Host smart-1afbe533-e455-4014-8615-610c95cd0a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40082
44634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.4008244634
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.958480494
Short name T1570
Test name
Test status
Simulation time 45490987 ps
CPU time 0.73 seconds
Started Jul 21 06:55:38 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206676 kb
Host smart-2d7b4b42-2209-4d4b-ac56-14474d08209f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95848
0494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.958480494
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.642275994
Short name T943
Test name
Test status
Simulation time 20336084865 ps
CPU time 45.59 seconds
Started Jul 21 06:55:41 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206980 kb
Host smart-2fc0a516-68c1-4c88-8b65-45021cefe736
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64227
5994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.642275994
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2578248944
Short name T1040
Test name
Test status
Simulation time 170725112 ps
CPU time 0.78 seconds
Started Jul 21 06:55:39 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206680 kb
Host smart-82f2847d-320e-4854-80a3-7f026ef373d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25782
48944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2578248944
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.848239469
Short name T472
Test name
Test status
Simulation time 210002861 ps
CPU time 0.89 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:55:44 PM PDT 24
Peak memory 206676 kb
Host smart-7bbc6d9a-63c4-4d37-b6b7-a1d429a423a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84823
9469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.848239469
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.113026971
Short name T2042
Test name
Test status
Simulation time 158918453 ps
CPU time 0.78 seconds
Started Jul 21 06:55:40 PM PDT 24
Finished Jul 21 06:55:42 PM PDT 24
Peak memory 206656 kb
Host smart-12303054-8e63-4f4e-87f9-f21b0fc879c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11302
6971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.113026971
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.2447041189
Short name T1247
Test name
Test status
Simulation time 146708425 ps
CPU time 0.85 seconds
Started Jul 21 06:55:45 PM PDT 24
Finished Jul 21 06:55:47 PM PDT 24
Peak memory 206680 kb
Host smart-9e8c0a0c-5053-4e98-a2e7-689b08b5f305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24470
41189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.2447041189
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.4136379641
Short name T1505
Test name
Test status
Simulation time 219469598 ps
CPU time 0.9 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206656 kb
Host smart-79397a1a-a5d2-4ce5-a6af-4f49b04542da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41363
79641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.4136379641
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.1966186275
Short name T2619
Test name
Test status
Simulation time 175452289 ps
CPU time 0.77 seconds
Started Jul 21 06:55:38 PM PDT 24
Finished Jul 21 06:55:39 PM PDT 24
Peak memory 206704 kb
Host smart-507b5c98-15ad-4cba-819d-686428ede29f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19661
86275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.1966186275
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.1396788659
Short name T1742
Test name
Test status
Simulation time 202358286 ps
CPU time 0.87 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:55:45 PM PDT 24
Peak memory 206684 kb
Host smart-57dd0a8a-4b40-47a8-b552-3878348a6f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13967
88659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.1396788659
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.1259403089
Short name T144
Test name
Test status
Simulation time 243572387 ps
CPU time 0.97 seconds
Started Jul 21 06:55:39 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 206668 kb
Host smart-6c123cc7-d114-4af2-b76d-466ce3287119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12594
03089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.1259403089
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.1527251044
Short name T1587
Test name
Test status
Simulation time 6952291934 ps
CPU time 64.64 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206944 kb
Host smart-214fbd8a-0c38-4e76-89d2-20b4817679a0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1527251044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.1527251044
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.121425377
Short name T590
Test name
Test status
Simulation time 182254467 ps
CPU time 0.78 seconds
Started Jul 21 06:56:13 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206420 kb
Host smart-f4c05665-0f80-405d-a2df-048b76f379a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12142
5377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.121425377
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.4102322091
Short name T2443
Test name
Test status
Simulation time 151576420 ps
CPU time 0.77 seconds
Started Jul 21 06:55:40 PM PDT 24
Finished Jul 21 06:55:41 PM PDT 24
Peak memory 206680 kb
Host smart-a287f635-3985-4a9a-a175-d8cd51783ecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41023
22091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.4102322091
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2407120650
Short name T2513
Test name
Test status
Simulation time 1055978075 ps
CPU time 2.37 seconds
Started Jul 21 06:55:38 PM PDT 24
Finished Jul 21 06:55:41 PM PDT 24
Peak memory 206800 kb
Host smart-cf4c39f7-0a9b-4c9b-8747-6e63b5c739c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24071
20650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2407120650
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.1558480766
Short name T2388
Test name
Test status
Simulation time 4214566980 ps
CPU time 119.07 seconds
Started Jul 21 06:55:41 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206908 kb
Host smart-d887416b-384d-4438-80c9-7eb64c246cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15584
80766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.1558480766
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.2235470876
Short name T1151
Test name
Test status
Simulation time 36539735 ps
CPU time 0.67 seconds
Started Jul 21 06:55:53 PM PDT 24
Finished Jul 21 06:55:55 PM PDT 24
Peak memory 206712 kb
Host smart-28ae6411-f498-4f6d-bd37-0e6e9a332171
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2235470876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.2235470876
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.514883604
Short name T2405
Test name
Test status
Simulation time 3451324115 ps
CPU time 4.48 seconds
Started Jul 21 06:55:45 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206740 kb
Host smart-88c0e09e-72e0-4606-9117-d0f728fd1d46
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=514883604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.514883604
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1283902032
Short name T1133
Test name
Test status
Simulation time 13394205163 ps
CPU time 12.99 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:55:58 PM PDT 24
Peak memory 206920 kb
Host smart-161480e6-4d73-4fb4-b338-336da9a78560
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1283902032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1283902032
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.3161121512
Short name T630
Test name
Test status
Simulation time 23317471644 ps
CPU time 21.82 seconds
Started Jul 21 06:55:46 PM PDT 24
Finished Jul 21 06:56:08 PM PDT 24
Peak memory 206944 kb
Host smart-4ab7eec2-2968-46fc-9382-b03d96ba151c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3161121512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.3161121512
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.3490206166
Short name T1692
Test name
Test status
Simulation time 177741579 ps
CPU time 0.86 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:55:44 PM PDT 24
Peak memory 206708 kb
Host smart-15801b11-b350-4bf1-a4a8-e0867a42ed85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34902
06166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.3490206166
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.1422499078
Short name T441
Test name
Test status
Simulation time 146034418 ps
CPU time 0.79 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:55:45 PM PDT 24
Peak memory 206668 kb
Host smart-13921503-130e-46a5-895d-e6c258c9ae25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14224
99078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.1422499078
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.4099657770
Short name T379
Test name
Test status
Simulation time 241409084 ps
CPU time 0.97 seconds
Started Jul 21 06:55:46 PM PDT 24
Finished Jul 21 06:55:47 PM PDT 24
Peak memory 206652 kb
Host smart-90533240-ffe5-484e-a968-d676433e368c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40996
57770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.4099657770
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.2630151125
Short name T857
Test name
Test status
Simulation time 464500848 ps
CPU time 1.29 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:55:46 PM PDT 24
Peak memory 206688 kb
Host smart-bbe84817-7407-4725-bd02-575848b4dbb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26301
51125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.2630151125
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.520265695
Short name T686
Test name
Test status
Simulation time 7985943802 ps
CPU time 16.22 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206948 kb
Host smart-576cc423-075f-445d-98ec-c00c5486f9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52026
5695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.520265695
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.216957086
Short name T1787
Test name
Test status
Simulation time 468888684 ps
CPU time 1.48 seconds
Started Jul 21 06:55:46 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206684 kb
Host smart-6c509605-9cdf-4295-859c-424043c03347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21695
7086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.216957086
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.2908491376
Short name T1734
Test name
Test status
Simulation time 145460385 ps
CPU time 0.77 seconds
Started Jul 21 06:55:45 PM PDT 24
Finished Jul 21 06:55:46 PM PDT 24
Peak memory 206700 kb
Host smart-03b9984f-74a6-4dc7-b194-a483b0e6bfd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29084
91376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.2908491376
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.253907484
Short name T718
Test name
Test status
Simulation time 45484041 ps
CPU time 0.63 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:55:45 PM PDT 24
Peak memory 206668 kb
Host smart-13014de0-1887-4809-8a95-bcce7455a0ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25390
7484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.253907484
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.977891267
Short name T1948
Test name
Test status
Simulation time 760613727 ps
CPU time 1.9 seconds
Started Jul 21 06:55:45 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206804 kb
Host smart-26d5f00d-76b3-4eb0-979c-a6bb19ec092c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97789
1267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.977891267
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.438630968
Short name T824
Test name
Test status
Simulation time 164364815 ps
CPU time 1.4 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:55:47 PM PDT 24
Peak memory 206812 kb
Host smart-0e704318-6960-45e4-9e96-333294160124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43863
0968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.438630968
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.1405995810
Short name T1536
Test name
Test status
Simulation time 196457513 ps
CPU time 0.9 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206668 kb
Host smart-5efbe8de-3a4f-4ef0-92aa-58c5d274f514
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14059
95810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.1405995810
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.2382793861
Short name T467
Test name
Test status
Simulation time 157226152 ps
CPU time 0.76 seconds
Started Jul 21 06:55:45 PM PDT 24
Finished Jul 21 06:55:47 PM PDT 24
Peak memory 206676 kb
Host smart-b7072a61-dd4e-4923-aea2-d2019c239134
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23827
93861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.2382793861
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.994986958
Short name T951
Test name
Test status
Simulation time 157043365 ps
CPU time 0.77 seconds
Started Jul 21 06:55:42 PM PDT 24
Finished Jul 21 06:55:43 PM PDT 24
Peak memory 206624 kb
Host smart-04f52680-c91e-4e11-b3ef-4097691335fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99498
6958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.994986958
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.1792109784
Short name T2697
Test name
Test status
Simulation time 8215073339 ps
CPU time 217.72 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206868 kb
Host smart-b3655fe1-69d3-4670-8d00-9129a7893a6e
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1792109784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.1792109784
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.1594088021
Short name T245
Test name
Test status
Simulation time 7528481850 ps
CPU time 60.18 seconds
Started Jul 21 06:55:46 PM PDT 24
Finished Jul 21 06:56:47 PM PDT 24
Peak memory 206884 kb
Host smart-9608868a-28cf-4cf5-b77f-ed5fe93f3ecf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15940
88021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.1594088021
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.3505591123
Short name T2018
Test name
Test status
Simulation time 162983781 ps
CPU time 0.82 seconds
Started Jul 21 06:55:46 PM PDT 24
Finished Jul 21 06:55:47 PM PDT 24
Peak memory 206652 kb
Host smart-d56c3c3f-cce4-431d-8bdc-9e52f259990f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35055
91123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.3505591123
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.818659352
Short name T592
Test name
Test status
Simulation time 23349292898 ps
CPU time 27.77 seconds
Started Jul 21 06:55:45 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206732 kb
Host smart-b013a49c-def6-40a5-a97a-750f85679cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81865
9352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.818659352
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.2102823746
Short name T1954
Test name
Test status
Simulation time 3318532163 ps
CPU time 3.68 seconds
Started Jul 21 06:55:43 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206748 kb
Host smart-98df514d-793d-4a68-92f8-b4b30ea92aa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21028
23746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.2102823746
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.862170185
Short name T1718
Test name
Test status
Simulation time 11118426169 ps
CPU time 302.9 seconds
Started Jul 21 06:55:45 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206980 kb
Host smart-43a4b0f5-0048-4efc-a26d-5a28af44e04d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86217
0185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.862170185
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3968452403
Short name T1344
Test name
Test status
Simulation time 6354509204 ps
CPU time 187.44 seconds
Started Jul 21 06:55:44 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206904 kb
Host smart-03fdef90-c039-4a9b-b5e9-9f18b2fe252c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3968452403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3968452403
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3674140415
Short name T2208
Test name
Test status
Simulation time 254401867 ps
CPU time 0.88 seconds
Started Jul 21 06:55:46 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206652 kb
Host smart-9b480ea9-e6e5-4d26-b678-03771088f042
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3674140415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3674140415
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2965341816
Short name T1914
Test name
Test status
Simulation time 193098017 ps
CPU time 0.89 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206668 kb
Host smart-3c5e1465-79f2-4b48-b3a2-bc5aaa4b165f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29653
41816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2965341816
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.2338959335
Short name T1263
Test name
Test status
Simulation time 5405297389 ps
CPU time 146.3 seconds
Started Jul 21 06:55:50 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 206872 kb
Host smart-a1351e31-8c4f-47b5-9e1b-fb3ea5b42a59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23389
59335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.2338959335
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.668108361
Short name T2345
Test name
Test status
Simulation time 4436259220 ps
CPU time 125.98 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:57:54 PM PDT 24
Peak memory 206892 kb
Host smart-6f9f5c66-3739-4d75-902a-72fbe3dafd80
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=668108361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.668108361
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.3230701820
Short name T577
Test name
Test status
Simulation time 194070648 ps
CPU time 0.81 seconds
Started Jul 21 06:55:52 PM PDT 24
Finished Jul 21 06:55:53 PM PDT 24
Peak memory 206684 kb
Host smart-088af7b0-1280-4a4f-9024-e4f855862d92
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3230701820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.3230701820
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.4121242387
Short name T2438
Test name
Test status
Simulation time 185732406 ps
CPU time 0.79 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206632 kb
Host smart-dd578c0e-d208-4e41-ba15-b47c91000ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41212
42387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.4121242387
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.806464972
Short name T1837
Test name
Test status
Simulation time 187219492 ps
CPU time 0.84 seconds
Started Jul 21 06:55:49 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206660 kb
Host smart-a45b42e4-aa8d-4985-96ee-d61c00f3f988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80646
4972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.806464972
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.2775971220
Short name T336
Test name
Test status
Simulation time 162231723 ps
CPU time 0.82 seconds
Started Jul 21 06:55:50 PM PDT 24
Finished Jul 21 06:55:51 PM PDT 24
Peak memory 206692 kb
Host smart-9d470382-4695-4a59-b426-579ac3fdef69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27759
71220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.2775971220
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.3049788944
Short name T2533
Test name
Test status
Simulation time 188345513 ps
CPU time 0.82 seconds
Started Jul 21 06:55:49 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206704 kb
Host smart-38ba463c-749b-4bbc-9bc4-e0af7f868fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30497
88944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.3049788944
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.1904241154
Short name T1628
Test name
Test status
Simulation time 209152150 ps
CPU time 0.86 seconds
Started Jul 21 06:55:49 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206668 kb
Host smart-a30a9eb0-9988-4b7c-9227-2e315ebb1248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19042
41154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.1904241154
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1939822205
Short name T1548
Test name
Test status
Simulation time 226131898 ps
CPU time 0.95 seconds
Started Jul 21 06:55:48 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206680 kb
Host smart-4c2e1d8e-21be-4674-a811-be61a8ed799a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1939822205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1939822205
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.3243098395
Short name T1333
Test name
Test status
Simulation time 135599521 ps
CPU time 0.77 seconds
Started Jul 21 06:55:51 PM PDT 24
Finished Jul 21 06:55:52 PM PDT 24
Peak memory 206656 kb
Host smart-d7e53bda-6510-4fcf-856d-65f8050270bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32430
98395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.3243098395
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.2274588622
Short name T1890
Test name
Test status
Simulation time 56231331 ps
CPU time 0.7 seconds
Started Jul 21 06:55:50 PM PDT 24
Finished Jul 21 06:55:51 PM PDT 24
Peak memory 206656 kb
Host smart-2c7a11ef-02c5-4cd6-806e-789942efee2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22745
88622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.2274588622
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.254691456
Short name T242
Test name
Test status
Simulation time 8778310866 ps
CPU time 18.75 seconds
Started Jul 21 06:55:48 PM PDT 24
Finished Jul 21 06:56:08 PM PDT 24
Peak memory 206952 kb
Host smart-7c1f7224-4833-42a6-810d-16f67bbad340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25469
1456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.254691456
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.3180294797
Short name T1786
Test name
Test status
Simulation time 193461203 ps
CPU time 0.86 seconds
Started Jul 21 06:55:48 PM PDT 24
Finished Jul 21 06:55:49 PM PDT 24
Peak memory 206664 kb
Host smart-1fa4370d-0e5a-44d9-b648-4260157d1bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31802
94797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.3180294797
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2021232809
Short name T1898
Test name
Test status
Simulation time 293453518 ps
CPU time 0.99 seconds
Started Jul 21 06:55:50 PM PDT 24
Finished Jul 21 06:55:51 PM PDT 24
Peak memory 206680 kb
Host smart-e656a9b9-a041-42d7-ab54-6929ae8b8c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20212
32809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2021232809
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.3082570541
Short name T2157
Test name
Test status
Simulation time 201095451 ps
CPU time 0.87 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206692 kb
Host smart-23686d85-d429-4b61-9bad-424da7f8337f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30825
70541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.3082570541
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.451733168
Short name T2028
Test name
Test status
Simulation time 161533258 ps
CPU time 0.88 seconds
Started Jul 21 06:55:49 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206640 kb
Host smart-27614b49-9704-4978-8b72-25023f8f49c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45173
3168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.451733168
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.2288045255
Short name T2577
Test name
Test status
Simulation time 175990218 ps
CPU time 0.88 seconds
Started Jul 21 06:55:47 PM PDT 24
Finished Jul 21 06:55:49 PM PDT 24
Peak memory 206688 kb
Host smart-a389dc1a-5d25-4455-a488-cd2491044355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22880
45255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.2288045255
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.2945129377
Short name T392
Test name
Test status
Simulation time 156973908 ps
CPU time 0.79 seconds
Started Jul 21 06:55:52 PM PDT 24
Finished Jul 21 06:55:53 PM PDT 24
Peak memory 206684 kb
Host smart-82d988ce-7d17-4a4d-82fe-c3be85182352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29451
29377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.2945129377
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3301656949
Short name T1359
Test name
Test status
Simulation time 200788954 ps
CPU time 1 seconds
Started Jul 21 06:55:49 PM PDT 24
Finished Jul 21 06:55:50 PM PDT 24
Peak memory 206652 kb
Host smart-9e5c92b1-09aa-4a55-9769-7e3e0a222c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33016
56949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3301656949
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.294513280
Short name T761
Test name
Test status
Simulation time 4158949705 ps
CPU time 115.74 seconds
Started Jul 21 06:55:49 PM PDT 24
Finished Jul 21 06:57:45 PM PDT 24
Peak memory 206868 kb
Host smart-81d1dc59-6081-4d4c-a761-7c4aab88d69c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=294513280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.294513280
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.3444175846
Short name T90
Test name
Test status
Simulation time 192272719 ps
CPU time 0.83 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:02 PM PDT 24
Peak memory 206648 kb
Host smart-b0d6cc1b-5340-4c34-8676-5eed75150429
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34441
75846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.3444175846
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.4090493454
Short name T2567
Test name
Test status
Simulation time 196638800 ps
CPU time 0.83 seconds
Started Jul 21 06:55:53 PM PDT 24
Finished Jul 21 06:55:54 PM PDT 24
Peak memory 206680 kb
Host smart-e10a4952-eb69-41bf-b638-b255eab7c749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40904
93454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.4090493454
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.3931922674
Short name T19
Test name
Test status
Simulation time 948395589 ps
CPU time 2.14 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:04 PM PDT 24
Peak memory 206772 kb
Host smart-e39db54e-0ad4-43f8-8540-7e0eb6e034d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39319
22674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.3931922674
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3547512546
Short name T1906
Test name
Test status
Simulation time 4571044351 ps
CPU time 129.03 seconds
Started Jul 21 06:55:54 PM PDT 24
Finished Jul 21 06:58:04 PM PDT 24
Peak memory 206892 kb
Host smart-8330c66f-8708-4b7a-8b1a-e9883a3d2380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35475
12546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3547512546
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.3416445778
Short name T179
Test name
Test status
Simulation time 38001280 ps
CPU time 0.68 seconds
Started Jul 21 06:56:02 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206736 kb
Host smart-206dabfd-4ac4-498c-a699-d2533854f27c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3416445778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.3416445778
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.2752899579
Short name T1605
Test name
Test status
Simulation time 3784158742 ps
CPU time 4.54 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206904 kb
Host smart-9791a477-266e-49dd-aeb3-dd63bd76aa93
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2752899579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.2752899579
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.578297853
Short name T520
Test name
Test status
Simulation time 13395902282 ps
CPU time 13.59 seconds
Started Jul 21 06:55:55 PM PDT 24
Finished Jul 21 06:56:09 PM PDT 24
Peak memory 206932 kb
Host smart-f6b5a8fb-6f37-4373-9a26-27f3fecf3a8f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=578297853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.578297853
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.318355442
Short name T6
Test name
Test status
Simulation time 23343921129 ps
CPU time 23.88 seconds
Started Jul 21 06:55:54 PM PDT 24
Finished Jul 21 06:56:18 PM PDT 24
Peak memory 206820 kb
Host smart-9e0cf87c-dba9-4cf4-9076-91f092e49655
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=318355442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.318355442
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.1057555111
Short name T1038
Test name
Test status
Simulation time 176203016 ps
CPU time 0.83 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:55:58 PM PDT 24
Peak memory 206684 kb
Host smart-d3607243-f9f5-44d6-98d4-6f73860f3f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10575
55111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.1057555111
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.2519269816
Short name T685
Test name
Test status
Simulation time 162694977 ps
CPU time 0.79 seconds
Started Jul 21 06:55:53 PM PDT 24
Finished Jul 21 06:55:55 PM PDT 24
Peak memory 206704 kb
Host smart-524b32ba-bf7c-4207-8aa4-6aec9f9ff106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25192
69816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.2519269816
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.4048318112
Short name T1871
Test name
Test status
Simulation time 292583197 ps
CPU time 1.12 seconds
Started Jul 21 06:55:52 PM PDT 24
Finished Jul 21 06:55:54 PM PDT 24
Peak memory 206700 kb
Host smart-acac74bf-3a75-4859-92fa-a9d216b3d685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40483
18112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.4048318112
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.3308679525
Short name T2663
Test name
Test status
Simulation time 869256487 ps
CPU time 2.1 seconds
Started Jul 21 06:55:54 PM PDT 24
Finished Jul 21 06:55:57 PM PDT 24
Peak memory 206768 kb
Host smart-2fb658bf-5d66-4717-9d4b-a947452b42a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33086
79525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.3308679525
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.1707562158
Short name T2115
Test name
Test status
Simulation time 13544017412 ps
CPU time 23.95 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206920 kb
Host smart-8b2a6fa2-36be-4e91-a579-036180d2688a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
62158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.1707562158
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.231806563
Short name T2215
Test name
Test status
Simulation time 497019835 ps
CPU time 1.42 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:55:58 PM PDT 24
Peak memory 206664 kb
Host smart-f59cf8f1-9d6b-4a5d-911a-32b9741207b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23180
6563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.231806563
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.848241865
Short name T1864
Test name
Test status
Simulation time 145570673 ps
CPU time 0.82 seconds
Started Jul 21 06:55:54 PM PDT 24
Finished Jul 21 06:55:56 PM PDT 24
Peak memory 206668 kb
Host smart-9038427d-d114-4298-a8e6-b73c7369eb2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84824
1865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.848241865
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.1603791430
Short name T1513
Test name
Test status
Simulation time 62546227 ps
CPU time 0.7 seconds
Started Jul 21 06:55:53 PM PDT 24
Finished Jul 21 06:55:54 PM PDT 24
Peak memory 206660 kb
Host smart-9d7f3616-8d37-4323-9fa2-266844d14157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16037
91430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.1603791430
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.2519930491
Short name T2705
Test name
Test status
Simulation time 847043366 ps
CPU time 1.95 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206812 kb
Host smart-de50926e-d97f-4a91-8093-5f120a06affc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25199
30491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.2519930491
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2070937463
Short name T1401
Test name
Test status
Simulation time 200283412 ps
CPU time 1.26 seconds
Started Jul 21 06:55:55 PM PDT 24
Finished Jul 21 06:55:57 PM PDT 24
Peak memory 206800 kb
Host smart-b3617305-8194-4496-9f08-84afbd8d4033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20709
37463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2070937463
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3169269522
Short name T2741
Test name
Test status
Simulation time 154610644 ps
CPU time 0.78 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:03 PM PDT 24
Peak memory 206648 kb
Host smart-beb92719-f407-41f0-85f0-9fc08dc72819
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31692
69522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3169269522
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.1451241132
Short name T1847
Test name
Test status
Simulation time 185242363 ps
CPU time 0.81 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:02 PM PDT 24
Peak memory 206644 kb
Host smart-b25c2c1e-9b92-4fdf-bfad-869b2c20e608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14512
41132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.1451241132
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.2583123188
Short name T1291
Test name
Test status
Simulation time 174951478 ps
CPU time 0.85 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:03 PM PDT 24
Peak memory 206648 kb
Host smart-53801187-e667-4f3e-b4ea-e83a5df89f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25831
23188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.2583123188
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_iso_retraction.862165507
Short name T844
Test name
Test status
Simulation time 9440715759 ps
CPU time 80.5 seconds
Started Jul 21 06:55:54 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 206940 kb
Host smart-272fec78-906b-4b92-97c4-19672eb9c491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86216
5507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_iso_retraction.862165507
Directory /workspace/16.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.3043007820
Short name T1212
Test name
Test status
Simulation time 192905143 ps
CPU time 0.87 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206688 kb
Host smart-61990e55-a92d-43fe-8a82-1f295432670c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30430
07820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.3043007820
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.180941924
Short name T949
Test name
Test status
Simulation time 23294796838 ps
CPU time 24.81 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:56:23 PM PDT 24
Peak memory 206768 kb
Host smart-f3db2e90-4541-44df-9419-09ee162d5c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18094
1924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.180941924
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.77847575
Short name T1527
Test name
Test status
Simulation time 3381731429 ps
CPU time 4.13 seconds
Started Jul 21 06:55:55 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206744 kb
Host smart-a1deeb9f-549b-4678-9430-dbf1e71effc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77847
575 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.77847575
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.978619383
Short name T2262
Test name
Test status
Simulation time 7683443982 ps
CPU time 53.31 seconds
Started Jul 21 06:55:55 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206952 kb
Host smart-368ed5c8-aa8c-4397-a6a0-7e08950c3cbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97861
9383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.978619383
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.600504434
Short name T557
Test name
Test status
Simulation time 6177859121 ps
CPU time 171.79 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206884 kb
Host smart-330393f8-b289-4728-82f8-04615d4499b2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=600504434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.600504434
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1760823118
Short name T1321
Test name
Test status
Simulation time 249528964 ps
CPU time 0.92 seconds
Started Jul 21 06:55:52 PM PDT 24
Finished Jul 21 06:55:54 PM PDT 24
Peak memory 206688 kb
Host smart-d2fd1753-aa4a-4899-97c6-b46880d332d0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1760823118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1760823118
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.2910097914
Short name T795
Test name
Test status
Simulation time 244938413 ps
CPU time 0.94 seconds
Started Jul 21 06:55:53 PM PDT 24
Finished Jul 21 06:55:55 PM PDT 24
Peak memory 206672 kb
Host smart-8462d0a5-04c6-4f6f-b7f2-629d824d3727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29100
97914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.2910097914
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.4254457238
Short name T1603
Test name
Test status
Simulation time 4165145959 ps
CPU time 39.24 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:56:37 PM PDT 24
Peak memory 206748 kb
Host smart-0a666893-8229-4b1d-a9fc-ba9f66f3c0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42544
57238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.4254457238
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.3580494229
Short name T1741
Test name
Test status
Simulation time 3464978703 ps
CPU time 95.21 seconds
Started Jul 21 06:55:59 PM PDT 24
Finished Jul 21 06:57:36 PM PDT 24
Peak memory 206872 kb
Host smart-e5e99e87-fc16-41c2-89eb-5d78798d3ee6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3580494229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.3580494229
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.1145743111
Short name T1601
Test name
Test status
Simulation time 152269720 ps
CPU time 0.77 seconds
Started Jul 21 06:55:58 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206696 kb
Host smart-2af1659b-573f-4872-a342-58078941a102
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1145743111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.1145743111
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3518237630
Short name T618
Test name
Test status
Simulation time 179292298 ps
CPU time 0.79 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206660 kb
Host smart-9954c31a-ab55-4d02-aa09-d6497c392e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35182
37630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3518237630
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.2714386401
Short name T1963
Test name
Test status
Simulation time 199547169 ps
CPU time 0.86 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:04 PM PDT 24
Peak memory 206696 kb
Host smart-b5d8836c-7e77-48e4-86f8-3525efa2e448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27143
86401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.2714386401
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.2807531518
Short name T1463
Test name
Test status
Simulation time 197314209 ps
CPU time 0.84 seconds
Started Jul 21 06:56:02 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206664 kb
Host smart-4fb0b939-9dd0-4fd2-9418-4291ce9140e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28075
31518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.2807531518
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.324704693
Short name T532
Test name
Test status
Simulation time 153153288 ps
CPU time 0.81 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206688 kb
Host smart-91400783-f824-4365-b16c-9d221fc2f650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32470
4693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.324704693
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.3598843374
Short name T572
Test name
Test status
Simulation time 209457963 ps
CPU time 1 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206652 kb
Host smart-67ab85cd-2289-45a5-a3f2-d28bd1935413
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3598843374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.3598843374
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.309405248
Short name T1549
Test name
Test status
Simulation time 149125848 ps
CPU time 0.76 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206660 kb
Host smart-1d8e4972-2ef8-4f0b-9d0c-8803706d59f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30940
5248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.309405248
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.4279726749
Short name T31
Test name
Test status
Simulation time 54247627 ps
CPU time 0.7 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:03 PM PDT 24
Peak memory 206652 kb
Host smart-4042b916-a2e1-4506-bb6e-4c8bc65797e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42797
26749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.4279726749
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.49323824
Short name T1249
Test name
Test status
Simulation time 7696541863 ps
CPU time 17.88 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206908 kb
Host smart-dc83e288-f97c-43c9-bcc2-a409710b3636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49323
824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.49323824
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1664443737
Short name T2043
Test name
Test status
Simulation time 163790108 ps
CPU time 0.86 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:03 PM PDT 24
Peak memory 206700 kb
Host smart-8ef249aa-42d7-4028-b499-7553fcd03a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16644
43737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1664443737
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.1712152683
Short name T2638
Test name
Test status
Simulation time 152128658 ps
CPU time 0.78 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206692 kb
Host smart-4ad66a1e-e89a-414e-a6fb-02adfd9dd3c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17121
52683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.1712152683
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.315036627
Short name T2250
Test name
Test status
Simulation time 206369638 ps
CPU time 0.86 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:04 PM PDT 24
Peak memory 206696 kb
Host smart-a01b50cf-0ca1-4e69-8dfe-bb7f37122731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31503
6627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.315036627
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3193641675
Short name T1878
Test name
Test status
Simulation time 185187899 ps
CPU time 0.9 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:55:58 PM PDT 24
Peak memory 206668 kb
Host smart-518c4167-0108-468e-8d19-325aeba86b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31936
41675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3193641675
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.3196465500
Short name T1146
Test name
Test status
Simulation time 198588526 ps
CPU time 0.9 seconds
Started Jul 21 06:55:59 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206640 kb
Host smart-24922dff-1d7d-4f03-b81e-4a1f355f777b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31964
65500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.3196465500
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.3921883260
Short name T624
Test name
Test status
Simulation time 185921991 ps
CPU time 0.82 seconds
Started Jul 21 06:55:59 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206664 kb
Host smart-6572450a-5321-4700-98be-e2abf71eea91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39218
83260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.3921883260
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.99379628
Short name T2211
Test name
Test status
Simulation time 198129357 ps
CPU time 0.84 seconds
Started Jul 21 06:55:59 PM PDT 24
Finished Jul 21 06:56:02 PM PDT 24
Peak memory 206636 kb
Host smart-621b5619-c7ef-4188-882e-2e06933bc681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99379
628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.99379628
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.595587299
Short name T2661
Test name
Test status
Simulation time 231795814 ps
CPU time 0.98 seconds
Started Jul 21 06:55:59 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206744 kb
Host smart-f40dbe0f-1121-4e6b-83dd-80396a58cab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59558
7299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.595587299
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.3350008466
Short name T1752
Test name
Test status
Simulation time 165896505 ps
CPU time 0.81 seconds
Started Jul 21 06:55:59 PM PDT 24
Finished Jul 21 06:56:02 PM PDT 24
Peak memory 206636 kb
Host smart-29dbff19-abad-4bf7-b029-d1c56b9c7834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33500
08466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.3350008466
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.2545171070
Short name T1935
Test name
Test status
Simulation time 195185817 ps
CPU time 0.91 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:04 PM PDT 24
Peak memory 206672 kb
Host smart-8faaf074-3b10-45bb-a699-88e9f8e9409b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25451
71070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.2545171070
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.2994012144
Short name T2402
Test name
Test status
Simulation time 944200900 ps
CPU time 2.33 seconds
Started Jul 21 06:55:59 PM PDT 24
Finished Jul 21 06:56:02 PM PDT 24
Peak memory 206784 kb
Host smart-ca5a82b2-f75f-41f0-9a91-1abf7134d149
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29940
12144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.2994012144
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2208118277
Short name T742
Test name
Test status
Simulation time 6225193121 ps
CPU time 46.05 seconds
Started Jul 21 06:55:58 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206952 kb
Host smart-241c705b-55f5-440a-a9df-d3f7cd1d6a76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22081
18277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2208118277
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.2062060951
Short name T2655
Test name
Test status
Simulation time 34944448 ps
CPU time 0.68 seconds
Started Jul 21 06:56:12 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206708 kb
Host smart-68cb970d-b9ea-47d0-9ec8-0eebd70426b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2062060951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.2062060951
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.1885336515
Short name T7
Test name
Test status
Simulation time 3523359634 ps
CPU time 4.85 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:07 PM PDT 24
Peak memory 206888 kb
Host smart-2ccadf0f-2f65-4f7d-8d00-255a85244c0d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1885336515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.1885336515
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3259558852
Short name T1485
Test name
Test status
Simulation time 13381117884 ps
CPU time 13.9 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206828 kb
Host smart-e67e01f6-3e1f-4ca0-abe6-4b75b276a762
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3259558852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3259558852
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.2996065357
Short name T1310
Test name
Test status
Simulation time 23364696606 ps
CPU time 24.07 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:28 PM PDT 24
Peak memory 206752 kb
Host smart-36771017-2519-446f-9259-76c9e568ecc7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2996065357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.2996065357
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.2428008801
Short name T430
Test name
Test status
Simulation time 148053588 ps
CPU time 0.77 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206664 kb
Host smart-9d864b23-5554-42a8-98a0-3986c73e4124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24280
08801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.2428008801
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.1350403610
Short name T354
Test name
Test status
Simulation time 143650558 ps
CPU time 0.81 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206672 kb
Host smart-162afeb1-e0c5-4cee-be9e-70c902b55971
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13504
03610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.1350403610
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.2929988172
Short name T2547
Test name
Test status
Simulation time 488551867 ps
CPU time 1.47 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:03 PM PDT 24
Peak memory 206652 kb
Host smart-4a2b6e14-4f8e-4bfb-80b2-75c41b0c6b22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29299
88172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.2929988172
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.1513249283
Short name T1308
Test name
Test status
Simulation time 1081612036 ps
CPU time 2.24 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:04 PM PDT 24
Peak memory 206784 kb
Host smart-a4b18f68-90c9-4ce6-8078-62570e6ea96b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15132
49283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.1513249283
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1811627053
Short name T1082
Test name
Test status
Simulation time 7274583840 ps
CPU time 14.46 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:16 PM PDT 24
Peak memory 207048 kb
Host smart-06de8ea9-e644-4971-9648-cdd7a0e36dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18116
27053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1811627053
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.938865178
Short name T2200
Test name
Test status
Simulation time 516716732 ps
CPU time 1.48 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:06 PM PDT 24
Peak memory 206688 kb
Host smart-2ef1a977-94db-4aec-b03e-7103d2c27526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93886
5178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.938865178
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.3652085146
Short name T1526
Test name
Test status
Simulation time 141109424 ps
CPU time 0.79 seconds
Started Jul 21 06:56:07 PM PDT 24
Finished Jul 21 06:56:08 PM PDT 24
Peak memory 206700 kb
Host smart-95b3bc3b-56ef-4677-a7af-20d1623b1241
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36520
85146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.3652085146
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.1158752802
Short name T1604
Test name
Test status
Simulation time 44269771 ps
CPU time 0.67 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206616 kb
Host smart-73c69d3d-209c-4789-befc-faaaec64a97b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11587
52802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.1158752802
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.4131857087
Short name T1776
Test name
Test status
Simulation time 878383786 ps
CPU time 2.26 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:06 PM PDT 24
Peak memory 206752 kb
Host smart-c9607a47-c033-4734-abb2-a1cf1739ef94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41318
57087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.4131857087
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.2327140372
Short name T175
Test name
Test status
Simulation time 178815456 ps
CPU time 1.39 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:04 PM PDT 24
Peak memory 206820 kb
Host smart-4907e2cf-9a48-45fc-90e4-4418370bd46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23271
40372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.2327140372
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.827955816
Short name T2012
Test name
Test status
Simulation time 294179469 ps
CPU time 1.03 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:03 PM PDT 24
Peak memory 206624 kb
Host smart-d5589f7d-00e8-4ea4-be57-ddc3d545eb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82795
5816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.827955816
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.500250135
Short name T445
Test name
Test status
Simulation time 138251473 ps
CPU time 0.78 seconds
Started Jul 21 06:56:02 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206648 kb
Host smart-1c05c80d-c4b5-4912-9c87-cc370d5df54b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50025
0135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.500250135
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.814756042
Short name T1147
Test name
Test status
Simulation time 188238763 ps
CPU time 0.92 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206668 kb
Host smart-c80d92c7-9ef2-41a4-b9d8-91b2412600f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81475
6042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.814756042
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.3742844247
Short name T644
Test name
Test status
Simulation time 8070123619 ps
CPU time 222.43 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:59:45 PM PDT 24
Peak memory 206904 kb
Host smart-d38e1135-8ca5-4668-9f41-2d8cc5ec1f0a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3742844247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.3742844247
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.452654437
Short name T1124
Test name
Test status
Simulation time 8061673219 ps
CPU time 68.79 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:57:16 PM PDT 24
Peak memory 206956 kb
Host smart-93ae228d-dced-41f7-abe5-5e5b20976a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45265
4437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.452654437
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.3162040309
Short name T330
Test name
Test status
Simulation time 236036882 ps
CPU time 1.03 seconds
Started Jul 21 06:56:00 PM PDT 24
Finished Jul 21 06:56:03 PM PDT 24
Peak memory 206668 kb
Host smart-8eb3938b-0a09-4a30-a20c-5a06d3070443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31620
40309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.3162040309
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.202475210
Short name T2374
Test name
Test status
Simulation time 23337557064 ps
CPU time 23.62 seconds
Started Jul 21 06:56:02 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206788 kb
Host smart-3caca20b-31f9-463a-9e1c-75017b464ebc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20247
5210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.202475210
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.2340771646
Short name T1778
Test name
Test status
Simulation time 3344780641 ps
CPU time 4 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:56:11 PM PDT 24
Peak memory 206768 kb
Host smart-f5f98b7e-7356-491e-8df1-5def67f8b999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23407
71646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.2340771646
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.1286827590
Short name T75
Test name
Test status
Simulation time 12286982528 ps
CPU time 341.05 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 07:01:44 PM PDT 24
Peak memory 206944 kb
Host smart-7c8ed967-2362-4c05-bd47-6e35b0bbb045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12868
27590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.1286827590
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.1030696616
Short name T2025
Test name
Test status
Simulation time 4896159760 ps
CPU time 33.14 seconds
Started Jul 21 06:56:01 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206900 kb
Host smart-c85fadc0-c0fd-4555-8f3a-1f28dbe9c48c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1030696616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.1030696616
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.912305326
Short name T1280
Test name
Test status
Simulation time 262525971 ps
CPU time 1.08 seconds
Started Jul 21 06:56:03 PM PDT 24
Finished Jul 21 06:56:05 PM PDT 24
Peak memory 206800 kb
Host smart-088e059e-6a4d-4cf0-8567-0fcda5be83f8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=912305326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.912305326
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.1739104514
Short name T957
Test name
Test status
Simulation time 191737274 ps
CPU time 0.81 seconds
Started Jul 21 06:56:05 PM PDT 24
Finished Jul 21 06:56:07 PM PDT 24
Peak memory 206664 kb
Host smart-d0904aeb-fc6c-4dda-bf72-3074b7dd75f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17391
04514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.1739104514
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.887274425
Short name T2517
Test name
Test status
Simulation time 4614330971 ps
CPU time 128.04 seconds
Started Jul 21 06:56:08 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 206856 kb
Host smart-1b831a8b-71ba-44ce-9e96-5a0eb8925af8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88727
4425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.887274425
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.3207899749
Short name T974
Test name
Test status
Simulation time 4929771504 ps
CPU time 134.34 seconds
Started Jul 21 06:56:07 PM PDT 24
Finished Jul 21 06:58:22 PM PDT 24
Peak memory 206876 kb
Host smart-d34e2a12-0ae6-4cde-9037-601c5e665d02
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3207899749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.3207899749
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1952878071
Short name T784
Test name
Test status
Simulation time 161763167 ps
CPU time 0.84 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:56:07 PM PDT 24
Peak memory 206680 kb
Host smart-3cdda71f-7c23-4f91-ad40-11dc4c72b3cf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1952878071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1952878071
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1935396296
Short name T2676
Test name
Test status
Simulation time 146640021 ps
CPU time 0.73 seconds
Started Jul 21 06:56:08 PM PDT 24
Finished Jul 21 06:56:09 PM PDT 24
Peak memory 206696 kb
Host smart-bb2db749-df10-4bca-9e85-0f4889bbfc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19353
96296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1935396296
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.3575284027
Short name T1882
Test name
Test status
Simulation time 152904555 ps
CPU time 0.8 seconds
Started Jul 21 06:56:04 PM PDT 24
Finished Jul 21 06:56:06 PM PDT 24
Peak memory 206704 kb
Host smart-c7c4f0d2-e8c9-44be-aa8e-d1991f39a634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35752
84027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.3575284027
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.178058893
Short name T752
Test name
Test status
Simulation time 241991240 ps
CPU time 0.87 seconds
Started Jul 21 06:56:09 PM PDT 24
Finished Jul 21 06:56:10 PM PDT 24
Peak memory 206668 kb
Host smart-63015492-f8d7-400c-8c2e-3d11189d012e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17805
8893 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.178058893
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.4134326148
Short name T1172
Test name
Test status
Simulation time 147557149 ps
CPU time 0.77 seconds
Started Jul 21 06:56:07 PM PDT 24
Finished Jul 21 06:56:08 PM PDT 24
Peak memory 206672 kb
Host smart-5b02ece4-0ee9-4963-a5b1-dfdc05c1a7fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41343
26148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.4134326148
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3294800596
Short name T141
Test name
Test status
Simulation time 154453295 ps
CPU time 0.76 seconds
Started Jul 21 06:56:05 PM PDT 24
Finished Jul 21 06:56:06 PM PDT 24
Peak memory 206664 kb
Host smart-2718fb86-4503-4e17-8b50-52d9e4fd4f78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32948
00596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3294800596
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.772586164
Short name T460
Test name
Test status
Simulation time 223878437 ps
CPU time 0.92 seconds
Started Jul 21 06:56:07 PM PDT 24
Finished Jul 21 06:56:09 PM PDT 24
Peak memory 206672 kb
Host smart-11904ae2-1d7f-4a6a-9abd-6e3dad03f8e9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=772586164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.772586164
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.2492016600
Short name T839
Test name
Test status
Simulation time 183623265 ps
CPU time 0.79 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:56:07 PM PDT 24
Peak memory 206672 kb
Host smart-3c8fc311-c42b-4be5-9e2f-2e0ad86c5a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24920
16600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.2492016600
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.476323840
Short name T2102
Test name
Test status
Simulation time 129007005 ps
CPU time 0.74 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:56:07 PM PDT 24
Peak memory 206644 kb
Host smart-a007773b-bc4b-4865-b79a-74e5d9a6faa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47632
3840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.476323840
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.368114315
Short name T2463
Test name
Test status
Simulation time 9218613252 ps
CPU time 23.02 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:56:30 PM PDT 24
Peak memory 206964 kb
Host smart-03d09e8c-ee04-4fce-b301-f4d260ded77e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811
4315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.368114315
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.1418547840
Short name T806
Test name
Test status
Simulation time 206376493 ps
CPU time 0.86 seconds
Started Jul 21 06:56:08 PM PDT 24
Finished Jul 21 06:56:10 PM PDT 24
Peak memory 206668 kb
Host smart-7b04e081-bc65-4c69-8acb-2dcdbd2f5a92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14185
47840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.1418547840
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3420181921
Short name T1691
Test name
Test status
Simulation time 268129520 ps
CPU time 0.98 seconds
Started Jul 21 06:56:07 PM PDT 24
Finished Jul 21 06:56:08 PM PDT 24
Peak memory 206668 kb
Host smart-39eec199-4912-40a7-80c1-48e914c1d6ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34201
81921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3420181921
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.2184898214
Short name T1809
Test name
Test status
Simulation time 228846023 ps
CPU time 0.88 seconds
Started Jul 21 06:56:06 PM PDT 24
Finished Jul 21 06:56:07 PM PDT 24
Peak memory 206652 kb
Host smart-3e929439-c821-4ca6-8ee4-a67731278aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21848
98214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.2184898214
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.3436655288
Short name T582
Test name
Test status
Simulation time 191023623 ps
CPU time 0.9 seconds
Started Jul 21 06:56:12 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206632 kb
Host smart-0f384ccf-a213-42c4-ab50-d369fad8baa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34366
55288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.3436655288
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2917276600
Short name T536
Test name
Test status
Simulation time 217813417 ps
CPU time 0.84 seconds
Started Jul 21 06:56:11 PM PDT 24
Finished Jul 21 06:56:12 PM PDT 24
Peak memory 206692 kb
Host smart-5220fed7-445f-473b-a40b-e374b2c0485b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29172
76600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2917276600
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.448163648
Short name T2700
Test name
Test status
Simulation time 146925944 ps
CPU time 0.79 seconds
Started Jul 21 06:56:13 PM PDT 24
Finished Jul 21 06:56:15 PM PDT 24
Peak memory 206648 kb
Host smart-e2ecf81f-5ebe-47b3-8b96-820c5a3e8523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44816
3648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.448163648
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.528092889
Short name T2607
Test name
Test status
Simulation time 240597596 ps
CPU time 0.85 seconds
Started Jul 21 06:56:12 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206660 kb
Host smart-c4c62d54-c259-4856-bba8-1bc7ca273fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52809
2889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.528092889
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.2562951103
Short name T1651
Test name
Test status
Simulation time 257422378 ps
CPU time 0.91 seconds
Started Jul 21 06:56:13 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206684 kb
Host smart-bf1107f6-dfe6-4744-8eeb-ee6ab52c7604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25629
51103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.2562951103
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.3766571541
Short name T2508
Test name
Test status
Simulation time 7093605111 ps
CPU time 201.68 seconds
Started Jul 21 06:56:10 PM PDT 24
Finished Jul 21 06:59:32 PM PDT 24
Peak memory 206900 kb
Host smart-28ef4d18-518c-4a6c-8be3-ed164d5838b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3766571541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.3766571541
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.2213305404
Short name T664
Test name
Test status
Simulation time 183543597 ps
CPU time 0.79 seconds
Started Jul 21 06:56:10 PM PDT 24
Finished Jul 21 06:56:11 PM PDT 24
Peak memory 206608 kb
Host smart-e87570c2-6051-48bb-9f64-fdb268a0c4ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
05404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.2213305404
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.3163629950
Short name T497
Test name
Test status
Simulation time 183810367 ps
CPU time 0.86 seconds
Started Jul 21 06:56:16 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206676 kb
Host smart-f4d3fb17-fdbc-43f6-99a4-9dca9d4c12b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31636
29950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.3163629950
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.1485175267
Short name T1766
Test name
Test status
Simulation time 1267373283 ps
CPU time 2.72 seconds
Started Jul 21 06:56:14 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206788 kb
Host smart-70eb8515-dd16-4e65-ae3c-8d3e6b47e1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14851
75267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.1485175267
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2703143856
Short name T1516
Test name
Test status
Simulation time 6251338589 ps
CPU time 168.89 seconds
Started Jul 21 06:56:12 PM PDT 24
Finished Jul 21 06:59:02 PM PDT 24
Peak memory 206932 kb
Host smart-5b2feb51-6908-44c8-ae4d-575edf57168b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27031
43856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2703143856
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.1942278624
Short name T694
Test name
Test status
Simulation time 40916620 ps
CPU time 0.68 seconds
Started Jul 21 06:56:20 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206728 kb
Host smart-2362a0aa-23a4-4984-8c80-ca63bcfb2fef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1942278624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.1942278624
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.669423922
Short name T1937
Test name
Test status
Simulation time 3983467338 ps
CPU time 5.64 seconds
Started Jul 21 06:56:11 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206808 kb
Host smart-06c0069f-5a5a-4a98-a2f3-2d334e680bb2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=669423922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.669423922
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.67573565
Short name T1044
Test name
Test status
Simulation time 13333336032 ps
CPU time 12.43 seconds
Started Jul 21 06:56:11 PM PDT 24
Finished Jul 21 06:56:23 PM PDT 24
Peak memory 206784 kb
Host smart-7b62d5bb-1736-4893-ba1c-9b02ed9b3062
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=67573565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.67573565
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.1158830514
Short name T2145
Test name
Test status
Simulation time 23363159621 ps
CPU time 28.59 seconds
Started Jul 21 06:56:12 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206800 kb
Host smart-b0f203c1-6324-4eb6-8953-a04d607d94e9
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1158830514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.1158830514
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.2379915127
Short name T2703
Test name
Test status
Simulation time 157997851 ps
CPU time 0.8 seconds
Started Jul 21 06:56:13 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206652 kb
Host smart-99491058-b11a-4d3f-a2ae-b96d1152fae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23799
15127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.2379915127
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.2589853946
Short name T2675
Test name
Test status
Simulation time 161564507 ps
CPU time 0.8 seconds
Started Jul 21 06:56:13 PM PDT 24
Finished Jul 21 06:56:14 PM PDT 24
Peak memory 206656 kb
Host smart-0e57c8bc-82aa-4ece-a349-3c16aea14653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25898
53946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.2589853946
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.2749979832
Short name T2268
Test name
Test status
Simulation time 615388958 ps
CPU time 1.99 seconds
Started Jul 21 06:56:11 PM PDT 24
Finished Jul 21 06:56:13 PM PDT 24
Peak memory 206792 kb
Host smart-0c2abada-a219-4bef-8efc-120cb877dde1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27499
79832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.2749979832
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.1571338289
Short name T672
Test name
Test status
Simulation time 1071215905 ps
CPU time 2.33 seconds
Started Jul 21 06:56:12 PM PDT 24
Finished Jul 21 06:56:15 PM PDT 24
Peak memory 206748 kb
Host smart-323c8154-5b17-471d-b976-4181edae2a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15713
38289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.1571338289
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.2530758414
Short name T2098
Test name
Test status
Simulation time 23273512608 ps
CPU time 51.88 seconds
Started Jul 21 06:56:14 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206912 kb
Host smart-5f1aa71f-9fcf-4f9a-8fe8-d3c31a19b9b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25307
58414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.2530758414
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.284334518
Short name T2446
Test name
Test status
Simulation time 457118282 ps
CPU time 1.43 seconds
Started Jul 21 06:56:14 PM PDT 24
Finished Jul 21 06:56:16 PM PDT 24
Peak memory 206668 kb
Host smart-212fe4a3-280e-4767-ab06-2d9ced9824df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28433
4518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.284334518
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.127010778
Short name T2143
Test name
Test status
Simulation time 169417164 ps
CPU time 0.85 seconds
Started Jul 21 06:56:20 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206680 kb
Host smart-a6b11802-1ec0-4c2e-a4d2-27b9c58f6592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12701
0778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.127010778
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.137875631
Short name T1575
Test name
Test status
Simulation time 46760517 ps
CPU time 0.73 seconds
Started Jul 21 06:56:16 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206672 kb
Host smart-39636b19-2592-480e-afc7-ec75606adf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13787
5631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.137875631
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.669130159
Short name T367
Test name
Test status
Simulation time 981504057 ps
CPU time 2.33 seconds
Started Jul 21 06:56:17 PM PDT 24
Finished Jul 21 06:56:20 PM PDT 24
Peak memory 206784 kb
Host smart-9d03d0e4-b7a3-418e-a1b4-dff92800e5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66913
0159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.669130159
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.1517182829
Short name T548
Test name
Test status
Simulation time 185535612 ps
CPU time 1.77 seconds
Started Jul 21 06:56:14 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206824 kb
Host smart-66882029-5197-4920-a754-794b2da5af5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15171
82829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.1517182829
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.473459137
Short name T327
Test name
Test status
Simulation time 248210035 ps
CPU time 0.91 seconds
Started Jul 21 06:56:20 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206672 kb
Host smart-99c033fe-6665-4712-a148-04ee7d3a6e14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47345
9137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.473459137
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.1980622909
Short name T2022
Test name
Test status
Simulation time 134020799 ps
CPU time 0.75 seconds
Started Jul 21 06:56:15 PM PDT 24
Finished Jul 21 06:56:16 PM PDT 24
Peak memory 206652 kb
Host smart-05e79fdb-dbf2-4782-a853-041f323bf0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19806
22909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.1980622909
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.2606595984
Short name T2753
Test name
Test status
Simulation time 219553175 ps
CPU time 0.91 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:56:41 PM PDT 24
Peak memory 206668 kb
Host smart-2e51680a-72d1-4aef-9385-78e087245988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26065
95984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.2606595984
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_invalid_sync.2482062422
Short name T212
Test name
Test status
Simulation time 8705472871 ps
CPU time 82.81 seconds
Started Jul 21 06:56:16 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206932 kb
Host smart-a85cb3cf-0dd5-4b22-bf82-15641f1ffebe
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2482062422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_invalid_sync.2482062422
Directory /workspace/18.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.2069804029
Short name T437
Test name
Test status
Simulation time 200683761 ps
CPU time 0.89 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206660 kb
Host smart-59de8cfd-a3c3-4fe4-b4e3-3de674f3e2b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20698
04029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.2069804029
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1903562752
Short name T1497
Test name
Test status
Simulation time 23323233892 ps
CPU time 22.23 seconds
Started Jul 21 06:56:16 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 206804 kb
Host smart-9a0143a9-3819-45ac-9278-a130eaaa5cfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19035
62752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1903562752
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.222968617
Short name T1869
Test name
Test status
Simulation time 3350216698 ps
CPU time 4.62 seconds
Started Jul 21 06:56:20 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206748 kb
Host smart-51580acd-ed5f-413d-a1ce-7581162378bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22296
8617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.222968617
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.780153829
Short name T2395
Test name
Test status
Simulation time 8708057875 ps
CPU time 64.58 seconds
Started Jul 21 06:56:16 PM PDT 24
Finished Jul 21 06:57:21 PM PDT 24
Peak memory 206956 kb
Host smart-07280de7-0380-4611-88d5-24d0f53b33c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78015
3829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.780153829
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.1049279576
Short name T1430
Test name
Test status
Simulation time 4589801341 ps
CPU time 133.76 seconds
Started Jul 21 06:56:15 PM PDT 24
Finished Jul 21 06:58:29 PM PDT 24
Peak memory 206876 kb
Host smart-cc20f732-eaa3-4005-9e7a-1540d9d53129
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1049279576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.1049279576
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.1770373379
Short name T310
Test name
Test status
Simulation time 230501195 ps
CPU time 0.87 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:19 PM PDT 24
Peak memory 206656 kb
Host smart-2d096e49-ba2f-407a-858f-ba14b38f131e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1770373379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.1770373379
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.214076045
Short name T1442
Test name
Test status
Simulation time 191892664 ps
CPU time 0.89 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:20 PM PDT 24
Peak memory 206724 kb
Host smart-15280fea-ea63-43ff-987b-ece4828d9fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21407
6045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.214076045
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.1611431486
Short name T2092
Test name
Test status
Simulation time 3128947959 ps
CPU time 21.64 seconds
Started Jul 21 06:56:17 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206900 kb
Host smart-19fd94d7-ee0b-4194-8a71-bd578a841412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16114
31486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.1611431486
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.1972237198
Short name T1366
Test name
Test status
Simulation time 3705120671 ps
CPU time 105.82 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:58:04 PM PDT 24
Peak memory 206824 kb
Host smart-f87b1f05-65ba-4d55-be8d-fe7b460c66c2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1972237198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.1972237198
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.290697493
Short name T383
Test name
Test status
Simulation time 192163371 ps
CPU time 0.81 seconds
Started Jul 21 06:56:20 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206676 kb
Host smart-75e4d4a5-e5f9-4b35-b8a5-9c809af7c7c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=290697493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.290697493
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.1611520057
Short name T1420
Test name
Test status
Simulation time 166215317 ps
CPU time 0.76 seconds
Started Jul 21 06:56:17 PM PDT 24
Finished Jul 21 06:56:19 PM PDT 24
Peak memory 206624 kb
Host smart-d2fc7594-a3e0-424b-9948-d801c1de3f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16115
20057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.1611520057
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.3501516599
Short name T1936
Test name
Test status
Simulation time 173239668 ps
CPU time 0.87 seconds
Started Jul 21 06:56:17 PM PDT 24
Finished Jul 21 06:56:18 PM PDT 24
Peak memory 206652 kb
Host smart-ebe5664c-233f-4647-aa07-7bc6d98ee862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35015
16599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.3501516599
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.128460368
Short name T852
Test name
Test status
Simulation time 157485051 ps
CPU time 0.78 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:19 PM PDT 24
Peak memory 206664 kb
Host smart-a5876648-e976-4122-9e1b-ed84ed108c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12846
0368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.128460368
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.2829137168
Short name T495
Test name
Test status
Simulation time 194166979 ps
CPU time 0.87 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206644 kb
Host smart-b24bf060-be4c-4a0b-bad6-1f085a231c55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28291
37168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.2829137168
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.1585700091
Short name T870
Test name
Test status
Simulation time 152923176 ps
CPU time 0.78 seconds
Started Jul 21 06:56:22 PM PDT 24
Finished Jul 21 06:56:24 PM PDT 24
Peak memory 206668 kb
Host smart-dd814dc1-6bbe-4038-aa33-a0889467456b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15857
00091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.1585700091
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.1666078696
Short name T2052
Test name
Test status
Simulation time 243854846 ps
CPU time 0.96 seconds
Started Jul 21 06:56:15 PM PDT 24
Finished Jul 21 06:56:16 PM PDT 24
Peak memory 206668 kb
Host smart-421ebde5-695e-4d3b-99b3-e227e66a3c3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1666078696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.1666078696
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.3805462703
Short name T36
Test name
Test status
Simulation time 136921956 ps
CPU time 0.79 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:26 PM PDT 24
Peak memory 206652 kb
Host smart-a95c5555-86b1-487b-986a-9e5f577564d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38054
62703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.3805462703
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.242498314
Short name T26
Test name
Test status
Simulation time 43302891 ps
CPU time 0.67 seconds
Started Jul 21 06:56:16 PM PDT 24
Finished Jul 21 06:56:17 PM PDT 24
Peak memory 206680 kb
Host smart-9edc3d1a-4196-476f-ae04-4fc21fd878ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24249
8314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.242498314
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.2766224807
Short name T918
Test name
Test status
Simulation time 22350230906 ps
CPU time 47.29 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:57:13 PM PDT 24
Peak memory 215148 kb
Host smart-878d8ae0-6876-431f-aeb3-6b26aed6184e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27662
24807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.2766224807
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.1903642261
Short name T2642
Test name
Test status
Simulation time 178581253 ps
CPU time 0.78 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206680 kb
Host smart-bcfd40d0-adb3-4a66-9117-43c031885d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19036
42261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.1903642261
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.977449114
Short name T768
Test name
Test status
Simulation time 225270667 ps
CPU time 0.89 seconds
Started Jul 21 06:56:17 PM PDT 24
Finished Jul 21 06:56:18 PM PDT 24
Peak memory 206700 kb
Host smart-62f03186-7a98-4719-a6e4-6657d1f90e27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97744
9114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.977449114
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.3427941804
Short name T596
Test name
Test status
Simulation time 205684079 ps
CPU time 0.84 seconds
Started Jul 21 06:56:21 PM PDT 24
Finished Jul 21 06:56:22 PM PDT 24
Peak memory 206660 kb
Host smart-1538360d-c170-41d9-9933-6049dadff8ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34279
41804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.3427941804
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.3792648646
Short name T1065
Test name
Test status
Simulation time 215874829 ps
CPU time 0.88 seconds
Started Jul 21 06:56:23 PM PDT 24
Finished Jul 21 06:56:24 PM PDT 24
Peak memory 206780 kb
Host smart-c8d057db-5795-4b82-b318-f4d047ba39c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37926
48646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.3792648646
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.3803376803
Short name T412
Test name
Test status
Simulation time 199357555 ps
CPU time 0.8 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:56:21 PM PDT 24
Peak memory 206652 kb
Host smart-2ee3fdc8-bbf8-4ae3-b299-953162d07cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38033
76803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.3803376803
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.2316912929
Short name T1887
Test name
Test status
Simulation time 159654058 ps
CPU time 0.78 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:20 PM PDT 24
Peak memory 206652 kb
Host smart-1e9b8e9a-79c5-4976-9739-7381b4704825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23169
12929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.2316912929
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3018233937
Short name T896
Test name
Test status
Simulation time 182312835 ps
CPU time 0.78 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:20 PM PDT 24
Peak memory 206672 kb
Host smart-c92bab1c-fcaf-4385-93c8-0e42614fb530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30182
33937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3018233937
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.1256532295
Short name T828
Test name
Test status
Simulation time 271112607 ps
CPU time 0.95 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:20 PM PDT 24
Peak memory 206600 kb
Host smart-69f105cd-94a9-48ae-b201-189ead55497e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12565
32295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.1256532295
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.2440165904
Short name T1872
Test name
Test status
Simulation time 6345405149 ps
CPU time 175.83 seconds
Started Jul 21 06:56:20 PM PDT 24
Finished Jul 21 06:59:16 PM PDT 24
Peak memory 206896 kb
Host smart-6d9d23e1-89c8-49a9-832a-dd5cfdb72b36
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2440165904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.2440165904
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.657470423
Short name T2706
Test name
Test status
Simulation time 156397205 ps
CPU time 0.77 seconds
Started Jul 21 06:56:21 PM PDT 24
Finished Jul 21 06:56:22 PM PDT 24
Peak memory 206768 kb
Host smart-2de09994-f7f6-4ad3-9332-7fe3a969470a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65747
0423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.657470423
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.2487124625
Short name T2559
Test name
Test status
Simulation time 186887195 ps
CPU time 0.86 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:20 PM PDT 24
Peak memory 206668 kb
Host smart-bd57e5ef-84bb-45c9-ac78-948fa757c1d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
24625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.2487124625
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.65132198
Short name T466
Test name
Test status
Simulation time 1139741131 ps
CPU time 2.37 seconds
Started Jul 21 06:56:21 PM PDT 24
Finished Jul 21 06:56:23 PM PDT 24
Peak memory 206832 kb
Host smart-10186b75-48ef-4445-95e2-984eccc456cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65132
198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.65132198
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2812541038
Short name T1469
Test name
Test status
Simulation time 3173817915 ps
CPU time 93.54 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206888 kb
Host smart-73cdcaf3-cc08-4a80-8a23-e3354a9b4616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
41038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2812541038
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.2772892881
Short name T547
Test name
Test status
Simulation time 35921514 ps
CPU time 0.67 seconds
Started Jul 21 06:56:30 PM PDT 24
Finished Jul 21 06:56:31 PM PDT 24
Peak memory 206708 kb
Host smart-12ab4c8b-37d8-4dc5-a513-e58841ae56bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2772892881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.2772892881
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.2475792436
Short name T12
Test name
Test status
Simulation time 4037212002 ps
CPU time 4.77 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206880 kb
Host smart-ccfa5ee3-6f7e-4184-b24a-1aa3c8bc4f87
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2475792436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.2475792436
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1645407344
Short name T2261
Test name
Test status
Simulation time 13378045800 ps
CPU time 11.73 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:56:31 PM PDT 24
Peak memory 206940 kb
Host smart-b058a37a-f1e1-41c1-bda1-2f3d8905b8b4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1645407344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1645407344
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.1542822059
Short name T1204
Test name
Test status
Simulation time 23398957947 ps
CPU time 23.74 seconds
Started Jul 21 06:56:21 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206808 kb
Host smart-60055866-6590-4bde-ac6b-91bcb54c3edc
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1542822059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.1542822059
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.1649871150
Short name T681
Test name
Test status
Simulation time 174647229 ps
CPU time 0.79 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:20 PM PDT 24
Peak memory 206684 kb
Host smart-e6ddb760-ad19-45ca-8532-b30e050a3026
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16498
71150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.1649871150
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.3904906184
Short name T431
Test name
Test status
Simulation time 156295137 ps
CPU time 0.81 seconds
Started Jul 21 06:56:21 PM PDT 24
Finished Jul 21 06:56:22 PM PDT 24
Peak memory 206664 kb
Host smart-8b9dd413-e3dc-418d-a807-4004f07c8f8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39049
06184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.3904906184
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.1931202805
Short name T2302
Test name
Test status
Simulation time 448783718 ps
CPU time 1.45 seconds
Started Jul 21 06:56:20 PM PDT 24
Finished Jul 21 06:56:22 PM PDT 24
Peak memory 206660 kb
Host smart-80f79452-914f-40bb-b2e8-bc85fc4c7000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19312
02805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.1931202805
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3731187822
Short name T565
Test name
Test status
Simulation time 848323527 ps
CPU time 2.15 seconds
Started Jul 21 06:56:19 PM PDT 24
Finished Jul 21 06:56:22 PM PDT 24
Peak memory 206768 kb
Host smart-080b7ae6-7c6b-43fc-ba69-b3b0ab16bfff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37311
87822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3731187822
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.3259628363
Short name T1719
Test name
Test status
Simulation time 8061155322 ps
CPU time 15.69 seconds
Started Jul 21 06:56:18 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206900 kb
Host smart-a3d635af-1970-43e8-b4e3-3615ed965b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32596
28363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.3259628363
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.836412197
Short name T1414
Test name
Test status
Simulation time 437708057 ps
CPU time 1.52 seconds
Started Jul 21 06:56:26 PM PDT 24
Finished Jul 21 06:56:28 PM PDT 24
Peak memory 206772 kb
Host smart-6b3632eb-11df-463c-a4a6-a5ae56d5748f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83641
2197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.836412197
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.3557213314
Short name T910
Test name
Test status
Simulation time 161004638 ps
CPU time 0.83 seconds
Started Jul 21 06:56:22 PM PDT 24
Finished Jul 21 06:56:24 PM PDT 24
Peak memory 206664 kb
Host smart-f56eb0f7-6339-44c9-8a49-1e506d958a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35572
13314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.3557213314
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.2910828339
Short name T1394
Test name
Test status
Simulation time 35646960 ps
CPU time 0.65 seconds
Started Jul 21 06:56:22 PM PDT 24
Finished Jul 21 06:56:23 PM PDT 24
Peak memory 206668 kb
Host smart-ea97199b-451d-4119-b5a1-5e0abdc352cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29108
28339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.2910828339
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.2262844985
Short name T567
Test name
Test status
Simulation time 831185336 ps
CPU time 2.21 seconds
Started Jul 21 06:56:23 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206792 kb
Host smart-91466c93-1a9a-4eda-b797-c50c045d33b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22628
44985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.2262844985
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.3786770554
Short name T765
Test name
Test status
Simulation time 199636135 ps
CPU time 2.16 seconds
Started Jul 21 06:56:22 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206800 kb
Host smart-49bf3f1a-0678-4ef1-b0d4-0c129bf0bb1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37867
70554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.3786770554
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.771298653
Short name T2592
Test name
Test status
Simulation time 272247737 ps
CPU time 0.9 seconds
Started Jul 21 06:56:23 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206644 kb
Host smart-b1116768-6f8d-4c6d-82e3-a5135f3ccaf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77129
8653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.771298653
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2722787227
Short name T2569
Test name
Test status
Simulation time 164391845 ps
CPU time 0.8 seconds
Started Jul 21 06:56:22 PM PDT 24
Finished Jul 21 06:56:24 PM PDT 24
Peak memory 206656 kb
Host smart-e0bbdeb4-32bb-4d13-a272-d27c42db847d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27227
87227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2722787227
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.2027005
Short name T1324
Test name
Test status
Simulation time 189760375 ps
CPU time 0.87 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206664 kb
Host smart-ae5abda1-0003-4b78-af10-79a747e2f481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20270
05 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.2027005
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.1147428460
Short name T1533
Test name
Test status
Simulation time 6564798173 ps
CPU time 19.06 seconds
Started Jul 21 06:56:26 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206860 kb
Host smart-aaf623e1-57da-4ec4-b1c3-a2c0ab89a21b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11474
28460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.1147428460
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.3602802495
Short name T2587
Test name
Test status
Simulation time 195988293 ps
CPU time 0.86 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206660 kb
Host smart-ed79db3d-e8af-4dc1-b792-2483ad20f159
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36028
02495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.3602802495
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.933203944
Short name T316
Test name
Test status
Simulation time 23401362738 ps
CPU time 24.43 seconds
Started Jul 21 06:56:23 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206800 kb
Host smart-4ac12747-50ce-4e74-af1c-8098ba6eff24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93320
3944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.933203944
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.1316012209
Short name T981
Test name
Test status
Simulation time 3314510941 ps
CPU time 3.72 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:56:29 PM PDT 24
Peak memory 206748 kb
Host smart-4b91e7a2-d813-4996-919e-b9fc46e9ce7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13160
12209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.1316012209
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.1630794315
Short name T523
Test name
Test status
Simulation time 8097929675 ps
CPU time 231.4 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 07:00:17 PM PDT 24
Peak memory 206940 kb
Host smart-5a1d53dd-1e06-4de2-bb71-8bc42a15b5b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
94315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.1630794315
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.3827018885
Short name T1411
Test name
Test status
Simulation time 6962769069 ps
CPU time 193.24 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:59:38 PM PDT 24
Peak memory 206876 kb
Host smart-33fa8def-c897-45dc-b626-d9970e80e8ba
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3827018885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.3827018885
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.2554506128
Short name T2367
Test name
Test status
Simulation time 241219125 ps
CPU time 0.99 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206660 kb
Host smart-ff26b63a-3bbd-449e-9ca9-c843f70cf09e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2554506128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.2554506128
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.130211302
Short name T848
Test name
Test status
Simulation time 199399037 ps
CPU time 0.87 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206652 kb
Host smart-5144bffd-3ac5-45ed-a8c8-75583b125dd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13021
1302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.130211302
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.406662865
Short name T2041
Test name
Test status
Simulation time 4145665381 ps
CPU time 40.05 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206912 kb
Host smart-d1832fa7-df6a-407f-9020-9ad969db317b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40666
2865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.406662865
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.1864542043
Short name T1563
Test name
Test status
Simulation time 3805726866 ps
CPU time 25.76 seconds
Started Jul 21 06:56:26 PM PDT 24
Finished Jul 21 06:56:52 PM PDT 24
Peak memory 206856 kb
Host smart-fcbd1105-fbf5-4c81-9c6a-6986db2d6b6f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1864542043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.1864542043
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.541689172
Short name T313
Test name
Test status
Simulation time 153975336 ps
CPU time 0.79 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:26 PM PDT 24
Peak memory 206672 kb
Host smart-6ee8b31e-c6d2-49f0-9d51-fb0c92870099
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=541689172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.541689172
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.822494459
Short name T1748
Test name
Test status
Simulation time 209507166 ps
CPU time 0.88 seconds
Started Jul 21 06:56:26 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206696 kb
Host smart-5469b90e-4367-45a5-9c94-0af10e461764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82249
4459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.822494459
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3206567125
Short name T103
Test name
Test status
Simulation time 295570093 ps
CPU time 0.9 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206780 kb
Host smart-f1f3c3cc-8fdb-44a1-901b-868edc982083
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
67125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3206567125
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.4277638001
Short name T405
Test name
Test status
Simulation time 167480792 ps
CPU time 0.79 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206664 kb
Host smart-c1e8806b-d30c-40e0-9348-6cf745d00fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42776
38001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.4277638001
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.1904484522
Short name T2236
Test name
Test status
Simulation time 170766459 ps
CPU time 0.83 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:30 PM PDT 24
Peak memory 206692 kb
Host smart-5e9161f3-b7cf-420d-ac53-da8537bc0249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19044
84522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.1904484522
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.642566081
Short name T1775
Test name
Test status
Simulation time 156362025 ps
CPU time 0.78 seconds
Started Jul 21 06:56:26 PM PDT 24
Finished Jul 21 06:56:28 PM PDT 24
Peak memory 206700 kb
Host smart-5d2e6769-7c39-433b-adcb-3261c26dc96a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64256
6081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.642566081
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1283255432
Short name T1585
Test name
Test status
Simulation time 177702837 ps
CPU time 0.82 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206656 kb
Host smart-2a9b1c48-7d18-4d57-bc5a-7ea0fd8a5b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12832
55432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1283255432
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3736181202
Short name T2711
Test name
Test status
Simulation time 246026258 ps
CPU time 0.92 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:30 PM PDT 24
Peak memory 206696 kb
Host smart-82e0a361-64ed-4f82-80ed-790f15d149f4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3736181202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3736181202
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.3480709708
Short name T375
Test name
Test status
Simulation time 160780492 ps
CPU time 0.74 seconds
Started Jul 21 06:56:24 PM PDT 24
Finished Jul 21 06:56:25 PM PDT 24
Peak memory 206772 kb
Host smart-1f522fb4-a7d3-40cc-8a32-9d7613a762b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34807
09708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.3480709708
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.868318664
Short name T1392
Test name
Test status
Simulation time 47257829 ps
CPU time 0.68 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206644 kb
Host smart-558d47c2-0b2b-4530-9be2-274788cdd54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86831
8664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.868318664
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.944147494
Short name T240
Test name
Test status
Simulation time 18599386487 ps
CPU time 42.97 seconds
Started Jul 21 06:56:22 PM PDT 24
Finished Jul 21 06:57:06 PM PDT 24
Peak memory 206968 kb
Host smart-61365706-871f-41d5-ad29-0179b297f014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94414
7494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.944147494
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3228808058
Short name T1453
Test name
Test status
Simulation time 171797283 ps
CPU time 0.86 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206688 kb
Host smart-1027d4e2-296d-42f0-b4fc-846b86e516ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32288
08058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3228808058
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.1085547685
Short name T1213
Test name
Test status
Simulation time 212147988 ps
CPU time 0.91 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206648 kb
Host smart-d457aac6-15b0-4f3d-8d33-87a8af3fd13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10855
47685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.1085547685
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.2550383581
Short name T753
Test name
Test status
Simulation time 208527063 ps
CPU time 0.84 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:26 PM PDT 24
Peak memory 206680 kb
Host smart-efae2bd4-682d-4d1f-b1fd-3cbe39b438b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25503
83581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.2550383581
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.23699368
Short name T827
Test name
Test status
Simulation time 166468790 ps
CPU time 0.79 seconds
Started Jul 21 06:56:25 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206676 kb
Host smart-a66c9288-5bf2-4214-8f15-43fdefeb2f4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23699
368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.23699368
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.164575302
Short name T1822
Test name
Test status
Simulation time 255375447 ps
CPU time 0.87 seconds
Started Jul 21 06:56:28 PM PDT 24
Finished Jul 21 06:56:29 PM PDT 24
Peak memory 206696 kb
Host smart-ac17851d-deb6-44a5-9a4d-f645018c493c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16457
5302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.164575302
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2731448453
Short name T1919
Test name
Test status
Simulation time 155110922 ps
CPU time 0.75 seconds
Started Jul 21 06:56:31 PM PDT 24
Finished Jul 21 06:56:32 PM PDT 24
Peak memory 206668 kb
Host smart-ee0a85eb-c098-47d0-b9b0-37b57daa2935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27314
48453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2731448453
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3918781587
Short name T1482
Test name
Test status
Simulation time 173221795 ps
CPU time 0.83 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:30 PM PDT 24
Peak memory 206672 kb
Host smart-40858465-1c49-4174-8b73-10340d357848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39187
81587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3918781587
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.3843751888
Short name T2272
Test name
Test status
Simulation time 256544207 ps
CPU time 0.95 seconds
Started Jul 21 06:56:28 PM PDT 24
Finished Jul 21 06:56:30 PM PDT 24
Peak memory 206676 kb
Host smart-c8716a85-2fca-4944-b13e-23af2d95587c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38437
51888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.3843751888
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.3435697220
Short name T1009
Test name
Test status
Simulation time 4261144056 ps
CPU time 32.79 seconds
Started Jul 21 06:56:26 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206956 kb
Host smart-04574482-1029-40d6-ba69-856fd1d26e18
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3435697220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.3435697220
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.3530684394
Short name T1476
Test name
Test status
Simulation time 199401548 ps
CPU time 0.81 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:30 PM PDT 24
Peak memory 206684 kb
Host smart-56bc0178-6ebd-4f91-b516-066e6592b808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35306
84394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.3530684394
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.879712636
Short name T1309
Test name
Test status
Simulation time 226848335 ps
CPU time 0.87 seconds
Started Jul 21 06:56:28 PM PDT 24
Finished Jul 21 06:56:29 PM PDT 24
Peak memory 206652 kb
Host smart-4ef955fc-2b68-490a-a7a8-319a19664403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87971
2636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.879712636
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.4187439835
Short name T986
Test name
Test status
Simulation time 1145973570 ps
CPU time 2.43 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:32 PM PDT 24
Peak memory 206800 kb
Host smart-5d357c95-4c17-4ba8-872b-54369c1e6119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41874
39835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.4187439835
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.3890880262
Short name T2531
Test name
Test status
Simulation time 6754076956 ps
CPU time 63.84 seconds
Started Jul 21 06:56:28 PM PDT 24
Finished Jul 21 06:57:33 PM PDT 24
Peak memory 206904 kb
Host smart-9f40ccea-a55c-4ef9-bdc4-45117d96b797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38908
80262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.3890880262
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.1081416305
Short name T1306
Test name
Test status
Simulation time 37938144 ps
CPU time 0.66 seconds
Started Jul 21 06:53:09 PM PDT 24
Finished Jul 21 06:53:10 PM PDT 24
Peak memory 206656 kb
Host smart-80020c8c-8a88-416e-bf5b-1a94dc50aaf5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1081416305 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.1081416305
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.1626109831
Short name T1715
Test name
Test status
Simulation time 3897496093 ps
CPU time 5.03 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:52:56 PM PDT 24
Peak memory 206736 kb
Host smart-252a5dac-2cfc-4715-b271-ab860cddeba9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1626109831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.1626109831
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2668058738
Short name T1522
Test name
Test status
Simulation time 13330135717 ps
CPU time 13.87 seconds
Started Jul 21 06:52:49 PM PDT 24
Finished Jul 21 06:53:04 PM PDT 24
Peak memory 206904 kb
Host smart-b45cae82-79dd-4785-83cd-a9844f4e285b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2668058738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2668058738
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1531881220
Short name T1447
Test name
Test status
Simulation time 23338727865 ps
CPU time 26.3 seconds
Started Jul 21 06:52:56 PM PDT 24
Finished Jul 21 06:53:23 PM PDT 24
Peak memory 206804 kb
Host smart-a3d7c317-8ac7-4a9c-b82f-0f1599439908
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1531881220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1531881220
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.4157114457
Short name T1142
Test name
Test status
Simulation time 160919120 ps
CPU time 0.82 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206688 kb
Host smart-76f289b5-e381-4b22-9a48-3746d9bb5437
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41571
14457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.4157114457
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.952722936
Short name T48
Test name
Test status
Simulation time 197071286 ps
CPU time 0.86 seconds
Started Jul 21 06:53:01 PM PDT 24
Finished Jul 21 06:53:03 PM PDT 24
Peak memory 206300 kb
Host smart-5801c413-faf4-4ef1-bdd2-67610dfe6baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95272
2936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.952722936
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.136287909
Short name T60
Test name
Test status
Simulation time 165257544 ps
CPU time 0.76 seconds
Started Jul 21 06:52:52 PM PDT 24
Finished Jul 21 06:52:53 PM PDT 24
Peak memory 206560 kb
Host smart-a90d3c29-e170-4def-abfd-11f1dc9f0ea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13628
7909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.136287909
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3452715652
Short name T2214
Test name
Test status
Simulation time 177432457 ps
CPU time 0.82 seconds
Started Jul 21 06:52:50 PM PDT 24
Finished Jul 21 06:52:51 PM PDT 24
Peak memory 206636 kb
Host smart-d7b6b98e-7a3e-47d3-8d46-2a1a379b9e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34527
15652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3452715652
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.4158883565
Short name T2436
Test name
Test status
Simulation time 430374042 ps
CPU time 1.44 seconds
Started Jul 21 06:52:56 PM PDT 24
Finished Jul 21 06:52:59 PM PDT 24
Peak memory 206548 kb
Host smart-a2b9e345-0200-4493-b28e-dc86f40e4313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41588
83565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.4158883565
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3330425681
Short name T878
Test name
Test status
Simulation time 1381557149 ps
CPU time 3.33 seconds
Started Jul 21 06:52:53 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206764 kb
Host smart-06dbfe49-3947-42e3-b640-a450883a7f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33304
25681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3330425681
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.3303898732
Short name T2165
Test name
Test status
Simulation time 6596441587 ps
CPU time 13.59 seconds
Started Jul 21 06:52:54 PM PDT 24
Finished Jul 21 06:53:08 PM PDT 24
Peak memory 206928 kb
Host smart-9205f535-1255-4f15-9e83-907cada7ae2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33038
98732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.3303898732
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1209829546
Short name T2300
Test name
Test status
Simulation time 403948007 ps
CPU time 1.3 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206680 kb
Host smart-a0643b72-0175-426f-8b15-13cb94d5fc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12098
29546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1209829546
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.590395622
Short name T1176
Test name
Test status
Simulation time 153982865 ps
CPU time 0.8 seconds
Started Jul 21 06:52:56 PM PDT 24
Finished Jul 21 06:52:59 PM PDT 24
Peak memory 206688 kb
Host smart-c0e35c9e-6772-43b2-b3a0-5e0e45a3779b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59039
5622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.590395622
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.373290956
Short name T2481
Test name
Test status
Simulation time 76444811 ps
CPU time 0.71 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206668 kb
Host smart-0cdba39a-8f62-49a7-a15a-7428607f6699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37329
0956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.373290956
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.2733357845
Short name T1181
Test name
Test status
Simulation time 1004078724 ps
CPU time 2.25 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:58 PM PDT 24
Peak memory 206848 kb
Host smart-e61b55c6-33a5-49fb-b91a-b6d4e16fd59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27333
57845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.2733357845
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.9874814
Short name T1768
Test name
Test status
Simulation time 194244592 ps
CPU time 2.26 seconds
Started Jul 21 06:52:53 PM PDT 24
Finished Jul 21 06:52:56 PM PDT 24
Peak memory 206760 kb
Host smart-63c39d8c-e260-428f-8e77-b863b719a77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98748
14 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.9874814
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.1787847621
Short name T372
Test name
Test status
Simulation time 104185168696 ps
CPU time 141.42 seconds
Started Jul 21 06:52:58 PM PDT 24
Finished Jul 21 06:55:21 PM PDT 24
Peak memory 206856 kb
Host smart-80ab00c0-0a07-4a97-b1ac-58a024ce9471
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1787847621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.1787847621
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.1091477559
Short name T35
Test name
Test status
Simulation time 102230229996 ps
CPU time 136.43 seconds
Started Jul 21 06:52:56 PM PDT 24
Finished Jul 21 06:55:14 PM PDT 24
Peak memory 206952 kb
Host smart-26fb169b-6d50-4b32-949e-458f89668967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091477559 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.1091477559
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.544165960
Short name T1790
Test name
Test status
Simulation time 99101843175 ps
CPU time 123.98 seconds
Started Jul 21 06:52:57 PM PDT 24
Finished Jul 21 06:55:02 PM PDT 24
Peak memory 206980 kb
Host smart-1972ba6c-0b02-48b6-81d1-cd7aaf4556f9
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=544165960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.544165960
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.2807502839
Short name T778
Test name
Test status
Simulation time 88267606280 ps
CPU time 113.53 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:54:49 PM PDT 24
Peak memory 206916 kb
Host smart-848ce41b-1684-4f20-a933-f242255a1a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807502839 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.2807502839
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.655226405
Short name T2304
Test name
Test status
Simulation time 106184463197 ps
CPU time 132.05 seconds
Started Jul 21 06:52:57 PM PDT 24
Finished Jul 21 06:55:10 PM PDT 24
Peak memory 206948 kb
Host smart-2ed2ba11-a9c8-4c91-a32d-996bb2365b12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65522
6405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.655226405
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.3734824164
Short name T811
Test name
Test status
Simulation time 157406649 ps
CPU time 0.8 seconds
Started Jul 21 06:52:57 PM PDT 24
Finished Jul 21 06:52:59 PM PDT 24
Peak memory 206668 kb
Host smart-2c234440-4641-43e1-a75a-4ef5f4c35fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37348
24164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.3734824164
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.3726786665
Short name T895
Test name
Test status
Simulation time 134307660 ps
CPU time 0.77 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206672 kb
Host smart-761caa89-bbb6-48ad-bde6-b7d0f256469b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37267
86665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.3726786665
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1685319860
Short name T1825
Test name
Test status
Simulation time 173855872 ps
CPU time 0.81 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206700 kb
Host smart-05143c4b-a558-4195-912d-994191ad7f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16853
19860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1685319860
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_invalid_sync.1869303478
Short name T2467
Test name
Test status
Simulation time 7538278621 ps
CPU time 216.98 seconds
Started Jul 21 06:52:57 PM PDT 24
Finished Jul 21 06:56:35 PM PDT 24
Peak memory 206900 kb
Host smart-e0630f35-4ad9-4c70-a24f-dbde232213b2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1869303478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_invalid_sync.1869303478
Directory /workspace/2.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.4236899217
Short name T1662
Test name
Test status
Simulation time 10928435562 ps
CPU time 98.5 seconds
Started Jul 21 06:52:54 PM PDT 24
Finished Jul 21 06:54:33 PM PDT 24
Peak memory 206908 kb
Host smart-5ee9eef8-0411-45d6-952d-a3cf5258be6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42368
99217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.4236899217
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.3338143155
Short name T1058
Test name
Test status
Simulation time 238660392 ps
CPU time 0.87 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:52:57 PM PDT 24
Peak memory 206680 kb
Host smart-a71f949c-60f1-4e6f-8704-14f0c54a9a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33381
43155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.3338143155
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.672372139
Short name T1424
Test name
Test status
Simulation time 23310906904 ps
CPU time 27.64 seconds
Started Jul 21 06:52:56 PM PDT 24
Finished Jul 21 06:53:25 PM PDT 24
Peak memory 206708 kb
Host smart-42319945-d5f9-4fb6-8b12-84aba0b5abef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67237
2139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.672372139
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.1375098398
Short name T1826
Test name
Test status
Simulation time 3330430452 ps
CPU time 4.32 seconds
Started Jul 21 06:52:56 PM PDT 24
Finished Jul 21 06:53:01 PM PDT 24
Peak memory 206724 kb
Host smart-295a9b62-d974-4aae-ba92-e96fe68fea65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13750
98398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.1375098398
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.2174924702
Short name T2333
Test name
Test status
Simulation time 6872025354 ps
CPU time 183.61 seconds
Started Jul 21 06:52:55 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206924 kb
Host smart-6907caf7-f6a4-4b76-aa94-f4c4627f9e72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21749
24702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.2174924702
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.3822513013
Short name T2418
Test name
Test status
Simulation time 5563658765 ps
CPU time 51.51 seconds
Started Jul 21 06:52:58 PM PDT 24
Finished Jul 21 06:53:50 PM PDT 24
Peak memory 206932 kb
Host smart-f08b5cf7-e510-413b-83bc-4b57d98f9099
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3822513013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.3822513013
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.206014370
Short name T667
Test name
Test status
Simulation time 244440343 ps
CPU time 0.87 seconds
Started Jul 21 06:52:59 PM PDT 24
Finished Jul 21 06:53:01 PM PDT 24
Peak memory 206712 kb
Host smart-7dba6b0b-f1d9-40d2-b9e8-b1294708aeb6
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=206014370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.206014370
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.4118630816
Short name T2743
Test name
Test status
Simulation time 195825123 ps
CPU time 0.98 seconds
Started Jul 21 06:53:00 PM PDT 24
Finished Jul 21 06:53:03 PM PDT 24
Peak memory 206692 kb
Host smart-2c178a98-4ec2-4557-b69b-11dd639b175f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41186
30816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.4118630816
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.4217544550
Short name T1648
Test name
Test status
Simulation time 5229230725 ps
CPU time 140.02 seconds
Started Jul 21 06:53:00 PM PDT 24
Finished Jul 21 06:55:20 PM PDT 24
Peak memory 206872 kb
Host smart-3ec7d635-e7bc-466a-9a24-fe4b16566b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
44550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.4217544550
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.4055512479
Short name T2393
Test name
Test status
Simulation time 3761460592 ps
CPU time 27.57 seconds
Started Jul 21 06:53:02 PM PDT 24
Finished Jul 21 06:53:31 PM PDT 24
Peak memory 206968 kb
Host smart-077c0216-969e-4ec5-a45b-60c3580a555c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4055512479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.4055512479
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.314941239
Short name T2723
Test name
Test status
Simulation time 166317024 ps
CPU time 0.76 seconds
Started Jul 21 06:53:00 PM PDT 24
Finished Jul 21 06:53:01 PM PDT 24
Peak memory 206680 kb
Host smart-eb46e6bd-9abf-4597-9821-c957a13efb86
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=314941239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.314941239
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.2153367538
Short name T2040
Test name
Test status
Simulation time 145522774 ps
CPU time 0.83 seconds
Started Jul 21 06:53:01 PM PDT 24
Finished Jul 21 06:53:03 PM PDT 24
Peak memory 206660 kb
Host smart-0612c55c-fc1a-439c-8096-870025904ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21533
67538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.2153367538
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.432479307
Short name T1446
Test name
Test status
Simulation time 226251613 ps
CPU time 0.98 seconds
Started Jul 21 06:53:02 PM PDT 24
Finished Jul 21 06:53:04 PM PDT 24
Peak memory 206692 kb
Host smart-6c1a5971-015f-455d-af38-1c28a9481f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43247
9307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.432479307
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.1634119579
Short name T1390
Test name
Test status
Simulation time 187845088 ps
CPU time 0.88 seconds
Started Jul 21 06:53:00 PM PDT 24
Finished Jul 21 06:53:02 PM PDT 24
Peak memory 206688 kb
Host smart-aa1834ef-5310-4389-bf3e-afcd45e42de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16341
19579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.1634119579
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3348999921
Short name T1061
Test name
Test status
Simulation time 185205982 ps
CPU time 0.84 seconds
Started Jul 21 06:53:03 PM PDT 24
Finished Jul 21 06:53:05 PM PDT 24
Peak memory 206640 kb
Host smart-27f3fccc-8602-400e-8aad-8434619e8b25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33489
99921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3348999921
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1643957358
Short name T1656
Test name
Test status
Simulation time 168712247 ps
CPU time 0.78 seconds
Started Jul 21 06:53:03 PM PDT 24
Finished Jul 21 06:53:04 PM PDT 24
Peak memory 206660 kb
Host smart-8d769a94-cd51-4f44-a537-ecf83c7532c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16439
57358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1643957358
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.1399174356
Short name T1426
Test name
Test status
Simulation time 209398414 ps
CPU time 0.97 seconds
Started Jul 21 06:52:58 PM PDT 24
Finished Jul 21 06:53:00 PM PDT 24
Peak memory 206688 kb
Host smart-739e727c-df60-4249-adef-13c960f123d1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1399174356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.1399174356
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1746702302
Short name T194
Test name
Test status
Simulation time 183983399 ps
CPU time 0.93 seconds
Started Jul 21 06:53:02 PM PDT 24
Finished Jul 21 06:53:04 PM PDT 24
Peak memory 206700 kb
Host smart-15abfc70-cf8e-4379-bac2-b9018c38c967
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17467
02302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1746702302
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.1748608762
Short name T1866
Test name
Test status
Simulation time 152786943 ps
CPU time 0.83 seconds
Started Jul 21 06:53:04 PM PDT 24
Finished Jul 21 06:53:06 PM PDT 24
Peak memory 206660 kb
Host smart-56d8c591-6b8b-4111-af57-7dcaf7eb9d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17486
08762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.1748608762
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.1852108761
Short name T972
Test name
Test status
Simulation time 70498831 ps
CPU time 0.7 seconds
Started Jul 21 06:53:00 PM PDT 24
Finished Jul 21 06:53:02 PM PDT 24
Peak memory 206700 kb
Host smart-e0c98d86-da3b-4b93-b3ac-3e438e4c21e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18521
08761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.1852108761
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.2847423191
Short name T1854
Test name
Test status
Simulation time 10823115708 ps
CPU time 24.16 seconds
Started Jul 21 06:52:59 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206892 kb
Host smart-7127a647-2e86-4233-82dd-db2a3f7f3de0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28474
23191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.2847423191
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3867690672
Short name T277
Test name
Test status
Simulation time 238915910 ps
CPU time 0.88 seconds
Started Jul 21 06:53:01 PM PDT 24
Finished Jul 21 06:53:03 PM PDT 24
Peak memory 206660 kb
Host smart-f3155bc7-b580-4d3a-991c-cb98b364d504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38676
90672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3867690672
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.3244940258
Short name T2324
Test name
Test status
Simulation time 215263748 ps
CPU time 0.88 seconds
Started Jul 21 06:53:03 PM PDT 24
Finished Jul 21 06:53:05 PM PDT 24
Peak memory 206628 kb
Host smart-f935e3ee-4e0c-4cc7-b12c-dc702c997c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32449
40258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.3244940258
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.111971662
Short name T2408
Test name
Test status
Simulation time 8192995471 ps
CPU time 34.94 seconds
Started Jul 21 06:53:03 PM PDT 24
Finished Jul 21 06:53:39 PM PDT 24
Peak memory 206812 kb
Host smart-307f4bde-9fcf-4abd-b886-aa955bd5f950
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=111971662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.111971662
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2798255288
Short name T161
Test name
Test status
Simulation time 15952111512 ps
CPU time 404.64 seconds
Started Jul 21 06:53:05 PM PDT 24
Finished Jul 21 06:59:50 PM PDT 24
Peak memory 206976 kb
Host smart-746d7785-41fc-4220-9e65-80221e700733
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2798255288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2798255288
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.408742234
Short name T2466
Test name
Test status
Simulation time 12488090043 ps
CPU time 87.69 seconds
Started Jul 21 06:53:08 PM PDT 24
Finished Jul 21 06:54:37 PM PDT 24
Peak memory 206904 kb
Host smart-a3b00a91-d7a7-479c-8a6c-f592a2a2024d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=408742234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.408742234
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.569076546
Short name T1991
Test name
Test status
Simulation time 220102062 ps
CPU time 0.91 seconds
Started Jul 21 06:53:09 PM PDT 24
Finished Jul 21 06:53:10 PM PDT 24
Peak memory 206668 kb
Host smart-368aadbc-9d4e-4095-937a-581fdfa684c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56907
6546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.569076546
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.4256245439
Short name T1104
Test name
Test status
Simulation time 198306546 ps
CPU time 0.85 seconds
Started Jul 21 06:53:04 PM PDT 24
Finished Jul 21 06:53:05 PM PDT 24
Peak memory 206704 kb
Host smart-ab188382-9ac5-4447-943a-07dada03968b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42562
45439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.4256245439
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.2779041728
Short name T2461
Test name
Test status
Simulation time 145277057 ps
CPU time 0.77 seconds
Started Jul 21 06:53:03 PM PDT 24
Finished Jul 21 06:53:04 PM PDT 24
Peak memory 206672 kb
Host smart-3b697281-9209-4c59-abc5-2afee4f32986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27790
41728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.2779041728
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.188199253
Short name T2608
Test name
Test status
Simulation time 226583437 ps
CPU time 0.85 seconds
Started Jul 21 06:53:05 PM PDT 24
Finished Jul 21 06:53:06 PM PDT 24
Peak memory 206672 kb
Host smart-b46923ef-9ea4-4765-af10-965d922c19d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18819
9253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.188199253
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.422466903
Short name T202
Test name
Test status
Simulation time 1294695935 ps
CPU time 1.95 seconds
Started Jul 21 06:53:06 PM PDT 24
Finished Jul 21 06:53:08 PM PDT 24
Peak memory 224572 kb
Host smart-66fa7fc3-4aa7-4de8-a75b-690224b7dddf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=422466903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.422466903
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2881012599
Short name T619
Test name
Test status
Simulation time 325849556 ps
CPU time 1.1 seconds
Started Jul 21 06:53:05 PM PDT 24
Finished Jul 21 06:53:07 PM PDT 24
Peak memory 206644 kb
Host smart-ae5e2821-cded-4f36-a92d-0dd76b41ac66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28810
12599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2881012599
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.2081695318
Short name T1163
Test name
Test status
Simulation time 196836929 ps
CPU time 0.9 seconds
Started Jul 21 06:53:07 PM PDT 24
Finished Jul 21 06:53:09 PM PDT 24
Peak memory 206652 kb
Host smart-04853a2c-f772-4985-aa0c-7c0cd008efbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20816
95318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.2081695318
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.3641418791
Short name T2110
Test name
Test status
Simulation time 209102675 ps
CPU time 0.83 seconds
Started Jul 21 06:53:07 PM PDT 24
Finished Jul 21 06:53:08 PM PDT 24
Peak memory 206740 kb
Host smart-f3a2f27e-053b-4e2b-b650-171d983bac4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36414
18791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.3641418791
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.522665891
Short name T1200
Test name
Test status
Simulation time 167102835 ps
CPU time 0.83 seconds
Started Jul 21 06:53:08 PM PDT 24
Finished Jul 21 06:53:09 PM PDT 24
Peak memory 206648 kb
Host smart-62c74639-cdb2-40ae-adff-c272b6e793a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52266
5891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.522665891
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.868626072
Short name T23
Test name
Test status
Simulation time 213222908 ps
CPU time 0.9 seconds
Started Jul 21 06:53:06 PM PDT 24
Finished Jul 21 06:53:07 PM PDT 24
Peak memory 206696 kb
Host smart-5791cf8e-228d-4bf8-bfa4-8f057081c1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86862
6072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.868626072
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.798483667
Short name T807
Test name
Test status
Simulation time 4600110539 ps
CPU time 41.48 seconds
Started Jul 21 06:53:08 PM PDT 24
Finished Jul 21 06:53:50 PM PDT 24
Peak memory 206876 kb
Host smart-dbd15c4d-42ff-48ba-b8c6-f4a808d29def
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=798483667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.798483667
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.215426085
Short name T2280
Test name
Test status
Simulation time 161426170 ps
CPU time 0.82 seconds
Started Jul 21 06:53:04 PM PDT 24
Finished Jul 21 06:53:06 PM PDT 24
Peak memory 206668 kb
Host smart-683241bf-e475-4e1e-b029-60c866c2b803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21542
6085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.215426085
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.173337881
Short name T2297
Test name
Test status
Simulation time 183342015 ps
CPU time 0.83 seconds
Started Jul 21 06:53:08 PM PDT 24
Finished Jul 21 06:53:10 PM PDT 24
Peak memory 206652 kb
Host smart-b5ac12d7-53c8-470c-b632-4d29553c9f42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17333
7881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.173337881
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.1541023775
Short name T1452
Test name
Test status
Simulation time 449767041 ps
CPU time 1.3 seconds
Started Jul 21 06:53:05 PM PDT 24
Finished Jul 21 06:53:07 PM PDT 24
Peak memory 206648 kb
Host smart-27b0b48c-b8e2-4236-a6f2-6ca06260253f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15410
23775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.1541023775
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.1112855419
Short name T797
Test name
Test status
Simulation time 4297187961 ps
CPU time 30.12 seconds
Started Jul 21 06:53:06 PM PDT 24
Finished Jul 21 06:53:36 PM PDT 24
Peak memory 206948 kb
Host smart-12e5bd7f-fde1-40be-902e-1fe07714d492
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11128
55419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.1112855419
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.615744459
Short name T58
Test name
Test status
Simulation time 9307775749 ps
CPU time 56.32 seconds
Started Jul 21 06:53:08 PM PDT 24
Finished Jul 21 06:54:05 PM PDT 24
Peak memory 207020 kb
Host smart-83983e2f-3882-49bb-9536-ba39a7a91f04
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=615744459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.615744459
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.2876140
Short name T1569
Test name
Test status
Simulation time 86554386 ps
CPU time 0.72 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 206716 kb
Host smart-a9528a75-8482-45c5-be92-16015b097630
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2876140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.2876140
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.4042571968
Short name T873
Test name
Test status
Simulation time 4269849905 ps
CPU time 6.04 seconds
Started Jul 21 06:56:30 PM PDT 24
Finished Jul 21 06:56:37 PM PDT 24
Peak memory 206820 kb
Host smart-75aaed98-7ece-4f73-a6ac-49ee62d18ff4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4042571968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.4042571968
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.4277368760
Short name T1580
Test name
Test status
Simulation time 13457575896 ps
CPU time 12.52 seconds
Started Jul 21 06:56:31 PM PDT 24
Finished Jul 21 06:56:43 PM PDT 24
Peak memory 206940 kb
Host smart-8aad2256-f406-49d6-bdd6-849bc8fe6b7f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4277368760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.4277368760
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.3171712652
Short name T2738
Test name
Test status
Simulation time 23307461162 ps
CPU time 22.34 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:52 PM PDT 24
Peak memory 206952 kb
Host smart-a67edaea-bf23-4985-8638-da7ccca57b1f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3171712652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.3171712652
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.2769746857
Short name T1402
Test name
Test status
Simulation time 151909422 ps
CPU time 0.8 seconds
Started Jul 21 06:56:28 PM PDT 24
Finished Jul 21 06:56:29 PM PDT 24
Peak memory 206680 kb
Host smart-5e15dcd8-e007-4786-901e-911718a5856e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27697
46857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.2769746857
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.3068722178
Short name T921
Test name
Test status
Simulation time 161209180 ps
CPU time 0.86 seconds
Started Jul 21 06:56:30 PM PDT 24
Finished Jul 21 06:56:32 PM PDT 24
Peak memory 206676 kb
Host smart-c87a9f0a-ccd4-40ed-b24d-9f622cbdf1cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30687
22178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.3068722178
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2787630833
Short name T2351
Test name
Test status
Simulation time 418380194 ps
CPU time 1.25 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:31 PM PDT 24
Peak memory 206676 kb
Host smart-b00bffb3-fa2f-4f7c-bd11-99f59ef87cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27876
30833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2787630833
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.3003653821
Short name T1843
Test name
Test status
Simulation time 10934690025 ps
CPU time 20.27 seconds
Started Jul 21 06:56:30 PM PDT 24
Finished Jul 21 06:56:50 PM PDT 24
Peak memory 206952 kb
Host smart-94e905fa-379e-4046-aecd-e27ba5cdfc11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30036
53821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.3003653821
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.2640096891
Short name T561
Test name
Test status
Simulation time 437973884 ps
CPU time 1.34 seconds
Started Jul 21 06:56:28 PM PDT 24
Finished Jul 21 06:56:30 PM PDT 24
Peak memory 206636 kb
Host smart-9a734ecb-0cf0-4709-9297-e2dd7eb56213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26400
96891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.2640096891
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.795980991
Short name T41
Test name
Test status
Simulation time 144524473 ps
CPU time 0.8 seconds
Started Jul 21 06:56:29 PM PDT 24
Finished Jul 21 06:56:31 PM PDT 24
Peak memory 206652 kb
Host smart-a8333945-e087-403e-9839-b8c082b60a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79598
0991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.795980991
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.3392102436
Short name T1897
Test name
Test status
Simulation time 64661734 ps
CPU time 0.68 seconds
Started Jul 21 06:56:27 PM PDT 24
Finished Jul 21 06:56:28 PM PDT 24
Peak memory 206680 kb
Host smart-60f4befd-92a0-467b-a7a6-ae9c17224d20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33921
02436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.3392102436
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.55402511
Short name T791
Test name
Test status
Simulation time 892111445 ps
CPU time 1.97 seconds
Started Jul 21 06:56:32 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206792 kb
Host smart-5efd53fc-b9a8-4518-8021-5b542c8e4d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55402
511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.55402511
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.2048083889
Short name T2085
Test name
Test status
Simulation time 236174309 ps
CPU time 1.37 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:56:37 PM PDT 24
Peak memory 206764 kb
Host smart-ddb1bf51-adf2-4664-abd5-308e9d63b02c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20480
83889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.2048083889
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.478197953
Short name T1491
Test name
Test status
Simulation time 195354902 ps
CPU time 0.84 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:56:37 PM PDT 24
Peak memory 206660 kb
Host smart-3c8f7272-5e78-4c2b-a322-77b2feb82e66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47819
7953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.478197953
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.1375170654
Short name T1421
Test name
Test status
Simulation time 143403130 ps
CPU time 0.81 seconds
Started Jul 21 06:56:34 PM PDT 24
Finished Jul 21 06:56:35 PM PDT 24
Peak memory 206652 kb
Host smart-8b787893-04bf-48d2-a744-b9a7484fc978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13751
70654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.1375170654
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.137174473
Short name T2709
Test name
Test status
Simulation time 241381607 ps
CPU time 0.87 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:56:37 PM PDT 24
Peak memory 206680 kb
Host smart-02da72f7-605c-4c7d-a66d-95560b3366c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13717
4473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.137174473
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.3182626049
Short name T2130
Test name
Test status
Simulation time 5710895633 ps
CPU time 50.67 seconds
Started Jul 21 06:56:32 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206956 kb
Host smart-93402c1f-367b-47df-894d-5b3d16e141a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31826
26049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.3182626049
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.1560734401
Short name T1675
Test name
Test status
Simulation time 187817913 ps
CPU time 0.88 seconds
Started Jul 21 06:56:33 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206680 kb
Host smart-910106e8-b2fc-4e3d-b0c7-916166d4b633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15607
34401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.1560734401
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.4245409320
Short name T2189
Test name
Test status
Simulation time 23291966851 ps
CPU time 24.31 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206780 kb
Host smart-22000c30-2f51-4bd5-a0ec-7a4e5cee0929
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42454
09320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.4245409320
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.3803903076
Short name T1509
Test name
Test status
Simulation time 3347739255 ps
CPU time 3.74 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 206748 kb
Host smart-7cd30fb3-8c2a-434c-8bae-266bcd90ff0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38039
03076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.3803903076
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2499929991
Short name T2640
Test name
Test status
Simulation time 10288001662 ps
CPU time 296.56 seconds
Started Jul 21 06:56:34 PM PDT 24
Finished Jul 21 07:01:31 PM PDT 24
Peak memory 206932 kb
Host smart-46665956-cb57-445d-8a48-f30383a35636
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24999
29991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2499929991
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.127084481
Short name T1646
Test name
Test status
Simulation time 4180220303 ps
CPU time 28.47 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:57:04 PM PDT 24
Peak memory 206920 kb
Host smart-afea76fc-a1ec-49d8-b274-77c6ef8a2382
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=127084481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.127084481
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1092328315
Short name T825
Test name
Test status
Simulation time 244777115 ps
CPU time 0.98 seconds
Started Jul 21 06:56:34 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206652 kb
Host smart-49c0f6a6-42d1-4f7f-894d-0ec8557341cf
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1092328315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1092328315
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.2221666773
Short name T2060
Test name
Test status
Simulation time 193575348 ps
CPU time 0.89 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206696 kb
Host smart-31655984-9b82-4e0e-a71f-abc644b04500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22216
66773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.2221666773
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3341137750
Short name T1489
Test name
Test status
Simulation time 7210692353 ps
CPU time 192.11 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:59:48 PM PDT 24
Peak memory 206884 kb
Host smart-f760a443-c96d-48e2-8258-ee8cf4f7532a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33411
37750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3341137750
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.1725256451
Short name T135
Test name
Test status
Simulation time 5705735173 ps
CPU time 39.91 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:57:16 PM PDT 24
Peak memory 206908 kb
Host smart-e9914788-3064-42c1-ba96-4d66c859445f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1725256451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.1725256451
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.1423503964
Short name T683
Test name
Test status
Simulation time 171161618 ps
CPU time 0.82 seconds
Started Jul 21 06:56:32 PM PDT 24
Finished Jul 21 06:56:33 PM PDT 24
Peak memory 206672 kb
Host smart-ad09a7ce-0789-47d3-a9ec-2b2ab5832f9d
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1423503964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.1423503964
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3950922817
Short name T1003
Test name
Test status
Simulation time 171876580 ps
CPU time 0.8 seconds
Started Jul 21 06:56:34 PM PDT 24
Finished Jul 21 06:56:35 PM PDT 24
Peak memory 206656 kb
Host smart-1956c8fb-7c59-43b9-93f1-58c4c192f36b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39509
22817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3950922817
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2749359675
Short name T107
Test name
Test status
Simulation time 197487169 ps
CPU time 0.83 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206692 kb
Host smart-c5ff0380-01ff-40dd-b12c-1e4c9b5a46ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27493
59675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2749359675
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3466158430
Short name T2394
Test name
Test status
Simulation time 178189730 ps
CPU time 0.87 seconds
Started Jul 21 06:56:33 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206656 kb
Host smart-3d69d74d-eb0d-44ad-9107-59c512fa9cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34661
58430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3466158430
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.320647294
Short name T2754
Test name
Test status
Simulation time 183049993 ps
CPU time 0.82 seconds
Started Jul 21 06:56:34 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206676 kb
Host smart-8e9f2e6a-75b8-49e0-a89d-59d754fb1ca1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32064
7294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.320647294
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.672876878
Short name T2088
Test name
Test status
Simulation time 185403724 ps
CPU time 0.83 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206684 kb
Host smart-9bde64a7-07c3-4fd3-8569-70f26017778f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67287
6878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.672876878
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.2979291973
Short name T1340
Test name
Test status
Simulation time 171830995 ps
CPU time 0.75 seconds
Started Jul 21 06:56:33 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206420 kb
Host smart-4d1c7dc0-d3dc-48eb-ba47-73ef221df321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29792
91973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.2979291973
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.2461458683
Short name T1196
Test name
Test status
Simulation time 233448063 ps
CPU time 0.88 seconds
Started Jul 21 06:56:34 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206672 kb
Host smart-59dc783c-ca3e-47bb-813c-7790f97a9f50
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2461458683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.2461458683
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.2201271056
Short name T787
Test name
Test status
Simulation time 156319020 ps
CPU time 0.74 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206652 kb
Host smart-2af72214-8803-4b9e-9d8a-3f16c5baabf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22012
71056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.2201271056
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1440297972
Short name T2499
Test name
Test status
Simulation time 39998837 ps
CPU time 0.66 seconds
Started Jul 21 06:56:34 PM PDT 24
Finished Jul 21 06:56:35 PM PDT 24
Peak memory 206636 kb
Host smart-e4423822-2f11-4093-82d9-5c7d44206cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402
97972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1440297972
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.1801229759
Short name T1363
Test name
Test status
Simulation time 12463094686 ps
CPU time 30.77 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:57:06 PM PDT 24
Peak memory 206948 kb
Host smart-3e580deb-548f-4b44-b934-83b850e0b369
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18012
29759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.1801229759
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.522049503
Short name T1284
Test name
Test status
Simulation time 162261242 ps
CPU time 0.77 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 206632 kb
Host smart-2863558a-a94f-4e69-bfcc-cf86465528bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52204
9503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.522049503
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.3757360069
Short name T1614
Test name
Test status
Simulation time 245044358 ps
CPU time 0.92 seconds
Started Jul 21 06:56:33 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206664 kb
Host smart-4aac981b-1bd2-467a-a309-fe86e9ef81da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37573
60069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.3757360069
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.3286173732
Short name T223
Test name
Test status
Simulation time 170936830 ps
CPU time 0.75 seconds
Started Jul 21 06:56:33 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206420 kb
Host smart-b9b0ce11-df93-4f14-9ea3-fab5b12a4e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32861
73732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.3286173732
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.729294017
Short name T959
Test name
Test status
Simulation time 169755303 ps
CPU time 0.8 seconds
Started Jul 21 06:56:35 PM PDT 24
Finished Jul 21 06:56:37 PM PDT 24
Peak memory 206680 kb
Host smart-0fd81311-51b8-45f1-8e29-a7ef33949532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72929
4017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.729294017
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.3516024274
Short name T443
Test name
Test status
Simulation time 215755069 ps
CPU time 0.82 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206628 kb
Host smart-88a238c1-3f14-4143-b1c7-89bd53521d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35160
24274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.3516024274
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.1749414643
Short name T509
Test name
Test status
Simulation time 155296311 ps
CPU time 0.78 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206624 kb
Host smart-3334bc50-088a-4158-8094-16e284d846ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17494
14643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.1749414643
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.1049405975
Short name T329
Test name
Test status
Simulation time 165801967 ps
CPU time 0.85 seconds
Started Jul 21 06:56:32 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206704 kb
Host smart-e32d738d-cfba-41e2-ad5c-ee14ba515a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10494
05975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.1049405975
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.277417010
Short name T800
Test name
Test status
Simulation time 220992405 ps
CPU time 0.94 seconds
Started Jul 21 06:56:33 PM PDT 24
Finished Jul 21 06:56:34 PM PDT 24
Peak memory 206724 kb
Host smart-ebb04db2-e164-4384-a084-a56bc6b8a002
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
7010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.277417010
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.1646705583
Short name T2068
Test name
Test status
Simulation time 5864703983 ps
CPU time 42.96 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:57:22 PM PDT 24
Peak memory 206880 kb
Host smart-b04ce82a-1eaf-4f14-b49f-430b8c860d1e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1646705583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.1646705583
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.883854033
Short name T1466
Test name
Test status
Simulation time 160754824 ps
CPU time 0.78 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206684 kb
Host smart-bb7ab524-e49c-44e8-a56d-9b77fa3eec17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88385
4033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.883854033
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1924724624
Short name T1165
Test name
Test status
Simulation time 163674673 ps
CPU time 0.8 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206692 kb
Host smart-aa1e88c0-1b85-4b7e-bcbf-92af9ce27d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19247
24624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1924724624
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.2659131074
Short name T1100
Test name
Test status
Simulation time 458613899 ps
CPU time 1.23 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:56:41 PM PDT 24
Peak memory 206692 kb
Host smart-4447903d-2415-4464-8529-a1fdcf2e6694
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26591
31074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.2659131074
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.3858733111
Short name T1663
Test name
Test status
Simulation time 4921995661 ps
CPU time 34.77 seconds
Started Jul 21 06:56:40 PM PDT 24
Finished Jul 21 06:57:16 PM PDT 24
Peak memory 206848 kb
Host smart-888a6118-1058-45ea-82dc-e2a3c2a4bd9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38587
33111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.3858733111
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1103951872
Short name T1410
Test name
Test status
Simulation time 69287682 ps
CPU time 0.74 seconds
Started Jul 21 06:56:44 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206840 kb
Host smart-ad1443c1-b570-4c75-9553-1531d5c4efcc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1103951872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1103951872
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.342595472
Short name T748
Test name
Test status
Simulation time 3978532609 ps
CPU time 5.61 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:44 PM PDT 24
Peak memory 206720 kb
Host smart-95c579c0-3a96-4f8a-883a-0cb1b6d3d80a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=342595472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.342595472
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3794206086
Short name T2415
Test name
Test status
Simulation time 13393745123 ps
CPU time 12.85 seconds
Started Jul 21 06:56:40 PM PDT 24
Finished Jul 21 06:56:54 PM PDT 24
Peak memory 206784 kb
Host smart-9d56796f-ef07-4ca2-b8cf-11f71444e322
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3794206086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3794206086
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3458474174
Short name T2518
Test name
Test status
Simulation time 23290420393 ps
CPU time 26.14 seconds
Started Jul 21 06:56:40 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206808 kb
Host smart-4207c158-d247-44ac-99e2-6ad208f97bd8
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3458474174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.3458474174
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.1932157760
Short name T385
Test name
Test status
Simulation time 160311791 ps
CPU time 0.82 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:56:41 PM PDT 24
Peak memory 206684 kb
Host smart-d0ffc624-15da-4add-b33a-79ab34ac25c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19321
57760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.1932157760
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.4005509912
Short name T378
Test name
Test status
Simulation time 151655414 ps
CPU time 0.76 seconds
Started Jul 21 06:56:40 PM PDT 24
Finished Jul 21 06:56:42 PM PDT 24
Peak memory 206536 kb
Host smart-683d1ad0-6379-47a5-bdc6-d4d105907288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40055
09912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.4005509912
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.2400015697
Short name T1996
Test name
Test status
Simulation time 322505026 ps
CPU time 1.16 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 206648 kb
Host smart-0934b8f3-5e0b-4e71-8794-15dec60cb6f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24000
15697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.2400015697
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.2246618679
Short name T2173
Test name
Test status
Simulation time 1106238842 ps
CPU time 2.4 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206844 kb
Host smart-4cdab747-0404-4b23-b3e8-8c976151b6ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22466
18679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.2246618679
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_device_address.669155226
Short name T170
Test name
Test status
Simulation time 13530844005 ps
CPU time 30.19 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 206880 kb
Host smart-9d86a6fb-b0c3-4bb7-a6b9-f8e6aa1d142c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66915
5226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.669155226
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.854934666
Short name T2360
Test name
Test status
Simulation time 349810550 ps
CPU time 1.14 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:56:42 PM PDT 24
Peak memory 206420 kb
Host smart-730a1ff0-ffee-4487-9e87-0604e21ce1ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85493
4666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.854934666
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.4082184135
Short name T1556
Test name
Test status
Simulation time 209253700 ps
CPU time 0.84 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206688 kb
Host smart-27b627e2-2680-4d81-8da5-d23419e4862a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40821
84135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.4082184135
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/default/21.usbdev_enable.2774171312
Short name T368
Test name
Test status
Simulation time 39862920 ps
CPU time 0.65 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 206680 kb
Host smart-5530ae30-9913-4f3b-9356-c7bcd206ab02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
71312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.2774171312
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.3784984660
Short name T725
Test name
Test status
Simulation time 908902417 ps
CPU time 2.16 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206716 kb
Host smart-95968e33-5706-4163-b5b6-f52ec8ba4ea8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37849
84660 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.3784984660
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.3414707030
Short name T496
Test name
Test status
Simulation time 228242016 ps
CPU time 1.57 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:56:41 PM PDT 24
Peak memory 206796 kb
Host smart-610c63b4-6e62-4d61-840b-472c551b38c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34147
07030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.3414707030
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.323966087
Short name T788
Test name
Test status
Simulation time 232988107 ps
CPU time 0.85 seconds
Started Jul 21 06:56:42 PM PDT 24
Finished Jul 21 06:56:44 PM PDT 24
Peak memory 206620 kb
Host smart-84a20ac0-3126-4d79-9523-3976b4bc5982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
6087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.323966087
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.210322931
Short name T931
Test name
Test status
Simulation time 179903939 ps
CPU time 0.83 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206696 kb
Host smart-357d25fa-24dd-4bc7-945f-d3de575c107f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21032
2931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.210322931
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.1601317917
Short name T1351
Test name
Test status
Simulation time 244492240 ps
CPU time 0.92 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206696 kb
Host smart-d476acba-d961-4268-81e6-a15b10fcdedc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16013
17917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.1601317917
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.3119682495
Short name T1434
Test name
Test status
Simulation time 188000264 ps
CPU time 0.86 seconds
Started Jul 21 06:56:41 PM PDT 24
Finished Jul 21 06:56:42 PM PDT 24
Peak memory 206656 kb
Host smart-93ac710a-022e-4ccc-9e71-950e5ae3610a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31196
82495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.3119682495
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.224355866
Short name T2469
Test name
Test status
Simulation time 23287296103 ps
CPU time 26.89 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:57:06 PM PDT 24
Peak memory 206816 kb
Host smart-0b02c792-dccf-4623-9aee-b1b94abfb726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22435
5866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.224355866
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.1462407815
Short name T1369
Test name
Test status
Simulation time 3297994465 ps
CPU time 3.67 seconds
Started Jul 21 06:56:40 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206592 kb
Host smart-21dd7c6b-3b71-4425-9d15-3891042c0da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14624
07815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.1462407815
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.3483568856
Short name T415
Test name
Test status
Simulation time 10035807882 ps
CPU time 285.29 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 07:01:26 PM PDT 24
Peak memory 206648 kb
Host smart-1ee9f2e3-6838-4cb2-a878-49328a3be6b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34835
68856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.3483568856
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.4123040956
Short name T406
Test name
Test status
Simulation time 4581802065 ps
CPU time 120.65 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:58:38 PM PDT 24
Peak memory 206900 kb
Host smart-c0934976-1dae-4757-995f-df0c9f45f3af
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4123040956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.4123040956
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.4158629786
Short name T425
Test name
Test status
Simulation time 244531223 ps
CPU time 1.06 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:56:38 PM PDT 24
Peak memory 206664 kb
Host smart-9ff91fa5-e450-4f1d-bd7c-52f6f093dd43
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4158629786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.4158629786
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.1136220011
Short name T1816
Test name
Test status
Simulation time 191450737 ps
CPU time 0.85 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206624 kb
Host smart-9d39e8eb-fedd-4d7f-bebc-0bffdb98da20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
20011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.1136220011
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.1674128426
Short name T1894
Test name
Test status
Simulation time 3759352266 ps
CPU time 103.28 seconds
Started Jul 21 06:56:42 PM PDT 24
Finished Jul 21 06:58:26 PM PDT 24
Peak memory 206840 kb
Host smart-d414d5ff-6202-4bce-baf5-8663c3f34bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16741
28426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.1674128426
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.789936546
Short name T660
Test name
Test status
Simulation time 4177336507 ps
CPU time 40.15 seconds
Started Jul 21 06:56:44 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206968 kb
Host smart-227c2436-d2c5-4e9e-b361-9c0e9fe5f686
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=789936546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.789936546
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.3760832393
Short name T205
Test name
Test status
Simulation time 167996168 ps
CPU time 0.86 seconds
Started Jul 21 06:56:40 PM PDT 24
Finished Jul 21 06:56:42 PM PDT 24
Peak memory 206796 kb
Host smart-dfc980e7-7fbd-4ce4-a979-aa24dba93264
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3760832393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.3760832393
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.2991144007
Short name T641
Test name
Test status
Simulation time 150039904 ps
CPU time 0.77 seconds
Started Jul 21 06:56:40 PM PDT 24
Finished Jul 21 06:56:42 PM PDT 24
Peak memory 206664 kb
Host smart-51bda5e0-b75b-41ae-b5a2-7a606fe53bfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29911
44007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.2991144007
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.1046697268
Short name T2625
Test name
Test status
Simulation time 192748788 ps
CPU time 0.83 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:56:41 PM PDT 24
Peak memory 206684 kb
Host smart-e7e1d367-e6db-4b63-aa25-eb5806bac605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10466
97268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.1046697268
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.1192817458
Short name T626
Test name
Test status
Simulation time 174527948 ps
CPU time 0.76 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:56:38 PM PDT 24
Peak memory 206700 kb
Host smart-3979d518-5e2c-4e62-b735-7b1a9f647324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11928
17458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.1192817458
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.1308805208
Short name T494
Test name
Test status
Simulation time 198901091 ps
CPU time 0.85 seconds
Started Jul 21 06:56:38 PM PDT 24
Finished Jul 21 06:56:40 PM PDT 24
Peak memory 206684 kb
Host smart-132453d3-622a-4388-9f4e-ea1cd0f7e56f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
05208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.1308805208
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.1606523222
Short name T2153
Test name
Test status
Simulation time 194402256 ps
CPU time 0.84 seconds
Started Jul 21 06:56:39 PM PDT 24
Finished Jul 21 06:56:41 PM PDT 24
Peak memory 206660 kb
Host smart-d0b61fd6-701e-4b55-8b84-b5c1fdd4d1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16065
23222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.1606523222
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.2586216321
Short name T1027
Test name
Test status
Simulation time 199476649 ps
CPU time 0.88 seconds
Started Jul 21 06:56:37 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 206688 kb
Host smart-d5b31c4e-9c6a-4461-8c14-c4f485cf1631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25862
16321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.2586216321
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.671206362
Short name T2023
Test name
Test status
Simulation time 237343863 ps
CPU time 0.99 seconds
Started Jul 21 06:56:44 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206664 kb
Host smart-27eca090-a059-4a81-a1e6-4d824f3fc3a7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=671206362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.671206362
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.1428759077
Short name T861
Test name
Test status
Simulation time 143718028 ps
CPU time 0.79 seconds
Started Jul 21 06:56:42 PM PDT 24
Finished Jul 21 06:56:44 PM PDT 24
Peak memory 206632 kb
Host smart-8e9eb511-4182-4bde-91dc-7c65551a43b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14287
59077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.1428759077
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.3464913276
Short name T243
Test name
Test status
Simulation time 9494922441 ps
CPU time 22.07 seconds
Started Jul 21 06:56:51 PM PDT 24
Finished Jul 21 06:57:14 PM PDT 24
Peak memory 206932 kb
Host smart-bdf3b59b-ae26-47c3-bbb6-46c209f3be21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34649
13276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.3464913276
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.2502287074
Short name T1746
Test name
Test status
Simulation time 151182304 ps
CPU time 0.78 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206680 kb
Host smart-24fcc946-8b99-43d0-987f-e8707514c6a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25022
87074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.2502287074
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.2297319043
Short name T2322
Test name
Test status
Simulation time 222751191 ps
CPU time 0.89 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206672 kb
Host smart-6b0a8799-e0d7-4036-9159-a2ead77b6e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
19043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.2297319043
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.151904577
Short name T1221
Test name
Test status
Simulation time 239601544 ps
CPU time 0.88 seconds
Started Jul 21 06:56:51 PM PDT 24
Finished Jul 21 06:56:53 PM PDT 24
Peak memory 206372 kb
Host smart-d72a7e4d-d7df-4287-8258-df83f5848c62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15190
4577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.151904577
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.3852375379
Short name T301
Test name
Test status
Simulation time 169148537 ps
CPU time 0.83 seconds
Started Jul 21 06:56:41 PM PDT 24
Finished Jul 21 06:56:42 PM PDT 24
Peak memory 206688 kb
Host smart-3e60ddcb-ba70-4bea-9464-68de27ba436d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38523
75379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.3852375379
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.1853922505
Short name T1561
Test name
Test status
Simulation time 164827286 ps
CPU time 0.77 seconds
Started Jul 21 06:56:45 PM PDT 24
Finished Jul 21 06:56:47 PM PDT 24
Peak memory 206660 kb
Host smart-9de42c92-a6be-438c-a603-60d9b2fbfdd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18539
22505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.1853922505
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.2428828246
Short name T1834
Test name
Test status
Simulation time 153039485 ps
CPU time 0.83 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:44 PM PDT 24
Peak memory 206656 kb
Host smart-886d7551-0914-4411-b86f-5ab1ac3ed5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24288
28246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.2428828246
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.278773258
Short name T1162
Test name
Test status
Simulation time 165039834 ps
CPU time 0.84 seconds
Started Jul 21 06:56:42 PM PDT 24
Finished Jul 21 06:56:43 PM PDT 24
Peak memory 206668 kb
Host smart-e1d07263-fdbc-4c46-b723-973b42049622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27877
3258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.278773258
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.1470759094
Short name T2682
Test name
Test status
Simulation time 186222374 ps
CPU time 0.91 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206680 kb
Host smart-a6724eca-b39f-4995-9568-0cd2f9ff4417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14707
59094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.1470759094
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1902199745
Short name T1219
Test name
Test status
Simulation time 4367554320 ps
CPU time 119.1 seconds
Started Jul 21 06:56:51 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206584 kb
Host smart-d256f9fa-d5df-484e-a7d3-a20db69d1d15
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1902199745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1902199745
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.3378216397
Short name T1701
Test name
Test status
Simulation time 155600795 ps
CPU time 0.79 seconds
Started Jul 21 06:56:44 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206632 kb
Host smart-55ea6889-f4c3-4f01-afd5-121583ec025b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33782
16397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.3378216397
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.4242357034
Short name T2370
Test name
Test status
Simulation time 238765996 ps
CPU time 0.85 seconds
Started Jul 21 06:56:42 PM PDT 24
Finished Jul 21 06:56:43 PM PDT 24
Peak memory 206672 kb
Host smart-97356a80-343f-4909-b6b3-a4b10613907d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42423
57034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.4242357034
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.500910573
Short name T1208
Test name
Test status
Simulation time 503965635 ps
CPU time 1.32 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206668 kb
Host smart-b7fdd73e-b5d8-46f0-8b97-097a1505d3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50091
0573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.500910573
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3727624241
Short name T1
Test name
Test status
Simulation time 6090182841 ps
CPU time 42.3 seconds
Started Jul 21 06:56:45 PM PDT 24
Finished Jul 21 06:57:28 PM PDT 24
Peak memory 206896 kb
Host smart-35ee326a-e214-4598-b266-05372c4f0d9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37276
24241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3727624241
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.861851927
Short name T970
Test name
Test status
Simulation time 40113425 ps
CPU time 0.63 seconds
Started Jul 21 06:57:13 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 206700 kb
Host smart-22aac9e5-9655-4574-93af-fd0428879845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=861851927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.861851927
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.1192255667
Short name T2233
Test name
Test status
Simulation time 3983777267 ps
CPU time 4.35 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206736 kb
Host smart-e9a562a5-01ef-489d-9602-f2fa1db61830
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1192255667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.1192255667
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.781586277
Short name T2166
Test name
Test status
Simulation time 13415456087 ps
CPU time 12.27 seconds
Started Jul 21 06:56:43 PM PDT 24
Finished Jul 21 06:56:56 PM PDT 24
Peak memory 206848 kb
Host smart-4c4511a7-defd-4481-9368-152d90315c60
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=781586277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.781586277
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.1940715456
Short name T714
Test name
Test status
Simulation time 23504027313 ps
CPU time 22.81 seconds
Started Jul 21 06:56:45 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206940 kb
Host smart-5111d75c-0dae-4389-b8da-3acafdccf0aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1940715456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.1940715456
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.1564265894
Short name T2410
Test name
Test status
Simulation time 167243392 ps
CPU time 0.81 seconds
Started Jul 21 06:56:44 PM PDT 24
Finished Jul 21 06:56:45 PM PDT 24
Peak memory 206684 kb
Host smart-85e563c3-5da8-4128-8e44-307caae8949c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15642
65894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.1564265894
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3446350127
Short name T703
Test name
Test status
Simulation time 140787205 ps
CPU time 0.78 seconds
Started Jul 21 06:56:44 PM PDT 24
Finished Jul 21 06:56:46 PM PDT 24
Peak memory 206672 kb
Host smart-1e962c2e-eb03-4ab5-aedc-4e80d76d463b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34463
50127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3446350127
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.1974093009
Short name T552
Test name
Test status
Simulation time 365709958 ps
CPU time 1.22 seconds
Started Jul 21 06:56:42 PM PDT 24
Finished Jul 21 06:56:44 PM PDT 24
Peak memory 206652 kb
Host smart-26667e9b-da19-4b8d-8496-14208fa91c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19740
93009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.1974093009
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.321000019
Short name T91
Test name
Test status
Simulation time 948375560 ps
CPU time 2.04 seconds
Started Jul 21 06:56:51 PM PDT 24
Finished Jul 21 06:56:54 PM PDT 24
Peak memory 206712 kb
Host smart-227d242a-bac8-4530-9629-a7e1475397b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
0019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.321000019
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.2560717278
Short name T1095
Test name
Test status
Simulation time 18993150256 ps
CPU time 31.97 seconds
Started Jul 21 06:56:44 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206944 kb
Host smart-b63de712-1c1a-41aa-8530-94385cd35633
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25607
17278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.2560717278
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.2792355376
Short name T1161
Test name
Test status
Simulation time 412951798 ps
CPU time 1.27 seconds
Started Jul 21 06:56:46 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206684 kb
Host smart-b20c33c9-3212-4bb0-b334-15dac8f9b727
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27923
55376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.2792355376
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.1018737856
Short name T1138
Test name
Test status
Simulation time 162634652 ps
CPU time 0.77 seconds
Started Jul 21 06:56:47 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206668 kb
Host smart-43e7d27d-688c-4054-a5cc-7ba2d790efe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
37856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.1018737856
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.3277955817
Short name T345
Test name
Test status
Simulation time 74016107 ps
CPU time 0.77 seconds
Started Jul 21 06:56:48 PM PDT 24
Finished Jul 21 06:56:49 PM PDT 24
Peak memory 206644 kb
Host smart-4b3eceb6-d12b-4f91-a30c-1152e3fd3131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32779
55817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.3277955817
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.1539275854
Short name T867
Test name
Test status
Simulation time 782512744 ps
CPU time 2.06 seconds
Started Jul 21 06:56:46 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206812 kb
Host smart-1f849c2f-ea18-45c8-a948-e83c7853dd1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15392
75854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.1539275854
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.629760036
Short name T458
Test name
Test status
Simulation time 341860545 ps
CPU time 2.09 seconds
Started Jul 21 06:56:46 PM PDT 24
Finished Jul 21 06:56:49 PM PDT 24
Peak memory 206780 kb
Host smart-d5012725-e050-4617-8d9d-2afe2d7374b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62976
0036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.629760036
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.3445325989
Short name T769
Test name
Test status
Simulation time 216751657 ps
CPU time 0.91 seconds
Started Jul 21 06:56:48 PM PDT 24
Finished Jul 21 06:56:49 PM PDT 24
Peak memory 206664 kb
Host smart-260a6f31-9b23-4dc2-aa3f-a02b9f933298
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34453
25989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.3445325989
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.2354329633
Short name T2183
Test name
Test status
Simulation time 179660735 ps
CPU time 0.8 seconds
Started Jul 21 06:56:49 PM PDT 24
Finished Jul 21 06:56:51 PM PDT 24
Peak memory 206680 kb
Host smart-038946f3-1633-482a-b342-689f353ebca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23543
29633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.2354329633
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3111906757
Short name T1596
Test name
Test status
Simulation time 196483385 ps
CPU time 0.79 seconds
Started Jul 21 06:56:46 PM PDT 24
Finished Jul 21 06:56:48 PM PDT 24
Peak memory 206632 kb
Host smart-26ddf375-b822-48dc-b920-ac9c4370ffdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31119
06757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3111906757
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.749497282
Short name T1677
Test name
Test status
Simulation time 8706847020 ps
CPU time 25.84 seconds
Started Jul 21 06:56:48 PM PDT 24
Finished Jul 21 06:57:14 PM PDT 24
Peak memory 206908 kb
Host smart-abc568d6-25c4-4ac4-abf5-71398388df21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74949
7282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.749497282
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.3740188315
Short name T1758
Test name
Test status
Simulation time 232445097 ps
CPU time 0.91 seconds
Started Jul 21 06:56:51 PM PDT 24
Finished Jul 21 06:56:53 PM PDT 24
Peak memory 206652 kb
Host smart-2c946561-cf71-4468-80b9-b5745b1a20a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37401
88315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.3740188315
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.1327390808
Short name T1739
Test name
Test status
Simulation time 23382310226 ps
CPU time 23.67 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:57:21 PM PDT 24
Peak memory 206796 kb
Host smart-c9dfaef2-074a-4f8c-8fe1-93c13a721ea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13273
90808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.1327390808
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.1872261486
Short name T1458
Test name
Test status
Simulation time 3327116418 ps
CPU time 3.95 seconds
Started Jul 21 06:56:50 PM PDT 24
Finished Jul 21 06:56:55 PM PDT 24
Peak memory 206740 kb
Host smart-4fab10eb-379f-4a5a-a16b-73d4547fc54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18722
61486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.1872261486
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.248912130
Short name T1010
Test name
Test status
Simulation time 10763198703 ps
CPU time 80.64 seconds
Started Jul 21 06:56:48 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206904 kb
Host smart-eb9f1942-a4c1-4e24-9cc7-7d86e9d33ac8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891
2130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.248912130
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.1850710337
Short name T1708
Test name
Test status
Simulation time 2858217790 ps
CPU time 19.79 seconds
Started Jul 21 06:56:47 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206936 kb
Host smart-61b4535d-2ed0-468c-8309-324e1e794e18
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1850710337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.1850710337
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.2477102576
Short name T2141
Test name
Test status
Simulation time 275415110 ps
CPU time 0.91 seconds
Started Jul 21 06:56:52 PM PDT 24
Finished Jul 21 06:56:54 PM PDT 24
Peak memory 206668 kb
Host smart-af08d4ab-5f6e-4978-95d6-00ac1b14ebb1
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2477102576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.2477102576
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.3251218237
Short name T1504
Test name
Test status
Simulation time 193760447 ps
CPU time 0.88 seconds
Started Jul 21 06:56:47 PM PDT 24
Finished Jul 21 06:56:49 PM PDT 24
Peak memory 206656 kb
Host smart-558dff1c-2a0e-437d-9311-9bfe3fe137b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32512
18237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.3251218237
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.1757769089
Short name T1545
Test name
Test status
Simulation time 5581706736 ps
CPU time 50.03 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:57:46 PM PDT 24
Peak memory 206904 kb
Host smart-42b262fb-85ac-4a73-ae72-0754b80b73c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17577
69089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.1757769089
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.1219424063
Short name T2203
Test name
Test status
Simulation time 5727878140 ps
CPU time 158.42 seconds
Started Jul 21 06:56:46 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206876 kb
Host smart-3c35c899-8c47-4dd3-9b54-c33917adf73b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1219424063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.1219424063
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1862632742
Short name T518
Test name
Test status
Simulation time 155199771 ps
CPU time 0.8 seconds
Started Jul 21 06:56:52 PM PDT 24
Finished Jul 21 06:56:53 PM PDT 24
Peak memory 206668 kb
Host smart-d4768ebc-c941-4031-a54b-5fef814edefa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1862632742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1862632742
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.162360877
Short name T374
Test name
Test status
Simulation time 145403104 ps
CPU time 0.81 seconds
Started Jul 21 06:57:00 PM PDT 24
Finished Jul 21 06:57:02 PM PDT 24
Peak memory 206540 kb
Host smart-dbf9d5c0-b351-40d9-bc51-0bc0df439e5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16236
0877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.162360877
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.2124126192
Short name T2737
Test name
Test status
Simulation time 194582672 ps
CPU time 0.81 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206660 kb
Host smart-f3e0be59-0bf5-424c-9b84-02e73758c8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21241
26192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.2124126192
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.3642655330
Short name T625
Test name
Test status
Simulation time 193240014 ps
CPU time 0.86 seconds
Started Jul 21 06:56:53 PM PDT 24
Finished Jul 21 06:56:55 PM PDT 24
Peak memory 206668 kb
Host smart-13630eb5-c3d6-4d3e-8352-32e1dd4ec148
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36426
55330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.3642655330
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.1016110785
Short name T338
Test name
Test status
Simulation time 165376909 ps
CPU time 0.84 seconds
Started Jul 21 06:56:52 PM PDT 24
Finished Jul 21 06:56:53 PM PDT 24
Peak memory 206656 kb
Host smart-9854f53b-e20c-4b73-b07b-40e8de7d049c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10161
10785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.1016110785
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.2653903242
Short name T1386
Test name
Test status
Simulation time 191365227 ps
CPU time 0.78 seconds
Started Jul 21 06:56:52 PM PDT 24
Finished Jul 21 06:56:53 PM PDT 24
Peak memory 206608 kb
Host smart-78ea6caa-d266-4a11-9c35-d94b81174eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
03242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.2653903242
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.471369606
Short name T2086
Test name
Test status
Simulation time 181759087 ps
CPU time 0.88 seconds
Started Jul 21 06:56:53 PM PDT 24
Finished Jul 21 06:56:55 PM PDT 24
Peak memory 206668 kb
Host smart-70bb7569-0ef7-4b22-8705-d18ea0271808
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47136
9606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.471369606
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.674863075
Short name T1246
Test name
Test status
Simulation time 237025272 ps
CPU time 0.93 seconds
Started Jul 21 06:56:52 PM PDT 24
Finished Jul 21 06:56:54 PM PDT 24
Peak memory 206612 kb
Host smart-03a7f407-bfa0-4613-9898-824dbf2c4214
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=674863075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.674863075
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3955422582
Short name T185
Test name
Test status
Simulation time 157654223 ps
CPU time 0.82 seconds
Started Jul 21 06:57:00 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206616 kb
Host smart-e016cb3a-9ee9-4276-9b0f-9844008d13bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39554
22582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3955422582
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.3328617613
Short name T29
Test name
Test status
Simulation time 35048504 ps
CPU time 0.66 seconds
Started Jul 21 06:56:57 PM PDT 24
Finished Jul 21 06:56:59 PM PDT 24
Peak memory 206632 kb
Host smart-de5feabc-6a67-40b0-9710-d6ccc400a4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33286
17613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.3328617613
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.3515780269
Short name T499
Test name
Test status
Simulation time 20485714707 ps
CPU time 46.51 seconds
Started Jul 21 06:56:52 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206940 kb
Host smart-ac3b365c-a545-409c-ae2b-4d94e41e905d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35157
80269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.3515780269
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.1749393702
Short name T728
Test name
Test status
Simulation time 182240243 ps
CPU time 0.88 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:56:56 PM PDT 24
Peak memory 206672 kb
Host smart-98749635-f15d-40bf-953b-9ef090a04299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17493
93702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.1749393702
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.945402494
Short name T358
Test name
Test status
Simulation time 197018767 ps
CPU time 0.9 seconds
Started Jul 21 06:56:52 PM PDT 24
Finished Jul 21 06:56:54 PM PDT 24
Peak memory 206668 kb
Host smart-2446592d-09ad-4d45-9fa9-3d0a001d5817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94540
2494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.945402494
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.2085859703
Short name T2296
Test name
Test status
Simulation time 169879029 ps
CPU time 0.86 seconds
Started Jul 21 06:57:00 PM PDT 24
Finished Jul 21 06:57:02 PM PDT 24
Peak memory 206628 kb
Host smart-54d80fa0-87f5-478e-9fac-64822ada1480
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20858
59703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.2085859703
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.29218430
Short name T400
Test name
Test status
Simulation time 170699852 ps
CPU time 0.83 seconds
Started Jul 21 06:56:54 PM PDT 24
Finished Jul 21 06:56:55 PM PDT 24
Peak memory 206664 kb
Host smart-e7e0c857-ec21-46b5-ba6e-1223bc84e48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29218
430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.29218430
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.2811813976
Short name T551
Test name
Test status
Simulation time 157382377 ps
CPU time 0.77 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:56:58 PM PDT 24
Peak memory 206636 kb
Host smart-50f25c2a-1e6b-403c-889d-ba64c4077530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
13976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.2811813976
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.1209443819
Short name T2730
Test name
Test status
Simulation time 184671002 ps
CPU time 0.86 seconds
Started Jul 21 06:56:54 PM PDT 24
Finished Jul 21 06:56:56 PM PDT 24
Peak memory 206692 kb
Host smart-11ab3e40-dbec-4f51-9116-280cad7743e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12094
43819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.1209443819
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.1794966314
Short name T2210
Test name
Test status
Simulation time 187017027 ps
CPU time 0.78 seconds
Started Jul 21 06:56:58 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206692 kb
Host smart-50d8d9a6-16c3-44de-823f-e010669e605a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17949
66314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.1794966314
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.3017816444
Short name T764
Test name
Test status
Simulation time 227180615 ps
CPU time 0.92 seconds
Started Jul 21 06:57:00 PM PDT 24
Finished Jul 21 06:57:02 PM PDT 24
Peak memory 206620 kb
Host smart-ef9e2030-bd6c-4e2f-856f-4ac25fdd008c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30178
16444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.3017816444
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.392390370
Short name T1216
Test name
Test status
Simulation time 4828631864 ps
CPU time 37.3 seconds
Started Jul 21 06:57:00 PM PDT 24
Finished Jul 21 06:57:38 PM PDT 24
Peak memory 206756 kb
Host smart-101cd49c-f258-4ca5-a0c3-e5991ea05b8f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=392390370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.392390370
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.649824534
Short name T387
Test name
Test status
Simulation time 215604372 ps
CPU time 0.91 seconds
Started Jul 21 06:56:54 PM PDT 24
Finished Jul 21 06:56:55 PM PDT 24
Peak memory 206692 kb
Host smart-0361995a-8195-45ff-87d0-809a997774e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64982
4534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.649824534
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.1056169270
Short name T2556
Test name
Test status
Simulation time 176028915 ps
CPU time 0.85 seconds
Started Jul 21 06:56:57 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206656 kb
Host smart-79461a40-45cc-46e4-a3c4-ef7cf0266dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
69270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.1056169270
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.3652192102
Short name T2000
Test name
Test status
Simulation time 575614113 ps
CPU time 1.55 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206656 kb
Host smart-f684dfbb-2ddf-4a5b-ae81-9846a6f5ea49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36521
92102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.3652192102
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.243614798
Short name T537
Test name
Test status
Simulation time 6538942501 ps
CPU time 47.58 seconds
Started Jul 21 06:56:58 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206840 kb
Host smart-5c1e2067-90be-4305-8ea6-0ce3eea15518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24361
4798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.243614798
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.792858244
Short name T819
Test name
Test status
Simulation time 45488441 ps
CPU time 0.72 seconds
Started Jul 21 06:57:01 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206732 kb
Host smart-fe57f29a-7f1b-4349-aaf8-b8865dd347fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=792858244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.792858244
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.1747284093
Short name T2358
Test name
Test status
Simulation time 3476049012 ps
CPU time 4.45 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206888 kb
Host smart-7774a746-a68d-4bd4-8f93-e06f44c583a9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1747284093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.1747284093
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.668110677
Short name T1851
Test name
Test status
Simulation time 13325600790 ps
CPU time 12.29 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206884 kb
Host smart-ecc78ff7-9a93-4b21-acb8-0a715d4c9430
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=668110677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.668110677
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.1397873657
Short name T1418
Test name
Test status
Simulation time 23327941786 ps
CPU time 24.87 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:57:22 PM PDT 24
Peak memory 206792 kb
Host smart-d5e9964d-e3e6-4b67-9427-ef82548d3b9a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1397873657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.1397873657
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.3768983755
Short name T2365
Test name
Test status
Simulation time 199024482 ps
CPU time 0.84 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:56:59 PM PDT 24
Peak memory 206708 kb
Host smart-9867df2d-5a71-453f-9f98-df05f19f0d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37689
83755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.3768983755
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.4021866015
Short name T2035
Test name
Test status
Simulation time 227752797 ps
CPU time 0.84 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:56:58 PM PDT 24
Peak memory 206704 kb
Host smart-fecd7399-6408-443e-8c28-bccf45816f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
66015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.4021866015
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.1038624918
Short name T2348
Test name
Test status
Simulation time 514758503 ps
CPU time 1.5 seconds
Started Jul 21 06:57:03 PM PDT 24
Finished Jul 21 06:57:05 PM PDT 24
Peak memory 206676 kb
Host smart-163dce00-b74e-4e0f-99cd-7e88932b8e62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10386
24918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.1038624918
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.1880408299
Short name T1969
Test name
Test status
Simulation time 1117433804 ps
CPU time 2.41 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206756 kb
Host smart-bb9e1be0-0437-4d1c-9f81-58473072a3ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18804
08299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.1880408299
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.2258681091
Short name T85
Test name
Test status
Simulation time 17121020377 ps
CPU time 32.78 seconds
Started Jul 21 06:56:57 PM PDT 24
Finished Jul 21 06:57:32 PM PDT 24
Peak memory 206876 kb
Host smart-18d394bb-7a77-4436-833a-ca94d1fd3e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22586
81091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.2258681091
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.591057464
Short name T1136
Test name
Test status
Simulation time 373978010 ps
CPU time 1.07 seconds
Started Jul 21 06:57:18 PM PDT 24
Finished Jul 21 06:57:19 PM PDT 24
Peak memory 206660 kb
Host smart-b912cd38-df2a-401c-9cc2-4a741baf0f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59105
7464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.591057464
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.1222967040
Short name T1253
Test name
Test status
Simulation time 133741656 ps
CPU time 0.77 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:56:57 PM PDT 24
Peak memory 206664 kb
Host smart-f82745c9-df2f-4200-99d7-6251d4736411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12229
67040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.1222967040
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3365036447
Short name T2715
Test name
Test status
Simulation time 36293710 ps
CPU time 0.65 seconds
Started Jul 21 06:56:57 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206644 kb
Host smart-de38c6a1-4e33-4c55-9021-ae0eaaacf4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33650
36447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3365036447
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.1238432938
Short name T2294
Test name
Test status
Simulation time 1013453382 ps
CPU time 2.34 seconds
Started Jul 21 06:57:14 PM PDT 24
Finished Jul 21 06:57:18 PM PDT 24
Peak memory 206748 kb
Host smart-c5a6fac7-7181-4dcc-9724-c7c71d128aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12384
32938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.1238432938
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.2325872963
Short name T1987
Test name
Test status
Simulation time 174927942 ps
CPU time 1.84 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:56:59 PM PDT 24
Peak memory 206824 kb
Host smart-312c7795-d0f3-40a4-a0b7-7555698a1670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23258
72963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.2325872963
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.1356032890
Short name T1006
Test name
Test status
Simulation time 157392244 ps
CPU time 0.81 seconds
Started Jul 21 06:56:58 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206624 kb
Host smart-6ec3d5ca-4133-4dbf-8717-fc2719314287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13560
32890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.1356032890
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.3908054219
Short name T1477
Test name
Test status
Simulation time 151092438 ps
CPU time 0.76 seconds
Started Jul 21 06:57:14 PM PDT 24
Finished Jul 21 06:57:16 PM PDT 24
Peak memory 206656 kb
Host smart-7deaa534-5e49-49e4-8ad3-207fed0e256d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39080
54219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.3908054219
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.4032449546
Short name T1807
Test name
Test status
Simulation time 284188352 ps
CPU time 0.95 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:56:59 PM PDT 24
Peak memory 206700 kb
Host smart-dea1edc9-78c7-4861-954e-5bd7f510cf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40324
49546 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.4032449546
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.3518996930
Short name T2033
Test name
Test status
Simulation time 6691028328 ps
CPU time 186.16 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206872 kb
Host smart-40be5733-0608-4fc5-b87e-e8b654aeeff6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3518996930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.3518996930
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.2542306880
Short name T22
Test name
Test status
Simulation time 227676290 ps
CPU time 0.93 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:56:58 PM PDT 24
Peak memory 206692 kb
Host smart-3809d3f9-a7e3-481a-aebb-0f8912bd0496
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25423
06880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.2542306880
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.2419659013
Short name T1514
Test name
Test status
Simulation time 23354022541 ps
CPU time 24.78 seconds
Started Jul 21 06:57:14 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206784 kb
Host smart-a265cb5e-9e7b-482f-9327-fcb9856ebd27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24196
59013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.2419659013
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.3249134489
Short name T587
Test name
Test status
Simulation time 3284222072 ps
CPU time 3.72 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:57:02 PM PDT 24
Peak memory 206752 kb
Host smart-0ed0f9f2-73d4-402a-90c3-dad6d96f5118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32491
34489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.3249134489
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.1332852623
Short name T1917
Test name
Test status
Simulation time 6882114152 ps
CPU time 51.1 seconds
Started Jul 21 06:56:57 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206896 kb
Host smart-e478db5d-2629-44f9-a77e-00e970e8924b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13328
52623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.1332852623
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.2636822372
Short name T74
Test name
Test status
Simulation time 5136246868 ps
CPU time 38.27 seconds
Started Jul 21 06:56:56 PM PDT 24
Finished Jul 21 06:57:36 PM PDT 24
Peak memory 206888 kb
Host smart-ededd2a3-aa5f-4915-8e65-4ab064acbefa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2636822372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.2636822372
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.496780847
Short name T2257
Test name
Test status
Simulation time 303866817 ps
CPU time 0.94 seconds
Started Jul 21 06:57:14 PM PDT 24
Finished Jul 21 06:57:16 PM PDT 24
Peak memory 206660 kb
Host smart-9ef4d1dd-990d-438d-875f-3961f62c5487
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=496780847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.496780847
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.1007466536
Short name T1085
Test name
Test status
Simulation time 205490178 ps
CPU time 0.87 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:56:58 PM PDT 24
Peak memory 206680 kb
Host smart-cbd082b2-8d31-4885-ab43-2517887de859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10074
66536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.1007466536
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.2877672091
Short name T414
Test name
Test status
Simulation time 3354047596 ps
CPU time 30.93 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:57:28 PM PDT 24
Peak memory 206928 kb
Host smart-fd2f0ce0-3c88-4da5-89bf-06493df15484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
72091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.2877672091
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.869440282
Short name T1764
Test name
Test status
Simulation time 5326603244 ps
CPU time 50.42 seconds
Started Jul 21 06:56:55 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206952 kb
Host smart-09f130c0-6899-4b4d-b5f4-3a94816c3c1d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=869440282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.869440282
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.1541099234
Short name T1380
Test name
Test status
Simulation time 155144502 ps
CPU time 0.81 seconds
Started Jul 21 06:56:59 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206680 kb
Host smart-972aa255-e1dd-41af-8ebe-686121e6f3ce
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1541099234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.1541099234
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.3205503024
Short name T2615
Test name
Test status
Simulation time 143527814 ps
CPU time 0.76 seconds
Started Jul 21 06:57:04 PM PDT 24
Finished Jul 21 06:57:06 PM PDT 24
Peak memory 206788 kb
Host smart-e20b3aef-a9aa-4cd1-bdbe-6c366f7d0699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32055
03024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.3205503024
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1755929086
Short name T113
Test name
Test status
Simulation time 244685615 ps
CPU time 0.91 seconds
Started Jul 21 06:57:01 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206668 kb
Host smart-d2243724-f4ac-435a-a8e2-3c96fd20e481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17559
29086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1755929086
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3155259992
Short name T1473
Test name
Test status
Simulation time 148143599 ps
CPU time 0.82 seconds
Started Jul 21 06:57:02 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206632 kb
Host smart-816ea9cd-7aec-4db9-98b3-3bcc05ec829e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31552
59992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3155259992
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.1024394183
Short name T676
Test name
Test status
Simulation time 172942281 ps
CPU time 0.81 seconds
Started Jul 21 06:57:03 PM PDT 24
Finished Jul 21 06:57:05 PM PDT 24
Peak memory 206664 kb
Host smart-020c6786-001b-4d40-a0ac-f8c11cce441e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10243
94183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.1024394183
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.394202939
Short name T540
Test name
Test status
Simulation time 165450353 ps
CPU time 0.8 seconds
Started Jul 21 06:57:06 PM PDT 24
Finished Jul 21 06:57:08 PM PDT 24
Peak memory 206680 kb
Host smart-da25c8e5-1777-49df-acc9-1d36bb2aae24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39420
2939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.394202939
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.69564478
Short name T559
Test name
Test status
Simulation time 161546764 ps
CPU time 0.76 seconds
Started Jul 21 06:57:02 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206664 kb
Host smart-786dc449-e2a7-4ab6-b3d8-5c9c83be4ba0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69564
478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.69564478
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.628827527
Short name T1990
Test name
Test status
Simulation time 246845360 ps
CPU time 1.14 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 206332 kb
Host smart-0c53aeec-9cf7-4cd5-8cbd-bd7861010a59
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=628827527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.628827527
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.1105810255
Short name T969
Test name
Test status
Simulation time 149366346 ps
CPU time 0.79 seconds
Started Jul 21 06:56:59 PM PDT 24
Finished Jul 21 06:57:00 PM PDT 24
Peak memory 206700 kb
Host smart-2dade4a5-b61c-40a4-ba47-a1699b616ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058
10255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.1105810255
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.2369249721
Short name T417
Test name
Test status
Simulation time 70761743 ps
CPU time 0.71 seconds
Started Jul 21 06:57:07 PM PDT 24
Finished Jul 21 06:57:08 PM PDT 24
Peak memory 206632 kb
Host smart-6d804d65-60e0-43f5-90c9-a4ff7c3c45d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23692
49721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.2369249721
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2542083013
Short name T1583
Test name
Test status
Simulation time 20213187076 ps
CPU time 47.84 seconds
Started Jul 21 06:56:59 PM PDT 24
Finished Jul 21 06:57:48 PM PDT 24
Peak memory 206980 kb
Host smart-30756353-f3bf-4741-899a-2479bec15378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25420
83013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2542083013
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.538491512
Short name T276
Test name
Test status
Simulation time 193854932 ps
CPU time 0.94 seconds
Started Jul 21 06:57:01 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206656 kb
Host smart-551807ea-9af7-4efc-9cdf-7acea808ad70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53849
1512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.538491512
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.4104892198
Short name T993
Test name
Test status
Simulation time 281003797 ps
CPU time 0.97 seconds
Started Jul 21 06:57:02 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206688 kb
Host smart-e841936a-c4a2-46e5-98b3-96115d91b2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41048
92198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.4104892198
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.4245324027
Short name T1460
Test name
Test status
Simulation time 200101743 ps
CPU time 0.93 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206564 kb
Host smart-729fc585-9a1d-4c87-ad8c-07165231185b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42453
24027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.4245324027
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.3627734630
Short name T2599
Test name
Test status
Simulation time 171765275 ps
CPU time 0.77 seconds
Started Jul 21 06:57:11 PM PDT 24
Finished Jul 21 06:57:13 PM PDT 24
Peak memory 206660 kb
Host smart-ab8bbb0e-ca08-41c4-a3ac-68154d0a275f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36277
34630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.3627734630
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.1910376402
Short name T845
Test name
Test status
Simulation time 203037273 ps
CPU time 0.95 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206560 kb
Host smart-5e5ddbe9-17e3-42a7-944c-8dfad918bf60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
76402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.1910376402
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.2653620470
Short name T1819
Test name
Test status
Simulation time 180508848 ps
CPU time 0.75 seconds
Started Jul 21 06:56:59 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206672 kb
Host smart-582f291a-713f-46a4-b4d6-953c64a7d787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26536
20470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.2653620470
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.1350650157
Short name T321
Test name
Test status
Simulation time 156058498 ps
CPU time 0.79 seconds
Started Jul 21 06:57:02 PM PDT 24
Finished Jul 21 06:57:04 PM PDT 24
Peak memory 206680 kb
Host smart-d83b73a8-a386-4af0-86fa-0a1e2ffe26d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13506
50157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.1350650157
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1951716844
Short name T1113
Test name
Test status
Simulation time 211381782 ps
CPU time 0.87 seconds
Started Jul 21 06:57:07 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206652 kb
Host smart-c28bd9c8-4ab8-40c1-a1c4-15f0fc0ef411
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19517
16844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1951716844
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.660618866
Short name T1372
Test name
Test status
Simulation time 3963726319 ps
CPU time 36.81 seconds
Started Jul 21 06:57:02 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206928 kb
Host smart-91e4a70b-65bd-4092-9093-f46f28349224
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=660618866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.660618866
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.558267538
Short name T1277
Test name
Test status
Simulation time 200584091 ps
CPU time 0.83 seconds
Started Jul 21 06:57:02 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206656 kb
Host smart-5207a603-c42d-4b82-80c1-e29749178481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55826
7538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.558267538
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.619569085
Short name T2601
Test name
Test status
Simulation time 172235384 ps
CPU time 0.83 seconds
Started Jul 21 06:57:01 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206636 kb
Host smart-94947cb7-334a-477e-8642-3f86a7dc7597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61956
9085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.619569085
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.2112134782
Short name T1852
Test name
Test status
Simulation time 781911841 ps
CPU time 1.72 seconds
Started Jul 21 06:57:00 PM PDT 24
Finished Jul 21 06:57:03 PM PDT 24
Peak memory 206848 kb
Host smart-60f497f4-460e-496c-9fdc-adc49dbff011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21121
34782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.2112134782
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.917730044
Short name T2620
Test name
Test status
Simulation time 5468877867 ps
CPU time 147.59 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:59:39 PM PDT 24
Peak memory 206872 kb
Host smart-39ff51d7-47bb-4d7f-9423-c64c07c5aee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91773
0044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.917730044
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.1443888046
Short name T2082
Test name
Test status
Simulation time 40021659 ps
CPU time 0.7 seconds
Started Jul 21 06:57:17 PM PDT 24
Finished Jul 21 06:57:18 PM PDT 24
Peak memory 206740 kb
Host smart-183c7bdf-7bff-4b4a-80ea-90d3809efb40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1443888046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.1443888046
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.392727827
Short name T1475
Test name
Test status
Simulation time 4302009028 ps
CPU time 4.94 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206912 kb
Host smart-a225159e-ecbf-4c3a-8a68-debe56c47683
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=392727827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.392727827
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.2324944970
Short name T1025
Test name
Test status
Simulation time 13389180900 ps
CPU time 14.7 seconds
Started Jul 21 06:57:03 PM PDT 24
Finished Jul 21 06:57:18 PM PDT 24
Peak memory 206784 kb
Host smart-9aaadc08-6820-4a78-8220-c190295f55fc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2324944970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.2324944970
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.1425711347
Short name T218
Test name
Test status
Simulation time 23404990456 ps
CPU time 24.26 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:34 PM PDT 24
Peak memory 206512 kb
Host smart-1334094f-da9a-4608-be43-a3308d5cb392
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1425711347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.1425711347
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.1334801532
Short name T2372
Test name
Test status
Simulation time 173688031 ps
CPU time 0.81 seconds
Started Jul 21 06:56:59 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206708 kb
Host smart-dcd9a5b6-563f-490f-bd04-6ea9c26c8577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13348
01532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.1334801532
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.1428046393
Short name T2101
Test name
Test status
Simulation time 158946353 ps
CPU time 0.84 seconds
Started Jul 21 06:56:59 PM PDT 24
Finished Jul 21 06:57:01 PM PDT 24
Peak memory 206676 kb
Host smart-96a24c2b-2e5e-448a-a534-d822ab5dd271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14280
46393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.1428046393
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.3920263671
Short name T759
Test name
Test status
Simulation time 713610933 ps
CPU time 1.91 seconds
Started Jul 21 06:57:02 PM PDT 24
Finished Jul 21 06:57:04 PM PDT 24
Peak memory 206740 kb
Host smart-275e99a0-2505-48ea-9266-13c794015072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39202
63671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.3920263671
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3394256561
Short name T20
Test name
Test status
Simulation time 1370876552 ps
CPU time 3.16 seconds
Started Jul 21 06:57:01 PM PDT 24
Finished Jul 21 06:57:05 PM PDT 24
Peak memory 206804 kb
Host smart-9da510d5-007b-4637-b01c-93b8617ed196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
56561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3394256561
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3929513195
Short name T1612
Test name
Test status
Simulation time 15390463301 ps
CPU time 28.13 seconds
Started Jul 21 06:57:04 PM PDT 24
Finished Jul 21 06:57:33 PM PDT 24
Peak memory 206960 kb
Host smart-b26ffd7b-ff0c-49ee-9635-11e449140dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39295
13195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3929513195
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.2900717491
Short name T2591
Test name
Test status
Simulation time 417497427 ps
CPU time 1.35 seconds
Started Jul 21 06:57:04 PM PDT 24
Finished Jul 21 06:57:06 PM PDT 24
Peak memory 206668 kb
Host smart-587ce492-ef9a-45ec-97f0-5ad42a6ca534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29007
17491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.2900717491
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.293904696
Short name T1637
Test name
Test status
Simulation time 154588565 ps
CPU time 0.84 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206684 kb
Host smart-9ae84bcd-1e17-4cc6-afb4-51e0ae5d7d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29390
4696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.293904696
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1051900962
Short name T1022
Test name
Test status
Simulation time 38605555 ps
CPU time 0.66 seconds
Started Jul 21 06:57:07 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206664 kb
Host smart-a7e91286-44d3-4eda-958a-942251f74e3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10519
00962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1051900962
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1330974156
Short name T453
Test name
Test status
Simulation time 187158767 ps
CPU time 2.28 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206796 kb
Host smart-aabfee38-f931-43dc-8df7-43e999a8c1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13309
74156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1330974156
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.1743312892
Short name T893
Test name
Test status
Simulation time 248879202 ps
CPU time 0.91 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206692 kb
Host smart-d106c389-dc8d-4e55-93be-04832d212327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17433
12892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.1743312892
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2565868119
Short name T648
Test name
Test status
Simulation time 224909423 ps
CPU time 0.83 seconds
Started Jul 21 06:57:09 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 206644 kb
Host smart-daa0aa73-2c78-4ec6-b001-1856aea26bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
68119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2565868119
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.690514511
Short name T1078
Test name
Test status
Simulation time 231132868 ps
CPU time 0.95 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206632 kb
Host smart-42232ee6-9967-47bb-b464-ddfb4f7e9ddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69051
4511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.690514511
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.112286361
Short name T1166
Test name
Test status
Simulation time 6598388589 ps
CPU time 64.39 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206944 kb
Host smart-85ef96b0-d369-477e-bc28-75c14a390ca8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=112286361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.112286361
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_iso_retraction.2805846876
Short name T2471
Test name
Test status
Simulation time 12939522765 ps
CPU time 114.9 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:59:03 PM PDT 24
Peak memory 206908 kb
Host smart-daa83d39-d2f2-4992-84d2-9aa8ff8f4b88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28058
46876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_iso_retraction.2805846876
Directory /workspace/24.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.875855634
Short name T2686
Test name
Test status
Simulation time 228224703 ps
CPU time 0.94 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206640 kb
Host smart-422f280e-606b-4fa8-b55e-2dc99827436f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87585
5634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.875855634
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.4265046042
Short name T967
Test name
Test status
Simulation time 23306258432 ps
CPU time 23.4 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:29 PM PDT 24
Peak memory 206804 kb
Host smart-069d8a34-bc7e-4552-a6c3-aa1cc65c5f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42650
46042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.4265046042
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.95793843
Short name T319
Test name
Test status
Simulation time 3287572805 ps
CPU time 3.54 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 206768 kb
Host smart-5981421d-967c-4182-adb6-badd3017a3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95793
843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.95793843
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.4274153082
Short name T887
Test name
Test status
Simulation time 5420118656 ps
CPU time 41.33 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206924 kb
Host smart-96bb4d5b-6fec-4ad4-a246-cbab218e9d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42741
53082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.4274153082
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.1656520421
Short name T1964
Test name
Test status
Simulation time 7883657943 ps
CPU time 75.04 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:58:20 PM PDT 24
Peak memory 206856 kb
Host smart-96148caa-4707-4927-9e00-feb7c1bd8812
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1656520421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.1656520421
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.714408698
Short name T2260
Test name
Test status
Simulation time 280626294 ps
CPU time 0.93 seconds
Started Jul 21 06:57:07 PM PDT 24
Finished Jul 21 06:57:08 PM PDT 24
Peak memory 206664 kb
Host smart-7f51aad3-43ac-4e85-b92c-e1b6131960ef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=714408698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.714408698
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.140869233
Short name T1566
Test name
Test status
Simulation time 233279574 ps
CPU time 0.91 seconds
Started Jul 21 06:57:07 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206668 kb
Host smart-fa3f917f-fa6b-4285-adc1-1774675ace44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14086
9233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.140869233
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.3072157846
Short name T134
Test name
Test status
Simulation time 5886841373 ps
CPU time 43.84 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206872 kb
Host smart-854e2c34-96af-4101-9847-7bcd46ed77cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30721
57846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.3072157846
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.1446191242
Short name T1501
Test name
Test status
Simulation time 4150547703 ps
CPU time 108.68 seconds
Started Jul 21 06:57:06 PM PDT 24
Finished Jul 21 06:58:56 PM PDT 24
Peak memory 206844 kb
Host smart-9b4d6f89-bb62-493f-ba49-994c3ca0f8b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1446191242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.1446191242
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.1315235330
Short name T2639
Test name
Test status
Simulation time 154630870 ps
CPU time 0.8 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:07 PM PDT 24
Peak memory 206668 kb
Host smart-3f666677-ac1f-4066-a862-ede277fa9199
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1315235330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.1315235330
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.4099432007
Short name T646
Test name
Test status
Simulation time 202337905 ps
CPU time 0.86 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206660 kb
Host smart-8ceb762c-0df2-4c30-9dd9-8926a0f32677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40994
32007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.4099432007
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.2967850237
Short name T104
Test name
Test status
Simulation time 210294514 ps
CPU time 0.91 seconds
Started Jul 21 06:57:09 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 206648 kb
Host smart-93812803-162a-4179-bafa-f99ce294a962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29678
50237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.2967850237
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.1057747561
Short name T393
Test name
Test status
Simulation time 147676567 ps
CPU time 0.8 seconds
Started Jul 21 06:57:05 PM PDT 24
Finished Jul 21 06:57:06 PM PDT 24
Peak memory 206692 kb
Host smart-6bb75ac5-1d11-4d7b-bc67-948e66b81d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10577
47561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.1057747561
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.1048336139
Short name T940
Test name
Test status
Simulation time 177336840 ps
CPU time 0.86 seconds
Started Jul 21 06:57:04 PM PDT 24
Finished Jul 21 06:57:05 PM PDT 24
Peak memory 206668 kb
Host smart-c1d6fc85-4ee7-4414-8dee-0d6acb83f333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10483
36139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.1048336139
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.2769091273
Short name T1912
Test name
Test status
Simulation time 186733443 ps
CPU time 0.9 seconds
Started Jul 21 06:57:07 PM PDT 24
Finished Jul 21 06:57:09 PM PDT 24
Peak memory 206672 kb
Host smart-f915777d-c44e-4bf3-bfd4-2c87e209bd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27690
91273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.2769091273
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.4270207226
Short name T403
Test name
Test status
Simulation time 212747453 ps
CPU time 0.88 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206652 kb
Host smart-0cb4070b-a71e-4cb8-846e-a583a78eadf3
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4270207226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.4270207226
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.1940205265
Short name T1350
Test name
Test status
Simulation time 143288059 ps
CPU time 0.8 seconds
Started Jul 21 06:57:09 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 206672 kb
Host smart-12be1089-9ea7-42c1-ab01-ebf35b05e609
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19402
05265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.1940205265
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.4007784584
Short name T1069
Test name
Test status
Simulation time 40179778 ps
CPU time 0.68 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206664 kb
Host smart-9d04f613-94c0-4ca3-a7cc-257401baddd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40077
84584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.4007784584
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.4137233406
Short name T995
Test name
Test status
Simulation time 19116347388 ps
CPU time 39.27 seconds
Started Jul 21 06:57:12 PM PDT 24
Finished Jul 21 06:57:52 PM PDT 24
Peak memory 207056 kb
Host smart-9515651a-73cf-4aa5-8b4f-7c21994b23f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41372
33406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.4137233406
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.67891561
Short name T2611
Test name
Test status
Simulation time 194571852 ps
CPU time 0.8 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206664 kb
Host smart-21abab7f-7378-4045-9a14-607caaf47d1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67891
561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.67891561
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.4122433647
Short name T2693
Test name
Test status
Simulation time 159207635 ps
CPU time 0.85 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206696 kb
Host smart-124e0fb4-2c10-446d-bdc6-3755af384eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41224
33647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.4122433647
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.3321283845
Short name T1932
Test name
Test status
Simulation time 178738764 ps
CPU time 0.88 seconds
Started Jul 21 06:57:11 PM PDT 24
Finished Jul 21 06:57:13 PM PDT 24
Peak memory 206676 kb
Host smart-9de07272-950e-4aff-9edb-65f41d5aebf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33212
83845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.3321283845
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.89757859
Short name T710
Test name
Test status
Simulation time 167549504 ps
CPU time 0.77 seconds
Started Jul 21 06:57:13 PM PDT 24
Finished Jul 21 06:57:14 PM PDT 24
Peak memory 206684 kb
Host smart-07bfcfb1-64d4-4aea-8dc0-6c2c551b7b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89757
859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.89757859
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.3232664836
Short name T663
Test name
Test status
Simulation time 206131016 ps
CPU time 0.82 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:10 PM PDT 24
Peak memory 206680 kb
Host smart-17dde580-3325-48a5-9254-154ae394e64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32326
64836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.3232664836
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.797218294
Short name T938
Test name
Test status
Simulation time 192963607 ps
CPU time 0.86 seconds
Started Jul 21 06:57:14 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 206676 kb
Host smart-7f8584e4-bb7f-4791-aea9-d8897f78b99c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79721
8294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.797218294
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.3506986270
Short name T1901
Test name
Test status
Simulation time 150997537 ps
CPU time 0.8 seconds
Started Jul 21 06:57:11 PM PDT 24
Finished Jul 21 06:57:13 PM PDT 24
Peak memory 206680 kb
Host smart-fb3cc64a-ae61-4809-a1ea-5ba665c8eeb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35069
86270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.3506986270
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.1208404528
Short name T1168
Test name
Test status
Simulation time 233279728 ps
CPU time 0.89 seconds
Started Jul 21 06:57:09 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 206672 kb
Host smart-5b65f3e0-1198-4696-9095-deb24e8e686c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12084
04528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.1208404528
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.279650237
Short name T1450
Test name
Test status
Simulation time 4167744217 ps
CPU time 29.21 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:38 PM PDT 24
Peak memory 206900 kb
Host smart-97b451ac-f86c-4bd4-b594-e078ff59bb51
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=279650237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.279650237
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.2745794757
Short name T1356
Test name
Test status
Simulation time 221551394 ps
CPU time 0.87 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206664 kb
Host smart-2d53df22-091e-45f5-9a21-096994219d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27457
94757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.2745794757
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.1907960474
Short name T2673
Test name
Test status
Simulation time 147609250 ps
CPU time 0.79 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206664 kb
Host smart-9048585f-663c-47cc-932d-9ab87fc705f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19079
60474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.1907960474
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.3969913455
Short name T340
Test name
Test status
Simulation time 1137189738 ps
CPU time 2.57 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:11 PM PDT 24
Peak memory 206768 kb
Host smart-961a3f4f-da2a-4c26-8dbd-c39d3d018175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39699
13455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.3969913455
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.2818461788
Short name T463
Test name
Test status
Simulation time 5385133886 ps
CPU time 37.22 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:49 PM PDT 24
Peak memory 206948 kb
Host smart-216f76dc-347d-4b80-843a-36d5c344b470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
61788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.2818461788
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.822490773
Short name T2380
Test name
Test status
Simulation time 44684994 ps
CPU time 0.67 seconds
Started Jul 21 06:57:26 PM PDT 24
Finished Jul 21 06:57:28 PM PDT 24
Peak memory 206728 kb
Host smart-49f84fda-dddb-432e-9a0b-088b4eb10391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=822490773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.822490773
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.806123368
Short name T1833
Test name
Test status
Simulation time 3521462052 ps
CPU time 3.98 seconds
Started Jul 21 06:57:12 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206992 kb
Host smart-f217978f-3fa7-4da1-8ee2-9675e898e575
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=806123368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.806123368
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.3692600718
Short name T2437
Test name
Test status
Simulation time 13453072735 ps
CPU time 12.55 seconds
Started Jul 21 06:57:11 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206948 kb
Host smart-9fdcf6ff-c31a-41b7-ba95-0bc420b0fb66
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3692600718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.3692600718
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.1874175581
Short name T469
Test name
Test status
Simulation time 23379191892 ps
CPU time 26.47 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:38 PM PDT 24
Peak memory 206804 kb
Host smart-1415f9b1-a5d4-4222-b05a-ead0b8a287f1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1874175581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.1874175581
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3817666444
Short name T299
Test name
Test status
Simulation time 167601384 ps
CPU time 0.8 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:13 PM PDT 24
Peak memory 206668 kb
Host smart-02d61d0c-16bd-416d-b8e6-d6256fdfcfd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38176
66444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3817666444
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1723203592
Short name T423
Test name
Test status
Simulation time 145727102 ps
CPU time 0.81 seconds
Started Jul 21 06:57:10 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206692 kb
Host smart-e1257eb7-afff-4d47-be8d-0ae9d3730bb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17232
03592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1723203592
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.3296157388
Short name T1902
Test name
Test status
Simulation time 609184785 ps
CPU time 1.89 seconds
Started Jul 21 06:57:11 PM PDT 24
Finished Jul 21 06:57:14 PM PDT 24
Peak memory 206832 kb
Host smart-c9d65056-4a97-40fd-9483-d1ca470b4951
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32961
57388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.3296157388
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.4211700362
Short name T774
Test name
Test status
Simulation time 1366832144 ps
CPU time 2.96 seconds
Started Jul 21 06:57:09 PM PDT 24
Finished Jul 21 06:57:13 PM PDT 24
Peak memory 206828 kb
Host smart-61680610-f3ba-4893-98a1-19710d1a7c70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42117
00362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.4211700362
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.4195086165
Short name T82
Test name
Test status
Simulation time 15244433382 ps
CPU time 30.25 seconds
Started Jul 21 06:57:08 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206860 kb
Host smart-0e720c70-f83c-4003-b122-b8c8dcaa1261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41950
86165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.4195086165
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.1682721216
Short name T381
Test name
Test status
Simulation time 469424745 ps
CPU time 1.37 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206700 kb
Host smart-7887cebf-5f75-4ef1-95e7-64983f1f3db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16827
21216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.1682721216
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.1921501690
Short name T904
Test name
Test status
Simulation time 158779137 ps
CPU time 0.79 seconds
Started Jul 21 06:57:15 PM PDT 24
Finished Jul 21 06:57:16 PM PDT 24
Peak memory 206652 kb
Host smart-372b7a5d-080e-4228-9ac7-41597e52c536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19215
01690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.1921501690
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.2043516347
Short name T1559
Test name
Test status
Simulation time 81184833 ps
CPU time 0.7 seconds
Started Jul 21 06:57:21 PM PDT 24
Finished Jul 21 06:57:23 PM PDT 24
Peak memory 206648 kb
Host smart-fc4cb61d-0a09-4797-8341-0fb391b2e066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20435
16347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.2043516347
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.4140918388
Short name T1713
Test name
Test status
Simulation time 739894114 ps
CPU time 1.84 seconds
Started Jul 21 06:57:18 PM PDT 24
Finished Jul 21 06:57:20 PM PDT 24
Peak memory 206752 kb
Host smart-dacabe08-1ff5-4eea-86c5-2f34bd41f7ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41409
18388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.4140918388
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.2992547218
Short name T2298
Test name
Test status
Simulation time 206341778 ps
CPU time 1.42 seconds
Started Jul 21 06:57:13 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 206808 kb
Host smart-50128a93-5da4-4b42-a9a5-cc0ba05d58e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29925
47218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.2992547218
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.983120041
Short name T1492
Test name
Test status
Simulation time 230003928 ps
CPU time 0.88 seconds
Started Jul 21 06:57:13 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 206672 kb
Host smart-cea44bf3-970d-48ce-afbe-159efc779f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98312
0041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.983120041
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.2822453557
Short name T503
Test name
Test status
Simulation time 142722059 ps
CPU time 0.73 seconds
Started Jul 21 06:57:15 PM PDT 24
Finished Jul 21 06:57:16 PM PDT 24
Peak memory 206688 kb
Host smart-385bf660-bb13-417c-a2ce-2f0c497585fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28224
53557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.2822453557
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.1114524289
Short name T832
Test name
Test status
Simulation time 172144286 ps
CPU time 0.85 seconds
Started Jul 21 06:57:13 PM PDT 24
Finished Jul 21 06:57:15 PM PDT 24
Peak memory 206680 kb
Host smart-7f98af2a-0dc0-4dae-b2e8-a87616dd20a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11145
24289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.1114524289
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_invalid_sync.751706520
Short name T93
Test name
Test status
Simulation time 8705895672 ps
CPU time 246.99 seconds
Started Jul 21 06:57:19 PM PDT 24
Finished Jul 21 07:01:26 PM PDT 24
Peak memory 206856 kb
Host smart-83f8ff2a-11e1-4877-8b2d-96b53e89f032
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=751706520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_invalid_sync.751706520
Directory /workspace/25.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.4147015526
Short name T1616
Test name
Test status
Simulation time 12530361743 ps
CPU time 46.41 seconds
Started Jul 21 06:57:13 PM PDT 24
Finished Jul 21 06:58:00 PM PDT 24
Peak memory 206896 kb
Host smart-3a761dcd-db19-4492-a7d0-01501a578df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41470
15526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.4147015526
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.2556361160
Short name T2303
Test name
Test status
Simulation time 156166520 ps
CPU time 0.75 seconds
Started Jul 21 06:57:18 PM PDT 24
Finished Jul 21 06:57:19 PM PDT 24
Peak memory 206668 kb
Host smart-7b0f8949-dafb-4d15-85f1-60917e00f71f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25563
61160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.2556361160
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.491943321
Short name T1183
Test name
Test status
Simulation time 23347254219 ps
CPU time 26.25 seconds
Started Jul 21 06:57:14 PM PDT 24
Finished Jul 21 06:57:41 PM PDT 24
Peak memory 206808 kb
Host smart-5e848a26-3f93-4ceb-8bff-23593b0561c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49194
3321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.491943321
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.586710821
Short name T917
Test name
Test status
Simulation time 3277849958 ps
CPU time 4.52 seconds
Started Jul 21 06:57:13 PM PDT 24
Finished Jul 21 06:57:18 PM PDT 24
Peak memory 206724 kb
Host smart-53073f53-c68e-4bc3-91b2-f9c1fb38711c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58671
0821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.586710821
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.3368409778
Short name T2553
Test name
Test status
Simulation time 9097826208 ps
CPU time 63.29 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206832 kb
Host smart-63c9a64b-aa4a-43ac-a022-0c3e6205ee08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33684
09778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.3368409778
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.820340173
Short name T1643
Test name
Test status
Simulation time 4809183284 ps
CPU time 137.02 seconds
Started Jul 21 06:57:14 PM PDT 24
Finished Jul 21 06:59:32 PM PDT 24
Peak memory 206904 kb
Host smart-335d481d-95e7-495c-b96e-0f8f89bc5d37
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=820340173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.820340173
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.3987728820
Short name T2031
Test name
Test status
Simulation time 263988854 ps
CPU time 0.93 seconds
Started Jul 21 06:57:15 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206664 kb
Host smart-7a9d4ed1-df15-42f7-9fc4-7b8df01fba3f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3987728820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.3987728820
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.858997789
Short name T1808
Test name
Test status
Simulation time 234522806 ps
CPU time 0.94 seconds
Started Jul 21 06:57:12 PM PDT 24
Finished Jul 21 06:57:14 PM PDT 24
Peak memory 206636 kb
Host smart-fad94a25-3327-4ef1-afa7-d3ba0a66ebaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85899
7789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.858997789
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.4066660956
Short name T1934
Test name
Test status
Simulation time 6685880242 ps
CPU time 190.49 seconds
Started Jul 21 06:57:15 PM PDT 24
Finished Jul 21 07:00:26 PM PDT 24
Peak memory 206864 kb
Host smart-9dccfc57-1716-4e99-9ec7-7cb88afd8c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40666
60956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.4066660956
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.3145032196
Short name T1304
Test name
Test status
Simulation time 4330692017 ps
CPU time 40.16 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206760 kb
Host smart-e31d6ff1-0bd5-45d0-a438-6250acdd53ba
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3145032196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.3145032196
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.3102653042
Short name T1288
Test name
Test status
Simulation time 161431664 ps
CPU time 0.78 seconds
Started Jul 21 06:57:16 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206676 kb
Host smart-c7613c7b-8f72-44bf-98b0-71a535a4529e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3102653042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.3102653042
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.2663930703
Short name T2422
Test name
Test status
Simulation time 154464071 ps
CPU time 0.87 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206560 kb
Host smart-2f325574-66c5-4aeb-b7f0-f9a77903ac15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26639
30703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.2663930703
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.4261357633
Short name T128
Test name
Test status
Simulation time 181095930 ps
CPU time 0.83 seconds
Started Jul 21 06:57:15 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206664 kb
Host smart-16a27da9-b94b-40e0-a5d2-380c9f10aa96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42613
57633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.4261357633
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.3422764820
Short name T1429
Test name
Test status
Simulation time 197127711 ps
CPU time 0.8 seconds
Started Jul 21 06:57:15 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206672 kb
Host smart-bc6c6b98-30fd-4229-8015-9ce0e1aec4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34227
64820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.3422764820
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.2141505308
Short name T1562
Test name
Test status
Simulation time 171350853 ps
CPU time 0.74 seconds
Started Jul 21 06:57:16 PM PDT 24
Finished Jul 21 06:57:17 PM PDT 24
Peak memory 206672 kb
Host smart-b65fa6f6-449f-4be4-8cd5-50f26367134f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21415
05308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.2141505308
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.772910551
Short name T2212
Test name
Test status
Simulation time 227072273 ps
CPU time 0.83 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206568 kb
Host smart-aeb16d41-c917-4d13-8fd1-1dd29e4a5b66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77291
0551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.772910551
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.595133012
Short name T770
Test name
Test status
Simulation time 153517706 ps
CPU time 0.79 seconds
Started Jul 21 06:57:19 PM PDT 24
Finished Jul 21 06:57:20 PM PDT 24
Peak memory 206668 kb
Host smart-02a5b2c7-9b46-4251-afab-0da79d5e9114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59513
3012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.595133012
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2400574848
Short name T2683
Test name
Test status
Simulation time 264895455 ps
CPU time 1.02 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206568 kb
Host smart-f3e47741-feec-4ef1-845e-0b5fb11726bc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2400574848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2400574848
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.3496373529
Short name T1047
Test name
Test status
Simulation time 136276479 ps
CPU time 0.72 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:57:28 PM PDT 24
Peak memory 206560 kb
Host smart-d036fea3-0f0e-484c-abd9-9915dedd3146
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
73529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.3496373529
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.2669783856
Short name T454
Test name
Test status
Simulation time 59063456 ps
CPU time 0.66 seconds
Started Jul 21 06:57:17 PM PDT 24
Finished Jul 21 06:57:18 PM PDT 24
Peak memory 206672 kb
Host smart-60847568-074b-4528-a46c-541835c8559a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26697
83856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.2669783856
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.2161762866
Short name T2647
Test name
Test status
Simulation time 6469210091 ps
CPU time 15.33 seconds
Started Jul 21 06:57:19 PM PDT 24
Finished Jul 21 06:57:34 PM PDT 24
Peak memory 206892 kb
Host smart-a0f7cc08-07a9-466c-b8e7-28e3d43e26d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21617
62866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.2161762866
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.1718052794
Short name T2618
Test name
Test status
Simulation time 181981267 ps
CPU time 0.84 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:22 PM PDT 24
Peak memory 206684 kb
Host smart-034d876d-c67e-4ea0-8d6f-119ac10f07e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17180
52794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.1718052794
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.2514911746
Short name T1376
Test name
Test status
Simulation time 245046048 ps
CPU time 0.91 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:22 PM PDT 24
Peak memory 206684 kb
Host smart-f6a6c8bf-bfb7-44fb-a65c-a3c50339c51c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25149
11746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.2514911746
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.2860723889
Short name T2155
Test name
Test status
Simulation time 183407843 ps
CPU time 0.82 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:21 PM PDT 24
Peak memory 206664 kb
Host smart-f1b7d40b-7e06-4099-a961-def275f1c797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28607
23889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.2860723889
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.1027792911
Short name T2470
Test name
Test status
Simulation time 220412775 ps
CPU time 0.94 seconds
Started Jul 21 06:57:25 PM PDT 24
Finished Jul 21 06:57:27 PM PDT 24
Peak memory 206664 kb
Host smart-641e6d4a-6339-4a3c-a703-142c0ad301fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10277
92911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.1027792911
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.778673187
Short name T1922
Test name
Test status
Simulation time 191467828 ps
CPU time 0.8 seconds
Started Jul 21 06:57:21 PM PDT 24
Finished Jul 21 06:57:23 PM PDT 24
Peak memory 206684 kb
Host smart-712a6ac6-0c2f-43cb-a73d-82efb13e1c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77867
3187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.778673187
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.1946201590
Short name T77
Test name
Test status
Simulation time 220606694 ps
CPU time 0.82 seconds
Started Jul 21 06:57:19 PM PDT 24
Finished Jul 21 06:57:20 PM PDT 24
Peak memory 206704 kb
Host smart-34322e46-deae-45f4-97d0-aa88e5dd36ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19462
01590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.1946201590
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.3624939537
Short name T2745
Test name
Test status
Simulation time 155840838 ps
CPU time 0.77 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:21 PM PDT 24
Peak memory 206652 kb
Host smart-27823030-f2ba-4434-b384-040f7060aac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
39537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.3624939537
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.756671089
Short name T2195
Test name
Test status
Simulation time 245145652 ps
CPU time 0.97 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:22 PM PDT 24
Peak memory 206680 kb
Host smart-11979562-f225-4fd6-bd59-d7dbceda2675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75667
1089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.756671089
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2212817107
Short name T805
Test name
Test status
Simulation time 6713166293 ps
CPU time 64.59 seconds
Started Jul 21 06:57:21 PM PDT 24
Finished Jul 21 06:58:26 PM PDT 24
Peak memory 206624 kb
Host smart-4eb660ec-69a1-40b7-b535-a6b3649f3fec
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2212817107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2212817107
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.3909568074
Short name T708
Test name
Test status
Simulation time 179385126 ps
CPU time 0.8 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206668 kb
Host smart-b33e0fa0-75c1-4261-85a8-8c3214cd3982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39095
68074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.3909568074
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.1241761246
Short name T1595
Test name
Test status
Simulation time 178253650 ps
CPU time 0.83 seconds
Started Jul 21 06:57:18 PM PDT 24
Finished Jul 21 06:57:19 PM PDT 24
Peak memory 206692 kb
Host smart-e30328f5-b48f-4edc-aa7a-6e115e644efb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12417
61246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.1241761246
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.1722999249
Short name T2147
Test name
Test status
Simulation time 998969382 ps
CPU time 2.21 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:27 PM PDT 24
Peak memory 206808 kb
Host smart-b0abfba7-4975-46ac-a328-eba3e0a01085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17229
99249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.1722999249
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.1943937008
Short name T1357
Test name
Test status
Simulation time 6048060723 ps
CPU time 167.84 seconds
Started Jul 21 06:57:21 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206880 kb
Host smart-27dc79cd-5d59-4106-b137-0669d88886a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19439
37008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.1943937008
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.55113322
Short name T2610
Test name
Test status
Simulation time 100732309 ps
CPU time 0.76 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206708 kb
Host smart-e002624a-142a-485f-96bf-f32555cc1777
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=55113322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.55113322
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2661887781
Short name T1117
Test name
Test status
Simulation time 4252830769 ps
CPU time 5.17 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206804 kb
Host smart-5a53a3a8-6327-4ac6-b724-435aefbad9ba
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2661887781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2661887781
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.2509689308
Short name T923
Test name
Test status
Simulation time 13305993252 ps
CPU time 11.75 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206976 kb
Host smart-e5f5a42c-b437-4780-aceb-fc7a70439493
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2509689308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.2509689308
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.3896400789
Short name T631
Test name
Test status
Simulation time 23358941312 ps
CPU time 24.44 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:49 PM PDT 24
Peak memory 206752 kb
Host smart-14fb9bee-5f5f-443c-831c-1c03786fc147
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3896400789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.3896400789
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.3366623859
Short name T1510
Test name
Test status
Simulation time 164492589 ps
CPU time 0.83 seconds
Started Jul 21 06:57:19 PM PDT 24
Finished Jul 21 06:57:20 PM PDT 24
Peak memory 206692 kb
Host smart-b847ffcd-4fcc-4ae0-ace0-536a7406edbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33666
23859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.3366623859
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.3975577847
Short name T57
Test name
Test status
Simulation time 152073372 ps
CPU time 0.75 seconds
Started Jul 21 06:57:26 PM PDT 24
Finished Jul 21 06:57:28 PM PDT 24
Peak memory 206692 kb
Host smart-538fe05f-aa19-458c-ba69-63a8bc94f559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39755
77847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.3975577847
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3555373289
Short name T1817
Test name
Test status
Simulation time 322268090 ps
CPU time 1.18 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 06:57:27 PM PDT 24
Peak memory 206680 kb
Host smart-1774cff8-a19f-4e7d-9c43-402e2132ea01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35553
73289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3555373289
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.37587594
Short name T491
Test name
Test status
Simulation time 496179575 ps
CPU time 1.42 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206648 kb
Host smart-b039a675-23b2-4ed4-adc3-cc48c1230061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37587
594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.37587594
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.3177717838
Short name T2209
Test name
Test status
Simulation time 11064029542 ps
CPU time 23.05 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:44 PM PDT 24
Peak memory 206896 kb
Host smart-8b6e0dcc-0e02-43b0-ad56-2e8d103eb18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31777
17838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.3177717838
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.3751934987
Short name T364
Test name
Test status
Simulation time 438707116 ps
CPU time 1.58 seconds
Started Jul 21 06:57:21 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206696 kb
Host smart-6d32fd85-8a5b-4222-a4b6-4695bb49e954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37519
34987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.3751934987
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.2986900051
Short name T1404
Test name
Test status
Simulation time 176951353 ps
CPU time 0.82 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:21 PM PDT 24
Peak memory 206656 kb
Host smart-09a054a5-0236-4c8f-897e-569c08bfa120
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29869
00051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.2986900051
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1889229142
Short name T869
Test name
Test status
Simulation time 41330659 ps
CPU time 0.66 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206560 kb
Host smart-1b98c0a4-aa35-48e8-90b3-7b0306ef0abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18892
29142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1889229142
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3662743812
Short name T2489
Test name
Test status
Simulation time 928235490 ps
CPU time 2.15 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206756 kb
Host smart-290927f5-6935-48ca-b320-e038abc61538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36627
43812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3662743812
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.189945181
Short name T1800
Test name
Test status
Simulation time 174102336 ps
CPU time 1.73 seconds
Started Jul 21 06:57:20 PM PDT 24
Finished Jul 21 06:57:23 PM PDT 24
Peak memory 206740 kb
Host smart-03565bae-fa5e-454c-ad11-f37889422fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18994
5181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.189945181
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3748134443
Short name T309
Test name
Test status
Simulation time 298948705 ps
CPU time 0.94 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206648 kb
Host smart-2388b44b-ce60-4cd5-9d85-161f85ccd78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37481
34443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3748134443
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.2497411044
Short name T720
Test name
Test status
Simulation time 143694818 ps
CPU time 0.78 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206672 kb
Host smart-2ed93269-c4ea-4577-81c5-95297dcb0460
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24974
11044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.2497411044
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.3508213243
Short name T1393
Test name
Test status
Simulation time 236044880 ps
CPU time 0.94 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 06:57:27 PM PDT 24
Peak memory 206680 kb
Host smart-d7318b6c-ac9e-4991-a70e-45d19964d8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35082
13243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.3508213243
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.3657253807
Short name T2575
Test name
Test status
Simulation time 5896875315 ps
CPU time 39.24 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:58:08 PM PDT 24
Peak memory 206876 kb
Host smart-1d31e445-7a43-4bb1-8af3-523e80c1ede1
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3657253807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.3657253807
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3919078756
Short name T1693
Test name
Test status
Simulation time 205524426 ps
CPU time 0.86 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:57:28 PM PDT 24
Peak memory 206740 kb
Host smart-561986cc-e605-49b1-9145-48c149129ea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39190
78756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3919078756
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.734438241
Short name T1494
Test name
Test status
Simulation time 23395766663 ps
CPU time 27.89 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206792 kb
Host smart-d4aada3f-2a75-4542-9def-6294ed14f7cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73443
8241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.734438241
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.3141037329
Short name T1150
Test name
Test status
Simulation time 3307138010 ps
CPU time 4.33 seconds
Started Jul 21 06:57:21 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206764 kb
Host smart-5f9472e5-c3bc-47f8-bb7a-6f730e798bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31410
37329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.3141037329
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.4085155207
Short name T2478
Test name
Test status
Simulation time 11344965564 ps
CPU time 319.84 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 07:02:45 PM PDT 24
Peak memory 206920 kb
Host smart-d5c10e82-c725-4593-a508-e2c2ea6a60ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40851
55207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.4085155207
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.1032510140
Short name T653
Test name
Test status
Simulation time 6506097374 ps
CPU time 62.7 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 207000 kb
Host smart-50e36e3e-36ad-45c4-b785-0802058b7878
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1032510140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.1032510140
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.3689574052
Short name T640
Test name
Test status
Simulation time 240138183 ps
CPU time 0.91 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206664 kb
Host smart-45d9ecdd-d719-4ef7-8689-add7e02422fb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3689574052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.3689574052
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.3904202143
Short name T1940
Test name
Test status
Simulation time 186553986 ps
CPU time 0.85 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206700 kb
Host smart-8f2b6523-f87d-4457-9d6e-65312f7fbfa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39042
02143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.3904202143
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.1798358252
Short name T982
Test name
Test status
Simulation time 3279863523 ps
CPU time 23.75 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 06:57:49 PM PDT 24
Peak memory 206960 kb
Host smart-14903930-dd40-4ece-b271-1951709af28e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17983
58252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.1798358252
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.3222057445
Short name T1055
Test name
Test status
Simulation time 3121475361 ps
CPU time 84.46 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206868 kb
Host smart-e2288025-3329-4cdc-aa11-eccf50b81dab
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3222057445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.3222057445
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.2914006597
Short name T1059
Test name
Test status
Simulation time 158493154 ps
CPU time 0.81 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206632 kb
Host smart-859859b5-66f6-4fe6-bf2a-39868021a7bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2914006597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.2914006597
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3575321193
Short name T1874
Test name
Test status
Simulation time 183751751 ps
CPU time 0.81 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:57:29 PM PDT 24
Peak memory 206656 kb
Host smart-f02d4714-0d56-484d-a760-8a0049ad106f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35753
21193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3575321193
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.3148642630
Short name T1336
Test name
Test status
Simulation time 226626314 ps
CPU time 0.91 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206632 kb
Host smart-ace05474-1e00-4048-b999-0f163f430ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31486
42630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.3148642630
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.3966358938
Short name T1631
Test name
Test status
Simulation time 165461458 ps
CPU time 0.81 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206652 kb
Host smart-dbf43d82-72e0-4db9-8f57-d62452800db3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39663
58938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.3966358938
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.1412075727
Short name T763
Test name
Test status
Simulation time 162503686 ps
CPU time 0.84 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206668 kb
Host smart-86349a4e-b505-4c03-b931-e95a31e0865b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14120
75727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.1412075727
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.491541708
Short name T2235
Test name
Test status
Simulation time 181225027 ps
CPU time 0.85 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206668 kb
Host smart-ac150a3e-7d2b-45bc-bf04-09b18a797078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49154
1708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.491541708
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.1936800500
Short name T2204
Test name
Test status
Simulation time 166038043 ps
CPU time 0.75 seconds
Started Jul 21 06:57:25 PM PDT 24
Finished Jul 21 06:57:27 PM PDT 24
Peak memory 206668 kb
Host smart-06d2933f-b79a-4b2d-99f2-2d2a989a2384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19368
00500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.1936800500
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.1906958653
Short name T1524
Test name
Test status
Simulation time 245187746 ps
CPU time 1.03 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206664 kb
Host smart-2d3d5841-aedc-4417-ae98-2a59acd1f694
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1906958653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.1906958653
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.517009484
Short name T1892
Test name
Test status
Simulation time 187720773 ps
CPU time 0.76 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206632 kb
Host smart-b6261e8e-b4c9-4880-8744-3b83290b1eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51700
9484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.517009484
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.227676506
Short name T1373
Test name
Test status
Simulation time 32950986 ps
CPU time 0.68 seconds
Started Jul 21 06:57:23 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206652 kb
Host smart-4a1a1cf8-c884-49d4-a60d-95cf7ec3d47d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
6506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.227676506
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.403391044
Short name T244
Test name
Test status
Simulation time 20591741298 ps
CPU time 40.83 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206896 kb
Host smart-a6e708d8-b8b4-435b-b82e-4ffc17521c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40339
1044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.403391044
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.2484659201
Short name T2144
Test name
Test status
Simulation time 161976625 ps
CPU time 0.76 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206632 kb
Host smart-9e288009-8f81-42fe-b325-8cde42ece62f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24846
59201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.2484659201
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.4290306114
Short name T2717
Test name
Test status
Simulation time 206630288 ps
CPU time 0.94 seconds
Started Jul 21 06:57:22 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206672 kb
Host smart-b649fce8-c3a4-472c-8f8d-8dc104c2eb33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42903
06114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.4290306114
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2781336821
Short name T836
Test name
Test status
Simulation time 200928198 ps
CPU time 0.88 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206680 kb
Host smart-80eae556-898b-46d9-b6da-a7402808ee8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27813
36821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2781336821
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3291328357
Short name T1427
Test name
Test status
Simulation time 224110440 ps
CPU time 0.85 seconds
Started Jul 21 06:57:29 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206628 kb
Host smart-e7271d35-6bcd-4c83-9b8e-735db1d73555
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32913
28357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3291328357
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.602919330
Short name T2319
Test name
Test status
Simulation time 177701802 ps
CPU time 0.85 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206668 kb
Host smart-c818e937-4312-4a1c-93d1-8bb0ec71f06f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60291
9330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.602919330
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.1783590819
Short name T2013
Test name
Test status
Simulation time 170066419 ps
CPU time 0.88 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 06:57:26 PM PDT 24
Peak memory 206660 kb
Host smart-b2a9eabf-1633-47db-8268-aa0acd55e70b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17835
90819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.1783590819
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.2789153022
Short name T531
Test name
Test status
Simulation time 172299900 ps
CPU time 0.81 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:57:28 PM PDT 24
Peak memory 206668 kb
Host smart-8351d2d2-ad35-48af-b729-d48b8bf37a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27891
53022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.2789153022
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3969156268
Short name T2291
Test name
Test status
Simulation time 238056800 ps
CPU time 0.98 seconds
Started Jul 21 06:57:24 PM PDT 24
Finished Jul 21 06:57:27 PM PDT 24
Peak memory 206664 kb
Host smart-b2057444-1498-4051-883c-a3fbba8007b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39691
56268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3969156268
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.2582372368
Short name T1953
Test name
Test status
Simulation time 5378429307 ps
CPU time 39.97 seconds
Started Jul 21 06:57:34 PM PDT 24
Finished Jul 21 06:58:14 PM PDT 24
Peak memory 206924 kb
Host smart-5fac0033-b7e4-4046-a80a-bcfc225dc2c1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2582372368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.2582372368
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.3541596379
Short name T950
Test name
Test status
Simulation time 176863364 ps
CPU time 0.86 seconds
Started Jul 21 06:57:31 PM PDT 24
Finished Jul 21 06:57:32 PM PDT 24
Peak memory 206632 kb
Host smart-6f395f47-16f7-41e5-887e-87e5ecb211a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35415
96379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.3541596379
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.3000045735
Short name T1079
Test name
Test status
Simulation time 182369640 ps
CPU time 0.82 seconds
Started Jul 21 06:57:29 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206608 kb
Host smart-b5797c98-cc4a-451f-9166-7a961bab492f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30000
45735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.3000045735
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3247839074
Short name T2229
Test name
Test status
Simulation time 484191073 ps
CPU time 1.25 seconds
Started Jul 21 06:57:29 PM PDT 24
Finished Jul 21 06:57:32 PM PDT 24
Peak memory 206656 kb
Host smart-b1a16537-3b84-4be8-8d81-523cce033629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32478
39074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3247839074
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.3309770105
Short name T842
Test name
Test status
Simulation time 4313655575 ps
CPU time 31.84 seconds
Started Jul 21 06:57:30 PM PDT 24
Finished Jul 21 06:58:03 PM PDT 24
Peak memory 206904 kb
Host smart-38de8403-ae82-466e-9083-e55a53a99cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33097
70105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.3309770105
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3194093954
Short name T928
Test name
Test status
Simulation time 79200880 ps
CPU time 0.71 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206764 kb
Host smart-55c4507c-7bfd-4a6f-9a51-3f4230bf6f86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3194093954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3194093954
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.1557812288
Short name T1154
Test name
Test status
Simulation time 3467986659 ps
CPU time 4.82 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:34 PM PDT 24
Peak memory 206780 kb
Host smart-a7870a88-e8e8-4167-a33d-2c71c19dfab1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1557812288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.1557812288
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.358247027
Short name T935
Test name
Test status
Simulation time 13335010978 ps
CPU time 12.68 seconds
Started Jul 21 06:57:30 PM PDT 24
Finished Jul 21 06:57:43 PM PDT 24
Peak memory 206904 kb
Host smart-c80e7d29-3caf-4c9e-a6be-d8ac6171f18b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=358247027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.358247027
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.1336758071
Short name T1377
Test name
Test status
Simulation time 23387163526 ps
CPU time 23.1 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206736 kb
Host smart-33568a04-40eb-46b0-a4a2-c45bcd6cf4dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1336758071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.1336758071
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.1986077442
Short name T377
Test name
Test status
Simulation time 157375615 ps
CPU time 0.81 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:57:29 PM PDT 24
Peak memory 206676 kb
Host smart-dff2182e-85aa-4674-ba44-ffe43981b81a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19860
77442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.1986077442
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.3025059925
Short name T2750
Test name
Test status
Simulation time 145421498 ps
CPU time 0.82 seconds
Started Jul 21 06:57:29 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206612 kb
Host smart-ec3ce3c5-7f7a-4628-95db-d527cb713a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30250
59925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.3025059925
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.3946021361
Short name T2049
Test name
Test status
Simulation time 346623885 ps
CPU time 1.2 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206668 kb
Host smart-6d26cc2d-998c-40a8-8997-664728f00ee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39460
21361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.3946021361
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.3128056959
Short name T529
Test name
Test status
Simulation time 1156713215 ps
CPU time 2.81 seconds
Started Jul 21 06:57:33 PM PDT 24
Finished Jul 21 06:57:36 PM PDT 24
Peak memory 206812 kb
Host smart-7c8f3280-f492-46c9-ae6a-c00a509cb884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31280
56959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.3128056959
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.1530958810
Short name T2540
Test name
Test status
Simulation time 11821200663 ps
CPU time 23.07 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206904 kb
Host smart-3e839ff7-a115-4420-9f35-5204b2353e9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15309
58810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1530958810
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.597872701
Short name T2630
Test name
Test status
Simulation time 498977122 ps
CPU time 1.49 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:31 PM PDT 24
Peak memory 206680 kb
Host smart-197d15ba-f9a5-4c98-b8dc-f05d5910cb71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59787
2701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.597872701
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.992985237
Short name T2312
Test name
Test status
Simulation time 172869635 ps
CPU time 0.78 seconds
Started Jul 21 06:57:27 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206684 kb
Host smart-8aa9686b-6c9a-4f55-a04c-f201be0c43ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99298
5237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.992985237
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.92855515
Short name T459
Test name
Test status
Simulation time 75470114 ps
CPU time 0.67 seconds
Started Jul 21 06:57:28 PM PDT 24
Finished Jul 21 06:57:30 PM PDT 24
Peak memory 206620 kb
Host smart-9a20fdea-7196-4dd9-9d81-87bdbcd952c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92855
515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.92855515
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.474563865
Short name T1001
Test name
Test status
Simulation time 969926350 ps
CPU time 2.2 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:38 PM PDT 24
Peak memory 206728 kb
Host smart-38994d4e-b497-4f85-a75c-53ee32762232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47456
3865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.474563865
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2591753246
Short name T937
Test name
Test status
Simulation time 161117640 ps
CPU time 1.26 seconds
Started Jul 21 06:57:33 PM PDT 24
Finished Jul 21 06:57:35 PM PDT 24
Peak memory 206804 kb
Host smart-e2259212-5f3c-4ffa-bc6c-d38c111af268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25917
53246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2591753246
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.3509168309
Short name T1013
Test name
Test status
Simulation time 167960497 ps
CPU time 0.8 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206664 kb
Host smart-2202c9ef-d142-4145-97e4-a93f6e5dd511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35091
68309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.3509168309
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1920412957
Short name T2689
Test name
Test status
Simulation time 161345599 ps
CPU time 0.81 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:36 PM PDT 24
Peak memory 206656 kb
Host smart-d624d39e-bc23-45d2-97e4-ea06f10634ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19204
12957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1920412957
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.922527462
Short name T2117
Test name
Test status
Simulation time 243746933 ps
CPU time 0.98 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:37 PM PDT 24
Peak memory 206652 kb
Host smart-bf8b2aee-9ce7-4a3a-9f64-d472004431ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92252
7462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.922527462
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.4053764712
Short name T1071
Test name
Test status
Simulation time 5578437157 ps
CPU time 21.36 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:59 PM PDT 24
Peak memory 206884 kb
Host smart-756d4b9d-8d2f-406c-9dee-f78fb093e064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40537
64712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.4053764712
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.4196928598
Short name T2414
Test name
Test status
Simulation time 225350388 ps
CPU time 0.92 seconds
Started Jul 21 06:57:33 PM PDT 24
Finished Jul 21 06:57:34 PM PDT 24
Peak memory 206660 kb
Host smart-58b898b6-8ddc-4f02-802c-7187220cdd4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41969
28598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.4196928598
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.601610129
Short name T513
Test name
Test status
Simulation time 23309242687 ps
CPU time 22.47 seconds
Started Jul 21 06:57:36 PM PDT 24
Finished Jul 21 06:57:59 PM PDT 24
Peak memory 206776 kb
Host smart-ba13c6d0-2afd-4a2d-b639-da4ea7e30aba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60161
0129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.601610129
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.2095063786
Short name T1283
Test name
Test status
Simulation time 3317904400 ps
CPU time 4.25 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206748 kb
Host smart-1593ca86-eb20-4d5a-a0b7-7ca2a879aad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20950
63786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.2095063786
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.2938940755
Short name T2677
Test name
Test status
Simulation time 8064979756 ps
CPU time 79.65 seconds
Started Jul 21 06:57:32 PM PDT 24
Finished Jul 21 06:58:52 PM PDT 24
Peak memory 206920 kb
Host smart-d7ef018e-e334-4245-96ff-ad5111d98f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29389
40755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.2938940755
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.2417294813
Short name T1910
Test name
Test status
Simulation time 5293201503 ps
CPU time 51.71 seconds
Started Jul 21 06:57:36 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206920 kb
Host smart-be63c2a5-a578-4c4d-aa05-a5399ebba708
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2417294813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.2417294813
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.4294794298
Short name T1126
Test name
Test status
Simulation time 261242473 ps
CPU time 0.96 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206668 kb
Host smart-957a9fc6-073c-4085-bbb4-396e7c982e8c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4294794298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.4294794298
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.1059855213
Short name T2509
Test name
Test status
Simulation time 260528010 ps
CPU time 0.96 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206664 kb
Host smart-a7b5c45e-8023-4fd8-b35c-f36729820c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10598
55213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.1059855213
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.3018817426
Short name T1597
Test name
Test status
Simulation time 4871004669 ps
CPU time 135.55 seconds
Started Jul 21 06:57:33 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206864 kb
Host smart-432b265c-6086-4fc4-8291-c9d298c45cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30188
17426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.3018817426
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.162073059
Short name T1231
Test name
Test status
Simulation time 7581381489 ps
CPU time 71.86 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:58:50 PM PDT 24
Peak memory 206940 kb
Host smart-3a6186ed-ce5a-404a-9905-23ba52659117
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=162073059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.162073059
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2883595898
Short name T1187
Test name
Test status
Simulation time 172019985 ps
CPU time 0.78 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:36 PM PDT 24
Peak memory 206656 kb
Host smart-5d456b58-c261-4aeb-a367-e75de6bf92bb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2883595898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2883595898
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1767293354
Short name T776
Test name
Test status
Simulation time 176702337 ps
CPU time 0.81 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:37 PM PDT 24
Peak memory 206692 kb
Host smart-a5518320-65ce-4a92-9d02-7b1af70fee2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17672
93354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1767293354
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.2693965519
Short name T1193
Test name
Test status
Simulation time 218680443 ps
CPU time 0.88 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:37 PM PDT 24
Peak memory 206696 kb
Host smart-33bc9bb5-0eb5-4975-a363-7b7f9aaff968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
65519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.2693965519
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.3664277749
Short name T2617
Test name
Test status
Simulation time 185649743 ps
CPU time 0.92 seconds
Started Jul 21 06:57:35 PM PDT 24
Finished Jul 21 06:57:36 PM PDT 24
Peak memory 206668 kb
Host smart-21ffee74-b745-4b28-81df-f3ce84ddf5bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36642
77749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.3664277749
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.1946882616
Short name T501
Test name
Test status
Simulation time 186066755 ps
CPU time 0.86 seconds
Started Jul 21 06:57:36 PM PDT 24
Finished Jul 21 06:57:38 PM PDT 24
Peak memory 206680 kb
Host smart-680461d4-0aaf-4a61-ba82-2044793b7b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19468
82616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.1946882616
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2496096619
Short name T598
Test name
Test status
Simulation time 198152126 ps
CPU time 0.89 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206684 kb
Host smart-30d7a58a-82cb-4135-9105-83ef99c7759e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24960
96619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2496096619
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.451087873
Short name T2163
Test name
Test status
Simulation time 189277060 ps
CPU time 0.84 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206652 kb
Host smart-2708178a-2999-4b16-99de-1825a1e06bf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45108
7873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.451087873
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.2924710601
Short name T599
Test name
Test status
Simulation time 214859730 ps
CPU time 0.91 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:38 PM PDT 24
Peak memory 206652 kb
Host smart-5aef9a57-e46d-4c20-b87b-90efd073d06c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2924710601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.2924710601
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.2725614370
Short name T789
Test name
Test status
Simulation time 155870695 ps
CPU time 0.78 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206624 kb
Host smart-9875f482-be89-43bb-987a-56a3ffc20361
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27256
14370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.2725614370
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.1596967043
Short name T1312
Test name
Test status
Simulation time 116894124 ps
CPU time 0.73 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206676 kb
Host smart-70647494-8c45-4700-8710-1ac22aa60f99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15969
67043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.1596967043
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.2442281250
Short name T2127
Test name
Test status
Simulation time 17266058970 ps
CPU time 38.68 seconds
Started Jul 21 06:57:41 PM PDT 24
Finished Jul 21 06:58:20 PM PDT 24
Peak memory 215124 kb
Host smart-34273d94-1f6d-4d9c-855c-f42b685d48ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24422
81250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.2442281250
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.215529729
Short name T1781
Test name
Test status
Simulation time 182776073 ps
CPU time 0.84 seconds
Started Jul 21 06:57:39 PM PDT 24
Finished Jul 21 06:57:42 PM PDT 24
Peak memory 206660 kb
Host smart-b1048b2b-e1af-4f84-8ee9-9cf6f113de14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21552
9729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.215529729
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.364400516
Short name T782
Test name
Test status
Simulation time 203875203 ps
CPU time 0.85 seconds
Started Jul 21 06:57:41 PM PDT 24
Finished Jul 21 06:57:43 PM PDT 24
Peak memory 206664 kb
Host smart-279e85ef-8b66-4642-8158-2f8c6694be3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36440
0516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.364400516
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.2792068182
Short name T871
Test name
Test status
Simulation time 222502538 ps
CPU time 0.83 seconds
Started Jul 21 06:57:41 PM PDT 24
Finished Jul 21 06:57:42 PM PDT 24
Peak memory 206652 kb
Host smart-679c69d2-6357-46d1-b2d2-7d5206977fc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27920
68182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.2792068182
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.1787819322
Short name T1449
Test name
Test status
Simulation time 199621535 ps
CPU time 0.85 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206668 kb
Host smart-3f2228d3-79b0-468d-af18-c19f2ff9be25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17878
19322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.1787819322
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.3074632803
Short name T579
Test name
Test status
Simulation time 169365763 ps
CPU time 0.81 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206652 kb
Host smart-cb4539f2-9e4f-45b9-bc7d-851c54f0f028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
32803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.3074632803
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.3368123693
Short name T1419
Test name
Test status
Simulation time 212057843 ps
CPU time 0.83 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206688 kb
Host smart-3e445ad2-8386-473a-bd65-efe5f6101e38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33681
23693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.3368123693
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3855623761
Short name T1791
Test name
Test status
Simulation time 147883657 ps
CPU time 0.81 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206668 kb
Host smart-39c43768-d86c-47f5-af0d-cb11c8f03e88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38556
23761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3855623761
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.87694309
Short name T837
Test name
Test status
Simulation time 286938444 ps
CPU time 0.97 seconds
Started Jul 21 06:57:39 PM PDT 24
Finished Jul 21 06:57:42 PM PDT 24
Peak memory 206672 kb
Host smart-32d7650e-0070-4355-93eb-f4ebd00db71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87694
309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.87694309
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.3614499151
Short name T1175
Test name
Test status
Simulation time 6002690391 ps
CPU time 41.46 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:58:20 PM PDT 24
Peak memory 206904 kb
Host smart-eb9b5641-9330-422d-bc6b-72209f23679c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3614499151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.3614499151
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.905209157
Short name T696
Test name
Test status
Simulation time 192969360 ps
CPU time 0.83 seconds
Started Jul 21 06:57:40 PM PDT 24
Finished Jul 21 06:57:42 PM PDT 24
Peak memory 206704 kb
Host smart-ee830ea7-c493-4683-b51d-718edf322ffc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90520
9157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.905209157
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.649527002
Short name T1091
Test name
Test status
Simulation time 175133838 ps
CPU time 0.8 seconds
Started Jul 21 06:57:40 PM PDT 24
Finished Jul 21 06:57:42 PM PDT 24
Peak memory 206664 kb
Host smart-598470fd-03a9-4aed-8723-84dae3267c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64952
7002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.649527002
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.1856067426
Short name T475
Test name
Test status
Simulation time 353529467 ps
CPU time 1.16 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:41 PM PDT 24
Peak memory 206680 kb
Host smart-4b9d8f7d-fc21-4483-8b23-3a2e96b6b335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18560
67426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.1856067426
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2615032
Short name T988
Test name
Test status
Simulation time 5368348135 ps
CPU time 40.7 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:58:27 PM PDT 24
Peak memory 206916 kb
Host smart-435795df-0b79-4a45-a428-921e041d0830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26150
32 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2615032
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3044369248
Short name T1379
Test name
Test status
Simulation time 43152650 ps
CPU time 0.69 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206708 kb
Host smart-1cbdf5b1-3df4-480c-aa36-bc9a6ebb8241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3044369248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3044369248
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.293422981
Short name T1974
Test name
Test status
Simulation time 3669961570 ps
CPU time 4.36 seconds
Started Jul 21 06:57:40 PM PDT 24
Finished Jul 21 06:57:45 PM PDT 24
Peak memory 206876 kb
Host smart-eca2ac4e-ac48-4033-9fff-558b6da87d0b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=293422981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.293422981
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.547130646
Short name T704
Test name
Test status
Simulation time 13398971233 ps
CPU time 12.18 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:58:00 PM PDT 24
Peak memory 206788 kb
Host smart-4aefb42e-8980-462d-8a0c-0ab76f498a6d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=547130646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.547130646
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.3026933757
Short name T2201
Test name
Test status
Simulation time 23332296547 ps
CPU time 22.35 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:58:00 PM PDT 24
Peak memory 206864 kb
Host smart-2080f966-cb8e-416a-9947-7f94c36569d1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3026933757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.3026933757
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.985883348
Short name T2580
Test name
Test status
Simulation time 165808787 ps
CPU time 0.81 seconds
Started Jul 21 06:57:37 PM PDT 24
Finished Jul 21 06:57:39 PM PDT 24
Peak memory 206660 kb
Host smart-93118607-367e-43cf-8f28-ed54e4b5eab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98588
3348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.985883348
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.1867029634
Short name T2521
Test name
Test status
Simulation time 165277176 ps
CPU time 0.8 seconds
Started Jul 21 06:57:39 PM PDT 24
Finished Jul 21 06:57:41 PM PDT 24
Peak memory 206684 kb
Host smart-93115588-1471-4df2-bae6-e17b27298b54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18670
29634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.1867029634
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.3881894560
Short name T2606
Test name
Test status
Simulation time 220752154 ps
CPU time 0.97 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206680 kb
Host smart-baaa19d3-046a-4c37-b0f4-2ebdd994ded9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38818
94560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.3881894560
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.714151659
Short name T1018
Test name
Test status
Simulation time 1401015607 ps
CPU time 2.91 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:42 PM PDT 24
Peak memory 206808 kb
Host smart-9299a650-f528-4a3e-972c-990d3338bf72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71415
1659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.714151659
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.2517464101
Short name T1975
Test name
Test status
Simulation time 21949137249 ps
CPU time 42.86 seconds
Started Jul 21 06:57:46 PM PDT 24
Finished Jul 21 06:58:29 PM PDT 24
Peak memory 206948 kb
Host smart-8dd9929b-cdc1-454f-8aaa-bbed9f461d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25174
64101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.2517464101
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.4180185688
Short name T2305
Test name
Test status
Simulation time 443828914 ps
CPU time 1.34 seconds
Started Jul 21 06:57:40 PM PDT 24
Finished Jul 21 06:57:42 PM PDT 24
Peak memory 206652 kb
Host smart-01a962f4-8b19-48e8-bdea-e99c9db966f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41801
85688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.4180185688
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.4180444899
Short name T2054
Test name
Test status
Simulation time 148695162 ps
CPU time 0.74 seconds
Started Jul 21 06:57:39 PM PDT 24
Finished Jul 21 06:57:41 PM PDT 24
Peak memory 206704 kb
Host smart-46c424ba-a18d-474e-9ab2-f222687bc0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41804
44899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.4180444899
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.1426499900
Short name T2421
Test name
Test status
Simulation time 49057561 ps
CPU time 0.66 seconds
Started Jul 21 06:57:44 PM PDT 24
Finished Jul 21 06:57:45 PM PDT 24
Peak memory 206676 kb
Host smart-c12bfcdf-0745-41ad-b710-1c1f35175ed2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14264
99900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.1426499900
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.2190255571
Short name T544
Test name
Test status
Simulation time 990032379 ps
CPU time 2.44 seconds
Started Jul 21 06:57:42 PM PDT 24
Finished Jul 21 06:57:45 PM PDT 24
Peak memory 206764 kb
Host smart-fdbe9b7b-b045-4f17-9087-7d94c798864c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902
55571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.2190255571
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1776316020
Short name T177
Test name
Test status
Simulation time 200893696 ps
CPU time 2.16 seconds
Started Jul 21 06:57:43 PM PDT 24
Finished Jul 21 06:57:45 PM PDT 24
Peak memory 206812 kb
Host smart-b4f5feab-19f7-41a9-b274-b9dd76992bd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17763
16020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1776316020
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.3151897244
Short name T420
Test name
Test status
Simulation time 162477262 ps
CPU time 0.81 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206700 kb
Host smart-77033776-d29f-42e4-857f-e823b931c4c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31518
97244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.3151897244
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.627411407
Short name T1586
Test name
Test status
Simulation time 139296749 ps
CPU time 0.73 seconds
Started Jul 21 06:57:38 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206664 kb
Host smart-c2769485-3437-4ea2-b638-dde14368a24c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62741
1407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.627411407
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.3098303009
Short name T419
Test name
Test status
Simulation time 241947288 ps
CPU time 0.89 seconds
Started Jul 21 06:57:46 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206696 kb
Host smart-f86cf92f-eba7-4084-9b2b-0f490de7f638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30983
03009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.3098303009
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.3018871810
Short name T1554
Test name
Test status
Simulation time 4992175300 ps
CPU time 130.95 seconds
Started Jul 21 06:57:39 PM PDT 24
Finished Jul 21 06:59:52 PM PDT 24
Peak memory 206904 kb
Host smart-01c2c507-3781-4428-87a7-4c3755ca77c6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3018871810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.3018871810
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.2667230260
Short name T1743
Test name
Test status
Simulation time 222458408 ps
CPU time 0.94 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206660 kb
Host smart-f666b296-d6a1-436b-b143-00768a9dbad0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26672
30260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.2667230260
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.4149842375
Short name T2062
Test name
Test status
Simulation time 23343977774 ps
CPU time 24.96 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:58:11 PM PDT 24
Peak memory 206828 kb
Host smart-59d5e978-0709-42ef-923f-e16d9b39018e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41498
42375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.4149842375
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.281360142
Short name T944
Test name
Test status
Simulation time 3321486947 ps
CPU time 3.7 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206748 kb
Host smart-2213a6f3-be8d-46f0-9ea0-e721350aa3c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28136
0142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.281360142
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.3732551650
Short name T563
Test name
Test status
Simulation time 10181780087 ps
CPU time 95.22 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 206960 kb
Host smart-e064a3aa-ed6c-4643-b422-ce2f3dc8bff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37325
51650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.3732551650
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3141082394
Short name T2311
Test name
Test status
Simulation time 4912287003 ps
CPU time 132.81 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206888 kb
Host smart-8459044b-da03-4813-b4d6-ee37e0c6a926
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3141082394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3141082394
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.282660768
Short name T1326
Test name
Test status
Simulation time 241415321 ps
CPU time 0.9 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206668 kb
Host smart-7fdc26cc-5ac2-439d-bbed-5a1241fbb62e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=282660768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.282660768
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.2735914737
Short name T1233
Test name
Test status
Simulation time 185610836 ps
CPU time 0.84 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206676 kb
Host smart-bd5d86ba-6dd4-4bbe-8023-4e8c1078ef38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27359
14737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.2735914737
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.3331842057
Short name T1972
Test name
Test status
Simulation time 3875946838 ps
CPU time 107.19 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:59:39 PM PDT 24
Peak memory 206856 kb
Host smart-37e3ca0c-1716-48ad-ade1-ad7b0865ac52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33318
42057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.3331842057
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.2307801078
Short name T997
Test name
Test status
Simulation time 4421195170 ps
CPU time 43.97 seconds
Started Jul 21 06:57:46 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206892 kb
Host smart-ee002f70-6ea7-4bd4-ab0f-400905d2b2c2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2307801078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.2307801078
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.702134270
Short name T1190
Test name
Test status
Simulation time 166701282 ps
CPU time 0.79 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206680 kb
Host smart-56025862-4dda-4970-910e-e6c346a7bab5
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=702134270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.702134270
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.4041980260
Short name T727
Test name
Test status
Simulation time 144348411 ps
CPU time 0.76 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206652 kb
Host smart-0847dd0f-2519-408d-a99e-bf61cdc9a3a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40419
80260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.4041980260
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1754909671
Short name T109
Test name
Test status
Simulation time 180474709 ps
CPU time 0.81 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:57:49 PM PDT 24
Peak memory 206788 kb
Host smart-572692e1-4424-4465-ad4b-31e7a6d72d28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17549
09671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1754909671
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.737855693
Short name T465
Test name
Test status
Simulation time 160658679 ps
CPU time 0.8 seconds
Started Jul 21 06:57:46 PM PDT 24
Finished Jul 21 06:57:48 PM PDT 24
Peak memory 206664 kb
Host smart-341a535f-3dd1-4d36-b958-a82c162e1a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73785
5693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.737855693
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.2563892522
Short name T831
Test name
Test status
Simulation time 144756395 ps
CPU time 0.76 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:52 PM PDT 24
Peak memory 206628 kb
Host smart-098d9737-17d9-4b39-8b10-dea2b515c35d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25638
92522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.2563892522
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.2302976442
Short name T1042
Test name
Test status
Simulation time 156973952 ps
CPU time 0.75 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206648 kb
Host smart-5a7572fc-fcc8-4b99-8d9a-487856dbbf29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23029
76442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.2302976442
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.979373206
Short name T163
Test name
Test status
Simulation time 214157794 ps
CPU time 0.86 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206684 kb
Host smart-70127bea-68b8-4f97-8733-cf5d92c6b0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97937
3206 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.979373206
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.3757812936
Short name T2504
Test name
Test status
Simulation time 187247717 ps
CPU time 0.87 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206664 kb
Host smart-22d64516-006e-47c5-bbf6-a2e16d2fac5e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3757812936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.3757812936
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.2155746373
Short name T812
Test name
Test status
Simulation time 182856427 ps
CPU time 0.79 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:57:48 PM PDT 24
Peak memory 206644 kb
Host smart-1f1cd0ac-6aab-40b5-98b4-ff990f7df892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21557
46373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.2155746373
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2926389481
Short name T1931
Test name
Test status
Simulation time 49851421 ps
CPU time 0.68 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:52 PM PDT 24
Peak memory 206632 kb
Host smart-fd161dd2-a04e-4360-84c5-66adbfe00742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29263
89481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2926389481
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.936013805
Short name T1620
Test name
Test status
Simulation time 19439889949 ps
CPU time 41.4 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206944 kb
Host smart-5bb44cc5-9bcd-4265-82ae-0f3836ec4bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93601
3805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.936013805
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.189493088
Short name T1695
Test name
Test status
Simulation time 190255507 ps
CPU time 0.91 seconds
Started Jul 21 06:57:46 PM PDT 24
Finished Jul 21 06:57:48 PM PDT 24
Peak memory 206664 kb
Host smart-56c2918c-656f-4876-baab-5d7e61529ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18949
3088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.189493088
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1059058336
Short name T1886
Test name
Test status
Simulation time 197304573 ps
CPU time 0.86 seconds
Started Jul 21 06:57:54 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206664 kb
Host smart-d5c4fcba-e51a-45f6-b4e0-d0459079dde4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10590
58336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1059058336
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.190990716
Short name T1696
Test name
Test status
Simulation time 179290319 ps
CPU time 0.89 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206664 kb
Host smart-3892cd05-0415-4dc4-9fd0-3fb3ed913158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19099
0716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.190990716
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.647408392
Short name T925
Test name
Test status
Simulation time 166888253 ps
CPU time 0.81 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:57:46 PM PDT 24
Peak memory 206680 kb
Host smart-07c41b74-cffb-4778-ae2c-1655c48022f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64740
8392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.647408392
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.4058634898
Short name T1413
Test name
Test status
Simulation time 178663153 ps
CPU time 0.81 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206696 kb
Host smart-2aee0c3b-b385-4b4e-abdd-9e71c6f08844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40586
34898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.4058634898
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3275327397
Short name T2152
Test name
Test status
Simulation time 160021066 ps
CPU time 0.78 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:57:46 PM PDT 24
Peak memory 206668 kb
Host smart-2592bce5-cfab-44aa-8b20-3bb1c9e7f95b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32753
27397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3275327397
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.4276035598
Short name T347
Test name
Test status
Simulation time 202786185 ps
CPU time 0.84 seconds
Started Jul 21 06:57:46 PM PDT 24
Finished Jul 21 06:57:48 PM PDT 24
Peak memory 206668 kb
Host smart-66b207d7-473e-429e-868e-fc5335d10337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42760
35598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.4276035598
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.640417980
Short name T958
Test name
Test status
Simulation time 241120844 ps
CPU time 0.96 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206644 kb
Host smart-ec051a5f-4103-4eda-9c3a-bc34d9666230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64041
7980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.640417980
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.2147497827
Short name T1179
Test name
Test status
Simulation time 6797954947 ps
CPU time 195.7 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 206844 kb
Host smart-4f55d254-f114-4351-bddb-c5165b390b3a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2147497827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.2147497827
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.1806130861
Short name T2343
Test name
Test status
Simulation time 197217141 ps
CPU time 0.85 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206684 kb
Host smart-1975fdf4-956b-411e-b11c-a4cab43665af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18061
30861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.1806130861
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.228003851
Short name T1470
Test name
Test status
Simulation time 196875782 ps
CPU time 0.87 seconds
Started Jul 21 06:57:45 PM PDT 24
Finished Jul 21 06:57:47 PM PDT 24
Peak memory 206652 kb
Host smart-82b9bc63-5c39-4c7a-84a2-0abefe0435e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22800
3851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.228003851
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.192619494
Short name T2546
Test name
Test status
Simulation time 1375925803 ps
CPU time 2.93 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206756 kb
Host smart-6692c323-065d-490d-8b19-16293c9fb9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19261
9494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.192619494
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.3706246056
Short name T1913
Test name
Test status
Simulation time 7224973591 ps
CPU time 68.15 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:58:57 PM PDT 24
Peak memory 206936 kb
Host smart-b044f9f9-8d8a-4490-8639-0d6101881da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37062
46056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.3706246056
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.1834797457
Short name T2718
Test name
Test status
Simulation time 31082043 ps
CPU time 0.67 seconds
Started Jul 21 06:57:56 PM PDT 24
Finished Jul 21 06:57:57 PM PDT 24
Peak memory 206740 kb
Host smart-fe9bfa55-b171-4441-87ce-ee339c0567e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1834797457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.1834797457
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.1550660522
Short name T1195
Test name
Test status
Simulation time 3965410753 ps
CPU time 4.65 seconds
Started Jul 21 06:57:52 PM PDT 24
Finished Jul 21 06:57:58 PM PDT 24
Peak memory 206876 kb
Host smart-8a8016fd-4470-41ef-9df6-b3325a997258
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1550660522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.1550660522
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.1689445160
Short name T989
Test name
Test status
Simulation time 13332210832 ps
CPU time 12.32 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:58:04 PM PDT 24
Peak memory 206904 kb
Host smart-aef2bb75-abd2-4b16-b50b-84439f0966f1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1689445160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.1689445160
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3445711004
Short name T1992
Test name
Test status
Simulation time 23296617340 ps
CPU time 29.9 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:58:22 PM PDT 24
Peak memory 206808 kb
Host smart-aeae2752-5a70-41ff-9239-f92726bb56dd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3445711004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3445711004
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.883283661
Short name T535
Test name
Test status
Simulation time 188361854 ps
CPU time 0.85 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:57:54 PM PDT 24
Peak memory 206668 kb
Host smart-93fe3087-7e48-4bd9-8fb7-9e003d088a9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88328
3661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.883283661
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.4210587156
Short name T1480
Test name
Test status
Simulation time 146442092 ps
CPU time 0.78 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:57:49 PM PDT 24
Peak memory 206704 kb
Host smart-ea227e58-beb7-4719-81ea-e94fc135c877
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42105
87156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.4210587156
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.3724379259
Short name T668
Test name
Test status
Simulation time 374495485 ps
CPU time 1.23 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206652 kb
Host smart-530ada65-29cb-4939-814c-21c150af00f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37243
79259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.3724379259
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.2263170153
Short name T94
Test name
Test status
Simulation time 674254494 ps
CPU time 1.68 seconds
Started Jul 21 06:57:47 PM PDT 24
Finished Jul 21 06:57:50 PM PDT 24
Peak memory 206752 kb
Host smart-9802378e-5d94-4718-8f9a-fd9dc05849f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22631
70153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.2263170153
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.1898886475
Short name T2666
Test name
Test status
Simulation time 8123647804 ps
CPU time 17.27 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:58:10 PM PDT 24
Peak memory 206884 kb
Host smart-762d838a-a8cb-4fc8-9350-d30e881abb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18988
86475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.1898886475
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.1623230922
Short name T2361
Test name
Test status
Simulation time 458198735 ps
CPU time 1.38 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206644 kb
Host smart-8032d50f-8af9-457a-b386-271cb2ee1def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
30922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.1623230922
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.309532285
Short name T1016
Test name
Test status
Simulation time 182256212 ps
CPU time 0.78 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206672 kb
Host smart-269d68c5-8e4c-45ef-ae22-9210683bd1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30953
2285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.309532285
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.2832515060
Short name T1077
Test name
Test status
Simulation time 33622314 ps
CPU time 0.67 seconds
Started Jul 21 06:57:55 PM PDT 24
Finished Jul 21 06:57:57 PM PDT 24
Peak memory 206676 kb
Host smart-4a0f5f71-051a-4a0c-b532-f1ede13c331d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28325
15060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.2832515060
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.4238700112
Short name T2419
Test name
Test status
Simulation time 973470833 ps
CPU time 2.23 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:54 PM PDT 24
Peak memory 206756 kb
Host smart-1812b9a1-3c7f-4334-827b-a4f4f0f4d318
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42387
00112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.4238700112
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.450991064
Short name T2659
Test name
Test status
Simulation time 174400531 ps
CPU time 1.6 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206768 kb
Host smart-a9f55a76-1cd6-455f-aa88-2d9f252a08b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45099
1064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.450991064
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.3524820760
Short name T1564
Test name
Test status
Simulation time 180905842 ps
CPU time 0.92 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206660 kb
Host smart-f59b7d06-d90f-4cf3-96cc-c9415f67e0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35248
20760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.3524820760
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2734575879
Short name T1907
Test name
Test status
Simulation time 172941777 ps
CPU time 0.78 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206688 kb
Host smart-76437ffe-d43e-429f-b74a-f9c856be779d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27345
75879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2734575879
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.3038663119
Short name T2749
Test name
Test status
Simulation time 235119999 ps
CPU time 0.89 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206664 kb
Host smart-6c630d21-4aea-4fcb-914b-e92e291f7600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30386
63119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.3038663119
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.425573921
Short name T1929
Test name
Test status
Simulation time 5867494341 ps
CPU time 48.22 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:58:41 PM PDT 24
Peak memory 206904 kb
Host smart-f125558a-000b-4f47-a4cc-d70dbc437192
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42557
3921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.425573921
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.525942972
Short name T2629
Test name
Test status
Simulation time 173437918 ps
CPU time 0.83 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206644 kb
Host smart-52ab5010-e699-4f09-ac75-e4a0c291738d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52594
2972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.525942972
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.1343885269
Short name T908
Test name
Test status
Simulation time 23351680267 ps
CPU time 24.36 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:58:14 PM PDT 24
Peak memory 206752 kb
Host smart-d3b57acb-f594-44ae-af48-2427f720fb67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13438
85269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.1343885269
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.720593591
Short name T976
Test name
Test status
Simulation time 3317247767 ps
CPU time 3.9 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206760 kb
Host smart-0af8096d-032e-48e7-b9aa-66d35a38f914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72059
3591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.720593591
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.1060854979
Short name T1560
Test name
Test status
Simulation time 11446519918 ps
CPU time 108.39 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206996 kb
Host smart-ce6401a8-b60e-4713-9e4d-629710967219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10608
54979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.1060854979
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.523226284
Short name T2281
Test name
Test status
Simulation time 4254954739 ps
CPU time 116.28 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206864 kb
Host smart-1f0bbeb5-25f8-432e-b021-0667fa80bbc6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=523226284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.523226284
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.2089093297
Short name T1004
Test name
Test status
Simulation time 255778604 ps
CPU time 0.97 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206656 kb
Host smart-9c53d911-8929-4e7d-9446-515c0b3c86c5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2089093297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.2089093297
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.1778885741
Short name T689
Test name
Test status
Simulation time 196517404 ps
CPU time 0.85 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206688 kb
Host smart-0148903b-9b2b-419b-910f-908de995eb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17788
85741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.1778885741
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.3083314799
Short name T2231
Test name
Test status
Simulation time 5385546692 ps
CPU time 146.06 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 07:00:27 PM PDT 24
Peak memory 206892 kb
Host smart-aacc0180-582d-49d5-a9b6-43a2f53a90ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30833
14799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.3083314799
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3918618750
Short name T665
Test name
Test status
Simulation time 4108230867 ps
CPU time 39.12 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206848 kb
Host smart-c7e0834e-4ab3-429c-820c-4398b0884852
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3918618750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3918618750
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1774849243
Short name T1240
Test name
Test status
Simulation time 157037357 ps
CPU time 0.81 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:57 PM PDT 24
Peak memory 206672 kb
Host smart-c76ef880-fdbd-49aa-89eb-364effdaefe8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1774849243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1774849243
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.914021055
Short name T1014
Test name
Test status
Simulation time 141392058 ps
CPU time 0.77 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206684 kb
Host smart-06f37865-9087-4557-9d5a-7e9f1386bd3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91402
1055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.914021055
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.2134960130
Short name T118
Test name
Test status
Simulation time 181660464 ps
CPU time 0.8 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206672 kb
Host smart-cd89f178-a4e3-4a82-a6cb-1c9979cb6a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21349
60130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.2134960130
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.1502762358
Short name T1846
Test name
Test status
Simulation time 152642616 ps
CPU time 0.82 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206656 kb
Host smart-e6c7730a-52c7-4b0e-854b-205b41e80691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15027
62358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.1502762358
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.3091588849
Short name T777
Test name
Test status
Simulation time 208970688 ps
CPU time 0.84 seconds
Started Jul 21 06:57:50 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206660 kb
Host smart-82cb6ddd-2309-40c8-87aa-b5afd8732c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30915
88849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.3091588849
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.984738793
Short name T1543
Test name
Test status
Simulation time 168028745 ps
CPU time 0.77 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:57:52 PM PDT 24
Peak memory 206652 kb
Host smart-96e7d720-62ca-4bd7-8062-56fbc92b7a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98473
8793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.984738793
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2876057943
Short name T1861
Test name
Test status
Simulation time 153589118 ps
CPU time 0.8 seconds
Started Jul 21 06:57:57 PM PDT 24
Finished Jul 21 06:57:58 PM PDT 24
Peak memory 206660 kb
Host smart-1645dd5a-dc7e-4ba4-bd6b-b1f15dca835f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28760
57943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2876057943
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.1997180825
Short name T1261
Test name
Test status
Simulation time 221452036 ps
CPU time 1.03 seconds
Started Jul 21 06:58:05 PM PDT 24
Finished Jul 21 06:58:06 PM PDT 24
Peak memory 206680 kb
Host smart-ad71165e-e8fb-4e72-b03d-f16d643eb1b2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1997180825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.1997180825
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.872381508
Short name T2206
Test name
Test status
Simulation time 144548753 ps
CPU time 0.81 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206632 kb
Host smart-c19e80d3-71e2-40af-9a63-2b211f17af26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87238
1508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.872381508
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.3840662819
Short name T877
Test name
Test status
Simulation time 32583948 ps
CPU time 0.65 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206636 kb
Host smart-b7e92191-d066-4800-9dd6-98cbb380a5a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38406
62819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.3840662819
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.791106831
Short name T1140
Test name
Test status
Simulation time 9968949393 ps
CPU time 20.62 seconds
Started Jul 21 06:57:49 PM PDT 24
Finished Jul 21 06:58:11 PM PDT 24
Peak memory 215156 kb
Host smart-962a0e76-12c7-4d72-b6c1-f668b392149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79110
6831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.791106831
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.1914357834
Short name T1939
Test name
Test status
Simulation time 172664521 ps
CPU time 0.88 seconds
Started Jul 21 06:57:58 PM PDT 24
Finished Jul 21 06:58:00 PM PDT 24
Peak memory 206632 kb
Host smart-6672db37-4f92-43ae-aff6-309e4598b61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19143
57834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.1914357834
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.219016552
Short name T1159
Test name
Test status
Simulation time 181137549 ps
CPU time 0.87 seconds
Started Jul 21 06:57:51 PM PDT 24
Finished Jul 21 06:57:53 PM PDT 24
Peak memory 206688 kb
Host smart-86dcd79f-b9d9-4db4-bc0e-bc64912c1207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21901
6552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.219016552
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.2582535253
Short name T2176
Test name
Test status
Simulation time 252708402 ps
CPU time 0.92 seconds
Started Jul 21 06:57:48 PM PDT 24
Finished Jul 21 06:57:51 PM PDT 24
Peak memory 206688 kb
Host smart-fe295a0f-5021-4493-84b2-6f4e5a743604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25825
35253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.2582535253
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.1331381862
Short name T1519
Test name
Test status
Simulation time 180306738 ps
CPU time 0.85 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206640 kb
Host smart-5d1800b4-ba68-4fe5-8bc0-193aa58bee5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13313
81862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.1331381862
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.2834873015
Short name T1153
Test name
Test status
Simulation time 173018350 ps
CPU time 0.82 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 06:58:02 PM PDT 24
Peak memory 206676 kb
Host smart-dfbd5542-1659-46d6-a762-4a15eb11efb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28348
73015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.2834873015
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.2801738132
Short name T1185
Test name
Test status
Simulation time 145217868 ps
CPU time 0.75 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206676 kb
Host smart-e13000c9-bb1b-4571-a885-3c066b974c37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28017
38132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.2801738132
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3897735097
Short name T1673
Test name
Test status
Simulation time 152965981 ps
CPU time 0.79 seconds
Started Jul 21 06:57:56 PM PDT 24
Finished Jul 21 06:57:57 PM PDT 24
Peak memory 206664 kb
Host smart-e251f332-13b9-4104-89ff-2ce0edf062eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38977
35097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3897735097
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.1641824411
Short name T209
Test name
Test status
Simulation time 229141130 ps
CPU time 0.96 seconds
Started Jul 21 06:57:54 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206672 kb
Host smart-bc88566a-0c7a-429c-867c-35359dc7915d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16418
24411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.1641824411
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.4257947149
Short name T1629
Test name
Test status
Simulation time 3155743326 ps
CPU time 31.01 seconds
Started Jul 21 06:57:56 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206836 kb
Host smart-574f977e-84da-4d22-9545-e5a7d39c359f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4257947149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.4257947149
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.132465216
Short name T1214
Test name
Test status
Simulation time 175086030 ps
CPU time 0.81 seconds
Started Jul 21 06:57:54 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206664 kb
Host smart-a8c3bdce-dc3a-4d7b-a282-1fadb8da458a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13246
5216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.132465216
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.4137012404
Short name T1950
Test name
Test status
Simulation time 165599028 ps
CPU time 0.82 seconds
Started Jul 21 06:57:54 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206680 kb
Host smart-0ed61a39-c76c-4fde-8eb5-3921dc34c58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41370
12404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.4137012404
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.3552261408
Short name T1346
Test name
Test status
Simulation time 323418987 ps
CPU time 1.09 seconds
Started Jul 21 06:57:56 PM PDT 24
Finished Jul 21 06:57:57 PM PDT 24
Peak memory 206648 kb
Host smart-828a9855-8d11-4479-a0a3-b9c3a27bcd8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35522
61408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.3552261408
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.1221010452
Short name T755
Test name
Test status
Simulation time 4758755874 ps
CPU time 134.81 seconds
Started Jul 21 06:57:52 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206928 kb
Host smart-23e99bfe-2457-4f45-8404-37f4a422e05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12210
10452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.1221010452
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.1998988972
Short name T2269
Test name
Test status
Simulation time 46647277 ps
CPU time 0.67 seconds
Started Jul 21 06:53:20 PM PDT 24
Finished Jul 21 06:53:21 PM PDT 24
Peak memory 206720 kb
Host smart-e800dbc4-506d-4db5-aced-0d9757d0c4e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1998988972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.1998988972
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.4129685678
Short name T2185
Test name
Test status
Simulation time 4305454069 ps
CPU time 5.03 seconds
Started Jul 21 06:53:10 PM PDT 24
Finished Jul 21 06:53:15 PM PDT 24
Peak memory 206780 kb
Host smart-7bff81c7-d3fd-475e-9ab7-19b33376105f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4129685678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.4129685678
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.3484266804
Short name T1039
Test name
Test status
Simulation time 13327216355 ps
CPU time 15.58 seconds
Started Jul 21 06:53:11 PM PDT 24
Finished Jul 21 06:53:27 PM PDT 24
Peak memory 206808 kb
Host smart-390f854b-0dba-4c97-9876-d1208d08b25c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3484266804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.3484266804
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3804117785
Short name T2292
Test name
Test status
Simulation time 23395479397 ps
CPU time 25.4 seconds
Started Jul 21 06:53:07 PM PDT 24
Finished Jul 21 06:53:33 PM PDT 24
Peak memory 206952 kb
Host smart-9fa35f56-529e-4ea8-8154-80c3bffa949a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3804117785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3804117785
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.2945643786
Short name T1772
Test name
Test status
Simulation time 145864068 ps
CPU time 0.8 seconds
Started Jul 21 06:53:09 PM PDT 24
Finished Jul 21 06:53:10 PM PDT 24
Peak memory 206656 kb
Host smart-b8a0e70b-89ec-4daa-9b84-e9b206198573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29456
43786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.2945643786
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.2803896900
Short name T50
Test name
Test status
Simulation time 177285638 ps
CPU time 0.86 seconds
Started Jul 21 06:53:09 PM PDT 24
Finished Jul 21 06:53:11 PM PDT 24
Peak memory 206684 kb
Host smart-e9a9d694-349c-47f9-a197-3b3f013c03fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28038
96900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.2803896900
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.484200481
Short name T688
Test name
Test status
Simulation time 198225841 ps
CPU time 0.8 seconds
Started Jul 21 06:53:09 PM PDT 24
Finished Jul 21 06:53:10 PM PDT 24
Peak memory 206660 kb
Host smart-2405b2c8-9a02-41fa-9fcd-eb8db6124e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48420
0481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.484200481
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.3139339047
Short name T2066
Test name
Test status
Simulation time 236657499 ps
CPU time 0.93 seconds
Started Jul 21 06:53:11 PM PDT 24
Finished Jul 21 06:53:12 PM PDT 24
Peak memory 206676 kb
Host smart-d97b4f13-bf11-4af0-936f-5e625f8b2066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31393
39047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.3139339047
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.601871331
Short name T802
Test name
Test status
Simulation time 1088356456 ps
CPU time 2.48 seconds
Started Jul 21 06:53:09 PM PDT 24
Finished Jul 21 06:53:12 PM PDT 24
Peak memory 206708 kb
Host smart-ee973c90-9bcf-4860-aed3-d9137c18af57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60187
1331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.601871331
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2715427073
Short name T164
Test name
Test status
Simulation time 19506104513 ps
CPU time 34.3 seconds
Started Jul 21 06:53:14 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206964 kb
Host smart-a2b36270-3871-4d49-87bc-b427063a8ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27154
27073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2715427073
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.2497599668
Short name T516
Test name
Test status
Simulation time 398517934 ps
CPU time 1.26 seconds
Started Jul 21 06:53:10 PM PDT 24
Finished Jul 21 06:53:12 PM PDT 24
Peak memory 206688 kb
Host smart-3c352aba-be3b-4509-b306-cdd5c166bbd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24975
99668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.2497599668
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.1168330836
Short name T2121
Test name
Test status
Simulation time 155339686 ps
CPU time 0.79 seconds
Started Jul 21 06:53:07 PM PDT 24
Finished Jul 21 06:53:08 PM PDT 24
Peak memory 206696 kb
Host smart-451d804e-7366-4a35-b561-7455322e72c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11683
30836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.1168330836
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.1108256885
Short name T2221
Test name
Test status
Simulation time 60471109 ps
CPU time 0.7 seconds
Started Jul 21 06:53:11 PM PDT 24
Finished Jul 21 06:53:12 PM PDT 24
Peak memory 206672 kb
Host smart-63c9cb83-dd9a-4a3f-84e7-b72bbd741ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11082
56885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.1108256885
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.219144958
Short name T2376
Test name
Test status
Simulation time 859179247 ps
CPU time 2.02 seconds
Started Jul 21 06:53:10 PM PDT 24
Finished Jul 21 06:53:12 PM PDT 24
Peak memory 206800 kb
Host smart-e28ceffa-a6c4-496e-afda-8d8fcf0d8692
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21914
4958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.219144958
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.3862624512
Short name T2671
Test name
Test status
Simulation time 196981192 ps
CPU time 1.26 seconds
Started Jul 21 06:53:07 PM PDT 24
Finished Jul 21 06:53:09 PM PDT 24
Peak memory 206780 kb
Host smart-544598b4-aa88-48e2-9f56-a0e03baa3516
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38626
24512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.3862624512
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.614154765
Short name T2244
Test name
Test status
Simulation time 114181733940 ps
CPU time 156.89 seconds
Started Jul 21 06:53:14 PM PDT 24
Finished Jul 21 06:55:52 PM PDT 24
Peak memory 206924 kb
Host smart-137b1197-e38f-4f45-85aa-9e4ad0bddd54
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=614154765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.614154765
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.838495352
Short name T2628
Test name
Test status
Simulation time 83339732764 ps
CPU time 121.05 seconds
Started Jul 21 06:53:17 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206924 kb
Host smart-4f77ff42-727a-4025-a4cb-d8b004b571ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838495352 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.838495352
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.182303127
Short name T1255
Test name
Test status
Simulation time 100101223381 ps
CPU time 137.6 seconds
Started Jul 21 06:53:15 PM PDT 24
Finished Jul 21 06:55:33 PM PDT 24
Peak memory 206412 kb
Host smart-59325e26-ac0d-422d-9a04-c1737be11bf1
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=182303127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.182303127
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.1159048093
Short name T1635
Test name
Test status
Simulation time 109890359347 ps
CPU time 143.97 seconds
Started Jul 21 06:53:12 PM PDT 24
Finished Jul 21 06:55:37 PM PDT 24
Peak memory 206932 kb
Host smart-cb8e95fc-7474-4dea-945f-9eb11421a215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159048093 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.1159048093
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.2665106182
Short name T1400
Test name
Test status
Simulation time 95116983638 ps
CPU time 119.33 seconds
Started Jul 21 06:53:14 PM PDT 24
Finished Jul 21 06:55:13 PM PDT 24
Peak memory 206872 kb
Host smart-0c48e9d7-a3c5-4717-91b9-c37c63b3ad4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26651
06182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.2665106182
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.3255858912
Short name T2056
Test name
Test status
Simulation time 195643173 ps
CPU time 0.89 seconds
Started Jul 21 06:53:13 PM PDT 24
Finished Jul 21 06:53:14 PM PDT 24
Peak memory 206648 kb
Host smart-444d0ca1-5951-4b4e-b4f3-5fd8ae941884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32558
58912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.3255858912
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.4075778070
Short name T101
Test name
Test status
Simulation time 147124451 ps
CPU time 0.75 seconds
Started Jul 21 06:53:14 PM PDT 24
Finished Jul 21 06:53:15 PM PDT 24
Peak memory 206656 kb
Host smart-90e1c8c5-c016-4e65-9a42-9c41d44adb02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40757
78070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.4075778070
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.2251090540
Short name T210
Test name
Test status
Simulation time 258103729 ps
CPU time 0.96 seconds
Started Jul 21 06:53:14 PM PDT 24
Finished Jul 21 06:53:15 PM PDT 24
Peak memory 206680 kb
Host smart-b296f698-2ba6-4982-b07f-6b0d1ea425ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22510
90540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.2251090540
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.1049250052
Short name T860
Test name
Test status
Simulation time 8662409954 ps
CPU time 237.6 seconds
Started Jul 21 06:53:14 PM PDT 24
Finished Jul 21 06:57:12 PM PDT 24
Peak memory 206868 kb
Host smart-df9de181-dde2-4d02-9b45-6429cdab9d66
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1049250052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.1049250052
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_iso_retraction.4130773210
Short name T2562
Test name
Test status
Simulation time 9254058312 ps
CPU time 36.8 seconds
Started Jul 21 06:53:17 PM PDT 24
Finished Jul 21 06:53:55 PM PDT 24
Peak memory 206896 kb
Host smart-8c0f1b31-4fb6-4549-9ddd-8d30051a2af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41307
73210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_iso_retraction.4130773210
Directory /workspace/3.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2062163659
Short name T1028
Test name
Test status
Simulation time 190229013 ps
CPU time 0.79 seconds
Started Jul 21 06:53:15 PM PDT 24
Finished Jul 21 06:53:17 PM PDT 24
Peak memory 206168 kb
Host smart-3416e1cd-9e47-4edd-9eff-41780fcc953d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20621
63659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2062163659
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.3359313133
Short name T2425
Test name
Test status
Simulation time 23297780160 ps
CPU time 24.98 seconds
Started Jul 21 06:53:17 PM PDT 24
Finished Jul 21 06:53:43 PM PDT 24
Peak memory 206804 kb
Host smart-394c647e-b4f2-41f3-a0dd-335d253a359b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33593
13133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.3359313133
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.2118234484
Short name T1275
Test name
Test status
Simulation time 3312412732 ps
CPU time 3.61 seconds
Started Jul 21 06:53:13 PM PDT 24
Finished Jul 21 06:53:17 PM PDT 24
Peak memory 206720 kb
Host smart-41ef493e-3753-4c50-a809-ff7e128d1806
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21182
34484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.2118234484
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.3536206460
Short name T1774
Test name
Test status
Simulation time 9088803107 ps
CPU time 252.49 seconds
Started Jul 21 06:53:12 PM PDT 24
Finished Jul 21 06:57:25 PM PDT 24
Peak memory 206916 kb
Host smart-f26af9c5-e47d-4ecd-8744-8e0ba79115a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35362
06460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.3536206460
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.55835704
Short name T2299
Test name
Test status
Simulation time 6910316315 ps
CPU time 70.31 seconds
Started Jul 21 06:53:13 PM PDT 24
Finished Jul 21 06:54:24 PM PDT 24
Peak memory 206860 kb
Host smart-26d2d6ff-9b2b-44d5-977d-af0c9dc0e423
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=55835704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.55835704
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.785175848
Short name T1981
Test name
Test status
Simulation time 243203414 ps
CPU time 0.89 seconds
Started Jul 21 06:53:14 PM PDT 24
Finished Jul 21 06:53:15 PM PDT 24
Peak memory 206668 kb
Host smart-1f7094c9-4215-4291-a363-b8d3cb7bd111
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=785175848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.785175848
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.2173635081
Short name T1396
Test name
Test status
Simulation time 244037036 ps
CPU time 0.88 seconds
Started Jul 21 06:53:13 PM PDT 24
Finished Jul 21 06:53:14 PM PDT 24
Peak memory 206680 kb
Host smart-51223dd3-978f-46b4-9241-80de2593ace8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21736
35081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.2173635081
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.2185771074
Short name T2514
Test name
Test status
Simulation time 3828944427 ps
CPU time 36.62 seconds
Started Jul 21 06:53:15 PM PDT 24
Finished Jul 21 06:53:52 PM PDT 24
Peak memory 206852 kb
Host smart-9825f774-9a9e-44ca-afee-4406c18dc5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21857
71074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.2185771074
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.755018715
Short name T449
Test name
Test status
Simulation time 7158538451 ps
CPU time 52.66 seconds
Started Jul 21 06:53:12 PM PDT 24
Finished Jul 21 06:54:05 PM PDT 24
Peak memory 206880 kb
Host smart-ba6de8c2-2726-41b4-b09a-69ab554db0be
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=755018715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.755018715
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3587638977
Short name T692
Test name
Test status
Simulation time 149144649 ps
CPU time 0.8 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 206684 kb
Host smart-a2166d47-686d-49b6-947e-debcc25ac43c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3587638977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3587638977
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.188201583
Short name T2254
Test name
Test status
Simulation time 148859158 ps
CPU time 0.74 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206660 kb
Host smart-d8b90598-0f2d-4a3d-b84f-cb65f69fd6fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18820
1583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.188201583
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.3195915210
Short name T2335
Test name
Test status
Simulation time 200404602 ps
CPU time 0.9 seconds
Started Jul 21 06:53:21 PM PDT 24
Finished Jul 21 06:53:22 PM PDT 24
Peak memory 206688 kb
Host smart-7a18b2c2-89d7-4092-85cf-44cb753afad6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31959
15210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.3195915210
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1197400406
Short name T409
Test name
Test status
Simulation time 268326811 ps
CPU time 0.95 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206660 kb
Host smart-638e2960-ec30-42b2-8f48-224ab1a06672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11974
00406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1197400406
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.1577429337
Short name T855
Test name
Test status
Simulation time 147432412 ps
CPU time 0.8 seconds
Started Jul 21 06:53:19 PM PDT 24
Finished Jul 21 06:53:20 PM PDT 24
Peak memory 206652 kb
Host smart-9bfc1181-7a9b-4b1d-aaa0-70d17fe0865c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15774
29337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.1577429337
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1073453125
Short name T2397
Test name
Test status
Simulation time 181049848 ps
CPU time 0.82 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206700 kb
Host smart-2efb31c3-3ab8-4308-8849-109e987a333e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10734
53125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1073453125
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.2941532144
Short name T1789
Test name
Test status
Simulation time 145352937 ps
CPU time 0.79 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206672 kb
Host smart-d8172cf0-4f5f-4f7a-8077-aaa6ad290e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29415
32144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.2941532144
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.4196884383
Short name T751
Test name
Test status
Simulation time 244730037 ps
CPU time 0.94 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206700 kb
Host smart-26dea1c0-4428-4c1e-83d5-0ae0e4f138bb
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4196884383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.4196884383
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.1198745471
Short name T2187
Test name
Test status
Simulation time 238550471 ps
CPU time 1.04 seconds
Started Jul 21 06:53:19 PM PDT 24
Finished Jul 21 06:53:20 PM PDT 24
Peak memory 206608 kb
Host smart-de685a40-cbe0-401b-9681-ae39b8f17b1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11987
45471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.1198745471
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3793903127
Short name T1086
Test name
Test status
Simulation time 140428944 ps
CPU time 0.75 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206692 kb
Host smart-16b50659-5c40-414d-b5f4-67bf8307e30a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37939
03127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3793903127
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.1009095719
Short name T1053
Test name
Test status
Simulation time 54129579 ps
CPU time 0.68 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206656 kb
Host smart-2e99632f-86b2-40fc-b398-63f90b5f589f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10090
95719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.1009095719
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.1847435039
Short name T2219
Test name
Test status
Simulation time 16470065943 ps
CPU time 37.54 seconds
Started Jul 21 06:53:21 PM PDT 24
Finished Jul 21 06:54:00 PM PDT 24
Peak memory 206900 kb
Host smart-77f0c780-4843-4a10-9b29-08dadc575cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18474
35039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.1847435039
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.3063853464
Short name T1697
Test name
Test status
Simulation time 217044346 ps
CPU time 0.9 seconds
Started Jul 21 06:53:21 PM PDT 24
Finished Jul 21 06:53:22 PM PDT 24
Peak memory 206660 kb
Host smart-d48ca710-9724-497a-a33c-6e1d8c6bf31b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30638
53464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.3063853464
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.762851728
Short name T1900
Test name
Test status
Simulation time 171126049 ps
CPU time 0.8 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 206676 kb
Host smart-609008da-5ff8-40d3-a2fd-302ba9892e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76285
1728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.762851728
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.2649372272
Short name T2713
Test name
Test status
Simulation time 12524335893 ps
CPU time 85.61 seconds
Started Jul 21 06:53:23 PM PDT 24
Finished Jul 21 06:54:49 PM PDT 24
Peak memory 206960 kb
Host smart-9ee8669e-784a-48e4-81f0-83f07de72fb5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2649372272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.2649372272
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2229376545
Short name T2543
Test name
Test status
Simulation time 4309339550 ps
CPU time 33.83 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:57 PM PDT 24
Peak memory 206940 kb
Host smart-9aaa99c5-9cc4-4324-af4b-7db6c5657f1f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2229376545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2229376545
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2144523444
Short name T2174
Test name
Test status
Simulation time 8142401283 ps
CPU time 126.82 seconds
Started Jul 21 06:53:21 PM PDT 24
Finished Jul 21 06:55:29 PM PDT 24
Peak memory 206928 kb
Host smart-5750fb50-bce8-4e92-8735-6b8c6f61b082
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2144523444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2144523444
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.1060619689
Short name T723
Test name
Test status
Simulation time 225389878 ps
CPU time 0.92 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 206680 kb
Host smart-cc525a1d-b51e-4567-9ef1-c4306b9b9fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10606
19689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.1060619689
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2085472409
Short name T677
Test name
Test status
Simulation time 165957932 ps
CPU time 0.8 seconds
Started Jul 21 06:53:23 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206632 kb
Host smart-a5bc0088-c988-4f79-8c8b-b691aa81938e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20854
72409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2085472409
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.3014236423
Short name T1034
Test name
Test status
Simulation time 143103258 ps
CPU time 0.8 seconds
Started Jul 21 06:53:19 PM PDT 24
Finished Jul 21 06:53:20 PM PDT 24
Peak memory 206636 kb
Host smart-4e21b4f7-2bfe-41d6-8ee0-bc10433613af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30142
36423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.3014236423
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.2755842306
Short name T2560
Test name
Test status
Simulation time 169312354 ps
CPU time 0.83 seconds
Started Jul 21 06:53:21 PM PDT 24
Finished Jul 21 06:53:22 PM PDT 24
Peak memory 206712 kb
Host smart-40b9ca73-afac-4444-b594-1c992afee41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27558
42306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.2755842306
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.1042861696
Short name T188
Test name
Test status
Simulation time 298623902 ps
CPU time 1.13 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 224516 kb
Host smart-63f33308-291a-4ac4-8c25-9420ab410705
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1042861696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.1042861696
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.509552244
Short name T1609
Test name
Test status
Simulation time 486094129 ps
CPU time 1.36 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206668 kb
Host smart-f3632306-ec15-4b85-b643-0e3aca316c5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50955
2244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.509552244
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.2839036169
Short name T1257
Test name
Test status
Simulation time 305800752 ps
CPU time 0.97 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:53:24 PM PDT 24
Peak memory 206664 kb
Host smart-6de432dc-cbce-45b2-bcef-290176705ff0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28390
36169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.2839036169
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.3734809168
Short name T2523
Test name
Test status
Simulation time 162679103 ps
CPU time 0.81 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 206664 kb
Host smart-208ef9ab-da1e-415f-a694-f149f948b13c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37348
09168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.3734809168
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.1568629336
Short name T707
Test name
Test status
Simulation time 149042575 ps
CPU time 0.81 seconds
Started Jul 21 06:53:19 PM PDT 24
Finished Jul 21 06:53:20 PM PDT 24
Peak memory 206664 kb
Host smart-4f154696-f67c-4a7c-aad3-61b6ff88a092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15686
29336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.1568629336
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.1336287098
Short name T2401
Test name
Test status
Simulation time 242467169 ps
CPU time 1.05 seconds
Started Jul 21 06:53:20 PM PDT 24
Finished Jul 21 06:53:22 PM PDT 24
Peak memory 206672 kb
Host smart-3b9f7298-bf51-4e44-ba78-d1d4f947e811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13362
87098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.1336287098
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3333215421
Short name T2739
Test name
Test status
Simulation time 5072353260 ps
CPU time 38.26 seconds
Started Jul 21 06:53:23 PM PDT 24
Finished Jul 21 06:54:02 PM PDT 24
Peak memory 206920 kb
Host smart-b2d112a3-57a1-4129-873f-eba66e97980a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3333215421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3333215421
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.2414637176
Short name T342
Test name
Test status
Simulation time 182323500 ps
CPU time 0.89 seconds
Started Jul 21 06:53:20 PM PDT 24
Finished Jul 21 06:53:21 PM PDT 24
Peak memory 206672 kb
Host smart-654562d6-db0c-48c1-a075-1ec1a89223c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24146
37176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.2414637176
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.2416395656
Short name T312
Test name
Test status
Simulation time 187923010 ps
CPU time 0.86 seconds
Started Jul 21 06:53:20 PM PDT 24
Finished Jul 21 06:53:21 PM PDT 24
Peak memory 206668 kb
Host smart-9a7ed4bf-a99e-4ef7-bd46-1803ede3067d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24163
95656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.2416395656
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.3654040060
Short name T655
Test name
Test status
Simulation time 615178567 ps
CPU time 1.61 seconds
Started Jul 21 06:53:25 PM PDT 24
Finished Jul 21 06:53:28 PM PDT 24
Peak memory 206632 kb
Host smart-4eeb3e92-91d3-41ba-b2bb-e22421dea25f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36540
40060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.3654040060
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.1083552083
Short name T1824
Test name
Test status
Simulation time 5725250061 ps
CPU time 157.84 seconds
Started Jul 21 06:53:22 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206848 kb
Host smart-bb33c0b8-41b8-4b07-afa0-b5834f0fb088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10835
52083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.1083552083
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.3971738361
Short name T1064
Test name
Test status
Simulation time 45337957 ps
CPU time 0.67 seconds
Started Jul 21 06:57:57 PM PDT 24
Finished Jul 21 06:57:58 PM PDT 24
Peak memory 206680 kb
Host smart-ba5acb08-92a5-440c-9e76-e5dcac560a34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3971738361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.3971738361
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1837678430
Short name T1169
Test name
Test status
Simulation time 3514987107 ps
CPU time 4.05 seconds
Started Jul 21 06:58:02 PM PDT 24
Finished Jul 21 06:58:06 PM PDT 24
Peak memory 206836 kb
Host smart-a7e005b0-8105-4cee-90aa-c12aaf6b2c5c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1837678430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1837678430
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.3829057454
Short name T1186
Test name
Test status
Simulation time 13347044067 ps
CPU time 14.06 seconds
Started Jul 21 06:57:56 PM PDT 24
Finished Jul 21 06:58:10 PM PDT 24
Peak memory 206792 kb
Host smart-49019cb6-eb0d-4c79-ac68-64ef57f18004
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3829057454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.3829057454
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.4098660174
Short name T1331
Test name
Test status
Simulation time 23535088809 ps
CPU time 25.58 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:58:20 PM PDT 24
Peak memory 206896 kb
Host smart-04f36b8a-8f86-4d8c-aec1-2e7ef64b60c4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4098660174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.4098660174
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.3470210015
Short name T1471
Test name
Test status
Simulation time 194049487 ps
CPU time 0.86 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206676 kb
Host smart-c959938f-665f-423b-961a-768f392fb709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34702
10015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.3470210015
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.2172038996
Short name T1967
Test name
Test status
Simulation time 173299173 ps
CPU time 0.8 seconds
Started Jul 21 06:57:59 PM PDT 24
Finished Jul 21 06:58:00 PM PDT 24
Peak memory 206696 kb
Host smart-e6993852-4a12-4497-94df-99c9d5ae286f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21720
38996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.2172038996
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3589445595
Short name T875
Test name
Test status
Simulation time 323041224 ps
CPU time 1.23 seconds
Started Jul 21 06:57:54 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206624 kb
Host smart-94d534f0-950c-40ce-b9a2-7a6b0c6417ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35894
45595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3589445595
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.3183062406
Short name T1433
Test name
Test status
Simulation time 1658384622 ps
CPU time 3.51 seconds
Started Jul 21 06:58:00 PM PDT 24
Finished Jul 21 06:58:04 PM PDT 24
Peak memory 206816 kb
Host smart-29ad6c2e-722a-43ba-8620-4bcd8dad30ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31830
62406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.3183062406
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.2266982209
Short name T1455
Test name
Test status
Simulation time 15123929524 ps
CPU time 31.47 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:58:26 PM PDT 24
Peak memory 206956 kb
Host smart-60266c4c-b063-46d1-9151-85f21fd102c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22669
82209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.2266982209
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.2879896692
Short name T421
Test name
Test status
Simulation time 350662632 ps
CPU time 1.18 seconds
Started Jul 21 06:58:00 PM PDT 24
Finished Jul 21 06:58:02 PM PDT 24
Peak memory 206660 kb
Host smart-e76ac58a-e7d9-4b1a-9e8b-76ca7c2c33ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28798
96692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.2879896692
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3799486185
Short name T2109
Test name
Test status
Simulation time 155367212 ps
CPU time 0.75 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206692 kb
Host smart-10ee3267-d033-44d3-8d44-d0cc82526f65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37994
86185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3799486185
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.1655441385
Short name T1578
Test name
Test status
Simulation time 64974012 ps
CPU time 0.69 seconds
Started Jul 21 06:57:53 PM PDT 24
Finished Jul 21 06:57:55 PM PDT 24
Peak memory 206676 kb
Host smart-694cda24-1f62-4313-be49-037ab8a06038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16554
41385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.1655441385
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.1719872518
Short name T447
Test name
Test status
Simulation time 888447528 ps
CPU time 1.99 seconds
Started Jul 21 06:58:00 PM PDT 24
Finished Jul 21 06:58:03 PM PDT 24
Peak memory 206780 kb
Host smart-0e8a4b2a-87eb-4e97-8dca-9553fc66e0b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17198
72518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.1719872518
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.3801101236
Short name T2120
Test name
Test status
Simulation time 326617758 ps
CPU time 2.16 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 06:58:03 PM PDT 24
Peak memory 206884 kb
Host smart-c22343fb-9f4c-4439-b520-c10e5f6a2b97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38011
01236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.3801101236
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1189998012
Short name T2459
Test name
Test status
Simulation time 280803135 ps
CPU time 0.96 seconds
Started Jul 21 06:57:54 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206644 kb
Host smart-172262e6-adfa-4ca0-88fa-858f0a581f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11899
98012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1189998012
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.2641514270
Short name T1131
Test name
Test status
Simulation time 205128120 ps
CPU time 0.8 seconds
Started Jul 21 06:57:56 PM PDT 24
Finished Jul 21 06:57:58 PM PDT 24
Peak memory 206668 kb
Host smart-cb51fb59-d419-4602-8f73-eb7f0f8cdf08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26415
14270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.2641514270
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.3737122843
Short name T1322
Test name
Test status
Simulation time 219639719 ps
CPU time 0.96 seconds
Started Jul 21 06:57:54 PM PDT 24
Finished Jul 21 06:57:56 PM PDT 24
Peak memory 206676 kb
Host smart-caf8da6f-ddb3-40e2-9e22-9365b267f320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37371
22843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.3737122843
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_invalid_sync.2072020262
Short name T2563
Test name
Test status
Simulation time 8897826209 ps
CPU time 247.78 seconds
Started Jul 21 06:58:05 PM PDT 24
Finished Jul 21 07:02:13 PM PDT 24
Peak memory 206892 kb
Host smart-429fded5-f994-403c-b32a-f15ca3e627eb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2072020262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_invalid_sync.2072020262
Directory /workspace/30.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.1486566014
Short name T352
Test name
Test status
Simulation time 211613975 ps
CPU time 0.9 seconds
Started Jul 21 06:58:05 PM PDT 24
Finished Jul 21 06:58:06 PM PDT 24
Peak memory 206664 kb
Host smart-e81472e3-22ff-4ea4-8768-0e4efb8092c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14865
66014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.1486566014
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.3633821920
Short name T2687
Test name
Test status
Simulation time 23272922884 ps
CPU time 22.54 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:30 PM PDT 24
Peak memory 206812 kb
Host smart-a5da8f73-249a-4686-a0ad-8db20942c489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36338
21920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.3633821920
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.3516182428
Short name T1607
Test name
Test status
Simulation time 3277401413 ps
CPU time 4.01 seconds
Started Jul 21 06:58:12 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206732 kb
Host smart-8d7d16d7-5774-497a-bfaa-d51603c1ea91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35161
82428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.3516182428
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.1232135460
Short name T2074
Test name
Test status
Simulation time 8522764666 ps
CPU time 231.87 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 07:02:07 PM PDT 24
Peak memory 206920 kb
Host smart-d53c84f4-2c3a-4830-90a2-e1c93240fb97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12321
35460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.1232135460
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.723945941
Short name T1737
Test name
Test status
Simulation time 2949307645 ps
CPU time 21.27 seconds
Started Jul 21 06:58:00 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206852 kb
Host smart-b768cc34-652e-433c-82fb-c3d6f800f32b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=723945941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.723945941
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.1969052434
Short name T515
Test name
Test status
Simulation time 239658423 ps
CPU time 0.91 seconds
Started Jul 21 06:57:59 PM PDT 24
Finished Jul 21 06:58:00 PM PDT 24
Peak memory 206684 kb
Host smart-5b8e551e-e8ee-4a8c-a666-54d2afc8cf84
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1969052434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.1969052434
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1904387522
Short name T411
Test name
Test status
Simulation time 221393139 ps
CPU time 0.85 seconds
Started Jul 21 06:57:58 PM PDT 24
Finished Jul 21 06:57:59 PM PDT 24
Peak memory 206668 kb
Host smart-bda448fe-b7fb-455f-b7c6-4c29757ff8c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19043
87522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1904387522
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.3394219531
Short name T2308
Test name
Test status
Simulation time 3707356435 ps
CPU time 35.57 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206920 kb
Host smart-34107c32-989f-4a3b-953a-6b8f56ea1637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
19531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.3394219531
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3322302129
Short name T462
Test name
Test status
Simulation time 4553283790 ps
CPU time 123.96 seconds
Started Jul 21 06:57:59 PM PDT 24
Finished Jul 21 07:00:04 PM PDT 24
Peak memory 206868 kb
Host smart-139cf3f8-3dbb-49bd-b276-369a57b0b022
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3322302129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3322302129
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1209341019
Short name T1520
Test name
Test status
Simulation time 169568905 ps
CPU time 0.83 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 06:58:02 PM PDT 24
Peak memory 206656 kb
Host smart-386ca0c9-d674-4f8a-8b76-5d7d53422f54
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1209341019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1209341019
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.3379934276
Short name T1397
Test name
Test status
Simulation time 144561652 ps
CPU time 0.79 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 206648 kb
Host smart-8bff05fa-dd11-4f82-9c1d-c4b500a5c1f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33799
34276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.3379934276
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3308830930
Short name T2323
Test name
Test status
Simulation time 176397306 ps
CPU time 0.87 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:14 PM PDT 24
Peak memory 206672 kb
Host smart-36489bd5-46ed-4e85-bccf-b6f7b85ae37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33088
30930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3308830930
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.3499876969
Short name T1252
Test name
Test status
Simulation time 163715416 ps
CPU time 0.79 seconds
Started Jul 21 06:57:57 PM PDT 24
Finished Jul 21 06:57:59 PM PDT 24
Peak memory 206700 kb
Host smart-1e9737dc-b98d-4d1c-a68f-f3a818cfc800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34998
76969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.3499876969
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.2853579113
Short name T1989
Test name
Test status
Simulation time 181236320 ps
CPU time 0.9 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206664 kb
Host smart-d5d8b1fb-d2ab-45a8-b0e0-2d8d35a901e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28535
79113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.2853579113
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.773733112
Short name T2081
Test name
Test status
Simulation time 175269295 ps
CPU time 0.91 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206684 kb
Host smart-d2c5934e-b906-4660-a582-fc9d80f39413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77373
3112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.773733112
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.1196953049
Short name T2099
Test name
Test status
Simulation time 193722066 ps
CPU time 0.88 seconds
Started Jul 21 06:57:59 PM PDT 24
Finished Jul 21 06:58:00 PM PDT 24
Peak memory 206648 kb
Host smart-173b7c7c-e70c-48a7-aa0a-aa36e8fd754a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1196953049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.1196953049
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.2818482901
Short name T1508
Test name
Test status
Simulation time 160798170 ps
CPU time 0.89 seconds
Started Jul 21 06:58:08 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206688 kb
Host smart-7f7ed99f-4206-49c7-bf84-23b095286f85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28184
82901 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.2818482901
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.3520067910
Short name T1272
Test name
Test status
Simulation time 49908911 ps
CPU time 0.68 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 06:58:07 PM PDT 24
Peak memory 206632 kb
Host smart-5317818a-d72b-4297-9fdf-c86263178ff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
67910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.3520067910
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.934566165
Short name T1300
Test name
Test status
Simulation time 7830415060 ps
CPU time 17.06 seconds
Started Jul 21 06:58:10 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206952 kb
Host smart-82f19304-f485-4d3a-ba66-793aca456bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93456
6165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.934566165
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.1180129832
Short name T1733
Test name
Test status
Simulation time 232953408 ps
CPU time 0.96 seconds
Started Jul 21 06:57:59 PM PDT 24
Finished Jul 21 06:58:01 PM PDT 24
Peak memory 206680 kb
Host smart-1465dae0-1a8c-4a52-aadd-0ac6d84b4a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11801
29832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.1180129832
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1045896542
Short name T1541
Test name
Test status
Simulation time 186670082 ps
CPU time 0.94 seconds
Started Jul 21 06:58:16 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 206664 kb
Host smart-fcf46671-bb90-40bf-90dc-024fd10c3495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10458
96542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1045896542
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.4258120688
Short name T2698
Test name
Test status
Simulation time 169387145 ps
CPU time 0.9 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 206564 kb
Host smart-4272a053-b4a8-4a3f-be13-c1cc368da33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42581
20688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.4258120688
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.1930624930
Short name T450
Test name
Test status
Simulation time 168865068 ps
CPU time 0.83 seconds
Started Jul 21 06:57:58 PM PDT 24
Finished Jul 21 06:57:59 PM PDT 24
Peak memory 206608 kb
Host smart-df4cef4d-e3c2-4d81-9352-de3fbdb53206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19306
24930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.1930624930
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.4117178536
Short name T1023
Test name
Test status
Simulation time 177222447 ps
CPU time 0.8 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 06:58:02 PM PDT 24
Peak memory 206644 kb
Host smart-17dc7d19-f751-4dbd-8b32-91976c36acc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41171
78536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.4117178536
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3555242162
Short name T1160
Test name
Test status
Simulation time 157318748 ps
CPU time 0.78 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:14 PM PDT 24
Peak memory 206564 kb
Host smart-5e43af2e-ec29-4656-9dd3-534e4ebcc718
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35552
42162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3555242162
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2329968429
Short name T2046
Test name
Test status
Simulation time 158497655 ps
CPU time 0.84 seconds
Started Jul 21 06:57:57 PM PDT 24
Finished Jul 21 06:57:59 PM PDT 24
Peak memory 206684 kb
Host smart-3005305f-c631-4767-9159-1725c14fadba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23299
68429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2329968429
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.3982943174
Short name T851
Test name
Test status
Simulation time 218628244 ps
CPU time 0.96 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 06:58:02 PM PDT 24
Peak memory 206656 kb
Host smart-8368aa93-6473-4c48-a44a-4e1d8f4f109b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39829
43174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.3982943174
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2766460970
Short name T1754
Test name
Test status
Simulation time 3300155696 ps
CPU time 24.19 seconds
Started Jul 21 06:57:59 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206932 kb
Host smart-0049545d-f94d-4b7e-bdec-f018d7058c84
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2766460970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2766460970
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.3216158960
Short name T1260
Test name
Test status
Simulation time 230001750 ps
CPU time 0.81 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 206660 kb
Host smart-1d877dfd-dddf-42a7-89d9-cf77caccc5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32161
58960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.3216158960
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2576895886
Short name T2579
Test name
Test status
Simulation time 160647927 ps
CPU time 0.81 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 206560 kb
Host smart-18a87b69-12ce-4882-a41e-c1d9f6ff5606
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25768
95886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2576895886
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.1008648248
Short name T1375
Test name
Test status
Simulation time 965526287 ps
CPU time 2.05 seconds
Started Jul 21 06:58:00 PM PDT 24
Finished Jul 21 06:58:03 PM PDT 24
Peak memory 206804 kb
Host smart-2bc177ad-0469-4461-a84c-dd5927948ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10086
48248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.1008648248
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.2699255040
Short name T560
Test name
Test status
Simulation time 4142598129 ps
CPU time 114.35 seconds
Started Jul 21 06:58:03 PM PDT 24
Finished Jul 21 06:59:57 PM PDT 24
Peak memory 206872 kb
Host smart-a000c9a5-f8ad-4123-b2f8-4db31fed9a89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26992
55040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.2699255040
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1696526016
Short name T868
Test name
Test status
Simulation time 80021305 ps
CPU time 0.71 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:19 PM PDT 24
Peak memory 206732 kb
Host smart-be9691fb-3e2f-48a7-b4a6-1cf58d08d8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1696526016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1696526016
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3012639980
Short name T1423
Test name
Test status
Simulation time 4240283542 ps
CPU time 5.01 seconds
Started Jul 21 06:58:01 PM PDT 24
Finished Jul 21 06:58:07 PM PDT 24
Peak memory 206740 kb
Host smart-600902f4-e203-46f1-8eb6-0b77d9b0cee5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3012639980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3012639980
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.584275525
Short name T1000
Test name
Test status
Simulation time 13365879693 ps
CPU time 12.95 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206840 kb
Host smart-bb1bcd56-eebb-45e2-9ae7-6f65b236d824
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=584275525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.584275525
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.1047869631
Short name T14
Test name
Test status
Simulation time 23367018018 ps
CPU time 23.21 seconds
Started Jul 21 06:58:10 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206808 kb
Host smart-a9dbc0f6-c6f5-4434-9909-b62924cb3b3a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1047869631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.1047869631
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.1609719621
Short name T1332
Test name
Test status
Simulation time 173685233 ps
CPU time 0.79 seconds
Started Jul 21 06:58:06 PM PDT 24
Finished Jul 21 06:58:08 PM PDT 24
Peak memory 206676 kb
Host smart-a5a44e9a-6f03-4b82-bd30-58c84b339a31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16097
19621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.1609719621
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1942004118
Short name T408
Test name
Test status
Simulation time 228147098 ps
CPU time 0.85 seconds
Started Jul 21 06:58:06 PM PDT 24
Finished Jul 21 06:58:07 PM PDT 24
Peak memory 206660 kb
Host smart-cabfb1f7-8c5a-4947-8d5e-43837e5291aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
04118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1942004118
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3868546000
Short name T574
Test name
Test status
Simulation time 543875025 ps
CPU time 1.63 seconds
Started Jul 21 06:58:03 PM PDT 24
Finished Jul 21 06:58:05 PM PDT 24
Peak memory 206752 kb
Host smart-1e051011-2fb1-40bc-94d3-1a4f7888b5cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38685
46000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3868546000
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.3432401371
Short name T2482
Test name
Test status
Simulation time 589180785 ps
CPU time 1.55 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206676 kb
Host smart-3d29762e-81e6-4868-8200-27d0cd077ac4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34324
01371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.3432401371
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.1738111499
Short name T1750
Test name
Test status
Simulation time 21872233799 ps
CPU time 43.65 seconds
Started Jul 21 06:58:08 PM PDT 24
Finished Jul 21 06:58:52 PM PDT 24
Peak memory 206872 kb
Host smart-cb52b763-4592-470a-85f9-05d082d8e014
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17381
11499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.1738111499
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.292024444
Short name T2742
Test name
Test status
Simulation time 514578732 ps
CPU time 1.53 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206696 kb
Host smart-4ea8d364-f2bd-407d-87e6-22deae34550f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29202
4444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.292024444
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.1689655400
Short name T996
Test name
Test status
Simulation time 166981754 ps
CPU time 0.76 seconds
Started Jul 21 06:58:12 PM PDT 24
Finished Jul 21 06:58:13 PM PDT 24
Peak memory 206688 kb
Host smart-bc8740a5-4507-476a-b4f0-66cafe015d70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16896
55400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.1689655400
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.2816957399
Short name T2293
Test name
Test status
Simulation time 78614052 ps
CPU time 0.71 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206656 kb
Host smart-ca91b13b-350b-4e32-86ad-64e96eaaec37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28169
57399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.2816957399
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2530404783
Short name T2162
Test name
Test status
Simulation time 982335515 ps
CPU time 2.24 seconds
Started Jul 21 06:58:17 PM PDT 24
Finished Jul 21 06:58:19 PM PDT 24
Peak memory 206744 kb
Host smart-30417546-49e8-4727-b6b8-a95b6f00b8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25304
04783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2530404783
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3751123426
Short name T1248
Test name
Test status
Simulation time 430298102 ps
CPU time 2.67 seconds
Started Jul 21 06:58:17 PM PDT 24
Finished Jul 21 06:58:20 PM PDT 24
Peak memory 206804 kb
Host smart-52f8f679-0f80-4e86-bc61-260a364d0c72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37511
23426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3751123426
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.91775316
Short name T1387
Test name
Test status
Simulation time 226010060 ps
CPU time 0.97 seconds
Started Jul 21 06:58:15 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 206648 kb
Host smart-8f34f354-6eca-4a50-b723-729be008091e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91775
316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.91775316
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.3606531053
Short name T1236
Test name
Test status
Simulation time 139195384 ps
CPU time 0.75 seconds
Started Jul 21 06:58:08 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206668 kb
Host smart-d807bba1-8852-4019-ab52-78cd277b8bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36065
31053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.3606531053
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.113699295
Short name T650
Test name
Test status
Simulation time 255537267 ps
CPU time 0.91 seconds
Started Jul 21 06:58:11 PM PDT 24
Finished Jul 21 06:58:12 PM PDT 24
Peak memory 206684 kb
Host smart-e0f5b5f5-ddce-40f1-846d-00ef8c0e7121
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11369
9295 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.113699295
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_invalid_sync.2913294432
Short name T1096
Test name
Test status
Simulation time 8363179137 ps
CPU time 229.95 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 206876 kb
Host smart-f088c323-5b61-4814-a0fb-983e2eed1c9a
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2913294432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_invalid_sync.2913294432
Directory /workspace/31.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.2609894786
Short name T2555
Test name
Test status
Simulation time 5864065711 ps
CPU time 45.52 seconds
Started Jul 21 06:58:03 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206848 kb
Host smart-97c59977-b719-4eb2-9527-863462ca4763
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26098
94786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.2609894786
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.1395359999
Short name T934
Test name
Test status
Simulation time 170794731 ps
CPU time 0.81 seconds
Started Jul 21 06:58:12 PM PDT 24
Finished Jul 21 06:58:13 PM PDT 24
Peak memory 206664 kb
Host smart-5d982553-996e-4926-ba3d-cc15d75103a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13953
59999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.1395359999
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.257120805
Short name T1821
Test name
Test status
Simulation time 23365279570 ps
CPU time 23.96 seconds
Started Jul 21 06:58:15 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206804 kb
Host smart-20ea3e8e-4293-420d-ad0b-20d2f0f4b847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25712
0805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.257120805
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.3249720008
Short name T675
Test name
Test status
Simulation time 3321950372 ps
CPU time 3.84 seconds
Started Jul 21 06:58:12 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206748 kb
Host smart-2566e435-eb70-4a6f-84b7-bec7e459c728
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32497
20008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.3249720008
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.684785099
Short name T2650
Test name
Test status
Simulation time 7253885773 ps
CPU time 202.24 seconds
Started Jul 21 06:58:06 PM PDT 24
Finished Jul 21 07:01:29 PM PDT 24
Peak memory 206960 kb
Host smart-2f38edea-9e31-437e-93fa-0d32b909cefe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68478
5099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.684785099
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.3906518122
Short name T2320
Test name
Test status
Simulation time 5364490976 ps
CPU time 36.1 seconds
Started Jul 21 06:58:05 PM PDT 24
Finished Jul 21 06:58:42 PM PDT 24
Peak memory 206948 kb
Host smart-f3e7df2b-d858-4b5a-a177-74648cf54687
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3906518122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.3906518122
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.2349344560
Short name T2409
Test name
Test status
Simulation time 243117633 ps
CPU time 0.98 seconds
Started Jul 21 06:58:19 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206696 kb
Host smart-8afa544b-2e15-4b35-bfb9-98dcc6d60f37
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2349344560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.2349344560
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.4157913671
Short name T1731
Test name
Test status
Simulation time 207225756 ps
CPU time 0.92 seconds
Started Jul 21 06:58:11 PM PDT 24
Finished Jul 21 06:58:12 PM PDT 24
Peak memory 206680 kb
Host smart-eab3c369-6a85-4611-ae45-a469e556b758
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41579
13671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.4157913671
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.31748530
Short name T2654
Test name
Test status
Simulation time 3464534398 ps
CPU time 31.91 seconds
Started Jul 21 06:58:12 PM PDT 24
Finished Jul 21 06:58:44 PM PDT 24
Peak memory 206956 kb
Host smart-ca3081ab-09de-4a84-85e3-3a807fbd5ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31748
530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.31748530
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.4108419903
Short name T2020
Test name
Test status
Simulation time 5544461201 ps
CPU time 40.18 seconds
Started Jul 21 06:58:17 PM PDT 24
Finished Jul 21 06:58:58 PM PDT 24
Peak memory 206920 kb
Host smart-9500b71d-898c-4bd3-9de4-d6195c3446c2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4108419903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.4108419903
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.3163317608
Short name T856
Test name
Test status
Simulation time 191053496 ps
CPU time 0.83 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:08 PM PDT 24
Peak memory 206668 kb
Host smart-b0354b8f-5254-4c7b-9a42-6fd54baf0f24
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3163317608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.3163317608
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.840090232
Short name T1653
Test name
Test status
Simulation time 142200785 ps
CPU time 0.75 seconds
Started Jul 21 06:58:16 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 206680 kb
Host smart-f53eb652-20c4-4e62-850d-65ce19ca1c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84009
0232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.840090232
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.3063233721
Short name T111
Test name
Test status
Simulation time 190643234 ps
CPU time 0.94 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 206696 kb
Host smart-bc589161-362d-47be-ac22-a87d3e6ea7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30632
33721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.3063233721
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.369077643
Short name T1676
Test name
Test status
Simulation time 169473818 ps
CPU time 0.85 seconds
Started Jul 21 06:58:05 PM PDT 24
Finished Jul 21 06:58:07 PM PDT 24
Peak memory 206704 kb
Host smart-ed344359-6a7a-4fb8-bf0f-ba4dbbe9800d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36907
7643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.369077643
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.1309579175
Short name T2458
Test name
Test status
Simulation time 157520672 ps
CPU time 0.81 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206672 kb
Host smart-8c28eed4-4c5d-4ac7-baf8-0d62f1d27de8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13095
79175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.1309579175
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.3366196445
Short name T1530
Test name
Test status
Simulation time 197217903 ps
CPU time 0.85 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:08 PM PDT 24
Peak memory 206652 kb
Host smart-c6393cb4-b5f6-47ea-8d34-5004ee4f820b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33661
96445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.3366196445
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.282027790
Short name T2193
Test name
Test status
Simulation time 159626965 ps
CPU time 0.79 seconds
Started Jul 21 06:58:03 PM PDT 24
Finished Jul 21 06:58:05 PM PDT 24
Peak memory 206632 kb
Host smart-79227454-af65-4c88-8670-7129460561ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28202
7790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.282027790
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.2018658154
Short name T2055
Test name
Test status
Simulation time 263832229 ps
CPU time 0.97 seconds
Started Jul 21 06:58:11 PM PDT 24
Finished Jul 21 06:58:12 PM PDT 24
Peak memory 206608 kb
Host smart-93223d81-4996-4b7f-9c50-67d7a38ab8ed
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2018658154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.2018658154
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3245658748
Short name T1857
Test name
Test status
Simulation time 162527233 ps
CPU time 0.8 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206668 kb
Host smart-52b98fbd-b9cc-4bda-8917-2c6357335c6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32456
58748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3245658748
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.3949197974
Short name T616
Test name
Test status
Simulation time 36732479 ps
CPU time 0.65 seconds
Started Jul 21 06:58:19 PM PDT 24
Finished Jul 21 06:58:20 PM PDT 24
Peak memory 206692 kb
Host smart-0e3665cf-df11-484f-a10d-fac2838d7715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39491
97974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.3949197974
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.63296478
Short name T246
Test name
Test status
Simulation time 18311823789 ps
CPU time 40.41 seconds
Started Jul 21 06:58:17 PM PDT 24
Finished Jul 21 06:58:58 PM PDT 24
Peak memory 206956 kb
Host smart-84521aca-d63c-4624-a997-7e0d55d1e802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63296
478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.63296478
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.4109406278
Short name T2105
Test name
Test status
Simulation time 180844162 ps
CPU time 0.86 seconds
Started Jul 21 06:58:11 PM PDT 24
Finished Jul 21 06:58:13 PM PDT 24
Peak memory 206656 kb
Host smart-422e5b6d-a023-49f5-896f-831749c2eeca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41094
06278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.4109406278
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.3491115814
Short name T2366
Test name
Test status
Simulation time 165208838 ps
CPU time 0.84 seconds
Started Jul 21 06:58:07 PM PDT 24
Finished Jul 21 06:58:09 PM PDT 24
Peak memory 206664 kb
Host smart-a6a9dee5-64db-4746-8423-3bff0a74bb27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34911
15814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.3491115814
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.1831045512
Short name T1568
Test name
Test status
Simulation time 194492258 ps
CPU time 0.81 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:19 PM PDT 24
Peak memory 206564 kb
Host smart-f8a9a75c-92b0-4017-a2fa-a11f60fd488c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18310
45512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.1831045512
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.4215874836
Short name T1157
Test name
Test status
Simulation time 162395051 ps
CPU time 0.83 seconds
Started Jul 21 06:58:19 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206780 kb
Host smart-7e5e43bf-76a1-42f7-a178-d6d89d578a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42158
74836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.4215874836
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.1779714361
Short name T719
Test name
Test status
Simulation time 198104966 ps
CPU time 0.8 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:26 PM PDT 24
Peak memory 206208 kb
Host smart-c02163a4-d3c2-43fe-a83d-3138265bb051
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17797
14361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.1779714361
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.194695080
Short name T432
Test name
Test status
Simulation time 151735784 ps
CPU time 0.76 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:26 PM PDT 24
Peak memory 206188 kb
Host smart-08f1f0c4-9481-4da6-927d-94040b379314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19469
5080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.194695080
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.1045514871
Short name T890
Test name
Test status
Simulation time 162464399 ps
CPU time 0.81 seconds
Started Jul 21 06:58:10 PM PDT 24
Finished Jul 21 06:58:11 PM PDT 24
Peak memory 206628 kb
Host smart-e2fcbb4d-4cf8-4e82-8a41-0e95c736282d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10455
14871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.1045514871
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3815642307
Short name T1486
Test name
Test status
Simulation time 224389573 ps
CPU time 0.96 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:14 PM PDT 24
Peak memory 206644 kb
Host smart-4ae5e23f-1904-4b78-a835-1124d183c3c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38156
42307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3815642307
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.1252352222
Short name T603
Test name
Test status
Simulation time 3582651031 ps
CPU time 26.62 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:48 PM PDT 24
Peak memory 207028 kb
Host smart-33fe6c2c-a003-437e-9a5d-4277cb167b67
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1252352222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.1252352222
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.3921788071
Short name T2445
Test name
Test status
Simulation time 178337986 ps
CPU time 0.94 seconds
Started Jul 21 06:58:09 PM PDT 24
Finished Jul 21 06:58:10 PM PDT 24
Peak memory 206660 kb
Host smart-00587e80-0b2c-49bd-bc36-37cf7c0ae078
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217
88071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.3921788071
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3376606959
Short name T2156
Test name
Test status
Simulation time 169374411 ps
CPU time 0.84 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206660 kb
Host smart-44fda4dd-94b6-42e2-b07c-60ff5266a289
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33766
06959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3376606959
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.2671726263
Short name T1294
Test name
Test status
Simulation time 1002927528 ps
CPU time 2.19 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206732 kb
Host smart-e8813a10-7c8b-4d5a-b6d1-6214b1442c14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26717
26263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.2671726263
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.2308223690
Short name T1425
Test name
Test status
Simulation time 4087712370 ps
CPU time 115.72 seconds
Started Jul 21 06:58:08 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206880 kb
Host smart-01e5e641-cfa4-4ac3-a167-21bc96211b3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23082
23690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.2308223690
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.3009010632
Short name T678
Test name
Test status
Simulation time 36144856 ps
CPU time 0.63 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206672 kb
Host smart-575d4148-c947-45a1-8a2f-372b35897334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3009010632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.3009010632
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.3530776038
Short name T2091
Test name
Test status
Simulation time 3729192265 ps
CPU time 4.63 seconds
Started Jul 21 06:58:16 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206724 kb
Host smart-d5060802-82e7-41fa-9b71-269216829b7c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3530776038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.3530776038
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.2367378610
Short name T1863
Test name
Test status
Simulation time 13410239292 ps
CPU time 12.96 seconds
Started Jul 21 06:58:10 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206812 kb
Host smart-205e74b0-2200-43a9-8466-ab03b2520f32
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2367378610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.2367378610
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.2185646033
Short name T2126
Test name
Test status
Simulation time 23328336526 ps
CPU time 22.27 seconds
Started Jul 21 06:58:09 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206924 kb
Host smart-0d0ff7de-0299-4cc0-9426-6f3e2bd43e16
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2185646033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.2185646033
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.906482832
Short name T2573
Test name
Test status
Simulation time 166961895 ps
CPU time 0.85 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206604 kb
Host smart-1fe2e45f-8429-4ec9-a1d3-56e9ce55060e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90648
2832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.906482832
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.696059525
Short name T2515
Test name
Test status
Simulation time 158181891 ps
CPU time 0.94 seconds
Started Jul 21 06:58:10 PM PDT 24
Finished Jul 21 06:58:11 PM PDT 24
Peak memory 206684 kb
Host smart-8151a3b3-70c5-4370-8280-aac059a821eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69605
9525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.696059525
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.1966488859
Short name T1123
Test name
Test status
Simulation time 255818995 ps
CPU time 1 seconds
Started Jul 21 06:58:08 PM PDT 24
Finished Jul 21 06:58:10 PM PDT 24
Peak memory 206672 kb
Host smart-7c77cd8e-3a98-428b-8ac9-4783c1aa2489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19664
88859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.1966488859
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.1118132574
Short name T610
Test name
Test status
Simulation time 340572568 ps
CPU time 1.09 seconds
Started Jul 21 06:58:19 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206680 kb
Host smart-cfff0959-d35e-4b1c-b190-697c7c5d43d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11181
32574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.1118132574
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.2892072891
Short name T1457
Test name
Test status
Simulation time 10844799502 ps
CPU time 20.84 seconds
Started Jul 21 06:58:19 PM PDT 24
Finished Jul 21 06:58:41 PM PDT 24
Peak memory 206928 kb
Host smart-873dbed0-6808-4646-8d53-f069d0ec56d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28920
72891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.2892072891
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.2810255445
Short name T2484
Test name
Test status
Simulation time 374751985 ps
CPU time 1.22 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:19 PM PDT 24
Peak memory 206628 kb
Host smart-c1627d79-9234-4bef-95dd-7f77b8caf7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28102
55445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.2810255445
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_enable.4083482682
Short name T2122
Test name
Test status
Simulation time 44343024 ps
CPU time 0.68 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:22 PM PDT 24
Peak memory 206644 kb
Host smart-3ecdcff5-ba93-4afd-ad0a-95a469c16bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40834
82682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.4083482682
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.749810930
Short name T1352
Test name
Test status
Simulation time 869434700 ps
CPU time 2.34 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 06:58:24 PM PDT 24
Peak memory 206736 kb
Host smart-3f547202-d3f1-4835-b28f-50462123bdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74981
0930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.749810930
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.1298520508
Short name T2149
Test name
Test status
Simulation time 219331840 ps
CPU time 1.82 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:20 PM PDT 24
Peak memory 206748 kb
Host smart-218b45d4-33f0-4ee6-8c35-a33eb0cf5fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12985
20508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.1298520508
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1602434316
Short name T1512
Test name
Test status
Simulation time 202684739 ps
CPU time 0.85 seconds
Started Jul 21 06:58:15 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206648 kb
Host smart-14df171f-ffff-42de-8f01-a99de59b6a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16024
34316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1602434316
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.1972058943
Short name T2532
Test name
Test status
Simulation time 138752930 ps
CPU time 0.74 seconds
Started Jul 21 06:58:19 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206652 kb
Host smart-ef8fc48f-c75a-49f0-9dea-1e84e48b1cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19720
58943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.1972058943
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.1161484761
Short name T814
Test name
Test status
Simulation time 202341575 ps
CPU time 0.94 seconds
Started Jul 21 06:58:13 PM PDT 24
Finished Jul 21 06:58:15 PM PDT 24
Peak memory 206692 kb
Host smart-2d8d3e3e-df8f-4493-a624-2467ce644af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11614
84761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.1161484761
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.897020735
Short name T1015
Test name
Test status
Simulation time 7730295945 ps
CPU time 75.21 seconds
Started Jul 21 06:58:22 PM PDT 24
Finished Jul 21 06:59:38 PM PDT 24
Peak memory 206856 kb
Host smart-8d68c3e4-182a-4018-a7b1-37c2c0aa7cdd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=897020735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.897020735
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.2650039889
Short name T1072
Test name
Test status
Simulation time 12778871812 ps
CPU time 37.25 seconds
Started Jul 21 06:58:24 PM PDT 24
Finished Jul 21 06:59:02 PM PDT 24
Peak memory 206884 kb
Host smart-ddb758ed-e279-4638-b51a-201931ada30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26500
39889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.2650039889
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1385674830
Short name T2267
Test name
Test status
Simulation time 176166157 ps
CPU time 0.78 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:19 PM PDT 24
Peak memory 206676 kb
Host smart-c4776141-0e95-4f36-9d83-b3acdf937c3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
74830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1385674830
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.4209547750
Short name T1371
Test name
Test status
Simulation time 23299644273 ps
CPU time 24.01 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206812 kb
Host smart-086e4f2e-9d14-48ce-b270-b7bbed6819df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42095
47750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.4209547750
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.2235681479
Short name T2266
Test name
Test status
Simulation time 3291380730 ps
CPU time 3.95 seconds
Started Jul 21 06:58:24 PM PDT 24
Finished Jul 21 06:58:29 PM PDT 24
Peak memory 206664 kb
Host smart-ad261324-4230-4f2e-803e-4f253fefca59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22356
81479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.2235681479
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.2341404483
Short name T2479
Test name
Test status
Simulation time 12704244555 ps
CPU time 118.66 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 07:00:20 PM PDT 24
Peak memory 206292 kb
Host smart-8c569ffd-b454-42e9-ac24-8dcfcae3bd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23414
04483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.2341404483
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.4169547965
Short name T2646
Test name
Test status
Simulation time 6731551089 ps
CPU time 67.14 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206864 kb
Host smart-4b4f6bd9-e3a4-43b3-af0f-a88c6e8bc45c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4169547965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.4169547965
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.2013395516
Short name T294
Test name
Test status
Simulation time 266511748 ps
CPU time 0.9 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:19 PM PDT 24
Peak memory 206692 kb
Host smart-b98c1d8e-e62c-4f92-8ded-2316b70818e9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2013395516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.2013395516
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3976572071
Short name T1916
Test name
Test status
Simulation time 253154472 ps
CPU time 0.92 seconds
Started Jul 21 06:58:19 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206664 kb
Host smart-c333a26b-5131-4b05-a804-490a74bacb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39765
72071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3976572071
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1830374386
Short name T2439
Test name
Test status
Simulation time 5568394069 ps
CPU time 55.12 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206928 kb
Host smart-4dc7404b-0d18-4ae4-af3f-93d39a51d92f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
74386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1830374386
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.505441000
Short name T2134
Test name
Test status
Simulation time 5130351202 ps
CPU time 136.03 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 07:00:38 PM PDT 24
Peak memory 206808 kb
Host smart-8654916a-1e71-4d02-b926-49e3c8f1901d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=505441000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.505441000
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.2152443984
Short name T2525
Test name
Test status
Simulation time 156205196 ps
CPU time 0.77 seconds
Started Jul 21 06:58:15 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206656 kb
Host smart-2582f667-5c9b-48dd-8083-191c546ee468
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2152443984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.2152443984
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.523937217
Short name T1398
Test name
Test status
Simulation time 157136344 ps
CPU time 0.75 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:21 PM PDT 24
Peak memory 206648 kb
Host smart-1775aaad-4eb7-41cc-9e50-0bc3bad0f9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52393
7217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.523937217
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.2635663773
Short name T105
Test name
Test status
Simulation time 227971268 ps
CPU time 0.93 seconds
Started Jul 21 06:58:14 PM PDT 24
Finished Jul 21 06:58:16 PM PDT 24
Peak memory 206668 kb
Host smart-f98946b4-0c4c-4761-91f7-6c8e6d33fe61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26356
63773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.2635663773
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.471517783
Short name T422
Test name
Test status
Simulation time 192892092 ps
CPU time 0.89 seconds
Started Jul 21 06:58:15 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 206692 kb
Host smart-06476d23-53bb-47c8-a83d-a02b1ecafcca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47151
7783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.471517783
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.682513669
Short name T1436
Test name
Test status
Simulation time 200456050 ps
CPU time 0.81 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206564 kb
Host smart-4726408f-ed3e-46d3-99e0-8f0cc315cdf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68251
3669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.682513669
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.348086490
Short name T2616
Test name
Test status
Simulation time 192873708 ps
CPU time 0.86 seconds
Started Jul 21 06:58:16 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 206632 kb
Host smart-88ed3123-1990-4cb9-9e0f-cf48b62a80e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34808
6490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.348086490
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.1122783095
Short name T142
Test name
Test status
Simulation time 183163847 ps
CPU time 0.81 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206660 kb
Host smart-7674dcdb-0173-4e3c-bf9e-53b80923c047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
83095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.1122783095
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.2220601797
Short name T1167
Test name
Test status
Simulation time 256286933 ps
CPU time 0.99 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206564 kb
Host smart-5e2393a0-250f-4cbc-8553-edcdcd5c2856
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2220601797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.2220601797
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.4001085261
Short name T657
Test name
Test status
Simulation time 199038263 ps
CPU time 0.8 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:19 PM PDT 24
Peak memory 206564 kb
Host smart-7c673bf0-0cbe-41fb-a393-dbefc22ee20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40010
85261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.4001085261
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1552953695
Short name T1884
Test name
Test status
Simulation time 35306165 ps
CPU time 0.66 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:22 PM PDT 24
Peak memory 206652 kb
Host smart-60de0aea-f274-453d-b10b-f1263e7f5218
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15529
53695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1552953695
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.1360402233
Short name T1241
Test name
Test status
Simulation time 20431608181 ps
CPU time 45.49 seconds
Started Jul 21 06:58:24 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206932 kb
Host smart-5a1a5e11-ee1e-407d-8df8-13bca3e9e765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13604
02233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.1360402233
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.406587236
Short name T2710
Test name
Test status
Simulation time 220138831 ps
CPU time 0.88 seconds
Started Jul 21 06:58:27 PM PDT 24
Finished Jul 21 06:58:29 PM PDT 24
Peak memory 206672 kb
Host smart-3ec0b596-939b-49a1-8129-71822abd4580
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40658
7236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.406587236
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.4114746440
Short name T2270
Test name
Test status
Simulation time 205160193 ps
CPU time 0.89 seconds
Started Jul 21 06:58:22 PM PDT 24
Finished Jul 21 06:58:24 PM PDT 24
Peak memory 206692 kb
Host smart-0b1e653c-822b-4c85-bcc5-1355992d501a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41147
46440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.4114746440
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.1270429472
Short name T2186
Test name
Test status
Simulation time 182139667 ps
CPU time 0.81 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206628 kb
Host smart-47e467c5-d263-4330-a7a5-fe0773cc165d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12704
29472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.1270429472
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.191611652
Short name T1830
Test name
Test status
Simulation time 158292834 ps
CPU time 0.78 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206700 kb
Host smart-072b4e35-069d-4795-9031-c6e40607276b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19161
1652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.191611652
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1769072241
Short name T840
Test name
Test status
Simulation time 161650943 ps
CPU time 0.88 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:22 PM PDT 24
Peak memory 206612 kb
Host smart-78c2547b-c602-4bc3-b192-8c63999d0250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17690
72241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1769072241
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.4080845573
Short name T2597
Test name
Test status
Simulation time 205795695 ps
CPU time 0.84 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:22 PM PDT 24
Peak memory 206656 kb
Host smart-8c0dcba6-6f3e-449d-8da6-551bdf822923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40808
45573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.4080845573
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1805454189
Short name T1290
Test name
Test status
Simulation time 155693756 ps
CPU time 0.8 seconds
Started Jul 21 06:58:27 PM PDT 24
Finished Jul 21 06:58:29 PM PDT 24
Peak memory 206564 kb
Host smart-ec227e53-d045-442d-9105-e741e5ef4e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18054
54189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1805454189
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.2912214249
Short name T2196
Test name
Test status
Simulation time 211753056 ps
CPU time 0.92 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206672 kb
Host smart-6227e07f-5f8c-438d-ac1c-069f56a89fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29122
14249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.2912214249
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1661748716
Short name T2247
Test name
Test status
Simulation time 4664242196 ps
CPU time 123.25 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 07:00:30 PM PDT 24
Peak memory 206864 kb
Host smart-23460527-9ae4-454b-8d2a-84813fd0bb00
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1661748716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1661748716
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.4083009580
Short name T2164
Test name
Test status
Simulation time 168356761 ps
CPU time 0.77 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206512 kb
Host smart-d10217df-4470-4b0a-8f4e-f27930230e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40830
09580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.4083009580
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.4292233407
Short name T1855
Test name
Test status
Simulation time 159736474 ps
CPU time 0.78 seconds
Started Jul 21 06:58:24 PM PDT 24
Finished Jul 21 06:58:26 PM PDT 24
Peak memory 206696 kb
Host smart-c87e41ba-6676-459e-9173-62f77766ace6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42922
33407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.4292233407
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1256332334
Short name T1002
Test name
Test status
Simulation time 820766377 ps
CPU time 2.01 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206168 kb
Host smart-5a74f316-a0b8-4881-8a11-2a3b9cbdb622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12563
32334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1256332334
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.102014379
Short name T916
Test name
Test status
Simulation time 3713173921 ps
CPU time 32.98 seconds
Started Jul 21 06:58:27 PM PDT 24
Finished Jul 21 06:59:01 PM PDT 24
Peak memory 206900 kb
Host smart-3bafc81c-836c-46c8-b77b-311db6c9b9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10201
4379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.102014379
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.2738854435
Short name T634
Test name
Test status
Simulation time 79667094 ps
CPU time 0.75 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:30 PM PDT 24
Peak memory 206704 kb
Host smart-c10e2964-71b3-4ce9-862a-fb67260a62a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2738854435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.2738854435
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1275483822
Short name T183
Test name
Test status
Simulation time 3880832319 ps
CPU time 4.36 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 06:58:27 PM PDT 24
Peak memory 206748 kb
Host smart-f09cecea-74a4-44b1-8189-7d721791bad3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1275483822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1275483822
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.2332401996
Short name T1836
Test name
Test status
Simulation time 13415335899 ps
CPU time 12.49 seconds
Started Jul 21 06:58:18 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206816 kb
Host smart-0cea784c-2d35-4023-ae61-f59b4a418e47
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2332401996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.2332401996
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.1763399342
Short name T2216
Test name
Test status
Simulation time 23379794213 ps
CPU time 24.34 seconds
Started Jul 21 06:58:24 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206808 kb
Host smart-3f61a5ca-9f8f-45cf-8ad7-ed7cf2517980
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1763399342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.1763399342
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.2607333877
Short name T543
Test name
Test status
Simulation time 153501405 ps
CPU time 0.84 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206632 kb
Host smart-033668e1-10f8-470d-ba1d-f8b7d4158354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26073
33877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.2607333877
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.3593943334
Short name T2375
Test name
Test status
Simulation time 152333594 ps
CPU time 0.79 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:27 PM PDT 24
Peak memory 206632 kb
Host smart-1e4a31a4-a1c5-4dd5-af81-cb51c8db80e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35939
43334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.3593943334
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.2185307655
Short name T553
Test name
Test status
Simulation time 249857728 ps
CPU time 1.03 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:27 PM PDT 24
Peak memory 206688 kb
Host smart-473e355c-3903-4773-883d-94ce61908c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21853
07655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.2185307655
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3302265082
Short name T1043
Test name
Test status
Simulation time 997464020 ps
CPU time 2.35 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 06:58:30 PM PDT 24
Peak memory 206788 kb
Host smart-f50c00d0-a0b3-4331-96ca-a08e72200d75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33022
65082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3302265082
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.1133080502
Short name T1602
Test name
Test status
Simulation time 10082356457 ps
CPU time 20.96 seconds
Started Jul 21 06:58:28 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206896 kb
Host smart-0c0d880c-833c-485c-ba3c-2b0e530f9dca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11330
80502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.1133080502
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.260813359
Short name T815
Test name
Test status
Simulation time 436290293 ps
CPU time 1.31 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:27 PM PDT 24
Peak memory 206660 kb
Host smart-31dbbbcc-986c-4ec9-90ef-ea64dad74c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26081
3359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.260813359
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.4228297560
Short name T2384
Test name
Test status
Simulation time 149959274 ps
CPU time 0.81 seconds
Started Jul 21 06:58:21 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206696 kb
Host smart-75491ece-003a-4282-adfd-9d018b25ea40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42282
97560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.4228297560
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.450054483
Short name T1555
Test name
Test status
Simulation time 106459783 ps
CPU time 0.69 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:30 PM PDT 24
Peak memory 206684 kb
Host smart-761f7eef-ec19-40a6-91b7-e1bf6b8a0691
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45005
4483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.450054483
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.559817298
Short name T906
Test name
Test status
Simulation time 867150077 ps
CPU time 2.08 seconds
Started Jul 21 06:58:20 PM PDT 24
Finished Jul 21 06:58:23 PM PDT 24
Peak memory 206804 kb
Host smart-bab022a6-8e0d-4905-8794-b49a558af2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55981
7298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.559817298
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.1030597199
Short name T2005
Test name
Test status
Simulation time 251145708 ps
CPU time 1.92 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 06:58:29 PM PDT 24
Peak memory 206776 kb
Host smart-e916edd5-4e1b-4672-8604-176aea87ee53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10305
97199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.1030597199
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3304862258
Short name T2154
Test name
Test status
Simulation time 257372436 ps
CPU time 0.94 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206684 kb
Host smart-04f490eb-3b4f-4cf2-8163-85b21ece5a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33048
62258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3304862258
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2770276793
Short name T2009
Test name
Test status
Simulation time 194560585 ps
CPU time 0.78 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206672 kb
Host smart-d28460ac-489a-4d99-ac91-af180323a6c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27702
76793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2770276793
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.3531579839
Short name T2621
Test name
Test status
Simulation time 237135596 ps
CPU time 0.92 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206664 kb
Host smart-c57a0514-96f4-4f1d-bc32-2a1173596f80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35315
79839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.3531579839
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_invalid_sync.1913173277
Short name T1573
Test name
Test status
Simulation time 5306250088 ps
CPU time 38.59 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206980 kb
Host smart-3660fb24-b208-4c2f-abde-db48538326cd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1913173277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_invalid_sync.1913173277
Directory /workspace/33.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.2292735627
Short name T1877
Test name
Test status
Simulation time 13400726301 ps
CPU time 52.96 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206948 kb
Host smart-8c7fcfe3-8580-4412-a9e4-2dbb31bc6f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22927
35627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.2292735627
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.1351865676
Short name T1017
Test name
Test status
Simulation time 157233755 ps
CPU time 0.78 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206680 kb
Host smart-94f6beaf-46ba-4bca-b3fd-e67e8c6a8eb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13518
65676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.1351865676
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.2741021619
Short name T2744
Test name
Test status
Simulation time 23386905926 ps
CPU time 23.94 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:55 PM PDT 24
Peak memory 206784 kb
Host smart-bd3415f8-e604-433e-b1c7-3ab7a039999c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27410
21619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.2741021619
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.1129009043
Short name T2285
Test name
Test status
Simulation time 3324005464 ps
CPU time 4.5 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206764 kb
Host smart-681b3df5-f441-4197-b7f2-85e87ae9fa8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11290
09043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.1129009043
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.1749998502
Short name T2516
Test name
Test status
Simulation time 7675064303 ps
CPU time 72.14 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 06:59:39 PM PDT 24
Peak memory 206920 kb
Host smart-46725f56-bf6e-41da-b7f7-76c40298e918
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17499
98502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.1749998502
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.2856737965
Short name T2019
Test name
Test status
Simulation time 5924497451 ps
CPU time 145.76 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 206848 kb
Host smart-080b9896-9d95-4bc9-a06c-d695c5b8c8ed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2856737965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.2856737965
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.566965985
Short name T2496
Test name
Test status
Simulation time 253536213 ps
CPU time 0.94 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:30 PM PDT 24
Peak memory 206632 kb
Host smart-952b3a42-928c-413f-94c1-32c279bd9960
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=566965985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.566965985
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2400133841
Short name T2736
Test name
Test status
Simulation time 202534213 ps
CPU time 0.85 seconds
Started Jul 21 06:58:27 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206664 kb
Host smart-dd264742-8b28-412b-8b66-98d471eabcda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24001
33841 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2400133841
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.446141127
Short name T438
Test name
Test status
Simulation time 6381497736 ps
CPU time 45.3 seconds
Started Jul 21 06:58:28 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206912 kb
Host smart-254eddae-8ac8-43eb-85cf-4b9fa4ed80d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44614
1127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.446141127
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.225250432
Short name T1207
Test name
Test status
Simulation time 3364923188 ps
CPU time 24.5 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:48 PM PDT 24
Peak memory 206872 kb
Host smart-4a1fd1e6-c038-49d6-ab0a-3ef30a65c844
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=225250432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.225250432
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.2370822681
Short name T1678
Test name
Test status
Simulation time 153963871 ps
CPU time 0.79 seconds
Started Jul 21 06:58:27 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206700 kb
Host smart-e8aadf14-e443-4456-bff8-13e9948b8a73
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2370822681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.2370822681
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.2469276368
Short name T570
Test name
Test status
Simulation time 142578472 ps
CPU time 0.79 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206652 kb
Host smart-69b4a735-dc58-4730-9506-863547765401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24692
76368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.2469276368
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.4177163269
Short name T1868
Test name
Test status
Simulation time 209108509 ps
CPU time 0.9 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206660 kb
Host smart-237bf773-3eca-4eed-9f5a-7312179e1ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41771
63269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.4177163269
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.3748024852
Short name T2207
Test name
Test status
Simulation time 149264769 ps
CPU time 0.73 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206560 kb
Host smart-fa6f813a-5435-4047-b69d-e30bdac0df15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37480
24852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.3748024852
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.2017930480
Short name T1441
Test name
Test status
Simulation time 170832244 ps
CPU time 0.85 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206696 kb
Host smart-6c537332-0647-4e78-bdb7-23357dad1351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20179
30480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.2017930480
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.764029131
Short name T1740
Test name
Test status
Simulation time 190776608 ps
CPU time 0.78 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206684 kb
Host smart-ffabbcbf-debc-416d-bb72-52827b416a67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76402
9131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.764029131
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.3378284136
Short name T169
Test name
Test status
Simulation time 154192843 ps
CPU time 0.76 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:27 PM PDT 24
Peak memory 206700 kb
Host smart-f14c5fb0-6f23-4ab5-9a82-13ef7985c5c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33782
84136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.3378284136
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2147522229
Short name T1320
Test name
Test status
Simulation time 219020183 ps
CPU time 0.89 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206652 kb
Host smart-1bfdd281-34a5-4d88-bc1d-79a53017f626
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2147522229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2147522229
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3021665721
Short name T2578
Test name
Test status
Simulation time 173404342 ps
CPU time 0.95 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:24 PM PDT 24
Peak memory 206704 kb
Host smart-96d42b8c-1ae9-4380-8652-4ec64eab81f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
65721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3021665721
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.647114415
Short name T2725
Test name
Test status
Simulation time 38256521 ps
CPU time 0.66 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206664 kb
Host smart-46446f3b-d31f-48cd-8aa4-6a8b9a484081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64711
4415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.647114415
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.4172447030
Short name T1973
Test name
Test status
Simulation time 8830056585 ps
CPU time 20.17 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:43 PM PDT 24
Peak memory 206884 kb
Host smart-3f08deb2-cbde-4082-a9d4-266c3ab2b158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41724
47030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.4172447030
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1822861184
Short name T2306
Test name
Test status
Simulation time 167349564 ps
CPU time 0.83 seconds
Started Jul 21 06:58:27 PM PDT 24
Finished Jul 21 06:58:29 PM PDT 24
Peak memory 206668 kb
Host smart-8f26f3c2-4303-4fc7-baa3-95506b04ebf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18228
61184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1822861184
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.3303762694
Short name T762
Test name
Test status
Simulation time 186633220 ps
CPU time 0.83 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206664 kb
Host smart-2b5eb8a7-4428-43b1-bff5-792fb153a15a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33037
62694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.3303762694
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.3641447036
Short name T1712
Test name
Test status
Simulation time 161484236 ps
CPU time 0.82 seconds
Started Jul 21 06:58:23 PM PDT 24
Finished Jul 21 06:58:25 PM PDT 24
Peak memory 206656 kb
Host smart-4cd3eb32-dd7d-44b3-926f-f2cf7a01c4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36414
47036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.3641447036
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.1059460946
Short name T2485
Test name
Test status
Simulation time 141559065 ps
CPU time 0.77 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206632 kb
Host smart-46ce22e0-1bab-454c-9557-3763597e4d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10594
60946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.1059460946
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.2847788507
Short name T924
Test name
Test status
Simulation time 223824202 ps
CPU time 0.83 seconds
Started Jul 21 06:58:28 PM PDT 24
Finished Jul 21 06:58:30 PM PDT 24
Peak memory 206668 kb
Host smart-ba7063ff-4943-4892-b43c-484c16e70662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28477
88507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.2847788507
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3314150051
Short name T1971
Test name
Test status
Simulation time 164602631 ps
CPU time 0.8 seconds
Started Jul 21 06:58:26 PM PDT 24
Finished Jul 21 06:58:28 PM PDT 24
Peak memory 206648 kb
Host smart-4b6f5ecf-cabe-4bb6-8142-3ba0fa6013e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33141
50051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3314150051
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.1900648429
Short name T1270
Test name
Test status
Simulation time 169962752 ps
CPU time 0.82 seconds
Started Jul 21 06:58:25 PM PDT 24
Finished Jul 21 06:58:27 PM PDT 24
Peak memory 206680 kb
Host smart-9326c0ca-4ebc-4311-b397-6cb21496f0c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19006
48429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.1900648429
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.2435746582
Short name T436
Test name
Test status
Simulation time 215873609 ps
CPU time 0.95 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:36 PM PDT 24
Peak memory 206652 kb
Host smart-4a74e87f-e883-41e1-8ec7-a93f2a3b0592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24357
46582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.2435746582
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.3070469869
Short name T2719
Test name
Test status
Simulation time 4997007363 ps
CPU time 38.07 seconds
Started Jul 21 06:58:32 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206988 kb
Host smart-30956f03-2be7-4dcc-b75a-66c69628661f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3070469869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.3070469869
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.1084362990
Short name T2600
Test name
Test status
Simulation time 161186600 ps
CPU time 0.85 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:38 PM PDT 24
Peak memory 206700 kb
Host smart-73b28c9b-2790-4d10-ac2b-3c392b4e8c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10843
62990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.1084362990
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.2226876238
Short name T822
Test name
Test status
Simulation time 169225932 ps
CPU time 0.8 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:33 PM PDT 24
Peak memory 206652 kb
Host smart-e7e20c6a-7db2-4106-826e-4155f4c2d850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22268
76238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.2226876238
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.2824418557
Short name T2657
Test name
Test status
Simulation time 702226638 ps
CPU time 1.92 seconds
Started Jul 21 06:58:36 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206800 kb
Host smart-c32fb213-8108-40f5-91fd-61f2811dff67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244
18557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.2824418557
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.3881054606
Short name T389
Test name
Test status
Simulation time 4656272534 ps
CPU time 45.83 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:59:15 PM PDT 24
Peak memory 206940 kb
Host smart-5220f9c2-dd3c-47bb-a6c2-4f03a01d5836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38810
54606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.3881054606
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.3955656597
Short name T1818
Test name
Test status
Simulation time 52382778 ps
CPU time 0.69 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:37 PM PDT 24
Peak memory 206680 kb
Host smart-5ea56b9b-d694-46e8-905a-c62e732be3b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3955656597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.3955656597
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.3473876478
Short name T1431
Test name
Test status
Simulation time 3613477503 ps
CPU time 4.62 seconds
Started Jul 21 06:58:28 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206884 kb
Host smart-d43d7afc-f202-4983-97d1-eac96f01c0b4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3473876478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.3473876478
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.719595970
Short name T1243
Test name
Test status
Simulation time 13317876548 ps
CPU time 11.64 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:43 PM PDT 24
Peak memory 206856 kb
Host smart-7ba77b1f-7045-466e-bd7f-6a0890009b59
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=719595970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.719595970
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.1098175461
Short name T1129
Test name
Test status
Simulation time 23464019262 ps
CPU time 26.18 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:59:03 PM PDT 24
Peak memory 206956 kb
Host smart-59865891-e1ef-4c40-9698-8114fcd91e77
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1098175461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.1098175461
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.870141954
Short name T2352
Test name
Test status
Simulation time 184681565 ps
CPU time 0.83 seconds
Started Jul 21 06:58:32 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206608 kb
Host smart-2896d2cc-f268-4bba-9c86-613f15d4dffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87014
1954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.870141954
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.403080532
Short name T479
Test name
Test status
Simulation time 144963733 ps
CPU time 0.72 seconds
Started Jul 21 06:58:45 PM PDT 24
Finished Jul 21 06:58:46 PM PDT 24
Peak memory 206696 kb
Host smart-c96477b3-9f2b-4dee-bb2c-f7af9fdea557
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40308
0532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.403080532
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2924085715
Short name T1517
Test name
Test status
Simulation time 517501280 ps
CPU time 1.52 seconds
Started Jul 21 06:58:32 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206828 kb
Host smart-66f806f0-79d9-42db-9dfc-10c7ba796f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29240
85715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2924085715
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.3402582598
Short name T1895
Test name
Test status
Simulation time 709703973 ps
CPU time 1.67 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206816 kb
Host smart-184d0377-e4d0-4cf6-b3e9-6125392fb7d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34025
82598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.3402582598
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.114051919
Short name T1529
Test name
Test status
Simulation time 14905285979 ps
CPU time 30.76 seconds
Started Jul 21 06:58:36 PM PDT 24
Finished Jul 21 06:59:08 PM PDT 24
Peak memory 206920 kb
Host smart-c3610ba7-d491-421f-8c45-7ce202a4df40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11405
1919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.114051919
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.456588858
Short name T1962
Test name
Test status
Simulation time 476112562 ps
CPU time 1.36 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:38 PM PDT 24
Peak memory 206692 kb
Host smart-52cf3120-32ef-4fa2-9e50-fdf9cf9dea45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45658
8858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.456588858
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.1243491082
Short name T2442
Test name
Test status
Simulation time 187108632 ps
CPU time 0.84 seconds
Started Jul 21 06:58:32 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206664 kb
Host smart-b88046ed-77b5-470c-932b-14a9b4dc133b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
91082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.1243491082
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.445207183
Short name T1032
Test name
Test status
Simulation time 33542516 ps
CPU time 0.67 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206652 kb
Host smart-9083f18b-43a3-41a0-967a-09f3d3d10ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44520
7183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.445207183
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.761970490
Short name T2389
Test name
Test status
Simulation time 938407131 ps
CPU time 2.2 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206840 kb
Host smart-5520130e-de49-44b8-9ef2-baa597419a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76197
0490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.761970490
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.1398153361
Short name T669
Test name
Test status
Simulation time 151361930 ps
CPU time 1.13 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:38 PM PDT 24
Peak memory 206768 kb
Host smart-aa10b3f2-30bc-4d53-8f77-dee33e5039ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13981
53361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.1398153361
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2704383266
Short name T2679
Test name
Test status
Simulation time 244694818 ps
CPU time 0.95 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:31 PM PDT 24
Peak memory 206676 kb
Host smart-8b6e83f4-6fc2-4d72-bc05-553762c8e076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27043
83266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2704383266
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.4055234653
Short name T1156
Test name
Test status
Simulation time 151456947 ps
CPU time 0.76 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206648 kb
Host smart-42282161-3c42-49a6-b289-8625551c6784
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40552
34653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.4055234653
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.1310882421
Short name T1031
Test name
Test status
Simulation time 234490610 ps
CPU time 0.94 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206684 kb
Host smart-dd34f314-3ba8-485a-b3bf-b9912b026092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13108
82421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.1310882421
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.53981536
Short name T859
Test name
Test status
Simulation time 7676574746 ps
CPU time 214.19 seconds
Started Jul 21 06:58:36 PM PDT 24
Finished Jul 21 07:02:11 PM PDT 24
Peak memory 206924 kb
Host smart-2a34af38-4ccb-4aee-934f-a8f4da9e7055
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=53981536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.53981536
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.3639221050
Short name T1667
Test name
Test status
Simulation time 249729640 ps
CPU time 0.94 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:33 PM PDT 24
Peak memory 206604 kb
Host smart-c2e1f924-2a31-456b-8954-21793f6522ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36392
21050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.3639221050
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.4153242461
Short name T1815
Test name
Test status
Simulation time 23334065341 ps
CPU time 24.45 seconds
Started Jul 21 06:58:33 PM PDT 24
Finished Jul 21 06:59:04 PM PDT 24
Peak memory 206804 kb
Host smart-dd5d2cc0-0d7c-4cb2-8717-1f7f21357fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41532
42461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.4153242461
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3188637448
Short name T1832
Test name
Test status
Simulation time 3343447353 ps
CPU time 3.82 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206736 kb
Host smart-318c717a-2437-44b3-937c-6292ffab4e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31886
37448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3188637448
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.4168300553
Short name T1054
Test name
Test status
Simulation time 12855475730 ps
CPU time 87.47 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206924 kb
Host smart-b8192461-d016-47e6-a2ea-4f7920561b29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41683
00553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.4168300553
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.1899721912
Short name T2561
Test name
Test status
Simulation time 5074016576 ps
CPU time 46.02 seconds
Started Jul 21 06:58:33 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206992 kb
Host smart-3be6b7fc-3cab-418f-91e0-53aef09ad4ec
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1899721912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.1899721912
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.3759037435
Short name T1624
Test name
Test status
Simulation time 261822589 ps
CPU time 0.99 seconds
Started Jul 21 06:58:36 PM PDT 24
Finished Jul 21 06:58:38 PM PDT 24
Peak memory 206692 kb
Host smart-1deedc45-8371-4501-8787-86d4f319dc87
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3759037435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.3759037435
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.3628426190
Short name T854
Test name
Test status
Simulation time 183167206 ps
CPU time 0.86 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:37 PM PDT 24
Peak memory 206668 kb
Host smart-6b46fc94-b8c3-470a-9aa1-5c0d8a189356
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36284
26190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.3628426190
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.2611801859
Short name T1399
Test name
Test status
Simulation time 4917001112 ps
CPU time 35.78 seconds
Started Jul 21 06:58:32 PM PDT 24
Finished Jul 21 06:59:09 PM PDT 24
Peak memory 206996 kb
Host smart-e2f3b5b2-aeb6-4aea-b76c-6f046cc60a48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26118
01859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.2611801859
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.3331188380
Short name T783
Test name
Test status
Simulation time 3575198759 ps
CPU time 23.6 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:59:02 PM PDT 24
Peak memory 206876 kb
Host smart-a5dec396-522d-41ef-852c-c47fda9a150c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3331188380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.3331188380
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.1940953989
Short name T1574
Test name
Test status
Simulation time 156790460 ps
CPU time 0.77 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:33 PM PDT 24
Peak memory 206664 kb
Host smart-4d555c3b-2360-4d3c-8717-6b81c1ea6a49
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1940953989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.1940953989
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.545338608
Short name T2342
Test name
Test status
Simulation time 193369982 ps
CPU time 0.81 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206680 kb
Host smart-e419ea2d-6950-40b8-a17f-87e385e35e13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54533
8608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.545338608
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.1237798180
Short name T2696
Test name
Test status
Simulation time 181311149 ps
CPU time 0.86 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206680 kb
Host smart-2b319d11-d718-41d8-ba40-38454366d03e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12377
98180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.1237798180
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.3736727606
Short name T1717
Test name
Test status
Simulation time 221817189 ps
CPU time 0.89 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:33 PM PDT 24
Peak memory 206664 kb
Host smart-7c01803f-bce8-4e4d-84b8-dd29a72ff6ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37367
27606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.3736727606
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.1938958924
Short name T1841
Test name
Test status
Simulation time 163688230 ps
CPU time 0.81 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206660 kb
Host smart-aa3df022-f27e-4ca4-9364-2341757dce17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19389
58924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.1938958924
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.279264892
Short name T2457
Test name
Test status
Simulation time 152984313 ps
CPU time 0.78 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:33 PM PDT 24
Peak memory 206648 kb
Host smart-52765746-6dfa-4f71-8d27-0a9f7f19b216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27926
4892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.279264892
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.122886248
Short name T1388
Test name
Test status
Simulation time 160960365 ps
CPU time 0.81 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206680 kb
Host smart-464fe2ee-f01e-4fff-94ce-616876b4dd59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12288
6248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.122886248
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2527664821
Short name T2321
Test name
Test status
Simulation time 221122014 ps
CPU time 0.97 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206684 kb
Host smart-d1073cc4-7a92-49a9-9398-c2bc4e54cb4c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2527664821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2527664821
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.2340940525
Short name T498
Test name
Test status
Simulation time 148993058 ps
CPU time 0.76 seconds
Started Jul 21 06:58:33 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206660 kb
Host smart-b6a7730d-f550-4212-8c06-e9212b8786b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23409
40525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.2340940525
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.3427276150
Short name T550
Test name
Test status
Simulation time 36314918 ps
CPU time 0.67 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:35 PM PDT 24
Peak memory 206632 kb
Host smart-1f17b2c0-a661-4c5d-96f3-d212c195380b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34272
76150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.3427276150
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.1713075735
Short name T2735
Test name
Test status
Simulation time 7484480786 ps
CPU time 17.28 seconds
Started Jul 21 06:58:29 PM PDT 24
Finished Jul 21 06:58:48 PM PDT 24
Peak memory 215136 kb
Host smart-76fd591e-34a1-4b82-874f-72d692e88ada
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17130
75735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.1713075735
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.3487259814
Short name T746
Test name
Test status
Simulation time 217530979 ps
CPU time 0.86 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:36 PM PDT 24
Peak memory 206656 kb
Host smart-a52c6c04-50e2-445c-972f-16182c923d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34872
59814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.3487259814
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.3348512208
Short name T1799
Test name
Test status
Simulation time 213385736 ps
CPU time 0.89 seconds
Started Jul 21 06:58:31 PM PDT 24
Finished Jul 21 06:58:33 PM PDT 24
Peak memory 206644 kb
Host smart-23b38705-5990-433f-b888-65d5d1756d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33485
12208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.3348512208
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.1807677562
Short name T1438
Test name
Test status
Simulation time 203990368 ps
CPU time 0.88 seconds
Started Jul 21 06:58:30 PM PDT 24
Finished Jul 21 06:58:32 PM PDT 24
Peak memory 206648 kb
Host smart-04b5aeeb-952c-4a21-9030-10d420eb9a6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18076
77562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.1807677562
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.2292305357
Short name T357
Test name
Test status
Simulation time 170357964 ps
CPU time 0.82 seconds
Started Jul 21 06:58:32 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206660 kb
Host smart-3041ad7e-14a1-4684-aef8-458e8469fb1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22923
05357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.2292305357
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3267021084
Short name T510
Test name
Test status
Simulation time 214182944 ps
CPU time 0.79 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:36 PM PDT 24
Peak memory 206680 kb
Host smart-ca6dbc3d-13ee-4b4f-ab64-5c5b995463a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32670
21084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3267021084
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3766005545
Short name T2627
Test name
Test status
Simulation time 154937467 ps
CPU time 0.76 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:37 PM PDT 24
Peak memory 206628 kb
Host smart-2cc0b6d3-5544-4571-96b8-87626c577075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37660
05545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3766005545
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.324669351
Short name T521
Test name
Test status
Simulation time 179348747 ps
CPU time 0.79 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206684 kb
Host smart-69b1aa56-1824-4dd2-a314-33be76a59be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32466
9351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.324669351
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.2454633179
Short name T1503
Test name
Test status
Simulation time 245278253 ps
CPU time 1.04 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:37 PM PDT 24
Peak memory 206660 kb
Host smart-c56c7ecb-1100-4475-87a0-d88d3bbbeb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24546
33179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.2454633179
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.3199026439
Short name T1795
Test name
Test status
Simulation time 4734827351 ps
CPU time 31.39 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:59:08 PM PDT 24
Peak memory 206916 kb
Host smart-853ebf74-a370-49d1-9fe2-b5a7a6df2a98
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3199026439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.3199026439
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.1278162320
Short name T1256
Test name
Test status
Simulation time 194171919 ps
CPU time 0.84 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206636 kb
Host smart-c1c9b4bd-d582-443c-9bec-abca21368e18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12781
62320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.1278162320
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.1036229694
Short name T1829
Test name
Test status
Simulation time 169643944 ps
CPU time 0.82 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:36 PM PDT 24
Peak memory 206664 kb
Host smart-12e55c22-038f-48ab-8a7b-521b92619e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10362
29694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.1036229694
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.3749937886
Short name T2045
Test name
Test status
Simulation time 1236265908 ps
CPU time 2.66 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206772 kb
Host smart-f08b0b16-fa0b-44bd-96fa-6c29cf7631b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37499
37886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3749937886
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2366592315
Short name T1941
Test name
Test status
Simulation time 6760279409 ps
CPU time 62.64 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:59:39 PM PDT 24
Peak memory 206956 kb
Host smart-f369924a-c28c-492c-9dde-fd2ed6b6585d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23665
92315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2366592315
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.3966164694
Short name T1188
Test name
Test status
Simulation time 47448484 ps
CPU time 0.67 seconds
Started Jul 21 06:58:53 PM PDT 24
Finished Jul 21 06:58:54 PM PDT 24
Peak memory 206704 kb
Host smart-3651d1ec-0b56-49be-8dff-b01cbf85e494
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3966164694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.3966164694
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.379511507
Short name T15
Test name
Test status
Simulation time 3952888170 ps
CPU time 4.72 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206864 kb
Host smart-2e38b7c9-56c9-472c-a3d9-d2acedefe359
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=379511507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.379511507
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.57593309
Short name T1681
Test name
Test status
Simulation time 13338414364 ps
CPU time 13.58 seconds
Started Jul 21 06:58:41 PM PDT 24
Finished Jul 21 06:58:55 PM PDT 24
Peak memory 206872 kb
Host smart-337b728e-e15c-4da3-8e86-9be60abe4274
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=57593309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.57593309
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3717995440
Short name T1558
Test name
Test status
Simulation time 23337939335 ps
CPU time 23.01 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:59 PM PDT 24
Peak memory 206796 kb
Host smart-1f89bf5f-71c4-46d2-8c4a-813ccf53de5b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3717995440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3717995440
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2752948310
Short name T1481
Test name
Test status
Simulation time 145169304 ps
CPU time 0.75 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206672 kb
Host smart-7f9ae2dd-5385-413e-a494-5fce337bac66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27529
48310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2752948310
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.2605151000
Short name T2755
Test name
Test status
Simulation time 190273055 ps
CPU time 0.85 seconds
Started Jul 21 06:58:41 PM PDT 24
Finished Jul 21 06:58:43 PM PDT 24
Peak memory 206684 kb
Host smart-44b0dec2-0762-4235-8d3a-9b4e122bfa04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26051
51000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.2605151000
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2203322253
Short name T2447
Test name
Test status
Simulation time 501959116 ps
CPU time 1.52 seconds
Started Jul 21 06:58:38 PM PDT 24
Finished Jul 21 06:58:41 PM PDT 24
Peak memory 206756 kb
Host smart-aebfb672-351f-4b91-9a61-894e2d6b7cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22033
22253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2203322253
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.231745356
Short name T1889
Test name
Test status
Simulation time 1427229657 ps
CPU time 3.37 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:38 PM PDT 24
Peak memory 206780 kb
Host smart-63f0e101-c979-4726-a9c4-4e9c71e0540d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23174
5356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.231745356
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1722417457
Short name T1114
Test name
Test status
Simulation time 13601964213 ps
CPU time 25.46 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:59:01 PM PDT 24
Peak memory 206880 kb
Host smart-405008f5-e9cf-471a-86ac-329ad7f9dd87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17224
17457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1722417457
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1251716900
Short name T1011
Test name
Test status
Simulation time 367232310 ps
CPU time 1.16 seconds
Started Jul 21 06:58:36 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206604 kb
Host smart-2dbd890a-f239-4edc-8df3-5df19e6e3a8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12517
16900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1251716900
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.640033902
Short name T947
Test name
Test status
Simulation time 151981691 ps
CPU time 0.75 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:36 PM PDT 24
Peak memory 206692 kb
Host smart-0c56036d-b84a-4c1b-ba10-4fcd3c00c65f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64003
3902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.640033902
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.373662405
Short name T1279
Test name
Test status
Simulation time 43086260 ps
CPU time 0.65 seconds
Started Jul 21 06:58:34 PM PDT 24
Finished Jul 21 06:58:36 PM PDT 24
Peak memory 206668 kb
Host smart-674f0309-baf6-4512-bb50-fe1c5d708337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37366
2405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.373662405
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.2383833799
Short name T442
Test name
Test status
Simulation time 812983940 ps
CPU time 2.06 seconds
Started Jul 21 06:58:40 PM PDT 24
Finished Jul 21 06:58:43 PM PDT 24
Peak memory 206792 kb
Host smart-2340d1e4-81e4-433a-abc5-b852f8c95f40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23838
33799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.2383833799
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.447728935
Short name T1298
Test name
Test status
Simulation time 283262080 ps
CPU time 2.03 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206796 kb
Host smart-534647fd-9a8b-42e1-ab1f-ee102b8e69c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44772
8935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.447728935
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.1925510565
Short name T1484
Test name
Test status
Simulation time 221311124 ps
CPU time 0.87 seconds
Started Jul 21 06:58:55 PM PDT 24
Finished Jul 21 06:58:57 PM PDT 24
Peak memory 206664 kb
Host smart-fe3ffdd9-caf9-4a47-b270-be7afebbe394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19255
10565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.1925510565
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.200491776
Short name T1342
Test name
Test status
Simulation time 193191818 ps
CPU time 0.8 seconds
Started Jul 21 06:58:32 PM PDT 24
Finished Jul 21 06:58:34 PM PDT 24
Peak memory 206660 kb
Host smart-e4becf58-a07e-48aa-bb52-6af1c5a3c614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20049
1776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.200491776
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2799576376
Short name T2339
Test name
Test status
Simulation time 224257819 ps
CPU time 0.97 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206684 kb
Host smart-57596c42-094f-455f-98d9-3034f823c88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27995
76376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2799576376
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.3176978996
Short name T2199
Test name
Test status
Simulation time 10126404898 ps
CPU time 31.2 seconds
Started Jul 21 06:58:38 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206964 kb
Host smart-4ed7b9a8-5089-4227-8916-7e92febc6413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31769
78996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.3176978996
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.2121328322
Short name T804
Test name
Test status
Simulation time 221159584 ps
CPU time 0.88 seconds
Started Jul 21 06:58:37 PM PDT 24
Finished Jul 21 06:58:39 PM PDT 24
Peak memory 206660 kb
Host smart-714bac62-e17e-4306-95f8-de6b4eb10276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21213
28322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.2121328322
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.202537297
Short name T809
Test name
Test status
Simulation time 23321479120 ps
CPU time 24.67 seconds
Started Jul 21 06:58:38 PM PDT 24
Finished Jul 21 06:59:04 PM PDT 24
Peak memory 206820 kb
Host smart-721a7654-ab14-40c2-ad37-a4993c0ce4ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20253
7297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.202537297
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2594412784
Short name T562
Test name
Test status
Simulation time 3259723373 ps
CPU time 4.12 seconds
Started Jul 21 06:58:45 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206736 kb
Host smart-ac80ebc1-2a60-49d0-b4b2-e9319fa1bd76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25944
12784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2594412784
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.2336202149
Short name T1106
Test name
Test status
Simulation time 7543514456 ps
CPU time 194.76 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 206968 kb
Host smart-a3f8efd0-5aa6-4b2b-b63a-cdc5adea131d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
02149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.2336202149
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3768992689
Short name T314
Test name
Test status
Simulation time 4430334429 ps
CPU time 30.89 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:59:08 PM PDT 24
Peak memory 206956 kb
Host smart-38d51779-27e8-4c12-b2d5-dfcb6ff3c72e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3768992689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3768992689
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.2158542339
Short name T2398
Test name
Test status
Simulation time 232111483 ps
CPU time 0.88 seconds
Started Jul 21 06:58:36 PM PDT 24
Finished Jul 21 06:58:38 PM PDT 24
Peak memory 206556 kb
Host smart-c3516cc0-939e-4961-b934-bb9ddfbcfb83
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2158542339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.2158542339
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.1707117075
Short name T208
Test name
Test status
Simulation time 261581194 ps
CPU time 0.87 seconds
Started Jul 21 06:58:35 PM PDT 24
Finished Jul 21 06:58:37 PM PDT 24
Peak memory 206660 kb
Host smart-cfa751ec-3035-403f-a726-aceb16cd44de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17071
17075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.1707117075
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2909000952
Short name T356
Test name
Test status
Simulation time 5566656140 ps
CPU time 39.55 seconds
Started Jul 21 06:58:42 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206908 kb
Host smart-e596efac-f8af-4b59-addc-0d8613d36eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29090
00952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2909000952
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.2137747799
Short name T155
Test name
Test status
Simulation time 6363962331 ps
CPU time 173.64 seconds
Started Jul 21 06:58:47 PM PDT 24
Finished Jul 21 07:01:41 PM PDT 24
Peak memory 206860 kb
Host smart-248195d2-e39d-489a-a6c9-2bf2d6852545
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2137747799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.2137747799
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.3977740382
Short name T353
Test name
Test status
Simulation time 157659360 ps
CPU time 0.83 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206628 kb
Host smart-566631aa-048a-4c14-9a5d-5db05f26f2e0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3977740382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.3977740382
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.380141137
Short name T1945
Test name
Test status
Simulation time 193380087 ps
CPU time 0.84 seconds
Started Jul 21 06:58:44 PM PDT 24
Finished Jul 21 06:58:45 PM PDT 24
Peak memory 206668 kb
Host smart-f5166546-3fe5-41fd-90c3-22d30a3cb4e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38014
1137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.380141137
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.3551174910
Short name T132
Test name
Test status
Simulation time 226595837 ps
CPU time 0.99 seconds
Started Jul 21 06:58:39 PM PDT 24
Finished Jul 21 06:58:41 PM PDT 24
Peak memory 206656 kb
Host smart-0d9240ea-a7f6-489a-be6b-ce91b89ef8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35511
74910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.3551174910
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.1825086195
Short name T2192
Test name
Test status
Simulation time 178870403 ps
CPU time 0.83 seconds
Started Jul 21 06:58:55 PM PDT 24
Finished Jul 21 06:58:56 PM PDT 24
Peak memory 206688 kb
Host smart-b255167c-5e02-4701-913c-d62979e7150b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18250
86195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.1825086195
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.2416457070
Short name T1148
Test name
Test status
Simulation time 246215400 ps
CPU time 0.91 seconds
Started Jul 21 06:58:38 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206680 kb
Host smart-ede327d5-a887-427b-92a3-9bda91bdef53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24164
57070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.2416457070
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3299472289
Short name T2184
Test name
Test status
Simulation time 171692350 ps
CPU time 0.84 seconds
Started Jul 21 06:58:45 PM PDT 24
Finished Jul 21 06:58:46 PM PDT 24
Peak memory 206648 kb
Host smart-8a1294e4-04ab-4f9f-9a12-f1814c84312e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32994
72289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3299472289
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3361080360
Short name T2595
Test name
Test status
Simulation time 190778803 ps
CPU time 0.87 seconds
Started Jul 21 06:58:58 PM PDT 24
Finished Jul 21 06:58:59 PM PDT 24
Peak memory 206660 kb
Host smart-27fab58f-1311-4a28-8365-0f8ef8519d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33610
80360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3361080360
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.2183686049
Short name T2708
Test name
Test status
Simulation time 198710356 ps
CPU time 0.91 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:08 PM PDT 24
Peak memory 206632 kb
Host smart-4dc7641d-a0f8-44de-adb2-c4ffc8fc8903
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2183686049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.2183686049
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.1685271881
Short name T1588
Test name
Test status
Simulation time 160014066 ps
CPU time 0.78 seconds
Started Jul 21 06:58:51 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206696 kb
Host smart-094be84f-015f-48b5-b0f8-3f6bbc6c76f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16852
71881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.1685271881
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2196971825
Short name T2557
Test name
Test status
Simulation time 38385039 ps
CPU time 0.66 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206636 kb
Host smart-2df82b15-3cc2-421b-bd19-a0f24d094f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21969
71825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2196971825
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1446019721
Short name T2378
Test name
Test status
Simulation time 9761785764 ps
CPU time 22.4 seconds
Started Jul 21 06:58:43 PM PDT 24
Finished Jul 21 06:59:06 PM PDT 24
Peak memory 206916 kb
Host smart-07141e0f-bd37-4c19-9edd-f03010a181a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14460
19721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1446019721
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.2654645437
Short name T2589
Test name
Test status
Simulation time 164368484 ps
CPU time 0.82 seconds
Started Jul 21 06:58:38 PM PDT 24
Finished Jul 21 06:58:40 PM PDT 24
Peak memory 206680 kb
Host smart-ffb9bf89-5170-4fa6-8756-566ca9e4a4c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26546
45437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.2654645437
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1742516950
Short name T2747
Test name
Test status
Simulation time 299298253 ps
CPU time 0.98 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206660 kb
Host smart-263e0d0f-547d-4adf-ad1a-b0a18991be4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17425
16950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1742516950
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.697886297
Short name T1952
Test name
Test status
Simulation time 197898359 ps
CPU time 0.83 seconds
Started Jul 21 06:58:44 PM PDT 24
Finished Jul 21 06:58:45 PM PDT 24
Peak memory 206672 kb
Host smart-1279e302-1378-49b9-a537-f191ebb76c98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69788
6297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.697886297
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.600696914
Short name T1611
Test name
Test status
Simulation time 143785136 ps
CPU time 0.79 seconds
Started Jul 21 06:58:51 PM PDT 24
Finished Jul 21 06:58:52 PM PDT 24
Peak memory 206648 kb
Host smart-fd0e78f8-2e44-4d4f-af15-a98f7b76e53c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60069
6914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.600696914
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.2259328978
Short name T1134
Test name
Test status
Simulation time 194029922 ps
CPU time 0.81 seconds
Started Jul 21 06:58:55 PM PDT 24
Finished Jul 21 06:58:56 PM PDT 24
Peak memory 206676 kb
Host smart-2534e05b-e51e-43f3-9184-d7b82b11f1d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593
28978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.2259328978
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.1039531344
Short name T145
Test name
Test status
Simulation time 149771145 ps
CPU time 0.82 seconds
Started Jul 21 06:58:48 PM PDT 24
Finished Jul 21 06:58:49 PM PDT 24
Peak memory 206688 kb
Host smart-fd1f1a58-5619-4029-848c-1665258c3579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10395
31344 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.1039531344
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.3163793045
Short name T952
Test name
Test status
Simulation time 149119514 ps
CPU time 0.82 seconds
Started Jul 21 06:58:52 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206656 kb
Host smart-c7e07220-75ab-4b44-b222-199e5fad2f6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31637
93045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.3163793045
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.2613624620
Short name T1688
Test name
Test status
Simulation time 220787324 ps
CPU time 1.01 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206592 kb
Host smart-c6f10771-b3ce-42bd-bea3-a8864bdb762b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136
24620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.2613624620
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.221462603
Short name T2289
Test name
Test status
Simulation time 5228123557 ps
CPU time 35.3 seconds
Started Jul 21 06:58:59 PM PDT 24
Finished Jul 21 06:59:34 PM PDT 24
Peak memory 206896 kb
Host smart-43a84ad6-f3ac-44b8-89a1-dbb526ab0928
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=221462603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.221462603
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1671249242
Short name T2748
Test name
Test status
Simulation time 169980702 ps
CPU time 0.82 seconds
Started Jul 21 06:58:51 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206636 kb
Host smart-f0b594fa-c4ca-4f23-ae0f-f73e3207d3bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16712
49242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1671249242
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.981851595
Short name T1194
Test name
Test status
Simulation time 200536549 ps
CPU time 0.89 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206788 kb
Host smart-39d2dfb7-a63f-4eca-8961-bc8214628a42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98185
1595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.981851595
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.1125215445
Short name T1382
Test name
Test status
Simulation time 748741404 ps
CPU time 1.72 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206780 kb
Host smart-4a79b44d-a469-4a1c-a531-9ac9575ede81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11252
15445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.1125215445
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.2847110923
Short name T760
Test name
Test status
Simulation time 6837822219 ps
CPU time 63.95 seconds
Started Jul 21 06:58:46 PM PDT 24
Finished Jul 21 06:59:50 PM PDT 24
Peak memory 206868 kb
Host smart-9bf9b878-eb5e-4825-a35b-f9200ceb8ed8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28471
10923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.2847110923
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.2514830704
Short name T2494
Test name
Test status
Simulation time 93379840 ps
CPU time 0.73 seconds
Started Jul 21 06:59:08 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206712 kb
Host smart-c6afd2ac-e81b-43ac-a30a-3252157de451
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2514830704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.2514830704
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.582116995
Short name T1074
Test name
Test status
Simulation time 4300798548 ps
CPU time 5.93 seconds
Started Jul 21 06:58:59 PM PDT 24
Finished Jul 21 06:59:06 PM PDT 24
Peak memory 206760 kb
Host smart-ec54e1cd-23ee-4cf2-ab7c-e32b78bffa66
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=582116995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.582116995
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.1758305829
Short name T195
Test name
Test status
Simulation time 13301780776 ps
CPU time 11.76 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206960 kb
Host smart-1fe0e9a2-e100-473b-bd36-ce7efbad8ecf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1758305829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.1758305829
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.1243345418
Short name T885
Test name
Test status
Simulation time 23350221355 ps
CPU time 26.5 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:28 PM PDT 24
Peak memory 206792 kb
Host smart-d2524b5a-44fe-4089-bd9b-df0318cabea6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1243345418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.1243345418
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.271302986
Short name T1927
Test name
Test status
Simulation time 160036447 ps
CPU time 0.85 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:03 PM PDT 24
Peak memory 206740 kb
Host smart-14786c81-024b-4732-bf29-f68d5748e42c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27130
2986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.271302986
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.964150586
Short name T2039
Test name
Test status
Simulation time 228469751 ps
CPU time 0.86 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206664 kb
Host smart-8f58d28e-2a29-416d-8485-e0bb49ac97dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96415
0586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.964150586
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.841902560
Short name T1685
Test name
Test status
Simulation time 450783707 ps
CPU time 1.4 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:08 PM PDT 24
Peak memory 206660 kb
Host smart-c5b62758-b188-4168-9c4e-37d1497e93b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84190
2560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.841902560
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1029284036
Short name T2290
Test name
Test status
Simulation time 344963350 ps
CPU time 1 seconds
Started Jul 21 06:59:03 PM PDT 24
Finished Jul 21 06:59:06 PM PDT 24
Peak memory 206628 kb
Host smart-7633e70e-7d31-491f-9cc1-54f289a17d0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10292
84036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1029284036
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.2544817530
Short name T84
Test name
Test status
Simulation time 12384795019 ps
CPU time 23.5 seconds
Started Jul 21 06:58:55 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206888 kb
Host smart-8b4f64a3-3264-4582-9c45-1d6fdbdb9eca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
17530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.2544817530
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.43905069
Short name T853
Test name
Test status
Simulation time 493865132 ps
CPU time 1.3 seconds
Started Jul 21 06:58:52 PM PDT 24
Finished Jul 21 06:58:54 PM PDT 24
Peak memory 206704 kb
Host smart-5a7792fa-54c6-4f85-8184-cf6b2464c3ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43905
069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.43905069
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1296683725
Short name T1206
Test name
Test status
Simulation time 133565723 ps
CPU time 0.77 seconds
Started Jul 21 06:58:49 PM PDT 24
Finished Jul 21 06:58:50 PM PDT 24
Peak memory 206696 kb
Host smart-08a3897c-d160-442d-9453-6a9e1a303442
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12966
83725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1296683725
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.2601354284
Short name T645
Test name
Test status
Simulation time 35947585 ps
CPU time 0.66 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:06 PM PDT 24
Peak memory 206560 kb
Host smart-fa188a52-c92c-497d-811b-395fb503f508
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26013
54284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.2601354284
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.1236006963
Short name T1859
Test name
Test status
Simulation time 987441025 ps
CPU time 2.3 seconds
Started Jul 21 06:58:49 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206792 kb
Host smart-7e397f6f-045d-42d9-b0f8-8dd72bbd40fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12360
06963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1236006963
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1218094921
Short name T2462
Test name
Test status
Simulation time 207041764 ps
CPU time 1.51 seconds
Started Jul 21 06:58:57 PM PDT 24
Finished Jul 21 06:58:58 PM PDT 24
Peak memory 206808 kb
Host smart-eaabf575-6137-4d0a-accf-86276c8459ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12180
94921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1218094921
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.561709166
Short name T673
Test name
Test status
Simulation time 216535564 ps
CPU time 0.97 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:02 PM PDT 24
Peak memory 206672 kb
Host smart-9624563e-6340-4616-b7fe-3c79db5ff195
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56170
9166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.561709166
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.1527367083
Short name T730
Test name
Test status
Simulation time 134760275 ps
CPU time 0.72 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206608 kb
Host smart-fb61488f-362c-4afa-9c9f-189ff305e8e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15273
67083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.1527367083
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.2003187294
Short name T2586
Test name
Test status
Simulation time 214116418 ps
CPU time 0.89 seconds
Started Jul 21 06:58:47 PM PDT 24
Finished Jul 21 06:58:48 PM PDT 24
Peak memory 206636 kb
Host smart-65bf9ed9-b141-425f-b5ad-20cae2dbae1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20031
87294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.2003187294
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.912198773
Short name T407
Test name
Test status
Simulation time 7295306119 ps
CPU time 209.52 seconds
Started Jul 21 06:58:51 PM PDT 24
Finished Jul 21 07:02:21 PM PDT 24
Peak memory 206904 kb
Host smart-57db8354-d2ce-476a-ae83-540e9ad3614b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=912198773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.912198773
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2726948540
Short name T1437
Test name
Test status
Simulation time 6050632814 ps
CPU time 51.94 seconds
Started Jul 21 06:58:48 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206920 kb
Host smart-17102270-665e-4164-ba5d-efe4e5c08f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27269
48540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2726948540
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.695063845
Short name T2653
Test name
Test status
Simulation time 179568271 ps
CPU time 0.86 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206560 kb
Host smart-d8ffbb12-de7b-429b-bb08-4b79b223ed07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69506
3845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.695063845
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1935520420
Short name T968
Test name
Test status
Simulation time 23300178038 ps
CPU time 24.56 seconds
Started Jul 21 06:58:59 PM PDT 24
Finished Jul 21 06:59:24 PM PDT 24
Peak memory 206784 kb
Host smart-e543166f-4c16-4ac7-80f9-7f2e72d25040
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19355
20420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1935520420
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.52370437
Short name T302
Test name
Test status
Simulation time 3394257929 ps
CPU time 4.06 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206772 kb
Host smart-e9af5451-0a0a-40bb-9245-f8a77ecd5e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52370
437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.52370437
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.462982083
Short name T2604
Test name
Test status
Simulation time 10727142445 ps
CPU time 287.68 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 07:03:38 PM PDT 24
Peak memory 206988 kb
Host smart-c1ff7b71-701b-4572-9971-74d6a8bac04f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46298
2083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.462982083
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.1835579936
Short name T741
Test name
Test status
Simulation time 4910291124 ps
CPU time 47.9 seconds
Started Jul 21 06:59:00 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206932 kb
Host smart-789f36cc-6b53-4f10-9b89-1aa28c8007c9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1835579936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.1835579936
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2126565535
Short name T2668
Test name
Test status
Simulation time 236566519 ps
CPU time 0.89 seconds
Started Jul 21 06:58:46 PM PDT 24
Finished Jul 21 06:58:47 PM PDT 24
Peak memory 206632 kb
Host smart-f1e59fa0-31a6-440e-a885-649ab337ad14
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2126565535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2126565535
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.97597485
Short name T355
Test name
Test status
Simulation time 192451423 ps
CPU time 0.91 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206640 kb
Host smart-fc32bf97-d0b8-4f6d-9710-9b931f0188e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97597
485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.97597485
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.987404291
Short name T2622
Test name
Test status
Simulation time 4524218809 ps
CPU time 123.58 seconds
Started Jul 21 06:59:08 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 206884 kb
Host smart-23737b56-69e8-4bba-b467-68abef1c3ff2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98740
4291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.987404291
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1800193252
Short name T1777
Test name
Test status
Simulation time 7651673765 ps
CPU time 51.77 seconds
Started Jul 21 06:58:53 PM PDT 24
Finished Jul 21 06:59:45 PM PDT 24
Peak memory 206900 kb
Host smart-d95c3d66-f6c0-443b-b0f2-4d2d7d1a3166
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1800193252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1800193252
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1913245503
Short name T1802
Test name
Test status
Simulation time 176571248 ps
CPU time 0.8 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 06:58:51 PM PDT 24
Peak memory 206628 kb
Host smart-971deb9e-a7d5-4978-b5b6-b4af9f91ada8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1913245503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1913245503
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.4162671341
Short name T545
Test name
Test status
Simulation time 159078461 ps
CPU time 0.82 seconds
Started Jul 21 06:58:49 PM PDT 24
Finished Jul 21 06:58:50 PM PDT 24
Peak memory 206700 kb
Host smart-1dc78e06-39cf-464a-a4bd-e4b2d2f4164b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41626
71341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.4162671341
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1547122673
Short name T108
Test name
Test status
Simulation time 170038207 ps
CPU time 0.81 seconds
Started Jul 21 06:59:03 PM PDT 24
Finished Jul 21 06:59:06 PM PDT 24
Peak memory 206696 kb
Host smart-bf35b476-21f8-471c-bb76-f50ca57a10be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15471
22673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1547122673
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.240655011
Short name T991
Test name
Test status
Simulation time 171544221 ps
CPU time 0.83 seconds
Started Jul 21 06:58:52 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206700 kb
Host smart-e3431116-392e-4ead-8d1f-cf5c3b587aac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24065
5011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.240655011
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1456094885
Short name T2712
Test name
Test status
Simulation time 154361574 ps
CPU time 0.76 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206608 kb
Host smart-bc3f3b3d-5887-49b0-8a40-bfff4aad5916
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14560
94885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1456094885
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.2270753599
Short name T1796
Test name
Test status
Simulation time 165236813 ps
CPU time 0.81 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:09 PM PDT 24
Peak memory 206684 kb
Host smart-3893479e-917b-4483-a6bc-56435d7ef0fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22707
53599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.2270753599
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3862032258
Short name T729
Test name
Test status
Simulation time 162202732 ps
CPU time 0.8 seconds
Started Jul 21 06:58:52 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206692 kb
Host smart-281f94b1-2924-42fd-9b8b-23834eec680d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38620
32258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3862032258
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.3591340855
Short name T1262
Test name
Test status
Simulation time 251882285 ps
CPU time 1 seconds
Started Jul 21 06:59:03 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206688 kb
Host smart-ed0f0a3a-eded-4d4a-bf96-8b12e2cad5b2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3591340855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.3591340855
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.380729253
Short name T1242
Test name
Test status
Simulation time 156957055 ps
CPU time 0.8 seconds
Started Jul 21 06:58:51 PM PDT 24
Finished Jul 21 06:58:52 PM PDT 24
Peak memory 206672 kb
Host smart-ffa1599e-b519-4769-81ef-de39fc4582f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
9253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.380729253
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.654985953
Short name T754
Test name
Test status
Simulation time 102852852 ps
CPU time 0.72 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206560 kb
Host smart-c65c5c8a-2b8b-42c4-93ec-aec47a894a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65498
5953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.654985953
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.3931548866
Short name T1201
Test name
Test status
Simulation time 17322922841 ps
CPU time 40.28 seconds
Started Jul 21 06:58:52 PM PDT 24
Finished Jul 21 06:59:33 PM PDT 24
Peak memory 206960 kb
Host smart-3c30b43c-b86d-43de-b553-abee83c442df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39315
48866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.3931548866
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.2569081621
Short name T2716
Test name
Test status
Simulation time 180471066 ps
CPU time 0.81 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:18 PM PDT 24
Peak memory 206664 kb
Host smart-a8d9f133-ffdb-48e0-8ec3-e3328135359d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25690
81621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.2569081621
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.842712331
Short name T1354
Test name
Test status
Simulation time 272456145 ps
CPU time 0.94 seconds
Started Jul 21 06:58:51 PM PDT 24
Finished Jul 21 06:58:53 PM PDT 24
Peak memory 206680 kb
Host smart-0aa97b21-7471-4858-977b-6e7010f84aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84271
2331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.842712331
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3784682957
Short name T307
Test name
Test status
Simulation time 196545747 ps
CPU time 0.85 seconds
Started Jul 21 06:58:50 PM PDT 24
Finished Jul 21 06:58:52 PM PDT 24
Peak memory 206664 kb
Host smart-080e8129-5793-4fdd-ad5a-2607993b2652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37846
82957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3784682957
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.1599730078
Short name T2626
Test name
Test status
Simulation time 178128975 ps
CPU time 0.84 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:04 PM PDT 24
Peak memory 206664 kb
Host smart-3e8165da-da1c-43ed-b932-a71126800ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15997
30078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.1599730078
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.653146476
Short name T575
Test name
Test status
Simulation time 140134195 ps
CPU time 0.76 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:08 PM PDT 24
Peak memory 206664 kb
Host smart-1535aa3b-240e-461b-b13c-e553fcf3ca34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65314
6476 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.653146476
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.2063299529
Short name T2685
Test name
Test status
Simulation time 158383987 ps
CPU time 0.79 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:09 PM PDT 24
Peak memory 206568 kb
Host smart-92274a75-da21-4286-b879-e849b95c6db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20632
99529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.2063299529
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.4209220817
Short name T1008
Test name
Test status
Simulation time 164622943 ps
CPU time 0.8 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206784 kb
Host smart-fb5aebc7-2ac5-4d57-b09d-ea780c619797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42092
20817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.4209220817
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.2497589633
Short name T796
Test name
Test status
Simulation time 204422833 ps
CPU time 0.9 seconds
Started Jul 21 06:58:52 PM PDT 24
Finished Jul 21 06:58:54 PM PDT 24
Peak memory 206672 kb
Host smart-ef3ee568-888d-42c4-8261-9f2956aff6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24975
89633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.2497589633
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.959012230
Short name T2751
Test name
Test status
Simulation time 5946572923 ps
CPU time 55.6 seconds
Started Jul 21 06:58:52 PM PDT 24
Finished Jul 21 06:59:48 PM PDT 24
Peak memory 206856 kb
Host smart-0ea70997-7411-432c-81ca-49d0688f575c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=959012230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.959012230
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.2026659531
Short name T1690
Test name
Test status
Simulation time 184627895 ps
CPU time 0.87 seconds
Started Jul 21 06:59:00 PM PDT 24
Finished Jul 21 06:59:01 PM PDT 24
Peak memory 206672 kb
Host smart-dfe2d7be-962c-4f83-8cc9-e481a0154b71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20266
59531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.2026659531
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.171919444
Short name T2699
Test name
Test status
Simulation time 204558830 ps
CPU time 0.89 seconds
Started Jul 21 06:59:07 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206692 kb
Host smart-84eec9c7-3d9b-42af-9b91-e675f92d6635
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17191
9444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.171919444
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.1477073180
Short name T987
Test name
Test status
Simulation time 1120402002 ps
CPU time 2.33 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206820 kb
Host smart-b277c95a-f355-4fc4-9304-a19332615eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14770
73180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.1477073180
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.3921721525
Short name T1211
Test name
Test status
Simulation time 3064858334 ps
CPU time 27.76 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:36 PM PDT 24
Peak memory 206860 kb
Host smart-a1a777d7-0bdc-48f2-a566-e710f58de24f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39217
21525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.3921721525
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.26880780
Short name T1594
Test name
Test status
Simulation time 64114404 ps
CPU time 0.71 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:09 PM PDT 24
Peak memory 206712 kb
Host smart-9591abb0-d9fb-48c0-bc74-00daf8af3bd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=26880780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.26880780
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.2842614706
Short name T2129
Test name
Test status
Simulation time 4306302039 ps
CPU time 5.36 seconds
Started Jul 21 06:59:08 PM PDT 24
Finished Jul 21 06:59:16 PM PDT 24
Peak memory 206796 kb
Host smart-137f0b16-97f7-4698-b3b0-96daa66f3df7
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2842614706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.2842614706
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.186534706
Short name T2263
Test name
Test status
Simulation time 13295851550 ps
CPU time 12.39 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206980 kb
Host smart-9741bc2c-3cef-40db-b5bc-f9faad851bac
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=186534706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.186534706
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1328636374
Short name T2275
Test name
Test status
Simulation time 23335941192 ps
CPU time 30.91 seconds
Started Jul 21 06:58:55 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 206780 kb
Host smart-84b85e06-7f85-4fcc-aad4-69558a253ba6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1328636374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.1328636374
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.3750722236
Short name T2453
Test name
Test status
Simulation time 163756210 ps
CPU time 0.88 seconds
Started Jul 21 06:59:00 PM PDT 24
Finished Jul 21 06:59:02 PM PDT 24
Peak memory 206692 kb
Host smart-74171f7a-b1a8-44a3-aa50-f4d63a41bc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37507
22236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.3750722236
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.2971926716
Short name T1660
Test name
Test status
Simulation time 173861259 ps
CPU time 0.82 seconds
Started Jul 21 06:59:13 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206692 kb
Host smart-3534b560-7939-49f7-b062-8bd11d9f2fd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
26716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.2971926716
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.268082061
Short name T96
Test name
Test status
Simulation time 394063062 ps
CPU time 1.42 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:04 PM PDT 24
Peak memory 206664 kb
Host smart-5194d237-3d9b-4720-9100-48472854b9ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26808
2061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.268082061
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.2743576719
Short name T909
Test name
Test status
Simulation time 1502950179 ps
CPU time 3.61 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206796 kb
Host smart-82897661-d941-4a20-be6e-d41ccd8d7452
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27435
76719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.2743576719
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.4226137247
Short name T2021
Test name
Test status
Simulation time 9360004232 ps
CPU time 17.94 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206884 kb
Host smart-ccfc4b85-2a2a-4d39-a2e6-5728bb5246ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42261
37247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.4226137247
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.857324675
Short name T507
Test name
Test status
Simulation time 437827867 ps
CPU time 1.28 seconds
Started Jul 21 06:58:56 PM PDT 24
Finished Jul 21 06:58:58 PM PDT 24
Peak memory 206672 kb
Host smart-f77a7961-a55f-4105-8531-fe7b66a0f338
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85732
4675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.857324675
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.1542171226
Short name T585
Test name
Test status
Simulation time 147593432 ps
CPU time 0.76 seconds
Started Jul 21 06:59:00 PM PDT 24
Finished Jul 21 06:59:01 PM PDT 24
Peak memory 206636 kb
Host smart-0ed2713e-e377-47a4-a9e4-1e707f469c2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15421
71226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.1542171226
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.348425278
Short name T2432
Test name
Test status
Simulation time 56940390 ps
CPU time 0.68 seconds
Started Jul 21 06:59:08 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206656 kb
Host smart-4a55986b-ea3c-4ef5-95b6-f4c8bdfd8f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34842
5278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.348425278
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.837469907
Short name T1099
Test name
Test status
Simulation time 781287846 ps
CPU time 1.89 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206808 kb
Host smart-0f91084a-323b-440a-9c7b-5d507b58fa3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83746
9907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.837469907
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.3153652088
Short name T1810
Test name
Test status
Simulation time 345348355 ps
CPU time 2.01 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206732 kb
Host smart-e2a10e31-e890-4bc1-9dea-0f4a2fe22c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31536
52088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.3153652088
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.3543353680
Short name T1378
Test name
Test status
Simulation time 246213241 ps
CPU time 0.93 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206648 kb
Host smart-822b7761-1b21-4133-9cd5-fe3988ed50f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
53680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.3543353680
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.813117663
Short name T1671
Test name
Test status
Simulation time 155006299 ps
CPU time 0.83 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:09 PM PDT 24
Peak memory 206656 kb
Host smart-5dda6c82-6442-4f45-852c-5da43caf9cc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81311
7663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.813117663
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.4275589410
Short name T1171
Test name
Test status
Simulation time 189557673 ps
CPU time 0.9 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:03 PM PDT 24
Peak memory 206668 kb
Host smart-0927394e-1149-435c-bb16-9804503eb1e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42755
89410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.4275589410
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.1516403079
Short name T1756
Test name
Test status
Simulation time 10025721030 ps
CPU time 284.1 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 07:03:48 PM PDT 24
Peak memory 206912 kb
Host smart-9fd6af5b-6118-43c8-adc3-13eea37a1ea3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1516403079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.1516403079
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_iso_retraction.4028672081
Short name T1103
Test name
Test status
Simulation time 6922535844 ps
CPU time 58.45 seconds
Started Jul 21 06:59:08 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206932 kb
Host smart-a4f9e3b8-6a69-4d0d-9554-9100e29b7ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40286
72081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_iso_retraction.4028672081
Directory /workspace/37.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.632076053
Short name T397
Test name
Test status
Simulation time 167827360 ps
CPU time 0.8 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206652 kb
Host smart-b266e5b2-8077-4e21-9da6-f88946ac5d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63207
6053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.632076053
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2829025709
Short name T1478
Test name
Test status
Simulation time 23267596856 ps
CPU time 23.56 seconds
Started Jul 21 06:59:07 PM PDT 24
Finished Jul 21 06:59:33 PM PDT 24
Peak memory 206784 kb
Host smart-c5668109-b127-48a9-aa5f-c5d143ad57d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28290
25709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2829025709
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1554770810
Short name T446
Test name
Test status
Simulation time 3288113218 ps
CPU time 4.43 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206720 kb
Host smart-3f94bf0c-fafe-4f9f-9200-a2ea3adc394f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15547
70810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1554770810
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.4000250372
Short name T2424
Test name
Test status
Simulation time 9393689381 ps
CPU time 253.55 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 07:03:25 PM PDT 24
Peak memory 206964 kb
Host smart-21604b7f-b67e-4de0-bd44-95578f843525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40002
50372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.4000250372
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.145224053
Short name T1101
Test name
Test status
Simulation time 4493215852 ps
CPU time 126.07 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 206852 kb
Host smart-f8e44c9f-0053-4e56-84aa-ce8026d51ecc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=145224053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.145224053
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.3205666559
Short name T1652
Test name
Test status
Simulation time 241244840 ps
CPU time 0.99 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206660 kb
Host smart-e738b4b4-d2ce-4612-8789-ea31f00f3213
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3205666559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.3205666559
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.2256370219
Short name T1534
Test name
Test status
Simulation time 188500069 ps
CPU time 0.85 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206676 kb
Host smart-9f05a24d-5d1b-4183-af19-9bb65441d02e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22563
70219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.2256370219
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.409870164
Short name T382
Test name
Test status
Simulation time 5246489844 ps
CPU time 148.57 seconds
Started Jul 21 06:59:00 PM PDT 24
Finished Jul 21 07:01:30 PM PDT 24
Peak memory 206864 kb
Host smart-a959a08f-446f-47a0-9e10-1b2e1f1ebb7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40987
0164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.409870164
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2558053897
Short name T697
Test name
Test status
Simulation time 5235378108 ps
CPU time 37.92 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206900 kb
Host smart-ffe606d7-0af7-4ff3-8834-603a50129272
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2558053897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2558053897
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.3608153281
Short name T2213
Test name
Test status
Simulation time 200035607 ps
CPU time 0.85 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206684 kb
Host smart-c28e6afe-6192-4934-b29b-273f956526f2
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3608153281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.3608153281
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.1825740954
Short name T865
Test name
Test status
Simulation time 152054862 ps
CPU time 0.86 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:03 PM PDT 24
Peak memory 206660 kb
Host smart-1b2ed568-c2ae-430f-a332-b477d9200408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18257
40954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.1825740954
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.4018929496
Short name T130
Test name
Test status
Simulation time 223393887 ps
CPU time 0.9 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206656 kb
Host smart-d6c337bb-a48f-4b54-9799-eba33fc00e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40189
29496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.4018929496
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.2409757544
Short name T89
Test name
Test status
Simulation time 173481984 ps
CPU time 0.82 seconds
Started Jul 21 06:59:03 PM PDT 24
Finished Jul 21 06:59:06 PM PDT 24
Peak memory 206564 kb
Host smart-0637718a-cba4-400d-a123-9cfeed40da24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24097
57544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.2409757544
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.1826245672
Short name T1395
Test name
Test status
Simulation time 176530657 ps
CPU time 0.78 seconds
Started Jul 21 06:59:07 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206656 kb
Host smart-b1ab41b1-cd08-4e98-a3b5-6013711b4f2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18262
45672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.1826245672
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1913640604
Short name T1679
Test name
Test status
Simulation time 168979220 ps
CPU time 0.81 seconds
Started Jul 21 06:59:07 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206680 kb
Host smart-8fbe755f-e79b-453e-b2fc-13c50c334ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19136
40604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1913640604
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.1842653040
Short name T167
Test name
Test status
Simulation time 145416720 ps
CPU time 0.76 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206700 kb
Host smart-2dd9fae3-bfb1-4200-86a6-3277a1623bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18426
53040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.1842653040
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.1870359109
Short name T2476
Test name
Test status
Simulation time 216232783 ps
CPU time 0.87 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206680 kb
Host smart-30113671-781e-4df4-b957-01ad68a879f1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1870359109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.1870359109
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.2332435091
Short name T932
Test name
Test status
Simulation time 144529916 ps
CPU time 0.76 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206556 kb
Host smart-0797dc07-0456-4b33-b404-480fa7767037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23324
35091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.2332435091
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.1165729589
Short name T24
Test name
Test status
Simulation time 34181943 ps
CPU time 0.69 seconds
Started Jul 21 06:59:07 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206680 kb
Host smart-afc9268d-c2ec-429e-bfc3-e1886d106811
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11657
29589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.1165729589
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.421270412
Short name T2003
Test name
Test status
Simulation time 8606988793 ps
CPU time 19.74 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:34 PM PDT 24
Peak memory 206868 kb
Host smart-6e2cf716-a94f-4bad-9ded-248d30381be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42127
0412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.421270412
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.3766100228
Short name T905
Test name
Test status
Simulation time 182165132 ps
CPU time 0.87 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206684 kb
Host smart-6c81c179-ad5a-45c5-9e2e-03afbcce9713
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37661
00228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.3766100228
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.1750745615
Short name T874
Test name
Test status
Simulation time 198705304 ps
CPU time 0.88 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206684 kb
Host smart-4169bedb-25f7-494b-a49b-63ae3340e9b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17507
45615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.1750745615
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.763840452
Short name T2542
Test name
Test status
Simulation time 241933657 ps
CPU time 0.94 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206648 kb
Host smart-2da50269-b679-4dfc-8b4c-272df673ced1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76384
0452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.763840452
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.1176593258
Short name T977
Test name
Test status
Simulation time 179642330 ps
CPU time 0.83 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206564 kb
Host smart-fd340105-0a1f-491f-a8d7-f0e0ad2aa072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11765
93258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.1176593258
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.2946309296
Short name T1389
Test name
Test status
Simulation time 150879026 ps
CPU time 0.76 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:09 PM PDT 24
Peak memory 206680 kb
Host smart-495e361d-80e7-4776-8883-dba39ee2d1c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29463
09296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.2946309296
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.4275090072
Short name T482
Test name
Test status
Simulation time 153792460 ps
CPU time 0.78 seconds
Started Jul 21 06:58:56 PM PDT 24
Finished Jul 21 06:58:58 PM PDT 24
Peak memory 206664 kb
Host smart-feb744a3-62c2-42e5-aae4-694b7f3fa0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42750
90072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.4275090072
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.2348798936
Short name T350
Test name
Test status
Simulation time 159940987 ps
CPU time 0.83 seconds
Started Jul 21 06:59:02 PM PDT 24
Finished Jul 21 06:59:04 PM PDT 24
Peak memory 206680 kb
Host smart-eff060a8-3bd7-48e2-99ed-5e5efdc72893
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23487
98936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.2348798936
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.2836091405
Short name T1700
Test name
Test status
Simulation time 195862137 ps
CPU time 0.91 seconds
Started Jul 21 06:59:11 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206700 kb
Host smart-cbd887cd-d7e1-4439-9561-b84a233ac991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28360
91405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.2836091405
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.3408911811
Short name T2412
Test name
Test status
Simulation time 6143338035 ps
CPU time 164.22 seconds
Started Jul 21 06:59:11 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 206880 kb
Host smart-12bb885f-6fc1-4a09-9422-c7a3bb25ea8c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3408911811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.3408911811
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.954759232
Short name T2428
Test name
Test status
Simulation time 189055883 ps
CPU time 0.83 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206604 kb
Host smart-ad61b65b-4459-438c-a115-8dc453dcd538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95475
9232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.954759232
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.1652761437
Short name T542
Test name
Test status
Simulation time 186046659 ps
CPU time 0.92 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:02 PM PDT 24
Peak memory 206652 kb
Host smart-7e825479-7056-4ff2-91ba-67b7cde1a31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16527
61437 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.1652761437
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.91010727
Short name T1415
Test name
Test status
Simulation time 1397761826 ps
CPU time 3.12 seconds
Started Jul 21 06:59:12 PM PDT 24
Finished Jul 21 06:59:16 PM PDT 24
Peak memory 206828 kb
Host smart-cfab1596-04d0-49b7-9935-c9ad3cfdb14c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91010
727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.91010727
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.487434864
Short name T849
Test name
Test status
Simulation time 5499854429 ps
CPU time 156.5 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 07:01:48 PM PDT 24
Peak memory 206868 kb
Host smart-bfcdedee-9aac-4e55-854e-80c558dc194b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48743
4864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.487434864
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.462876868
Short name T2331
Test name
Test status
Simulation time 43107493 ps
CPU time 0.67 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206720 kb
Host smart-94280856-5ec9-4e8a-a19c-fe03e4b67672
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=462876868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.462876868
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3688913097
Short name T2574
Test name
Test status
Simulation time 4393228845 ps
CPU time 6.28 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206840 kb
Host smart-0b2fe4cf-54e9-4893-8cad-88c07cc42d3c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3688913097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3688913097
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.494515581
Short name T473
Test name
Test status
Simulation time 13337840399 ps
CPU time 12.58 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 06:59:24 PM PDT 24
Peak memory 206784 kb
Host smart-6f6a4301-815f-4ba5-92ca-d4df42aa2086
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=494515581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.494515581
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.3203590266
Short name T2349
Test name
Test status
Simulation time 23350771370 ps
CPU time 23.13 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:29 PM PDT 24
Peak memory 206776 kb
Host smart-90b57f3e-cfd1-4f0d-ae12-e32f6d9d2bb1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3203590266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.3203590266
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2984781250
Short name T1782
Test name
Test status
Simulation time 152757055 ps
CPU time 0.79 seconds
Started Jul 21 06:59:08 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206684 kb
Host smart-4a7d8942-ecdf-4f66-ae5b-0825008ba2aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29847
81250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2984781250
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.581623913
Short name T1749
Test name
Test status
Simulation time 143763410 ps
CPU time 0.83 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206696 kb
Host smart-8254fb4a-3f11-4932-9d94-15d751eb7b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58162
3913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.581623913
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.951924183
Short name T2171
Test name
Test status
Simulation time 196801626 ps
CPU time 0.87 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:03 PM PDT 24
Peak memory 206664 kb
Host smart-35eefec3-212b-4245-986b-b73b50f4539d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95192
4183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.951924183
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.4269181985
Short name T779
Test name
Test status
Simulation time 1105612491 ps
CPU time 2.54 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206844 kb
Host smart-37ed3068-de70-47b2-a899-1872b2ed0c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42691
81985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.4269181985
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3433115080
Short name T975
Test name
Test status
Simulation time 12368782688 ps
CPU time 23.27 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:33 PM PDT 24
Peak memory 206892 kb
Host smart-f7fabd97-78bd-455b-b19f-f594348b0351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34331
15080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3433115080
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.2899095446
Short name T1439
Test name
Test status
Simulation time 318195880 ps
CPU time 1.2 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206684 kb
Host smart-497e79e6-976f-40d4-8770-fe8e95e417ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28990
95446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.2899095446
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.3019493922
Short name T926
Test name
Test status
Simulation time 138671562 ps
CPU time 0.75 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:09 PM PDT 24
Peak memory 206672 kb
Host smart-f7becbd2-6319-4cb2-b98f-89a05d096ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30194
93922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.3019493922
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.412692337
Short name T2113
Test name
Test status
Simulation time 33367539 ps
CPU time 0.68 seconds
Started Jul 21 06:59:13 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206780 kb
Host smart-14a24f0e-477d-4c58-81d6-753e1da46b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41269
2337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.412692337
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.654386704
Short name T530
Test name
Test status
Simulation time 881309263 ps
CPU time 2.15 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206784 kb
Host smart-f26331ec-574f-4565-9ed2-8a7a7d3d9d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65438
6704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.654386704
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.4264646792
Short name T2359
Test name
Test status
Simulation time 330360460 ps
CPU time 2.49 seconds
Started Jul 21 06:59:05 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206740 kb
Host smart-062a43ff-bf70-4d69-9ce8-3f588bdd515c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
46792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.4264646792
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3727514473
Short name T715
Test name
Test status
Simulation time 230597119 ps
CPU time 0.93 seconds
Started Jul 21 06:59:07 PM PDT 24
Finished Jul 21 06:59:11 PM PDT 24
Peak memory 206676 kb
Host smart-ff326be5-0ca9-4cd6-aba4-876950552039
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37275
14473 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3727514473
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.2230849147
Short name T1355
Test name
Test status
Simulation time 153730736 ps
CPU time 0.78 seconds
Started Jul 21 06:59:00 PM PDT 24
Finished Jul 21 06:59:02 PM PDT 24
Peak memory 206672 kb
Host smart-0a86c202-aa4c-4845-a776-9df030252cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22308
49147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.2230849147
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.2794974720
Short name T2135
Test name
Test status
Simulation time 206750364 ps
CPU time 0.9 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:10 PM PDT 24
Peak memory 206672 kb
Host smart-c734d0cb-e0cf-4748-a316-23143ced7e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27949
74720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.2794974720
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.290494364
Short name T591
Test name
Test status
Simulation time 4397220736 ps
CPU time 113.11 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 206860 kb
Host smart-89f5ec9e-65a7-426b-931d-353d4c8bb204
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=290494364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.290494364
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.60237064
Short name T682
Test name
Test status
Simulation time 4924127295 ps
CPU time 17.4 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 06:59:29 PM PDT 24
Peak memory 206976 kb
Host smart-969bd35d-ae36-40d0-b030-5afee1b3a0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60237
064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.60237064
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.3060098913
Short name T1965
Test name
Test status
Simulation time 207335464 ps
CPU time 0.88 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206640 kb
Host smart-879668fd-5027-4355-8e87-3c790136e068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30600
98913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.3060098913
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.621684387
Short name T2396
Test name
Test status
Simulation time 23315021767 ps
CPU time 26.12 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 06:59:28 PM PDT 24
Peak memory 206800 kb
Host smart-41926ef3-3b17-4e92-a9db-8e9ffdf8fab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62168
4387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.621684387
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3550543165
Short name T2111
Test name
Test status
Simulation time 3329738490 ps
CPU time 3.6 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:16 PM PDT 24
Peak memory 206768 kb
Host smart-b6a88a5f-0c53-448e-9d09-e836a1ff97ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35505
43165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3550543165
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2351232121
Short name T2602
Test name
Test status
Simulation time 4992729404 ps
CPU time 137.66 seconds
Started Jul 21 06:59:01 PM PDT 24
Finished Jul 21 07:01:20 PM PDT 24
Peak memory 206948 kb
Host smart-91eaad48-5866-4cc5-a2c0-7428da8b9bc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23512
32121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2351232121
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.2561919453
Short name T2175
Test name
Test status
Simulation time 5309575739 ps
CPU time 48.82 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:58 PM PDT 24
Peak memory 206916 kb
Host smart-60684b8b-4141-4262-bd73-2bca74202d95
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2561919453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.2561919453
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.1554444838
Short name T2612
Test name
Test status
Simulation time 240757120 ps
CPU time 0.91 seconds
Started Jul 21 06:58:59 PM PDT 24
Finished Jul 21 06:59:01 PM PDT 24
Peak memory 206664 kb
Host smart-d22de363-0f77-409a-b3ca-5f81d6323341
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1554444838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.1554444838
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.3110854756
Short name T2357
Test name
Test status
Simulation time 202014134 ps
CPU time 0.87 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206628 kb
Host smart-d9c6d974-c4ea-4f3d-8cf3-949e484e8413
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31108
54756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.3110854756
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.2435759100
Short name T1315
Test name
Test status
Simulation time 5046483714 ps
CPU time 36.99 seconds
Started Jul 21 06:59:11 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206940 kb
Host smart-6b3e9161-5c9a-4127-8712-6da0040b3f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24357
59100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.2435759100
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2250902189
Short name T2529
Test name
Test status
Simulation time 7973378376 ps
CPU time 68.15 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 07:00:17 PM PDT 24
Peak memory 206848 kb
Host smart-6101fc36-2910-4951-bb8c-718a20cb339b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2250902189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2250902189
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.2845082097
Short name T886
Test name
Test status
Simulation time 179917919 ps
CPU time 0.86 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:07 PM PDT 24
Peak memory 206652 kb
Host smart-e3011e2d-759a-4685-819a-017fa65239ab
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2845082097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.2845082097
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.3114188804
Short name T486
Test name
Test status
Simulation time 154809014 ps
CPU time 0.76 seconds
Started Jul 21 06:59:12 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206656 kb
Host smart-27dbc6d2-84f4-4310-9327-743e6d2e5f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31141
88804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.3114188804
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.3121235004
Short name T1250
Test name
Test status
Simulation time 175759282 ps
CPU time 0.82 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206704 kb
Host smart-fbb00eb4-9676-4d38-840a-3acde43e59f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31212
35004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.3121235004
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3753311147
Short name T322
Test name
Test status
Simulation time 191765517 ps
CPU time 0.83 seconds
Started Jul 21 06:59:20 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206684 kb
Host smart-6a7c563a-7497-4016-b996-2521d66b66ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37533
11147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3753311147
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.954584842
Short name T2032
Test name
Test status
Simulation time 174391851 ps
CPU time 0.79 seconds
Started Jul 21 06:59:11 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206688 kb
Host smart-6e9bc580-4d47-479e-82bd-7bae84f4b7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95458
4842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.954584842
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3080620280
Short name T2069
Test name
Test status
Simulation time 147519858 ps
CPU time 0.78 seconds
Started Jul 21 06:59:19 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206668 kb
Host smart-dacc1c6c-b3f2-4c0e-9a3a-256de628d04e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30806
20280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3080620280
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.69363136
Short name T611
Test name
Test status
Simulation time 252142091 ps
CPU time 1.01 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206668 kb
Host smart-8a69bb6d-15a7-4488-85fe-c2a7693a75bf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=69363136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.69363136
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.1554912548
Short name T1341
Test name
Test status
Simulation time 141472034 ps
CPU time 0.76 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206672 kb
Host smart-af8e685b-db89-42f5-b98a-ea194b81422e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15549
12548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.1554912548
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.3858571803
Short name T2077
Test name
Test status
Simulation time 39741655 ps
CPU time 0.65 seconds
Started Jul 21 06:59:03 PM PDT 24
Finished Jul 21 06:59:05 PM PDT 24
Peak memory 206648 kb
Host smart-09981cb3-54d0-488f-a97c-5063d91878ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
71803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.3858571803
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1052786751
Short name T1259
Test name
Test status
Simulation time 12404691075 ps
CPU time 30.98 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:43 PM PDT 24
Peak memory 206948 kb
Host smart-e6b376af-a1ee-4475-8d57-80d75373b3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10527
86751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1052786751
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.69353587
Short name T1707
Test name
Test status
Simulation time 167332824 ps
CPU time 0.82 seconds
Started Jul 21 06:59:04 PM PDT 24
Finished Jul 21 06:59:06 PM PDT 24
Peak memory 206696 kb
Host smart-17c13e32-855e-4291-8cbb-d2f85be7adde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69353
587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.69353587
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.834939482
Short name T702
Test name
Test status
Simulation time 250848770 ps
CPU time 0.95 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:18 PM PDT 24
Peak memory 206676 kb
Host smart-29b6664a-e72a-46dd-8922-635433fdd574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83493
9482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.834939482
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.526139591
Short name T2507
Test name
Test status
Simulation time 190160596 ps
CPU time 0.83 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206624 kb
Host smart-3a4cf50b-a327-4bc9-a2b9-a519003ed6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52613
9591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.526139591
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.3015963374
Short name T1838
Test name
Test status
Simulation time 214497438 ps
CPU time 0.84 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206696 kb
Host smart-4d30d7d7-098f-42a0-a348-a5f76b026bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30159
63374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.3015963374
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3834756783
Short name T1581
Test name
Test status
Simulation time 138291922 ps
CPU time 0.74 seconds
Started Jul 21 06:59:11 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206648 kb
Host smart-1dbbc873-2e3f-476c-b4fa-72020faed77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38347
56783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3834756783
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.482132327
Short name T2089
Test name
Test status
Simulation time 170159724 ps
CPU time 0.82 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206628 kb
Host smart-c3a3fb1e-e9b7-463a-bff6-de943f927cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48213
2327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.482132327
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.1169085143
Short name T398
Test name
Test status
Simulation time 155180396 ps
CPU time 0.77 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206684 kb
Host smart-740ee424-c088-4b23-bf8b-778456076cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11690
85143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.1169085143
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.3337161706
Short name T724
Test name
Test status
Simulation time 226324707 ps
CPU time 0.92 seconds
Started Jul 21 06:59:13 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206652 kb
Host smart-5cbbb989-3757-4e0e-a623-314c3f343422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33371
61706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.3337161706
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.4201721643
Short name T1302
Test name
Test status
Simulation time 4801779721 ps
CPU time 129.09 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 07:01:29 PM PDT 24
Peak memory 206972 kb
Host smart-a58dcd41-62b6-4467-b257-bf1a4dea2828
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4201721643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.4201721643
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.383325444
Short name T2029
Test name
Test status
Simulation time 202892503 ps
CPU time 0.82 seconds
Started Jul 21 06:59:12 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206672 kb
Host smart-512d3e13-756b-4bcc-9056-d2b29647a985
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38332
5444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.383325444
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.360070401
Short name T564
Test name
Test status
Simulation time 212362364 ps
CPU time 0.79 seconds
Started Jul 21 06:59:24 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 206664 kb
Host smart-226395e6-c223-4bbc-a364-b998f529d245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36007
0401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.360070401
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.629945624
Short name T2137
Test name
Test status
Simulation time 994084058 ps
CPU time 2.35 seconds
Started Jul 21 06:59:12 PM PDT 24
Finished Jul 21 06:59:15 PM PDT 24
Peak memory 206772 kb
Host smart-6775f6d9-6825-4784-bb94-7baf889d6d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62994
5624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.629945624
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.2468099530
Short name T990
Test name
Test status
Simulation time 5792163653 ps
CPU time 40.78 seconds
Started Jul 21 06:59:13 PM PDT 24
Finished Jul 21 06:59:55 PM PDT 24
Peak memory 206948 kb
Host smart-e4531270-231a-4a43-8980-41b073a2cd1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24680
99530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.2468099530
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1335106210
Short name T2220
Test name
Test status
Simulation time 45227159 ps
CPU time 0.67 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206704 kb
Host smart-35468ade-29bf-4ba0-b8e5-8ddb7d8b31a7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1335106210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1335106210
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1891149028
Short name T679
Test name
Test status
Simulation time 3611993764 ps
CPU time 4.32 seconds
Started Jul 21 06:59:22 PM PDT 24
Finished Jul 21 06:59:27 PM PDT 24
Peak memory 206672 kb
Host smart-ed27f301-b3ff-4d91-854a-825ef05b38d1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1891149028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1891149028
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.4218741884
Short name T196
Test name
Test status
Simulation time 13326861238 ps
CPU time 12.88 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206928 kb
Host smart-b5714cfb-79a4-4765-ba85-d67202a8886b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4218741884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.4218741884
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.2515536643
Short name T2027
Test name
Test status
Simulation time 23422896094 ps
CPU time 24.94 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206928 kb
Host smart-38d3b2c9-b567-475e-bc93-286ea3231aaa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2515536643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.2515536643
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.1456894547
Short name T1282
Test name
Test status
Simulation time 159740119 ps
CPU time 0.79 seconds
Started Jul 21 06:59:08 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206684 kb
Host smart-ec5d3e79-38f4-46ee-b578-235cbd594a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14568
94547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.1456894547
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2747726032
Short name T2006
Test name
Test status
Simulation time 154485630 ps
CPU time 0.79 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206636 kb
Host smart-8f44e503-870d-4b15-b4da-71352310a215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27477
26032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2747726032
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.3560846092
Short name T2672
Test name
Test status
Simulation time 260524343 ps
CPU time 0.95 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206624 kb
Host smart-3281b8a5-38e0-4a6f-891c-dc94eb4d9100
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35608
46092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.3560846092
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.4191961119
Short name T2124
Test name
Test status
Simulation time 902456202 ps
CPU time 2.1 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206844 kb
Host smart-b01e80de-17a1-4867-8f2c-b70ede8d7c0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41919
61119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.4191961119
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2704853373
Short name T2635
Test name
Test status
Simulation time 18570695008 ps
CPU time 32.18 seconds
Started Jul 21 06:59:06 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206912 kb
Host smart-3256ba19-4599-4b54-b477-054f70f36843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27048
53373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2704853373
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.1299794369
Short name T238
Test name
Test status
Simulation time 508468599 ps
CPU time 1.29 seconds
Started Jul 21 06:59:24 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 206672 kb
Host smart-8fd2dc5a-a6b6-48f3-86c3-b333f10851f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12997
94369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.1299794369
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.3540874289
Short name T384
Test name
Test status
Simulation time 139622308 ps
CPU time 0.77 seconds
Started Jul 21 06:59:09 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 206684 kb
Host smart-2f462128-ff91-410f-8336-817f8713a6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35408
74289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.3540874289
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2326108064
Short name T1269
Test name
Test status
Simulation time 59918791 ps
CPU time 0.68 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206692 kb
Host smart-f1a4cdcd-fef7-4a06-8115-b5f6358270b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23261
08064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2326108064
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1803467636
Short name T2160
Test name
Test status
Simulation time 703401383 ps
CPU time 1.82 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206744 kb
Host smart-ff4ad1d8-f60b-4d72-ac62-50d946f4d172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034
67636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1803467636
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.3022897326
Short name T736
Test name
Test status
Simulation time 398965434 ps
CPU time 2.43 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206832 kb
Host smart-b584b8f1-b4f4-466a-8913-9bb643972bbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30228
97326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.3022897326
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.963315372
Short name T2217
Test name
Test status
Simulation time 188666713 ps
CPU time 0.85 seconds
Started Jul 21 06:59:22 PM PDT 24
Finished Jul 21 06:59:24 PM PDT 24
Peak memory 206644 kb
Host smart-62043414-12d0-48a8-b2d1-c546465242f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96331
5372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.963315372
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2825144010
Short name T332
Test name
Test status
Simulation time 143579038 ps
CPU time 0.76 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:15 PM PDT 24
Peak memory 206656 kb
Host smart-92023092-17fa-4670-ac69-4782cb9767be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28251
44010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2825144010
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.3457334306
Short name T1465
Test name
Test status
Simulation time 155247405 ps
CPU time 0.8 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206656 kb
Host smart-fd385fa6-9a38-4c23-aff6-d238e3da94c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34573
34306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.3457334306
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.471739330
Short name T2123
Test name
Test status
Simulation time 8044320620 ps
CPU time 207.06 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 07:02:47 PM PDT 24
Peak memory 206864 kb
Host smart-a4f6752f-e4f8-4601-872d-05cda7a61b91
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=471739330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.471739330
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.3652794301
Short name T1592
Test name
Test status
Simulation time 9189117701 ps
CPU time 27.21 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:47 PM PDT 24
Peak memory 206776 kb
Host smart-44433172-3a64-4d3b-adae-3799e7a8c315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36527
94301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.3652794301
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.1471189756
Short name T2605
Test name
Test status
Simulation time 213973340 ps
CPU time 0.85 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206664 kb
Host smart-846377eb-095b-42cd-9c51-9e3e9d116c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14711
89756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.1471189756
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.1393850389
Short name T2315
Test name
Test status
Simulation time 23255301129 ps
CPU time 24.67 seconds
Started Jul 21 06:59:19 PM PDT 24
Finished Jul 21 06:59:47 PM PDT 24
Peak memory 206812 kb
Host smart-9766a7f2-2968-46a3-b057-896b1cefb835
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13938
50389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.1393850389
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.4260536047
Short name T1021
Test name
Test status
Simulation time 3290638081 ps
CPU time 4.66 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206736 kb
Host smart-89180d3f-419a-4c82-adbd-eec369c0281e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42605
36047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.4260536047
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.2600437918
Short name T1225
Test name
Test status
Simulation time 12409565248 ps
CPU time 117.26 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 07:01:14 PM PDT 24
Peak memory 206956 kb
Host smart-727b4eb0-2ea4-4191-8a75-393d9716bba3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26004
37918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.2600437918
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.1073406277
Short name T168
Test name
Test status
Simulation time 7193824243 ps
CPU time 198.48 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 07:02:37 PM PDT 24
Peak memory 206892 kb
Host smart-049e5409-6e8b-415f-97ee-c553fa6dadbc
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1073406277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.1073406277
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.2308790600
Short name T2084
Test name
Test status
Simulation time 233206147 ps
CPU time 0.92 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:18 PM PDT 24
Peak memory 206692 kb
Host smart-8ef08202-be8c-4d1d-a1f4-7b2e3bfd0e72
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2308790600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.2308790600
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.3642382786
Short name T1205
Test name
Test status
Simulation time 197825368 ps
CPU time 0.84 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206584 kb
Host smart-c69d3c1b-b17d-4d2f-9a0d-b3c9c3dfdee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36423
82786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.3642382786
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.230690784
Short name T2400
Test name
Test status
Simulation time 5401723986 ps
CPU time 154.05 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 07:01:50 PM PDT 24
Peak memory 206908 kb
Host smart-1b415417-ef62-4f50-8fc0-fbfefd50f989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23069
0784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.230690784
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.2804608231
Short name T652
Test name
Test status
Simulation time 6558344779 ps
CPU time 174.79 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 07:02:12 PM PDT 24
Peak memory 206876 kb
Host smart-aba54764-4768-49c5-b52b-99004704584a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2804608231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.2804608231
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.4183948910
Short name T477
Test name
Test status
Simulation time 153851951 ps
CPU time 0.8 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206664 kb
Host smart-c6adf7ff-ac01-4ae4-ba4b-c739f2b13b79
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4183948910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.4183948910
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.633803503
Short name T876
Test name
Test status
Simulation time 145978107 ps
CPU time 0.79 seconds
Started Jul 21 06:59:13 PM PDT 24
Finished Jul 21 06:59:15 PM PDT 24
Peak memory 206684 kb
Host smart-a7ee9142-5729-4186-b0f4-4782c3c42a34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63380
3503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.633803503
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.1286333159
Short name T1747
Test name
Test status
Simulation time 227671096 ps
CPU time 0.88 seconds
Started Jul 21 06:59:22 PM PDT 24
Finished Jul 21 06:59:24 PM PDT 24
Peak memory 206664 kb
Host smart-5dedf558-8664-4dcf-9ccd-2270e634306b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12863
33159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.1286333159
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2382269242
Short name T817
Test name
Test status
Simulation time 213400287 ps
CPU time 0.83 seconds
Started Jul 21 06:59:13 PM PDT 24
Finished Jul 21 06:59:15 PM PDT 24
Peak memory 206608 kb
Host smart-01431a77-e5ff-4ff8-8b4a-e51ce3c37f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23822
69242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2382269242
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.60339137
Short name T1289
Test name
Test status
Simulation time 219347480 ps
CPU time 0.82 seconds
Started Jul 21 06:59:21 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206652 kb
Host smart-6a6feb83-2461-4c9a-ad60-3abbd1194e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60339
137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.60339137
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.2912266533
Short name T586
Test name
Test status
Simulation time 170792565 ps
CPU time 0.82 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:18 PM PDT 24
Peak memory 206684 kb
Host smart-4dfd69d9-9895-45ea-92f8-5df1fd9e77bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29122
66533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.2912266533
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.1151092129
Short name T2314
Test name
Test status
Simulation time 160993808 ps
CPU time 0.79 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206688 kb
Host smart-9f55fad4-99c8-4ffd-aa11-fbfe5ec63c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11510
92129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.1151092129
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.854693167
Short name T413
Test name
Test status
Simulation time 222343268 ps
CPU time 0.92 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206568 kb
Host smart-1dc98765-ab85-47a3-9fea-0ebd85421c8e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=854693167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.854693167
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.1167016713
Short name T2001
Test name
Test status
Simulation time 176831674 ps
CPU time 0.83 seconds
Started Jul 21 06:59:10 PM PDT 24
Finished Jul 21 06:59:13 PM PDT 24
Peak memory 206648 kb
Host smart-9ae2ebf5-792e-47e5-bb26-911e3b92a3b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11670
16713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.1167016713
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.2976235061
Short name T1384
Test name
Test status
Simulation time 73796489 ps
CPU time 0.7 seconds
Started Jul 21 06:59:19 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206632 kb
Host smart-a4e2084d-1dcd-4f05-b36d-0cd2d0145a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29762
35061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.2976235061
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3048408006
Short name T881
Test name
Test status
Simulation time 9643273981 ps
CPU time 20.91 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:38 PM PDT 24
Peak memory 206864 kb
Host smart-3abeba38-ded0-45ee-b1be-aad9bb6e10fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30484
08006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3048408006
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.4238964218
Short name T794
Test name
Test status
Simulation time 175063193 ps
CPU time 0.82 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206688 kb
Host smart-3167b0bb-a876-430d-a96c-7bc48e0f7b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42389
64218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.4238964218
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2427060666
Short name T306
Test name
Test status
Simulation time 241907511 ps
CPU time 0.89 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206688 kb
Host smart-364728e2-e034-4d77-8228-eb52af27f699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24270
60666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2427060666
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3939875148
Short name T1531
Test name
Test status
Simulation time 211856869 ps
CPU time 0.87 seconds
Started Jul 21 06:59:12 PM PDT 24
Finished Jul 21 06:59:14 PM PDT 24
Peak memory 206664 kb
Host smart-65acfa2c-fe75-413d-b02c-5d347f4f41aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39398
75148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3939875148
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.2005226229
Short name T2538
Test name
Test status
Simulation time 179562605 ps
CPU time 0.87 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206664 kb
Host smart-897abe74-d6e8-41ec-b545-36f0199dd4ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20052
26229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.2005226229
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.4162826604
Short name T1599
Test name
Test status
Simulation time 141729914 ps
CPU time 0.78 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206704 kb
Host smart-c2111078-b918-4b33-a649-3ecbccd2c588
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41628
26604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.4162826604
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.3167428937
Short name T2059
Test name
Test status
Simulation time 146902535 ps
CPU time 0.81 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206676 kb
Host smart-f428c6c5-51b4-45d8-95b3-95706ce480d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31674
28937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.3167428937
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.1808212800
Short name T333
Test name
Test status
Simulation time 169203401 ps
CPU time 0.79 seconds
Started Jul 21 06:59:21 PM PDT 24
Finished Jul 21 06:59:24 PM PDT 24
Peak memory 206664 kb
Host smart-8fd58d47-e7de-400b-9f68-217de7409639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18082
12800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.1808212800
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.1764672655
Short name T2076
Test name
Test status
Simulation time 207202891 ps
CPU time 0.92 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206600 kb
Host smart-1ce074ac-38a5-4897-8d0e-662f25fe11a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17646
72655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.1764672655
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3006976046
Short name T508
Test name
Test status
Simulation time 5565174525 ps
CPU time 51.94 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206792 kb
Host smart-79512f07-01a5-4509-b0d6-70a4d1ddd2bd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3006976046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3006976046
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.4077171915
Short name T847
Test name
Test status
Simulation time 171573331 ps
CPU time 0.78 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206668 kb
Host smart-120c55d4-05d4-41a5-8e5a-63da67ff34df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40771
71915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.4077171915
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1334300257
Short name T402
Test name
Test status
Simulation time 194064708 ps
CPU time 0.84 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206656 kb
Host smart-b2ae7554-f525-47fe-a3f3-4d813976cdf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343
00257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1334300257
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3815170355
Short name T1244
Test name
Test status
Simulation time 1180621761 ps
CPU time 2.65 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206788 kb
Host smart-9d3e8f63-6d24-404b-a713-3cfe6cc48489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38151
70355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3815170355
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.1146477514
Short name T712
Test name
Test status
Simulation time 3333431475 ps
CPU time 91.08 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 07:00:47 PM PDT 24
Peak memory 206876 kb
Host smart-cdcdeeb2-b353-471c-ad6c-bf206765f822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11464
77514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.1146477514
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.2397122851
Short name T1759
Test name
Test status
Simulation time 49828900 ps
CPU time 0.71 seconds
Started Jul 21 06:53:40 PM PDT 24
Finished Jul 21 06:53:41 PM PDT 24
Peak memory 206736 kb
Host smart-55ba9522-0077-4d21-9c31-acbe68364f04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2397122851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.2397122851
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.143448047
Short name T883
Test name
Test status
Simulation time 4247201843 ps
CPU time 5.41 seconds
Started Jul 21 06:53:23 PM PDT 24
Finished Jul 21 06:53:29 PM PDT 24
Peak memory 206760 kb
Host smart-280da030-895d-4698-9158-b11dafbe305f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=143448047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.143448047
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.2267839601
Short name T1839
Test name
Test status
Simulation time 23375309398 ps
CPU time 30.38 seconds
Started Jul 21 06:53:23 PM PDT 24
Finished Jul 21 06:53:55 PM PDT 24
Peak memory 206760 kb
Host smart-efcd9949-3c62-4936-bc49-a0af5d13740d
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2267839601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.2267839601
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.2051732579
Short name T2633
Test name
Test status
Simulation time 154590531 ps
CPU time 0.78 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 206676 kb
Host smart-f63c5368-fd0a-4cec-883b-46bc1d86fc9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20517
32579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.2051732579
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.3735493323
Short name T2288
Test name
Test status
Simulation time 180345748 ps
CPU time 0.85 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:27 PM PDT 24
Peak memory 206680 kb
Host smart-6ea37373-d281-4316-94b5-7142dce641c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37354
93323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.3735493323
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.794618103
Short name T78
Test name
Test status
Simulation time 168311692 ps
CPU time 0.79 seconds
Started Jul 21 06:53:26 PM PDT 24
Finished Jul 21 06:53:27 PM PDT 24
Peak memory 206680 kb
Host smart-0542f563-686d-449f-b111-98d33b1b566b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79461
8103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.794618103
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.3150387338
Short name T2404
Test name
Test status
Simulation time 183527905 ps
CPU time 0.79 seconds
Started Jul 21 06:53:25 PM PDT 24
Finished Jul 21 06:53:27 PM PDT 24
Peak memory 206660 kb
Host smart-82de2f30-821e-45fa-bf49-6cfc5aa287f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31503
87338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.3150387338
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.2976419502
Short name T1997
Test name
Test status
Simulation time 190104077 ps
CPU time 0.86 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 206652 kb
Host smart-f54f77db-3bd5-4811-a0f1-943a9a6a3780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29764
19502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.2976419502
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_device_address.2994962718
Short name T160
Test name
Test status
Simulation time 11357409650 ps
CPU time 21.57 seconds
Started Jul 21 06:53:25 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206896 kb
Host smart-d82ad5d7-03a1-4f61-b73e-df3584b6fc32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
62718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.2994962718
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.4111901867
Short name T318
Test name
Test status
Simulation time 316888389 ps
CPU time 1.16 seconds
Started Jul 21 06:53:25 PM PDT 24
Finished Jul 21 06:53:28 PM PDT 24
Peak memory 206660 kb
Host smart-28287fd3-b802-475e-9d2a-c28f19abf68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41119
01867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.4111901867
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.3717835123
Short name T2662
Test name
Test status
Simulation time 151491847 ps
CPU time 0.75 seconds
Started Jul 21 06:53:23 PM PDT 24
Finished Jul 21 06:53:25 PM PDT 24
Peak memory 206664 kb
Host smart-f7a97a7b-66ab-45d3-9793-878431d1f109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37178
35123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.3717835123
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.2276720030
Short name T317
Test name
Test status
Simulation time 44217574 ps
CPU time 0.66 seconds
Started Jul 21 06:53:25 PM PDT 24
Finished Jul 21 06:53:26 PM PDT 24
Peak memory 206672 kb
Host smart-413b7a60-ba3d-4cd0-8e6f-e14a53a4c6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22767
20030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.2276720030
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.3453573888
Short name T1170
Test name
Test status
Simulation time 857505210 ps
CPU time 2.37 seconds
Started Jul 21 06:53:24 PM PDT 24
Finished Jul 21 06:53:28 PM PDT 24
Peak memory 206812 kb
Host smart-cf191849-7bac-4d43-be42-75dedc8b3859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535
73888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.3453573888
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.3208855928
Short name T1498
Test name
Test status
Simulation time 194681991 ps
CPU time 1.37 seconds
Started Jul 21 06:53:27 PM PDT 24
Finished Jul 21 06:53:29 PM PDT 24
Peak memory 206736 kb
Host smart-db2c07b4-27c8-4c27-a023-8c1dfc5b9095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32088
55928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.3208855928
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.980279644
Short name T643
Test name
Test status
Simulation time 112198465095 ps
CPU time 145.84 seconds
Started Jul 21 06:53:25 PM PDT 24
Finished Jul 21 06:55:52 PM PDT 24
Peak memory 206900 kb
Host smart-4f51edf1-413e-4704-b450-06e7a7a12a2b
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=980279644 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.980279644
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.3737155921
Short name T674
Test name
Test status
Simulation time 89151837480 ps
CPU time 128.02 seconds
Started Jul 21 06:53:29 PM PDT 24
Finished Jul 21 06:55:37 PM PDT 24
Peak memory 206884 kb
Host smart-5e5406c1-88e3-4728-85f5-29b2b3e5f58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737155921 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.3737155921
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.1895822072
Short name T843
Test name
Test status
Simulation time 108105635318 ps
CPU time 133.14 seconds
Started Jul 21 06:53:29 PM PDT 24
Finished Jul 21 06:55:43 PM PDT 24
Peak memory 206956 kb
Host smart-6825b137-ed4e-4c35-82eb-eb8a5bd64af8
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1895822072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.1895822072
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.386298002
Short name T344
Test name
Test status
Simulation time 114107225288 ps
CPU time 141.99 seconds
Started Jul 21 06:53:27 PM PDT 24
Finished Jul 21 06:55:49 PM PDT 24
Peak memory 206936 kb
Host smart-9b058737-9890-4951-a3cb-c599b869dfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386298002 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.386298002
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.642109974
Short name T1850
Test name
Test status
Simulation time 82143401173 ps
CPU time 109.24 seconds
Started Jul 21 06:53:27 PM PDT 24
Finished Jul 21 06:55:17 PM PDT 24
Peak memory 206960 kb
Host smart-2dc4cb06-045c-4d0d-aa62-a5b6aeab5562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64210
9974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.642109974
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.416006817
Short name T1933
Test name
Test status
Simulation time 268354662 ps
CPU time 0.91 seconds
Started Jul 21 06:53:29 PM PDT 24
Finished Jul 21 06:53:31 PM PDT 24
Peak memory 206604 kb
Host smart-5ccf3744-6952-40b1-a623-3ec40496807a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41600
6817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.416006817
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.2353153673
Short name T461
Test name
Test status
Simulation time 140457563 ps
CPU time 0.77 seconds
Started Jul 21 06:53:30 PM PDT 24
Finished Jul 21 06:53:31 PM PDT 24
Peak memory 206608 kb
Host smart-55c0d24f-11d1-4211-b639-732770ca18fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23531
53673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.2353153673
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.2630870979
Short name T2036
Test name
Test status
Simulation time 213207016 ps
CPU time 0.88 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:53:30 PM PDT 24
Peak memory 206664 kb
Host smart-2c099809-1ddf-47a4-aad9-f7bc96c6e723
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26308
70979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.2630870979
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_invalid_sync.765544246
Short name T213
Test name
Test status
Simulation time 4645754726 ps
CPU time 131.17 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:55:40 PM PDT 24
Peak memory 207052 kb
Host smart-768853eb-7933-4947-8c57-da6595bb8b3b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=765544246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_invalid_sync.765544246
Directory /workspace/4.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.1371262485
Short name T2490
Test name
Test status
Simulation time 225526617 ps
CPU time 0.85 seconds
Started Jul 21 06:53:27 PM PDT 24
Finished Jul 21 06:53:28 PM PDT 24
Peak memory 206676 kb
Host smart-1cebf540-336c-44e1-a0da-cc5fbd46c0bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13712
62485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.1371262485
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.1930028842
Short name T998
Test name
Test status
Simulation time 23314596910 ps
CPU time 21.16 seconds
Started Jul 21 06:53:29 PM PDT 24
Finished Jul 21 06:53:51 PM PDT 24
Peak memory 206792 kb
Host smart-c08beb97-7ce2-4f8a-8cfd-640763f3640d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19300
28842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.1930028842
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2532283368
Short name T211
Test name
Test status
Simulation time 3297794101 ps
CPU time 3.71 seconds
Started Jul 21 06:53:29 PM PDT 24
Finished Jul 21 06:53:34 PM PDT 24
Peak memory 206752 kb
Host smart-dbae7f95-d98d-4382-9984-5f43ea605724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25322
83368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2532283368
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.1803364445
Short name T1600
Test name
Test status
Simulation time 7461338643 ps
CPU time 51.82 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:54:20 PM PDT 24
Peak memory 206960 kb
Host smart-e5890232-8301-411b-99e4-e4a70807c523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18033
64445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.1803364445
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2152122848
Short name T1669
Test name
Test status
Simulation time 4188976274 ps
CPU time 40.5 seconds
Started Jul 21 06:53:35 PM PDT 24
Finished Jul 21 06:54:16 PM PDT 24
Peak memory 206912 kb
Host smart-ae579e2c-e991-42db-a628-e7e52137c268
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2152122848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2152122848
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3735857273
Short name T2571
Test name
Test status
Simulation time 251603866 ps
CPU time 0.91 seconds
Started Jul 21 06:53:29 PM PDT 24
Finished Jul 21 06:53:30 PM PDT 24
Peak memory 206672 kb
Host smart-fd9b676b-5cad-4cd9-95c4-28be9a2d5cf5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3735857273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3735857273
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.225943862
Short name T1178
Test name
Test status
Simulation time 198780396 ps
CPU time 0.86 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:53:30 PM PDT 24
Peak memory 206700 kb
Host smart-13fb7000-602f-465d-bae9-22a8155f6415
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22594
3862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.225943862
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.2236420707
Short name T1661
Test name
Test status
Simulation time 5501969607 ps
CPU time 40.42 seconds
Started Jul 21 06:53:27 PM PDT 24
Finished Jul 21 06:54:08 PM PDT 24
Peak memory 206888 kb
Host smart-ee4068bf-c456-422a-8dc8-02c3c29e26b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22364
20707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.2236420707
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.1101130628
Short name T2251
Test name
Test status
Simulation time 7387988353 ps
CPU time 201.78 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:56:50 PM PDT 24
Peak memory 206892 kb
Host smart-ea521b1f-3e3b-48fa-be7b-bbd96287dfdb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1101130628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.1101130628
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1206014213
Short name T549
Test name
Test status
Simulation time 168569583 ps
CPU time 0.8 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:53:29 PM PDT 24
Peak memory 206680 kb
Host smart-8b646aa6-8aec-4226-96a4-777f0ba7a8c1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1206014213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1206014213
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.593298343
Short name T2353
Test name
Test status
Simulation time 151920775 ps
CPU time 0.75 seconds
Started Jul 21 06:53:29 PM PDT 24
Finished Jul 21 06:53:30 PM PDT 24
Peak memory 206668 kb
Host smart-7f0e0881-d5ab-4fc2-894c-aa5ceaaf3f34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59329
8343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.593298343
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.2084533508
Short name T121
Test name
Test status
Simulation time 236188858 ps
CPU time 0.86 seconds
Started Jul 21 06:53:28 PM PDT 24
Finished Jul 21 06:53:30 PM PDT 24
Peak memory 206672 kb
Host smart-72e3f9d9-88c1-4c7e-87a9-32e7f0770988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20845
33508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.2084533508
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.3943984835
Short name T424
Test name
Test status
Simulation time 227600119 ps
CPU time 0.85 seconds
Started Jul 21 06:53:33 PM PDT 24
Finished Jul 21 06:53:34 PM PDT 24
Peak memory 206644 kb
Host smart-daa236eb-bc9d-489d-887a-a03f83996c7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39439
84835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.3943984835
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.11602115
Short name T1622
Test name
Test status
Simulation time 160014754 ps
CPU time 0.76 seconds
Started Jul 21 06:53:32 PM PDT 24
Finished Jul 21 06:53:33 PM PDT 24
Peak memory 206660 kb
Host smart-2ef7fbe6-fa2c-40e9-a359-e2e853a4d1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11602
115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.11602115
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.532377663
Short name T2136
Test name
Test status
Simulation time 183906945 ps
CPU time 0.83 seconds
Started Jul 21 06:53:32 PM PDT 24
Finished Jul 21 06:53:33 PM PDT 24
Peak memory 206656 kb
Host smart-83bb4247-752f-463c-bbd7-5e7825cf3e41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53237
7663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.532377663
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.4073756706
Short name T1107
Test name
Test status
Simulation time 168041582 ps
CPU time 0.8 seconds
Started Jul 21 06:53:30 PM PDT 24
Finished Jul 21 06:53:32 PM PDT 24
Peak memory 206656 kb
Host smart-50a8b58d-689e-4861-a1ef-20868d1cfd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40737
56706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.4073756706
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.3851467685
Short name T1301
Test name
Test status
Simulation time 241604653 ps
CPU time 0.95 seconds
Started Jul 21 06:53:32 PM PDT 24
Finished Jul 21 06:53:34 PM PDT 24
Peak memory 206664 kb
Host smart-844378d9-7e32-4907-8cad-34d1a9addb34
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3851467685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.3851467685
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.2199070069
Short name T2746
Test name
Test status
Simulation time 244969658 ps
CPU time 0.94 seconds
Started Jul 21 06:53:32 PM PDT 24
Finished Jul 21 06:53:33 PM PDT 24
Peak memory 206676 kb
Host smart-4c6549dc-0500-4852-9f69-64caf2f98af1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21990
70069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.2199070069
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.3310891341
Short name T2273
Test name
Test status
Simulation time 154346993 ps
CPU time 0.75 seconds
Started Jul 21 06:53:31 PM PDT 24
Finished Jul 21 06:53:32 PM PDT 24
Peak memory 206688 kb
Host smart-e980efa2-d5bd-43e8-a064-1b51270f3a1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33108
91341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.3310891341
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2928543002
Short name T451
Test name
Test status
Simulation time 38030553 ps
CPU time 0.65 seconds
Started Jul 21 06:53:32 PM PDT 24
Finished Jul 21 06:53:34 PM PDT 24
Peak memory 206680 kb
Host smart-e3ebee06-72d8-4318-912e-9496c4638e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
43002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2928543002
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.151487102
Short name T266
Test name
Test status
Simulation time 6947912343 ps
CPU time 15.42 seconds
Started Jul 21 06:53:32 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206972 kb
Host smart-7485d61c-31f1-4c07-851f-51629352e705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15148
7102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.151487102
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1126896432
Short name T2226
Test name
Test status
Simulation time 193053355 ps
CPU time 0.9 seconds
Started Jul 21 06:53:34 PM PDT 24
Finished Jul 21 06:53:35 PM PDT 24
Peak memory 206672 kb
Host smart-68227ddc-9a9b-4714-9f25-56bb768077c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11268
96432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1126896432
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.1577752443
Short name T1828
Test name
Test status
Simulation time 249284516 ps
CPU time 0.92 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:43 PM PDT 24
Peak memory 206664 kb
Host smart-9947eb13-90ac-45c8-9dc7-21b358d8bfde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15777
52443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.1577752443
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.441670691
Short name T2541
Test name
Test status
Simulation time 11451099949 ps
CPU time 78.99 seconds
Started Jul 21 06:53:33 PM PDT 24
Finished Jul 21 06:54:52 PM PDT 24
Peak memory 206828 kb
Host smart-def22621-7f4e-4f36-b48d-5f358ea84045
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=441670691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.441670691
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.774491334
Short name T153
Test name
Test status
Simulation time 6478223732 ps
CPU time 155.57 seconds
Started Jul 21 06:53:31 PM PDT 24
Finished Jul 21 06:56:07 PM PDT 24
Peak memory 206928 kb
Host smart-4a2f8092-10e0-45c7-bf07-707cceac5235
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=774491334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.774491334
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.1115605177
Short name T1180
Test name
Test status
Simulation time 12227545271 ps
CPU time 62.05 seconds
Started Jul 21 06:53:33 PM PDT 24
Finished Jul 21 06:54:35 PM PDT 24
Peak memory 206948 kb
Host smart-2b179368-ab03-4236-836c-20ba9653b515
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1115605177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.1115605177
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.273773870
Short name T2239
Test name
Test status
Simulation time 321057385 ps
CPU time 0.97 seconds
Started Jul 21 06:53:32 PM PDT 24
Finished Jul 21 06:53:33 PM PDT 24
Peak memory 206632 kb
Host smart-254ccbe8-ec70-4b87-9d84-dc2552fb35fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27377
3870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.273773870
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.3945232919
Short name T1745
Test name
Test status
Simulation time 191201007 ps
CPU time 0.86 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:43 PM PDT 24
Peak memory 206644 kb
Host smart-15270215-0029-4357-a58d-f6f5c9984570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39452
32919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.3945232919
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.3926002955
Short name T1980
Test name
Test status
Simulation time 160643287 ps
CPU time 0.84 seconds
Started Jul 21 06:53:34 PM PDT 24
Finished Jul 21 06:53:35 PM PDT 24
Peak memory 206656 kb
Host smart-11ffc433-bbca-4cef-a515-4e62f91b880d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39260
02955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.3926002955
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2048348388
Short name T69
Test name
Test status
Simulation time 151822236 ps
CPU time 0.78 seconds
Started Jul 21 06:53:34 PM PDT 24
Finished Jul 21 06:53:35 PM PDT 24
Peak memory 206788 kb
Host smart-87253e3f-e060-4bfc-ad4b-fc80cc381663
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20483
48388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2048348388
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.451031534
Short name T187
Test name
Test status
Simulation time 308634723 ps
CPU time 1.14 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:44 PM PDT 24
Peak memory 224548 kb
Host smart-231bf67c-ad18-46e8-a835-d307977a73fb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=451031534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.451031534
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.2693324149
Short name T53
Test name
Test status
Simulation time 418478767 ps
CPU time 1.46 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:44 PM PDT 24
Peak memory 206648 kb
Host smart-c6345d41-0ea1-4ce7-8131-70976e6e1c9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26933
24149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.2693324149
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1321201428
Short name T152
Test name
Test status
Simulation time 210327654 ps
CPU time 0.93 seconds
Started Jul 21 06:53:41 PM PDT 24
Finished Jul 21 06:53:42 PM PDT 24
Peak memory 206648 kb
Host smart-06e2267d-f537-4f11-81d4-f89da706dfd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13212
01428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1321201428
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.2661833262
Short name T963
Test name
Test status
Simulation time 151168676 ps
CPU time 0.78 seconds
Started Jul 21 06:53:41 PM PDT 24
Finished Jul 21 06:53:42 PM PDT 24
Peak memory 206644 kb
Host smart-20759e25-d3fb-49c5-b329-419ac2afb965
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26618
33262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.2661833262
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.3303181559
Short name T620
Test name
Test status
Simulation time 189412021 ps
CPU time 0.76 seconds
Started Jul 21 06:53:36 PM PDT 24
Finished Jul 21 06:53:37 PM PDT 24
Peak memory 206652 kb
Host smart-8c10cbec-18b6-4067-a0fa-430933a23922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33031
81559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.3303181559
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.1033086329
Short name T2341
Test name
Test status
Simulation time 241099369 ps
CPU time 0.96 seconds
Started Jul 21 06:53:36 PM PDT 24
Finished Jul 21 06:53:37 PM PDT 24
Peak memory 206644 kb
Host smart-113a32f3-7fc2-44c0-8271-cae32c7e52e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10330
86329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.1033086329
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.1305405328
Short name T2535
Test name
Test status
Simulation time 5483456748 ps
CPU time 152.84 seconds
Started Jul 21 06:53:36 PM PDT 24
Finished Jul 21 06:56:09 PM PDT 24
Peak memory 206860 kb
Host smart-c91fdafd-70cb-4b58-a276-434009d738c9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1305405328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.1305405328
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1606529325
Short name T21
Test name
Test status
Simulation time 179057873 ps
CPU time 0.85 seconds
Started Jul 21 06:53:39 PM PDT 24
Finished Jul 21 06:53:40 PM PDT 24
Peak memory 206656 kb
Host smart-cb5fa7d8-8633-4bdc-9f36-f4846725db01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16065
29325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1606529325
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.1777635538
Short name T1674
Test name
Test status
Simulation time 215055921 ps
CPU time 0.86 seconds
Started Jul 21 06:53:38 PM PDT 24
Finished Jul 21 06:53:39 PM PDT 24
Peak memory 206672 kb
Host smart-0fcbb164-05e1-4439-953b-09c43701f527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17776
35538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.1777635538
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.572625150
Short name T1164
Test name
Test status
Simulation time 1256441720 ps
CPU time 2.4 seconds
Started Jul 21 06:53:37 PM PDT 24
Finished Jul 21 06:53:39 PM PDT 24
Peak memory 206848 kb
Host smart-5cb32e40-c779-42fc-b4b0-0fd440cd55b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57262
5150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.572625150
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.1268665984
Short name T1984
Test name
Test status
Simulation time 3308811879 ps
CPU time 26.51 seconds
Started Jul 21 06:53:37 PM PDT 24
Finished Jul 21 06:54:04 PM PDT 24
Peak memory 206908 kb
Host smart-983afa80-ac6e-4de5-b9cb-7167bc9ac86b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12686
65984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.1268665984
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.3780121104
Short name T2656
Test name
Test status
Simulation time 71548528 ps
CPU time 0.7 seconds
Started Jul 21 06:59:20 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206724 kb
Host smart-7ef2bfc2-0f51-4553-89b8-5781d8341d43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3780121104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.3780121104
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.1276304307
Short name T13
Test name
Test status
Simulation time 3683195953 ps
CPU time 4.59 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206712 kb
Host smart-50b25ae0-2859-41e9-b6ae-122dde25141b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1276304307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.1276304307
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.2608745248
Short name T1689
Test name
Test status
Simulation time 13323131900 ps
CPU time 13.64 seconds
Started Jul 21 06:59:28 PM PDT 24
Finished Jul 21 06:59:42 PM PDT 24
Peak memory 206780 kb
Host smart-155dda87-62ef-4e1f-bc03-1bfb06067805
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2608745248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.2608745248
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2128900892
Short name T739
Test name
Test status
Simulation time 23351015343 ps
CPU time 24.08 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:43 PM PDT 24
Peak memory 206756 kb
Host smart-355b09e5-3e2f-4b43-b140-dbea6ed72a35
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2128900892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2128900892
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2529093562
Short name T1547
Test name
Test status
Simulation time 171839911 ps
CPU time 0.83 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206660 kb
Host smart-11ebfb9b-6d71-4783-9df4-ddcb71f914f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25290
93562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2529093562
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.1073309709
Short name T1084
Test name
Test status
Simulation time 154244209 ps
CPU time 0.8 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206668 kb
Host smart-b376ecfb-bf2a-4020-8fc7-b23a408eb667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10733
09709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.1073309709
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.3804191436
Short name T2026
Test name
Test status
Simulation time 195221949 ps
CPU time 0.87 seconds
Started Jul 21 06:59:35 PM PDT 24
Finished Jul 21 06:59:37 PM PDT 24
Peak memory 206672 kb
Host smart-e79ef388-8347-438c-b747-6d689786af9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38041
91436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.3804191436
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.2835519098
Short name T1668
Test name
Test status
Simulation time 1332082184 ps
CPU time 3.19 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206792 kb
Host smart-d720e891-f4fb-4e3e-8b12-4e3d27a4de3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28355
19098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.2835519098
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.2373278886
Short name T1966
Test name
Test status
Simulation time 21380438413 ps
CPU time 41.03 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206964 kb
Host smart-2179709a-4dac-4d00-a5ec-981b13289bb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23732
78886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.2373278886
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.1154580109
Short name T206
Test name
Test status
Simulation time 447431209 ps
CPU time 1.43 seconds
Started Jul 21 06:59:30 PM PDT 24
Finished Jul 21 06:59:33 PM PDT 24
Peak memory 206684 kb
Host smart-d37aaf63-29dc-4f28-afa0-63b667c1253e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11545
80109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.1154580109
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.1871472454
Short name T628
Test name
Test status
Simulation time 149641632 ps
CPU time 0.81 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206664 kb
Host smart-a4662fd6-1f97-4ba1-b247-e86d38c53872
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18714
72454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.1871472454
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.811635809
Short name T1636
Test name
Test status
Simulation time 75770606 ps
CPU time 0.72 seconds
Started Jul 21 06:59:22 PM PDT 24
Finished Jul 21 06:59:24 PM PDT 24
Peak memory 206668 kb
Host smart-f7445207-3c81-4b31-a3c8-08ef70d52316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81163
5809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.811635809
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.1913449907
Short name T2079
Test name
Test status
Simulation time 764707247 ps
CPU time 1.79 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206776 kb
Host smart-820900bc-73d3-4341-841f-b8ea48b94ca0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19134
49907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.1913449907
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.2737228089
Short name T176
Test name
Test status
Simulation time 183774880 ps
CPU time 1.61 seconds
Started Jul 21 06:59:14 PM PDT 24
Finished Jul 21 06:59:18 PM PDT 24
Peak memory 206836 kb
Host smart-bb5334dc-f793-4c33-af28-71b0482d95cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27372
28089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.2737228089
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1374352977
Short name T1995
Test name
Test status
Simulation time 193279925 ps
CPU time 0.87 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:19 PM PDT 24
Peak memory 206648 kb
Host smart-e55fcc76-b2cd-47c9-9689-603338ff5817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13743
52977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1374352977
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.83274259
Short name T2050
Test name
Test status
Simulation time 136215475 ps
CPU time 0.75 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206648 kb
Host smart-440a8a62-7993-4b3f-a3b4-162b013bec44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83274
259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.83274259
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.56107143
Short name T2177
Test name
Test status
Simulation time 195110009 ps
CPU time 0.82 seconds
Started Jul 21 06:59:13 PM PDT 24
Finished Jul 21 06:59:15 PM PDT 24
Peak memory 206660 kb
Host smart-0e181d23-e2b1-4336-a200-bd699d82dd49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56107
143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.56107143
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.990550788
Short name T2550
Test name
Test status
Simulation time 9867636369 ps
CPU time 90.75 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206872 kb
Host smart-d84556fe-8c81-4ad4-a873-ac4bcd8be35b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=990550788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.990550788
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.1304919456
Short name T468
Test name
Test status
Simulation time 8828566706 ps
CPU time 33.78 seconds
Started Jul 21 06:59:30 PM PDT 24
Finished Jul 21 07:00:04 PM PDT 24
Peak memory 206920 kb
Host smart-4d0a92a0-2503-47a0-8bb1-772ae9a5d47a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13049
19456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.1304919456
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.38297619
Short name T2722
Test name
Test status
Simulation time 221357690 ps
CPU time 0.87 seconds
Started Jul 21 06:59:27 PM PDT 24
Finished Jul 21 06:59:28 PM PDT 24
Peak memory 206636 kb
Host smart-79f4714d-ecc1-4158-8ac4-1619da5ab231
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38297
619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.38297619
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1394933035
Short name T2048
Test name
Test status
Simulation time 23309071767 ps
CPU time 25.14 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:42 PM PDT 24
Peak memory 206816 kb
Host smart-bd6416ba-4c7a-4555-9824-84cb8ce720e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13949
33035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1394933035
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.2515815252
Short name T2497
Test name
Test status
Simulation time 3346500980 ps
CPU time 3.85 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206736 kb
Host smart-5f0a0f8b-bc35-44e5-9199-04e6097bbff1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25158
15252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.2515815252
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.1237236642
Short name T1311
Test name
Test status
Simulation time 5559998186 ps
CPU time 153.03 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 206892 kb
Host smart-4f0ce6b4-fb4b-41a6-a498-52262232778e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12372
36642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.1237236642
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.3866066941
Short name T456
Test name
Test status
Simulation time 3955757077 ps
CPU time 37.55 seconds
Started Jul 21 06:59:21 PM PDT 24
Finished Jul 21 07:00:00 PM PDT 24
Peak memory 206908 kb
Host smart-d7a0ec4d-b27c-4aa7-a2ea-5c5162bf6249
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3866066941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.3866066941
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.690282089
Short name T1721
Test name
Test status
Simulation time 242084799 ps
CPU time 0.9 seconds
Started Jul 21 06:59:30 PM PDT 24
Finished Jul 21 06:59:32 PM PDT 24
Peak memory 206680 kb
Host smart-dfa2c607-0beb-4085-9b79-073c5a0c8c7a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=690282089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.690282089
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.1639455707
Short name T1098
Test name
Test status
Simulation time 198709944 ps
CPU time 0.9 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:18 PM PDT 24
Peak memory 206688 kb
Host smart-e0d75f34-fb84-48be-9c9d-58265ed5cfb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16394
55707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.1639455707
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.4270152836
Short name T1783
Test name
Test status
Simulation time 6239230729 ps
CPU time 173.82 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 07:02:14 PM PDT 24
Peak memory 206840 kb
Host smart-0139d389-9834-44d4-b4d2-630d1d4af8ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
52836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.4270152836
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.621516905
Short name T1234
Test name
Test status
Simulation time 4365794124 ps
CPU time 42.01 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 07:00:03 PM PDT 24
Peak memory 206880 kb
Host smart-f9183ae2-205d-4609-ab90-f7215d737a5d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=621516905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.621516905
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.4029113073
Short name T757
Test name
Test status
Simulation time 169625881 ps
CPU time 0.81 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206628 kb
Host smart-b006bf82-1863-4b15-af34-9f5f1819987c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4029113073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.4029113073
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.3821032022
Short name T1647
Test name
Test status
Simulation time 215608262 ps
CPU time 0.84 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206660 kb
Host smart-3ca0883b-460d-4875-9a11-5b50d485a2f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38210
32022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.3821032022
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.2246962971
Short name T102
Test name
Test status
Simulation time 180450940 ps
CPU time 0.82 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206692 kb
Host smart-1432e9f0-980c-4e39-817e-7eb937eada96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22469
62971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.2246962971
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1587014434
Short name T915
Test name
Test status
Simulation time 197759955 ps
CPU time 0.88 seconds
Started Jul 21 06:59:16 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206688 kb
Host smart-75b23fad-a0cc-4fd2-8732-807eb7889f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15870
14434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1587014434
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.319408888
Short name T493
Test name
Test status
Simulation time 172290963 ps
CPU time 0.83 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206680 kb
Host smart-feed7059-35aa-49b2-8451-d9983f1f381a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31940
8888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.319408888
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3533515731
Short name T744
Test name
Test status
Simulation time 174247116 ps
CPU time 0.79 seconds
Started Jul 21 06:59:21 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206704 kb
Host smart-f759611b-2f3e-4f24-9679-a3e2d7e27067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35335
15731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3533515731
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.1204882316
Short name T810
Test name
Test status
Simulation time 190160297 ps
CPU time 0.81 seconds
Started Jul 21 06:59:31 PM PDT 24
Finished Jul 21 06:59:32 PM PDT 24
Peak memory 206684 kb
Host smart-07d8234b-ed2d-44cc-b1bc-446217d058d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12048
82316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.1204882316
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.4013703397
Short name T2455
Test name
Test status
Simulation time 206329495 ps
CPU time 0.92 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206628 kb
Host smart-2388885d-a5a5-4db2-b83b-1cda061de989
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4013703397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.4013703397
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.725882037
Short name T2429
Test name
Test status
Simulation time 158350987 ps
CPU time 0.81 seconds
Started Jul 21 06:59:19 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206680 kb
Host smart-f9cb3119-17db-4313-86fb-6a74a2660766
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72588
2037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.725882037
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3613631223
Short name T522
Test name
Test status
Simulation time 86801960 ps
CPU time 0.73 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206668 kb
Host smart-17487378-ece8-47a8-95cf-275a69a98acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36136
31223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3613631223
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.3747152471
Short name T2238
Test name
Test status
Simulation time 16323136807 ps
CPU time 41.5 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 07:00:03 PM PDT 24
Peak memory 206916 kb
Host smart-fbae1d3c-83e6-4f13-9c41-81905280aee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37471
52471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.3747152471
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.938259494
Short name T519
Test name
Test status
Simulation time 189104927 ps
CPU time 0.87 seconds
Started Jul 21 06:59:15 PM PDT 24
Finished Jul 21 06:59:17 PM PDT 24
Peak memory 206668 kb
Host smart-0719c984-6af1-49db-bf09-fbe48bd94085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93825
9494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.938259494
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.4103734603
Short name T2526
Test name
Test status
Simulation time 265655004 ps
CPU time 0.9 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206676 kb
Host smart-d5e88863-ebb2-4c16-9dac-757d1c4b6168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41037
34603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.4103734603
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2571340317
Short name T2411
Test name
Test status
Simulation time 250132905 ps
CPU time 0.86 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:20 PM PDT 24
Peak memory 206668 kb
Host smart-37989d57-0433-4026-9ebc-75669579e501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25713
40317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2571340317
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1092339969
Short name T2037
Test name
Test status
Simulation time 193860431 ps
CPU time 0.86 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206696 kb
Host smart-1ef9bbf3-ae8a-4d18-8e1e-38d21bb67ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10923
39969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1092339969
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.1043770454
Short name T1617
Test name
Test status
Simulation time 154709475 ps
CPU time 0.82 seconds
Started Jul 21 06:59:30 PM PDT 24
Finished Jul 21 06:59:32 PM PDT 24
Peak memory 206660 kb
Host smart-481015a3-5454-49fb-bcb6-4bd6c6d3bc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10437
70454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.1043770454
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.59225793
Short name T2539
Test name
Test status
Simulation time 172545784 ps
CPU time 0.8 seconds
Started Jul 21 06:59:30 PM PDT 24
Finished Jul 21 06:59:32 PM PDT 24
Peak memory 206664 kb
Host smart-2a588154-0d83-4c0b-a422-62b37bd53d5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59225
793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.59225793
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.3691073347
Short name T410
Test name
Test status
Simulation time 185358254 ps
CPU time 0.84 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206660 kb
Host smart-34608636-6d0a-4c78-84a5-bfad7b6ad0ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36910
73347 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.3691073347
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2741654021
Short name T2614
Test name
Test status
Simulation time 194619015 ps
CPU time 0.88 seconds
Started Jul 21 06:59:17 PM PDT 24
Finished Jul 21 06:59:21 PM PDT 24
Peak memory 206660 kb
Host smart-d87dd657-dd8a-48f9-80a8-e92a7e7d91fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27416
54021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2741654021
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2564943834
Short name T376
Test name
Test status
Simulation time 7122764706 ps
CPU time 68.49 seconds
Started Jul 21 06:59:30 PM PDT 24
Finished Jul 21 07:00:39 PM PDT 24
Peak memory 206884 kb
Host smart-6f15deb2-b107-4f2f-82ba-bed87fab4caa
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2564943834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2564943834
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.1183981878
Short name T2051
Test name
Test status
Simulation time 147070948 ps
CPU time 0.76 seconds
Started Jul 21 06:59:18 PM PDT 24
Finished Jul 21 06:59:22 PM PDT 24
Peak memory 206668 kb
Host smart-7c4a42c1-b991-4a8e-b3da-2d0887ce0203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11839
81878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.1183981878
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.227219286
Short name T2382
Test name
Test status
Simulation time 180241314 ps
CPU time 0.83 seconds
Started Jul 21 06:59:22 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206640 kb
Host smart-c49fe0d7-f566-4286-be02-7ec76147b1a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22721
9286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.227219286
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.1017020158
Short name T1664
Test name
Test status
Simulation time 389975838 ps
CPU time 1.3 seconds
Started Jul 21 06:59:24 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 206660 kb
Host smart-861b8479-a793-4ca9-b152-6c2ce2341594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10170
20158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.1017020158
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.2933999142
Short name T638
Test name
Test status
Simulation time 4594538656 ps
CPU time 32.93 seconds
Started Jul 21 06:59:24 PM PDT 24
Finished Jul 21 06:59:58 PM PDT 24
Peak memory 206880 kb
Host smart-1c1d23bf-79b7-46d7-9adb-d84844cbb84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29339
99142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.2933999142
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.1143071105
Short name T2024
Test name
Test status
Simulation time 47843875 ps
CPU time 0.65 seconds
Started Jul 21 06:59:45 PM PDT 24
Finished Jul 21 06:59:46 PM PDT 24
Peak memory 206732 kb
Host smart-720ca1e6-aa39-410b-bac2-a47e85a99676
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1143071105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.1143071105
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.1234456631
Short name T1730
Test name
Test status
Simulation time 4472727705 ps
CPU time 5.57 seconds
Started Jul 21 06:59:20 PM PDT 24
Finished Jul 21 06:59:28 PM PDT 24
Peak memory 206936 kb
Host smart-796f0182-481a-4cf5-b370-607d588fee57
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1234456631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.1234456631
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.689750916
Short name T1813
Test name
Test status
Simulation time 13382034238 ps
CPU time 12.23 seconds
Started Jul 21 06:59:20 PM PDT 24
Finished Jul 21 06:59:34 PM PDT 24
Peak memory 206928 kb
Host smart-b4b0d840-c919-4477-9ae2-42d99b61c201
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=689750916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.689750916
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.2627236001
Short name T1804
Test name
Test status
Simulation time 23330468410 ps
CPU time 24.08 seconds
Started Jul 21 06:59:21 PM PDT 24
Finished Jul 21 06:59:47 PM PDT 24
Peak memory 206904 kb
Host smart-7b918e96-2df4-43ba-8b67-bd6cf5989815
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2627236001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.2627236001
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.2579641659
Short name T2307
Test name
Test status
Simulation time 154630704 ps
CPU time 0.74 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206684 kb
Host smart-f5dc7e5b-3107-48ca-abf5-d4d1317f39d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25796
41659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.2579641659
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.2814191653
Short name T373
Test name
Test status
Simulation time 154251445 ps
CPU time 0.76 seconds
Started Jul 21 06:59:32 PM PDT 24
Finished Jul 21 06:59:33 PM PDT 24
Peak memory 206660 kb
Host smart-a3fffa4c-c394-4332-ab54-092800bbc8e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28141
91653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.2814191653
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.2096806971
Short name T471
Test name
Test status
Simulation time 521823764 ps
CPU time 1.53 seconds
Started Jul 21 06:59:23 PM PDT 24
Finished Jul 21 06:59:25 PM PDT 24
Peak memory 206772 kb
Host smart-112501f1-7947-40fc-a402-27820545af11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20968
06971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.2096806971
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.4191274010
Short name T1063
Test name
Test status
Simulation time 424720787 ps
CPU time 1.22 seconds
Started Jul 21 06:59:19 PM PDT 24
Finished Jul 21 06:59:23 PM PDT 24
Peak memory 206684 kb
Host smart-1d1f64df-24ab-4304-90fc-77d0e2ea4033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41912
74010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.4191274010
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.1184127662
Short name T1538
Test name
Test status
Simulation time 15237629043 ps
CPU time 29.48 seconds
Started Jul 21 06:59:20 PM PDT 24
Finished Jul 21 06:59:52 PM PDT 24
Peak memory 206896 kb
Host smart-cddf4992-ac60-4f3f-a050-ecbc4c268f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11841
27662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.1184127662
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.639141421
Short name T2277
Test name
Test status
Simulation time 379766650 ps
CPU time 1.38 seconds
Started Jul 21 06:59:26 PM PDT 24
Finished Jul 21 06:59:28 PM PDT 24
Peak memory 206688 kb
Host smart-6ea4fb40-6273-4092-b16c-24f3248b3976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63914
1421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.639141421
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.380325802
Short name T1467
Test name
Test status
Simulation time 147958295 ps
CPU time 0.75 seconds
Started Jul 21 06:59:27 PM PDT 24
Finished Jul 21 06:59:28 PM PDT 24
Peak memory 206672 kb
Host smart-bcf616a0-79e2-4333-bca1-c9cf9d313133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38032
5802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.380325802
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.3351323803
Short name T1119
Test name
Test status
Simulation time 31985338 ps
CPU time 0.66 seconds
Started Jul 21 06:59:32 PM PDT 24
Finished Jul 21 06:59:33 PM PDT 24
Peak memory 206652 kb
Host smart-3316e7de-96b1-429b-b59c-51607dbd19f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
23803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.3351323803
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.2762887109
Short name T936
Test name
Test status
Simulation time 851215584 ps
CPU time 1.96 seconds
Started Jul 21 06:59:32 PM PDT 24
Finished Jul 21 06:59:35 PM PDT 24
Peak memory 206752 kb
Host smart-545dcf2c-ff46-4495-a80c-dd0de6cf6186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27628
87109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.2762887109
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.3265735078
Short name T747
Test name
Test status
Simulation time 272968372 ps
CPU time 1.92 seconds
Started Jul 21 06:59:25 PM PDT 24
Finished Jul 21 06:59:28 PM PDT 24
Peak memory 206776 kb
Host smart-f28f8b2a-1e64-4e74-8a7a-0437b09d5f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32657
35078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.3265735078
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.13075792
Short name T99
Test name
Test status
Simulation time 191019340 ps
CPU time 0.84 seconds
Started Jul 21 06:59:25 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 206660 kb
Host smart-4ecf2b7b-3854-411b-b6c8-1a50aefd1111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13075
792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.13075792
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.1559077677
Short name T1870
Test name
Test status
Simulation time 153871860 ps
CPU time 0.75 seconds
Started Jul 21 06:59:34 PM PDT 24
Finished Jul 21 06:59:36 PM PDT 24
Peak memory 206660 kb
Host smart-a050ca3e-8ba0-4841-936c-1244fa72289b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15590
77677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.1559077677
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.3988585410
Short name T1120
Test name
Test status
Simulation time 164707072 ps
CPU time 0.85 seconds
Started Jul 21 06:59:25 PM PDT 24
Finished Jul 21 06:59:27 PM PDT 24
Peak memory 206660 kb
Host smart-334c467d-0e8c-477e-848f-1a2a1bd4a127
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39885
85410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.3988585410
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_invalid_sync.3664556075
Short name T1451
Test name
Test status
Simulation time 5548756658 ps
CPU time 159.07 seconds
Started Jul 21 06:59:31 PM PDT 24
Finished Jul 21 07:02:10 PM PDT 24
Peak memory 206932 kb
Host smart-d151269c-d0f6-4929-995d-417f76eb5079
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3664556075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_invalid_sync.3664556075
Directory /workspace/41.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.1184705338
Short name T80
Test name
Test status
Simulation time 7912658198 ps
CPU time 24.25 seconds
Started Jul 21 06:59:47 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206968 kb
Host smart-329ae2ba-6092-4fe3-98af-08d24c5861b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11847
05338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.1184705338
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3424857859
Short name T956
Test name
Test status
Simulation time 163966252 ps
CPU time 0.84 seconds
Started Jul 21 06:59:25 PM PDT 24
Finished Jul 21 06:59:26 PM PDT 24
Peak memory 206696 kb
Host smart-2b5e2985-4c2c-4345-ac62-99e6c5d3fdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34248
57859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3424857859
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.4209931121
Short name T2258
Test name
Test status
Simulation time 23304306634 ps
CPU time 27.85 seconds
Started Jul 21 06:59:39 PM PDT 24
Finished Jul 21 07:00:07 PM PDT 24
Peak memory 206816 kb
Host smart-6ce38aa7-820a-4a76-ac93-e56ffd9509cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42099
31121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.4209931121
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.1532987681
Short name T2125
Test name
Test status
Simulation time 3362583923 ps
CPU time 4 seconds
Started Jul 21 06:59:30 PM PDT 24
Finished Jul 21 06:59:34 PM PDT 24
Peak memory 206756 kb
Host smart-c46d8ca9-091b-49a8-993b-bf028a9dcb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15329
87681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.1532987681
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.2257920089
Short name T1367
Test name
Test status
Simulation time 5227025831 ps
CPU time 145.85 seconds
Started Jul 21 06:59:26 PM PDT 24
Finished Jul 21 07:01:57 PM PDT 24
Peak memory 206992 kb
Host smart-51895570-f7d1-4b2b-bc46-7ef3d7bed08b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22579
20089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.2257920089
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2965183069
Short name T2274
Test name
Test status
Simulation time 3825759398 ps
CPU time 35.55 seconds
Started Jul 21 06:59:24 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206876 kb
Host smart-a2a483a3-ebc8-4e89-b268-32e32efa3236
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2965183069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2965183069
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.4056967533
Short name T914
Test name
Test status
Simulation time 288947537 ps
CPU time 0.95 seconds
Started Jul 21 06:59:25 PM PDT 24
Finished Jul 21 06:59:27 PM PDT 24
Peak memory 206680 kb
Host smart-7d8de6c0-7dc3-4397-9b90-c6eddf3dd924
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4056967533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.4056967533
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3064267590
Short name T2734
Test name
Test status
Simulation time 203937490 ps
CPU time 0.93 seconds
Started Jul 21 06:59:48 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206688 kb
Host smart-a69342b8-2ad1-414a-a563-7439a283e55e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30642
67590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3064267590
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.2202897572
Short name T2179
Test name
Test status
Simulation time 4433610776 ps
CPU time 34.35 seconds
Started Jul 21 06:59:25 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206996 kb
Host smart-f7bdfc8e-cd3f-4354-998a-4664b95de6a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22028
97572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.2202897572
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.327876684
Short name T1080
Test name
Test status
Simulation time 3832561912 ps
CPU time 37.27 seconds
Started Jul 21 06:59:38 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206856 kb
Host smart-9f0e2161-1848-4c46-9219-c7b59bab9532
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=327876684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.327876684
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.946690561
Short name T588
Test name
Test status
Simulation time 154883763 ps
CPU time 0.82 seconds
Started Jul 21 06:59:29 PM PDT 24
Finished Jul 21 06:59:30 PM PDT 24
Peak memory 206676 kb
Host smart-97a76bee-96d4-433f-ad6a-40eabec1bac8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=946690561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.946690561
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.2778761873
Short name T2727
Test name
Test status
Simulation time 171058206 ps
CPU time 0.75 seconds
Started Jul 21 06:59:32 PM PDT 24
Finished Jul 21 06:59:33 PM PDT 24
Peak memory 206676 kb
Host smart-f4d838a1-58f4-4952-a55d-6e148a33d6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27787
61873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.2778761873
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1187575668
Short name T119
Test name
Test status
Simulation time 222225270 ps
CPU time 0.84 seconds
Started Jul 21 06:59:52 PM PDT 24
Finished Jul 21 06:59:53 PM PDT 24
Peak memory 206564 kb
Host smart-78ba7e92-40ff-476b-82a3-498284fd38da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11875
75668 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1187575668
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1558061277
Short name T1924
Test name
Test status
Simulation time 188111714 ps
CPU time 0.81 seconds
Started Jul 21 06:59:27 PM PDT 24
Finished Jul 21 06:59:29 PM PDT 24
Peak memory 206652 kb
Host smart-be247ec0-ca48-4d32-b3f4-e4f6b2277cff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15580
61277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1558061277
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.3488173978
Short name T2448
Test name
Test status
Simulation time 174171555 ps
CPU time 0.81 seconds
Started Jul 21 06:59:35 PM PDT 24
Finished Jul 21 06:59:37 PM PDT 24
Peak memory 206696 kb
Host smart-6ec0f575-28f2-42ae-8a89-7aed9b116953
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34881
73978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.3488173978
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.3048078543
Short name T297
Test name
Test status
Simulation time 197620518 ps
CPU time 0.83 seconds
Started Jul 21 06:59:36 PM PDT 24
Finished Jul 21 06:59:38 PM PDT 24
Peak memory 206636 kb
Host smart-2b6d09c6-2c18-46f5-aa62-7cda680ded86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30480
78543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.3048078543
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.1727870446
Short name T484
Test name
Test status
Simulation time 156984050 ps
CPU time 0.77 seconds
Started Jul 21 06:59:26 PM PDT 24
Finished Jul 21 06:59:27 PM PDT 24
Peak memory 206784 kb
Host smart-136fe90b-9fb3-4559-9672-09f0dd44d820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17278
70446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.1727870446
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.4202838091
Short name T984
Test name
Test status
Simulation time 207814798 ps
CPU time 0.85 seconds
Started Jul 21 06:59:25 PM PDT 24
Finished Jul 21 06:59:27 PM PDT 24
Peak memory 206680 kb
Host smart-ef9b01ac-9e8e-4f1b-b74b-613da4c1560e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4202838091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.4202838091
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.3269415979
Short name T2609
Test name
Test status
Simulation time 139839909 ps
CPU time 0.78 seconds
Started Jul 21 06:59:26 PM PDT 24
Finished Jul 21 06:59:27 PM PDT 24
Peak memory 206652 kb
Host smart-56c68c92-5a2d-4bb8-a17b-e130f987a74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32694
15979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.3269415979
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.752959380
Short name T1128
Test name
Test status
Simulation time 45082456 ps
CPU time 0.68 seconds
Started Jul 21 06:59:26 PM PDT 24
Finished Jul 21 06:59:27 PM PDT 24
Peak memory 206652 kb
Host smart-e1c1556b-7b27-456a-a99f-4644c7988074
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75295
9380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.752959380
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.1537956040
Short name T267
Test name
Test status
Simulation time 8823420664 ps
CPU time 19.79 seconds
Started Jul 21 06:59:28 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206936 kb
Host smart-14e5c041-e09e-401f-b567-f43fd18f0f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15379
56040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.1537956040
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.615311740
Short name T1334
Test name
Test status
Simulation time 224660479 ps
CPU time 0.89 seconds
Started Jul 21 06:59:36 PM PDT 24
Finished Jul 21 06:59:38 PM PDT 24
Peak memory 206660 kb
Host smart-9ca6320c-9ba4-493a-a582-e7cc41b2d311
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61531
1740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.615311740
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.1396448030
Short name T1521
Test name
Test status
Simulation time 221124884 ps
CPU time 0.9 seconds
Started Jul 21 06:59:42 PM PDT 24
Finished Jul 21 06:59:43 PM PDT 24
Peak memory 206632 kb
Host smart-0e1c3072-bb79-40ff-893c-22dd152e6ccb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13964
48030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.1396448030
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3135408511
Short name T2139
Test name
Test status
Simulation time 287413452 ps
CPU time 0.91 seconds
Started Jul 21 06:59:51 PM PDT 24
Finished Jul 21 06:59:52 PM PDT 24
Peak memory 206628 kb
Host smart-9c88a48d-7aab-4c75-9999-289a8ddea72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31354
08511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3135408511
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.3948790343
Short name T2053
Test name
Test status
Simulation time 160822817 ps
CPU time 0.8 seconds
Started Jul 21 06:59:42 PM PDT 24
Finished Jul 21 06:59:44 PM PDT 24
Peak memory 206672 kb
Host smart-5b626282-e4ae-46df-b846-6986eb515c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
90343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.3948790343
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4260012654
Short name T2423
Test name
Test status
Simulation time 244024106 ps
CPU time 0.92 seconds
Started Jul 21 06:59:43 PM PDT 24
Finished Jul 21 06:59:45 PM PDT 24
Peak memory 206640 kb
Host smart-719e68fa-a651-45fa-8408-e8dec364fd6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42600
12654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4260012654
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3341222224
Short name T2061
Test name
Test status
Simulation time 156250393 ps
CPU time 0.82 seconds
Started Jul 21 06:59:38 PM PDT 24
Finished Jul 21 06:59:39 PM PDT 24
Peak memory 206668 kb
Host smart-49978aa0-fb82-4aac-8d36-f85ca4f22528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33412
22224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3341222224
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.1934828581
Short name T348
Test name
Test status
Simulation time 154541232 ps
CPU time 0.76 seconds
Started Jul 21 06:59:48 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206668 kb
Host smart-bd221b1a-e465-4b7b-a6d2-8c9ee1a42285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19348
28581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.1934828581
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.1181355047
Short name T2371
Test name
Test status
Simulation time 263738725 ps
CPU time 1.02 seconds
Started Jul 21 06:59:49 PM PDT 24
Finished Jul 21 06:59:50 PM PDT 24
Peak memory 206676 kb
Host smart-80a0c037-c431-487f-8d26-a5ae11b97af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11813
55047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.1181355047
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.3883096410
Short name T2073
Test name
Test status
Simulation time 5277899743 ps
CPU time 50.08 seconds
Started Jul 21 06:59:46 PM PDT 24
Finished Jul 21 07:00:36 PM PDT 24
Peak memory 206896 kb
Host smart-005d8b80-28ba-4499-a8d5-a3a9051dd061
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3883096410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.3883096410
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.918507483
Short name T1785
Test name
Test status
Simulation time 156283767 ps
CPU time 0.75 seconds
Started Jul 21 06:59:40 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206668 kb
Host smart-579a9297-c898-42d3-9630-ef2db37437df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91850
7483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.918507483
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.684402933
Short name T1823
Test name
Test status
Simulation time 141913533 ps
CPU time 0.77 seconds
Started Jul 21 06:59:37 PM PDT 24
Finished Jul 21 06:59:38 PM PDT 24
Peak memory 206644 kb
Host smart-ba287d68-f8e2-42c7-8c08-b3c3cf6d9445
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68440
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.684402933
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.2197268182
Short name T2565
Test name
Test status
Simulation time 434055071 ps
CPU time 1.19 seconds
Started Jul 21 06:59:44 PM PDT 24
Finished Jul 21 06:59:46 PM PDT 24
Peak memory 206672 kb
Host smart-c9357ba2-fe0b-4d32-b714-f4044be09e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21972
68182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.2197268182
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.359839881
Short name T143
Test name
Test status
Simulation time 3116276255 ps
CPU time 86.96 seconds
Started Jul 21 06:59:32 PM PDT 24
Finished Jul 21 07:01:00 PM PDT 24
Peak memory 206900 kb
Host smart-60b540f3-7fb3-40b6-90c4-79426e19cd44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35983
9881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.359839881
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.2739672939
Short name T180
Test name
Test status
Simulation time 37942550 ps
CPU time 0.67 seconds
Started Jul 21 06:59:54 PM PDT 24
Finished Jul 21 06:59:55 PM PDT 24
Peak memory 206588 kb
Host smart-dea45813-311b-496d-bdbd-049d9c98bd90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2739672939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.2739672939
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1384703321
Short name T1155
Test name
Test status
Simulation time 4349004374 ps
CPU time 4.7 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:04 PM PDT 24
Peak memory 206892 kb
Host smart-9aea14a6-87b9-4c40-a3ba-9df9a6620736
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1384703321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1384703321
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2169970346
Short name T2278
Test name
Test status
Simulation time 13430121003 ps
CPU time 13.51 seconds
Started Jul 21 06:59:42 PM PDT 24
Finished Jul 21 06:59:56 PM PDT 24
Peak memory 206908 kb
Host smart-48057bd0-a84e-4cf4-b260-dcbd055d45b2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2169970346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2169970346
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.2017300055
Short name T706
Test name
Test status
Simulation time 23474868129 ps
CPU time 29.22 seconds
Started Jul 21 06:59:35 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206904 kb
Host smart-93b3578c-f018-4f82-8810-734e3fceedb4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2017300055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.2017300055
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.1576710315
Short name T1926
Test name
Test status
Simulation time 199436063 ps
CPU time 0.82 seconds
Started Jul 21 06:59:41 PM PDT 24
Finished Jul 21 06:59:42 PM PDT 24
Peak memory 206700 kb
Host smart-11c98c46-cf45-43e1-b552-b85161e00930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15767
10315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.1576710315
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.3870906447
Short name T541
Test name
Test status
Simulation time 159131725 ps
CPU time 0.79 seconds
Started Jul 21 06:59:43 PM PDT 24
Finished Jul 21 06:59:45 PM PDT 24
Peak memory 206644 kb
Host smart-d49de8fd-f97b-4e67-bf00-9da91a478d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38709
06447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.3870906447
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.1273492766
Short name T1358
Test name
Test status
Simulation time 391123885 ps
CPU time 1.22 seconds
Started Jul 21 06:59:40 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206664 kb
Host smart-b78283df-db47-437b-8f62-decfb1dd48f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12734
92766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.1273492766
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3003291132
Short name T2240
Test name
Test status
Simulation time 1243170502 ps
CPU time 2.91 seconds
Started Jul 21 06:59:48 PM PDT 24
Finished Jul 21 06:59:51 PM PDT 24
Peak memory 206836 kb
Host smart-d64096df-d563-436a-a30d-719943cf16a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30032
91132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3003291132
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.3743101082
Short name T65
Test name
Test status
Simulation time 9630632993 ps
CPU time 19.33 seconds
Started Jul 21 06:59:54 PM PDT 24
Finished Jul 21 07:00:14 PM PDT 24
Peak memory 206952 kb
Host smart-07a123de-c5a1-4677-80b0-e2670b79d3af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37431
01082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.3743101082
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.3705083480
Short name T1682
Test name
Test status
Simulation time 327604908 ps
CPU time 1.23 seconds
Started Jul 21 06:59:42 PM PDT 24
Finished Jul 21 06:59:43 PM PDT 24
Peak memory 206668 kb
Host smart-36424ec0-2b3f-46dd-9b32-fd90cd63b3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37050
83480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.3705083480
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.3761753754
Short name T690
Test name
Test status
Simulation time 155459946 ps
CPU time 0.75 seconds
Started Jul 21 06:59:40 PM PDT 24
Finished Jul 21 06:59:42 PM PDT 24
Peak memory 206680 kb
Host smart-1ed0f61b-a0ef-42a0-9181-c9f78c40a76d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37617
53754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.3761753754
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.1724319518
Short name T1842
Test name
Test status
Simulation time 30437383 ps
CPU time 0.63 seconds
Started Jul 21 06:59:47 PM PDT 24
Finished Jul 21 06:59:48 PM PDT 24
Peak memory 206700 kb
Host smart-a7b8a703-b395-4c0b-bbe1-90783baf59a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
19518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.1724319518
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.1990395106
Short name T818
Test name
Test status
Simulation time 909545067 ps
CPU time 2.18 seconds
Started Jul 21 06:59:46 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206808 kb
Host smart-a17a628e-030e-4ef5-9651-08e8dec95255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19903
95106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.1990395106
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.3482503197
Short name T2080
Test name
Test status
Simulation time 247549391 ps
CPU time 1.72 seconds
Started Jul 21 06:59:41 PM PDT 24
Finished Jul 21 06:59:44 PM PDT 24
Peak memory 206804 kb
Host smart-44e08374-633c-4fe4-8ded-45c2d1fd996b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34825
03197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.3482503197
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3322869431
Short name T962
Test name
Test status
Simulation time 190496100 ps
CPU time 0.86 seconds
Started Jul 21 06:59:44 PM PDT 24
Finished Jul 21 06:59:45 PM PDT 24
Peak memory 206676 kb
Host smart-69a36fd3-d19c-4138-b53d-0cf3f1419755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33228
69431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3322869431
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.2278849797
Short name T1598
Test name
Test status
Simulation time 152880752 ps
CPU time 0.78 seconds
Started Jul 21 06:59:41 PM PDT 24
Finished Jul 21 06:59:43 PM PDT 24
Peak memory 206668 kb
Host smart-232c2156-1609-426d-9b11-7dad4204a308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22788
49797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.2278849797
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.72462046
Short name T1930
Test name
Test status
Simulation time 190233403 ps
CPU time 0.87 seconds
Started Jul 21 06:59:39 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206668 kb
Host smart-86428062-663f-4c97-a6e3-4fb969a1a377
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72462
046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.72462046
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_invalid_sync.2753221924
Short name T627
Test name
Test status
Simulation time 7375865545 ps
CPU time 202.51 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 07:03:20 PM PDT 24
Peak memory 206908 kb
Host smart-ef8ae4c6-8cd4-4afb-9a2b-7ee190b40114
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2753221924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_invalid_sync.2753221924
Directory /workspace/42.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.1013537765
Short name T772
Test name
Test status
Simulation time 9203776126 ps
CPU time 32.96 seconds
Started Jul 21 06:59:44 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206888 kb
Host smart-09543835-ffa9-47a7-9e7a-96d7293a404c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10135
37765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.1013537765
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.428521253
Short name T1192
Test name
Test status
Simulation time 191729965 ps
CPU time 0.91 seconds
Started Jul 21 06:59:52 PM PDT 24
Finished Jul 21 06:59:54 PM PDT 24
Peak memory 206664 kb
Host smart-276fc6a1-2f61-4b1e-8730-44861d28d255
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42852
1253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.428521253
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.985486781
Short name T1406
Test name
Test status
Simulation time 23315376271 ps
CPU time 27.89 seconds
Started Jul 21 06:59:39 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206792 kb
Host smart-e8e0b525-9e42-4580-a658-73b2cd346c2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98548
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.985486781
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.1507046792
Short name T576
Test name
Test status
Simulation time 3338659143 ps
CPU time 3.95 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 06:59:58 PM PDT 24
Peak memory 206732 kb
Host smart-cbb65639-efdd-4bf3-a271-76ca25c7f5a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15070
46792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.1507046792
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.593285676
Short name T137
Test name
Test status
Simulation time 11405015308 ps
CPU time 113.61 seconds
Started Jul 21 06:59:39 PM PDT 24
Finished Jul 21 07:01:33 PM PDT 24
Peak memory 206972 kb
Host smart-b82e6cdd-b173-4ee0-a2ac-548f9b5436ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59328
5676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.593285676
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.1647394510
Short name T1293
Test name
Test status
Simulation time 3879188200 ps
CPU time 34.66 seconds
Started Jul 21 06:59:42 PM PDT 24
Finished Jul 21 07:00:17 PM PDT 24
Peak memory 206904 kb
Host smart-3b481ddf-24c3-4594-8267-3c7593846f0f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1647394510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.1647394510
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1682180872
Short name T360
Test name
Test status
Simulation time 254130054 ps
CPU time 0.92 seconds
Started Jul 21 06:59:55 PM PDT 24
Finished Jul 21 06:59:57 PM PDT 24
Peak memory 206680 kb
Host smart-a8d8f5f2-bef7-431e-a9ef-2143a25f0672
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1682180872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1682180872
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.500163144
Short name T2694
Test name
Test status
Simulation time 200978406 ps
CPU time 0.95 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 06:59:58 PM PDT 24
Peak memory 206288 kb
Host smart-760b91f0-4da7-4032-9284-58416ec9579d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50016
3144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.500163144
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.1014236718
Short name T1335
Test name
Test status
Simulation time 4882214269 ps
CPU time 37.74 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 07:00:35 PM PDT 24
Peak memory 206908 kb
Host smart-a6054786-8c84-40f9-b5a5-6610b1017675
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10142
36718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.1014236718
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.3497853626
Short name T394
Test name
Test status
Simulation time 7404341270 ps
CPU time 207.11 seconds
Started Jul 21 06:59:42 PM PDT 24
Finished Jul 21 07:03:10 PM PDT 24
Peak memory 206868 kb
Host smart-435dc15e-d56c-43ad-b2f5-ad5564d43524
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3497853626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.3497853626
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.3504264737
Short name T838
Test name
Test status
Simulation time 217258261 ps
CPU time 0.84 seconds
Started Jul 21 06:59:45 PM PDT 24
Finished Jul 21 06:59:46 PM PDT 24
Peak memory 206692 kb
Host smart-f45cfc1a-cd2d-413b-b3ea-0243b57d07dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3504264737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.3504264737
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.702278187
Short name T913
Test name
Test status
Simulation time 182303564 ps
CPU time 0.82 seconds
Started Jul 21 06:59:50 PM PDT 24
Finished Jul 21 06:59:52 PM PDT 24
Peak memory 206684 kb
Host smart-7b70e3b1-62cf-417d-b554-9dc81dae5a17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70227
8187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.702278187
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.1239378436
Short name T116
Test name
Test status
Simulation time 177537149 ps
CPU time 0.84 seconds
Started Jul 21 06:59:47 PM PDT 24
Finished Jul 21 06:59:48 PM PDT 24
Peak memory 206656 kb
Host smart-124f759d-a8c1-4400-813f-5fde79f11334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12393
78436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.1239378436
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.887479742
Short name T1019
Test name
Test status
Simulation time 174498614 ps
CPU time 0.84 seconds
Started Jul 21 06:59:49 PM PDT 24
Finished Jul 21 06:59:50 PM PDT 24
Peak memory 206660 kb
Host smart-3a86a1c2-6ec8-41f4-b21b-18ed0511da1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88747
9742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.887479742
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.708850672
Short name T370
Test name
Test status
Simulation time 240220242 ps
CPU time 0.92 seconds
Started Jul 21 06:59:46 PM PDT 24
Finished Jul 21 06:59:47 PM PDT 24
Peak memory 206664 kb
Host smart-c0d7e255-ed2f-48bb-8758-4e187a0be5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70885
0672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.708850672
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.2831442404
Short name T750
Test name
Test status
Simulation time 174317940 ps
CPU time 0.82 seconds
Started Jul 21 06:59:49 PM PDT 24
Finished Jul 21 06:59:50 PM PDT 24
Peak memory 206636 kb
Host smart-1387cc74-20cd-4379-b9fa-01d20dd42563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28314
42404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.2831442404
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.2415577536
Short name T1132
Test name
Test status
Simulation time 150117447 ps
CPU time 0.78 seconds
Started Jul 21 06:59:41 PM PDT 24
Finished Jul 21 06:59:42 PM PDT 24
Peak memory 206692 kb
Host smart-680a702b-4240-4bf5-8719-6ac4deff202d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24155
77536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.2415577536
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3589531759
Short name T954
Test name
Test status
Simulation time 225313896 ps
CPU time 0.89 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206684 kb
Host smart-cfd1aaf8-c01d-4726-854c-d9fad75e2a4e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3589531759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3589531759
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.729383835
Short name T1706
Test name
Test status
Simulation time 150421131 ps
CPU time 0.8 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:03 PM PDT 24
Peak memory 206676 kb
Host smart-32f1e912-4efb-4976-97c3-c357851a0d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72938
3835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.729383835
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.1098592999
Short name T1026
Test name
Test status
Simulation time 54081575 ps
CPU time 0.68 seconds
Started Jul 21 06:59:54 PM PDT 24
Finished Jul 21 06:59:55 PM PDT 24
Peak memory 206676 kb
Host smart-5b290187-6be5-4f9f-947c-a4ff30a6253c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10985
92999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.1098592999
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.3241538816
Short name T612
Test name
Test status
Simulation time 12462980758 ps
CPU time 26.86 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 07:00:21 PM PDT 24
Peak memory 206984 kb
Host smart-7e8ae0d8-c84a-451f-acb1-6b94ac881796
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32415
38816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.3241538816
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.3713612599
Short name T2454
Test name
Test status
Simulation time 157173998 ps
CPU time 0.81 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:00 PM PDT 24
Peak memory 206696 kb
Host smart-6e4d7bd0-36b7-47eb-b99a-66ffb4b46092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37136
12599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.3713612599
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.2093769883
Short name T1506
Test name
Test status
Simulation time 236364412 ps
CPU time 0.9 seconds
Started Jul 21 06:59:52 PM PDT 24
Finished Jul 21 06:59:54 PM PDT 24
Peak memory 206664 kb
Host smart-7e5b6bfd-87c1-4c89-8101-552d5c0f3624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20937
69883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.2093769883
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.2827854263
Short name T298
Test name
Test status
Simulation time 206456062 ps
CPU time 0.84 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:00 PM PDT 24
Peak memory 206684 kb
Host smart-6a9e4923-95e1-4138-82c1-e1a80490883f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28278
54263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.2827854263
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.3546220195
Short name T527
Test name
Test status
Simulation time 151437037 ps
CPU time 0.79 seconds
Started Jul 21 06:59:52 PM PDT 24
Finished Jul 21 06:59:54 PM PDT 24
Peak memory 206656 kb
Host smart-82ebbbc5-d9e5-4418-870f-1eab21b167ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35462
20195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.3546220195
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1731901867
Short name T546
Test name
Test status
Simulation time 185005959 ps
CPU time 0.83 seconds
Started Jul 21 06:59:50 PM PDT 24
Finished Jul 21 06:59:52 PM PDT 24
Peak memory 206684 kb
Host smart-f74025b1-7ef8-476f-8716-65fc9ed02a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17319
01867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1731901867
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.230386339
Short name T1915
Test name
Test status
Simulation time 167893805 ps
CPU time 0.82 seconds
Started Jul 21 06:59:40 PM PDT 24
Finished Jul 21 06:59:41 PM PDT 24
Peak memory 206636 kb
Host smart-96d1d212-1e68-4311-b856-e6d6b866363c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23038
6339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.230386339
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1388278303
Short name T1007
Test name
Test status
Simulation time 174700333 ps
CPU time 0.82 seconds
Started Jul 21 06:59:48 PM PDT 24
Finished Jul 21 06:59:49 PM PDT 24
Peak memory 206688 kb
Host smart-c1aa40e7-1afe-4f4f-b8a1-89f7ed90e1e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13882
78303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1388278303
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.4150935567
Short name T1067
Test name
Test status
Simulation time 244073778 ps
CPU time 0.96 seconds
Started Jul 21 06:59:43 PM PDT 24
Finished Jul 21 06:59:44 PM PDT 24
Peak memory 206648 kb
Host smart-8853f4d9-559e-4e6b-bce9-ad77abd0722c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
35567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.4150935567
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.2215572248
Short name T1488
Test name
Test status
Simulation time 3620370924 ps
CPU time 101.77 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:01:41 PM PDT 24
Peak memory 206880 kb
Host smart-c50ee519-2cfa-4560-ba33-807b0874fdbb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2215572248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.2215572248
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.2272573279
Short name T2002
Test name
Test status
Simulation time 223086000 ps
CPU time 0.9 seconds
Started Jul 21 06:59:38 PM PDT 24
Finished Jul 21 06:59:40 PM PDT 24
Peak memory 206612 kb
Host smart-2f528c49-b5d8-4512-887c-9416bd093c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22725
73279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.2272573279
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3569009673
Short name T1045
Test name
Test status
Simulation time 223523633 ps
CPU time 0.85 seconds
Started Jul 21 06:59:49 PM PDT 24
Finished Jul 21 06:59:50 PM PDT 24
Peak memory 206664 kb
Host smart-f4ea4da3-acc3-469f-bf8d-70a856a4a409
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35690
09673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3569009673
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.460953330
Short name T1235
Test name
Test status
Simulation time 1272283306 ps
CPU time 2.95 seconds
Started Jul 21 06:59:43 PM PDT 24
Finished Jul 21 06:59:47 PM PDT 24
Peak memory 206800 kb
Host smart-62f8278d-fcf1-4e3b-97ce-e60555f09cba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46095
3330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.460953330
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.877339134
Short name T1057
Test name
Test status
Simulation time 4293293294 ps
CPU time 30.36 seconds
Started Jul 21 06:59:50 PM PDT 24
Finished Jul 21 07:00:21 PM PDT 24
Peak memory 206952 kb
Host smart-ecb8ebb5-9576-459e-8e55-4b0dd2fac9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87733
9134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.877339134
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.1382753715
Short name T181
Test name
Test status
Simulation time 47143685 ps
CPU time 0.67 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:00 PM PDT 24
Peak memory 206696 kb
Host smart-e90546ae-7914-4636-8ddf-180b6eed0d54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1382753715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.1382753715
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.2539909283
Short name T219
Test name
Test status
Simulation time 4383515191 ps
CPU time 4.94 seconds
Started Jul 21 06:59:40 PM PDT 24
Finished Jul 21 06:59:46 PM PDT 24
Peak memory 206968 kb
Host smart-3af61d0e-556c-4ebe-977c-83f38c7c87e3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2539909283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.2539909283
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.533940627
Short name T888
Test name
Test status
Simulation time 13384009124 ps
CPU time 16.22 seconds
Started Jul 21 06:59:49 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206788 kb
Host smart-1d986523-8208-4892-8e31-ab47e0427d47
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=533940627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.533940627
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3025877777
Short name T511
Test name
Test status
Simulation time 23452268390 ps
CPU time 23.15 seconds
Started Jul 21 06:59:47 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206928 kb
Host smart-fa36bcf7-3be8-426d-b83b-51a3048cd56f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3025877777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3025877777
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2413793289
Short name T1251
Test name
Test status
Simulation time 160750379 ps
CPU time 0.85 seconds
Started Jul 21 06:59:57 PM PDT 24
Finished Jul 21 06:59:59 PM PDT 24
Peak memory 206680 kb
Host smart-c8991bf9-6989-4704-afaf-ebcc24dc6a0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24137
93289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2413793289
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.2684478764
Short name T2313
Test name
Test status
Simulation time 165492137 ps
CPU time 0.82 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 06:59:55 PM PDT 24
Peak memory 206692 kb
Host smart-ce672b29-a95f-494b-ad48-23fd0c2e97d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26844
78764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.2684478764
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.894202728
Short name T892
Test name
Test status
Simulation time 300105338 ps
CPU time 1.12 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 06:59:58 PM PDT 24
Peak memory 206140 kb
Host smart-6d6f04ce-992b-4b46-affb-0e47a3ccdded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89420
2728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.894202728
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.3378180810
Short name T2387
Test name
Test status
Simulation time 1422156347 ps
CPU time 3.51 seconds
Started Jul 21 06:59:43 PM PDT 24
Finished Jul 21 06:59:47 PM PDT 24
Peak memory 206808 kb
Host smart-d467593c-b080-4d61-bd32-79aa24e7f467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33781
80810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.3378180810
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.1347976555
Short name T1794
Test name
Test status
Simulation time 9654965641 ps
CPU time 19.68 seconds
Started Jul 21 06:59:42 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206912 kb
Host smart-103fb1c5-d02e-4179-861a-0f33494171a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13479
76555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.1347976555
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.3723115919
Short name T581
Test name
Test status
Simulation time 349810532 ps
CPU time 1.15 seconds
Started Jul 21 06:59:49 PM PDT 24
Finished Jul 21 06:59:51 PM PDT 24
Peak memory 206668 kb
Host smart-f2f1d18c-8136-483e-bf20-70ac9d1867c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37231
15919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.3723115919
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.1386032325
Short name T427
Test name
Test status
Simulation time 153948963 ps
CPU time 0.78 seconds
Started Jul 21 06:59:52 PM PDT 24
Finished Jul 21 06:59:53 PM PDT 24
Peak memory 206672 kb
Host smart-80034572-b3e0-4bc6-aab0-505c003a5a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13860
32325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.1386032325
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.10111980
Short name T816
Test name
Test status
Simulation time 35959906 ps
CPU time 0.67 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206648 kb
Host smart-aa3fc18a-8fd0-4d10-bb7f-45da66abe1db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10111
980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.10111980
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.2454960562
Short name T698
Test name
Test status
Simulation time 852524540 ps
CPU time 2.11 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 06:59:59 PM PDT 24
Peak memory 206780 kb
Host smart-ca77fe96-1a10-42d9-928b-61bf5326e08a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24549
60562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.2454960562
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.462369662
Short name T2218
Test name
Test status
Simulation time 278330604 ps
CPU time 1.68 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206808 kb
Host smart-d083d4ab-46ac-4609-a6a4-f7ebc6fe1b4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46236
9662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.462369662
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.778309377
Short name T1073
Test name
Test status
Simulation time 224851315 ps
CPU time 0.89 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206620 kb
Host smart-bc88cc13-a4ec-4931-b9dc-876c4b0f862d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77830
9377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.778309377
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2791695944
Short name T732
Test name
Test status
Simulation time 138368215 ps
CPU time 0.75 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:14 PM PDT 24
Peak memory 206620 kb
Host smart-769b26a2-26fa-470b-9b80-8d35a456a481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27916
95944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2791695944
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.2174863012
Short name T324
Test name
Test status
Simulation time 231153984 ps
CPU time 0.95 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 06:59:55 PM PDT 24
Peak memory 206692 kb
Host smart-8e924146-5b16-46c3-94c3-7323eca7c095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21748
63012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.2174863012
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.897553304
Short name T68
Test name
Test status
Simulation time 7672462455 ps
CPU time 207.91 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:03:32 PM PDT 24
Peak memory 206924 kb
Host smart-4030aa1e-9efa-45aa-bc9d-6828f2648b87
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=897553304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.897553304
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.490734033
Short name T1245
Test name
Test status
Simulation time 8973611467 ps
CPU time 30.19 seconds
Started Jul 21 06:59:55 PM PDT 24
Finished Jul 21 07:00:26 PM PDT 24
Peak memory 206924 kb
Host smart-e341a079-a95a-4e7e-b9ee-07a2d37b3245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49073
4033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.490734033
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.39105191
Short name T325
Test name
Test status
Simulation time 207309180 ps
CPU time 0.82 seconds
Started Jul 21 06:59:51 PM PDT 24
Finished Jul 21 06:59:53 PM PDT 24
Peak memory 206704 kb
Host smart-47623c52-8664-4153-bd24-467ccae89bbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39105
191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.39105191
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.2889301342
Short name T2064
Test name
Test status
Simulation time 23373711527 ps
CPU time 21.6 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:25 PM PDT 24
Peak memory 206856 kb
Host smart-9abd35f3-8552-4b01-bb2d-6da7cfd774d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28893
01342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.2889301342
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.2494950260
Short name T2581
Test name
Test status
Simulation time 3334787903 ps
CPU time 3.55 seconds
Started Jul 21 06:59:55 PM PDT 24
Finished Jul 21 06:59:59 PM PDT 24
Peak memory 206720 kb
Host smart-b9317b53-1e90-4410-9f6a-f5c2e259a6aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24949
50260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.2494950260
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.2237261983
Short name T1500
Test name
Test status
Simulation time 12971734880 ps
CPU time 353.01 seconds
Started Jul 21 06:59:57 PM PDT 24
Finished Jul 21 07:05:52 PM PDT 24
Peak memory 206952 kb
Host smart-0797bdb9-868c-46d0-9170-aa9407378057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22372
61983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.2237261983
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.2943796885
Short name T829
Test name
Test status
Simulation time 7312639155 ps
CPU time 202.57 seconds
Started Jul 21 07:00:02 PM PDT 24
Finished Jul 21 07:03:28 PM PDT 24
Peak memory 206932 kb
Host smart-5f90af05-e147-4236-9a03-8636afa6e243
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2943796885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.2943796885
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.2764797514
Short name T528
Test name
Test status
Simulation time 282682402 ps
CPU time 0.93 seconds
Started Jul 21 06:59:48 PM PDT 24
Finished Jul 21 06:59:50 PM PDT 24
Peak memory 206668 kb
Host smart-b63ebf62-91ef-4579-96b8-119c9c769603
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2764797514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.2764797514
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.2339718645
Short name T595
Test name
Test status
Simulation time 192166932 ps
CPU time 0.87 seconds
Started Jul 21 06:59:52 PM PDT 24
Finished Jul 21 06:59:54 PM PDT 24
Peak memory 206648 kb
Host smart-161c2c18-889c-4407-bd6a-502071ac14c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23397
18645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.2339718645
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.295727133
Short name T1361
Test name
Test status
Simulation time 5322164706 ps
CPU time 38.36 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 07:00:32 PM PDT 24
Peak memory 206932 kb
Host smart-09b44154-5061-437b-87b5-cecb9b15fe85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29572
7133 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.295727133
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.2706967779
Short name T1627
Test name
Test status
Simulation time 5422316185 ps
CPU time 151.16 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 07:02:24 PM PDT 24
Peak memory 206824 kb
Host smart-0db201d8-4fbc-4b06-815c-b33464879a82
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2706967779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.2706967779
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.3261878421
Short name T1223
Test name
Test status
Simulation time 153180724 ps
CPU time 0.78 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206680 kb
Host smart-40f1032e-4bea-410f-8a8e-855f22ccd042
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3261878421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.3261878421
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.297475720
Short name T1576
Test name
Test status
Simulation time 190194801 ps
CPU time 0.8 seconds
Started Jul 21 06:59:51 PM PDT 24
Finished Jul 21 06:59:53 PM PDT 24
Peak memory 206664 kb
Host smart-171a2b11-cc50-4740-ab21-fb602ae2f430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29747
5720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.297475720
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.936347190
Short name T125
Test name
Test status
Simulation time 212986292 ps
CPU time 0.94 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206660 kb
Host smart-93a7db63-f5bb-49af-a7de-ca35b15cb882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93634
7190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.936347190
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.2009864165
Short name T1189
Test name
Test status
Simulation time 181244780 ps
CPU time 0.88 seconds
Started Jul 21 06:59:57 PM PDT 24
Finished Jul 21 06:59:59 PM PDT 24
Peak memory 206688 kb
Host smart-87e0b63c-b7e2-44b5-b87b-3c3a259d78e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20098
64165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.2009864165
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.209456635
Short name T1769
Test name
Test status
Simulation time 204732401 ps
CPU time 0.86 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206692 kb
Host smart-16dfbb52-d61f-4b94-bd7b-8a10d459037e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20945
6635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.209456635
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.2295675571
Short name T2637
Test name
Test status
Simulation time 155627649 ps
CPU time 0.78 seconds
Started Jul 21 06:59:57 PM PDT 24
Finished Jul 21 06:59:59 PM PDT 24
Peak memory 206640 kb
Host smart-3624977a-6f8c-4fcd-a142-6e09f1332dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
75571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.2295675571
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.3638560955
Short name T1405
Test name
Test status
Simulation time 163639580 ps
CPU time 0.78 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 06:59:54 PM PDT 24
Peak memory 206632 kb
Host smart-68843051-8ab1-4e3e-b5be-ebe2447b8244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36385
60955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.3638560955
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.3994364382
Short name T359
Test name
Test status
Simulation time 247848471 ps
CPU time 0.9 seconds
Started Jul 21 06:59:53 PM PDT 24
Finished Jul 21 06:59:54 PM PDT 24
Peak memory 206672 kb
Host smart-e97f5bcf-0da5-4e24-b816-58b40d48853a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3994364382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.3994364382
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.3363381735
Short name T1983
Test name
Test status
Simulation time 141381843 ps
CPU time 0.78 seconds
Started Jul 21 06:59:47 PM PDT 24
Finished Jul 21 06:59:48 PM PDT 24
Peak memory 206680 kb
Host smart-68d9dee3-5c10-4366-97d9-5c6f04cfbb39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
81735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.3363381735
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.270661089
Short name T1228
Test name
Test status
Simulation time 53103409 ps
CPU time 0.66 seconds
Started Jul 21 06:59:47 PM PDT 24
Finished Jul 21 06:59:48 PM PDT 24
Peak memory 206644 kb
Host smart-63e66eeb-4719-423f-97ac-0af73f56673a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27066
1089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.270661089
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.4005145011
Short name T2225
Test name
Test status
Simulation time 21577630375 ps
CPU time 46.7 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:48 PM PDT 24
Peak memory 215132 kb
Host smart-79451406-e70e-47a8-997b-d22390ce0aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40051
45011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.4005145011
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.793598290
Short name T2107
Test name
Test status
Simulation time 189433771 ps
CPU time 0.81 seconds
Started Jul 21 06:59:55 PM PDT 24
Finished Jul 21 06:59:57 PM PDT 24
Peak memory 206672 kb
Host smart-06252d85-586c-41d9-8f4f-88b254fd50e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79359
8290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.793598290
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3300100671
Short name T2440
Test name
Test status
Simulation time 230238614 ps
CPU time 0.87 seconds
Started Jul 21 06:59:51 PM PDT 24
Finished Jul 21 06:59:53 PM PDT 24
Peak memory 206672 kb
Host smart-5378c599-3ef8-476f-b6dc-b0946ddcfa8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33001
00671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3300100671
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.1100148356
Short name T1942
Test name
Test status
Simulation time 201690835 ps
CPU time 0.89 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206664 kb
Host smart-33e6e0fe-4563-4162-9d82-911287dd4b4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11001
48356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.1100148356
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.643649527
Short name T2047
Test name
Test status
Simulation time 172885238 ps
CPU time 0.85 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206676 kb
Host smart-9d7919d3-1b0f-48a8-a6d4-5f2db0a62eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64364
9527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.643649527
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.3784642670
Short name T44
Test name
Test status
Simulation time 145745010 ps
CPU time 0.75 seconds
Started Jul 21 06:59:55 PM PDT 24
Finished Jul 21 06:59:57 PM PDT 24
Peak memory 206648 kb
Host smart-e7800227-ff8a-49f4-a380-28c7e5564337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37846
42670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.3784642670
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.1253775721
Short name T1435
Test name
Test status
Simulation time 158102962 ps
CPU time 0.77 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 06:59:58 PM PDT 24
Peak memory 206724 kb
Host smart-8ec3af0c-534b-45f8-a741-abcc09ba4245
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12537
75721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.1253775721
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.1207398406
Short name T2505
Test name
Test status
Simulation time 162140944 ps
CPU time 0.79 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206680 kb
Host smart-5a4d669d-a4d5-4d5d-8265-7b90f96bb2eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12073
98406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.1207398406
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.1716143525
Short name T1121
Test name
Test status
Simulation time 229914212 ps
CPU time 0.95 seconds
Started Jul 21 06:59:57 PM PDT 24
Finished Jul 21 06:59:59 PM PDT 24
Peak memory 206692 kb
Host smart-a938ccc3-a467-4687-a25c-35119b514b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17161
43525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.1716143525
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.1438642519
Short name T489
Test name
Test status
Simulation time 158977082 ps
CPU time 0.82 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:03 PM PDT 24
Peak memory 206648 kb
Host smart-97560cb8-5d81-45e1-b661-fc0a59d6bdcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14386
42519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.1438642519
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.1449466506
Short name T2011
Test name
Test status
Simulation time 166699630 ps
CPU time 0.83 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:04 PM PDT 24
Peak memory 206716 kb
Host smart-0fb0d185-1ffa-463c-90e5-d4148a68cd9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14494
66506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.1449466506
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.1323941842
Short name T1632
Test name
Test status
Simulation time 316975383 ps
CPU time 1.09 seconds
Started Jul 21 06:59:50 PM PDT 24
Finished Jul 21 06:59:52 PM PDT 24
Peak memory 206680 kb
Host smart-b1d95308-25e0-48ae-b171-3db56937f97a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13239
41842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.1323941842
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.710935082
Short name T1029
Test name
Test status
Simulation time 2889047237 ps
CPU time 74.97 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:01:18 PM PDT 24
Peak memory 206888 kb
Host smart-0619d2a6-5d7b-42f6-8642-983c0db25750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71093
5082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.710935082
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.2036597607
Short name T2407
Test name
Test status
Simulation time 37666552 ps
CPU time 0.68 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:07 PM PDT 24
Peak memory 206720 kb
Host smart-ff18973e-8876-472c-bd9d-6b8df08189ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2036597607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.2036597607
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.817279324
Short name T1565
Test name
Test status
Simulation time 3606489840 ps
CPU time 4.55 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:13 PM PDT 24
Peak memory 206756 kb
Host smart-43151e9c-06b8-4ff0-987a-6dd5780592af
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=817279324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.817279324
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2391676364
Short name T182
Test name
Test status
Simulation time 13392922050 ps
CPU time 14.64 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:15 PM PDT 24
Peak memory 206844 kb
Host smart-0f0987df-8d51-4ef3-b2d3-c03844445e39
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2391676364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2391676364
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.496957102
Short name T2475
Test name
Test status
Simulation time 23430293396 ps
CPU time 25.34 seconds
Started Jul 21 06:59:57 PM PDT 24
Finished Jul 21 07:00:24 PM PDT 24
Peak memory 206800 kb
Host smart-e2b8afbc-ec8d-451b-89e0-14a1291a4ed7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=496957102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.496957102
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.3400963025
Short name T2075
Test name
Test status
Simulation time 150270851 ps
CPU time 0.84 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206788 kb
Host smart-bc66f0b7-7705-43ca-95e8-75ad0842dff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34009
63025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.3400963025
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3340587998
Short name T1803
Test name
Test status
Simulation time 164503881 ps
CPU time 0.77 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 06:59:58 PM PDT 24
Peak memory 206660 kb
Host smart-1e201288-74c0-493a-b6e8-18e64d776e09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33405
87998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3340587998
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.3981768554
Short name T1732
Test name
Test status
Simulation time 233435415 ps
CPU time 0.98 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:03 PM PDT 24
Peak memory 206312 kb
Host smart-00032807-304d-4cbb-861a-07ba9d3256bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39817
68554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.3981768554
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.1316813121
Short name T1982
Test name
Test status
Simulation time 365514317 ps
CPU time 1.07 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:14 PM PDT 24
Peak memory 206684 kb
Host smart-a176bb63-09b5-469c-b58e-6c821ab0e3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13168
13121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.1316813121
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3702994219
Short name T1698
Test name
Test status
Simulation time 16127786633 ps
CPU time 31.25 seconds
Started Jul 21 06:59:55 PM PDT 24
Finished Jul 21 07:00:28 PM PDT 24
Peak memory 206836 kb
Host smart-a827ee24-5c42-4313-a199-c986f21bcf65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37029
94219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3702994219
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.2544142912
Short name T1771
Test name
Test status
Simulation time 370431432 ps
CPU time 1.19 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206636 kb
Host smart-4aecebfb-f4af-426d-9d25-b661c5d71da3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25441
42912 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.2544142912
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.2552751779
Short name T1060
Test name
Test status
Simulation time 187887579 ps
CPU time 0.8 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206688 kb
Host smart-6e071808-f09d-4b51-8a50-6cb2f5aa9dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
51779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.2552751779
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.1429515410
Short name T2488
Test name
Test status
Simulation time 36960772 ps
CPU time 0.69 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206672 kb
Host smart-9f46883d-1e5c-4664-b64e-92c7effe4e7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14295
15410 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.1429515410
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.1087564266
Short name T2249
Test name
Test status
Simulation time 802452134 ps
CPU time 1.89 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206776 kb
Host smart-732dabd9-f252-4cc4-ba1c-00376c28ab6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10875
64266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.1087564266
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.2266529723
Short name T1909
Test name
Test status
Simulation time 236398768 ps
CPU time 2.12 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206836 kb
Host smart-d0d41216-62d3-4d38-acd1-c963f4436f4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22665
29723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.2266529723
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.989114489
Short name T2008
Test name
Test status
Simulation time 171714601 ps
CPU time 0.82 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206684 kb
Host smart-a9158f92-833f-4363-a592-c3c59e997c40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98911
4489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.989114489
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.4051196222
Short name T487
Test name
Test status
Simulation time 165144963 ps
CPU time 0.79 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206560 kb
Host smart-9b4eb166-0318-4cd2-afec-269ba59a4cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40511
96222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.4051196222
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.2663027512
Short name T597
Test name
Test status
Simulation time 208902813 ps
CPU time 0.88 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:00 PM PDT 24
Peak memory 206608 kb
Host smart-c20cbb02-dba7-4c77-9705-ce07bd81fc9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26630
27512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.2663027512
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.96888338
Short name T1960
Test name
Test status
Simulation time 11487509788 ps
CPU time 95.98 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 07:01:33 PM PDT 24
Peak memory 206920 kb
Host smart-18f00b41-d803-43d5-b6ff-c6b1fc9caf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96888
338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.96888338
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.3802017366
Short name T1111
Test name
Test status
Simulation time 162107671 ps
CPU time 0.8 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206652 kb
Host smart-e11b81c8-e7fe-4d47-a960-99246b1d2915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38020
17366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.3802017366
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.1923996874
Short name T1827
Test name
Test status
Simulation time 23326660392 ps
CPU time 22.14 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:26 PM PDT 24
Peak memory 206808 kb
Host smart-533052d3-736f-441b-8211-cd429de702d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19239
96874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.1923996874
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.1255388341
Short name T320
Test name
Test status
Simulation time 3340322443 ps
CPU time 4.11 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206748 kb
Host smart-b48c07f9-3ae6-4eb6-890e-8037df79c81d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12553
88341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.1255388341
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.3748786384
Short name T428
Test name
Test status
Simulation time 7239087469 ps
CPU time 199.46 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:03:25 PM PDT 24
Peak memory 206968 kb
Host smart-5e37e80a-0ac5-4430-a8fc-8f7ae3fd2ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37487
86384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.3748786384
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.3087715327
Short name T1760
Test name
Test status
Simulation time 7689196935 ps
CPU time 73.78 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:01:18 PM PDT 24
Peak memory 206948 kb
Host smart-9e780de8-a64f-478e-98be-05c740bdd717
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3087715327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.3087715327
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.3636959064
Short name T2172
Test name
Test status
Simulation time 237015198 ps
CPU time 0.93 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206668 kb
Host smart-bebf6aa3-1921-4947-ba19-7c872eb98804
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3636959064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.3636959064
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.1168424495
Short name T1296
Test name
Test status
Simulation time 214612472 ps
CPU time 0.92 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:03 PM PDT 24
Peak memory 206212 kb
Host smart-21f4774c-41c9-4b2f-b069-ea16b9c029fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11684
24495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.1168424495
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3902627406
Short name T504
Test name
Test status
Simulation time 3489809709 ps
CPU time 96.99 seconds
Started Jul 21 06:59:54 PM PDT 24
Finished Jul 21 07:01:31 PM PDT 24
Peak memory 206868 kb
Host smart-1a64b8ef-2fd5-421b-b88c-5493596ac662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39026
27406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3902627406
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.1735318932
Short name T1606
Test name
Test status
Simulation time 3109362954 ps
CPU time 28.49 seconds
Started Jul 21 06:59:56 PM PDT 24
Finished Jul 21 07:00:26 PM PDT 24
Peak memory 206868 kb
Host smart-b385650d-9e5a-4ebd-9a1c-99ef0ced0698
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1735318932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.1735318932
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1728339307
Short name T2095
Test name
Test status
Simulation time 178187333 ps
CPU time 0.87 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206624 kb
Host smart-58e5e7fb-852d-4a74-bf0a-b487147af4aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1728339307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1728339307
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.763302083
Short name T1805
Test name
Test status
Simulation time 143462180 ps
CPU time 0.81 seconds
Started Jul 21 06:59:50 PM PDT 24
Finished Jul 21 06:59:51 PM PDT 24
Peak memory 206652 kb
Host smart-3190d424-d681-4d99-a406-fb2cc1e0309b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76330
2083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.763302083
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.2704056584
Short name T127
Test name
Test status
Simulation time 179043023 ps
CPU time 0.81 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:07 PM PDT 24
Peak memory 206564 kb
Host smart-f2bfe730-8558-4e70-a9a7-24f95417b1a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27040
56584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.2704056584
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.2854497370
Short name T1968
Test name
Test status
Simulation time 172257967 ps
CPU time 0.89 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:03 PM PDT 24
Peak memory 206680 kb
Host smart-061e540e-c9d0-47f1-af5f-e922d4eda359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28544
97370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.2854497370
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.1036895760
Short name T2433
Test name
Test status
Simulation time 178761858 ps
CPU time 0.83 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:00 PM PDT 24
Peak memory 206680 kb
Host smart-c99d744e-235c-4e65-9878-557022df81b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10368
95760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.1036895760
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3092537617
Short name T1081
Test name
Test status
Simulation time 168260220 ps
CPU time 0.8 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:07 PM PDT 24
Peak memory 206632 kb
Host smart-bf7de432-8f4f-4843-93ab-45743c3c4bc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30925
37617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3092537617
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.2460778904
Short name T2510
Test name
Test status
Simulation time 147979410 ps
CPU time 0.76 seconds
Started Jul 21 06:59:58 PM PDT 24
Finished Jul 21 07:00:00 PM PDT 24
Peak memory 206652 kb
Host smart-e28d9675-2426-46aa-b08f-ee0f806499f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24607
78904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.2460778904
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.1441389399
Short name T46
Test name
Test status
Simulation time 236725314 ps
CPU time 0.93 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206692 kb
Host smart-43144f9d-3ce9-4b72-b191-5abf0731b1e4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1441389399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.1441389399
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.3168702787
Short name T1856
Test name
Test status
Simulation time 156746179 ps
CPU time 0.77 seconds
Started Jul 21 06:59:52 PM PDT 24
Finished Jul 21 06:59:53 PM PDT 24
Peak memory 206656 kb
Host smart-b323d266-d00a-4b89-b833-3bc707f0175c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31687
02787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.3168702787
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3221999910
Short name T716
Test name
Test status
Simulation time 36559833 ps
CPU time 0.68 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206680 kb
Host smart-e31a66d8-282f-445a-b92f-15c640c59bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32219
99910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3221999910
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2496179926
Short name T1199
Test name
Test status
Simulation time 11677337292 ps
CPU time 26.99 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:34 PM PDT 24
Peak memory 215240 kb
Host smart-5368ddaf-a4c5-4c41-ba98-19f053e319dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
79926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2496179926
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.1381864679
Short name T2265
Test name
Test status
Simulation time 182593951 ps
CPU time 0.83 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206656 kb
Host smart-889fdcdc-a4ea-4063-8f8b-6451d475dd3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13818
64679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.1381864679
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1400556608
Short name T1089
Test name
Test status
Simulation time 233987324 ps
CPU time 0.92 seconds
Started Jul 21 07:00:08 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206680 kb
Host smart-c787f02b-a35e-4d7b-8acd-e53901392f51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14005
56608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1400556608
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.595717261
Short name T1412
Test name
Test status
Simulation time 251488567 ps
CPU time 0.9 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:02 PM PDT 24
Peak memory 206616 kb
Host smart-e733c00d-cf00-4016-a673-d43da9afa70c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59571
7261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.595717261
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.2938178111
Short name T2536
Test name
Test status
Simulation time 156006423 ps
CPU time 0.82 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:01 PM PDT 24
Peak memory 206632 kb
Host smart-70456dbf-7bff-45de-867c-238e930e6a35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
78111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.2938178111
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.224055056
Short name T391
Test name
Test status
Simulation time 205582479 ps
CPU time 0.88 seconds
Started Jul 21 07:00:02 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206688 kb
Host smart-7d1ad958-0d68-44af-a093-cb281579b669
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22405
5056 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.224055056
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.2908569153
Short name T2318
Test name
Test status
Simulation time 155884284 ps
CPU time 0.76 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206652 kb
Host smart-7f6d2591-8e15-4f2d-ace7-37232114bb7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29085
69153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.2908569153
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.2887390891
Short name T2726
Test name
Test status
Simulation time 162193573 ps
CPU time 0.78 seconds
Started Jul 21 07:00:02 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206680 kb
Host smart-910f6833-0a01-4a3e-a840-9fb67fdd43ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28873
90891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.2887390891
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.2860357506
Short name T899
Test name
Test status
Simulation time 187474152 ps
CPU time 0.92 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206656 kb
Host smart-850f49bb-4e5a-4b52-9a3d-5481ddc81c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603
57506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.2860357506
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.1145000547
Short name T1976
Test name
Test status
Simulation time 3791323017 ps
CPU time 34.31 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:42 PM PDT 24
Peak memory 206900 kb
Host smart-6a315ff6-ea91-4fef-9aee-c3ec478ed38c
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1145000547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.1145000547
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.365748229
Short name T339
Test name
Test status
Simulation time 199044856 ps
CPU time 0.86 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:04 PM PDT 24
Peak memory 206688 kb
Host smart-a2158209-7071-4fc8-86aa-588c598743e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36574
8229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.365748229
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2263693285
Short name T2732
Test name
Test status
Simulation time 158168677 ps
CPU time 0.8 seconds
Started Jul 21 07:00:22 PM PDT 24
Finished Jul 21 07:00:28 PM PDT 24
Peak memory 206652 kb
Host smart-56cff22a-86d9-44ac-94d6-01b61257895c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22636
93285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2263693285
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.1600497891
Short name T326
Test name
Test status
Simulation time 1016218887 ps
CPU time 2.33 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206792 kb
Host smart-9518cf99-5b53-4a16-bd31-4393ffc04f41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16004
97891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.1600497891
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.3511012577
Short name T2332
Test name
Test status
Simulation time 4200871020 ps
CPU time 36.36 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 206824 kb
Host smart-654a5131-206a-43b3-b671-e294ef116c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35110
12577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.3511012577
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.52139489
Short name T2544
Test name
Test status
Simulation time 53018096 ps
CPU time 0.69 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:14 PM PDT 24
Peak memory 206752 kb
Host smart-3aa19a13-6765-4b88-9983-c8cb12fc9cbb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=52139489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.52139489
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.387245025
Short name T11
Test name
Test status
Simulation time 3780698379 ps
CPU time 5.47 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:14 PM PDT 24
Peak memory 206816 kb
Host smart-e7405652-c4e0-44d5-b3ea-7a4e4fca9f37
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=387245025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.387245025
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.3455623089
Short name T2665
Test name
Test status
Simulation time 13351133468 ps
CPU time 13.45 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206796 kb
Host smart-1979e278-71c1-44f2-a800-91184cd8d76f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3455623089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.3455623089
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3127614566
Short name T9
Test name
Test status
Simulation time 23404507201 ps
CPU time 23.07 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:27 PM PDT 24
Peak memory 206812 kb
Host smart-5ff8d0b9-06a2-45e7-a675-8906b25721f6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3127614566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3127614566
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.594539981
Short name T2309
Test name
Test status
Simulation time 150712489 ps
CPU time 0.81 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206668 kb
Host smart-e4964e2f-81e2-4fd2-9365-1cc6e1793881
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59453
9981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.594539981
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.3469254058
Short name T366
Test name
Test status
Simulation time 183780209 ps
CPU time 0.9 seconds
Started Jul 21 07:00:18 PM PDT 24
Finished Jul 21 07:00:20 PM PDT 24
Peak memory 206692 kb
Host smart-d9cd7508-84b7-4d59-a51c-945085e8bb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34692
54058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.3469254058
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.2176140962
Short name T1780
Test name
Test status
Simulation time 424748721 ps
CPU time 1.36 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:05 PM PDT 24
Peak memory 206676 kb
Host smart-d001904d-8778-47dc-a80b-bb00eb142d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21761
40962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.2176140962
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.1426487234
Short name T2119
Test name
Test status
Simulation time 389010094 ps
CPU time 1.19 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206672 kb
Host smart-faf68d1e-2183-4900-8fc3-2b58837bbef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14264
87234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.1426487234
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.3858458135
Short name T1751
Test name
Test status
Simulation time 8887769453 ps
CPU time 16.89 seconds
Started Jul 21 07:00:11 PM PDT 24
Finished Jul 21 07:00:29 PM PDT 24
Peak memory 206848 kb
Host smart-a7cc8ab3-942a-41a7-bb81-38bcad5b05c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38584
58135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.3858458135
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.2111538209
Short name T2344
Test name
Test status
Simulation time 426109692 ps
CPU time 1.29 seconds
Started Jul 21 07:00:02 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206700 kb
Host smart-e85f2f1f-ef7c-4edc-a0a3-215431aacd04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21115
38209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.2111538209
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.620038407
Short name T2132
Test name
Test status
Simulation time 148007850 ps
CPU time 0.78 seconds
Started Jul 21 07:00:02 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206696 kb
Host smart-0474cfc7-886c-454d-bf75-fa37ff8592c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62003
8407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.620038407
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.2790833732
Short name T2528
Test name
Test status
Simulation time 47300516 ps
CPU time 0.67 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206688 kb
Host smart-0ff77f47-dafe-422c-83b9-d28785a926b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27908
33732 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.2790833732
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.1135101983
Short name T2148
Test name
Test status
Simulation time 958330901 ps
CPU time 2.15 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206828 kb
Host smart-a3f33e09-57cf-4871-a523-e81535fa3092
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11351
01983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.1135101983
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.2067235332
Short name T2108
Test name
Test status
Simulation time 157800422 ps
CPU time 1.64 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206764 kb
Host smart-643b9444-d2e8-4f1b-b2c4-9cc32fe8e17e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20672
35332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.2067235332
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.3541632453
Short name T862
Test name
Test status
Simulation time 243241813 ps
CPU time 0.9 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206560 kb
Host smart-6b40e225-8e4e-4ec7-93f2-dc91c288ee4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35416
32453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.3541632453
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.3965803258
Short name T1158
Test name
Test status
Simulation time 147034629 ps
CPU time 0.74 seconds
Started Jul 21 07:00:18 PM PDT 24
Finished Jul 21 07:00:25 PM PDT 24
Peak memory 206632 kb
Host smart-aa675cc6-7986-40aa-a8da-86e378f42388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39658
03258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.3965803258
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.2292063091
Short name T2483
Test name
Test status
Simulation time 208313952 ps
CPU time 0.86 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206688 kb
Host smart-089af697-22f7-4faf-b10e-f902576c89dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22920
63091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.2292063091
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.646337064
Short name T2502
Test name
Test status
Simulation time 6967280536 ps
CPU time 63.72 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 206864 kb
Host smart-5f35c275-3d48-4606-90ba-289874cc9759
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=646337064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.646337064
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1679143994
Short name T1666
Test name
Test status
Simulation time 6064372340 ps
CPU time 22.97 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:36 PM PDT 24
Peak memory 206864 kb
Host smart-4c0ecd0c-a157-4d1c-9885-45fb5eec75f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16791
43994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1679143994
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.1734075386
Short name T328
Test name
Test status
Simulation time 255597859 ps
CPU time 0.9 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206632 kb
Host smart-7e774818-7681-4546-99d1-8198ad4e2f93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17340
75386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.1734075386
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.3475471102
Short name T1911
Test name
Test status
Simulation time 23358944734 ps
CPU time 24.57 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:31 PM PDT 24
Peak memory 206700 kb
Host smart-82118ce4-22b2-4b49-b90b-fdc6ce0188ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34754
71102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.3475471102
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.2926821898
Short name T994
Test name
Test status
Simulation time 3286320124 ps
CPU time 4.23 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:13 PM PDT 24
Peak memory 206728 kb
Host smart-9f178877-9f3d-4e3a-8fca-d4dcb715bdbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29268
21898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.2926821898
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.3876856926
Short name T900
Test name
Test status
Simulation time 10749656671 ps
CPU time 75.61 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:01:19 PM PDT 24
Peak memory 206944 kb
Host smart-c01af776-52b4-41eb-8430-e6516ce9e045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38768
56926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.3876856926
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.2989107065
Short name T464
Test name
Test status
Simulation time 4316376652 ps
CPU time 116.92 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:02:04 PM PDT 24
Peak memory 206908 kb
Host smart-9e321f79-0459-4af1-8203-ecab2bd67416
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2989107065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.2989107065
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3617669848
Short name T296
Test name
Test status
Simulation time 235257386 ps
CPU time 0.89 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:17 PM PDT 24
Peak memory 206648 kb
Host smart-6e0e67e6-0fb3-4029-b7e1-b300aae118b4
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3617669848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3617669848
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.4083671234
Short name T1448
Test name
Test status
Simulation time 194153893 ps
CPU time 0.86 seconds
Started Jul 21 07:00:11 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206684 kb
Host smart-daecda05-28a7-4a7e-883f-157cb407e059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40836
71234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.4083671234
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.2802641338
Short name T1540
Test name
Test status
Simulation time 3607275111 ps
CPU time 34.05 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:40 PM PDT 24
Peak memory 206840 kb
Host smart-d27c5dc0-f520-4e78-84a7-f42967b3af46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28026
41338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.2802641338
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.970413570
Short name T1546
Test name
Test status
Simulation time 5044413448 ps
CPU time 140.89 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 207000 kb
Host smart-464d3932-7d24-43f3-8dca-b58d5a8514a6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=970413570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.970413570
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.3496060522
Short name T2197
Test name
Test status
Simulation time 154321437 ps
CPU time 0.8 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206660 kb
Host smart-bef23ff7-82cc-45cc-bb5d-d205feefad46
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3496060522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.3496060522
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.947614997
Short name T1957
Test name
Test status
Simulation time 163407972 ps
CPU time 0.8 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:07 PM PDT 24
Peak memory 206684 kb
Host smart-23ba5d57-4b5d-42b0-8b36-dfe3c6ce00db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94761
4997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.947614997
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.1272239093
Short name T2241
Test name
Test status
Simulation time 247809676 ps
CPU time 0.98 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206612 kb
Host smart-c5106d4d-c355-4da2-8b14-f04d68d7db10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12722
39093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.1272239093
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1532519241
Short name T1835
Test name
Test status
Simulation time 178563102 ps
CPU time 0.82 seconds
Started Jul 21 07:00:10 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206660 kb
Host smart-7e9b2a75-ab7a-48c0-8bb4-be27a08b5ff5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15325
19241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1532519241
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2315539898
Short name T2004
Test name
Test status
Simulation time 214418649 ps
CPU time 0.88 seconds
Started Jul 21 07:00:14 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206704 kb
Host smart-08fad37f-2dc9-4ea2-98ba-4df1687f6c9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23155
39898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2315539898
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.94582904
Short name T2286
Test name
Test status
Simulation time 152244450 ps
CPU time 0.82 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:00:25 PM PDT 24
Peak memory 206708 kb
Host smart-3656baf6-f6b1-4770-a6c5-ccfd56a685af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94582
904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.94582904
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.3964495610
Short name T1265
Test name
Test status
Simulation time 205384345 ps
CPU time 0.82 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:07 PM PDT 24
Peak memory 206648 kb
Host smart-3db105b3-c790-400d-b104-d95607989bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39644
95610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.3964495610
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.1916918734
Short name T2500
Test name
Test status
Simulation time 287710428 ps
CPU time 1.04 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206660 kb
Host smart-23ca4eea-c9a5-42ab-9c2e-a41e9c7bb205
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1916918734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.1916918734
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.1213627219
Short name T1202
Test name
Test status
Simulation time 168184265 ps
CPU time 0.78 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206688 kb
Host smart-979a21db-4268-462b-a91a-71c60df99a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12136
27219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.1213627219
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.1017683281
Short name T1879
Test name
Test status
Simulation time 78933143 ps
CPU time 0.7 seconds
Started Jul 21 07:00:27 PM PDT 24
Finished Jul 21 07:00:28 PM PDT 24
Peak memory 206724 kb
Host smart-b021f928-3583-4d91-86e9-76bdd437aade
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10176
83281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.1017683281
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.2102304323
Short name T1454
Test name
Test status
Simulation time 6017109948 ps
CPU time 14.71 seconds
Started Jul 21 07:00:01 PM PDT 24
Finished Jul 21 07:00:19 PM PDT 24
Peak memory 206948 kb
Host smart-9e412123-8634-49de-9352-2f8f40eda7c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21023
04323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.2102304323
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.1303198653
Short name T2390
Test name
Test status
Simulation time 164428017 ps
CPU time 0.8 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:14 PM PDT 24
Peak memory 206668 kb
Host smart-1a7cb190-a3ee-41c4-8721-b97a8eae7866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13031
98653 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.1303198653
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1467877517
Short name T1203
Test name
Test status
Simulation time 209557214 ps
CPU time 0.84 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206636 kb
Host smart-727cbdaf-78e9-4d12-b084-aa257c326283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14678
77517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1467877517
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.4150918634
Short name T426
Test name
Test status
Simulation time 198419962 ps
CPU time 0.89 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:04 PM PDT 24
Peak memory 206660 kb
Host smart-90aa51b3-64f8-482b-adaa-d44416cf3f6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
18634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.4150918634
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.4103805498
Short name T452
Test name
Test status
Simulation time 195810330 ps
CPU time 0.84 seconds
Started Jul 21 07:00:14 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206584 kb
Host smart-7a27ade3-64f2-4eb9-8e75-e9f87eff080f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41038
05498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.4103805498
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.1896065304
Short name T882
Test name
Test status
Simulation time 193053752 ps
CPU time 0.83 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206640 kb
Host smart-05b1ec67-74b6-4ea1-82c1-b10fbb9c7a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18960
65304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.1896065304
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.3562093897
Short name T971
Test name
Test status
Simulation time 227981855 ps
CPU time 0.87 seconds
Started Jul 21 07:00:14 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206584 kb
Host smart-8b760cd0-ea7b-4c0e-bfc9-148e80354a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35620
93897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.3562093897
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.2594772108
Short name T1365
Test name
Test status
Simulation time 155568958 ps
CPU time 0.81 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206664 kb
Host smart-a25da599-2dc7-4b05-b134-632a541445c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25947
72108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.2594772108
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.3521078183
Short name T1618
Test name
Test status
Simulation time 211857985 ps
CPU time 0.92 seconds
Started Jul 21 07:00:00 PM PDT 24
Finished Jul 21 07:00:04 PM PDT 24
Peak memory 206664 kb
Host smart-d69de64e-ecd0-4675-908a-852c5fa8bd36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35210
78183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.3521078183
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.1618572433
Short name T1409
Test name
Test status
Simulation time 3635938100 ps
CPU time 35.75 seconds
Started Jul 21 07:00:09 PM PDT 24
Finished Jul 21 07:00:47 PM PDT 24
Peak memory 206912 kb
Host smart-e8e57adf-c986-4e24-b282-168ae8fdcde6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1618572433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.1618572433
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.1988952272
Short name T1986
Test name
Test status
Simulation time 174353623 ps
CPU time 0.8 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206612 kb
Host smart-12f87e19-c759-4804-aaf1-0e20e1618242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19889
52272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.1988952272
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.4020731318
Short name T604
Test name
Test status
Simulation time 185196248 ps
CPU time 0.83 seconds
Started Jul 21 07:00:18 PM PDT 24
Finished Jul 21 07:00:20 PM PDT 24
Peak memory 206652 kb
Host smart-9d0f75ec-5d54-4ff7-888c-a4b4ebc3a66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40207
31318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.4020731318
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.1171709308
Short name T2480
Test name
Test status
Simulation time 681089406 ps
CPU time 1.73 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206780 kb
Host smart-f786372f-5dbc-4452-88bc-dd0361bd19aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11717
09308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.1171709308
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.1700284335
Short name T171
Test name
Test status
Simulation time 4950565003 ps
CPU time 33.51 seconds
Started Jul 21 06:59:59 PM PDT 24
Finished Jul 21 07:00:34 PM PDT 24
Peak memory 206940 kb
Host smart-0bde4d79-cf6e-463b-9b03-50472ae5d050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17002
84335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.1700284335
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.3267162572
Short name T1217
Test name
Test status
Simulation time 73907204 ps
CPU time 0.72 seconds
Started Jul 21 07:00:10 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206708 kb
Host smart-c553e044-af75-4340-a499-0519cf2c0e65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3267162572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.3267162572
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.2467711724
Short name T939
Test name
Test status
Simulation time 3784568037 ps
CPU time 4.22 seconds
Started Jul 21 07:00:02 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206892 kb
Host smart-013fa1d7-354e-414b-a218-379b0f4d90af
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2467711724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.2467711724
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.1408414783
Short name T2337
Test name
Test status
Simulation time 13344350677 ps
CPU time 12.36 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:22 PM PDT 24
Peak memory 206904 kb
Host smart-ef8ab60b-f995-4003-af38-48bc8d75cfca
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1408414783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.1408414783
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2285347963
Short name T2704
Test name
Test status
Simulation time 23413108032 ps
CPU time 24.01 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:33 PM PDT 24
Peak memory 206892 kb
Host smart-9531ccd7-5795-4fd2-8b92-36a041704a98
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2285347963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2285347963
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.1187376729
Short name T1444
Test name
Test status
Simulation time 163121279 ps
CPU time 0.78 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206684 kb
Host smart-2589e226-8952-4dc5-8142-f9e963f249f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11873
76729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.1187376729
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.2244403528
Short name T2660
Test name
Test status
Simulation time 161662930 ps
CPU time 0.81 seconds
Started Jul 21 07:00:02 PM PDT 24
Finished Jul 21 07:00:06 PM PDT 24
Peak memory 206652 kb
Host smart-7f968032-1ae8-4f14-b8ee-ed27bfccef86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22444
03528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.2244403528
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.569192769
Short name T1812
Test name
Test status
Simulation time 341935312 ps
CPU time 1.1 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206696 kb
Host smart-f0fba1df-6e85-4f9e-bcf7-6c6a5ee7bb50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56919
2769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.569192769
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.294883602
Short name T1024
Test name
Test status
Simulation time 681381003 ps
CPU time 1.56 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206680 kb
Host smart-20822222-d508-42ef-a657-c7f70d931b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29488
3602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.294883602
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/46.usbdev_device_address.3436203718
Short name T1738
Test name
Test status
Simulation time 8515806942 ps
CPU time 14.88 seconds
Started Jul 21 07:00:31 PM PDT 24
Finished Jul 21 07:00:46 PM PDT 24
Peak memory 206876 kb
Host smart-8c2328f1-9ed4-4c4a-bb38-41284723bcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34362
03718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.3436203718
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.2994851788
Short name T2450
Test name
Test status
Simulation time 390510928 ps
CPU time 1.25 seconds
Started Jul 21 07:00:14 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206680 kb
Host smart-777295f9-231c-4c6d-b29e-cb112d50c35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29948
51788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.2994851788
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.3967155599
Short name T894
Test name
Test status
Simulation time 142621291 ps
CPU time 0.75 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206668 kb
Host smart-70698404-fbe3-4fb7-b368-d2503d36eb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39671
55599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.3967155599
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.3754375686
Short name T1518
Test name
Test status
Simulation time 35439211 ps
CPU time 0.63 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206624 kb
Host smart-b8a235fa-fd23-40e5-960c-c44085e2a68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37543
75686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.3754375686
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.4171163320
Short name T1102
Test name
Test status
Simulation time 1029711377 ps
CPU time 2.17 seconds
Started Jul 21 07:00:24 PM PDT 24
Finished Jul 21 07:00:27 PM PDT 24
Peak memory 206808 kb
Host smart-30c3f622-e1af-4f07-868a-e2c8020d7a12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711
63320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.4171163320
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.359125665
Short name T1744
Test name
Test status
Simulation time 240191013 ps
CPU time 1.43 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:19 PM PDT 24
Peak memory 206820 kb
Host smart-7ac6d39e-e547-413c-8c42-d83cd83242c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35912
5665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.359125665
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.3183983461
Short name T100
Test name
Test status
Simulation time 183039448 ps
CPU time 0.77 seconds
Started Jul 21 07:00:16 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206672 kb
Host smart-1e266f2c-7d43-4ae6-aece-d28cfbf9beab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31839
83461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.3183983461
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.991479444
Short name T884
Test name
Test status
Simulation time 138572966 ps
CPU time 0.8 seconds
Started Jul 21 07:00:03 PM PDT 24
Finished Jul 21 07:00:07 PM PDT 24
Peak memory 206656 kb
Host smart-68c14f90-a14b-40d3-9788-124c1406e4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99147
9444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.991479444
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.104420587
Short name T369
Test name
Test status
Simulation time 267420727 ps
CPU time 0.92 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:15 PM PDT 24
Peak memory 206656 kb
Host smart-1f3a5aa9-d3ae-415a-b034-ea8cfef94bb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10442
0587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.104420587
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_invalid_sync.536770974
Short name T1557
Test name
Test status
Simulation time 5228754274 ps
CPU time 132.8 seconds
Started Jul 21 07:00:22 PM PDT 24
Finished Jul 21 07:02:35 PM PDT 24
Peak memory 206924 kb
Host smart-c646d14f-3ce0-4216-828b-846dbcc7a4a9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=536770974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_invalid_sync.536770974
Directory /workspace/46.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/46.usbdev_iso_retraction.1250937534
Short name T1714
Test name
Test status
Simulation time 5601699847 ps
CPU time 49.47 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 206952 kb
Host smart-b51fd9da-4b6a-4dbd-8624-e42135ac8073
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12509
37534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_iso_retraction.1250937534
Directory /workspace/46.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.2197037061
Short name T1239
Test name
Test status
Simulation time 219409258 ps
CPU time 0.88 seconds
Started Jul 21 07:00:04 PM PDT 24
Finished Jul 21 07:00:08 PM PDT 24
Peak memory 206580 kb
Host smart-ecbf9ec4-3024-423c-8c51-7e0d16c8dc52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21970
37061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.2197037061
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.539234497
Short name T1285
Test name
Test status
Simulation time 23256802417 ps
CPU time 23.41 seconds
Started Jul 21 07:00:17 PM PDT 24
Finished Jul 21 07:00:42 PM PDT 24
Peak memory 206764 kb
Host smart-771542dc-3d28-44b7-8eef-340e1ea08df0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53923
4497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.539234497
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2708372870
Short name T2399
Test name
Test status
Simulation time 3330569024 ps
CPU time 3.76 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:15 PM PDT 24
Peak memory 206764 kb
Host smart-2cb422cd-8450-4784-9bc7-a9319b87c756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27083
72870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2708372870
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.1327629917
Short name T1139
Test name
Test status
Simulation time 7045294214 ps
CPU time 66.52 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:01:30 PM PDT 24
Peak memory 206932 kb
Host smart-c9c88dad-56cf-403e-913f-5773e7fd2097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13276
29917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.1327629917
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.2648684042
Short name T1349
Test name
Test status
Simulation time 4569361983 ps
CPU time 31.83 seconds
Started Jul 21 07:00:24 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 206928 kb
Host smart-1dea9599-e1be-4511-a243-f2cc5ace245a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2648684042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.2648684042
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.2247764045
Short name T2464
Test name
Test status
Simulation time 244846172 ps
CPU time 0.93 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206724 kb
Host smart-3a459ea7-d9be-43e1-845f-c38d810639a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2247764045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.2247764045
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.1180767053
Short name T2259
Test name
Test status
Simulation time 194148917 ps
CPU time 0.84 seconds
Started Jul 21 07:00:27 PM PDT 24
Finished Jul 21 07:00:29 PM PDT 24
Peak memory 206724 kb
Host smart-116fa4d3-b4fb-4f60-8729-665a79ad5d9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11807
67053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.1180767053
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.356343788
Short name T2071
Test name
Test status
Simulation time 4197081118 ps
CPU time 29.77 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:38 PM PDT 24
Peak memory 206884 kb
Host smart-aeedfa83-3ec1-40b8-af6e-e64ca1375368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35634
3788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.356343788
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.2967312032
Short name T691
Test name
Test status
Simulation time 3647807960 ps
CPU time 100.3 seconds
Started Jul 21 07:00:16 PM PDT 24
Finished Jul 21 07:01:58 PM PDT 24
Peak memory 206876 kb
Host smart-a6dbc30f-5065-40dc-ac56-e18590593af0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2967312032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.2967312032
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.3160345250
Short name T351
Test name
Test status
Simulation time 151611501 ps
CPU time 0.79 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:15 PM PDT 24
Peak memory 206652 kb
Host smart-76454cee-4ca9-44f6-b208-1f63c4ebeeb4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3160345250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.3160345250
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.822651028
Short name T1567
Test name
Test status
Simulation time 159886543 ps
CPU time 0.78 seconds
Started Jul 21 07:00:30 PM PDT 24
Finished Jul 21 07:00:31 PM PDT 24
Peak memory 206708 kb
Host smart-1edb03b7-c7ff-41b5-acae-250dea45542e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82265
1028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.822651028
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.1733216857
Short name T2133
Test name
Test status
Simulation time 180697058 ps
CPU time 0.82 seconds
Started Jul 21 07:00:08 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206664 kb
Host smart-bff1487f-16d6-4a80-a9ef-6948bfb268f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17332
16857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.1733216857
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.2510281271
Short name T2545
Test name
Test status
Simulation time 175602061 ps
CPU time 0.84 seconds
Started Jul 21 07:00:06 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206664 kb
Host smart-b0c240b2-f60e-43d0-8f8b-52311a31b6b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25102
81271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.2510281271
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.2356971629
Short name T2636
Test name
Test status
Simulation time 179511411 ps
CPU time 0.82 seconds
Started Jul 21 07:00:09 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206708 kb
Host smart-9d20457f-b908-4a8d-847e-d0c061bc8091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23569
71629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.2356971629
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.480585487
Short name T1571
Test name
Test status
Simulation time 198747362 ps
CPU time 0.82 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206692 kb
Host smart-3ede28d3-4508-4b66-9cbc-66797729edef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48058
5487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.480585487
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.796049505
Short name T2325
Test name
Test status
Simulation time 154562315 ps
CPU time 0.8 seconds
Started Jul 21 07:00:30 PM PDT 24
Finished Jul 21 07:00:31 PM PDT 24
Peak memory 206728 kb
Host smart-4ac6618a-4c33-4cea-93eb-a41cd3186075
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79604
9505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.796049505
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.710260550
Short name T614
Test name
Test status
Simulation time 201706063 ps
CPU time 0.85 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206684 kb
Host smart-96c3601f-a0c2-439e-9dcb-47569278f047
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=710260550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.710260550
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.979528112
Short name T1532
Test name
Test status
Simulation time 151262770 ps
CPU time 0.81 seconds
Started Jul 21 07:00:09 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206648 kb
Host smart-bbcb8bc5-89d0-4dfc-ad1b-79e7b14dc336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97952
8112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.979528112
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1329106478
Short name T1659
Test name
Test status
Simulation time 33440514 ps
CPU time 0.63 seconds
Started Jul 21 07:00:20 PM PDT 24
Finished Jul 21 07:00:21 PM PDT 24
Peak memory 206724 kb
Host smart-fca3507a-03d4-4ab2-a526-71f9ac91809e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13291
06478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1329106478
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.4113058283
Short name T1127
Test name
Test status
Simulation time 21966655514 ps
CPU time 45.27 seconds
Started Jul 21 07:00:09 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 206912 kb
Host smart-bf1009c6-0520-4653-a751-1f39d0e51106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41130
58283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.4113058283
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1292992219
Short name T1220
Test name
Test status
Simulation time 186294877 ps
CPU time 0.83 seconds
Started Jul 21 07:00:27 PM PDT 24
Finished Jul 21 07:00:29 PM PDT 24
Peak memory 206704 kb
Host smart-791b4213-e6c5-4081-8499-8f192fec04dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12929
92219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1292992219
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.301538565
Short name T992
Test name
Test status
Simulation time 217616447 ps
CPU time 0.88 seconds
Started Jul 21 07:00:05 PM PDT 24
Finished Jul 21 07:00:09 PM PDT 24
Peak memory 206632 kb
Host smart-8905a5b2-4b44-4739-bb59-719e5f1e017d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30153
8565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.301538565
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.1951904318
Short name T922
Test name
Test status
Simulation time 235533053 ps
CPU time 0.9 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206608 kb
Host smart-cdaf5b7b-3aaa-414f-a634-03fd4509f41b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19519
04318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.1951904318
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.745172355
Short name T492
Test name
Test status
Simulation time 187011569 ps
CPU time 0.81 seconds
Started Jul 21 07:00:25 PM PDT 24
Finished Jul 21 07:00:26 PM PDT 24
Peak memory 206704 kb
Host smart-33bc5a60-93b6-4974-8d60-ce4d1f042438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74517
2355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.745172355
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.3254024500
Short name T67
Test name
Test status
Simulation time 144515243 ps
CPU time 0.75 seconds
Started Jul 21 07:00:10 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206664 kb
Host smart-2b480298-d35a-4d8a-b4f4-37c7a560ecb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32540
24500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.3254024500
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.3685940655
Short name T455
Test name
Test status
Simulation time 171347261 ps
CPU time 0.87 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206676 kb
Host smart-43e3f2ad-83b1-42dc-8def-22c729134e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36859
40655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.3685940655
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.1677861467
Short name T1143
Test name
Test status
Simulation time 168317280 ps
CPU time 0.81 seconds
Started Jul 21 07:00:27 PM PDT 24
Finished Jul 21 07:00:28 PM PDT 24
Peak memory 206696 kb
Host smart-bdeaa254-fb36-4e8a-bda7-1be52006f83c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16778
61467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.1677861467
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.2308955031
Short name T2202
Test name
Test status
Simulation time 206338008 ps
CPU time 0.89 seconds
Started Jul 21 07:00:07 PM PDT 24
Finished Jul 21 07:00:10 PM PDT 24
Peak memory 206660 kb
Host smart-7b44bead-cfe0-4e03-a2d4-cf21108e6dcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23089
55031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.2308955031
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.1420126248
Short name T2106
Test name
Test status
Simulation time 4690485455 ps
CPU time 123.76 seconds
Started Jul 21 07:00:09 PM PDT 24
Finished Jul 21 07:02:15 PM PDT 24
Peak memory 206972 kb
Host smart-3357ea01-87c1-4154-832f-e0149d9dbf6e
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1420126248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.1420126248
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3274107714
Short name T2232
Test name
Test status
Simulation time 147090589 ps
CPU time 0.8 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:00:24 PM PDT 24
Peak memory 206676 kb
Host smart-38186e79-1dff-4064-a4a6-a56c622acf69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32741
07714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3274107714
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2987516662
Short name T2451
Test name
Test status
Simulation time 222914372 ps
CPU time 0.86 seconds
Started Jul 21 07:00:10 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206680 kb
Host smart-069189f9-773c-427b-a68b-94a13cae91ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29875
16662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2987516662
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.3125982125
Short name T2487
Test name
Test status
Simulation time 1395297229 ps
CPU time 2.7 seconds
Started Jul 21 07:00:21 PM PDT 24
Finished Jul 21 07:00:24 PM PDT 24
Peak memory 206848 kb
Host smart-86a88751-5ac3-4619-b79d-9fede157e559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31259
82125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.3125982125
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3571300544
Short name T1814
Test name
Test status
Simulation time 4492297823 ps
CPU time 43.65 seconds
Started Jul 21 07:00:26 PM PDT 24
Finished Jul 21 07:01:10 PM PDT 24
Peak memory 206944 kb
Host smart-b76bd883-1407-4c9f-a740-e68c22134a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35713
00544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3571300544
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.371819307
Short name T2473
Test name
Test status
Simulation time 82922578 ps
CPU time 0.74 seconds
Started Jul 21 07:00:27 PM PDT 24
Finished Jul 21 07:00:28 PM PDT 24
Peak memory 206732 kb
Host smart-76e48513-c02a-40b7-9f8a-e24895bbe190
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=371819307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.371819307
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.2444304613
Short name T1313
Test name
Test status
Simulation time 4090486688 ps
CPU time 5.66 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:22 PM PDT 24
Peak memory 206716 kb
Host smart-95641e33-586f-426f-b970-6864dd83d687
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2444304613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.2444304613
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.976936400
Short name T1122
Test name
Test status
Simulation time 13368833930 ps
CPU time 13.01 seconds
Started Jul 21 07:00:14 PM PDT 24
Finished Jul 21 07:00:28 PM PDT 24
Peak memory 206728 kb
Host smart-88715157-acd0-409f-8ece-934d373f43a5
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=976936400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.976936400
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.4254234189
Short name T10
Test name
Test status
Simulation time 23364313367 ps
CPU time 24.47 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:38 PM PDT 24
Peak memory 206808 kb
Host smart-b081a855-4da9-4e3b-abce-45f1d1c7b919
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4254234189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.4254234189
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.3327827200
Short name T1087
Test name
Test status
Simulation time 252164695 ps
CPU time 0.93 seconds
Started Jul 21 07:00:10 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206680 kb
Host smart-212a92b3-3008-4c0d-b2d8-67e148ace86a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33278
27200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.3327827200
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.199768782
Short name T1066
Test name
Test status
Simulation time 159529604 ps
CPU time 0.83 seconds
Started Jul 21 07:00:17 PM PDT 24
Finished Jul 21 07:00:19 PM PDT 24
Peak memory 206668 kb
Host smart-5c7ce253-0873-4cd2-bf49-326d370a8f28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19976
8782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.199768782
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.159457615
Short name T858
Test name
Test status
Simulation time 553024020 ps
CPU time 1.54 seconds
Started Jul 21 07:00:26 PM PDT 24
Finished Jul 21 07:00:28 PM PDT 24
Peak memory 206832 kb
Host smart-99abdd4f-e8c0-420d-bc9d-bc27e447e165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15945
7615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.159457615
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.1837974192
Short name T1703
Test name
Test status
Simulation time 701822842 ps
CPU time 1.71 seconds
Started Jul 21 07:00:09 PM PDT 24
Finished Jul 21 07:00:13 PM PDT 24
Peak memory 206808 kb
Host smart-c17b95bf-e3a5-42e5-95d6-6b2f9e65a8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18379
74192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.1837974192
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3933864037
Short name T2392
Test name
Test status
Simulation time 10325989721 ps
CPU time 22.49 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:36 PM PDT 24
Peak memory 206928 kb
Host smart-a8780017-6842-4f01-b2da-f1158d2a77b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39338
64037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3933864037
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.1575178588
Short name T629
Test name
Test status
Simulation time 335100920 ps
CPU time 1.13 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:00:25 PM PDT 24
Peak memory 206676 kb
Host smart-4238fda2-fa36-45cc-829f-b51e7af85e02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15751
78588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.1575178588
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.2608466714
Short name T786
Test name
Test status
Simulation time 140989572 ps
CPU time 0.77 seconds
Started Jul 21 07:00:20 PM PDT 24
Finished Jul 21 07:00:22 PM PDT 24
Peak memory 206632 kb
Host smart-df171a35-5d85-4e04-acb6-3ecad8afc6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
66714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.2608466714
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.1478643683
Short name T224
Test name
Test status
Simulation time 67702505 ps
CPU time 0.67 seconds
Started Jul 21 07:00:08 PM PDT 24
Finished Jul 21 07:00:11 PM PDT 24
Peak memory 206684 kb
Host smart-015dfc6a-3ecf-4b31-b0da-a82b33b68fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14786
43683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.1478643683
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.1304135678
Short name T1947
Test name
Test status
Simulation time 867848006 ps
CPU time 1.97 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:16 PM PDT 24
Peak memory 206804 kb
Host smart-93ae9550-4774-4a37-97c1-3a9c9dbf0ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13041
35678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.1304135678
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.3785337846
Short name T651
Test name
Test status
Simulation time 223969964 ps
CPU time 1.44 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:21 PM PDT 24
Peak memory 206824 kb
Host smart-60cb34d9-daeb-4726-9464-220887773c25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37853
37846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.3785337846
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.2264329088
Short name T305
Test name
Test status
Simulation time 298901614 ps
CPU time 0.97 seconds
Started Jul 21 07:00:26 PM PDT 24
Finished Jul 21 07:00:27 PM PDT 24
Peak memory 206648 kb
Host smart-b8731647-a86b-4f95-8480-617310c55469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22643
29088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.2264329088
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.1738978157
Short name T311
Test name
Test status
Simulation time 183709195 ps
CPU time 0.8 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:21 PM PDT 24
Peak memory 206560 kb
Host smart-795690f0-570a-49eb-82a6-ecb8f16150b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17389
78157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.1738978157
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.915745845
Short name T1579
Test name
Test status
Simulation time 168350736 ps
CPU time 0.85 seconds
Started Jul 21 07:00:26 PM PDT 24
Finished Jul 21 07:00:27 PM PDT 24
Peak memory 206660 kb
Host smart-5db89f14-389a-4db2-8f38-c2a1fb28f7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91574
5845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.915745845
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1142124710
Short name T440
Test name
Test status
Simulation time 8323678107 ps
CPU time 30.26 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:43 PM PDT 24
Peak memory 206940 kb
Host smart-44f90205-ab3d-4246-8a9e-da60993176ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11421
24710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1142124710
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.1763244600
Short name T295
Test name
Test status
Simulation time 214576427 ps
CPU time 0.87 seconds
Started Jul 21 07:00:13 PM PDT 24
Finished Jul 21 07:00:15 PM PDT 24
Peak memory 206660 kb
Host smart-ebe41eae-12e6-4220-b53d-cc5922debbbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17632
44600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.1763244600
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.867283758
Short name T2572
Test name
Test status
Simulation time 23359667160 ps
CPU time 21.46 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 206760 kb
Host smart-58c4f6fe-adaa-48b4-99de-8b2e7cc4317d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86728
3758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.867283758
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.1255137113
Short name T2714
Test name
Test status
Simulation time 3280484998 ps
CPU time 3.74 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:17 PM PDT 24
Peak memory 206768 kb
Host smart-7383c69d-e3f8-4bd4-b01e-7fa7b88e6eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12551
37113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.1255137113
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2975786525
Short name T1626
Test name
Test status
Simulation time 10773539848 ps
CPU time 296.03 seconds
Started Jul 21 07:00:14 PM PDT 24
Finished Jul 21 07:05:11 PM PDT 24
Peak memory 206928 kb
Host smart-08a5f5e5-fd69-40a7-b4bd-a97aa65a00e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29757
86525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2975786525
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.3855007757
Short name T1229
Test name
Test status
Simulation time 8042374050 ps
CPU time 221.97 seconds
Started Jul 21 07:00:16 PM PDT 24
Finished Jul 21 07:04:00 PM PDT 24
Peak memory 206868 kb
Host smart-9b6930a3-1539-4836-811f-c5a9c3c8075d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3855007757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.3855007757
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.3785061224
Short name T16
Test name
Test status
Simulation time 241811003 ps
CPU time 0.91 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:13 PM PDT 24
Peak memory 206720 kb
Host smart-053d1331-e412-4c20-ad96-fdb224a02890
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3785061224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.3785061224
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.1313339155
Short name T207
Test name
Test status
Simulation time 188216666 ps
CPU time 0.84 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206560 kb
Host smart-407002a9-6cfc-48d6-8392-c392d3d4f774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13133
39155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.1313339155
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.1980119673
Short name T148
Test name
Test status
Simulation time 4370266877 ps
CPU time 112.18 seconds
Started Jul 21 07:00:30 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 206936 kb
Host smart-9362ad7d-d779-4373-8709-7354b719f805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19801
19673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.1980119673
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.3479412124
Short name T1037
Test name
Test status
Simulation time 5949951292 ps
CPU time 39.78 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 206936 kb
Host smart-9e5ca90f-16cb-42a9-97a6-ab8f84d684d8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3479412124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.3479412124
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.896243534
Short name T388
Test name
Test status
Simulation time 161907117 ps
CPU time 0.81 seconds
Started Jul 21 07:00:21 PM PDT 24
Finished Jul 21 07:00:23 PM PDT 24
Peak memory 206680 kb
Host smart-bde70948-0562-4a46-a9db-572c4b57d566
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=896243534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.896243534
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.2281606153
Short name T304
Test name
Test status
Simulation time 141364581 ps
CPU time 0.76 seconds
Started Jul 21 07:00:16 PM PDT 24
Finished Jul 21 07:00:19 PM PDT 24
Peak memory 206652 kb
Host smart-5e079e39-12cf-4994-a94f-e4f9fb62f9a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22816
06153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.2281606153
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.576256710
Short name T1144
Test name
Test status
Simulation time 198877136 ps
CPU time 0.9 seconds
Started Jul 21 07:00:25 PM PDT 24
Finished Jul 21 07:00:26 PM PDT 24
Peak memory 206688 kb
Host smart-931c0754-8695-4904-ad0d-5d7512be4f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57625
6710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.576256710
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3244119374
Short name T2568
Test name
Test status
Simulation time 167407183 ps
CPU time 0.83 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:13 PM PDT 24
Peak memory 206632 kb
Host smart-0f9571db-fbc9-45d0-ab96-3d2350df7c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32441
19374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3244119374
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.290770457
Short name T927
Test name
Test status
Simulation time 148311323 ps
CPU time 0.76 seconds
Started Jul 21 07:00:11 PM PDT 24
Finished Jul 21 07:00:12 PM PDT 24
Peak memory 206676 kb
Host smart-f54edb9e-6aac-4966-ab16-fd650b185be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29077
0457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.290770457
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.4128137127
Short name T1224
Test name
Test status
Simulation time 170708501 ps
CPU time 0.79 seconds
Started Jul 21 07:00:12 PM PDT 24
Finished Jul 21 07:00:14 PM PDT 24
Peak memory 206652 kb
Host smart-fd9b7c72-55d1-4180-9a2b-1d5ed5a67862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41281
37127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.4128137127
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.631981213
Short name T1820
Test name
Test status
Simulation time 225246758 ps
CPU time 0.86 seconds
Started Jul 21 07:00:25 PM PDT 24
Finished Jul 21 07:00:26 PM PDT 24
Peak memory 206704 kb
Host smart-02bccd7e-67e9-4f5f-92aa-4a8fc441ac45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63198
1213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.631981213
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.1693744273
Short name T973
Test name
Test status
Simulation time 221308246 ps
CPU time 0.91 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:17 PM PDT 24
Peak memory 206660 kb
Host smart-d32e4f50-2781-4001-a73c-672bf660ad37
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1693744273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.1693744273
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.34593911
Short name T1490
Test name
Test status
Simulation time 147723550 ps
CPU time 0.78 seconds
Started Jul 21 07:00:32 PM PDT 24
Finished Jul 21 07:00:34 PM PDT 24
Peak memory 206672 kb
Host smart-203d7866-9f00-448e-8b5a-ce09fc6af93d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34593
911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.34593911
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.998072499
Short name T349
Test name
Test status
Simulation time 38045085 ps
CPU time 0.66 seconds
Started Jul 21 07:00:21 PM PDT 24
Finished Jul 21 07:00:22 PM PDT 24
Peak memory 206636 kb
Host smart-f4a0670d-668d-485c-b0b1-50ed05a28591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99807
2499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.998072499
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.3169075934
Short name T1757
Test name
Test status
Simulation time 19751981604 ps
CPU time 42.45 seconds
Started Jul 21 07:00:21 PM PDT 24
Finished Jul 21 07:01:04 PM PDT 24
Peak memory 206944 kb
Host smart-fed4a85b-8efd-4c28-9001-77c604f93bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31690
75934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.3169075934
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.3544361835
Short name T2643
Test name
Test status
Simulation time 181134456 ps
CPU time 0.82 seconds
Started Jul 21 07:00:16 PM PDT 24
Finished Jul 21 07:00:19 PM PDT 24
Peak memory 206568 kb
Host smart-a6026533-5281-4879-b19a-f2ea0dba484c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35443
61835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.3544361835
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2912037667
Short name T2310
Test name
Test status
Simulation time 199840973 ps
CPU time 0.92 seconds
Started Jul 21 07:00:34 PM PDT 24
Finished Jul 21 07:00:36 PM PDT 24
Peak memory 206664 kb
Host smart-0af20212-87f6-417a-9a7d-89be64e40e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29120
37667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2912037667
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.206081276
Short name T390
Test name
Test status
Simulation time 183302915 ps
CPU time 0.82 seconds
Started Jul 21 07:00:35 PM PDT 24
Finished Jul 21 07:00:37 PM PDT 24
Peak memory 206652 kb
Host smart-fce57175-88b1-48b3-9f25-d102d4c98fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20608
1276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.206081276
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3937181322
Short name T1345
Test name
Test status
Simulation time 145580050 ps
CPU time 0.77 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206628 kb
Host smart-a7f8aa00-a661-4088-86ea-4b3bdc25504f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39371
81322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3937181322
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2310595197
Short name T2695
Test name
Test status
Simulation time 144806049 ps
CPU time 0.75 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206684 kb
Host smart-9fd07e92-0fd3-4fc4-b410-1a2152f7bd5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23105
95197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2310595197
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3808936004
Short name T1641
Test name
Test status
Simulation time 166553608 ps
CPU time 0.79 seconds
Started Jul 21 07:00:17 PM PDT 24
Finished Jul 21 07:00:19 PM PDT 24
Peak memory 206660 kb
Host smart-5ae6cf24-ed73-47d7-93bb-6986ec6cb803
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38089
36004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3808936004
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2070445918
Short name T2441
Test name
Test status
Simulation time 201469899 ps
CPU time 0.81 seconds
Started Jul 21 07:00:26 PM PDT 24
Finished Jul 21 07:00:27 PM PDT 24
Peak memory 206664 kb
Host smart-9109ec5c-4052-4738-9485-84dffd0f4c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20704
45918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2070445918
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.2796981691
Short name T1075
Test name
Test status
Simulation time 252719280 ps
CPU time 0.96 seconds
Started Jul 21 07:00:22 PM PDT 24
Finished Jul 21 07:00:24 PM PDT 24
Peak memory 206620 kb
Host smart-d76c2ffd-a415-4748-bb64-41a198da53fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27969
81691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.2796981691
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.1004436813
Short name T721
Test name
Test status
Simulation time 3327320483 ps
CPU time 89.72 seconds
Started Jul 21 07:00:29 PM PDT 24
Finished Jul 21 07:01:59 PM PDT 24
Peak memory 206860 kb
Host smart-b1d729ec-f958-40ba-b63d-4016f7472d41
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1004436813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.1004436813
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.4120988712
Short name T1374
Test name
Test status
Simulation time 164395291 ps
CPU time 0.78 seconds
Started Jul 21 07:00:16 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206680 kb
Host smart-8367a168-c660-49b6-8aa0-0e9b74d4c111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41209
88712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.4120988712
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.649152619
Short name T1499
Test name
Test status
Simulation time 153596378 ps
CPU time 0.87 seconds
Started Jul 21 07:00:32 PM PDT 24
Finished Jul 21 07:00:34 PM PDT 24
Peak memory 206676 kb
Host smart-e811e1a5-8463-42ed-819f-195f71b3e495
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64915
2619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.649152619
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.1662565649
Short name T2644
Test name
Test status
Simulation time 1101705813 ps
CPU time 2.37 seconds
Started Jul 21 07:00:44 PM PDT 24
Finished Jul 21 07:00:47 PM PDT 24
Peak memory 206776 kb
Host smart-e0e470d9-b77e-43fc-b227-f859e5801582
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16625
65649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.1662565649
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.545948863
Short name T602
Test name
Test status
Simulation time 4252288729 ps
CPU time 115.99 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:02:19 PM PDT 24
Peak memory 206952 kb
Host smart-3b05f629-ab72-4cde-9e80-d368662794b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54594
8863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.545948863
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3511201597
Short name T178
Test name
Test status
Simulation time 31911050 ps
CPU time 0.65 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206724 kb
Host smart-267ad92b-8274-491d-b32a-ef0b1dd2a1dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3511201597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3511201597
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.853320329
Short name T2701
Test name
Test status
Simulation time 4099349646 ps
CPU time 5.42 seconds
Started Jul 21 07:00:34 PM PDT 24
Finished Jul 21 07:00:39 PM PDT 24
Peak memory 206740 kb
Host smart-6126609d-d5aa-470c-8e82-cab00ef8a697
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=853320329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.853320329
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.722721384
Short name T953
Test name
Test status
Simulation time 13352227237 ps
CPU time 12.96 seconds
Started Jul 21 07:00:24 PM PDT 24
Finished Jul 21 07:00:38 PM PDT 24
Peak memory 206788 kb
Host smart-4ccb905e-479f-4284-8693-0e14a7d31a2c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=722721384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.722721384
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2768566550
Short name T1093
Test name
Test status
Simulation time 23321353818 ps
CPU time 25.81 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206816 kb
Host smart-bf4d22a5-099c-4c43-9179-d554d489121f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2768566550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.2768566550
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.1051851933
Short name T149
Test name
Test status
Simulation time 151404881 ps
CPU time 0.78 seconds
Started Jul 21 07:00:15 PM PDT 24
Finished Jul 21 07:00:18 PM PDT 24
Peak memory 206680 kb
Host smart-8cd4aa5f-49ae-4bf2-ad82-c7d68630afd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10518
51933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.1051851933
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.747433276
Short name T1464
Test name
Test status
Simulation time 201576007 ps
CPU time 0.85 seconds
Started Jul 21 07:00:23 PM PDT 24
Finished Jul 21 07:00:25 PM PDT 24
Peak memory 206708 kb
Host smart-bfa92173-3a50-4747-8270-4d2b2bfa10b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74743
3276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.747433276
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.1625377969
Short name T568
Test name
Test status
Simulation time 263099546 ps
CPU time 1.02 seconds
Started Jul 21 07:00:16 PM PDT 24
Finished Jul 21 07:00:23 PM PDT 24
Peak memory 206656 kb
Host smart-7ac08f74-8192-458d-b090-cc826be591f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16253
77969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.1625377969
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.2518350759
Short name T480
Test name
Test status
Simulation time 1280146702 ps
CPU time 2.78 seconds
Started Jul 21 07:00:17 PM PDT 24
Finished Jul 21 07:00:21 PM PDT 24
Peak memory 206748 kb
Host smart-9c2fc614-1f8f-4544-b129-f3c76cfeda95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25183
50759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.2518350759
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.164129454
Short name T661
Test name
Test status
Simulation time 16529752667 ps
CPU time 32.93 seconds
Started Jul 21 07:00:36 PM PDT 24
Finished Jul 21 07:01:09 PM PDT 24
Peak memory 206960 kb
Host smart-e307d85e-fc46-476d-8842-5b790677696c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16412
9454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.164129454
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2894178382
Short name T1949
Test name
Test status
Simulation time 387357995 ps
CPU time 1.21 seconds
Started Jul 21 07:00:38 PM PDT 24
Finished Jul 21 07:00:40 PM PDT 24
Peak memory 206680 kb
Host smart-54b03869-f1da-4d37-8425-c0162d7f4a6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28941
78382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2894178382
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.3052563450
Short name T1727
Test name
Test status
Simulation time 146766780 ps
CPU time 0.78 seconds
Started Jul 21 07:00:42 PM PDT 24
Finished Jul 21 07:00:44 PM PDT 24
Peak memory 206652 kb
Host smart-81b15794-8a7c-4f00-91a9-60e482d6a7bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30525
63450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.3052563450
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.3480933780
Short name T891
Test name
Test status
Simulation time 39549905 ps
CPU time 0.77 seconds
Started Jul 21 07:00:38 PM PDT 24
Finished Jul 21 07:00:39 PM PDT 24
Peak memory 206672 kb
Host smart-05bdea62-a524-4a6b-b655-edc01c8819bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34809
33780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.3480933780
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.2585267792
Short name T1658
Test name
Test status
Simulation time 756231061 ps
CPU time 1.93 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 206752 kb
Host smart-6dae9cbc-14fc-436a-85fe-d0495ef6d2c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25852
67792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.2585267792
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.3272075923
Short name T920
Test name
Test status
Simulation time 205558018 ps
CPU time 1.84 seconds
Started Jul 21 07:00:44 PM PDT 24
Finished Jul 21 07:00:47 PM PDT 24
Peak memory 206788 kb
Host smart-2c2ce96b-14b6-46fe-a527-d49452f17198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32720
75923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.3272075923
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.1146540419
Short name T2282
Test name
Test status
Simulation time 223679902 ps
CPU time 0.92 seconds
Started Jul 21 07:00:30 PM PDT 24
Finished Jul 21 07:00:31 PM PDT 24
Peak memory 206652 kb
Host smart-2e1f20e9-3489-4a27-bfe2-becb493f96f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11465
40419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.1146540419
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.2939790115
Short name T850
Test name
Test status
Simulation time 156450416 ps
CPU time 0.81 seconds
Started Jul 21 07:00:35 PM PDT 24
Finished Jul 21 07:00:36 PM PDT 24
Peak memory 206628 kb
Host smart-07404d00-b829-4ecc-829d-04eaa991642a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29397
90115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.2939790115
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2291029446
Short name T2678
Test name
Test status
Simulation time 207880886 ps
CPU time 0.87 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206628 kb
Host smart-50bc557d-e62a-42b3-ad83-e9fa9cb6c54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22910
29446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2291029446
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.2268747979
Short name T214
Test name
Test status
Simulation time 6460831483 ps
CPU time 176.62 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:03:46 PM PDT 24
Peak memory 206856 kb
Host smart-d9291498-b0d3-4eb0-b983-900efd396257
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2268747979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.2268747979
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_iso_retraction.2454413495
Short name T1317
Test name
Test status
Simulation time 14268817554 ps
CPU time 47.02 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:01:37 PM PDT 24
Peak memory 206936 kb
Host smart-ac2ad9ad-d686-440a-b50d-8ab6b9b96bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24544
13495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_iso_retraction.2454413495
Directory /workspace/48.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.437495432
Short name T1978
Test name
Test status
Simulation time 158840747 ps
CPU time 0.84 seconds
Started Jul 21 07:00:34 PM PDT 24
Finished Jul 21 07:00:36 PM PDT 24
Peak memory 206656 kb
Host smart-04da5ea7-51e7-4250-a601-9677639f5fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43749
5432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.437495432
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.645156398
Short name T713
Test name
Test status
Simulation time 23367864658 ps
CPU time 22.53 seconds
Started Jul 21 07:00:35 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 206792 kb
Host smart-38ed6c38-bc2d-4102-b817-551dbef31a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64515
6398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.645156398
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.255771964
Short name T919
Test name
Test status
Simulation time 3256133597 ps
CPU time 4.02 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:54 PM PDT 24
Peak memory 206728 kb
Host smart-5925e7fe-b885-4e7c-8543-fc91d108bac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25577
1964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.255771964
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.2551910182
Short name T478
Test name
Test status
Simulation time 9766261770 ps
CPU time 271.92 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:05:15 PM PDT 24
Peak memory 206948 kb
Host smart-9c64dc7e-2b31-45b2-a9a9-3714494fe467
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25519
10182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.2551910182
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.283857697
Short name T514
Test name
Test status
Simulation time 4762183194 ps
CPU time 34.66 seconds
Started Jul 21 07:00:38 PM PDT 24
Finished Jul 21 07:01:13 PM PDT 24
Peak memory 206860 kb
Host smart-eb590fb6-8094-4bc0-ada5-8c623be942a2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=283857697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.283857697
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.78514541
Short name T1237
Test name
Test status
Simulation time 310306048 ps
CPU time 0.95 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206680 kb
Host smart-9ffa3e5f-71da-47f7-8f21-4d24c4e8bc35
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=78514541 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.78514541
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.1551616509
Short name T2584
Test name
Test status
Simulation time 207164265 ps
CPU time 0.92 seconds
Started Jul 21 07:00:35 PM PDT 24
Finished Jul 21 07:00:36 PM PDT 24
Peak memory 206668 kb
Host smart-bb15ee82-cf2b-4313-8e99-3caeb7223124
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15516
16509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.1551616509
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3685104379
Short name T140
Test name
Test status
Simulation time 4194439559 ps
CPU time 29.29 seconds
Started Jul 21 07:00:46 PM PDT 24
Finished Jul 21 07:01:15 PM PDT 24
Peak memory 206876 kb
Host smart-6c5236f9-deb4-44a1-9418-004067f7a957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36851
04379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3685104379
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.865299238
Short name T1773
Test name
Test status
Simulation time 4631310419 ps
CPU time 42.48 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:01:26 PM PDT 24
Peak memory 206900 kb
Host smart-41622e1b-4e6d-4da8-98d3-18eebe0089bf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=865299238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.865299238
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.3245698261
Short name T2430
Test name
Test status
Simulation time 158800404 ps
CPU time 0.89 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 206564 kb
Host smart-edd99169-35c4-4034-a87b-3239793ba106
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3245698261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.3245698261
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.2469791766
Short name T1152
Test name
Test status
Simulation time 150414917 ps
CPU time 0.76 seconds
Started Jul 21 07:00:37 PM PDT 24
Finished Jul 21 07:00:38 PM PDT 24
Peak memory 206700 kb
Host smart-353ffbe3-15df-4593-8672-10a14a886281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24697
91766 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.2469791766
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1661091883
Short name T2495
Test name
Test status
Simulation time 228856305 ps
CPU time 0.87 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 206660 kb
Host smart-c08de6cc-1259-435d-a827-edfc3496551a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16610
91883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1661091883
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.2928375250
Short name T483
Test name
Test status
Simulation time 166212076 ps
CPU time 0.82 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206668 kb
Host smart-72535d14-98f8-4da1-b8c0-c12d7902bf25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29283
75250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.2928375250
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.1465718038
Short name T2465
Test name
Test status
Simulation time 172609040 ps
CPU time 0.83 seconds
Started Jul 21 07:00:45 PM PDT 24
Finished Jul 21 07:00:47 PM PDT 24
Peak memory 206660 kb
Host smart-eb6531f1-43f7-47ab-9ebb-e860a7b8562d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14657
18038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.1465718038
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.2663752819
Short name T2417
Test name
Test status
Simulation time 195750986 ps
CPU time 0.8 seconds
Started Jul 21 07:00:44 PM PDT 24
Finished Jul 21 07:00:46 PM PDT 24
Peak memory 206656 kb
Host smart-2b9409f3-199f-4611-b136-9c220e73d3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26637
52819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.2663752819
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2480716095
Short name T555
Test name
Test status
Simulation time 164153187 ps
CPU time 0.79 seconds
Started Jul 21 07:00:41 PM PDT 24
Finished Jul 21 07:00:42 PM PDT 24
Peak memory 206664 kb
Host smart-4682c44f-f5c0-4784-a8e7-8a97e4bc988f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24807
16095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2480716095
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1015193076
Short name T2224
Test name
Test status
Simulation time 292337607 ps
CPU time 0.99 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:52 PM PDT 24
Peak memory 206684 kb
Host smart-b420779f-372c-4fb6-88f3-03399c4864db
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1015193076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1015193076
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.2631025924
Short name T2190
Test name
Test status
Simulation time 142597009 ps
CPU time 0.8 seconds
Started Jul 21 07:00:45 PM PDT 24
Finished Jul 21 07:00:47 PM PDT 24
Peak memory 206672 kb
Host smart-4dc95c5b-4b7c-4574-a739-46d7bacc0695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26310
25924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.2631025924
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.2145711859
Short name T1784
Test name
Test status
Simulation time 31492835 ps
CPU time 0.65 seconds
Started Jul 21 07:00:33 PM PDT 24
Finished Jul 21 07:00:34 PM PDT 24
Peak memory 206632 kb
Host smart-6315795d-2278-4d2a-8cfd-2ebd8340c704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21457
11859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.2145711859
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.238754352
Short name T1496
Test name
Test status
Simulation time 16711549403 ps
CPU time 39.39 seconds
Started Jul 21 07:00:45 PM PDT 24
Finished Jul 21 07:01:25 PM PDT 24
Peak memory 206912 kb
Host smart-a648d468-9c53-4557-b58f-d10e4f5c8ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23875
4352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.238754352
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.2382819796
Short name T2350
Test name
Test status
Simulation time 235181748 ps
CPU time 0.92 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 206696 kb
Host smart-21e91e27-27dd-484d-bb24-4ce933a53f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23828
19796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.2382819796
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.2442804980
Short name T457
Test name
Test status
Simulation time 204703444 ps
CPU time 0.88 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:52 PM PDT 24
Peak memory 206680 kb
Host smart-20db6c13-8a1b-4017-92ca-d01fbc1639c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24428
04980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.2442804980
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.2190211730
Short name T792
Test name
Test status
Simulation time 194325649 ps
CPU time 0.81 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:50 PM PDT 24
Peak memory 206692 kb
Host smart-6d83e2a0-3ae0-46a3-9e38-81c5782310ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21902
11730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.2190211730
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.4271161250
Short name T476
Test name
Test status
Simulation time 165844281 ps
CPU time 0.81 seconds
Started Jul 21 07:00:46 PM PDT 24
Finished Jul 21 07:00:48 PM PDT 24
Peak memory 206656 kb
Host smart-b2900844-5dee-448f-a4ed-6e9591d43b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42711
61250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.4271161250
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.3823075794
Short name T66
Test name
Test status
Simulation time 170742869 ps
CPU time 0.81 seconds
Started Jul 21 07:00:34 PM PDT 24
Finished Jul 21 07:00:35 PM PDT 24
Peak memory 206680 kb
Host smart-1df98a23-57c2-4d78-88a0-69db53292904
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38230
75794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.3823075794
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3173391365
Short name T632
Test name
Test status
Simulation time 146095471 ps
CPU time 0.82 seconds
Started Jul 21 07:00:37 PM PDT 24
Finished Jul 21 07:00:39 PM PDT 24
Peak memory 206680 kb
Host smart-46491a12-a384-4930-8df2-f7e4905ce5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31733
91365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3173391365
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2253803828
Short name T2030
Test name
Test status
Simulation time 146612649 ps
CPU time 0.79 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206652 kb
Host smart-8d875e19-fe59-4575-a6a0-cb9f0ce80d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22538
03828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2253803828
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2213376173
Short name T363
Test name
Test status
Simulation time 222819991 ps
CPU time 0.98 seconds
Started Jul 21 07:00:38 PM PDT 24
Finished Jul 21 07:00:39 PM PDT 24
Peak memory 206688 kb
Host smart-7fb1cac0-ac35-45f4-8592-d07c2eb8ef25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
76173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2213376173
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.3131085430
Short name T647
Test name
Test status
Simulation time 5002631196 ps
CPU time 45.17 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:01:34 PM PDT 24
Peak memory 206872 kb
Host smart-708dd0d5-7d07-48f2-8b3c-3939d905afc0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3131085430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.3131085430
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.876194580
Short name T1184
Test name
Test status
Simulation time 183247735 ps
CPU time 0.87 seconds
Started Jul 21 07:00:44 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 206680 kb
Host smart-562f404a-9003-41aa-a7cf-6a6788447a1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87619
4580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.876194580
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.2651732217
Short name T726
Test name
Test status
Simulation time 145441507 ps
CPU time 0.79 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:00:44 PM PDT 24
Peak memory 206664 kb
Host smart-14fe93a0-f384-49b9-8402-e1c5e07788a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26517
32217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.2651732217
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.3153129547
Short name T2549
Test name
Test status
Simulation time 478875762 ps
CPU time 1.3 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:52 PM PDT 24
Peak memory 206636 kb
Host smart-d6a9f4d0-6a45-499d-a04d-ab1d03f70e40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31531
29547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.3153129547
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.2900145132
Short name T2641
Test name
Test status
Simulation time 4552707601 ps
CPU time 124.61 seconds
Started Jul 21 07:00:46 PM PDT 24
Finished Jul 21 07:02:52 PM PDT 24
Peak memory 206860 kb
Host smart-039a2998-19f9-434f-9425-d2e031713e3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29001
45132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.2900145132
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.2083681469
Short name T1507
Test name
Test status
Simulation time 45227085 ps
CPU time 0.67 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 206756 kb
Host smart-a7809ec2-cd4a-4854-ad7e-a2e9af245b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2083681469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.2083681469
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.413728584
Short name T2198
Test name
Test status
Simulation time 4338092308 ps
CPU time 5.58 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206780 kb
Host smart-d259ed60-107f-4be0-a0bc-ea8c708b8f8f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=413728584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.413728584
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.869868815
Short name T834
Test name
Test status
Simulation time 13374205690 ps
CPU time 12.35 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 206792 kb
Host smart-9008fd57-cfef-4c0b-82fe-ab81b6354a07
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=869868815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.869868815
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.3190081375
Short name T985
Test name
Test status
Simulation time 23467536590 ps
CPU time 25.5 seconds
Started Jul 21 07:00:45 PM PDT 24
Finished Jul 21 07:01:11 PM PDT 24
Peak memory 206904 kb
Host smart-9e681718-3bfe-4e15-b110-b989ab36f194
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3190081375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.3190081375
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.3861174168
Short name T2330
Test name
Test status
Simulation time 158550982 ps
CPU time 0.79 seconds
Started Jul 21 07:00:43 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 206648 kb
Host smart-2aa0a4ce-6580-43d1-b17a-83d551da398e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38611
74168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.3861174168
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.3839782866
Short name T2664
Test name
Test status
Simulation time 202044671 ps
CPU time 0.85 seconds
Started Jul 21 07:00:34 PM PDT 24
Finished Jul 21 07:00:35 PM PDT 24
Peak memory 206672 kb
Host smart-4692839c-b733-45c1-98e5-e75cbc20e0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38397
82866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.3839782866
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.2719271570
Short name T2255
Test name
Test status
Simulation time 413610107 ps
CPU time 1.22 seconds
Started Jul 21 07:00:39 PM PDT 24
Finished Jul 21 07:00:41 PM PDT 24
Peak memory 206656 kb
Host smart-d7297e67-394c-4376-980d-2a68c845de5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27192
71570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.2719271570
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.3211184120
Short name T1036
Test name
Test status
Simulation time 1341874266 ps
CPU time 3.15 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:52 PM PDT 24
Peak memory 206804 kb
Host smart-8c4fb30e-1114-48e0-9823-5baa67faba9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32111
84120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.3211184120
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.491958867
Short name T1209
Test name
Test status
Simulation time 12823704470 ps
CPU time 24.96 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:01:16 PM PDT 24
Peak memory 206872 kb
Host smart-39cf6689-d412-462d-b23d-3bff4d591bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49195
8867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.491958867
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.656638191
Short name T335
Test name
Test status
Simulation time 324354861 ps
CPU time 1.09 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 206672 kb
Host smart-3f8b1a8d-68a8-4336-a3c8-4a29932eaea7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65663
8191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.656638191
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.2844361371
Short name T589
Test name
Test status
Simulation time 138613558 ps
CPU time 0.76 seconds
Started Jul 21 07:00:39 PM PDT 24
Finished Jul 21 07:00:40 PM PDT 24
Peak memory 206660 kb
Host smart-660432f6-1287-487c-8bf7-aa928c883470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28443
61371 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.2844361371
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.134340781
Short name T303
Test name
Test status
Simulation time 74113167 ps
CPU time 0.73 seconds
Started Jul 21 07:00:33 PM PDT 24
Finished Jul 21 07:00:34 PM PDT 24
Peak memory 206676 kb
Host smart-0e394d3d-9be4-4c05-b3fd-6db242b34d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13434
0781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.134340781
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.3211630390
Short name T27
Test name
Test status
Simulation time 812532407 ps
CPU time 1.86 seconds
Started Jul 21 07:00:38 PM PDT 24
Finished Jul 21 07:00:40 PM PDT 24
Peak memory 206736 kb
Host smart-ae363ae0-ced8-43ec-a934-eccaf403eb69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32116
30390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.3211630390
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.4005380307
Short name T1422
Test name
Test status
Simulation time 366784735 ps
CPU time 2.44 seconds
Started Jul 21 07:00:41 PM PDT 24
Finished Jul 21 07:00:44 PM PDT 24
Peak memory 206832 kb
Host smart-b8e9ff47-804d-457a-9f0f-2fa10cf33b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40053
80307 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.4005380307
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.1673430718
Short name T2182
Test name
Test status
Simulation time 188838573 ps
CPU time 0.86 seconds
Started Jul 21 07:00:44 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 206696 kb
Host smart-b99727c0-63fe-4a50-9b4b-84c08ed7046c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16734
30718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.1673430718
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.3899382593
Short name T1551
Test name
Test status
Simulation time 195467837 ps
CPU time 0.77 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206692 kb
Host smart-aa51ae0f-fe00-494c-8deb-8c8b865bb5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
82593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.3899382593
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.3395163280
Short name T756
Test name
Test status
Simulation time 284770274 ps
CPU time 1.02 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:53 PM PDT 24
Peak memory 206680 kb
Host smart-000d3e08-509f-4209-8dc1-6e6dae11a156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33951
63280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.3395163280
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.1050194549
Short name T1858
Test name
Test status
Simulation time 8641179488 ps
CPU time 34.93 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:01:33 PM PDT 24
Peak memory 206876 kb
Host smart-c4f8f3ce-b0d5-4c15-8603-be485a767e74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10501
94549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.1050194549
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1001258374
Short name T835
Test name
Test status
Simulation time 299587631 ps
CPU time 1 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 206680 kb
Host smart-34c62cc0-9b80-4876-9dae-f5bf33e09dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10012
58374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1001258374
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.1034415737
Short name T1577
Test name
Test status
Simulation time 23355941835 ps
CPU time 22.43 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:23 PM PDT 24
Peak memory 206752 kb
Host smart-e11b1b48-1945-4a03-8893-113cb551b9c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10344
15737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.1034415737
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.91896124
Short name T18
Test name
Test status
Simulation time 3269622087 ps
CPU time 4.01 seconds
Started Jul 21 07:00:39 PM PDT 24
Finished Jul 21 07:00:44 PM PDT 24
Peak memory 206752 kb
Host smart-5fa841bc-83e9-4b46-bc14-2b9e41cbbae0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91896
124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.91896124
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.1320405002
Short name T1440
Test name
Test status
Simulation time 9460738966 ps
CPU time 79.74 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:02:13 PM PDT 24
Peak memory 206936 kb
Host smart-ec9aec6d-14d4-4b25-8fc2-a0f1f639affe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13204
05002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.1320405002
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.3532040345
Short name T490
Test name
Test status
Simulation time 7846329281 ps
CPU time 58.82 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:01:52 PM PDT 24
Peak memory 206920 kb
Host smart-8d664183-c3cb-4e4e-8591-d365430937fa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3532040345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.3532040345
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.1809996530
Short name T609
Test name
Test status
Simulation time 291480297 ps
CPU time 0.95 seconds
Started Jul 21 07:00:44 PM PDT 24
Finished Jul 21 07:00:45 PM PDT 24
Peak memory 206652 kb
Host smart-cb545fa7-d06a-4e85-b490-99d608031e4b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1809996530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.1809996530
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.4078578698
Short name T1970
Test name
Test status
Simulation time 204639167 ps
CPU time 0.81 seconds
Started Jul 21 07:00:44 PM PDT 24
Finished Jul 21 07:00:46 PM PDT 24
Peak memory 206676 kb
Host smart-3ccb2ae7-9193-4e2c-8049-8992960ae007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
78698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.4078578698
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.3204385657
Short name T2548
Test name
Test status
Simulation time 4042355455 ps
CPU time 28.87 seconds
Started Jul 21 07:00:38 PM PDT 24
Finished Jul 21 07:01:07 PM PDT 24
Peak memory 206844 kb
Host smart-d3b3fafd-5ed5-4271-82f6-9222490e6b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32043
85657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.3204385657
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.1901832008
Short name T1347
Test name
Test status
Simulation time 4316778584 ps
CPU time 41.36 seconds
Started Jul 21 07:00:40 PM PDT 24
Finished Jul 21 07:01:22 PM PDT 24
Peak memory 206860 kb
Host smart-2bab10e4-ad9f-4589-b89a-a5c8ad2b94cc
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1901832008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.1901832008
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1908015931
Short name T2564
Test name
Test status
Simulation time 163253936 ps
CPU time 0.76 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 206696 kb
Host smart-9a5d61fd-e615-426f-a3a1-15de203cec2e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1908015931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1908015931
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.3707019416
Short name T1654
Test name
Test status
Simulation time 193179976 ps
CPU time 0.82 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:49 PM PDT 24
Peak memory 206652 kb
Host smart-f3ccbe18-8dec-4aaa-9306-4ce1cb9c0a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37070
19416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.3707019416
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.1934823743
Short name T133
Test name
Test status
Simulation time 194149219 ps
CPU time 0.87 seconds
Started Jul 21 07:00:49 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 206700 kb
Host smart-9e802782-d99f-42da-afaa-5245356383c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19348
23743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.1934823743
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.1256742753
Short name T1655
Test name
Test status
Simulation time 187129739 ps
CPU time 0.9 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 206564 kb
Host smart-7ffc63db-ec90-4a79-bf47-ceec94817b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12567
42753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.1256742753
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1280424569
Short name T2512
Test name
Test status
Simulation time 229977378 ps
CPU time 0.83 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:57 PM PDT 24
Peak memory 206676 kb
Host smart-950399a5-1ec3-4982-bd31-cc6dc9f22248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12804
24569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1280424569
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.2201676956
Short name T1461
Test name
Test status
Simulation time 170444690 ps
CPU time 0.83 seconds
Started Jul 21 07:00:52 PM PDT 24
Finished Jul 21 07:00:56 PM PDT 24
Peak memory 206688 kb
Host smart-a416b822-7cee-4da0-b18a-b4f804ac801d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22016
76956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.2201676956
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.621643457
Short name T740
Test name
Test status
Simulation time 167387603 ps
CPU time 0.83 seconds
Started Jul 21 07:00:38 PM PDT 24
Finished Jul 21 07:00:39 PM PDT 24
Peak memory 206688 kb
Host smart-7a4172f0-4a18-45a2-aa3e-59e76b28a395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62164
3457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.621643457
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.2685628381
Short name T418
Test name
Test status
Simulation time 249196959 ps
CPU time 0.89 seconds
Started Jul 21 07:00:39 PM PDT 24
Finished Jul 21 07:00:40 PM PDT 24
Peak memory 206676 kb
Host smart-0cb8aecd-7e5b-4bd5-a1c8-24f6e90e56fd
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2685628381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.2685628381
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.3875380092
Short name T1174
Test name
Test status
Simulation time 144556528 ps
CPU time 0.73 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 206644 kb
Host smart-4e888f95-7c61-4bd8-b752-9adac80ad050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38753
80092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.3875380092
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.955031149
Short name T32
Test name
Test status
Simulation time 38527693 ps
CPU time 0.67 seconds
Started Jul 21 07:00:56 PM PDT 24
Finished Jul 21 07:01:01 PM PDT 24
Peak memory 206680 kb
Host smart-7895db5b-a550-42d1-84af-bf3c5acc4246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95503
1149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.955031149
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.3650999665
Short name T1642
Test name
Test status
Simulation time 19286559789 ps
CPU time 42.66 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:01:36 PM PDT 24
Peak memory 206932 kb
Host smart-15c69b2d-39aa-4996-96c7-ccadb91678b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36509
99665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.3650999665
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.3134650564
Short name T1798
Test name
Test status
Simulation time 204791918 ps
CPU time 0.84 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:00:54 PM PDT 24
Peak memory 206684 kb
Host smart-768e026d-3583-428b-ae36-062cfdd59a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31346
50564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.3134650564
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1400491923
Short name T1680
Test name
Test status
Simulation time 173866683 ps
CPU time 0.78 seconds
Started Jul 21 07:00:45 PM PDT 24
Finished Jul 21 07:00:46 PM PDT 24
Peak memory 206668 kb
Host smart-c8e3c792-2f4b-46b4-89bb-30f25fbd802a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14004
91923 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1400491923
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3850986007
Short name T2658
Test name
Test status
Simulation time 234326288 ps
CPU time 0.94 seconds
Started Jul 21 07:00:53 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 206652 kb
Host smart-394552b7-08ed-47a6-8b7a-be18e8811fac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38509
86007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3850986007
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.2012010805
Short name T2576
Test name
Test status
Simulation time 156154690 ps
CPU time 0.83 seconds
Started Jul 21 07:00:54 PM PDT 24
Finished Jul 21 07:00:59 PM PDT 24
Peak memory 206696 kb
Host smart-f436b090-c8ee-48fb-83f3-93581eab5308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20120
10805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.2012010805
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.805866837
Short name T2044
Test name
Test status
Simulation time 189679893 ps
CPU time 0.77 seconds
Started Jul 21 07:00:57 PM PDT 24
Finished Jul 21 07:01:03 PM PDT 24
Peak memory 206656 kb
Host smart-d65c2cdd-cb91-4150-82a2-64c46b46916c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80586
6837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.805866837
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.3057848876
Short name T1590
Test name
Test status
Simulation time 144080319 ps
CPU time 0.76 seconds
Started Jul 21 07:00:47 PM PDT 24
Finished Jul 21 07:00:50 PM PDT 24
Peak memory 206624 kb
Host smart-fc64d366-82b4-4b89-83c1-6e14ba317776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30578
48876 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.3057848876
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.3338405082
Short name T2651
Test name
Test status
Simulation time 150306353 ps
CPU time 0.83 seconds
Started Jul 21 07:00:42 PM PDT 24
Finished Jul 21 07:00:43 PM PDT 24
Peak memory 206652 kb
Host smart-9de11e70-74c2-4a9a-ab20-141d21ee4a64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33384
05082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.3338405082
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.1084811827
Short name T801
Test name
Test status
Simulation time 265534136 ps
CPU time 0.97 seconds
Started Jul 21 07:00:55 PM PDT 24
Finished Jul 21 07:01:00 PM PDT 24
Peak memory 206672 kb
Host smart-2dd0a72c-d163-4608-9186-9d784ddb1db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10848
11827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.1084811827
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.3272631573
Short name T2276
Test name
Test status
Simulation time 6431077940 ps
CPU time 178.5 seconds
Started Jul 21 07:00:51 PM PDT 24
Finished Jul 21 07:03:52 PM PDT 24
Peak memory 206792 kb
Host smart-f0edb09e-c035-495b-a5a7-1efbf1a910a6
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3272631573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.3272631573
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.2383002535
Short name T2468
Test name
Test status
Simulation time 174838496 ps
CPU time 0.82 seconds
Started Jul 21 07:00:46 PM PDT 24
Finished Jul 21 07:00:48 PM PDT 24
Peak memory 206648 kb
Host smart-b79aeb65-5726-42ab-9179-dfa0ccf4bc29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23830
02535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.2383002535
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1633312107
Short name T1108
Test name
Test status
Simulation time 240746945 ps
CPU time 0.84 seconds
Started Jul 21 07:00:48 PM PDT 24
Finished Jul 21 07:00:51 PM PDT 24
Peak memory 206692 kb
Host smart-933e5974-acd8-48de-846e-17c8aae3aed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16333
12107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1633312107
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.1272045567
Short name T785
Test name
Test status
Simulation time 201559930 ps
CPU time 0.88 seconds
Started Jul 21 07:00:50 PM PDT 24
Finished Jul 21 07:00:54 PM PDT 24
Peak memory 206704 kb
Host smart-68c1b0c8-a87b-4c1f-9eff-c84808d84749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12720
45567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.1272045567
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.1529555218
Short name T1762
Test name
Test status
Simulation time 5211471955 ps
CPU time 52.56 seconds
Started Jul 21 07:00:42 PM PDT 24
Finished Jul 21 07:01:35 PM PDT 24
Peak memory 207000 kb
Host smart-55a7772a-08bf-492b-ad75-d3922bc5a370
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15295
55218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.1529555218
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.157449583
Short name T711
Test name
Test status
Simulation time 46039413 ps
CPU time 0.66 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:53:53 PM PDT 24
Peak memory 206724 kb
Host smart-75388662-8eab-4a38-a90d-691c040b96c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=157449583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.157449583
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.267900995
Short name T1867
Test name
Test status
Simulation time 4008076280 ps
CPU time 5.86 seconds
Started Jul 21 06:53:37 PM PDT 24
Finished Jul 21 06:53:43 PM PDT 24
Peak memory 206740 kb
Host smart-d0e4c3b2-167b-4524-acd4-6471bddc54e1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=267900995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.267900995
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.3861140323
Short name T1116
Test name
Test status
Simulation time 13396164366 ps
CPU time 14.47 seconds
Started Jul 21 06:53:38 PM PDT 24
Finished Jul 21 06:53:53 PM PDT 24
Peak memory 206784 kb
Host smart-de9691fc-a763-4df3-921a-9018479efa38
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3861140323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.3861140323
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.2894911639
Short name T1479
Test name
Test status
Simulation time 23349390072 ps
CPU time 22.01 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:54:04 PM PDT 24
Peak memory 206908 kb
Host smart-9f837338-a940-4232-9156-0f0f7e941453
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2894911639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.2894911639
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.1371459246
Short name T1998
Test name
Test status
Simulation time 156160606 ps
CPU time 0.8 seconds
Started Jul 21 06:53:37 PM PDT 24
Finished Jul 21 06:53:38 PM PDT 24
Peak memory 206684 kb
Host smart-361923ea-0074-4a69-b55a-d5aecaab874a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13714
59246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.1371459246
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.2446091117
Short name T500
Test name
Test status
Simulation time 150950449 ps
CPU time 0.75 seconds
Started Jul 21 06:53:38 PM PDT 24
Finished Jul 21 06:53:39 PM PDT 24
Peak memory 206676 kb
Host smart-45c73063-f361-46a0-86c6-b8166f8f14a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24460
91117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.2446091117
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.1195203735
Short name T573
Test name
Test status
Simulation time 290557303 ps
CPU time 1.03 seconds
Started Jul 21 06:53:36 PM PDT 24
Finished Jul 21 06:53:37 PM PDT 24
Peak memory 206656 kb
Host smart-108b9abc-c965-4a50-96b5-3c66b4762b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11952
03735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.1195203735
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.1872640150
Short name T1943
Test name
Test status
Simulation time 368129252 ps
CPU time 1.14 seconds
Started Jul 21 06:53:38 PM PDT 24
Finished Jul 21 06:53:40 PM PDT 24
Peak memory 206648 kb
Host smart-6db3ec19-e42e-4f1e-b6c0-1413ae6ea43b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18726
40150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.1872640150
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3761072880
Short name T642
Test name
Test status
Simulation time 15599851624 ps
CPU time 31.3 seconds
Started Jul 21 06:53:38 PM PDT 24
Finished Jul 21 06:54:10 PM PDT 24
Peak memory 206896 kb
Host smart-1df24df4-90ea-4b8e-b150-284c3d2854d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37610
72880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3761072880
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.2608468232
Short name T907
Test name
Test status
Simulation time 430056158 ps
CPU time 1.28 seconds
Started Jul 21 06:53:38 PM PDT 24
Finished Jul 21 06:53:40 PM PDT 24
Peak memory 206704 kb
Host smart-f7ada7bd-2ea5-4a10-bf1c-41ce9ab90da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26084
68232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.2608468232
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.770325148
Short name T637
Test name
Test status
Simulation time 148704543 ps
CPU time 0.74 seconds
Started Jul 21 06:53:39 PM PDT 24
Finished Jul 21 06:53:41 PM PDT 24
Peak memory 206668 kb
Host smart-d431d3be-9d83-41be-b312-3ccc24af4cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77032
5148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.770325148
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.1663584425
Short name T1105
Test name
Test status
Simulation time 51824359 ps
CPU time 0.67 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:44 PM PDT 24
Peak memory 206656 kb
Host smart-327dbcd8-564f-4f0b-9283-07c6db497e63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16635
84425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.1663584425
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.4048685370
Short name T554
Test name
Test status
Simulation time 768238840 ps
CPU time 2.09 seconds
Started Jul 21 06:53:37 PM PDT 24
Finished Jul 21 06:53:40 PM PDT 24
Peak memory 206856 kb
Host smart-44bd1e5d-0c30-4b1c-a2e4-c73a73d12190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
85370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.4048685370
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.3887883145
Short name T2017
Test name
Test status
Simulation time 296666852 ps
CPU time 2.08 seconds
Started Jul 21 06:53:39 PM PDT 24
Finished Jul 21 06:53:42 PM PDT 24
Peak memory 206780 kb
Host smart-4dcb518f-bd0e-42f0-9b1f-5ea09898ae29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38878
83145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.3887883145
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3053708571
Short name T2100
Test name
Test status
Simulation time 173148327 ps
CPU time 0.82 seconds
Started Jul 21 06:53:36 PM PDT 24
Finished Jul 21 06:53:37 PM PDT 24
Peak memory 206668 kb
Host smart-15001fc4-18ac-440a-bcf9-3987fd0aee27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30537
08571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3053708571
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.801895957
Short name T1684
Test name
Test status
Simulation time 171037980 ps
CPU time 0.82 seconds
Started Jul 21 06:53:39 PM PDT 24
Finished Jul 21 06:53:41 PM PDT 24
Peak memory 206664 kb
Host smart-93b06373-e125-485b-87bc-2acd5f372a52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80189
5957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.801895957
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.884231163
Short name T2334
Test name
Test status
Simulation time 287905796 ps
CPU time 0.94 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206688 kb
Host smart-e2387280-7235-40db-99fd-7d32381c44cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88423
1163 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.884231163
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.3444250717
Short name T901
Test name
Test status
Simulation time 8966490971 ps
CPU time 248.08 seconds
Started Jul 21 06:53:40 PM PDT 24
Finished Jul 21 06:57:48 PM PDT 24
Peak memory 206864 kb
Host smart-9c1206b6-26c6-4ad9-b820-5bae989707c0
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3444250717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.3444250717
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.602561042
Short name T1226
Test name
Test status
Simulation time 6077989109 ps
CPU time 52.45 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:54:35 PM PDT 24
Peak memory 206908 kb
Host smart-c2b8f4a1-08e0-45bf-a048-15ea3d099664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60256
1042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.602561042
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.617741822
Short name T1891
Test name
Test status
Simulation time 205659686 ps
CPU time 0.87 seconds
Started Jul 21 06:53:44 PM PDT 24
Finished Jul 21 06:53:46 PM PDT 24
Peak memory 206692 kb
Host smart-0fa9a07f-0460-4e14-9d89-6de8ae68520b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61774
1822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.617741822
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.2822110205
Short name T2138
Test name
Test status
Simulation time 23302690357 ps
CPU time 21.28 seconds
Started Jul 21 06:53:43 PM PDT 24
Finished Jul 21 06:54:05 PM PDT 24
Peak memory 206796 kb
Host smart-56cf466f-fe94-40ff-ba4a-a361760c474a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28221
10205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.2822110205
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1750379246
Short name T1125
Test name
Test status
Simulation time 3281257944 ps
CPU time 3.56 seconds
Started Jul 21 06:53:43 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206764 kb
Host smart-77026cd0-8b02-463a-b63d-16debfc612c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17503
79246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1750379246
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.2409754949
Short name T1511
Test name
Test status
Simulation time 9540741052 ps
CPU time 83.34 seconds
Started Jul 21 06:53:43 PM PDT 24
Finished Jul 21 06:55:07 PM PDT 24
Peak memory 206904 kb
Host smart-fa3d0331-803f-438b-b80d-59be992889d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24097
54949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.2409754949
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.3193655416
Short name T911
Test name
Test status
Simulation time 4408493560 ps
CPU time 121.81 seconds
Started Jul 21 06:53:44 PM PDT 24
Finished Jul 21 06:55:46 PM PDT 24
Peak memory 206864 kb
Host smart-8cc0c5b2-a466-4386-b249-9ed2c0ebdcc5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3193655416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.3193655416
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3978447586
Short name T2492
Test name
Test status
Simulation time 235449404 ps
CPU time 0.84 seconds
Started Jul 21 06:53:40 PM PDT 24
Finished Jul 21 06:53:42 PM PDT 24
Peak memory 206672 kb
Host smart-ed5d6ad0-d8c8-42e7-ac9b-349c9ba76479
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3978447586 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3978447586
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.4280352462
Short name T2431
Test name
Test status
Simulation time 286476605 ps
CPU time 0.92 seconds
Started Jul 21 06:53:43 PM PDT 24
Finished Jul 21 06:53:45 PM PDT 24
Peak memory 206664 kb
Host smart-94b90a80-5bc7-42f0-b4ee-b5f0026a547b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42803
52462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.4280352462
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.2684471258
Short name T636
Test name
Test status
Simulation time 5292429074 ps
CPU time 142.57 seconds
Started Jul 21 06:53:43 PM PDT 24
Finished Jul 21 06:56:06 PM PDT 24
Peak memory 206848 kb
Host smart-5896a9aa-93bb-4c97-aa32-5f454e3559fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26844
71258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.2684471258
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.3638189721
Short name T2724
Test name
Test status
Simulation time 3082027428 ps
CPU time 30.29 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:54:13 PM PDT 24
Peak memory 206908 kb
Host smart-b1453c62-c4c3-41d6-95c7-b64abdcc2dad
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3638189721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.3638189721
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.1846583829
Short name T2287
Test name
Test status
Simulation time 182135769 ps
CPU time 0.83 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:53:49 PM PDT 24
Peak memory 206692 kb
Host smart-c3a00a9f-425c-46c2-ad39-730a74da96c6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1846583829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.1846583829
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1761099095
Short name T633
Test name
Test status
Simulation time 164760576 ps
CPU time 0.76 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:53:49 PM PDT 24
Peak memory 206692 kb
Host smart-7831a883-094b-4e70-b84b-99b9db11e20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17610
99095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1761099095
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.1928018486
Short name T126
Test name
Test status
Simulation time 227539864 ps
CPU time 0.88 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:44 PM PDT 24
Peak memory 206680 kb
Host smart-ce95b1f6-677e-4214-9761-38dfa67fd383
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19280
18486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.1928018486
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.1441184684
Short name T912
Test name
Test status
Simulation time 217837115 ps
CPU time 0.83 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:44 PM PDT 24
Peak memory 206664 kb
Host smart-1eb1c47b-8b81-4744-8d19-a513d50949d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411
84684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.1441184684
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2057483274
Short name T709
Test name
Test status
Simulation time 187364254 ps
CPU time 0.83 seconds
Started Jul 21 06:53:42 PM PDT 24
Finished Jul 21 06:53:43 PM PDT 24
Peak memory 206668 kb
Host smart-e60da184-afdd-4530-863d-7d71150e1d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20574
83274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2057483274
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.421752929
Short name T433
Test name
Test status
Simulation time 164546208 ps
CPU time 0.76 seconds
Started Jul 21 06:53:43 PM PDT 24
Finished Jul 21 06:53:45 PM PDT 24
Peak memory 206684 kb
Host smart-2135af93-3f34-4f1f-ab15-5307353d5fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
2929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.421752929
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.2076802012
Short name T841
Test name
Test status
Simulation time 166650860 ps
CPU time 0.79 seconds
Started Jul 21 06:53:48 PM PDT 24
Finished Jul 21 06:53:49 PM PDT 24
Peak memory 206664 kb
Host smart-647a8966-6654-47ef-abac-45f3acd513b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20768
02012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.2076802012
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.1548324980
Short name T1542
Test name
Test status
Simulation time 226779402 ps
CPU time 0.96 seconds
Started Jul 21 06:53:46 PM PDT 24
Finished Jul 21 06:53:47 PM PDT 24
Peak memory 206712 kb
Host smart-6e316baa-ca81-46f5-99d7-035f4042d054
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1548324980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.1548324980
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.117386320
Short name T1472
Test name
Test status
Simulation time 179667150 ps
CPU time 0.79 seconds
Started Jul 21 06:53:46 PM PDT 24
Finished Jul 21 06:53:47 PM PDT 24
Peak memory 206672 kb
Host smart-e8b761ae-9e74-438a-9d08-a08fb504f59b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11738
6320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.117386320
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.100104535
Short name T33
Test name
Test status
Simulation time 44589945 ps
CPU time 0.66 seconds
Started Jul 21 06:53:50 PM PDT 24
Finished Jul 21 06:53:51 PM PDT 24
Peak memory 206696 kb
Host smart-50d88044-3d3c-4fc5-ae8d-45e464b9578c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10010
4535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.100104535
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.4031397107
Short name T1584
Test name
Test status
Simulation time 7271724653 ps
CPU time 16.44 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:54:04 PM PDT 24
Peak memory 206920 kb
Host smart-884cdd00-7af1-422f-9c9f-884f9e5be60d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40313
97107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.4031397107
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.394788643
Short name T933
Test name
Test status
Simulation time 160435159 ps
CPU time 0.81 seconds
Started Jul 21 06:53:48 PM PDT 24
Finished Jul 21 06:53:50 PM PDT 24
Peak memory 206664 kb
Host smart-db5b7af7-2581-499f-a1a0-2686678d4cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39478
8643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.394788643
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.1841377514
Short name T1368
Test name
Test status
Simulation time 219955197 ps
CPU time 0.93 seconds
Started Jul 21 06:53:46 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206788 kb
Host smart-a56f97f8-bdcd-462e-a4fa-0ad0d692da35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18413
77514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.1841377514
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.2351299449
Short name T680
Test name
Test status
Simulation time 10139394743 ps
CPU time 87.32 seconds
Started Jul 21 06:53:49 PM PDT 24
Finished Jul 21 06:55:17 PM PDT 24
Peak memory 206808 kb
Host smart-24306b54-247a-45e7-b601-69db6b59feee
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2351299449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.2351299449
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.4143410875
Short name T173
Test name
Test status
Simulation time 11494379472 ps
CPU time 296.86 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:58:45 PM PDT 24
Peak memory 206968 kb
Host smart-b8f9c343-420a-4072-b3b8-ccdc5ff5adfa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4143410875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.4143410875
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3946823072
Short name T1407
Test name
Test status
Simulation time 12203518491 ps
CPU time 77.83 seconds
Started Jul 21 06:53:50 PM PDT 24
Finished Jul 21 06:55:08 PM PDT 24
Peak memory 206976 kb
Host smart-28f3d5ec-9904-4440-9dda-82c397e2ab40
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3946823072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3946823072
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.686289769
Short name T1353
Test name
Test status
Simulation time 272848938 ps
CPU time 0.91 seconds
Started Jul 21 06:53:48 PM PDT 24
Finished Jul 21 06:53:50 PM PDT 24
Peak memory 206664 kb
Host smart-74d64ca8-f872-4c4b-836e-ed4b62a8e476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68628
9769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.686289769
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.3846334787
Short name T758
Test name
Test status
Simulation time 149485369 ps
CPU time 0.81 seconds
Started Jul 21 06:53:48 PM PDT 24
Finished Jul 21 06:53:50 PM PDT 24
Peak memory 206644 kb
Host smart-a3129c5d-1cfd-4288-8510-bc5dcd9b8455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38463
34787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.3846334787
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.1094174888
Short name T731
Test name
Test status
Simulation time 164564312 ps
CPU time 0.79 seconds
Started Jul 21 06:53:49 PM PDT 24
Finished Jul 21 06:53:50 PM PDT 24
Peak memory 206664 kb
Host smart-9426d186-8efa-44fb-a56f-65a86174c175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10941
74888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.1094174888
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2126795171
Short name T605
Test name
Test status
Simulation time 158273277 ps
CPU time 0.73 seconds
Started Jul 21 06:53:46 PM PDT 24
Finished Jul 21 06:53:47 PM PDT 24
Peak memory 206680 kb
Host smart-feeb481e-25d5-490a-a9b1-24b8448b7c3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21267
95171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2126795171
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.876640333
Short name T693
Test name
Test status
Simulation time 174432674 ps
CPU time 0.83 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206704 kb
Host smart-fed2b0ad-d17a-4c3a-8c28-485d43a4b0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87664
0333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.876640333
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3038278654
Short name T606
Test name
Test status
Simulation time 262323234 ps
CPU time 1.02 seconds
Started Jul 21 06:53:45 PM PDT 24
Finished Jul 21 06:53:47 PM PDT 24
Peak memory 206688 kb
Host smart-e1f1a81f-bf27-49c4-9522-bec41ee73e9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30382
78654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3038278654
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.4206778470
Short name T978
Test name
Test status
Simulation time 5237295410 ps
CPU time 141.61 seconds
Started Jul 21 06:53:49 PM PDT 24
Finished Jul 21 06:56:11 PM PDT 24
Peak memory 206764 kb
Host smart-2344ca29-9c79-4dc8-8d74-2a2d2f853116
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4206778470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.4206778470
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.1530818138
Short name T343
Test name
Test status
Simulation time 203657015 ps
CPU time 0.86 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:53:49 PM PDT 24
Peak memory 206692 kb
Host smart-037252dc-3bec-40f1-bcaa-dd415f48ac47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15308
18138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.1530818138
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.922446051
Short name T2435
Test name
Test status
Simulation time 182691657 ps
CPU time 0.84 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:53:48 PM PDT 24
Peak memory 206712 kb
Host smart-04fa8997-a3be-4b78-9db7-0ef82d17b1a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92244
6051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.922446051
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2285736918
Short name T1865
Test name
Test status
Simulation time 910898374 ps
CPU time 1.89 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:53:50 PM PDT 24
Peak memory 206796 kb
Host smart-154bcb93-67b7-45c1-854e-b783803c21e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22857
36918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2285736918
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.409033275
Short name T1502
Test name
Test status
Simulation time 6243354772 ps
CPU time 54.09 seconds
Started Jul 21 06:53:47 PM PDT 24
Finished Jul 21 06:54:42 PM PDT 24
Peak memory 206904 kb
Host smart-865df084-a4af-4c5a-9207-bf39e0d95722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40903
3275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.409033275
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.3485828617
Short name T1337
Test name
Test status
Simulation time 33212470 ps
CPU time 0.73 seconds
Started Jul 21 06:54:02 PM PDT 24
Finished Jul 21 06:54:04 PM PDT 24
Peak memory 206756 kb
Host smart-6f79cd5c-86d2-4b9c-9dae-f12a81504e85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3485828617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.3485828617
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.960850090
Short name T1704
Test name
Test status
Simulation time 4127406888 ps
CPU time 5.5 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:53:58 PM PDT 24
Peak memory 206840 kb
Host smart-0e330207-bc9f-4e8f-a4b0-0ca66a770f8e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=960850090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.960850090
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.628112331
Short name T2537
Test name
Test status
Simulation time 13436313382 ps
CPU time 12.35 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:54:05 PM PDT 24
Peak memory 206880 kb
Host smart-2081b2b3-b3e3-4f28-8b2b-bba4f17f4fc6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=628112331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.628112331
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.1132468018
Short name T2552
Test name
Test status
Simulation time 23346653309 ps
CPU time 23.48 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:54:16 PM PDT 24
Peak memory 206800 kb
Host smart-72e174bc-4cd9-4359-8fe7-035aecbd04d2
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1132468018 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.1132468018
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.1652689232
Short name T1274
Test name
Test status
Simulation time 159953993 ps
CPU time 0.75 seconds
Started Jul 21 06:53:51 PM PDT 24
Finished Jul 21 06:53:52 PM PDT 24
Peak memory 206660 kb
Host smart-774d3d4f-2ac1-4753-b559-1819aeaae2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16526
89232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.1652689232
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.1659063884
Short name T1724
Test name
Test status
Simulation time 179766223 ps
CPU time 0.86 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:53:53 PM PDT 24
Peak memory 206804 kb
Host smart-bd00bfee-33bc-4320-8b0c-e67ed7ff78fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
63884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.1659063884
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.367364928
Short name T1621
Test name
Test status
Simulation time 288674987 ps
CPU time 1.14 seconds
Started Jul 21 06:53:56 PM PDT 24
Finished Jul 21 06:53:58 PM PDT 24
Peak memory 206636 kb
Host smart-79f07075-4bd1-4793-abc9-732518a73caa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36736
4928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.367364928
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.1444319398
Short name T1694
Test name
Test status
Simulation time 1313722834 ps
CPU time 2.97 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:53:55 PM PDT 24
Peak memory 206780 kb
Host smart-64b620b0-e032-47f1-b939-1f56d0c4a5e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14443
19398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.1444319398
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.1577806313
Short name T1130
Test name
Test status
Simulation time 467997050 ps
CPU time 1.46 seconds
Started Jul 21 06:53:52 PM PDT 24
Finished Jul 21 06:53:54 PM PDT 24
Peak memory 206648 kb
Host smart-1d5a84d0-feb3-4c57-8c8f-122f5d2f2a65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15778
06313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.1577806313
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.2616620723
Short name T40
Test name
Test status
Simulation time 138319633 ps
CPU time 0.77 seconds
Started Jul 21 06:53:55 PM PDT 24
Finished Jul 21 06:53:56 PM PDT 24
Peak memory 206676 kb
Host smart-c3fce532-3375-41c1-aa5b-59042850885d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26166
20723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.2616620723
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.3768134934
Short name T1343
Test name
Test status
Simulation time 62789089 ps
CPU time 0.67 seconds
Started Jul 21 06:54:00 PM PDT 24
Finished Jul 21 06:54:01 PM PDT 24
Peak memory 206676 kb
Host smart-53b2ce6e-f480-424e-9655-d35e84055c96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37681
34934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.3768134934
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.1651112989
Short name T2582
Test name
Test status
Simulation time 999732707 ps
CPU time 2.3 seconds
Started Jul 21 06:53:57 PM PDT 24
Finished Jul 21 06:54:00 PM PDT 24
Peak memory 206772 kb
Host smart-e4517b9b-32d1-41c8-a64d-a028230d750f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16511
12989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.1651112989
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.608237665
Short name T615
Test name
Test status
Simulation time 207879150 ps
CPU time 1.72 seconds
Started Jul 21 06:53:59 PM PDT 24
Finished Jul 21 06:54:01 PM PDT 24
Peak memory 206808 kb
Host smart-d8ca0b33-3513-4132-bdfe-8282aeb8d749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60823
7665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.608237665
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3390859972
Short name T1149
Test name
Test status
Simulation time 215065855 ps
CPU time 0.92 seconds
Started Jul 21 06:53:56 PM PDT 24
Finished Jul 21 06:53:57 PM PDT 24
Peak memory 206660 kb
Host smart-94a6b5f8-de20-4418-a438-7fce59bff8be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33908
59972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3390859972
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.306319598
Short name T2632
Test name
Test status
Simulation time 139056978 ps
CPU time 0.76 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:02 PM PDT 24
Peak memory 206692 kb
Host smart-5186edb5-c720-4934-9000-9f6d4e356665
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30631
9598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.306319598
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.2158877073
Short name T1110
Test name
Test status
Simulation time 237007650 ps
CPU time 0.94 seconds
Started Jul 21 06:53:56 PM PDT 24
Finished Jul 21 06:53:57 PM PDT 24
Peak memory 206664 kb
Host smart-ff6171a7-cc54-47ba-8b4f-209a850180c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21588
77073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.2158877073
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.899558327
Short name T2234
Test name
Test status
Simulation time 7337246454 ps
CPU time 205.91 seconds
Started Jul 21 06:53:58 PM PDT 24
Finished Jul 21 06:57:24 PM PDT 24
Peak memory 206808 kb
Host smart-36740753-2974-479e-b323-2becb8d2583b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=899558327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.899558327
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.793313831
Short name T2613
Test name
Test status
Simulation time 186598134 ps
CPU time 0.87 seconds
Started Jul 21 06:54:02 PM PDT 24
Finished Jul 21 06:54:03 PM PDT 24
Peak memory 206700 kb
Host smart-272e93bb-5041-483e-aa6b-912ee0e2e5d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79331
3831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.793313831
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.385864991
Short name T2178
Test name
Test status
Simulation time 23298652219 ps
CPU time 25.48 seconds
Started Jul 21 06:54:00 PM PDT 24
Finished Jul 21 06:54:26 PM PDT 24
Peak memory 206808 kb
Host smart-6c05075a-17f8-4404-a38e-54c49da0e956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38586
4991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.385864991
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.48009731
Short name T820
Test name
Test status
Simulation time 3338476092 ps
CPU time 3.7 seconds
Started Jul 21 06:53:57 PM PDT 24
Finished Jul 21 06:54:01 PM PDT 24
Peak memory 206700 kb
Host smart-eeb3495a-231f-4beb-82b9-cae909475961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48009
731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.48009731
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.716817942
Short name T2180
Test name
Test status
Simulation time 7975209630 ps
CPU time 222.06 seconds
Started Jul 21 06:53:57 PM PDT 24
Finished Jul 21 06:57:40 PM PDT 24
Peak memory 206936 kb
Host smart-dbed2953-3eae-454c-84ed-4517b2ae8ca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71681
7942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.716817942
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.3604377196
Short name T2227
Test name
Test status
Simulation time 4735974781 ps
CPU time 46.86 seconds
Started Jul 21 06:53:56 PM PDT 24
Finished Jul 21 06:54:44 PM PDT 24
Peak memory 206896 kb
Host smart-3fa5e992-09d6-45d2-98a6-607ce587f3a6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3604377196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.3604377196
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.464949754
Short name T315
Test name
Test status
Simulation time 239761956 ps
CPU time 0.86 seconds
Started Jul 21 06:53:59 PM PDT 24
Finished Jul 21 06:54:00 PM PDT 24
Peak memory 206664 kb
Host smart-51a5287a-fbc8-4b50-adc9-2052129f8bfc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=464949754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.464949754
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2812967150
Short name T1630
Test name
Test status
Simulation time 235318219 ps
CPU time 0.94 seconds
Started Jul 21 06:53:57 PM PDT 24
Finished Jul 21 06:53:58 PM PDT 24
Peak memory 206684 kb
Host smart-0c9ddb2e-2ba6-496d-a7e8-e61551a9f3ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28129
67150 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2812967150
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.2819320807
Short name T434
Test name
Test status
Simulation time 5627302939 ps
CPU time 149.3 seconds
Started Jul 21 06:53:57 PM PDT 24
Finished Jul 21 06:56:27 PM PDT 24
Peak memory 206920 kb
Host smart-dbf85fb2-73e7-4bf5-a173-a421294c9d33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28193
20807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.2819320807
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.3023391459
Short name T942
Test name
Test status
Simulation time 4499123608 ps
CPU time 42.7 seconds
Started Jul 21 06:54:00 PM PDT 24
Finished Jul 21 06:54:43 PM PDT 24
Peak memory 206872 kb
Host smart-437c400d-79e4-4e1b-9b3c-b8f97b370dd5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3023391459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.3023391459
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.2288060384
Short name T846
Test name
Test status
Simulation time 174401052 ps
CPU time 0.85 seconds
Started Jul 21 06:53:59 PM PDT 24
Finished Jul 21 06:54:00 PM PDT 24
Peak memory 206664 kb
Host smart-09ea1285-c6d7-462c-afae-c29c4b6e296f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2288060384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.2288060384
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.1576110386
Short name T371
Test name
Test status
Simulation time 167184320 ps
CPU time 0.83 seconds
Started Jul 21 06:53:58 PM PDT 24
Finished Jul 21 06:53:59 PM PDT 24
Peak memory 206684 kb
Host smart-83db583f-7fa8-4297-a2fa-a65e05245f06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15761
10386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.1576110386
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.602257694
Short name T124
Test name
Test status
Simulation time 243511084 ps
CPU time 0.84 seconds
Started Jul 21 06:53:56 PM PDT 24
Finished Jul 21 06:53:57 PM PDT 24
Peak memory 206652 kb
Host smart-8ac9a4be-7df2-44d7-af75-c5ea06320906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60225
7694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.602257694
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.595212032
Short name T671
Test name
Test status
Simulation time 183975762 ps
CPU time 0.91 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:02 PM PDT 24
Peak memory 206692 kb
Host smart-3bf572d3-7623-431e-b736-66d86ceff2ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59521
2032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.595212032
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.697074422
Short name T2078
Test name
Test status
Simulation time 198150999 ps
CPU time 0.86 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:03 PM PDT 24
Peak memory 206668 kb
Host smart-2347095d-01ea-48a3-ac33-63ed5d3fb9b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69707
4422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.697074422
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.4069376395
Short name T2243
Test name
Test status
Simulation time 172252562 ps
CPU time 0.85 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:02 PM PDT 24
Peak memory 206680 kb
Host smart-43138004-8deb-49f4-8dd6-6e0ec80d3e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40693
76395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.4069376395
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.266806703
Short name T607
Test name
Test status
Simulation time 158363210 ps
CPU time 0.77 seconds
Started Jul 21 06:53:57 PM PDT 24
Finished Jul 21 06:53:59 PM PDT 24
Peak memory 206676 kb
Host smart-079fa674-7f39-42be-8515-b755e5d87d89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26680
6703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.266806703
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.4012256304
Short name T2527
Test name
Test status
Simulation time 216340778 ps
CPU time 0.89 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:03 PM PDT 24
Peak memory 206672 kb
Host smart-2a42fa1e-5bd5-4d29-ac7d-1144fc531e97
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4012256304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.4012256304
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2206095640
Short name T2338
Test name
Test status
Simulation time 147778752 ps
CPU time 0.83 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:02 PM PDT 24
Peak memory 206692 kb
Host smart-d99715b1-eed0-4b80-b3dc-58979c4b4d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22060
95640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2206095640
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.954717482
Short name T666
Test name
Test status
Simulation time 46185685 ps
CPU time 0.69 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:03 PM PDT 24
Peak memory 206668 kb
Host smart-b11b2cf3-9027-47fc-868b-87822fa61b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95471
7482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.954717482
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.3476433053
Short name T1944
Test name
Test status
Simulation time 9943838322 ps
CPU time 25.29 seconds
Started Jul 21 06:54:05 PM PDT 24
Finished Jul 21 06:54:31 PM PDT 24
Peak memory 206908 kb
Host smart-f0b08661-8a4d-4639-85b8-302db40c036c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34764
33053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.3476433053
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.1724347750
Short name T2128
Test name
Test status
Simulation time 195396193 ps
CPU time 0.84 seconds
Started Jul 21 06:54:03 PM PDT 24
Finished Jul 21 06:54:04 PM PDT 24
Peak memory 206688 kb
Host smart-16470873-a98b-4b6d-908d-9623ab890809
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17243
47750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.1724347750
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.1724867714
Short name T1222
Test name
Test status
Simulation time 168162040 ps
CPU time 0.78 seconds
Started Jul 21 06:54:05 PM PDT 24
Finished Jul 21 06:54:06 PM PDT 24
Peak memory 206516 kb
Host smart-45197806-8855-4967-b23b-8626d6360b10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
67714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.1724867714
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1097017849
Short name T156
Test name
Test status
Simulation time 8244784744 ps
CPU time 34.21 seconds
Started Jul 21 06:54:03 PM PDT 24
Finished Jul 21 06:54:38 PM PDT 24
Peak memory 206892 kb
Host smart-5fc39e37-79d5-40d4-b05f-a8c7be1ddde6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1097017849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1097017849
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.139896015
Short name T2222
Test name
Test status
Simulation time 4608836597 ps
CPU time 26.59 seconds
Started Jul 21 06:54:00 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206904 kb
Host smart-0ad8d3a7-f0a2-4b1a-b2a6-50392e392279
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=139896015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.139896015
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.909083000
Short name T2598
Test name
Test status
Simulation time 10888152601 ps
CPU time 196.39 seconds
Started Jul 21 06:54:02 PM PDT 24
Finished Jul 21 06:57:19 PM PDT 24
Peak memory 206940 kb
Host smart-b5a4b49f-ef4f-4383-9476-89b89d9bf04b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=909083000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.909083000
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.3894002755
Short name T2264
Test name
Test status
Simulation time 212354826 ps
CPU time 0.9 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:03 PM PDT 24
Peak memory 206628 kb
Host smart-71c1fa82-97e4-417d-b201-45165e93293b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38940
02755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.3894002755
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.3711497768
Short name T361
Test name
Test status
Simulation time 207123401 ps
CPU time 0.89 seconds
Started Jul 21 06:54:02 PM PDT 24
Finished Jul 21 06:54:03 PM PDT 24
Peak memory 206636 kb
Host smart-ca4f20cd-b119-4866-a1b5-07b529f53590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37114
97768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.3711497768
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.374962922
Short name T2570
Test name
Test status
Simulation time 154818689 ps
CPU time 0.86 seconds
Started Jul 21 06:54:05 PM PDT 24
Finished Jul 21 06:54:07 PM PDT 24
Peak memory 206668 kb
Host smart-66769b39-aedd-441d-b0d1-fbeb0aeedfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37496
2922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.374962922
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.1892615475
Short name T1860
Test name
Test status
Simulation time 156117793 ps
CPU time 0.79 seconds
Started Jul 21 06:54:07 PM PDT 24
Finished Jul 21 06:54:08 PM PDT 24
Peak memory 206652 kb
Host smart-916cd826-bcd8-4e3f-914d-a1d64f284403
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18926
15475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.1892615475
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.1351024156
Short name T2519
Test name
Test status
Simulation time 153599339 ps
CPU time 0.77 seconds
Started Jul 21 06:54:03 PM PDT 24
Finished Jul 21 06:54:05 PM PDT 24
Peak memory 206660 kb
Host smart-920668ce-4ced-450a-9f1f-a08cbbad75c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13510
24156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.1351024156
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.1775526663
Short name T1515
Test name
Test status
Simulation time 226495851 ps
CPU time 0.96 seconds
Started Jul 21 06:54:01 PM PDT 24
Finished Jul 21 06:54:03 PM PDT 24
Peak memory 206684 kb
Host smart-5990792f-b6a5-451c-9a16-0715c0b040b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17755
26663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.1775526663
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.2152031085
Short name T2649
Test name
Test status
Simulation time 3619823670 ps
CPU time 99.67 seconds
Started Jul 21 06:54:03 PM PDT 24
Finished Jul 21 06:55:43 PM PDT 24
Peak memory 206872 kb
Host smart-7590f7d6-e39c-4781-ac3e-d5c9445d7c24
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2152031085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.2152031085
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.434689124
Short name T2356
Test name
Test status
Simulation time 167376160 ps
CPU time 0.81 seconds
Started Jul 21 06:54:03 PM PDT 24
Finished Jul 21 06:54:04 PM PDT 24
Peak memory 206676 kb
Host smart-4bd26280-e7e9-4dfc-addb-a32f2bf68ce0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43468
9124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.434689124
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.1256950733
Short name T2493
Test name
Test status
Simulation time 179151515 ps
CPU time 0.8 seconds
Started Jul 21 06:54:05 PM PDT 24
Finished Jul 21 06:54:06 PM PDT 24
Peak memory 206464 kb
Host smart-908560b8-aeea-464e-9c93-394bea06bc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12569
50733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.1256950733
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.199514454
Short name T2252
Test name
Test status
Simulation time 430546713 ps
CPU time 1.28 seconds
Started Jul 21 06:54:07 PM PDT 24
Finished Jul 21 06:54:09 PM PDT 24
Peak memory 206700 kb
Host smart-296016a4-9852-4070-b97c-6229114ec9c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19951
4454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.199514454
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.3270830037
Short name T448
Test name
Test status
Simulation time 4083145901 ps
CPU time 28.64 seconds
Started Jul 21 06:54:02 PM PDT 24
Finished Jul 21 06:54:31 PM PDT 24
Peak memory 206868 kb
Host smart-7c2c1809-c80f-44d8-8f18-04f4021a3e68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32708
30037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.3270830037
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.3549352775
Short name T2585
Test name
Test status
Simulation time 88212488 ps
CPU time 0.7 seconds
Started Jul 21 06:54:17 PM PDT 24
Finished Jul 21 06:54:18 PM PDT 24
Peak memory 206732 kb
Host smart-a4db3b8a-b2cb-4f82-a21b-2664ef41e48a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3549352775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.3549352775
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.608588168
Short name T2729
Test name
Test status
Simulation time 4104907773 ps
CPU time 5.68 seconds
Started Jul 21 06:54:00 PM PDT 24
Finished Jul 21 06:54:06 PM PDT 24
Peak memory 206756 kb
Host smart-ff55d6c1-b8f1-4783-8e85-1b3fa35454d4
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=608588168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.608588168
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.2473614096
Short name T2554
Test name
Test status
Simulation time 13436319097 ps
CPU time 12.45 seconds
Started Jul 21 06:54:04 PM PDT 24
Finished Jul 21 06:54:17 PM PDT 24
Peak memory 206928 kb
Host smart-7bb8dd14-2468-4d2a-8201-c2b65f40cb8b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2473614096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.2473614096
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.4146199006
Short name T1644
Test name
Test status
Simulation time 23373929150 ps
CPU time 24.72 seconds
Started Jul 21 06:54:04 PM PDT 24
Finished Jul 21 06:54:29 PM PDT 24
Peak memory 206884 kb
Host smart-fe2b750b-e7bc-43f5-9079-0b354f1d5f5f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4146199006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.4146199006
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.2883939430
Short name T2151
Test name
Test status
Simulation time 166371588 ps
CPU time 0.85 seconds
Started Jul 21 06:54:03 PM PDT 24
Finished Jul 21 06:54:05 PM PDT 24
Peak memory 206688 kb
Host smart-7b17a37d-40a2-4e2a-a272-0f10709e8215
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28839
39430 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.2883939430
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.457835738
Short name T1076
Test name
Test status
Simulation time 174684873 ps
CPU time 0.78 seconds
Started Jul 21 06:54:19 PM PDT 24
Finished Jul 21 06:54:20 PM PDT 24
Peak memory 206684 kb
Host smart-91ce9d00-c4c2-461c-90f3-eb928375fe8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45783
5738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.457835738
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.1713413390
Short name T2191
Test name
Test status
Simulation time 265583543 ps
CPU time 1.02 seconds
Started Jul 21 06:54:13 PM PDT 24
Finished Jul 21 06:54:14 PM PDT 24
Peak memory 206656 kb
Host smart-9f76b751-2850-48c9-90e1-5b24a68d00b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17134
13390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.1713413390
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.4137733577
Short name T2391
Test name
Test status
Simulation time 988975156 ps
CPU time 2.25 seconds
Started Jul 21 06:54:08 PM PDT 24
Finished Jul 21 06:54:11 PM PDT 24
Peak memory 206792 kb
Host smart-d0ebb5ae-5713-44cd-93b1-44dbe9f4a220
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41377
33577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.4137733577
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.437829376
Short name T1403
Test name
Test status
Simulation time 11298917538 ps
CPU time 23.98 seconds
Started Jul 21 06:54:09 PM PDT 24
Finished Jul 21 06:54:33 PM PDT 24
Peak memory 206932 kb
Host smart-434c1c90-7863-46ef-b12e-1c0375962586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43782
9376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.437829376
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.705989753
Short name T505
Test name
Test status
Simulation time 473326576 ps
CPU time 1.51 seconds
Started Jul 21 06:54:05 PM PDT 24
Finished Jul 21 06:54:07 PM PDT 24
Peak memory 206704 kb
Host smart-d3948e68-22d3-4742-aa56-731fc66e9007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70598
9753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.705989753
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.4000888
Short name T1705
Test name
Test status
Simulation time 142660799 ps
CPU time 0.75 seconds
Started Jul 21 06:54:14 PM PDT 24
Finished Jul 21 06:54:15 PM PDT 24
Peak memory 206644 kb
Host smart-b545d0da-21e3-47dc-86ef-4efe9574b716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40008
88 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.4000888
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.3623873611
Short name T1923
Test name
Test status
Simulation time 87437754 ps
CPU time 0.69 seconds
Started Jul 21 06:54:06 PM PDT 24
Finished Jul 21 06:54:07 PM PDT 24
Peak memory 206652 kb
Host smart-c029377a-c5a4-45f8-802e-131c6e11107c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36238
73611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.3623873611
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1167569324
Short name T658
Test name
Test status
Simulation time 855320389 ps
CPU time 2.25 seconds
Started Jul 21 06:54:08 PM PDT 24
Finished Jul 21 06:54:11 PM PDT 24
Peak memory 206656 kb
Host smart-e7a0c22f-a47e-463c-ad3f-8e75fd761a62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11675
69324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1167569324
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.1450452087
Short name T1266
Test name
Test status
Simulation time 152603076 ps
CPU time 1.15 seconds
Started Jul 21 06:54:06 PM PDT 24
Finished Jul 21 06:54:07 PM PDT 24
Peak memory 206832 kb
Host smart-6cf4135e-733e-42d1-ae54-9634e705401d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14504
52087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.1450452087
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.142183243
Short name T1946
Test name
Test status
Simulation time 174436299 ps
CPU time 0.84 seconds
Started Jul 21 06:54:04 PM PDT 24
Finished Jul 21 06:54:06 PM PDT 24
Peak memory 206672 kb
Host smart-fb5b316e-f49d-4ce7-8d7f-130d5ac785a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14218
3243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.142183243
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.468422100
Short name T826
Test name
Test status
Simulation time 142040405 ps
CPU time 0.79 seconds
Started Jul 21 06:54:13 PM PDT 24
Finished Jul 21 06:54:14 PM PDT 24
Peak memory 206652 kb
Host smart-dca53cd9-0f27-4198-bfc1-c70a73cde799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46842
2100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.468422100
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2354034167
Short name T2702
Test name
Test status
Simulation time 213790754 ps
CPU time 0.93 seconds
Started Jul 21 06:54:07 PM PDT 24
Finished Jul 21 06:54:08 PM PDT 24
Peak memory 206668 kb
Host smart-7031eec7-b02e-4470-b67d-11a9c45b9a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23540
34167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2354034167
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.3985926624
Short name T1711
Test name
Test status
Simulation time 11148428747 ps
CPU time 100.87 seconds
Started Jul 21 06:54:06 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 206920 kb
Host smart-134ed66a-a6c2-4c0e-8b9b-fc5b999008c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39859
26624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.3985926624
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2711490170
Short name T1535
Test name
Test status
Simulation time 175198809 ps
CPU time 0.79 seconds
Started Jul 21 06:54:08 PM PDT 24
Finished Jul 21 06:54:09 PM PDT 24
Peak memory 206680 kb
Host smart-0ad539e9-fb07-48aa-bcec-eb84fc229a74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27114
90170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2711490170
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.498420196
Short name T323
Test name
Test status
Simulation time 23267410058 ps
CPU time 26.21 seconds
Started Jul 21 06:54:14 PM PDT 24
Finished Jul 21 06:54:40 PM PDT 24
Peak memory 206768 kb
Host smart-bdadfc5f-da9c-459d-83fe-e1142edf460b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49842
0196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.498420196
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.213128836
Short name T2477
Test name
Test status
Simulation time 3270632416 ps
CPU time 4.71 seconds
Started Jul 21 06:54:09 PM PDT 24
Finished Jul 21 06:54:14 PM PDT 24
Peak memory 206724 kb
Host smart-630c2138-8b9f-46f2-9fe8-4e3f3e23362a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21312
8836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.213128836
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.3478248574
Short name T2170
Test name
Test status
Simulation time 9807297325 ps
CPU time 88.46 seconds
Started Jul 21 06:54:08 PM PDT 24
Finished Jul 21 06:55:38 PM PDT 24
Peak memory 206952 kb
Host smart-c8a09846-b541-4549-941d-013e7831b9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34782
48574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.3478248574
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.2385350785
Short name T1845
Test name
Test status
Simulation time 5884672895 ps
CPU time 43.2 seconds
Started Jul 21 06:54:09 PM PDT 24
Finished Jul 21 06:54:53 PM PDT 24
Peak memory 206912 kb
Host smart-d780189f-06bc-46ab-91a8-747e70c191db
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2385350785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.2385350785
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.2354925842
Short name T1046
Test name
Test status
Simulation time 241616542 ps
CPU time 0.92 seconds
Started Jul 21 06:54:10 PM PDT 24
Finished Jul 21 06:54:11 PM PDT 24
Peak memory 206684 kb
Host smart-a6990e4c-d4ce-43c0-839d-b42809d54c0f
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2354925842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.2354925842
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.3552841707
Short name T2444
Test name
Test status
Simulation time 211607961 ps
CPU time 0.94 seconds
Started Jul 21 06:54:10 PM PDT 24
Finished Jul 21 06:54:12 PM PDT 24
Peak memory 206636 kb
Host smart-b81f977c-5a18-4606-baab-3abff21912aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35528
41707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.3552841707
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.17662825
Short name T1896
Test name
Test status
Simulation time 5943864642 ps
CPU time 166.69 seconds
Started Jul 21 06:54:12 PM PDT 24
Finished Jul 21 06:56:59 PM PDT 24
Peak memory 206948 kb
Host smart-50f2043e-396a-4ef2-ab07-0eade7b8779c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17662
825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.17662825
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.1227029863
Short name T2551
Test name
Test status
Simulation time 5872636796 ps
CPU time 51.59 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:55:08 PM PDT 24
Peak memory 206860 kb
Host smart-0e6a70ad-df52-4768-a7d3-2f8b6266561e
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1227029863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.1227029863
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.764090096
Short name T517
Test name
Test status
Simulation time 149154275 ps
CPU time 0.81 seconds
Started Jul 21 06:54:11 PM PDT 24
Finished Jul 21 06:54:12 PM PDT 24
Peak memory 206668 kb
Host smart-4b718531-4fc7-4af8-9724-7b5993b1dfa6
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=764090096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.764090096
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2371165662
Short name T1528
Test name
Test status
Simulation time 161945038 ps
CPU time 0.79 seconds
Started Jul 21 06:54:10 PM PDT 24
Finished Jul 21 06:54:12 PM PDT 24
Peak memory 206672 kb
Host smart-eda8edf8-8fcf-4733-9d58-c92c9fa7b95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23711
65662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2371165662
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.227028604
Short name T122
Test name
Test status
Simulation time 203278922 ps
CPU time 0.83 seconds
Started Jul 21 06:54:10 PM PDT 24
Finished Jul 21 06:54:11 PM PDT 24
Peak memory 206656 kb
Host smart-dad2de68-717b-46c8-8268-d04013f5c942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22702
8604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.227028604
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.870228957
Short name T781
Test name
Test status
Simulation time 192196298 ps
CPU time 0.92 seconds
Started Jul 21 06:54:11 PM PDT 24
Finished Jul 21 06:54:12 PM PDT 24
Peak memory 206688 kb
Host smart-fcbae3dc-869f-4460-b3f9-0c327677072e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87022
8957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.870228957
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2550668249
Short name T1881
Test name
Test status
Simulation time 193614046 ps
CPU time 0.84 seconds
Started Jul 21 06:54:12 PM PDT 24
Finished Jul 21 06:54:13 PM PDT 24
Peak memory 206684 kb
Host smart-2dd6501c-e99d-4ef0-946c-2d3d3f373329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25506
68249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2550668249
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.1315001099
Short name T964
Test name
Test status
Simulation time 185346250 ps
CPU time 0.81 seconds
Started Jul 21 06:54:11 PM PDT 24
Finished Jul 21 06:54:12 PM PDT 24
Peak memory 206640 kb
Host smart-ba55f0e4-043c-417c-9ceb-1aadbd212d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13150
01099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.1315001099
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.2053496062
Short name T1903
Test name
Test status
Simulation time 160317820 ps
CPU time 0.8 seconds
Started Jul 21 06:54:14 PM PDT 24
Finished Jul 21 06:54:15 PM PDT 24
Peak memory 206652 kb
Host smart-547fb1e2-d3d1-44e4-a969-d70af976bc0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20534
96062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.2053496062
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.1708451386
Short name T2558
Test name
Test status
Simulation time 216217664 ps
CPU time 0.94 seconds
Started Jul 21 06:54:10 PM PDT 24
Finished Jul 21 06:54:12 PM PDT 24
Peak memory 206664 kb
Host smart-45ddb6c5-da1c-4b5e-9663-9770fc930ba2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1708451386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.1708451386
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.184692151
Short name T1640
Test name
Test status
Simulation time 152580211 ps
CPU time 0.8 seconds
Started Jul 21 06:54:09 PM PDT 24
Finished Jul 21 06:54:10 PM PDT 24
Peak memory 206668 kb
Host smart-b26c44e6-64f1-4d09-b263-44826ae18bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18469
2151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.184692151
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.43102761
Short name T1958
Test name
Test status
Simulation time 97444908 ps
CPU time 0.7 seconds
Started Jul 21 06:54:15 PM PDT 24
Finished Jul 21 06:54:17 PM PDT 24
Peak memory 206784 kb
Host smart-078d1c74-44d4-47d4-8d4a-3ccc627de0f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43102
761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.43102761
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.1754439576
Short name T241
Test name
Test status
Simulation time 7770143948 ps
CPU time 17.68 seconds
Started Jul 21 06:54:17 PM PDT 24
Finished Jul 21 06:54:35 PM PDT 24
Peak memory 206932 kb
Host smart-ac222284-68fb-4d79-bb50-61f74578e13e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17544
39576 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.1754439576
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.3851915813
Short name T1215
Test name
Test status
Simulation time 193073550 ps
CPU time 0.82 seconds
Started Jul 21 06:54:15 PM PDT 24
Finished Jul 21 06:54:16 PM PDT 24
Peak memory 206676 kb
Host smart-176431c8-e83a-4118-b438-f034d4625f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38519
15813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.3851915813
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.4085513613
Short name T1278
Test name
Test status
Simulation time 217487143 ps
CPU time 0.85 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:54:17 PM PDT 24
Peak memory 206672 kb
Host smart-e7853861-7daf-4427-b71f-bad526baeaec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40855
13613 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.4085513613
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3216065013
Short name T151
Test name
Test status
Simulation time 7108003879 ps
CPU time 96.7 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:55:54 PM PDT 24
Peak memory 206920 kb
Host smart-4e4cb9c2-2bdd-4b65-91d7-f3ca908b0d22
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3216065013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3216065013
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.3535384781
Short name T2237
Test name
Test status
Simulation time 8998715415 ps
CPU time 62.7 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206904 kb
Host smart-12d2746d-2278-4ce1-b352-0af952115bfa
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3535384781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.3535384781
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.946110918
Short name T1182
Test name
Test status
Simulation time 17106263920 ps
CPU time 367.55 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 07:00:25 PM PDT 24
Peak memory 206904 kb
Host smart-11dd0a76-c341-49ee-b395-a9e02b99821c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=946110918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.946110918
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.1029376516
Short name T1035
Test name
Test status
Simulation time 233784620 ps
CPU time 0.88 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:54:18 PM PDT 24
Peak memory 206664 kb
Host smart-a9f3feeb-38f3-4c74-a92d-fccc682cce1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10293
76516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.1029376516
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.1244884980
Short name T2246
Test name
Test status
Simulation time 180089044 ps
CPU time 0.91 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:54:22 PM PDT 24
Peak memory 206692 kb
Host smart-53cca35f-0556-4cd2-a4fb-598973e1da71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12448
84980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.1244884980
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1206972190
Short name T1767
Test name
Test status
Simulation time 173393804 ps
CPU time 0.77 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:54:18 PM PDT 24
Peak memory 206664 kb
Host smart-f30f0fce-bca2-411f-9334-443cd6b37dea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12069
72190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1206972190
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.2923107004
Short name T1068
Test name
Test status
Simulation time 149236016 ps
CPU time 0.73 seconds
Started Jul 21 06:54:15 PM PDT 24
Finished Jul 21 06:54:16 PM PDT 24
Peak memory 206704 kb
Host smart-f86db4c0-4e55-453d-876e-15c0639fb21f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29231
07004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.2923107004
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.4046411134
Short name T1806
Test name
Test status
Simulation time 163190608 ps
CPU time 0.82 seconds
Started Jul 21 06:54:15 PM PDT 24
Finished Jul 21 06:54:16 PM PDT 24
Peak memory 206676 kb
Host smart-4c4dee20-fff9-4040-bb68-afd65712407b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40464
11134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.4046411134
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.3609494328
Short name T435
Test name
Test status
Simulation time 248912971 ps
CPU time 0.99 seconds
Started Jul 21 06:54:15 PM PDT 24
Finished Jul 21 06:54:17 PM PDT 24
Peak memory 206620 kb
Host smart-0b229793-3b75-4209-8efc-893f8161275e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36094
94328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.3609494328
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.3966970601
Short name T1381
Test name
Test status
Simulation time 5808500783 ps
CPU time 42.02 seconds
Started Jul 21 06:54:14 PM PDT 24
Finished Jul 21 06:54:57 PM PDT 24
Peak memory 206936 kb
Host smart-5ce2c722-3f6b-4a7e-9742-2d357d03586f
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3966970601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.3966970601
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.3192215068
Short name T556
Test name
Test status
Simulation time 174064752 ps
CPU time 0.82 seconds
Started Jul 21 06:54:13 PM PDT 24
Finished Jul 21 06:54:14 PM PDT 24
Peak memory 206672 kb
Host smart-d62980a6-fcbb-4d44-905d-d626c6e27e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31922
15068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.3192215068
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.36962313
Short name T1763
Test name
Test status
Simulation time 203480272 ps
CPU time 0.79 seconds
Started Jul 21 06:54:14 PM PDT 24
Finished Jul 21 06:54:15 PM PDT 24
Peak memory 206684 kb
Host smart-2471c8c9-8fd9-4ec5-96da-01b874916bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36962
313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.36962313
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.3669405622
Short name T346
Test name
Test status
Simulation time 1266159316 ps
CPU time 2.54 seconds
Started Jul 21 06:54:17 PM PDT 24
Finished Jul 21 06:54:20 PM PDT 24
Peak memory 206756 kb
Host smart-b164a454-6d0d-433b-8266-f6d75873c096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36694
05622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.3669405622
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.4157100434
Short name T1273
Test name
Test status
Simulation time 5681236392 ps
CPU time 53.43 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:55:14 PM PDT 24
Peak memory 206876 kb
Host smart-884c8d32-73e6-424a-a34b-88a7baee1f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41571
00434 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.4157100434
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.2685514095
Short name T2223
Test name
Test status
Simulation time 58222385 ps
CPU time 0.7 seconds
Started Jul 21 06:54:30 PM PDT 24
Finished Jul 21 06:54:31 PM PDT 24
Peak memory 206720 kb
Host smart-e82b1679-612f-475b-9d08-bb5b3b1e711e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2685514095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.2685514095
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.1729874300
Short name T649
Test name
Test status
Simulation time 3828283085 ps
CPU time 4.6 seconds
Started Jul 21 06:54:14 PM PDT 24
Finished Jul 21 06:54:19 PM PDT 24
Peak memory 206752 kb
Host smart-a70b0f54-56f4-4656-a416-18da7a873b26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1729874300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.1729874300
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.3123462164
Short name T979
Test name
Test status
Simulation time 13413851871 ps
CPU time 13.58 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:54:30 PM PDT 24
Peak memory 206796 kb
Host smart-9c35e1fb-3d9e-4aab-bf99-d9f15a1c482c
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3123462164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.3123462164
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.2051611795
Short name T220
Test name
Test status
Simulation time 23454166148 ps
CPU time 28.97 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:54:50 PM PDT 24
Peak memory 206972 kb
Host smart-b7c1b06d-0d83-4cc3-9041-5677a31ff447
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2051611795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.2051611795
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.779425664
Short name T766
Test name
Test status
Simulation time 174933160 ps
CPU time 0.8 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:54:21 PM PDT 24
Peak memory 206684 kb
Host smart-7347c815-b2b9-434a-8ef4-0437cb52a75e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77942
5664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.779425664
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.2373870864
Short name T566
Test name
Test status
Simulation time 221493631 ps
CPU time 0.82 seconds
Started Jul 21 06:54:16 PM PDT 24
Finished Jul 21 06:54:18 PM PDT 24
Peak memory 206652 kb
Host smart-a445f763-23c7-4632-adcf-691fc9898608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23738
70864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.2373870864
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.4262485683
Short name T1908
Test name
Test status
Simulation time 162235887 ps
CPU time 0.78 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:25 PM PDT 24
Peak memory 206664 kb
Host smart-8934d29f-c19e-453c-9a67-4e7aabb597a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42624
85683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.4262485683
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.464143787
Short name T2530
Test name
Test status
Simulation time 328528573 ps
CPU time 1.05 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206592 kb
Host smart-4ea14733-c73a-490d-98cd-23aa3a2725f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46414
3787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.464143787
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1315406718
Short name T1328
Test name
Test status
Simulation time 21415091526 ps
CPU time 42.62 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:55:03 PM PDT 24
Peak memory 206876 kb
Host smart-118307c1-ae9b-4bc1-9913-09f783de58f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13154
06718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1315406718
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.1003385740
Short name T1873
Test name
Test status
Simulation time 433142468 ps
CPU time 1.37 seconds
Started Jul 21 06:54:29 PM PDT 24
Finished Jul 21 06:54:31 PM PDT 24
Peak memory 206548 kb
Host smart-ca3e312d-7408-4b9d-a158-b5986b413009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10033
85740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.1003385740
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.1292843463
Short name T879
Test name
Test status
Simulation time 145186072 ps
CPU time 0.76 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:54:21 PM PDT 24
Peak memory 206652 kb
Host smart-27d2024f-1199-4c6c-9bed-f704b32dff42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12928
43463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.1292843463
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.3636540971
Short name T833
Test name
Test status
Simulation time 31487062 ps
CPU time 0.7 seconds
Started Jul 21 06:54:21 PM PDT 24
Finished Jul 21 06:54:22 PM PDT 24
Peak memory 206656 kb
Host smart-ce5d196b-3447-457e-82bb-0dd5360015da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36365
40971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.3636540971
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.1710450507
Short name T1921
Test name
Test status
Simulation time 745952564 ps
CPU time 1.88 seconds
Started Jul 21 06:54:21 PM PDT 24
Finished Jul 21 06:54:24 PM PDT 24
Peak memory 206556 kb
Host smart-cfe10315-538f-41f9-85ad-52035b48869a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17104
50507 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.1710450507
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.3043127829
Short name T1951
Test name
Test status
Simulation time 342661073 ps
CPU time 2.19 seconds
Started Jul 21 06:54:25 PM PDT 24
Finished Jul 21 06:54:28 PM PDT 24
Peak memory 206920 kb
Host smart-5551be39-710b-4722-a1af-0e3d02addb18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30431
27829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.3043127829
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.2909399733
Short name T2385
Test name
Test status
Simulation time 252757286 ps
CPU time 0.9 seconds
Started Jul 21 06:54:25 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206656 kb
Host smart-2ff43d7d-4fe9-4bde-9dbe-6bfa6329cceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29093
99733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.2909399733
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.3006933025
Short name T1238
Test name
Test status
Simulation time 140948571 ps
CPU time 0.75 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:26 PM PDT 24
Peak memory 206776 kb
Host smart-bfa00eb8-50b7-4f1d-add4-d18ab470e447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30069
33025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.3006933025
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.601232536
Short name T2721
Test name
Test status
Simulation time 232782894 ps
CPU time 1 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:54:21 PM PDT 24
Peak memory 206672 kb
Host smart-b8c47d29-4c87-4a69-acca-85f5e161cdf6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60123
2536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.601232536
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.2511003173
Short name T1639
Test name
Test status
Simulation time 8891974587 ps
CPU time 236.39 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:58:22 PM PDT 24
Peak memory 206992 kb
Host smart-fa9c030e-3ecb-4175-a12d-3f80a6e2f4c9
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2511003173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.2511003173
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_iso_retraction.2632117659
Short name T2680
Test name
Test status
Simulation time 3881009111 ps
CPU time 11.96 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:54:33 PM PDT 24
Peak memory 206944 kb
Host smart-ac6135d6-e020-4282-a430-5f7cb12b0d2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26321
17659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_iso_retraction.2632117659
Directory /workspace/8.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.2659251232
Short name T1292
Test name
Test status
Simulation time 180543069 ps
CPU time 0.82 seconds
Started Jul 21 06:54:17 PM PDT 24
Finished Jul 21 06:54:18 PM PDT 24
Peak memory 206692 kb
Host smart-9abf1c7c-ad68-4b6f-beb3-f1f9403d4ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26592
51232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.2659251232
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.4195372699
Short name T2731
Test name
Test status
Simulation time 23338357906 ps
CPU time 26.22 seconds
Started Jul 21 06:54:21 PM PDT 24
Finished Jul 21 06:54:48 PM PDT 24
Peak memory 206612 kb
Host smart-65fc1dfb-7905-4534-b101-23ed54a4b363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41953
72699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.4195372699
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2837995201
Short name T1012
Test name
Test status
Simulation time 3299168354 ps
CPU time 3.88 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:30 PM PDT 24
Peak memory 206656 kb
Host smart-2e8a036c-adc7-4afa-8a98-df2fed6a526f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28379
95201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2837995201
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.565015464
Short name T2506
Test name
Test status
Simulation time 9402499963 ps
CPU time 64.79 seconds
Started Jul 21 06:54:29 PM PDT 24
Finished Jul 21 06:55:35 PM PDT 24
Peak memory 206832 kb
Host smart-7dfb1ee6-5cd6-48c6-8f11-d2897ec5f48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56501
5464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.565015464
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.152135269
Short name T1625
Test name
Test status
Simulation time 3887111651 ps
CPU time 27.27 seconds
Started Jul 21 06:54:21 PM PDT 24
Finished Jul 21 06:54:49 PM PDT 24
Peak memory 206968 kb
Host smart-96d9a09c-3439-4f5d-aefb-0520b6b2471c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=152135269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.152135269
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.2341764960
Short name T444
Test name
Test status
Simulation time 249219569 ps
CPU time 0.86 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206776 kb
Host smart-95778f5c-cbe2-4e15-a61e-55872034f484
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2341764960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.2341764960
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.4181415844
Short name T2034
Test name
Test status
Simulation time 242908961 ps
CPU time 0.89 seconds
Started Jul 21 06:54:20 PM PDT 24
Finished Jul 21 06:54:22 PM PDT 24
Peak memory 206672 kb
Host smart-433e6717-4635-4c55-9976-3f5f970906f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41814
15844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.4181415844
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.1953771276
Short name T2733
Test name
Test status
Simulation time 5487970523 ps
CPU time 52.76 seconds
Started Jul 21 06:54:25 PM PDT 24
Finished Jul 21 06:55:19 PM PDT 24
Peak memory 206880 kb
Host smart-20f2b456-de1c-452f-870e-81d6e60dc33b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19537
71276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.1953771276
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.789089205
Short name T2158
Test name
Test status
Simulation time 4323791646 ps
CPU time 42.64 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:55:08 PM PDT 24
Peak memory 206900 kb
Host smart-59332e01-1da0-4d11-8ef1-9ee99bec27f9
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=789089205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.789089205
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.52132683
Short name T2426
Test name
Test status
Simulation time 227038173 ps
CPU time 0.86 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206680 kb
Host smart-6a29a5a3-3fae-4a2f-a54d-383c2444c13b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=52132683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.52132683
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.829470121
Short name T808
Test name
Test status
Simulation time 218507963 ps
CPU time 0.85 seconds
Started Jul 21 06:54:23 PM PDT 24
Finished Jul 21 06:54:25 PM PDT 24
Peak memory 206680 kb
Host smart-7c156d1e-806d-42b7-9f1b-ccae249e7212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82947
0121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.829470121
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3931582010
Short name T2667
Test name
Test status
Simulation time 188368069 ps
CPU time 0.8 seconds
Started Jul 21 06:54:25 PM PDT 24
Finished Jul 21 06:54:28 PM PDT 24
Peak memory 206668 kb
Host smart-de7c349d-8876-4f67-bc83-ec608cc92499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39315
82010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3931582010
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.2901434108
Short name T2669
Test name
Test status
Simulation time 171862536 ps
CPU time 0.84 seconds
Started Jul 21 06:54:25 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206696 kb
Host smart-9531512d-3bc1-4309-8dff-2ff6635f5f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29014
34108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.2901434108
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.426453147
Short name T1550
Test name
Test status
Simulation time 188836426 ps
CPU time 0.82 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206704 kb
Host smart-69d80218-01e3-4672-8d99-82cf93856bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
3147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.426453147
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3408345906
Short name T1459
Test name
Test status
Simulation time 141179491 ps
CPU time 0.77 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206672 kb
Host smart-20eeb365-734b-4268-a840-9a5eb65c61b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34083
45906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3408345906
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.1220127329
Short name T174
Test name
Test status
Simulation time 157802282 ps
CPU time 0.84 seconds
Started Jul 21 06:54:27 PM PDT 24
Finished Jul 21 06:54:29 PM PDT 24
Peak memory 206676 kb
Host smart-84a2a6c0-d556-46f7-ac61-089f8e4a8d76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12201
27329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.1220127329
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.3798830886
Short name T737
Test name
Test status
Simulation time 304627255 ps
CPU time 1.02 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:25 PM PDT 24
Peak memory 206672 kb
Host smart-fcc5534d-2dcb-4aec-9afe-a0ad302a506f
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3798830886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.3798830886
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.1344798630
Short name T1899
Test name
Test status
Simulation time 152556650 ps
CPU time 0.81 seconds
Started Jul 21 06:54:28 PM PDT 24
Finished Jul 21 06:54:30 PM PDT 24
Peak memory 206664 kb
Host smart-3f6c47ea-2a97-48cc-ad1b-a90bdb585779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13447
98630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.1344798630
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.4080453973
Short name T1314
Test name
Test status
Simulation time 61834045 ps
CPU time 0.69 seconds
Started Jul 21 06:54:25 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206640 kb
Host smart-3093683b-5dcb-46af-8fd5-227edc008ebb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40804
53973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.4080453973
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2137525438
Short name T2427
Test name
Test status
Simulation time 13880076436 ps
CPU time 28.07 seconds
Started Jul 21 06:54:30 PM PDT 24
Finished Jul 21 06:54:59 PM PDT 24
Peak memory 206892 kb
Host smart-3bab8173-e1f3-40a1-9525-59242da80fea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21375
25438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2137525438
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.3176106389
Short name T600
Test name
Test status
Simulation time 163435134 ps
CPU time 0.88 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206684 kb
Host smart-24051b15-bd1e-48c8-a20a-8e23b18fb66b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31761
06389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.3176106389
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.3770439192
Short name T2205
Test name
Test status
Simulation time 9692224657 ps
CPU time 253.36 seconds
Started Jul 21 06:54:30 PM PDT 24
Finished Jul 21 06:58:44 PM PDT 24
Peak memory 206276 kb
Host smart-0610b283-b59f-4e62-ae22-b814456fe23a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3770439192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.3770439192
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.732933564
Short name T2354
Test name
Test status
Simulation time 11977735074 ps
CPU time 78.89 seconds
Started Jul 21 06:54:23 PM PDT 24
Finished Jul 21 06:55:43 PM PDT 24
Peak memory 206940 kb
Host smart-1f34a843-bb41-4cc7-93a2-4832362a7df7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=732933564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.732933564
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.3749194650
Short name T2456
Test name
Test status
Simulation time 11738226477 ps
CPU time 231.57 seconds
Started Jul 21 06:54:25 PM PDT 24
Finished Jul 21 06:58:18 PM PDT 24
Peak memory 207056 kb
Host smart-66884812-7044-4458-805d-7aa18e23342b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3749194650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.3749194650
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.1264576349
Short name T380
Test name
Test status
Simulation time 291837131 ps
CPU time 1.01 seconds
Started Jul 21 06:54:30 PM PDT 24
Finished Jul 21 06:54:32 PM PDT 24
Peak memory 206664 kb
Host smart-1f20ad8d-80bc-4882-b706-15cfbd8fe3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12645
76349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.1264576349
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.4062470112
Short name T1030
Test name
Test status
Simulation time 255071623 ps
CPU time 0.89 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206704 kb
Host smart-3dd67be9-73d6-4fe1-9940-b58eadb52eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40624
70112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.4062470112
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.1162969152
Short name T2670
Test name
Test status
Simulation time 156811892 ps
CPU time 0.74 seconds
Started Jul 21 06:54:23 PM PDT 24
Finished Jul 21 06:54:25 PM PDT 24
Peak memory 206680 kb
Host smart-a0b2a2c0-6f0e-409b-97cc-0f58cdd8b3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11629
69152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.1162969152
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.3034979569
Short name T2326
Test name
Test status
Simulation time 154128318 ps
CPU time 0.78 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206660 kb
Host smart-5b8bc8c3-b92a-4657-8ceb-2d3332122090
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30349
79569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.3034979569
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.2170442514
Short name T1348
Test name
Test status
Simulation time 183977192 ps
CPU time 0.85 seconds
Started Jul 21 06:54:30 PM PDT 24
Finished Jul 21 06:54:31 PM PDT 24
Peak memory 205976 kb
Host smart-d42e9c9e-2fd3-4a20-9e44-b1d629101188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704
42514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.2170442514
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.988721760
Short name T1083
Test name
Test status
Simulation time 210215799 ps
CPU time 0.89 seconds
Started Jul 21 06:54:29 PM PDT 24
Finished Jul 21 06:54:30 PM PDT 24
Peak memory 206656 kb
Host smart-0a5eec53-a6ff-4bc0-b32a-cb17d3a456ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98872
1760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.988721760
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.657483090
Short name T1523
Test name
Test status
Simulation time 6498966937 ps
CPU time 184.98 seconds
Started Jul 21 06:54:28 PM PDT 24
Finished Jul 21 06:57:34 PM PDT 24
Peak memory 206880 kb
Host smart-c74c8808-16dc-4d65-b931-074868377129
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=657483090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.657483090
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.579961945
Short name T1230
Test name
Test status
Simulation time 235172556 ps
CPU time 0.91 seconds
Started Jul 21 06:54:24 PM PDT 24
Finished Jul 21 06:54:27 PM PDT 24
Peak memory 206704 kb
Host smart-978f6145-434c-4fb8-90b9-4bc22d486c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57996
1945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.579961945
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.2412952093
Short name T1702
Test name
Test status
Simulation time 172018315 ps
CPU time 0.82 seconds
Started Jul 21 06:54:32 PM PDT 24
Finished Jul 21 06:54:33 PM PDT 24
Peak memory 206648 kb
Host smart-adcfce15-bdfa-4e3f-98b5-1e89a9a4a285
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24129
52093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.2412952093
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.4289140859
Short name T654
Test name
Test status
Simulation time 321342418 ps
CPU time 1.02 seconds
Started Jul 21 06:54:28 PM PDT 24
Finished Jul 21 06:54:29 PM PDT 24
Peak memory 206640 kb
Host smart-59db6fc2-8603-4a70-87c1-015c4d0166c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42891
40859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.4289140859
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.866791339
Short name T2096
Test name
Test status
Simulation time 5620869214 ps
CPU time 55.66 seconds
Started Jul 21 06:54:30 PM PDT 24
Finished Jul 21 06:55:26 PM PDT 24
Peak memory 206916 kb
Host smart-6ce08a4a-2dfd-40be-87e4-e330f885c0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86679
1339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.866791339
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.343623518
Short name T960
Test name
Test status
Simulation time 55730314 ps
CPU time 0.69 seconds
Started Jul 21 06:54:46 PM PDT 24
Finished Jul 21 06:54:48 PM PDT 24
Peak memory 206708 kb
Host smart-f9c1bb1b-52bc-44eb-8e46-6a331e827f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=343623518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.343623518
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.4109285929
Short name T2271
Test name
Test status
Simulation time 3680996909 ps
CPU time 4.35 seconds
Started Jul 21 06:54:31 PM PDT 24
Finished Jul 21 06:54:36 PM PDT 24
Peak memory 206708 kb
Host smart-16a678f8-a467-4872-92ee-15a35653dffd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4109285929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.4109285929
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.3412309039
Short name T1049
Test name
Test status
Simulation time 13338745329 ps
CPU time 13.49 seconds
Started Jul 21 06:54:31 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206732 kb
Host smart-7d7a9f4b-3f86-46c4-ab9f-170bb3dc755b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3412309039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.3412309039
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.4103804497
Short name T1650
Test name
Test status
Simulation time 23409241616 ps
CPU time 21.33 seconds
Started Jul 21 06:54:29 PM PDT 24
Finished Jul 21 06:54:51 PM PDT 24
Peak memory 206924 kb
Host smart-a9dd7df5-db72-48b1-a541-2bae663a6af0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4103804497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.4103804497
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.2155306219
Short name T2403
Test name
Test status
Simulation time 157421557 ps
CPU time 0.8 seconds
Started Jul 21 06:54:31 PM PDT 24
Finished Jul 21 06:54:32 PM PDT 24
Peak memory 206636 kb
Host smart-1c8dc85a-3b72-47dd-9e1f-035ad1f90097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21553
06219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.2155306219
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.633287321
Short name T1432
Test name
Test status
Simulation time 201432441 ps
CPU time 0.83 seconds
Started Jul 21 06:54:33 PM PDT 24
Finished Jul 21 06:54:35 PM PDT 24
Peak memory 206680 kb
Host smart-9157fe64-ed4f-4646-b037-3741d3ebfeb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63328
7321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.633287321
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2747693440
Short name T1462
Test name
Test status
Simulation time 355977034 ps
CPU time 1.17 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206416 kb
Host smart-b5a44dd0-6d44-4cbd-ba6a-afadf4751ef4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27476
93440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2747693440
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.2145116597
Short name T1788
Test name
Test status
Simulation time 368237705 ps
CPU time 1.1 seconds
Started Jul 21 06:54:33 PM PDT 24
Finished Jul 21 06:54:35 PM PDT 24
Peak memory 206644 kb
Host smart-48a41be3-5d27-49d1-b53e-17b92908683a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21451
16597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.2145116597
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.2459876132
Short name T1338
Test name
Test status
Simulation time 9848377384 ps
CPU time 18.34 seconds
Started Jul 21 06:54:36 PM PDT 24
Finished Jul 21 06:54:54 PM PDT 24
Peak memory 206992 kb
Host smart-b632f39d-671e-4722-b805-dc2829ee5783
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24598
76132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.2459876132
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.3489002256
Short name T1610
Test name
Test status
Simulation time 336581709 ps
CPU time 1.11 seconds
Started Jul 21 06:54:35 PM PDT 24
Finished Jul 21 06:54:36 PM PDT 24
Peak memory 206672 kb
Host smart-6e1565a1-9a8d-4aa8-92e7-dd564c90e1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34890
02256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.3489002256
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.1789385042
Short name T771
Test name
Test status
Simulation time 141455353 ps
CPU time 0.74 seconds
Started Jul 21 06:54:33 PM PDT 24
Finished Jul 21 06:54:34 PM PDT 24
Peak memory 206660 kb
Host smart-d4a34dbe-c3b3-425d-845a-2e771290985b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17893
85042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.1789385042
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.661222888
Short name T1218
Test name
Test status
Simulation time 35589326 ps
CPU time 0.64 seconds
Started Jul 21 06:54:34 PM PDT 24
Finished Jul 21 06:54:35 PM PDT 24
Peak memory 206656 kb
Host smart-d4da0a20-9c06-4cfd-8a64-ab999a4da4fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66122
2888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.661222888
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.163058265
Short name T1370
Test name
Test status
Simulation time 761080820 ps
CPU time 1.76 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:01 PM PDT 24
Peak memory 206592 kb
Host smart-68e2908f-e3cc-48a8-9135-ef85dc8910fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16305
8265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.163058265
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.3259240505
Short name T2381
Test name
Test status
Simulation time 312242411 ps
CPU time 1.86 seconds
Started Jul 21 06:54:34 PM PDT 24
Finished Jul 21 06:54:37 PM PDT 24
Peak memory 206720 kb
Host smart-a5eea212-c643-4c4d-b54a-c2aae4e3b689
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32592
40505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.3259240505
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.1763695125
Short name T569
Test name
Test status
Simulation time 178260209 ps
CPU time 0.87 seconds
Started Jul 21 06:55:42 PM PDT 24
Finished Jul 21 06:55:45 PM PDT 24
Peak memory 205120 kb
Host smart-c52eeeba-584d-4e77-872e-29e59b012022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17636
95125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.1763695125
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.2010308595
Short name T1141
Test name
Test status
Simulation time 142142119 ps
CPU time 0.73 seconds
Started Jul 21 06:54:35 PM PDT 24
Finished Jul 21 06:54:37 PM PDT 24
Peak memory 206696 kb
Host smart-9dd27ae1-4178-4c74-b6e9-a837ff8c1db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20103
08595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.2010308595
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.2098234081
Short name T722
Test name
Test status
Simulation time 248000396 ps
CPU time 0.93 seconds
Started Jul 21 06:54:35 PM PDT 24
Finished Jul 21 06:54:36 PM PDT 24
Peak memory 206668 kb
Host smart-87ed83c7-09e1-4a22-98a1-2e1b00077ff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20982
34081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.2098234081
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.4174364081
Short name T983
Test name
Test status
Simulation time 11393337088 ps
CPU time 40.85 seconds
Started Jul 21 06:54:32 PM PDT 24
Finished Jul 21 06:55:13 PM PDT 24
Peak memory 206860 kb
Host smart-bdcfbf4a-5a4b-4cd5-9fcf-cafa1da9704b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41743
64081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.4174364081
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.547075415
Short name T701
Test name
Test status
Simulation time 194063935 ps
CPU time 0.8 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:54:39 PM PDT 24
Peak memory 206664 kb
Host smart-fe0d816a-5215-4b8d-aafb-efa1318ec0c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54707
5415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.547075415
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.2751359453
Short name T889
Test name
Test status
Simulation time 23306189428 ps
CPU time 22.84 seconds
Started Jul 21 06:54:33 PM PDT 24
Finished Jul 21 06:54:56 PM PDT 24
Peak memory 206800 kb
Host smart-f92efa38-69c3-4111-b9ba-048ea0cb9745
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27513
59453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.2751359453
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.383785551
Short name T1955
Test name
Test status
Simulation time 3297548867 ps
CPU time 4.35 seconds
Started Jul 21 06:55:42 PM PDT 24
Finished Jul 21 06:55:48 PM PDT 24
Peak memory 205260 kb
Host smart-a2ef392c-0f87-4645-8e66-b51d8759aee1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38378
5551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.383785551
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.3083606740
Short name T2228
Test name
Test status
Simulation time 9118588759 ps
CPU time 87.43 seconds
Started Jul 21 06:54:34 PM PDT 24
Finished Jul 21 06:56:02 PM PDT 24
Peak memory 206956 kb
Host smart-3bc1e95d-1a18-4a83-8024-6113a5ddedff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30836
06740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.3083606740
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.4134471289
Short name T5
Test name
Test status
Simulation time 4927532341 ps
CPU time 35.67 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:55:13 PM PDT 24
Peak memory 206856 kb
Host smart-1e8623ac-1ecf-4723-9ad0-d8b3191b0e47
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4134471289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.4134471289
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.3799062083
Short name T1880
Test name
Test status
Simulation time 268906531 ps
CPU time 0.94 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:54:40 PM PDT 24
Peak memory 206664 kb
Host smart-897db8f7-df7c-4ec7-a75b-24d60829c5bc
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3799062083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.3799062083
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.1136876110
Short name T2416
Test name
Test status
Simulation time 245223467 ps
CPU time 0.94 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206416 kb
Host smart-141d1722-b216-477b-b490-49ec31574639
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11368
76110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.1136876110
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.2012664195
Short name T1552
Test name
Test status
Simulation time 4049604022 ps
CPU time 113.59 seconds
Started Jul 21 06:54:41 PM PDT 24
Finished Jul 21 06:56:36 PM PDT 24
Peak memory 206904 kb
Host smart-0e8f67d2-0430-4c67-b0e0-e9287ceba853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20126
64195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.2012664195
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3401244404
Short name T1883
Test name
Test status
Simulation time 5396428777 ps
CPU time 45.84 seconds
Started Jul 21 06:54:38 PM PDT 24
Finished Jul 21 06:55:24 PM PDT 24
Peak memory 206928 kb
Host smart-d99755af-8ad0-4735-b6ee-66ce3bb9fc19
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3401244404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3401244404
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.2139128553
Short name T2363
Test name
Test status
Simulation time 220420063 ps
CPU time 0.86 seconds
Started Jul 21 06:54:38 PM PDT 24
Finished Jul 21 06:54:40 PM PDT 24
Peak memory 206696 kb
Host smart-4107c7cc-3110-412b-a3b4-710a7e97a6aa
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2139128553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.2139128553
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.16601395
Short name T700
Test name
Test status
Simulation time 135959956 ps
CPU time 0.77 seconds
Started Jul 21 06:54:40 PM PDT 24
Finished Jul 21 06:54:41 PM PDT 24
Peak memory 206680 kb
Host smart-986765be-534c-44e3-bc32-b5067c1aea69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16601
395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.16601395
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.3120741969
Short name T2688
Test name
Test status
Simulation time 219068892 ps
CPU time 0.84 seconds
Started Jul 21 06:54:40 PM PDT 24
Finished Jul 21 06:54:42 PM PDT 24
Peak memory 206692 kb
Host smart-eee30d91-6952-436f-abf5-1bff51aea2bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31207
41969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.3120741969
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.4150921104
Short name T1416
Test name
Test status
Simulation time 208215364 ps
CPU time 0.9 seconds
Started Jul 21 06:54:38 PM PDT 24
Finished Jul 21 06:54:40 PM PDT 24
Peak memory 206628 kb
Host smart-2e819fa5-858d-4d20-845c-3862cce65e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41509
21104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.4150921104
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2926049816
Short name T1305
Test name
Test status
Simulation time 165813767 ps
CPU time 0.78 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:55:59 PM PDT 24
Peak memory 206424 kb
Host smart-9ae109a5-b39a-4427-a4a9-a723ff1285ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29260
49816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2926049816
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.679558531
Short name T2652
Test name
Test status
Simulation time 174370123 ps
CPU time 0.76 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:55:58 PM PDT 24
Peak memory 206436 kb
Host smart-742aeb42-157d-42cd-aed0-ccfc7d617e6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67955
8531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.679558531
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.3768010617
Short name T158
Test name
Test status
Simulation time 152033785 ps
CPU time 0.78 seconds
Started Jul 21 06:54:40 PM PDT 24
Finished Jul 21 06:54:41 PM PDT 24
Peak memory 206668 kb
Host smart-975cf6dd-92bf-402e-a8b6-97111d88a36f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37680
10617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.3768010617
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.205761038
Short name T533
Test name
Test status
Simulation time 229816236 ps
CPU time 0.92 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:54:39 PM PDT 24
Peak memory 206700 kb
Host smart-35fa15fd-cc88-4afd-a66d-f88be0695d41
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=205761038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.205761038
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.3428088778
Short name T623
Test name
Test status
Simulation time 150473964 ps
CPU time 0.74 seconds
Started Jul 21 06:54:40 PM PDT 24
Finished Jul 21 06:54:41 PM PDT 24
Peak memory 206684 kb
Host smart-545393fa-3b55-4ee1-830f-47f70772a08c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34280
88778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.3428088778
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.2737902390
Short name T30
Test name
Test status
Simulation time 64943782 ps
CPU time 0.69 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:54:39 PM PDT 24
Peak memory 206664 kb
Host smart-8bb6d12f-30a4-4d2b-a935-998e28802edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27379
02390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.2737902390
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.3202265503
Short name T1593
Test name
Test status
Simulation time 16448669525 ps
CPU time 34.27 seconds
Started Jul 21 06:54:40 PM PDT 24
Finished Jul 21 06:55:16 PM PDT 24
Peak memory 215140 kb
Host smart-6f538e21-e1b6-4b73-b6b6-b595247c654c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32022
65503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.3202265503
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.368805743
Short name T539
Test name
Test status
Simulation time 167419016 ps
CPU time 0.83 seconds
Started Jul 21 06:54:40 PM PDT 24
Finished Jul 21 06:54:42 PM PDT 24
Peak memory 206632 kb
Host smart-4119f78d-0e4f-4b0e-942d-96239c77dc22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36880
5743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.368805743
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2643112420
Short name T2681
Test name
Test status
Simulation time 209418239 ps
CPU time 0.86 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:54:40 PM PDT 24
Peak memory 206700 kb
Host smart-4e6fe132-3b73-4f9a-bf47-627c4ab1a914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26431
12420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2643112420
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.813371991
Short name T1761
Test name
Test status
Simulation time 8945357671 ps
CPU time 242.99 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:58:42 PM PDT 24
Peak memory 206908 kb
Host smart-d4c2d0a0-c65f-40ec-93eb-aa184e5143a6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=813371991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.813371991
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.1172866963
Short name T166
Test name
Test status
Simulation time 12200914954 ps
CPU time 250.22 seconds
Started Jul 21 06:54:37 PM PDT 24
Finished Jul 21 06:58:47 PM PDT 24
Peak memory 206936 kb
Host smart-e6a00fbd-afc0-430f-9462-e625a33d5ff6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1172866963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.1172866963
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.2092488804
Short name T396
Test name
Test status
Simulation time 10927518961 ps
CPU time 178.62 seconds
Started Jul 21 06:55:56 PM PDT 24
Finished Jul 21 06:58:56 PM PDT 24
Peak memory 206712 kb
Host smart-e897717c-dc60-4ad3-a2ca-cf40e3cbbe3b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2092488804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.2092488804
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.412265160
Short name T2674
Test name
Test status
Simulation time 216440511 ps
CPU time 0.9 seconds
Started Jul 21 06:55:57 PM PDT 24
Finished Jul 21 06:56:00 PM PDT 24
Peak memory 206424 kb
Host smart-927d9ceb-383d-4a0a-b4dc-31b3b4556a2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41226
5160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.412265160
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.1177599834
Short name T1687
Test name
Test status
Simulation time 206540996 ps
CPU time 0.85 seconds
Started Jul 21 06:54:40 PM PDT 24
Finished Jul 21 06:54:42 PM PDT 24
Peak memory 206668 kb
Host smart-4c49b346-b132-47bb-951f-85f01e2e29c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11775
99834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.1177599834
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.2068543895
Short name T1052
Test name
Test status
Simulation time 158398652 ps
CPU time 0.76 seconds
Started Jul 21 06:54:43 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206680 kb
Host smart-f6bfe59b-7885-4a88-9619-1a369196d25c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20685
43895 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.2068543895
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.2235912980
Short name T1327
Test name
Test status
Simulation time 145863125 ps
CPU time 0.83 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:54:44 PM PDT 24
Peak memory 206684 kb
Host smart-4fb2d92f-baca-4c16-beff-c37e602a0294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22359
12980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.2235912980
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.252101162
Short name T2181
Test name
Test status
Simulation time 152163454 ps
CPU time 0.77 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:54:44 PM PDT 24
Peak memory 206660 kb
Host smart-bdb4e59b-bfd8-413e-bf00-098b68fc09ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25210
1162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.252101162
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.2903435637
Short name T793
Test name
Test status
Simulation time 202953563 ps
CPU time 0.91 seconds
Started Jul 21 06:54:43 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206680 kb
Host smart-cfc5cf14-fb25-4a16-b2ea-30968f1703b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29034
35637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.2903435637
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.2782697452
Short name T1885
Test name
Test status
Simulation time 5428590463 ps
CPU time 37.51 seconds
Started Jul 21 06:54:43 PM PDT 24
Finished Jul 21 06:55:22 PM PDT 24
Peak memory 206932 kb
Host smart-59757711-ffca-4f4a-a3a6-890a225f7622
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2782697452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.2782697452
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2747905110
Short name T2194
Test name
Test status
Simulation time 165138036 ps
CPU time 0.78 seconds
Started Jul 21 06:54:43 PM PDT 24
Finished Jul 21 06:54:45 PM PDT 24
Peak memory 206692 kb
Host smart-ec71c737-e1a4-43bb-b584-e9ebf3036dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27479
05110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2747905110
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.3469243549
Short name T621
Test name
Test status
Simulation time 162046165 ps
CPU time 0.82 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:54:44 PM PDT 24
Peak memory 206660 kb
Host smart-9ec82a5b-0d4e-4f40-b46e-0484d87b2704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34692
43549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.3469243549
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.2160937930
Short name T1844
Test name
Test status
Simulation time 891758332 ps
CPU time 2.09 seconds
Started Jul 21 06:54:43 PM PDT 24
Finished Jul 21 06:54:47 PM PDT 24
Peak memory 206804 kb
Host smart-020ff0a4-6ca4-4e88-a8d3-7f12613a473f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21609
37930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.2160937930
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.4228337358
Short name T2707
Test name
Test status
Simulation time 5063117764 ps
CPU time 35.05 seconds
Started Jul 21 06:54:42 PM PDT 24
Finished Jul 21 06:55:18 PM PDT 24
Peak memory 206884 kb
Host smart-9386e6a7-c9d1-4b34-b423-7dcd56174b93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42283
37358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.4228337358
Directory /workspace/9.usbdev_streaming_out/latest
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