Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	77317	1		T1	2		T2	2		T3	2
all_values[1]	77317	1		T1	2		T2	2		T3	2
all_values[2]	77317	1		T1	2		T2	2		T3	2
all_values[3]	77317	1		T1	2		T2	2		T3	2
all_values[4]	77317	1		T1	2		T2	2		T3	2
all_values[5]	77317	1		T1	2		T2	2		T3	2
all_values[6]	77317	1		T1	2		T2	2		T3	2
all_values[7]	77317	1		T1	2		T2	2		T3	2
all_values[8]	77317	1		T1	2		T2	2		T3	2
all_values[9]	77317	1		T1	2		T2	2		T3	2
all_values[10]	77317	1		T1	2		T2	2		T3	2
all_values[11]	77317	1		T1	2		T2	2		T3	2
all_values[12]	77317	1		T1	2		T2	2		T3	2
all_values[13]	77317	1		T1	2		T2	2		T3	2
all_values[14]	77317	1		T1	2		T2	2		T3	2
all_values[15]	77317	1		T1	2		T2	2		T3	2
all_values[16]	77317	1		T1	2		T2	2		T3	2
all_values[17]	77317	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1384912	1		T1	36		T2	36		T3	36
auto[1]	6794	1		T38	3		T27	3		T39	3

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1386817	1		T1	36		T2	36		T3	36
auto[1]	4889	1		T201	121		T202	62		T203	74

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	76344	1		T1	2		T2	2		T3	2
all_values[0]	auto[0]	auto[1]	156	1		T201	4		T202	2		T203	4
all_values[0]	auto[1]	auto[0]	696	1		T38	3		T29	4		T21	4
all_values[0]	auto[1]	auto[1]	121	1		T201	4		T202	3		T203	1
all_values[1]	auto[0]	auto[0]	75532	1		T1	2		T2	2		T3	2
all_values[1]	auto[0]	auto[1]	96	1		T201	2		T202	3		T203	1
all_values[1]	auto[1]	auto[0]	1539	1		T27	3		T7	2		T18	2
all_values[1]	auto[1]	auto[1]	150	1		T201	5		T202	2		T203	4
all_values[2]	auto[0]	auto[0]	76920	1		T1	2		T2	2		T3	2
all_values[2]	auto[0]	auto[1]	138	1		T201	4		T203	4		T204	1
all_values[2]	auto[1]	auto[0]	126	1		T49	2		T50	2		T51	2
all_values[2]	auto[1]	auto[1]	133	1		T201	2		T202	3		T203	1
all_values[3]	auto[0]	auto[0]	75583	1		T1	2		T2	2		T3	2
all_values[3]	auto[0]	auto[1]	165	1		T201	6		T203	3		T204	4
all_values[3]	auto[1]	auto[0]	1445	1		T72	1429		T285	1		T287	1
all_values[3]	auto[1]	auto[1]	124	1		T201	2		T202	5		T203	2
all_values[4]	auto[0]	auto[0]	77015	1		T1	2		T2	2		T3	2
all_values[4]	auto[0]	auto[1]	153	1		T201	5		T202	3		T203	4
all_values[4]	auto[1]	auto[0]	33	1		T73	2		T202	1		T284	1
all_values[4]	auto[1]	auto[1]	116	1		T201	2		T203	1		T204	4
all_values[5]	auto[0]	auto[0]	77016	1		T1	2		T2	2		T3	2
all_values[5]	auto[0]	auto[1]	155	1		T201	6		T202	4		T203	4
all_values[5]	auto[1]	auto[0]	26	1		T201	1		T284	1		T288	1
all_values[5]	auto[1]	auto[1]	120	1		T201	1		T202	1		T203	1
all_values[6]	auto[0]	auto[0]	77018	1		T1	2		T2	2		T3	2
all_values[6]	auto[0]	auto[1]	128	1		T201	2		T202	1		T203	3
all_values[6]	auto[1]	auto[0]	40	1		T201	1		T203	2		T284	3
all_values[6]	auto[1]	auto[1]	131	1		T201	4		T202	3		T204	5
all_values[7]	auto[0]	auto[0]	77003	1		T1	2		T2	2		T3	2
all_values[7]	auto[0]	auto[1]	138	1		T201	1		T202	3		T203	3
all_values[7]	auto[1]	auto[0]	36	1		T59	2		T60	2		T61	2
all_values[7]	auto[1]	auto[1]	140	1		T201	7		T202	2		T203	2
all_values[8]	auto[0]	auto[0]	77006	1		T1	2		T2	2		T3	2
all_values[8]	auto[0]	auto[1]	119	1		T201	1		T202	1		T203	1
all_values[8]	auto[1]	auto[0]	33	1		T31	11		T201	3		T284	5
all_values[8]	auto[1]	auto[1]	159	1		T201	3		T202	4		T203	4
all_values[9]	auto[0]	auto[0]	76989	1		T1	2		T2	2		T3	2
all_values[9]	auto[0]	auto[1]	157	1		T201	6		T203	3		T204	6
all_values[9]	auto[1]	auto[0]	49	1		T56	5		T70	5		T71	5
all_values[9]	auto[1]	auto[1]	122	1		T201	1		T203	2		T204	2
all_values[10]	auto[0]	auto[0]	77020	1		T1	2		T2	2		T3	2
all_values[10]	auto[0]	auto[1]	137	1		T201	4		T202	3		T203	4
all_values[10]	auto[1]	auto[0]	34	1		T201	1		T285	1		T289	2
all_values[10]	auto[1]	auto[1]	126	1		T201	2		T202	2		T203	1
all_values[11]	auto[0]	auto[0]	76927	1		T1	2		T2	2		T3	2
all_values[11]	auto[0]	auto[1]	129	1		T201	6		T203	5		T204	1
all_values[11]	auto[1]	auto[0]	118	1		T57	2		T78	2		T79	2
all_values[11]	auto[1]	auto[1]	143	1		T201	1		T204	6		T284	3
all_values[12]	auto[0]	auto[0]	77001	1		T1	2		T2	2		T3	2
all_values[12]	auto[0]	auto[1]	120	1		T201	4		T202	1		T204	3
all_values[12]	auto[1]	auto[0]	44	1		T39	3		T80	3		T81	3
all_values[12]	auto[1]	auto[1]	152	1		T201	4		T202	3		T204	3
all_values[13]	auto[0]	auto[0]	77022	1		T1	2		T2	2		T3	2
all_values[13]	auto[0]	auto[1]	129	1		T201	2		T202	4		T204	1
all_values[13]	auto[1]	auto[0]	33	1		T284	2		T285	5		T289	1
all_values[13]	auto[1]	auto[1]	133	1		T201	6		T203	4		T204	7
all_values[14]	auto[0]	auto[0]	77007	1		T1	2		T2	2		T3	2
all_values[14]	auto[0]	auto[1]	123	1		T201	2		T203	1		T204	4
all_values[14]	auto[1]	auto[0]	31	1		T201	1		T202	4		T203	1
all_values[14]	auto[1]	auto[1]	156	1		T201	5		T203	3		T204	2
all_values[15]	auto[0]	auto[0]	77020	1		T1	2		T2	2		T3	2
all_values[15]	auto[0]	auto[1]	151	1		T202	4		T203	3		T204	7
all_values[15]	auto[1]	auto[0]	31	1		T201	1		T202	1		T203	2
all_values[15]	auto[1]	auto[1]	115	1		T201	3		T204	1		T284	1
all_values[16]	auto[0]	auto[0]	76999	1		T1	2		T2	2		T3	2
all_values[16]	auto[0]	auto[1]	140	1		T201	4		T204	5		T290	1
all_values[16]	auto[1]	auto[0]	53	1		T75	8		T76	8		T77	8
all_values[16]	auto[1]	auto[1]	125	1		T201	3		T204	2		T284	4
all_values[17]	auto[0]	auto[0]	77004	1		T1	2		T2	2		T3	2
all_values[17]	auto[0]	auto[1]	152	1		T201	4		T202	1		T204	3
all_values[17]	auto[1]	auto[0]	24	1		T65	2		T66	2		T201	1
all_values[17]	auto[1]	auto[1]	137	1		T201	3		T202	4		T203	5