Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	77317	1		T1	2		T2	2		T3	2
all_pins[1]	77317	1		T1	2		T2	2		T3	2
all_pins[2]	77317	1		T1	2		T2	2		T3	2
all_pins[3]	77317	1		T1	2		T2	2		T3	2
all_pins[4]	77317	1		T1	2		T2	2		T3	2
all_pins[5]	77317	1		T1	2		T2	2		T3	2
all_pins[6]	77317	1		T1	2		T2	2		T3	2
all_pins[7]	77317	1		T1	2		T2	2		T3	2
all_pins[8]	77317	1		T1	2		T2	2		T3	2
all_pins[9]	77317	1		T1	2		T2	2		T3	2
all_pins[10]	77317	1		T1	2		T2	2		T3	2
all_pins[11]	77317	1		T1	2		T2	2		T3	2
all_pins[12]	77317	1		T1	2		T2	2		T3	2
all_pins[13]	77317	1		T1	2		T2	2		T3	2
all_pins[14]	77317	1		T1	2		T2	2		T3	2
all_pins[15]	77317	1		T1	2		T2	2		T3	2
all_pins[16]	77317	1		T1	2		T2	2		T3	2
all_pins[17]	77317	1		T1	2		T2	2		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1389471	1		T1	36		T2	36		T3	36
values[0x1]	2235	1		T27	1		T39	1		T29	1
transitions[0x0=>0x1]	1939	1		T27	1		T39	1		T29	1
transitions[0x1=>0x0]	1956	1		T27	1		T39	1		T29	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	77224	1		T1	2		T2	2		T3	2
all_pins[0]	values[0x1]	93	1		T29	1		T21	1		T58	1
all_pins[0]	transitions[0x0=>0x1]	85	1		T29	1		T21	1		T58	1
all_pins[0]	transitions[0x1=>0x0]	1006	1		T27	1		T7	1		T18	1
all_pins[1]	values[0x0]	76303	1		T1	2		T2	2		T3	2
all_pins[1]	values[0x1]	1014	1		T27	1		T7	1		T18	1
all_pins[1]	transitions[0x0=>0x1]	989	1		T27	1		T7	1		T18	1
all_pins[1]	transitions[0x1=>0x0]	103	1		T49	1		T50	1		T51	1
all_pins[2]	values[0x0]	77189	1		T1	2		T2	2		T3	2
all_pins[2]	values[0x1]	128	1		T49	1		T50	1		T51	1
all_pins[2]	transitions[0x0=>0x1]	103	1		T49	1		T50	1		T51	1
all_pins[2]	transitions[0x1=>0x0]	36	1		T72	1		T201	2		T204	2
all_pins[3]	values[0x0]	77256	1		T1	2		T2	2		T3	2
all_pins[3]	values[0x1]	61	1		T72	1		T201	2		T202	4
all_pins[3]	transitions[0x0=>0x1]	50	1		T72	1		T201	1		T202	4
all_pins[3]	transitions[0x1=>0x0]	45	1		T73	1		T203	1		T284	1
all_pins[4]	values[0x0]	77261	1		T1	2		T2	2		T3	2
all_pins[4]	values[0x1]	56	1		T73	1		T201	1		T203	1
all_pins[4]	transitions[0x0=>0x1]	42	1		T73	1		T201	1		T203	1
all_pins[4]	transitions[0x1=>0x0]	45	1		T201	1		T202	1		T291	1
all_pins[5]	values[0x0]	77258	1		T1	2		T2	2		T3	2
all_pins[5]	values[0x1]	59	1		T201	1		T202	1		T204	2
all_pins[5]	transitions[0x0=>0x1]	48	1		T201	1		T202	1		T290	1
all_pins[5]	transitions[0x1=>0x0]	53	1		T204	2		T290	2		T288	1
all_pins[6]	values[0x0]	77253	1		T1	2		T2	2		T3	2
all_pins[6]	values[0x1]	64	1		T204	4		T290	2		T291	1
all_pins[6]	transitions[0x0=>0x1]	50	1		T204	2		T290	2		T291	1
all_pins[6]	transitions[0x1=>0x0]	48	1		T59	1		T60	1		T61	1
all_pins[7]	values[0x0]	77255	1		T1	2		T2	2		T3	2
all_pins[7]	values[0x1]	62	1		T59	1		T60	1		T61	1
all_pins[7]	transitions[0x0=>0x1]	44	1		T59	1		T60	1		T61	1
all_pins[7]	transitions[0x1=>0x0]	46	1		T31	1		T201	1		T202	1
all_pins[8]	values[0x0]	77253	1		T1	2		T2	2		T3	2
all_pins[8]	values[0x1]	64	1		T31	1		T201	1		T202	1
all_pins[8]	transitions[0x0=>0x1]	53	1		T31	1		T201	1		T202	1
all_pins[8]	transitions[0x1=>0x0]	55	1		T56	2		T70	2		T71	2
all_pins[9]	values[0x0]	77251	1		T1	2		T2	2		T3	2
all_pins[9]	values[0x1]	66	1		T56	2		T70	2		T71	2
all_pins[9]	transitions[0x0=>0x1]	46	1		T56	2		T70	2		T71	2
all_pins[9]	transitions[0x1=>0x0]	43	1		T201	2		T202	2		T204	5
all_pins[10]	values[0x0]	77254	1		T1	2		T2	2		T3	2
all_pins[10]	values[0x1]	63	1		T201	2		T202	2		T203	1
all_pins[10]	transitions[0x0=>0x1]	48	1		T201	2		T202	2		T203	1
all_pins[10]	transitions[0x1=>0x0]	97	1		T57	1		T78	1		T79	1
all_pins[11]	values[0x0]	77205	1		T1	2		T2	2		T3	2
all_pins[11]	values[0x1]	112	1		T57	1		T78	1		T79	1
all_pins[11]	transitions[0x0=>0x1]	100	1		T57	1		T78	1		T79	1
all_pins[11]	transitions[0x1=>0x0]	54	1		T39	1		T80	1		T81	1
all_pins[12]	values[0x0]	77251	1		T1	2		T2	2		T3	2
all_pins[12]	values[0x1]	66	1		T39	1		T80	1		T81	1
all_pins[12]	transitions[0x0=>0x1]	51	1		T39	1		T80	1		T81	1
all_pins[12]	transitions[0x1=>0x0]	40	1		T201	2		T203	1		T204	3
all_pins[13]	values[0x0]	77262	1		T1	2		T2	2		T3	2
all_pins[13]	values[0x1]	55	1		T201	2		T203	1		T204	5
all_pins[13]	transitions[0x0=>0x1]	40	1		T201	1		T203	1		T204	4
all_pins[13]	transitions[0x1=>0x0]	54	1		T201	3		T291	4		T287	2
all_pins[14]	values[0x0]	77248	1		T1	2		T2	2		T3	2
all_pins[14]	values[0x1]	69	1		T201	4		T204	1		T291	5
all_pins[14]	transitions[0x0=>0x1]	57	1		T201	2		T204	1		T291	4
all_pins[14]	transitions[0x1=>0x0]	46	1		T284	1		T290	1		T291	1
all_pins[15]	values[0x0]	77259	1		T1	2		T2	2		T3	2
all_pins[15]	values[0x1]	58	1		T201	2		T284	1		T290	1
all_pins[15]	transitions[0x0=>0x1]	42	1		T201	2		T290	1		T291	2
all_pins[15]	transitions[0x1=>0x0]	72	1		T75	4		T76	4		T77	4
all_pins[16]	values[0x0]	77229	1		T1	2		T2	2		T3	2
all_pins[16]	values[0x1]	88	1		T75	4		T76	4		T77	4
all_pins[16]	transitions[0x0=>0x1]	66	1		T75	4		T76	4		T77	4
all_pins[16]	transitions[0x1=>0x0]	35	1		T65	1		T66	1		T202	1
all_pins[17]	values[0x0]	77260	1		T1	2		T2	2		T3	2
all_pins[17]	values[0x1]	57	1		T65	1		T66	1		T201	1
all_pins[17]	transitions[0x0=>0x1]	25	1		T65	1		T66	1		T202	1
all_pins[17]	transitions[0x1=>0x0]	78	1		T29	1		T21	1		T58	1