Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	275	1		T201	7		T202	4		T203	4
all_values[1]	275	1		T201	7		T202	4		T203	4
all_values[2]	275	1		T201	7		T202	4		T203	4
all_values[3]	275	1		T201	7		T202	4		T203	4
all_values[4]	275	1		T201	7		T202	4		T203	4
all_values[5]	275	1		T201	7		T202	4		T203	4
all_values[6]	275	1		T201	7		T202	4		T203	4
all_values[7]	275	1		T201	7		T202	4		T203	4
all_values[8]	275	1		T201	7		T202	4		T203	4
all_values[9]	275	1		T201	7		T202	4		T203	4
all_values[10]	275	1		T201	7		T202	4		T203	4
all_values[11]	275	1		T201	7		T202	4		T203	4
all_values[12]	275	1		T201	7		T202	4		T203	4
all_values[13]	275	1		T201	7		T202	4		T203	4
all_values[14]	275	1		T201	7		T202	4		T203	4
all_values[15]	275	1		T201	7		T202	4		T203	4
all_values[16]	275	1		T201	7		T202	4		T203	4
all_values[17]	275	1		T201	7		T202	4		T203	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2777	1		T201	74		T202	46		T203	34
auto[1]	2173	1		T201	52		T202	26		T203	38

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	895	1		T201	23		T202	24		T203	14
auto[1]	4055	1		T201	103		T202	48		T203	58

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2948	1		T201	75		T202	47		T203	42
auto[1]	2002	1		T201	51		T202	25		T203	30

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	29	1		T284	1		T290	1		T285	4
all_values[0]	auto[0]	auto[0]	auto[1]	70	1		T201	3		T203	1		T204	2
all_values[0]	auto[0]	auto[1]	auto[0]	14	1		T288	2		T292	1		T293	2
all_values[0]	auto[0]	auto[1]	auto[1]	55	1		T201	1		T202	2		T203	1
all_values[0]	auto[1]	auto[0]	auto[1]	65	1		T201	3		T202	2		T203	1
all_values[0]	auto[1]	auto[1]	auto[1]	42	1		T203	1		T284	1		T290	1
all_values[1]	auto[0]	auto[0]	auto[0]	46	1		T201	1		T290	1		T291	5
all_values[1]	auto[0]	auto[0]	auto[1]	38	1		T201	1		T202	2		T203	2
all_values[1]	auto[0]	auto[1]	auto[0]	26	1		T287	2		T294	3		T295	3
all_values[1]	auto[0]	auto[1]	auto[1]	60	1		T201	1		T203	1		T204	4
all_values[1]	auto[1]	auto[0]	auto[1]	52	1		T201	3		T202	1		T204	2
all_values[1]	auto[1]	auto[1]	auto[1]	53	1		T201	1		T202	1		T203	1
all_values[2]	auto[0]	auto[0]	auto[0]	36	1		T201	2		T202	1		T204	2
all_values[2]	auto[0]	auto[0]	auto[1]	54	1		T201	2		T203	1		T204	1
all_values[2]	auto[0]	auto[1]	auto[0]	15	1		T202	1		T292	1		T296	1
all_values[2]	auto[0]	auto[1]	auto[1]	57	1		T202	1		T203	1		T204	2
all_values[2]	auto[1]	auto[0]	auto[1]	54	1		T201	2		T203	1		T204	1
all_values[2]	auto[1]	auto[1]	auto[1]	59	1		T201	1		T202	1		T203	1
all_values[3]	auto[0]	auto[0]	auto[0]	26	1		T291	2		T285	1		T288	2
all_values[3]	auto[0]	auto[0]	auto[1]	74	1		T201	2		T203	1		T204	3
all_values[3]	auto[0]	auto[1]	auto[0]	10	1		T287	2		T289	3		T295	1
all_values[3]	auto[0]	auto[1]	auto[1]	51	1		T201	1		T202	2		T203	1
all_values[3]	auto[1]	auto[0]	auto[1]	71	1		T201	1		T202	1		T204	2
all_values[3]	auto[1]	auto[1]	auto[1]	43	1		T201	3		T202	1		T203	2
all_values[4]	auto[0]	auto[0]	auto[0]	38	1		T201	1		T202	1		T284	1
all_values[4]	auto[0]	auto[0]	auto[1]	68	1		T201	2		T202	1		T203	2
all_values[4]	auto[0]	auto[1]	auto[0]	17	1		T202	1		T287	1		T289	2
all_values[4]	auto[0]	auto[1]	auto[1]	47	1		T201	1		T204	1		T290	1
all_values[4]	auto[1]	auto[0]	auto[1]	60	1		T201	2		T202	1		T203	1
all_values[4]	auto[1]	auto[1]	auto[1]	45	1		T201	1		T203	1		T204	2
all_values[5]	auto[0]	auto[0]	auto[0]	25	1		T201	1		T284	1		T288	2
all_values[5]	auto[0]	auto[0]	auto[1]	70	1		T201	3		T202	2		T203	1
all_values[5]	auto[0]	auto[1]	auto[0]	23	1		T284	1		T297	3		T292	1
all_values[5]	auto[0]	auto[1]	auto[1]	42	1		T204	1		T290	1		T285	1
all_values[5]	auto[1]	auto[0]	auto[1]	73	1		T201	3		T202	2		T203	2
all_values[5]	auto[1]	auto[1]	auto[1]	42	1		T203	1		T204	1		T291	1
all_values[6]	auto[0]	auto[0]	auto[0]	33	1		T201	1		T202	1		T284	3
all_values[6]	auto[0]	auto[0]	auto[1]	54	1		T201	1		T203	1		T291	3
all_values[6]	auto[0]	auto[1]	auto[0]	26	1		T201	1		T203	2		T284	1
all_values[6]	auto[0]	auto[1]	auto[1]	56	1		T201	2		T202	2		T204	3
all_values[6]	auto[1]	auto[0]	auto[1]	54	1		T202	1		T204	2		T291	3
all_values[6]	auto[1]	auto[1]	auto[1]	52	1		T201	2		T203	1		T204	2
all_values[7]	auto[0]	auto[0]	auto[0]	24	1		T204	1		T284	1		T286	1
all_values[7]	auto[0]	auto[0]	auto[1]	57	1		T202	1		T203	1		T284	1
all_values[7]	auto[0]	auto[1]	auto[0]	20	1		T292	1		T298	1		T296	2
all_values[7]	auto[0]	auto[1]	auto[1]	52	1		T201	3		T202	1		T204	2
all_values[7]	auto[1]	auto[0]	auto[1]	66	1		T201	1		T202	2		T284	1
all_values[7]	auto[1]	auto[1]	auto[1]	56	1		T201	3		T203	3		T204	4
all_values[8]	auto[0]	auto[0]	auto[0]	26	1		T201	1		T204	1		T284	1
all_values[8]	auto[0]	auto[0]	auto[1]	57	1		T204	1		T291	2		T285	1
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T201	3		T284	3		T290	1
all_values[8]	auto[0]	auto[1]	auto[1]	57	1		T201	1		T202	2		T203	1
all_values[8]	auto[1]	auto[0]	auto[1]	61	1		T201	2		T202	2		T203	1
all_values[8]	auto[1]	auto[1]	auto[1]	55	1		T203	2		T204	1		T288	2
all_values[9]	auto[0]	auto[0]	auto[0]	26	1		T201	1		T202	3		T285	2
all_values[9]	auto[0]	auto[0]	auto[1]	65	1		T201	3		T203	1		T204	2
all_values[9]	auto[0]	auto[1]	auto[0]	17	1		T202	1		T287	2		T295	1
all_values[9]	auto[0]	auto[1]	auto[1]	53	1		T201	1		T203	1		T204	3
all_values[9]	auto[1]	auto[0]	auto[1]	69	1		T201	1		T204	2		T284	1
all_values[9]	auto[1]	auto[1]	auto[1]	45	1		T201	1		T203	2		T284	1
all_values[10]	auto[0]	auto[0]	auto[0]	34	1		T201	2		T290	2		T285	1
all_values[10]	auto[0]	auto[0]	auto[1]	57	1		T201	1		T202	2		T203	2
all_values[10]	auto[0]	auto[1]	auto[0]	23	1		T285	1		T289	1		T296	1
all_values[10]	auto[0]	auto[1]	auto[1]	51	1		T201	2		T204	2		T290	1
all_values[10]	auto[1]	auto[0]	auto[1]	60	1		T201	1		T202	1		T203	1
all_values[10]	auto[1]	auto[1]	auto[1]	50	1		T201	1		T202	1		T203	1
all_values[11]	auto[0]	auto[0]	auto[0]	43	1		T201	1		T202	4		T204	1
all_values[11]	auto[0]	auto[0]	auto[1]	61	1		T201	3		T203	3		T284	2
all_values[11]	auto[0]	auto[1]	auto[0]	7	1		T289	1		T293	1		T299	1
all_values[11]	auto[0]	auto[1]	auto[1]	55	1		T204	3		T284	1		T291	2
all_values[11]	auto[1]	auto[0]	auto[1]	67	1		T201	2		T203	1		T204	1
all_values[11]	auto[1]	auto[1]	auto[1]	42	1		T201	1		T204	2		T291	4
all_values[12]	auto[0]	auto[0]	auto[0]	33	1		T202	1		T203	4		T204	2
all_values[12]	auto[0]	auto[0]	auto[1]	50	1		T201	2		T284	1		T290	1
all_values[12]	auto[0]	auto[1]	auto[0]	15	1		T284	1		T287	2		T289	2
all_values[12]	auto[0]	auto[1]	auto[1]	67	1		T201	1		T202	1		T204	1
all_values[12]	auto[1]	auto[0]	auto[1]	65	1		T201	4		T204	2		T284	1
all_values[12]	auto[1]	auto[1]	auto[1]	45	1		T202	2		T204	2		T291	3
all_values[13]	auto[0]	auto[0]	auto[0]	38	1		T202	1		T203	1		T284	1
all_values[13]	auto[0]	auto[0]	auto[1]	56	1		T201	2		T202	1		T204	1
all_values[13]	auto[0]	auto[1]	auto[0]	21	1		T284	1		T285	3		T300	1
all_values[13]	auto[0]	auto[1]	auto[1]	54	1		T201	2		T203	1		T204	1
all_values[13]	auto[1]	auto[0]	auto[1]	66	1		T201	1		T202	2		T204	2
all_values[13]	auto[1]	auto[1]	auto[1]	40	1		T201	2		T203	2		T204	3
all_values[14]	auto[0]	auto[0]	auto[0]	25	1		T201	1		T202	2		T204	2
all_values[14]	auto[0]	auto[0]	auto[1]	53	1		T201	1		T203	1		T204	1
all_values[14]	auto[0]	auto[1]	auto[0]	16	1		T202	2		T203	1		T284	2
all_values[14]	auto[0]	auto[1]	auto[1]	73	1		T201	3		T203	1		T291	3
all_values[14]	auto[1]	auto[0]	auto[1]	59	1		T203	1		T204	3		T285	1
all_values[14]	auto[1]	auto[1]	auto[1]	49	1		T201	2		T204	1		T291	3
all_values[15]	auto[0]	auto[0]	auto[0]	30	1		T201	3		T202	1		T290	1
all_values[15]	auto[0]	auto[0]	auto[1]	63	1		T202	1		T203	1		T204	3
all_values[15]	auto[0]	auto[1]	auto[0]	25	1		T201	2		T203	2		T288	2
all_values[15]	auto[0]	auto[1]	auto[1]	51	1		T201	1		T204	1		T285	3
all_values[15]	auto[1]	auto[0]	auto[1]	62	1		T201	1		T202	1		T204	3
all_values[15]	auto[1]	auto[1]	auto[1]	44	1		T202	1		T203	1		T284	1
all_values[16]	auto[0]	auto[0]	auto[0]	38	1		T201	1		T202	3		T203	2
all_values[16]	auto[0]	auto[0]	auto[1]	65	1		T201	1		T204	1		T291	3
all_values[16]	auto[0]	auto[1]	auto[0]	16	1		T202	1		T203	2		T297	1
all_values[16]	auto[0]	auto[1]	auto[1]	43	1		T201	2		T204	2		T284	1
all_values[16]	auto[1]	auto[0]	auto[1]	57	1		T204	1		T290	1		T291	2
all_values[16]	auto[1]	auto[1]	auto[1]	56	1		T201	3		T204	2		T284	2
all_values[17]	auto[0]	auto[0]	auto[0]	25	1		T201	1		T284	1		T288	2
all_values[17]	auto[0]	auto[0]	auto[1]	61	1		T201	1		T202	1		T291	3
all_values[17]	auto[0]	auto[1]	auto[0]	10	1		T284	1		T301	1		T293	1
all_values[17]	auto[0]	auto[1]	auto[1]	56	1		T201	2		T202	1		T203	2
all_values[17]	auto[1]	auto[0]	auto[1]	68	1		T201	2		T202	1		T204	2
all_values[17]	auto[1]	auto[1]	auto[1]	55	1		T201	1		T202	1		T203	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal