Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
93.58 97.84 93.79 97.44 75.00 96.26 98.17 96.58


Total test records in report: 2852
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T2765 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2264341168 Jul 22 06:21:09 PM PDT 24 Jul 22 06:21:11 PM PDT 24 52678815 ps
T266 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3951491091 Jul 22 06:20:51 PM PDT 24 Jul 22 06:20:54 PM PDT 24 86620907 ps
T2766 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.999671996 Jul 22 06:21:00 PM PDT 24 Jul 22 06:21:04 PM PDT 24 389692593 ps
T2767 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3463244372 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:20 PM PDT 24 124201371 ps
T267 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3945741718 Jul 22 06:21:11 PM PDT 24 Jul 22 06:21:13 PM PDT 24 142132375 ps
T2768 /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2319803627 Jul 22 06:20:53 PM PDT 24 Jul 22 06:20:54 PM PDT 24 158358307 ps
T294 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2126048627 Jul 22 06:23:59 PM PDT 24 Jul 22 06:24:00 PM PDT 24 48130365 ps
T295 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3353521327 Jul 22 06:23:18 PM PDT 24 Jul 22 06:23:19 PM PDT 24 42490206 ps
T2769 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.686195705 Jul 22 06:20:58 PM PDT 24 Jul 22 06:21:01 PM PDT 24 259477646 ps
T2770 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4248463698 Jul 22 06:21:19 PM PDT 24 Jul 22 06:21:30 PM PDT 24 822938052 ps
T2771 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1815021100 Jul 22 06:23:17 PM PDT 24 Jul 22 06:23:18 PM PDT 24 36063468 ps
T2772 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3216855584 Jul 22 06:20:58 PM PDT 24 Jul 22 06:21:00 PM PDT 24 118821258 ps
T2773 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1721404379 Jul 22 06:23:18 PM PDT 24 Jul 22 06:23:20 PM PDT 24 125229449 ps
T2774 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3937347848 Jul 22 06:20:59 PM PDT 24 Jul 22 06:21:01 PM PDT 24 155319190 ps
T300 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3019721566 Jul 22 06:21:17 PM PDT 24 Jul 22 06:21:21 PM PDT 24 64726561 ps
T301 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2046959141 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:17 PM PDT 24 42333418 ps
T2775 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.603276608 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:21 PM PDT 24 94188039 ps
T2776 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2410036038 Jul 22 06:21:14 PM PDT 24 Jul 22 06:21:16 PM PDT 24 222486206 ps
T2777 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4179076149 Jul 22 06:21:12 PM PDT 24 Jul 22 06:21:14 PM PDT 24 63781108 ps
T2778 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.973164135 Jul 22 06:21:13 PM PDT 24 Jul 22 06:21:16 PM PDT 24 557242864 ps
T293 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2275256585 Jul 22 06:21:26 PM PDT 24 Jul 22 06:21:28 PM PDT 24 42009927 ps
T2779 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3361472304 Jul 22 06:21:12 PM PDT 24 Jul 22 06:21:16 PM PDT 24 128687878 ps
T2780 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1105603380 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:21 PM PDT 24 173071379 ps
T232 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1846513063 Jul 22 06:21:20 PM PDT 24 Jul 22 06:21:26 PM PDT 24 152381883 ps
T2781 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1441398652 Jul 22 06:21:26 PM PDT 24 Jul 22 06:21:29 PM PDT 24 222182591 ps
T2782 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3804772339 Jul 22 06:21:02 PM PDT 24 Jul 22 06:21:03 PM PDT 24 44897550 ps
T2783 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3280288801 Jul 22 06:21:11 PM PDT 24 Jul 22 06:21:14 PM PDT 24 195715972 ps
T2784 /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3359503130 Jul 22 06:21:21 PM PDT 24 Jul 22 06:21:25 PM PDT 24 64993117 ps
T2785 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1298904535 Jul 22 06:21:10 PM PDT 24 Jul 22 06:21:14 PM PDT 24 810490387 ps
T2786 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.565502246 Jul 22 06:22:22 PM PDT 24 Jul 22 06:22:25 PM PDT 24 45094441 ps
T2787 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2756578237 Jul 22 06:22:34 PM PDT 24 Jul 22 06:22:38 PM PDT 24 165033446 ps
T2788 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4183416083 Jul 22 06:22:34 PM PDT 24 Jul 22 06:22:37 PM PDT 24 291549592 ps
T2789 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1265528908 Jul 22 06:21:13 PM PDT 24 Jul 22 06:21:15 PM PDT 24 74394770 ps
T2790 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1866990189 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:16 PM PDT 24 35595170 ps
T2791 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.128442426 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:17 PM PDT 24 129708809 ps
T235 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.772277511 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:21 PM PDT 24 99074545 ps
T2792 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.941613704 Jul 22 06:23:59 PM PDT 24 Jul 22 06:24:00 PM PDT 24 127123432 ps
T2793 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1292837200 Jul 22 06:24:13 PM PDT 24 Jul 22 06:24:17 PM PDT 24 275729666 ps
T2794 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1703468832 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:59 PM PDT 24 79546362 ps
T2795 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.945745739 Jul 22 06:20:51 PM PDT 24 Jul 22 06:20:52 PM PDT 24 182346909 ps
T2796 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2331959597 Jul 22 06:21:09 PM PDT 24 Jul 22 06:21:11 PM PDT 24 59131252 ps
T299 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3023357611 Jul 22 06:21:08 PM PDT 24 Jul 22 06:21:10 PM PDT 24 57325236 ps
T2797 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1985359160 Jul 22 06:24:13 PM PDT 24 Jul 22 06:24:14 PM PDT 24 40838448 ps
T2798 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1083735807 Jul 22 06:21:18 PM PDT 24 Jul 22 06:21:22 PM PDT 24 83090631 ps
T2799 /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.89533075 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:20 PM PDT 24 266037058 ps
T2800 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3942310146 Jul 22 06:21:24 PM PDT 24 Jul 22 06:21:31 PM PDT 24 905534065 ps
T2801 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2538903039 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:20 PM PDT 24 62294532 ps
T302 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1477997832 Jul 22 06:21:10 PM PDT 24 Jul 22 06:21:16 PM PDT 24 738744320 ps
T2802 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.859718838 Jul 22 06:21:18 PM PDT 24 Jul 22 06:21:24 PM PDT 24 160461076 ps
T2803 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2661574085 Jul 22 06:21:13 PM PDT 24 Jul 22 06:21:16 PM PDT 24 164000208 ps
T2804 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2284207088 Jul 22 06:21:17 PM PDT 24 Jul 22 06:21:21 PM PDT 24 63840338 ps
T2805 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1226416277 Jul 22 06:21:08 PM PDT 24 Jul 22 06:21:11 PM PDT 24 169459802 ps
T2806 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1322277030 Jul 22 06:21:04 PM PDT 24 Jul 22 06:21:06 PM PDT 24 79119836 ps
T303 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2582473092 Jul 22 06:21:14 PM PDT 24 Jul 22 06:21:20 PM PDT 24 1032408122 ps
T2807 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3137108616 Jul 22 06:21:18 PM PDT 24 Jul 22 06:21:23 PM PDT 24 40315334 ps
T2808 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.286872461 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:20 PM PDT 24 166395541 ps
T2809 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2184000761 Jul 22 06:21:19 PM PDT 24 Jul 22 06:21:23 PM PDT 24 36379115 ps
T2810 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3434193524 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:18 PM PDT 24 48912114 ps
T2811 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1668333038 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:19 PM PDT 24 58449553 ps
T2812 /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1584999245 Jul 22 06:21:09 PM PDT 24 Jul 22 06:21:14 PM PDT 24 479917532 ps
T2813 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2306350609 Jul 22 06:24:13 PM PDT 24 Jul 22 06:24:14 PM PDT 24 35024569 ps
T2814 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1762085176 Jul 22 06:21:26 PM PDT 24 Jul 22 06:21:28 PM PDT 24 30479822 ps
T2815 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2223778819 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:19 PM PDT 24 96956316 ps
T2816 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2152886036 Jul 22 06:21:13 PM PDT 24 Jul 22 06:21:15 PM PDT 24 116858020 ps
T2817 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1377475721 Jul 22 06:23:18 PM PDT 24 Jul 22 06:23:20 PM PDT 24 167131927 ps
T2818 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2149835526 Jul 22 06:21:20 PM PDT 24 Jul 22 06:21:26 PM PDT 24 361930150 ps
T2819 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.413400769 Jul 22 06:22:55 PM PDT 24 Jul 22 06:22:56 PM PDT 24 59020412 ps
T2820 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4024772042 Jul 22 06:21:12 PM PDT 24 Jul 22 06:21:18 PM PDT 24 992541564 ps
T2821 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.504715513 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:20 PM PDT 24 39720927 ps
T2822 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.36799161 Jul 22 06:21:54 PM PDT 24 Jul 22 06:21:55 PM PDT 24 47046039 ps
T2823 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1558597682 Jul 22 06:22:05 PM PDT 24 Jul 22 06:22:06 PM PDT 24 82713707 ps
T2824 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3491984117 Jul 22 06:21:15 PM PDT 24 Jul 22 06:21:17 PM PDT 24 88415098 ps
T2825 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1774241962 Jul 22 06:21:12 PM PDT 24 Jul 22 06:21:14 PM PDT 24 38787218 ps
T2826 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4139619060 Jul 22 06:22:22 PM PDT 24 Jul 22 06:22:27 PM PDT 24 105923642 ps
T2827 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.999645762 Jul 22 06:21:13 PM PDT 24 Jul 22 06:21:15 PM PDT 24 111961722 ps
T2828 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2272774769 Jul 22 06:21:11 PM PDT 24 Jul 22 06:21:15 PM PDT 24 216270554 ps
T2829 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2779639068 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:22 PM PDT 24 200115610 ps
T2830 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2159459171 Jul 22 06:21:10 PM PDT 24 Jul 22 06:21:11 PM PDT 24 48001556 ps
T2831 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.202995310 Jul 22 06:21:24 PM PDT 24 Jul 22 06:21:27 PM PDT 24 71330495 ps
T2832 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1338151852 Jul 22 06:21:12 PM PDT 24 Jul 22 06:21:16 PM PDT 24 98015843 ps
T304 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3245982769 Jul 22 06:21:26 PM PDT 24 Jul 22 06:21:30 PM PDT 24 658806705 ps
T2833 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4002932170 Jul 22 06:21:11 PM PDT 24 Jul 22 06:21:13 PM PDT 24 61660387 ps
T2834 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.206625483 Jul 22 06:20:48 PM PDT 24 Jul 22 06:20:49 PM PDT 24 82805745 ps
T2835 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2143653919 Jul 22 06:23:58 PM PDT 24 Jul 22 06:23:59 PM PDT 24 60001357 ps
T2836 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2307027285 Jul 22 06:21:05 PM PDT 24 Jul 22 06:21:07 PM PDT 24 58173330 ps
T2837 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3346717588 Jul 22 06:21:08 PM PDT 24 Jul 22 06:21:17 PM PDT 24 1260164965 ps
T2838 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.918767493 Jul 22 06:21:04 PM PDT 24 Jul 22 06:21:07 PM PDT 24 66885642 ps
T2839 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2589916484 Jul 22 06:23:58 PM PDT 24 Jul 22 06:23:59 PM PDT 24 38952773 ps
T2840 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1031339944 Jul 22 06:21:17 PM PDT 24 Jul 22 06:21:21 PM PDT 24 107946895 ps
T2841 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1428247885 Jul 22 06:21:06 PM PDT 24 Jul 22 06:21:08 PM PDT 24 101365574 ps
T2842 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2960554013 Jul 22 06:21:16 PM PDT 24 Jul 22 06:21:20 PM PDT 24 158467362 ps
T2843 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.533898598 Jul 22 06:21:08 PM PDT 24 Jul 22 06:21:10 PM PDT 24 120007105 ps
T2844 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1509008253 Jul 22 06:21:20 PM PDT 24 Jul 22 06:21:25 PM PDT 24 90437486 ps
T2845 /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1762745282 Jul 22 06:22:56 PM PDT 24 Jul 22 06:22:59 PM PDT 24 59000925 ps
T2846 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.400038107 Jul 22 06:21:41 PM PDT 24 Jul 22 06:21:42 PM PDT 24 41711498 ps
T2847 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3838370989 Jul 22 06:23:00 PM PDT 24 Jul 22 06:23:04 PM PDT 24 152222189 ps
T2848 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3573616233 Jul 22 06:21:21 PM PDT 24 Jul 22 06:21:25 PM PDT 24 42498936 ps
T2849 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3332069201 Jul 22 06:21:04 PM PDT 24 Jul 22 06:21:07 PM PDT 24 87108130 ps
T2850 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4019974574 Jul 22 06:21:17 PM PDT 24 Jul 22 06:21:21 PM PDT 24 49986442 ps
T2851 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1392093808 Jul 22 06:24:13 PM PDT 24 Jul 22 06:24:15 PM PDT 24 90608999 ps
T307 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.196750464 Jul 22 06:21:11 PM PDT 24 Jul 22 06:21:14 PM PDT 24 348358810 ps
T2852 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2667040215 Jul 22 06:20:55 PM PDT 24 Jul 22 06:20:58 PM PDT 24 92887848 ps

Test location /workspace/coverage/default/46.usbdev_data_toggle_restore.1300091381
Short name T3
Test name
Test status
Simulation time 416366623 ps
CPU time 1.2 seconds
Started Jul 22 06:03:19 PM PDT 24
Finished Jul 22 06:03:21 PM PDT 24
Peak memory 206912 kb
Host smart-f5ad0665-3a07-4853-8b8f-93264c71ba4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13000
91381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_restore.1300091381
Directory /workspace/46.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_reset.3188610627
Short name T7
Test name
Test status
Simulation time 13472579955 ps
CPU time 14.26 seconds
Started Jul 22 05:58:24 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206864 kb
Host smart-77a922b3-cc86-45e0-b2f2-b74cc93f9e64
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3188610627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_reset.3188610627
Directory /workspace/13.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.1890808885
Short name T201
Test name
Test status
Simulation time 109712330 ps
CPU time 0.75 seconds
Started Jul 22 06:21:09 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 206544 kb
Host smart-fe52edb8-4536-4fff-a235-4df0b700321a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1890808885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.1890808885
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/default/21.usbdev_device_address.3833784543
Short name T22
Test name
Test status
Simulation time 21608017844 ps
CPU time 40.32 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 06:00:14 PM PDT 24
Peak memory 206944 kb
Host smart-ade29c4f-4504-4c53-8d45-db0a9fd9bcce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38337
84543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_device_address.3833784543
Directory /workspace/21.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_iso_retraction.1081325894
Short name T93
Test name
Test status
Simulation time 5516551637 ps
CPU time 21.16 seconds
Started Jul 22 06:03:20 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206860 kb
Host smart-5b57ec99-bd91-4e32-bfbd-b94fe1bc0828
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10813
25894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_iso_retraction.1081325894
Directory /workspace/45.usbdev_iso_retraction/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.544512494
Short name T192
Test name
Test status
Simulation time 1176006422 ps
CPU time 4.78 seconds
Started Jul 22 06:21:05 PM PDT 24
Finished Jul 22 06:21:10 PM PDT 24
Peak memory 206792 kb
Host smart-bbd21df9-febe-43a8-8729-c68d71abb88b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=544512494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.544512494
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_stall_priority_over_nak.1315154777
Short name T28
Test name
Test status
Simulation time 146062881 ps
CPU time 0.8 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206908 kb
Host smart-6c0ca15c-2905-4798-9460-509e3c2441e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13151
54777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_priority_over_nak.1315154777
Directory /workspace/11.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_out_iso.1595117524
Short name T97
Test name
Test status
Simulation time 146646981 ps
CPU time 0.78 seconds
Started Jul 22 06:03:25 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206624 kb
Host smart-5b81a6a3-adc2-49be-a0d1-27931a9fe1dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15951
17524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_iso.1595117524
Directory /workspace/45.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_disconnected.232135420
Short name T50
Test name
Test status
Simulation time 176496800 ps
CPU time 0.81 seconds
Started Jul 22 05:59:53 PM PDT 24
Finished Jul 22 05:59:55 PM PDT 24
Peak memory 206712 kb
Host smart-bef04f4f-cd3f-424a-8117-98874b691012
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23213
5420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disconnected.232135420
Directory /workspace/21.usbdev_disconnected/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.214267308
Short name T289
Test name
Test status
Simulation time 65354573 ps
CPU time 0.73 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206592 kb
Host smart-b4bcd27c-92a3-4819-a870-abc7d076ef78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=214267308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.214267308
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.1830422191
Short name T226
Test name
Test status
Simulation time 215851014 ps
CPU time 2.65 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:15 PM PDT 24
Peak memory 222428 kb
Host smart-cf149af6-d687-4f7d-877c-f09e38aed04e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1830422191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.1830422191
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/default/19.usbdev_low_speed_traffic.3650002382
Short name T143
Test name
Test status
Simulation time 6828689014 ps
CPU time 52.52 seconds
Started Jul 22 05:59:18 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206948 kb
Host smart-b8740019-5fa9-4954-b583-d7ed78c3ed90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36500
02382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_low_speed_traffic.3650002382
Directory /workspace/19.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_sec_cm.2568377639
Short name T190
Test name
Test status
Simulation time 530595801 ps
CPU time 1.37 seconds
Started Jul 22 05:56:22 PM PDT 24
Finished Jul 22 05:56:24 PM PDT 24
Peak memory 225484 kb
Host smart-8d5f3b93-ccac-4d0a-8824-5e653699ccb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2568377639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_sec_cm.2568377639
Directory /workspace/0.usbdev_sec_cm/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_reset.4189470899
Short name T55
Test name
Test status
Simulation time 13413513161 ps
CPU time 12.9 seconds
Started Jul 22 06:03:21 PM PDT 24
Finished Jul 22 06:03:35 PM PDT 24
Peak memory 206728 kb
Host smart-21da282e-9a3a-46f8-a572-ebca63566684
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4189470899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_reset.4189470899
Directory /workspace/45.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_phy_pins_sense.3162740495
Short name T25
Test name
Test status
Simulation time 38785832 ps
CPU time 0.67 seconds
Started Jul 22 06:02:58 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206700 kb
Host smart-b9b59a11-8c0f-4a89-8c1e-56fde94c1ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31627
40495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_pins_sense.3162740495
Directory /workspace/43.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_rx_crc_err.2302036498
Short name T78
Test name
Test status
Simulation time 192307561 ps
CPU time 0.86 seconds
Started Jul 22 06:02:08 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206736 kb
Host smart-e5e7b0a8-5791-4863-b551-e58b9941e1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23020
36498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_rx_crc_err.2302036498
Directory /workspace/21.usbdev_rx_crc_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3334273505
Short name T286
Test name
Test status
Simulation time 68906539 ps
CPU time 0.72 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 206724 kb
Host smart-6d32f156-efca-4d12-befa-57185b51baba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3334273505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3334273505
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_osc_test_mode.375667061
Short name T83
Test name
Test status
Simulation time 304691304 ps
CPU time 1 seconds
Started Jul 22 05:56:07 PM PDT 24
Finished Jul 22 05:56:08 PM PDT 24
Peak memory 206652 kb
Host smart-f275178d-89ae-47df-80fe-4281863721c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37566
7061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_tx_osc_test_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_osc_test_mode.375667061
Directory /workspace/0.usbdev_phy_config_tx_osc_test_mode/latest

Test location /workspace/coverage/default/3.usbdev_stress_usb_traffic.1607346319
Short name T48
Test name
Test status
Simulation time 5498111860 ps
CPU time 45.43 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206924 kb
Host smart-a11f2ad3-32c2-413e-8cc1-36a03cf65011
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1607346319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stress_usb_traffic.1607346319
Directory /workspace/3.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_resume_link_active.717858960
Short name T54
Test name
Test status
Simulation time 20163793848 ps
CPU time 19.75 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 05:56:40 PM PDT 24
Peak memory 206764 kb
Host smart-2974d8d5-b103-433e-9630-73ab710edfd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71785
8960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_resume_link_active_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_resume_link_active.717858960
Directory /workspace/0.usbdev_resume_link_active/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_clear.2972093278
Short name T719
Test name
Test status
Simulation time 342482283 ps
CPU time 1.19 seconds
Started Jul 22 05:58:15 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206756 kb
Host smart-5f6220aa-5140-4753-99ae-b39c1015ff53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29720
93278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_clear.2972093278
Directory /workspace/12.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3581952773
Short name T258
Test name
Test status
Simulation time 96929009 ps
CPU time 0.98 seconds
Started Jul 22 06:20:53 PM PDT 24
Finished Jul 22 06:20:55 PM PDT 24
Peak memory 206708 kb
Host smart-84708064-51a3-4ac2-86e3-23b2ab287018
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3581952773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3581952773
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1677532787
Short name T292
Test name
Test status
Simulation time 72987141 ps
CPU time 0.74 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:23 PM PDT 24
Peak memory 206536 kb
Host smart-9371e7d0-28da-4c66-bd84-c2f825616631
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1677532787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1677532787
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/default/6.usbdev_pkt_received.2359754983
Short name T21
Test name
Test status
Simulation time 208648895 ps
CPU time 0.83 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206752 kb
Host smart-ee8542e9-7e8c-4542-9c43-1584c9af2f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23597
54983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_received.2359754983
Directory /workspace/6.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_invalid_sync.3419857831
Short name T5
Test name
Test status
Simulation time 8288312774 ps
CPU time 234.46 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 06:00:49 PM PDT 24
Peak memory 206876 kb
Host smart-d62243b4-6568-4069-9c65-cf5a0ad43f0c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3419857831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_invalid_sync.3419857831
Directory /workspace/3.usbdev_invalid_sync/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2582473092
Short name T303
Test name
Test status
Simulation time 1032408122 ps
CPU time 5.37 seconds
Started Jul 22 06:21:14 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 206828 kb
Host smart-15601528-050a-45bb-9bde-280974a45510
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2582473092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2582473092
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.504715513
Short name T2821
Test name
Test status
Simulation time 39720927 ps
CPU time 0.7 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 206500 kb
Host smart-6fb57484-fcbc-424f-aada-79d5578d7b1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=504715513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.504715513
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1726485535
Short name T202
Test name
Test status
Simulation time 42171482 ps
CPU time 0.64 seconds
Started Jul 22 06:21:14 PM PDT 24
Finished Jul 22 06:21:15 PM PDT 24
Peak memory 206556 kb
Host smart-0232a669-4ccd-4713-aecc-7377e22f4927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1726485535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1726485535
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/default/27.usbdev_pkt_buffer.1433590562
Short name T92
Test name
Test status
Simulation time 8927553414 ps
CPU time 19.55 seconds
Started Jul 22 06:00:40 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 206932 kb
Host smart-781ddc2d-3c8c-4c9f-93f0-87699b44f042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14335
90562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_buffer.1433590562
Directory /workspace/27.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_bitstuff_err.3617317910
Short name T331
Test name
Test status
Simulation time 147532387 ps
CPU time 0.75 seconds
Started Jul 22 05:57:50 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206764 kb
Host smart-2a391902-077a-417b-a476-34f5ff758307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36173
17910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_bitstuff_err.3617317910
Directory /workspace/10.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_invalid_data1_data0_toggle_test.565101550
Short name T75
Test name
Test status
Simulation time 429314097 ps
CPU time 1.16 seconds
Started Jul 22 05:56:10 PM PDT 24
Finished Jul 22 05:56:11 PM PDT 24
Peak memory 206732 kb
Host smart-fbb54460-4989-4841-aab0-0dfd5e8a634f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56510
1550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_invalid_data1_data0_toggle_test.565101550
Directory /workspace/0.usbdev_invalid_data1_data0_toggle_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1846513063
Short name T232
Test name
Test status
Simulation time 152381883 ps
CPU time 2.82 seconds
Started Jul 22 06:21:20 PM PDT 24
Finished Jul 22 06:21:26 PM PDT 24
Peak memory 222496 kb
Host smart-0f72fdcb-af70-4c22-84e5-d925a526877e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1846513063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1846513063
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_disconnect.3109076380
Short name T185
Test name
Test status
Simulation time 4369527635 ps
CPU time 5 seconds
Started Jul 22 05:59:23 PM PDT 24
Finished Jul 22 05:59:29 PM PDT 24
Peak memory 206816 kb
Host smart-3210a40f-9966-441f-a799-31473e994464
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3109076380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_disconnect.3109076380
Directory /workspace/19.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.490965419
Short name T242
Test name
Test status
Simulation time 396440361 ps
CPU time 2.66 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:23 PM PDT 24
Peak memory 206824 kb
Host smart-4bbce337-1eea-4c4d-8d35-c0dca9be4363
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=490965419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.490965419
Directory /workspace/9.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/11.usbdev_alert_test.325093740
Short name T182
Test name
Test status
Simulation time 41117691 ps
CPU time 0.68 seconds
Started Jul 22 05:58:18 PM PDT 24
Finished Jul 22 05:58:19 PM PDT 24
Peak memory 206736 kb
Host smart-8567cebe-1cff-4c8d-bfff-07fb032e063d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=325093740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_alert_test.325093740
Directory /workspace/11.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_resets.283251505
Short name T155
Test name
Test status
Simulation time 12286809658 ps
CPU time 79.26 seconds
Started Jul 22 05:57:27 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206952 kb
Host smart-617526c2-21ff-4b8a-9216-53ea6da28cc2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=283251505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_resets.283251505
Directory /workspace/7.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_restore.4272285751
Short name T103
Test name
Test status
Simulation time 655280645 ps
CPU time 1.68 seconds
Started Jul 22 05:59:06 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206752 kb
Host smart-36cbe487-51c4-4777-afb7-2d9e53e7748a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42722
85751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_restore.4272285751
Directory /workspace/17.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_rx_full.1428981227
Short name T31
Test name
Test status
Simulation time 246503910 ps
CPU time 0.97 seconds
Started Jul 22 05:56:22 PM PDT 24
Finished Jul 22 05:56:24 PM PDT 24
Peak memory 206704 kb
Host smart-c2db9231-9239-45c2-b6ee-ca1078895c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14289
81227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_full_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_full.1428981227
Directory /workspace/0.usbdev_rx_full/latest

Test location /workspace/coverage/default/0.usbdev_av_overflow.1357241742
Short name T87
Test name
Test status
Simulation time 166130081 ps
CPU time 0.84 seconds
Started Jul 22 05:55:59 PM PDT 24
Finished Jul 22 05:56:00 PM PDT 24
Peak memory 206724 kb
Host smart-754ae515-0cc5-4e52-8a6c-32942416ee5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13572
41742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_overflow.1357241742
Directory /workspace/0.usbdev_av_overflow/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.3234698248
Short name T224
Test name
Test status
Simulation time 461729025 ps
CPU time 2.58 seconds
Started Jul 22 06:23:18 PM PDT 24
Finished Jul 22 06:23:21 PM PDT 24
Peak memory 206864 kb
Host smart-7640f2ff-0d25-4e01-8d52-afa2d98e33d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3234698248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.3234698248
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/default/13.usbdev_invalid_sync.2990661628
Short name T46
Test name
Test status
Simulation time 6131167101 ps
CPU time 57.86 seconds
Started Jul 22 05:58:24 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206900 kb
Host smart-557f3eef-847a-4b03-be1a-c2c289bbf8ca
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2990661628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_invalid_sync.2990661628
Directory /workspace/13.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_disconnects.3605095597
Short name T158
Test name
Test status
Simulation time 9833322739 ps
CPU time 240.48 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 06:00:52 PM PDT 24
Peak memory 206900 kb
Host smart-cf961491-2782-4b09-bb68-c333adb57806
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3605095597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_disconnects.3605095597
Directory /workspace/3.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_suspends.4138147227
Short name T464
Test name
Test status
Simulation time 18479558473 ps
CPU time 97.35 seconds
Started Jul 22 05:57:47 PM PDT 24
Finished Jul 22 05:59:26 PM PDT 24
Peak memory 206892 kb
Host smart-c2169036-9a03-41d5-a1bf-a5ce9ad3e40a
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4138147227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_suspends.4138147227
Directory /workspace/9.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/45.usbdev_max_usb_traffic.567047082
Short name T150
Test name
Test status
Simulation time 6012072758 ps
CPU time 152.96 seconds
Started Jul 22 06:03:09 PM PDT 24
Finished Jul 22 06:05:44 PM PDT 24
Peak memory 206672 kb
Host smart-f62cb39d-2e36-4cdb-9bee-aa7fff8bfe22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56704
7082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_usb_traffic.567047082
Directory /workspace/45.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_usb_ref_disable.1978902752
Short name T44
Test name
Test status
Simulation time 143853935 ps
CPU time 0.78 seconds
Started Jul 22 05:56:36 PM PDT 24
Finished Jul 22 05:56:37 PM PDT 24
Peak memory 206704 kb
Host smart-5a149d10-ae18-4621-953d-6fa0c7b39b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19789
02752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_usb_ref_disable.1978902752
Directory /workspace/1.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_nak_trans.2387375320
Short name T133
Test name
Test status
Simulation time 212066017 ps
CPU time 0.92 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:27 PM PDT 24
Peak memory 206732 kb
Host smart-44028e4d-6d0f-488a-9107-b3dbcfd4cc57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23873
75320 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_nak_trans.2387375320
Directory /workspace/17.usbdev_nak_trans/latest

Test location /workspace/coverage/default/1.usbdev_av_overflow.568845622
Short name T71
Test name
Test status
Simulation time 140973901 ps
CPU time 0.79 seconds
Started Jul 22 05:56:21 PM PDT 24
Finished Jul 22 05:56:22 PM PDT 24
Peak memory 206728 kb
Host smart-a6a9bd9b-feed-4b95-b95c-6faf5ce4048c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56884
5622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_overflow.568845622
Directory /workspace/1.usbdev_av_overflow/latest

Test location /workspace/coverage/default/1.usbdev_fifo_rst.919223087
Short name T581
Test name
Test status
Simulation time 202609286 ps
CPU time 1.25 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 05:56:21 PM PDT 24
Peak memory 206876 kb
Host smart-01c8f6d3-83c5-40ba-9119-d9407a1bf71e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91922
3087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_fifo_rst.919223087
Directory /workspace/1.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_av_empty.3574517956
Short name T59
Test name
Test status
Simulation time 211665679 ps
CPU time 0.86 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:10 PM PDT 24
Peak memory 206724 kb
Host smart-8da8e4cc-af50-47fe-bf51-cff8b553f38a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35745
17956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_empty.3574517956
Directory /workspace/0.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_host_lost.3670491314
Short name T72
Test name
Test status
Simulation time 4166362809 ps
CPU time 9.11 seconds
Started Jul 22 05:56:11 PM PDT 24
Finished Jul 22 05:56:21 PM PDT 24
Peak memory 206920 kb
Host smart-1e46f3a9-896c-49b5-8b18-c28d9b74f18a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36704
91314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_host_lost_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_host_lost.3670491314
Directory /workspace/0.usbdev_host_lost/latest

Test location /workspace/coverage/default/0.usbdev_link_reset.1044897491
Short name T73
Test name
Test status
Simulation time 177979975 ps
CPU time 0.78 seconds
Started Jul 22 05:56:07 PM PDT 24
Finished Jul 22 05:56:08 PM PDT 24
Peak memory 206732 kb
Host smart-34e4fca0-d8e2-457f-a937-450358f94524
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10448
97491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_reset.1044897491
Directory /workspace/0.usbdev_link_reset/latest

Test location /workspace/coverage/default/0.usbdev_rx_pid_err.3755125973
Short name T2147
Test name
Test status
Simulation time 216366636 ps
CPU time 0.83 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 05:56:20 PM PDT 24
Peak memory 206732 kb
Host smart-32f82742-3887-4778-bec6-58515838c536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551
25973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_pid_err.3755125973
Directory /workspace/0.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_stress_usb_traffic.1621034143
Short name T159
Test name
Test status
Simulation time 29222852472 ps
CPU time 183.59 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 207020 kb
Host smart-c61f1cb4-ae7f-4e7f-af29-90b2a27d00b8
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1621034143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stress_usb_traffic.1621034143
Directory /workspace/1.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_phy_pins_sense.275464011
Short name T26
Test name
Test status
Simulation time 32150720 ps
CPU time 0.62 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206732 kb
Host smart-6411d5d1-9f51-4228-9b6d-0b3787d7c19e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27546
4011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_pins_sense.275464011
Directory /workspace/14.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_av_empty.1192522457
Short name T66
Test name
Test status
Simulation time 175353576 ps
CPU time 0.83 seconds
Started Jul 22 05:56:34 PM PDT 24
Finished Jul 22 05:56:35 PM PDT 24
Peak memory 206788 kb
Host smart-1155b664-58d7-4fe2-b13f-40b910ab086d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11925
22457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_empty.1192522457
Directory /workspace/3.usbdev_av_empty/latest

Test location /workspace/coverage/default/0.usbdev_nak_trans.3275250209
Short name T140
Test name
Test status
Simulation time 238580913 ps
CPU time 0.91 seconds
Started Jul 22 05:56:12 PM PDT 24
Finished Jul 22 05:56:13 PM PDT 24
Peak memory 206752 kb
Host smart-02c1ca9f-adea-48b4-80cb-94b27d30e882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32752
50209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_trans.3275250209
Directory /workspace/0.usbdev_nak_trans/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority.4016340801
Short name T64
Test name
Test status
Simulation time 395301970 ps
CPU time 1.29 seconds
Started Jul 22 05:56:22 PM PDT 24
Finished Jul 22 05:56:24 PM PDT 24
Peak memory 206680 kb
Host smart-34fc2b9d-0615-4e10-8ac1-351c670336db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40163
40801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority.4016340801
Directory /workspace/0.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_min_inter_pkt_delay.1751156490
Short name T310
Test name
Test status
Simulation time 5178797637 ps
CPU time 146.86 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:59:05 PM PDT 24
Peak memory 206900 kb
Host smart-01f26fe3-472a-484a-98d0-d347c35f355d
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1751156490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_inter_pkt_delay.1751156490
Directory /workspace/1.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_nak_trans.4294084587
Short name T121
Test name
Test status
Simulation time 166576591 ps
CPU time 0.81 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:43 PM PDT 24
Peak memory 206776 kb
Host smart-b2b58e5a-01f5-409c-95be-1111c113799f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42940
84587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_nak_trans.4294084587
Directory /workspace/1.usbdev_nak_trans/latest

Test location /workspace/coverage/default/10.usbdev_nak_trans.2970468884
Short name T1521
Test name
Test status
Simulation time 183161273 ps
CPU time 0.81 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:57 PM PDT 24
Peak memory 206628 kb
Host smart-a7135282-b407-4ed5-89ee-c05b5964b601
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29704
68884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_nak_trans.2970468884
Directory /workspace/10.usbdev_nak_trans/latest

Test location /workspace/coverage/default/11.usbdev_nak_trans.2698142898
Short name T117
Test name
Test status
Simulation time 185471936 ps
CPU time 0.81 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:06 PM PDT 24
Peak memory 206712 kb
Host smart-d3cd8b9b-b038-497a-8521-5ed3d19cf678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26981
42898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_nak_trans.2698142898
Directory /workspace/11.usbdev_nak_trans/latest

Test location /workspace/coverage/default/12.usbdev_nak_trans.1844932368
Short name T2507
Test name
Test status
Simulation time 207782674 ps
CPU time 0.89 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206736 kb
Host smart-6297bc3b-fcd4-475a-9d2e-6d046a483b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18449
32368 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_nak_trans.1844932368
Directory /workspace/12.usbdev_nak_trans/latest

Test location /workspace/coverage/default/16.usbdev_nak_trans.2519161191
Short name T112
Test name
Test status
Simulation time 228509272 ps
CPU time 0.89 seconds
Started Jul 22 05:58:58 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206744 kb
Host smart-68672d6e-61f8-42e1-a027-359742986500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25191
61191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_nak_trans.2519161191
Directory /workspace/16.usbdev_nak_trans/latest

Test location /workspace/coverage/default/2.usbdev_nak_trans.3803179485
Short name T126
Test name
Test status
Simulation time 233011231 ps
CPU time 0.91 seconds
Started Jul 22 05:56:36 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206912 kb
Host smart-dc8b696a-2791-47c0-b44a-867c4e86538c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38031
79485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_nak_trans.3803179485
Directory /workspace/2.usbdev_nak_trans/latest

Test location /workspace/coverage/default/20.usbdev_nak_trans.2253681899
Short name T129
Test name
Test status
Simulation time 228009417 ps
CPU time 0.97 seconds
Started Jul 22 05:59:34 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206668 kb
Host smart-ce014315-4add-4a6d-82cd-0739fbb7d4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22536
81899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_nak_trans.2253681899
Directory /workspace/20.usbdev_nak_trans/latest

Test location /workspace/coverage/default/26.usbdev_nak_trans.639492522
Short name T1737
Test name
Test status
Simulation time 230782385 ps
CPU time 0.93 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:22 PM PDT 24
Peak memory 206756 kb
Host smart-52843790-f8b3-4bbd-9a14-da2f69f51fa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63949
2522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_nak_trans.639492522
Directory /workspace/26.usbdev_nak_trans/latest

Test location /workspace/coverage/default/28.usbdev_nak_trans.1664278089
Short name T2617
Test name
Test status
Simulation time 208770737 ps
CPU time 0.89 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:00:41 PM PDT 24
Peak memory 206768 kb
Host smart-215e3e39-9f93-4807-aee9-bcf9d4d8a004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16642
78089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_nak_trans.1664278089
Directory /workspace/28.usbdev_nak_trans/latest

Test location /workspace/coverage/default/41.usbdev_nak_trans.1498915083
Short name T119
Test name
Test status
Simulation time 214702410 ps
CPU time 0.84 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206736 kb
Host smart-8a4eeccb-370f-4ab3-aa11-4bb30d0dc91d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14989
15083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_nak_trans.1498915083
Directory /workspace/41.usbdev_nak_trans/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1280447711
Short name T2752
Test name
Test status
Simulation time 216825315 ps
CPU time 2.09 seconds
Started Jul 22 06:20:49 PM PDT 24
Finished Jul 22 06:20:51 PM PDT 24
Peak memory 206832 kb
Host smart-b4f49a97-97e8-40ad-a282-2bee783d3901
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1280447711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1280447711
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1210006415
Short name T197
Test name
Test status
Simulation time 1841814835 ps
CPU time 10.13 seconds
Started Jul 22 06:23:18 PM PDT 24
Finished Jul 22 06:23:29 PM PDT 24
Peak memory 206792 kb
Host smart-e3f9c966-264c-4d0d-8a8e-da5f704b0d5f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1210006415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1210006415
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.2319803627
Short name T2768
Test name
Test status
Simulation time 158358307 ps
CPU time 0.92 seconds
Started Jul 22 06:20:53 PM PDT 24
Finished Jul 22 06:20:54 PM PDT 24
Peak memory 206604 kb
Host smart-1c0d0dbb-a73b-441d-8947-b12ee543a743
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2319803627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.2319803627
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1721404379
Short name T2773
Test name
Test status
Simulation time 125229449 ps
CPU time 1.33 seconds
Started Jul 22 06:23:18 PM PDT 24
Finished Jul 22 06:23:20 PM PDT 24
Peak memory 215052 kb
Host smart-ba3b5913-9b1d-44af-9b78-40bc50e36911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721404379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1721404379
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3216855584
Short name T2772
Test name
Test status
Simulation time 118821258 ps
CPU time 1.06 seconds
Started Jul 22 06:20:58 PM PDT 24
Finished Jul 22 06:21:00 PM PDT 24
Peak memory 206884 kb
Host smart-0d3d2238-e915-4787-acc3-e72a907210c5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3216855584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3216855584
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1815021100
Short name T2771
Test name
Test status
Simulation time 36063468 ps
CPU time 0.64 seconds
Started Jul 22 06:23:17 PM PDT 24
Finished Jul 22 06:23:18 PM PDT 24
Peak memory 206520 kb
Host smart-4b7518a5-cbb8-4312-97d4-7d3ca2eabbc6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1815021100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1815021100
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.3951491091
Short name T266
Test name
Test status
Simulation time 86620907 ps
CPU time 2.35 seconds
Started Jul 22 06:20:51 PM PDT 24
Finished Jul 22 06:20:54 PM PDT 24
Peak memory 215000 kb
Host smart-ea2447ae-f8a4-41b4-a620-d05d023b0266
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3951491091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.3951491091
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2667040215
Short name T2852
Test name
Test status
Simulation time 92887848 ps
CPU time 2.33 seconds
Started Jul 22 06:20:55 PM PDT 24
Finished Jul 22 06:20:58 PM PDT 24
Peak memory 206844 kb
Host smart-bb6724e7-ba10-4242-9c87-9cbf14cea687
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2667040215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2667040215
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1441398652
Short name T2781
Test name
Test status
Simulation time 222182591 ps
CPU time 1.57 seconds
Started Jul 22 06:21:26 PM PDT 24
Finished Jul 22 06:21:29 PM PDT 24
Peak memory 206836 kb
Host smart-63a873d8-1fe0-4bc1-b80b-86ebdc68bea1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1441398652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1441398652
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.2447448706
Short name T220
Test name
Test status
Simulation time 79664459 ps
CPU time 1.83 seconds
Started Jul 22 06:20:50 PM PDT 24
Finished Jul 22 06:20:52 PM PDT 24
Peak memory 207000 kb
Host smart-feed895f-3ed7-4c1d-87f5-bdd941bb872f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2447448706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.2447448706
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.4256305118
Short name T243
Test name
Test status
Simulation time 629859125 ps
CPU time 3.06 seconds
Started Jul 22 06:20:58 PM PDT 24
Finished Jul 22 06:21:02 PM PDT 24
Peak memory 206888 kb
Host smart-3abc9ba5-4c96-4202-a2c3-19b40430fcc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4256305118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.4256305118
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.543569847
Short name T2751
Test name
Test status
Simulation time 151412623 ps
CPU time 3.41 seconds
Started Jul 22 06:21:54 PM PDT 24
Finished Jul 22 06:21:58 PM PDT 24
Peak memory 206680 kb
Host smart-1a6b898f-da06-48f8-baff-5f4361d43f9f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=543569847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.543569847
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.1559174783
Short name T263
Test name
Test status
Simulation time 1622162010 ps
CPU time 8.84 seconds
Started Jul 22 06:20:56 PM PDT 24
Finished Jul 22 06:21:05 PM PDT 24
Peak memory 206852 kb
Host smart-d4ef9397-f770-4c14-951a-d22aa29cc8c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1559174783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.1559174783
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.945745739
Short name T2795
Test name
Test status
Simulation time 182346909 ps
CPU time 0.95 seconds
Started Jul 22 06:20:51 PM PDT 24
Finished Jul 22 06:20:52 PM PDT 24
Peak memory 206656 kb
Host smart-475729e8-7705-4e6b-bf2c-df3b8c6a22d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=945745739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.945745739
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.559391918
Short name T279
Test name
Test status
Simulation time 96084470 ps
CPU time 1.18 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 214960 kb
Host smart-7ced5c1e-5e19-401a-a5cc-50e9dce0026e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559391918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev
_csr_mem_rw_with_rand_reset.559391918
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.206625483
Short name T2834
Test name
Test status
Simulation time 82805745 ps
CPU time 0.7 seconds
Started Jul 22 06:20:48 PM PDT 24
Finished Jul 22 06:20:49 PM PDT 24
Peak memory 206520 kb
Host smart-2d0d4241-e116-410b-b49f-795d5cfdf98f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=206625483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.206625483
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2682092191
Short name T257
Test name
Test status
Simulation time 213629303 ps
CPU time 2.4 seconds
Started Jul 22 06:23:18 PM PDT 24
Finished Jul 22 06:23:21 PM PDT 24
Peak memory 215060 kb
Host smart-d7e23d57-1689-4984-90ff-e762e2661318
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2682092191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2682092191
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.686195705
Short name T2769
Test name
Test status
Simulation time 259477646 ps
CPU time 2.62 seconds
Started Jul 22 06:20:58 PM PDT 24
Finished Jul 22 06:21:01 PM PDT 24
Peak memory 206788 kb
Host smart-809d3d7b-56b6-4212-8501-def6a36d0ab9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=686195705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.686195705
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2264341168
Short name T2765
Test name
Test status
Simulation time 52678815 ps
CPU time 1.02 seconds
Started Jul 22 06:21:09 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 206776 kb
Host smart-1c1beb34-18aa-4d64-b1d8-b0cf35689289
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2264341168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2264341168
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.498390906
Short name T193
Test name
Test status
Simulation time 144732697 ps
CPU time 1.81 seconds
Started Jul 22 06:21:47 PM PDT 24
Finished Jul 22 06:21:49 PM PDT 24
Peak memory 222484 kb
Host smart-697486b5-8263-4122-bed5-369864c745c1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=498390906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.498390906
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.3245982769
Short name T304
Test name
Test status
Simulation time 658806705 ps
CPU time 3.03 seconds
Started Jul 22 06:21:26 PM PDT 24
Finished Jul 22 06:21:30 PM PDT 24
Peak memory 206852 kb
Host smart-52c2cc79-7d4b-4dc5-b13c-7e4de5a7c578
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3245982769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.3245982769
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1668333038
Short name T2811
Test name
Test status
Simulation time 58449553 ps
CPU time 1.23 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 215072 kb
Host smart-0c26024d-3fba-4b47-bcee-772b77c2d286
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668333038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.1668333038
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.47310547
Short name T2759
Test name
Test status
Simulation time 90783224 ps
CPU time 1.03 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 206864 kb
Host smart-8e1f3188-3512-4c47-99f8-07dfa44e05e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=47310547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.47310547
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1031339944
Short name T2840
Test name
Test status
Simulation time 107946895 ps
CPU time 0.72 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206604 kb
Host smart-c9d94479-8178-4f5d-8e7e-725d134f0122
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1031339944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1031339944
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.979378223
Short name T2758
Test name
Test status
Simulation time 65710976 ps
CPU time 1.05 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206868 kb
Host smart-73f86463-9ef9-4585-8311-30af667c21fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=979378223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.979378223
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.2960554013
Short name T2842
Test name
Test status
Simulation time 158467362 ps
CPU time 1.64 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 206820 kb
Host smart-b5c361d8-5f2e-4cfd-8dbd-e8f460cf6b09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2960554013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.2960554013
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.405254105
Short name T2756
Test name
Test status
Simulation time 57649577 ps
CPU time 1.21 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 215040 kb
Host smart-841b4816-08e2-4585-b3af-cf6fae82287e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405254105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbde
v_csr_mem_rw_with_rand_reset.405254105
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2554484808
Short name T264
Test name
Test status
Simulation time 101870564 ps
CPU time 0.83 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:18 PM PDT 24
Peak memory 206576 kb
Host smart-24ee9e99-c209-40f2-a1e4-cdab9be00ab0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2554484808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2554484808
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.2046959141
Short name T301
Test name
Test status
Simulation time 42333418 ps
CPU time 0.69 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:17 PM PDT 24
Peak memory 206560 kb
Host smart-c239df52-b0c5-450b-9ea1-4fca2d2b81ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2046959141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.2046959141
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.286872461
Short name T2808
Test name
Test status
Simulation time 166395541 ps
CPU time 1.52 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 206836 kb
Host smart-372ee042-0872-41b9-9e71-3d69b4304bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=286872461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.286872461
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.1377475721
Short name T2817
Test name
Test status
Simulation time 167131927 ps
CPU time 1.51 seconds
Started Jul 22 06:23:18 PM PDT 24
Finished Jul 22 06:23:20 PM PDT 24
Peak memory 206864 kb
Host smart-67f75949-c309-4ab8-a089-e309f3a6c8d0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1377475721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.1377475721
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.4178140238
Short name T278
Test name
Test status
Simulation time 433519205 ps
CPU time 2.97 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206836 kb
Host smart-3c06f75c-8b50-4a71-86d7-8093b50828d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4178140238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.4178140238
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.859718838
Short name T2802
Test name
Test status
Simulation time 160461076 ps
CPU time 1.8 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:24 PM PDT 24
Peak memory 215008 kb
Host smart-b1ab4ae5-cae6-4c94-964c-44bfb71d2b13
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859718838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbde
v_csr_mem_rw_with_rand_reset.859718838
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.2152886036
Short name T2816
Test name
Test status
Simulation time 116858020 ps
CPU time 1.07 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:21:15 PM PDT 24
Peak memory 206880 kb
Host smart-4138e9f5-21d3-4128-a92c-b872674932a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2152886036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.2152886036
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1774241962
Short name T2825
Test name
Test status
Simulation time 38787218 ps
CPU time 0.67 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206516 kb
Host smart-0971bcfc-6093-4366-8887-3ed71d600b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1774241962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1774241962
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.2410036038
Short name T2776
Test name
Test status
Simulation time 222486206 ps
CPU time 1.59 seconds
Started Jul 22 06:21:14 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 206788 kb
Host smart-ea510e0f-d3fd-47b3-8c7d-c26cf7aab63c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2410036038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.2410036038
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.376105231
Short name T306
Test name
Test status
Simulation time 754349588 ps
CPU time 4.51 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 206796 kb
Host smart-04ad352e-c4f1-4ccf-ac3b-5b6a9362f8c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=376105231 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.376105231
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1508497708
Short name T219
Test name
Test status
Simulation time 100901664 ps
CPU time 1.47 seconds
Started Jul 22 06:21:20 PM PDT 24
Finished Jul 22 06:21:25 PM PDT 24
Peak memory 218280 kb
Host smart-7f3b9c35-a114-4d76-9fa0-8af17f60f35c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508497708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd
ev_csr_mem_rw_with_rand_reset.1508497708
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.23392278
Short name T259
Test name
Test status
Simulation time 69118708 ps
CPU time 1 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 207064 kb
Host smart-cbf37ad6-69d3-461d-a52c-87b1fc5ea00e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=23392278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.23392278
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2143653919
Short name T2835
Test name
Test status
Simulation time 60001357 ps
CPU time 0.77 seconds
Started Jul 22 06:23:58 PM PDT 24
Finished Jul 22 06:23:59 PM PDT 24
Peak memory 206448 kb
Host smart-d95e622a-0de2-4fab-bcac-cdaee0eedcd6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2143653919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2143653919
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.3280288801
Short name T2783
Test name
Test status
Simulation time 195715972 ps
CPU time 1.67 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206816 kb
Host smart-5b74ed03-9bba-420b-9e64-efea4f848223
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3280288801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.3280288801
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.2886814951
Short name T230
Test name
Test status
Simulation time 290852205 ps
CPU time 2.95 seconds
Started Jul 22 06:21:06 PM PDT 24
Finished Jul 22 06:21:09 PM PDT 24
Peak memory 223244 kb
Host smart-fd92e8b5-11d3-4a51-9a80-781bf2352020
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2886814951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.2886814951
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4024772042
Short name T2820
Test name
Test status
Simulation time 992541564 ps
CPU time 5 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:18 PM PDT 24
Peak memory 206852 kb
Host smart-b85b8ac8-46ca-4b50-aa5c-4f270d3d617e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4024772042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4024772042
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.1509008253
Short name T2844
Test name
Test status
Simulation time 90437486 ps
CPU time 2.37 seconds
Started Jul 22 06:21:20 PM PDT 24
Finished Jul 22 06:21:25 PM PDT 24
Peak memory 215128 kb
Host smart-542d127d-d3da-40ee-920b-0011a51e67d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509008253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.1509008253
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.2256315479
Short name T281
Test name
Test status
Simulation time 55422814 ps
CPU time 0.84 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:12 PM PDT 24
Peak memory 206484 kb
Host smart-b19a22e5-8882-4e56-8430-96113889417d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2256315479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.2256315479
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.2503808480
Short name T2754
Test name
Test status
Simulation time 85489330 ps
CPU time 1.09 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206780 kb
Host smart-079b857b-d4a2-49e6-ad88-b7a70a41bd21
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2503808480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.2503808480
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.772277511
Short name T235
Test name
Test status
Simulation time 99074545 ps
CPU time 2.42 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 215308 kb
Host smart-a9241f65-81e8-4931-8975-5de2d9da8881
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=772277511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.772277511
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.1761575999
Short name T194
Test name
Test status
Simulation time 2392261567 ps
CPU time 5.99 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:24 PM PDT 24
Peak memory 207084 kb
Host smart-691fdba4-ab2e-4cac-80d4-37b0d9853051
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1761575999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.1761575999
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.1392093808
Short name T2851
Test name
Test status
Simulation time 90608999 ps
CPU time 1.37 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:24:15 PM PDT 24
Peak memory 215068 kb
Host smart-182583b4-38ed-491c-832e-6fe500cdc3c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392093808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.1392093808
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1376142915
Short name T269
Test name
Test status
Simulation time 64609019 ps
CPU time 0.86 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 206636 kb
Host smart-e037b35f-9167-4219-9048-419bf5ca16b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1376142915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1376142915
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.4049908218
Short name T297
Test name
Test status
Simulation time 47300655 ps
CPU time 0.7 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:21:15 PM PDT 24
Peak memory 206516 kb
Host smart-4cb2e406-9679-46e0-97ea-c6aaf62c51b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4049908218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.4049908218
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.2025632956
Short name T2753
Test name
Test status
Simulation time 168049885 ps
CPU time 1.51 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:18 PM PDT 24
Peak memory 206872 kb
Host smart-8e6932c7-2eb8-475c-b88a-cf0fa12a0b43
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2025632956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.2025632956
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1338151852
Short name T2832
Test name
Test status
Simulation time 98015843 ps
CPU time 2.53 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 206884 kb
Host smart-f61d4dd9-a193-4c26-b0a2-f171ddfb5089
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1338151852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1338151852
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1298904535
Short name T2785
Test name
Test status
Simulation time 810490387 ps
CPU time 3.51 seconds
Started Jul 22 06:21:10 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206816 kb
Host smart-bedbd843-3077-4ae3-805f-d632a944f413
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1298904535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1298904535
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.603276608
Short name T2775
Test name
Test status
Simulation time 94188039 ps
CPU time 1.44 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 215092 kb
Host smart-b0cfa5a6-1487-4192-b6fb-7def1a0abec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603276608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbde
v_csr_mem_rw_with_rand_reset.603276608
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1938643447
Short name T261
Test name
Test status
Simulation time 139647908 ps
CPU time 1.22 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206776 kb
Host smart-0f1c2694-5b6a-4a92-93a2-a357ae85a85c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1938643447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1938643447
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.512317015
Short name T203
Test name
Test status
Simulation time 44067220 ps
CPU time 0.72 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206592 kb
Host smart-d3d1f63f-3ca0-4bd7-b74a-a1fd70e65aa6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=512317015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.512317015
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.4053094676
Short name T268
Test name
Test status
Simulation time 190300072 ps
CPU time 1.63 seconds
Started Jul 22 06:22:55 PM PDT 24
Finished Jul 22 06:22:58 PM PDT 24
Peak memory 206872 kb
Host smart-91a0540b-3e56-4fd7-98af-010af0549005
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4053094676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.4053094676
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.1963238273
Short name T225
Test name
Test status
Simulation time 92197536 ps
CPU time 1.35 seconds
Started Jul 22 06:21:19 PM PDT 24
Finished Jul 22 06:21:24 PM PDT 24
Peak memory 206924 kb
Host smart-fe31ff77-171e-4540-ba8d-f439d782bc09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1963238273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.1963238273
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.196750464
Short name T307
Test name
Test status
Simulation time 348358810 ps
CPU time 2.48 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206752 kb
Host smart-f32ceed4-52cf-46b1-95f0-d54b93199b8f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=196750464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.196750464
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.918767493
Short name T2838
Test name
Test status
Simulation time 66885642 ps
CPU time 1.76 seconds
Started Jul 22 06:21:04 PM PDT 24
Finished Jul 22 06:21:07 PM PDT 24
Peak memory 215092 kb
Host smart-1a48346e-c35e-47cd-95e5-6c136fbe8390
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918767493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbde
v_csr_mem_rw_with_rand_reset.918767493
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2552009496
Short name T221
Test name
Test status
Simulation time 55198649 ps
CPU time 0.81 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206616 kb
Host smart-542c6936-ac8d-4541-8e74-294f0c407b94
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2552009496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2552009496
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2159459171
Short name T2830
Test name
Test status
Simulation time 48001556 ps
CPU time 0.65 seconds
Started Jul 22 06:21:10 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 206492 kb
Host smart-84fffe53-4e2e-403d-b084-d388141a11bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2159459171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2159459171
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.1105603380
Short name T2780
Test name
Test status
Simulation time 173071379 ps
CPU time 1.26 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206828 kb
Host smart-03805ce5-ccb3-463d-b2c4-dbbb192dbb68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1105603380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.1105603380
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.1292837200
Short name T2793
Test name
Test status
Simulation time 275729666 ps
CPU time 2.99 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:24:17 PM PDT 24
Peak memory 206860 kb
Host smart-2cb7efa2-a0b3-4e70-8283-44d7e335ea25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1292837200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.1292837200
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3463244372
Short name T2767
Test name
Test status
Simulation time 124201371 ps
CPU time 2.43 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 215044 kb
Host smart-f46bf7e7-2964-40a9-8410-be1e912bcbe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463244372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3463244372
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.1703468832
Short name T2794
Test name
Test status
Simulation time 79546362 ps
CPU time 1.01 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 206868 kb
Host smart-9a00534e-cf61-4cb9-8cf4-5d49a84dec29
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1703468832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.1703468832
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3353521327
Short name T295
Test name
Test status
Simulation time 42490206 ps
CPU time 0.69 seconds
Started Jul 22 06:23:18 PM PDT 24
Finished Jul 22 06:23:19 PM PDT 24
Peak memory 206524 kb
Host smart-6b24857e-4bee-4af7-85ee-c8acb4c37b77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3353521327 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3353521327
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.941613704
Short name T2792
Test name
Test status
Simulation time 127123432 ps
CPU time 1.25 seconds
Started Jul 22 06:23:59 PM PDT 24
Finished Jul 22 06:24:00 PM PDT 24
Peak memory 206492 kb
Host smart-fdd93d86-eaee-4df1-b298-4b5a18c4e1ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=941613704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.941613704
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.89533075
Short name T2799
Test name
Test status
Simulation time 266037058 ps
CPU time 2.32 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 214952 kb
Host smart-4c955c9f-facf-4a60-b04e-55f96607bc3a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=89533075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.89533075
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1064777751
Short name T240
Test name
Test status
Simulation time 807670278 ps
CPU time 5.43 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:24 PM PDT 24
Peak memory 206772 kb
Host smart-ff8829a8-41c8-42b7-8387-2b2dbe1c2fb7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1064777751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1064777751
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.3359503130
Short name T2784
Test name
Test status
Simulation time 64993117 ps
CPU time 1.31 seconds
Started Jul 22 06:21:21 PM PDT 24
Finished Jul 22 06:21:25 PM PDT 24
Peak memory 215056 kb
Host smart-74170d4b-a6bd-44a1-8955-5f3af7179119
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359503130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd
ev_csr_mem_rw_with_rand_reset.3359503130
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.4179076149
Short name T2777
Test name
Test status
Simulation time 63781108 ps
CPU time 1.02 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206780 kb
Host smart-1c6ed995-0651-4bc2-bedf-a810124be890
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4179076149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.4179076149
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.128442426
Short name T2791
Test name
Test status
Simulation time 129708809 ps
CPU time 0.76 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:17 PM PDT 24
Peak memory 206548 kb
Host smart-43363b51-e711-4c27-bb80-f4244f0258fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=128442426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.128442426
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.2734878650
Short name T2757
Test name
Test status
Simulation time 107851468 ps
CPU time 1.77 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:23 PM PDT 24
Peak memory 206880 kb
Host smart-7a538d04-4942-4dcc-a9c3-735340083525
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2734878650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.2734878650
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.3838370989
Short name T2847
Test name
Test status
Simulation time 152222189 ps
CPU time 2.44 seconds
Started Jul 22 06:23:00 PM PDT 24
Finished Jul 22 06:23:04 PM PDT 24
Peak memory 206848 kb
Host smart-37fbe060-b25f-4be2-87a8-c83879c59487
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3838370989 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.3838370989
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.3936643460
Short name T305
Test name
Test status
Simulation time 527460488 ps
CPU time 2.99 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:24:16 PM PDT 24
Peak memory 206232 kb
Host smart-f9b4fa7b-04e9-44cd-86b4-51203690128f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3936643460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.3936643460
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.999671996
Short name T2766
Test name
Test status
Simulation time 389692593 ps
CPU time 3.65 seconds
Started Jul 22 06:21:00 PM PDT 24
Finished Jul 22 06:21:04 PM PDT 24
Peak memory 206824 kb
Host smart-fe8a70e3-81f6-42ec-acf6-59a8a3edd17b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=999671996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.999671996
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4248463698
Short name T2770
Test name
Test status
Simulation time 822938052 ps
CPU time 7.44 seconds
Started Jul 22 06:21:19 PM PDT 24
Finished Jul 22 06:21:30 PM PDT 24
Peak memory 206796 kb
Host smart-6a9da68f-8c4f-4aa2-aaf0-d265c5815d2f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4248463698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4248463698
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2916480367
Short name T2763
Test name
Test status
Simulation time 110060221 ps
CPU time 0.84 seconds
Started Jul 22 06:22:35 PM PDT 24
Finished Jul 22 06:22:36 PM PDT 24
Peak memory 206608 kb
Host smart-70fec235-1181-42ef-84aa-5cb06fe1aa6c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2916480367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2916480367
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.1762745282
Short name T2845
Test name
Test status
Simulation time 59000925 ps
CPU time 1.21 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 215048 kb
Host smart-afdb8d28-57d0-4364-a56b-76f0166d387f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762745282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.1762745282
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1322277030
Short name T2806
Test name
Test status
Simulation time 79119836 ps
CPU time 1.08 seconds
Started Jul 22 06:21:04 PM PDT 24
Finished Jul 22 06:21:06 PM PDT 24
Peak memory 206808 kb
Host smart-0099a6d1-8a42-4954-9fdf-2fe9f765f7d0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1322277030 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1322277030
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2744011809
Short name T284
Test name
Test status
Simulation time 37629112 ps
CPU time 0.65 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:13 PM PDT 24
Peak memory 206484 kb
Host smart-5fb6424a-2c09-4435-a18a-cafac8536b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2744011809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2744011809
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.3945741718
Short name T267
Test name
Test status
Simulation time 142132375 ps
CPU time 1.45 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:13 PM PDT 24
Peak memory 223164 kb
Host smart-e1d52301-9b83-4594-8702-ad2e2f48cba3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3945741718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.3945741718
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.1584999245
Short name T2812
Test name
Test status
Simulation time 479917532 ps
CPU time 4.37 seconds
Started Jul 22 06:21:09 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 206772 kb
Host smart-f2d763f9-b942-4870-83d4-e596ca2ac2a2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1584999245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.1584999245
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.4002932170
Short name T2833
Test name
Test status
Simulation time 61660387 ps
CPU time 1.02 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:13 PM PDT 24
Peak memory 206840 kb
Host smart-c10d945c-5b34-4193-9747-7153d227232d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4002932170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.4002932170
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.2149835526
Short name T2818
Test name
Test status
Simulation time 361930150 ps
CPU time 3.39 seconds
Started Jul 22 06:21:20 PM PDT 24
Finished Jul 22 06:21:26 PM PDT 24
Peak memory 222420 kb
Host smart-bfe88d8b-0911-4765-9c09-3c34b2283f6e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2149835526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.2149835526
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.3019721566
Short name T300
Test name
Test status
Simulation time 64726561 ps
CPU time 0.68 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206516 kb
Host smart-f28c6014-b18d-4df7-b2dd-100272fec65f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3019721566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.3019721566
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2589916484
Short name T2839
Test name
Test status
Simulation time 38952773 ps
CPU time 0.73 seconds
Started Jul 22 06:23:58 PM PDT 24
Finished Jul 22 06:23:59 PM PDT 24
Peak memory 206448 kb
Host smart-18f0156f-8d12-4aa8-a950-088f5e6388f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2589916484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2589916484
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.400038107
Short name T2846
Test name
Test status
Simulation time 41711498 ps
CPU time 0.77 seconds
Started Jul 22 06:21:41 PM PDT 24
Finished Jul 22 06:21:42 PM PDT 24
Peak memory 206488 kb
Host smart-ae0d184c-13da-4c0e-b7ce-8644f83ae698
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=400038107 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.400038107
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1462947218
Short name T290
Test name
Test status
Simulation time 45048775 ps
CPU time 0.65 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 206448 kb
Host smart-8a68571b-d79a-4d71-adee-3de7d81469a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1462947218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1462947218
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1762085176
Short name T2814
Test name
Test status
Simulation time 30479822 ps
CPU time 0.66 seconds
Started Jul 22 06:21:26 PM PDT 24
Finished Jul 22 06:21:28 PM PDT 24
Peak memory 206560 kb
Host smart-b4840bbc-857b-4361-902b-54cc37bbd6d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1762085176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1762085176
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.1558597682
Short name T2823
Test name
Test status
Simulation time 82713707 ps
CPU time 0.73 seconds
Started Jul 22 06:22:05 PM PDT 24
Finished Jul 22 06:22:06 PM PDT 24
Peak memory 206524 kb
Host smart-e2305a6c-9912-43c3-bfda-f9c17c08a217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1558597682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.1558597682
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.2232214317
Short name T291
Test name
Test status
Simulation time 52751710 ps
CPU time 0.76 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 206592 kb
Host smart-0b8a09b8-5612-4127-bceb-d37fe064dc55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2232214317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.2232214317
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2126048627
Short name T294
Test name
Test status
Simulation time 48130365 ps
CPU time 0.68 seconds
Started Jul 22 06:23:59 PM PDT 24
Finished Jul 22 06:24:00 PM PDT 24
Peak memory 206212 kb
Host smart-aca2a456-7c21-4214-9d7b-de1b6bbce9eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2126048627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2126048627
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3361472304
Short name T2779
Test name
Test status
Simulation time 128687878 ps
CPU time 3.48 seconds
Started Jul 22 06:21:12 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 206788 kb
Host smart-b8c6cd05-1f3e-4b5a-badd-83b2228ed1fb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3361472304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3361472304
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.3346717588
Short name T2837
Test name
Test status
Simulation time 1260164965 ps
CPU time 7.42 seconds
Started Jul 22 06:21:08 PM PDT 24
Finished Jul 22 06:21:17 PM PDT 24
Peak memory 206720 kb
Host smart-57761674-1e79-4282-9f06-4f1799b3a67b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3346717588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.3346717588
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2838146144
Short name T283
Test name
Test status
Simulation time 136630497 ps
CPU time 0.97 seconds
Started Jul 22 06:21:24 PM PDT 24
Finished Jul 22 06:21:27 PM PDT 24
Peak memory 206636 kb
Host smart-b67cd939-83b7-4150-ba74-addb79b6e442
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2838146144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2838146144
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.3332069201
Short name T2849
Test name
Test status
Simulation time 87108130 ps
CPU time 1.87 seconds
Started Jul 22 06:21:04 PM PDT 24
Finished Jul 22 06:21:07 PM PDT 24
Peak memory 215132 kb
Host smart-4e40f564-0a63-48f2-a968-c4548d757439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332069201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.3332069201
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.2331959597
Short name T2796
Test name
Test status
Simulation time 59131252 ps
CPU time 0.83 seconds
Started Jul 22 06:21:09 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 206588 kb
Host smart-26547e6f-93f7-427f-a27e-296c8470196d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2331959597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.2331959597
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.36799161
Short name T2822
Test name
Test status
Simulation time 47046039 ps
CPU time 0.71 seconds
Started Jul 22 06:21:54 PM PDT 24
Finished Jul 22 06:21:55 PM PDT 24
Peak memory 206396 kb
Host smart-9cf622b9-029d-44cb-b90b-164905520b08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=36799161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.36799161
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4075311698
Short name T265
Test name
Test status
Simulation time 207807515 ps
CPU time 2.3 seconds
Started Jul 22 06:23:29 PM PDT 24
Finished Jul 22 06:23:32 PM PDT 24
Peak memory 214980 kb
Host smart-6b4c9d78-16cf-4eb7-9d67-43f87cc831a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4075311698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4075311698
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2756578237
Short name T2787
Test name
Test status
Simulation time 165033446 ps
CPU time 4 seconds
Started Jul 22 06:22:34 PM PDT 24
Finished Jul 22 06:22:38 PM PDT 24
Peak memory 206820 kb
Host smart-cdd5a2f4-267f-4dcf-ae88-e23d923c085f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2756578237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2756578237
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.2130669131
Short name T223
Test name
Test status
Simulation time 115111879 ps
CPU time 1.49 seconds
Started Jul 22 06:21:08 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 206812 kb
Host smart-aea7ec73-c64e-47b2-a433-ef22dd9143d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2130669131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.2130669131
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3969377462
Short name T231
Test name
Test status
Simulation time 175532759 ps
CPU time 2.39 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:14 PM PDT 24
Peak memory 222296 kb
Host smart-c3d04683-0b07-4327-9aea-9b7b6c838886
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3969377462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3969377462
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.3193759208
Short name T2755
Test name
Test status
Simulation time 497459021 ps
CPU time 2.55 seconds
Started Jul 22 06:21:08 PM PDT 24
Finished Jul 22 06:21:12 PM PDT 24
Peak memory 206760 kb
Host smart-315dc5c6-2a67-4a84-84ee-af74bb510add
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3193759208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.3193759208
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2275256585
Short name T293
Test name
Test status
Simulation time 42009927 ps
CPU time 0.67 seconds
Started Jul 22 06:21:26 PM PDT 24
Finished Jul 22 06:21:28 PM PDT 24
Peak memory 206532 kb
Host smart-1cbe6ddb-6b22-4ff3-a90e-e90d2e5540a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2275256585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2275256585
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.1096951772
Short name T298
Test name
Test status
Simulation time 43855504 ps
CPU time 0.67 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 206488 kb
Host smart-19fb3f24-a348-4b32-b459-9a3cb9ec2549
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1096951772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.1096951772
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.3573616233
Short name T2848
Test name
Test status
Simulation time 42498936 ps
CPU time 0.69 seconds
Started Jul 22 06:21:21 PM PDT 24
Finished Jul 22 06:21:25 PM PDT 24
Peak memory 206484 kb
Host smart-1f121400-a5e2-4398-bbd0-8d83856a2881
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3573616233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.3573616233
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2184000761
Short name T2809
Test name
Test status
Simulation time 36379115 ps
CPU time 0.68 seconds
Started Jul 22 06:21:19 PM PDT 24
Finished Jul 22 06:21:23 PM PDT 24
Peak memory 206448 kb
Host smart-165b22f4-dfd8-47b3-8e59-43e3b8eef877
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2184000761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2184000761
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.1985359160
Short name T2797
Test name
Test status
Simulation time 40838448 ps
CPU time 0.71 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:24:14 PM PDT 24
Peak memory 206080 kb
Host smart-561324d2-7be0-400b-82a1-4992452124d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1985359160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.1985359160
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.1276829054
Short name T296
Test name
Test status
Simulation time 48074779 ps
CPU time 0.7 seconds
Started Jul 22 06:21:26 PM PDT 24
Finished Jul 22 06:21:27 PM PDT 24
Peak memory 206556 kb
Host smart-f2e03eab-1342-466e-bc72-c89382e4aa57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1276829054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.1276829054
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1083735807
Short name T2798
Test name
Test status
Simulation time 83090631 ps
CPU time 0.77 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 206536 kb
Host smart-826ad7d1-f479-4019-ad12-934108b6a7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1083735807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1083735807
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.4130528948
Short name T288
Test name
Test status
Simulation time 50559420 ps
CPU time 0.69 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 206544 kb
Host smart-bf9f7f61-9069-4592-9134-511ddbf73622
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4130528948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.4130528948
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.3491984117
Short name T2824
Test name
Test status
Simulation time 88415098 ps
CPU time 0.7 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:17 PM PDT 24
Peak memory 206520 kb
Host smart-f43b90a4-d376-4add-bde1-3ecaa09088d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3491984117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.3491984117
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1226416277
Short name T2805
Test name
Test status
Simulation time 169459802 ps
CPU time 1.99 seconds
Started Jul 22 06:21:08 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 206824 kb
Host smart-86139c3a-2d87-459a-8ecf-339f1de65e18
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1226416277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1226416277
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.3209929905
Short name T256
Test name
Test status
Simulation time 666311099 ps
CPU time 7.35 seconds
Started Jul 22 06:21:05 PM PDT 24
Finished Jul 22 06:21:13 PM PDT 24
Peak memory 206792 kb
Host smart-93a21131-3341-41a9-bd44-cf9bb435fe3c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3209929905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.3209929905
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3937347848
Short name T2774
Test name
Test status
Simulation time 155319190 ps
CPU time 0.98 seconds
Started Jul 22 06:20:59 PM PDT 24
Finished Jul 22 06:21:01 PM PDT 24
Peak memory 206584 kb
Host smart-6bf0b8fa-8213-4775-9209-a39bfe2f6ffc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3937347848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3937347848
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.2779639068
Short name T2829
Test name
Test status
Simulation time 200115610 ps
CPU time 1.97 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 215076 kb
Host smart-95161aab-ddad-4021-8815-0ed18b2c66a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779639068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde
v_csr_mem_rw_with_rand_reset.2779639068
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.3720719382
Short name T2764
Test name
Test status
Simulation time 131461329 ps
CPU time 0.91 seconds
Started Jul 22 06:22:37 PM PDT 24
Finished Jul 22 06:22:39 PM PDT 24
Peak memory 206616 kb
Host smart-4d8f2656-ad7e-49be-9070-a3193a3321e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3720719382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.3720719382
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3804772339
Short name T2782
Test name
Test status
Simulation time 44897550 ps
CPU time 0.66 seconds
Started Jul 22 06:21:02 PM PDT 24
Finished Jul 22 06:21:03 PM PDT 24
Peak memory 206592 kb
Host smart-5347bac0-d51b-4f2c-8ab2-746bfffbcf08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3804772339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3804772339
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.2766867691
Short name T260
Test name
Test status
Simulation time 78893913 ps
CPU time 2.16 seconds
Started Jul 22 06:21:01 PM PDT 24
Finished Jul 22 06:21:04 PM PDT 24
Peak memory 214996 kb
Host smart-5ca3ce3e-16cd-4604-b6ec-bfb35a36c6c2
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2766867691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.2766867691
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.298798524
Short name T2750
Test name
Test status
Simulation time 309647381 ps
CPU time 2.54 seconds
Started Jul 22 06:21:03 PM PDT 24
Finished Jul 22 06:21:06 PM PDT 24
Peak memory 206784 kb
Host smart-aee80023-d23f-4056-96f8-c8d8e7fa168e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=298798524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.298798524
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.2609016230
Short name T270
Test name
Test status
Simulation time 134395393 ps
CPU time 1.6 seconds
Started Jul 22 06:22:56 PM PDT 24
Finished Jul 22 06:22:59 PM PDT 24
Peak memory 206812 kb
Host smart-5ae1c6d0-4f23-4751-9aac-350514071d47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2609016230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.2609016230
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3942310146
Short name T2800
Test name
Test status
Simulation time 905534065 ps
CPU time 5.44 seconds
Started Jul 22 06:21:24 PM PDT 24
Finished Jul 22 06:21:31 PM PDT 24
Peak memory 206792 kb
Host smart-ff372a4c-d1f2-4604-a605-387e7e8ff1c1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3942310146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3942310146
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2538903039
Short name T2801
Test name
Test status
Simulation time 62294532 ps
CPU time 0.69 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 206516 kb
Host smart-6664c173-9c7c-4f82-993b-55d6541dff02
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2538903039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2538903039
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.2086931980
Short name T285
Test name
Test status
Simulation time 68814493 ps
CPU time 0.7 seconds
Started Jul 22 06:22:51 PM PDT 24
Finished Jul 22 06:22:52 PM PDT 24
Peak memory 206524 kb
Host smart-8e7312d9-31f2-4cb0-ad7a-5fa722c63de9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2086931980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.2086931980
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.3434193524
Short name T2810
Test name
Test status
Simulation time 48912114 ps
CPU time 0.67 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:18 PM PDT 24
Peak memory 206520 kb
Host smart-6baf703a-e4f1-4ddb-8084-143153d72db9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3434193524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.3434193524
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.1866990189
Short name T2790
Test name
Test status
Simulation time 35595170 ps
CPU time 0.7 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 206520 kb
Host smart-257514de-98f3-4640-a698-9ff0374a196a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1866990189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.1866990189
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3137108616
Short name T2807
Test name
Test status
Simulation time 40315334 ps
CPU time 0.78 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:23 PM PDT 24
Peak memory 206536 kb
Host smart-beed405f-d8a8-4e75-9771-ef5f8447574b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3137108616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3137108616
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.4019974574
Short name T2850
Test name
Test status
Simulation time 49986442 ps
CPU time 0.68 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206520 kb
Host smart-49b2f0d2-bbb9-4c6b-a85d-a12fa3a1403e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4019974574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.4019974574
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.2487599739
Short name T287
Test name
Test status
Simulation time 41607738 ps
CPU time 0.81 seconds
Started Jul 22 06:21:19 PM PDT 24
Finished Jul 22 06:21:23 PM PDT 24
Peak memory 206536 kb
Host smart-77497617-47e1-4654-a637-fc4188610e81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2487599739 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.2487599739
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2284207088
Short name T2804
Test name
Test status
Simulation time 63840338 ps
CPU time 0.72 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:21 PM PDT 24
Peak memory 206496 kb
Host smart-5dbb8476-115f-4b25-b05b-e6742f5311cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2284207088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2284207088
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2306350609
Short name T2813
Test name
Test status
Simulation time 35024569 ps
CPU time 0.71 seconds
Started Jul 22 06:24:13 PM PDT 24
Finished Jul 22 06:24:14 PM PDT 24
Peak memory 206532 kb
Host smart-5f77ad8b-0de9-4566-aad6-1698249d7d33
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2306350609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2306350609
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.151091317
Short name T239
Test name
Test status
Simulation time 168854071 ps
CPU time 1.89 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:24 PM PDT 24
Peak memory 215128 kb
Host smart-10534d30-0e26-4ef6-9a08-7b1fefa33560
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151091317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev
_csr_mem_rw_with_rand_reset.151091317
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.202995310
Short name T2831
Test name
Test status
Simulation time 71330495 ps
CPU time 0.83 seconds
Started Jul 22 06:21:24 PM PDT 24
Finished Jul 22 06:21:27 PM PDT 24
Peak memory 206592 kb
Host smart-7a330319-ca56-4225-8bee-4f77698c793a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=202995310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.202995310
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2606602382
Short name T204
Test name
Test status
Simulation time 49049687 ps
CPU time 0.69 seconds
Started Jul 22 06:21:08 PM PDT 24
Finished Jul 22 06:21:10 PM PDT 24
Peak memory 206508 kb
Host smart-faf91164-6824-4958-bc80-01a512772b66
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2606602382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2606602382
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.514091191
Short name T2762
Test name
Test status
Simulation time 258258877 ps
CPU time 1.57 seconds
Started Jul 22 06:21:16 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 206824 kb
Host smart-bbce7950-67d8-43cc-9b4d-415f8fb71eef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=514091191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.514091191
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2272774769
Short name T2828
Test name
Test status
Simulation time 216270554 ps
CPU time 2.61 seconds
Started Jul 22 06:21:11 PM PDT 24
Finished Jul 22 06:21:15 PM PDT 24
Peak memory 215044 kb
Host smart-4df946a6-4cd3-4780-8dfb-bea40283cc27
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2272774769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2272774769
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.4183416083
Short name T2788
Test name
Test status
Simulation time 291549592 ps
CPU time 2.35 seconds
Started Jul 22 06:22:34 PM PDT 24
Finished Jul 22 06:22:37 PM PDT 24
Peak memory 206800 kb
Host smart-6b2a8a86-a837-4100-8c30-0906f80b205f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4183416083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.4183416083
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.785397038
Short name T233
Test name
Test status
Simulation time 89322780 ps
CPU time 1.66 seconds
Started Jul 22 06:21:09 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 215068 kb
Host smart-c211d22b-5b62-4808-b631-aca4b3f13192
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785397038 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev
_csr_mem_rw_with_rand_reset.785397038
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.4206196002
Short name T282
Test name
Test status
Simulation time 97280821 ps
CPU time 1.05 seconds
Started Jul 22 06:22:24 PM PDT 24
Finished Jul 22 06:22:28 PM PDT 24
Peak memory 206812 kb
Host smart-b827a6f4-6edc-46dd-84ab-1ee070a2712e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4206196002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.4206196002
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.2727238350
Short name T196
Test name
Test status
Simulation time 85705130 ps
CPU time 1.16 seconds
Started Jul 22 06:21:54 PM PDT 24
Finished Jul 22 06:21:56 PM PDT 24
Peak memory 206868 kb
Host smart-eb6406d3-b081-4172-bfc7-f21e2d82f052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2727238350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.2727238350
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.3689673101
Short name T229
Test name
Test status
Simulation time 183273249 ps
CPU time 2.11 seconds
Started Jul 22 06:21:18 PM PDT 24
Finished Jul 22 06:21:24 PM PDT 24
Peak memory 206964 kb
Host smart-09dd9144-b0e0-4a9a-af15-fdd57878ff82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3689673101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.3689673101
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.3771595028
Short name T241
Test name
Test status
Simulation time 1529779455 ps
CPU time 5.02 seconds
Started Jul 22 06:21:14 PM PDT 24
Finished Jul 22 06:21:20 PM PDT 24
Peak memory 206760 kb
Host smart-e2db6539-9914-44e2-ac6c-77a76320222d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3771595028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.3771595028
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2661574085
Short name T2803
Test name
Test status
Simulation time 164000208 ps
CPU time 1.78 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 215088 kb
Host smart-8cd9473e-6aec-442d-83e4-71efdf07603f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661574085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.2661574085
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.1170281069
Short name T262
Test name
Test status
Simulation time 56507176 ps
CPU time 1.04 seconds
Started Jul 22 06:21:09 PM PDT 24
Finished Jul 22 06:21:11 PM PDT 24
Peak memory 206836 kb
Host smart-fb676907-6234-438f-ab0b-9a6ee997c640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1170281069 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.1170281069
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.2223778819
Short name T2815
Test name
Test status
Simulation time 96956316 ps
CPU time 0.75 seconds
Started Jul 22 06:21:15 PM PDT 24
Finished Jul 22 06:21:19 PM PDT 24
Peak memory 206536 kb
Host smart-74791c5c-fa10-4e1e-915f-85420e3c9d4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223778819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.2223778819
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.533898598
Short name T2843
Test name
Test status
Simulation time 120007105 ps
CPU time 1.16 seconds
Started Jul 22 06:21:08 PM PDT 24
Finished Jul 22 06:21:10 PM PDT 24
Peak memory 206864 kb
Host smart-6fbe77b5-713d-4ab9-995f-2bdba08b8446
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=533898598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.533898598
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.1428247885
Short name T2841
Test name
Test status
Simulation time 101365574 ps
CPU time 1.39 seconds
Started Jul 22 06:21:06 PM PDT 24
Finished Jul 22 06:21:08 PM PDT 24
Peak memory 206776 kb
Host smart-4bbb55fa-cacf-4f4d-b46c-dcba6fa5ce92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1428247885 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.1428247885
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1477997832
Short name T302
Test name
Test status
Simulation time 738744320 ps
CPU time 4.62 seconds
Started Jul 22 06:21:10 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 206884 kb
Host smart-750ec3c4-ed20-4424-a690-7c9c0dbfe6fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1477997832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1477997832
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.999645762
Short name T2827
Test name
Test status
Simulation time 111961722 ps
CPU time 1.76 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:21:15 PM PDT 24
Peak memory 215056 kb
Host smart-f1ab650c-791b-4643-8722-49c7009643b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999645762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev
_csr_mem_rw_with_rand_reset.999645762
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1265528908
Short name T2789
Test name
Test status
Simulation time 74394770 ps
CPU time 1.02 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:21:15 PM PDT 24
Peak memory 206772 kb
Host smart-ef0a2420-9b30-49d3-8333-805738564c26
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1265528908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1265528908
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.413400769
Short name T2819
Test name
Test status
Simulation time 59020412 ps
CPU time 0.69 seconds
Started Jul 22 06:22:55 PM PDT 24
Finished Jul 22 06:22:56 PM PDT 24
Peak memory 206524 kb
Host smart-27f71ca8-a362-46a1-8fc6-60aa6ff228b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=413400769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.413400769
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.2951053616
Short name T2760
Test name
Test status
Simulation time 226133620 ps
CPU time 1.69 seconds
Started Jul 22 06:21:17 PM PDT 24
Finished Jul 22 06:21:22 PM PDT 24
Peak memory 206920 kb
Host smart-7dfb4196-1e44-4833-80e5-999e45863998
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2951053616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.2951053616
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.2307027285
Short name T2836
Test name
Test status
Simulation time 58173330 ps
CPU time 1.31 seconds
Started Jul 22 06:21:05 PM PDT 24
Finished Jul 22 06:21:07 PM PDT 24
Peak memory 206920 kb
Host smart-bf72fb74-7e5f-488e-ab9e-1844b49bd091
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2307027285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.2307027285
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.973164135
Short name T2778
Test name
Test status
Simulation time 557242864 ps
CPU time 2.67 seconds
Started Jul 22 06:21:13 PM PDT 24
Finished Jul 22 06:21:16 PM PDT 24
Peak memory 206872 kb
Host smart-180d986d-f346-42a3-947e-4e79b1d61cd6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=973164135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.973164135
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.1914416788
Short name T2761
Test name
Test status
Simulation time 122123684 ps
CPU time 2.6 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:26 PM PDT 24
Peak memory 215016 kb
Host smart-d866b32a-3078-4409-99be-6f870c16522d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914416788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde
v_csr_mem_rw_with_rand_reset.1914416788
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.565502246
Short name T2786
Test name
Test status
Simulation time 45094441 ps
CPU time 0.85 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:25 PM PDT 24
Peak memory 206608 kb
Host smart-ac1cb551-e60e-424b-a234-0c85fce6c813
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=565502246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.565502246
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.3023357611
Short name T299
Test name
Test status
Simulation time 57325236 ps
CPU time 0.67 seconds
Started Jul 22 06:21:08 PM PDT 24
Finished Jul 22 06:21:10 PM PDT 24
Peak memory 206520 kb
Host smart-2234d59c-3d6e-4fa5-9c1e-17f9eea53358
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3023357611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.3023357611
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.1769251915
Short name T280
Test name
Test status
Simulation time 199246753 ps
CPU time 1.61 seconds
Started Jul 22 06:23:18 PM PDT 24
Finished Jul 22 06:23:20 PM PDT 24
Peak memory 206868 kb
Host smart-59d217ca-3b1b-4411-8fa6-d133ff2b6332
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1769251915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.1769251915
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4139619060
Short name T2826
Test name
Test status
Simulation time 105923642 ps
CPU time 2.78 seconds
Started Jul 22 06:22:22 PM PDT 24
Finished Jul 22 06:22:27 PM PDT 24
Peak memory 206940 kb
Host smart-f096b6e1-a0f1-4875-9298-0d5a2ea410ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4139619060 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4139619060
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/default/0.usbdev_alert_test.2348431738
Short name T2303
Test name
Test status
Simulation time 66133139 ps
CPU time 0.76 seconds
Started Jul 22 05:56:18 PM PDT 24
Finished Jul 22 05:56:19 PM PDT 24
Peak memory 206652 kb
Host smart-e7a634ac-9450-49b7-8ccf-890109206333
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2348431738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_alert_test.2348431738
Directory /workspace/0.usbdev_alert_test/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_disconnect.3753802331
Short name T793
Test name
Test status
Simulation time 4132941744 ps
CPU time 5.21 seconds
Started Jul 22 05:56:02 PM PDT 24
Finished Jul 22 05:56:08 PM PDT 24
Peak memory 206916 kb
Host smart-5a270c0a-96dd-4620-b1a5-2c4ccf025106
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3753802331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_disconnect.3753802331
Directory /workspace/0.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_reset.3695478610
Short name T644
Test name
Test status
Simulation time 13461821514 ps
CPU time 12.56 seconds
Started Jul 22 05:56:04 PM PDT 24
Finished Jul 22 05:56:16 PM PDT 24
Peak memory 206888 kb
Host smart-6934f2b4-b02a-4cc3-a084-bd8bf79990f9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3695478610 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_reset.3695478610
Directory /workspace/0.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/0.usbdev_aon_wake_resume.1435658962
Short name T1035
Test name
Test status
Simulation time 23460385580 ps
CPU time 23.28 seconds
Started Jul 22 05:55:57 PM PDT 24
Finished Jul 22 05:56:21 PM PDT 24
Peak memory 206924 kb
Host smart-f83d8a3c-5c10-4aa0-90a0-8c6710ed3e64
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1435658962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_aon_wake_resume.1435658962
Directory /workspace/0.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/0.usbdev_av_buffer.2515897272
Short name T369
Test name
Test status
Simulation time 216644058 ps
CPU time 0.89 seconds
Started Jul 22 05:56:00 PM PDT 24
Finished Jul 22 05:56:01 PM PDT 24
Peak memory 206704 kb
Host smart-3835a307-a087-4f59-8875-87d35497f4b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25158
97272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_av_buffer.2515897272
Directory /workspace/0.usbdev_av_buffer/latest

Test location /workspace/coverage/default/0.usbdev_bitstuff_err.474849416
Short name T2582
Test name
Test status
Simulation time 164213705 ps
CPU time 0.8 seconds
Started Jul 22 05:55:59 PM PDT 24
Finished Jul 22 05:56:00 PM PDT 24
Peak memory 206748 kb
Host smart-1e6d8f89-2e31-4673-982f-22f4b278a31e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47484
9416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_bitstuff_err.474849416
Directory /workspace/0.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_clear.61868579
Short name T1009
Test name
Test status
Simulation time 251920116 ps
CPU time 1.05 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206732 kb
Host smart-0e96a74e-eded-444d-8cd2-ec545156bc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61868
579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_clear.61868579
Directory /workspace/0.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/0.usbdev_data_toggle_restore.3777736277
Short name T2455
Test name
Test status
Simulation time 893220022 ps
CPU time 2.05 seconds
Started Jul 22 05:56:03 PM PDT 24
Finished Jul 22 05:56:05 PM PDT 24
Peak memory 206812 kb
Host smart-b9cc8da0-4089-4244-a4a0-36fbbd4cb9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37777
36277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_data_toggle_restore.3777736277
Directory /workspace/0.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/0.usbdev_device_address.3429754688
Short name T2286
Test name
Test status
Simulation time 9575630126 ps
CPU time 21.5 seconds
Started Jul 22 05:56:03 PM PDT 24
Finished Jul 22 05:56:25 PM PDT 24
Peak memory 206940 kb
Host smart-8dc07b0c-d044-4abc-a33d-4c5697879b60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34297
54688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_device_address.3429754688
Directory /workspace/0.usbdev_device_address/latest

Test location /workspace/coverage/default/0.usbdev_disable_endpoint.700611746
Short name T751
Test name
Test status
Simulation time 438862340 ps
CPU time 1.44 seconds
Started Jul 22 05:56:00 PM PDT 24
Finished Jul 22 05:56:02 PM PDT 24
Peak memory 206792 kb
Host smart-2e329d1e-d417-407c-bb05-e127318fd5db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70061
1746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disable_endpoint.700611746
Directory /workspace/0.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/0.usbdev_disconnected.1569691783
Short name T1446
Test name
Test status
Simulation time 159844690 ps
CPU time 0.77 seconds
Started Jul 22 05:56:04 PM PDT 24
Finished Jul 22 05:56:05 PM PDT 24
Peak memory 206708 kb
Host smart-07f65be0-e45b-4f8e-b8ea-5ec9b127ed03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15696
91783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_disconnected.1569691783
Directory /workspace/0.usbdev_disconnected/latest

Test location /workspace/coverage/default/0.usbdev_dpi_config_host.1019742239
Short name T1462
Test name
Test status
Simulation time 5138289940 ps
CPU time 32.48 seconds
Started Jul 22 05:56:00 PM PDT 24
Finished Jul 22 05:56:32 PM PDT 24
Peak memory 206848 kb
Host smart-6664daab-d834-439d-a880-04b05b2bea91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10197
42239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_dpi_config_host_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_dpi_config_host.1019742239
Directory /workspace/0.usbdev_dpi_config_host/latest

Test location /workspace/coverage/default/0.usbdev_enable.2823747302
Short name T2554
Test name
Test status
Simulation time 35269184 ps
CPU time 0.67 seconds
Started Jul 22 05:55:59 PM PDT 24
Finished Jul 22 05:56:00 PM PDT 24
Peak memory 206656 kb
Host smart-ba582536-fee6-4125-85c4-f65dd8632a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28237
47302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_enable.2823747302
Directory /workspace/0.usbdev_enable/latest

Test location /workspace/coverage/default/0.usbdev_endpoint_access.1667019487
Short name T1619
Test name
Test status
Simulation time 919766818 ps
CPU time 2.21 seconds
Started Jul 22 05:56:04 PM PDT 24
Finished Jul 22 05:56:06 PM PDT 24
Peak memory 206840 kb
Host smart-679a2ace-3e3c-4ee4-a0ac-45b53a2753b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16670
19487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_endpoint_access.1667019487
Directory /workspace/0.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/0.usbdev_fifo_rst.3496363875
Short name T1852
Test name
Test status
Simulation time 240301480 ps
CPU time 1.55 seconds
Started Jul 22 05:55:58 PM PDT 24
Finished Jul 22 05:56:00 PM PDT 24
Peak memory 206888 kb
Host smart-ea5c0d92-4b83-467c-8739-d05a91ead9a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
63875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_fifo_rst.3496363875
Directory /workspace/0.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk.2758174796
Short name T1925
Test name
Test status
Simulation time 117215352617 ps
CPU time 152.11 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206944 kb
Host smart-c04060b5-639e-40a4-9cb7-88277859f189
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2758174796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk.2758174796
Directory /workspace/0.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_hiclk_max.2125378156
Short name T2670
Test name
Test status
Simulation time 94074143184 ps
CPU time 142.64 seconds
Started Jul 22 05:56:04 PM PDT 24
Finished Jul 22 05:58:27 PM PDT 24
Peak memory 206924 kb
Host smart-ae587093-df40-4f66-9771-e68451527189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125378156 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_hiclk_max.2125378156
Directory /workspace/0.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk.4242561383
Short name T403
Test name
Test status
Simulation time 96118708953 ps
CPU time 119.23 seconds
Started Jul 22 05:56:00 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206980 kb
Host smart-4d4a1adb-ddc8-4e84-a02e-2a95b24f6727
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4242561383 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk.4242561383
Directory /workspace/0.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/0.usbdev_freq_loclk_max.3491722532
Short name T388
Test name
Test status
Simulation time 111021079589 ps
CPU time 173.4 seconds
Started Jul 22 05:56:11 PM PDT 24
Finished Jul 22 05:59:05 PM PDT 24
Peak memory 206920 kb
Host smart-d6ac21f2-4c09-495b-b860-2ddd12bdafeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491722532 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_loclk_max.3491722532
Directory /workspace/0.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/0.usbdev_freq_phase.4096043987
Short name T1288
Test name
Test status
Simulation time 110166800116 ps
CPU time 148.53 seconds
Started Jul 22 05:56:09 PM PDT 24
Finished Jul 22 05:58:38 PM PDT 24
Peak memory 206896 kb
Host smart-ba934cea-3a3e-4a52-8b3c-84659ab54837
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40960
43987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_freq_phase.4096043987
Directory /workspace/0.usbdev_freq_phase/latest

Test location /workspace/coverage/default/0.usbdev_in_iso.1128930813
Short name T885
Test name
Test status
Simulation time 209200490 ps
CPU time 0.87 seconds
Started Jul 22 05:58:08 PM PDT 24
Finished Jul 22 05:58:09 PM PDT 24
Peak memory 206732 kb
Host smart-938edcb8-3575-4d6d-b3f3-03a6b0025a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11289
30813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_iso.1128930813
Directory /workspace/0.usbdev_in_iso/latest

Test location /workspace/coverage/default/0.usbdev_in_stall.3881681977
Short name T2695
Test name
Test status
Simulation time 201511596 ps
CPU time 0.8 seconds
Started Jul 22 05:56:10 PM PDT 24
Finished Jul 22 05:56:11 PM PDT 24
Peak memory 206752 kb
Host smart-ab24a10b-2069-4505-8d11-7750af0c8853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38816
81977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_stall.3881681977
Directory /workspace/0.usbdev_in_stall/latest

Test location /workspace/coverage/default/0.usbdev_in_trans.782337752
Short name T344
Test name
Test status
Simulation time 186279707 ps
CPU time 0.85 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:09 PM PDT 24
Peak memory 206740 kb
Host smart-1a6fa24f-33ce-4686-a453-8db5ae062900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78233
7752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_in_trans.782337752
Directory /workspace/0.usbdev_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_iso_retraction.1552452749
Short name T2226
Test name
Test status
Simulation time 11457913622 ps
CPU time 35.58 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206904 kb
Host smart-6cf7a3b2-112c-46f2-8af5-a88b8231366e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15524
52749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_iso_retraction.1552452749
Directory /workspace/0.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/0.usbdev_link_in_err.3804579531
Short name T916
Test name
Test status
Simulation time 184096100 ps
CPU time 0.81 seconds
Started Jul 22 05:56:17 PM PDT 24
Finished Jul 22 05:56:18 PM PDT 24
Peak memory 206732 kb
Host smart-04c9fef0-0f39-46aa-98c9-8ddd81587279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38045
79531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_in_err.3804579531
Directory /workspace/0.usbdev_link_in_err/latest

Test location /workspace/coverage/default/0.usbdev_link_out_err.411887751
Short name T77
Test name
Test status
Simulation time 538822202 ps
CPU time 1.37 seconds
Started Jul 22 05:56:07 PM PDT 24
Finished Jul 22 05:56:09 PM PDT 24
Peak memory 206740 kb
Host smart-fd963340-af7f-4473-9ff8-df9ab26bd20b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41188
7751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_out_err.411887751
Directory /workspace/0.usbdev_link_out_err/latest

Test location /workspace/coverage/default/0.usbdev_link_resume.2458718393
Short name T982
Test name
Test status
Simulation time 23324155239 ps
CPU time 21.5 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:30 PM PDT 24
Peak memory 206788 kb
Host smart-5fe44c97-cfdd-4fd9-82b0-06235b813491
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24587
18393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_resume.2458718393
Directory /workspace/0.usbdev_link_resume/latest

Test location /workspace/coverage/default/0.usbdev_link_suspend.3608072384
Short name T780
Test name
Test status
Simulation time 3333422481 ps
CPU time 3.89 seconds
Started Jul 22 05:56:09 PM PDT 24
Finished Jul 22 05:56:14 PM PDT 24
Peak memory 206824 kb
Host smart-7587f8f5-318b-425e-8de9-c941b1b8ce28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36080
72384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_link_suspend.3608072384
Directory /workspace/0.usbdev_link_suspend/latest

Test location /workspace/coverage/default/0.usbdev_low_speed_traffic.4276955618
Short name T1126
Test name
Test status
Simulation time 8115736682 ps
CPU time 77.07 seconds
Started Jul 22 05:56:09 PM PDT 24
Finished Jul 22 05:57:26 PM PDT 24
Peak memory 206968 kb
Host smart-77d968ae-9cb7-4897-bb67-6f65c423e99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42769
55618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_low_speed_traffic.4276955618
Directory /workspace/0.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/0.usbdev_max_inter_pkt_delay.4285644034
Short name T601
Test name
Test status
Simulation time 4376419163 ps
CPU time 115.14 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206936 kb
Host smart-1f315175-52ba-4cc1-a3e3-6f0a5922a5de
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4285644034 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_inter_pkt_delay.4285644034
Directory /workspace/0.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_max_length_in_transaction.3011006487
Short name T2363
Test name
Test status
Simulation time 266522148 ps
CPU time 0.9 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:10 PM PDT 24
Peak memory 206708 kb
Host smart-0cb5728f-1515-411d-8ba5-94482d949d8e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3011006487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_in_transaction.3011006487
Directory /workspace/0.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_length_out_transaction.375365777
Short name T1985
Test name
Test status
Simulation time 214407766 ps
CPU time 0.9 seconds
Started Jul 22 05:56:07 PM PDT 24
Finished Jul 22 05:56:08 PM PDT 24
Peak memory 206748 kb
Host smart-749ae31a-3e64-4ecc-a5fc-df7d67d7e992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37536
5777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_length_out_transaction.375365777
Directory /workspace/0.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_max_usb_traffic.3101557202
Short name T1326
Test name
Test status
Simulation time 4883036443 ps
CPU time 135.58 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206936 kb
Host smart-a7aa4286-6f9a-4252-a470-9d04d9849430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31015
57202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_max_usb_traffic.3101557202
Directory /workspace/0.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/0.usbdev_min_inter_pkt_delay.1773267997
Short name T1018
Test name
Test status
Simulation time 3796743846 ps
CPU time 102.21 seconds
Started Jul 22 05:56:10 PM PDT 24
Finished Jul 22 05:57:53 PM PDT 24
Peak memory 206880 kb
Host smart-f7f2cd09-b58e-46d4-a24c-51f0a2a08ee3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1773267997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_inter_pkt_delay.1773267997
Directory /workspace/0.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/0.usbdev_min_length_in_transaction.909631243
Short name T370
Test name
Test status
Simulation time 204553507 ps
CPU time 0.81 seconds
Started Jul 22 05:56:12 PM PDT 24
Finished Jul 22 05:56:19 PM PDT 24
Peak memory 206712 kb
Host smart-a6e929cd-de76-4efd-ab5b-94a44847cab0
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=909631243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_in_transaction.909631243
Directory /workspace/0.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_min_length_out_transaction.1596695406
Short name T961
Test name
Test status
Simulation time 136138715 ps
CPU time 0.78 seconds
Started Jul 22 05:56:15 PM PDT 24
Finished Jul 22 05:56:17 PM PDT 24
Peak memory 206692 kb
Host smart-13dfac69-1ba8-41ec-bb9c-3b97195291b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15966
95406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_min_length_out_transaction.1596695406
Directory /workspace/0.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1105821050
Short name T76
Test name
Test status
Simulation time 560827527 ps
CPU time 1.37 seconds
Started Jul 22 05:56:09 PM PDT 24
Finished Jul 22 05:56:11 PM PDT 24
Peak memory 206628 kb
Host smart-5780a68d-70cf-4bb4-bbe5-04fd87110b38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11058
21050 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_out_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full.1105821050
Directory /workspace/0.usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full/latest

Test location /workspace/coverage/default/0.usbdev_out_iso.732425762
Short name T1486
Test name
Test status
Simulation time 176118679 ps
CPU time 0.83 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:10 PM PDT 24
Peak memory 206692 kb
Host smart-46685c1e-4f67-4341-8699-b11410973b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73242
5762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_iso.732425762
Directory /workspace/0.usbdev_out_iso/latest

Test location /workspace/coverage/default/0.usbdev_out_stall.1955947292
Short name T411
Test name
Test status
Simulation time 183272230 ps
CPU time 0.82 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:10 PM PDT 24
Peak memory 206760 kb
Host smart-114cd479-2b6b-4b72-b12b-46a52c20027c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19559
47292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_stall.1955947292
Directory /workspace/0.usbdev_out_stall/latest

Test location /workspace/coverage/default/0.usbdev_out_trans_nak.4051302329
Short name T1068
Test name
Test status
Simulation time 171574543 ps
CPU time 0.81 seconds
Started Jul 22 05:56:09 PM PDT 24
Finished Jul 22 05:56:10 PM PDT 24
Peak memory 206732 kb
Host smart-a19db465-3e02-41c8-8c86-032d41417b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40513
02329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_out_trans_nak.4051302329
Directory /workspace/0.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/0.usbdev_pending_in_trans.4114624814
Short name T168
Test name
Test status
Simulation time 175207157 ps
CPU time 0.81 seconds
Started Jul 22 05:56:12 PM PDT 24
Finished Jul 22 05:56:13 PM PDT 24
Peak memory 206712 kb
Host smart-e46412db-1ff2-4c8f-8be3-49a9d2b59e70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41146
24814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pending_in_trans.4114624814
Directory /workspace/0.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_eop_single_bit_handling.2121537122
Short name T1425
Test name
Test status
Simulation time 180980541 ps
CPU time 0.87 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:07 PM PDT 24
Peak memory 206736 kb
Host smart-5a3f0bc6-f318-4ecb-9491-069053389bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21215
37122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_eop_single_bit_handling_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_eop_single_bit_handling.2121537122
Directory /workspace/0.usbdev_phy_config_eop_single_bit_handling/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_pinflip.931192688
Short name T1213
Test name
Test status
Simulation time 228826311 ps
CPU time 0.94 seconds
Started Jul 22 05:56:06 PM PDT 24
Finished Jul 22 05:56:07 PM PDT 24
Peak memory 206708 kb
Host smart-b3602ca9-6285-4d5a-9fe2-a4114b4ffa33
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=931192688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_pinflip.931192688
Directory /workspace/0.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rand_bus_type.1471307822
Short name T200
Test name
Test status
Simulation time 215500212 ps
CPU time 0.91 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:09 PM PDT 24
Peak memory 206728 kb
Host smart-2debb5ac-32c9-44a8-9a9a-ab864382cb13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14713
07822 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rand_bus_type.1471307822
Directory /workspace/0.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_rx_dp_dn.2999901675
Short name T1726
Test name
Test status
Simulation time 255020405 ps
CPU time 1.01 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:56:36 PM PDT 24
Peak memory 206748 kb
Host smart-a19ea9a7-64d7-4179-910a-ed27ca393255
User root
Command /workspace/default/simv +en_diff_rcvr=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2999901675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_rx_dp_dn.2999901675
Directory /workspace/0.usbdev_phy_config_rx_dp_dn/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_tx_use_d_se0.2538209465
Short name T2089
Test name
Test status
Simulation time 294247523 ps
CPU time 1.12 seconds
Started Jul 22 05:56:16 PM PDT 24
Finished Jul 22 05:56:17 PM PDT 24
Peak memory 206664 kb
Host smart-8b404753-df8f-4f57-b447-2f73e1de62e0
User root
Command /workspace/default/simv +tx_use_d_se0=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2538209465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_tx_use_d_se0.2538209465
Directory /workspace/0.usbdev_phy_config_tx_use_d_se0/latest

Test location /workspace/coverage/default/0.usbdev_phy_config_usb_ref_disable.2089527125
Short name T2676
Test name
Test status
Simulation time 161485078 ps
CPU time 0.82 seconds
Started Jul 22 05:56:16 PM PDT 24
Finished Jul 22 05:56:17 PM PDT 24
Peak memory 206212 kb
Host smart-8c13b947-315c-4831-9d3b-c222d23d1913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895
27125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_config_usb_ref_disable.2089527125
Directory /workspace/0.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/0.usbdev_phy_pins_sense.276862538
Short name T2434
Test name
Test status
Simulation time 67799809 ps
CPU time 0.69 seconds
Started Jul 22 05:56:11 PM PDT 24
Finished Jul 22 05:56:12 PM PDT 24
Peak memory 206684 kb
Host smart-4875200c-e281-4349-9aad-8e9a5697378a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27686
2538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_phy_pins_sense.276862538
Directory /workspace/0.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/0.usbdev_pkt_buffer.260808699
Short name T2505
Test name
Test status
Simulation time 19107948851 ps
CPU time 42.6 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206872 kb
Host smart-c49d85ac-37fc-47d0-95d0-727232f1431f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26080
8699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_buffer.260808699
Directory /workspace/0.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/0.usbdev_pkt_received.669210364
Short name T517
Test name
Test status
Simulation time 223275373 ps
CPU time 0.98 seconds
Started Jul 22 05:56:10 PM PDT 24
Finished Jul 22 05:56:12 PM PDT 24
Peak memory 206752 kb
Host smart-7f54118d-5a10-4fed-b359-7ca3768f1f54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66921
0364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_received.669210364
Directory /workspace/0.usbdev_pkt_received/latest

Test location /workspace/coverage/default/0.usbdev_pkt_sent.1952275970
Short name T1293
Test name
Test status
Simulation time 185150995 ps
CPU time 0.84 seconds
Started Jul 22 05:56:09 PM PDT 24
Finished Jul 22 05:56:11 PM PDT 24
Peak memory 206704 kb
Host smart-509eec70-b3d4-4750-9588-d7896de56c02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19522
75970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_pkt_sent.1952275970
Directory /workspace/0.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_disconnects.2910211500
Short name T853
Test name
Test status
Simulation time 4235513076 ps
CPU time 103.59 seconds
Started Jul 22 05:56:10 PM PDT 24
Finished Jul 22 05:57:54 PM PDT 24
Peak memory 206940 kb
Host smart-1e8ca38c-cacf-4a79-b946-9d54466f69ad
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2910211500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_disconnects.2910211500
Directory /workspace/0.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/0.usbdev_rand_bus_resets.2631193531
Short name T840
Test name
Test status
Simulation time 10645109231 ps
CPU time 88.37 seconds
Started Jul 22 05:56:16 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206524 kb
Host smart-c36bcdf5-c307-4e68-bdc9-7ff38bf3322a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2631193531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_bus_resets.2631193531
Directory /workspace/0.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/0.usbdev_rand_suspends.3865902417
Short name T1780
Test name
Test status
Simulation time 11824414989 ps
CPU time 256.64 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206876 kb
Host smart-4dbd4be6-8f0e-4fe6-b5f0-b63f90e73b83
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3865902417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rand_suspends.3865902417
Directory /workspace/0.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/0.usbdev_random_length_in_transaction.1778246819
Short name T917
Test name
Test status
Simulation time 178645296 ps
CPU time 0.8 seconds
Started Jul 22 05:56:11 PM PDT 24
Finished Jul 22 05:56:12 PM PDT 24
Peak memory 206700 kb
Host smart-8f56f79e-25ce-4ad4-9baa-3122194cd306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17782
46819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_in_transaction.1778246819
Directory /workspace/0.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/0.usbdev_random_length_out_transaction.1076984771
Short name T337
Test name
Test status
Simulation time 191436604 ps
CPU time 0.87 seconds
Started Jul 22 05:56:08 PM PDT 24
Finished Jul 22 05:56:10 PM PDT 24
Peak memory 206724 kb
Host smart-0dbf509d-d99f-4cba-a389-efd90a325cec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10769
84771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_random_length_out_transaction.1076984771
Directory /workspace/0.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/0.usbdev_rx_crc_err.4166619130
Short name T2293
Test name
Test status
Simulation time 231420951 ps
CPU time 0.88 seconds
Started Jul 22 05:56:23 PM PDT 24
Finished Jul 22 05:56:24 PM PDT 24
Peak memory 206760 kb
Host smart-836ec956-8b5d-43d5-804a-636e7164e070
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41666
19130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_rx_crc_err.4166619130
Directory /workspace/0.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/0.usbdev_setup_priority_over_stall_response.4291376294
Short name T2647
Test name
Test status
Simulation time 342647849 ps
CPU time 1.08 seconds
Started Jul 22 05:56:21 PM PDT 24
Finished Jul 22 05:56:23 PM PDT 24
Peak memory 206708 kb
Host smart-5bc35b85-622c-4159-9660-b9a8c2a610d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42913
76294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_priority_over_stall_response.4291376294
Directory /workspace/0.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/0.usbdev_setup_stage.2585504886
Short name T909
Test name
Test status
Simulation time 156426493 ps
CPU time 0.77 seconds
Started Jul 22 05:56:18 PM PDT 24
Finished Jul 22 05:56:20 PM PDT 24
Peak memory 206656 kb
Host smart-67498954-b87b-4b93-8b0c-dfddeefd1f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25855
04886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_stage.2585504886
Directory /workspace/0.usbdev_setup_stage/latest

Test location /workspace/coverage/default/0.usbdev_setup_trans_ignored.1130728808
Short name T2339
Test name
Test status
Simulation time 153126620 ps
CPU time 0.75 seconds
Started Jul 22 05:56:18 PM PDT 24
Finished Jul 22 05:56:20 PM PDT 24
Peak memory 206752 kb
Host smart-dec4e2cb-1aa7-4d08-9151-ad7f2dbe8d69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11307
28808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_setup_trans_ignored.1130728808
Directory /workspace/0.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/0.usbdev_smoke.2329071350
Short name T2288
Test name
Test status
Simulation time 242022917 ps
CPU time 1 seconds
Started Jul 22 05:56:20 PM PDT 24
Finished Jul 22 05:56:21 PM PDT 24
Peak memory 206728 kb
Host smart-2cdc0b44-a365-4a3e-a996-b160c1f97578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23290
71350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_smoke.2329071350
Directory /workspace/0.usbdev_smoke/latest

Test location /workspace/coverage/default/0.usbdev_spurious_pids_ignored.1966979311
Short name T1433
Test name
Test status
Simulation time 5299362585 ps
CPU time 143.4 seconds
Started Jul 22 05:56:22 PM PDT 24
Finished Jul 22 05:58:46 PM PDT 24
Peak memory 206824 kb
Host smart-40fe1399-7cdc-4284-9404-a6dcd7fa8cbf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1966979311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_spurious_pids_ignored.1966979311
Directory /workspace/0.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/0.usbdev_stall_priority_over_nak.3519950787
Short name T1294
Test name
Test status
Simulation time 186940651 ps
CPU time 0.8 seconds
Started Jul 22 05:56:18 PM PDT 24
Finished Jul 22 05:56:19 PM PDT 24
Peak memory 206712 kb
Host smart-f37e679b-6b78-42f2-8aaf-384aa3faeea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35199
50787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_priority_over_nak.3519950787
Directory /workspace/0.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/0.usbdev_stall_trans.2881511693
Short name T783
Test name
Test status
Simulation time 197471197 ps
CPU time 0.91 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 05:56:21 PM PDT 24
Peak memory 206744 kb
Host smart-d8437299-3e04-495c-91f7-9cbe083fc7fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28815
11693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stall_trans.2881511693
Directory /workspace/0.usbdev_stall_trans/latest

Test location /workspace/coverage/default/0.usbdev_stream_len_max.1943706146
Short name T1401
Test name
Test status
Simulation time 383681511 ps
CPU time 1.25 seconds
Started Jul 22 05:56:17 PM PDT 24
Finished Jul 22 05:56:18 PM PDT 24
Peak memory 206748 kb
Host smart-5d232d0e-46df-46ed-9def-df025fdd218f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19437
06146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stream_len_max.1943706146
Directory /workspace/0.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/0.usbdev_streaming_out.1026676275
Short name T1189
Test name
Test status
Simulation time 4978507636 ps
CPU time 142.99 seconds
Started Jul 22 05:56:23 PM PDT 24
Finished Jul 22 05:58:46 PM PDT 24
Peak memory 206912 kb
Host smart-6e3e8438-59d7-4e5d-bb96-c0336098698d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
76275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_streaming_out.1026676275
Directory /workspace/0.usbdev_streaming_out/latest

Test location /workspace/coverage/default/0.usbdev_stress_usb_traffic.2329938572
Short name T2095
Test name
Test status
Simulation time 12151831958 ps
CPU time 244.92 seconds
Started Jul 22 05:56:17 PM PDT 24
Finished Jul 22 06:00:23 PM PDT 24
Peak memory 207020 kb
Host smart-1dfabc47-d585-48ab-bcb9-747b996d74b7
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2329938572 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.usbdev_stress_usb_traffic.2329938572
Directory /workspace/0.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_alert_test.711147636
Short name T812
Test name
Test status
Simulation time 32471685 ps
CPU time 0.65 seconds
Started Jul 22 05:56:31 PM PDT 24
Finished Jul 22 05:56:32 PM PDT 24
Peak memory 206416 kb
Host smart-65e1d233-a287-4ff2-b99a-3c5ea9397828
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=711147636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_alert_test.711147636
Directory /workspace/1.usbdev_alert_test/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_disconnect.1577370021
Short name T2478
Test name
Test status
Simulation time 3619138653 ps
CPU time 4.01 seconds
Started Jul 22 05:56:17 PM PDT 24
Finished Jul 22 05:56:22 PM PDT 24
Peak memory 206960 kb
Host smart-8bbdb54e-2b86-46c0-8cbf-50db36de8605
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1577370021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_disconnect.1577370021
Directory /workspace/1.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_reset.1202463484
Short name T2156
Test name
Test status
Simulation time 13356217050 ps
CPU time 12.35 seconds
Started Jul 22 05:56:22 PM PDT 24
Finished Jul 22 05:56:35 PM PDT 24
Peak memory 206740 kb
Host smart-4425dd64-284f-4be3-8f8f-f872d162ad7e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1202463484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_reset.1202463484
Directory /workspace/1.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/1.usbdev_aon_wake_resume.1486218238
Short name T2191
Test name
Test status
Simulation time 23402551900 ps
CPU time 23.18 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 05:56:42 PM PDT 24
Peak memory 206808 kb
Host smart-5705f500-5c6e-47ae-919f-cb65f32d3fd4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1486218238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_aon_wake_resume.1486218238
Directory /workspace/1.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/1.usbdev_av_buffer.295347794
Short name T1748
Test name
Test status
Simulation time 152206851 ps
CPU time 0.79 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206748 kb
Host smart-34d82c76-d6d1-4ac1-b6db-27fbda4096cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29534
7794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_buffer.295347794
Directory /workspace/1.usbdev_av_buffer/latest

Test location /workspace/coverage/default/1.usbdev_av_empty.517735145
Short name T60
Test name
Test status
Simulation time 178691143 ps
CPU time 0.8 seconds
Started Jul 22 05:56:23 PM PDT 24
Finished Jul 22 05:56:24 PM PDT 24
Peak memory 206748 kb
Host smart-5a52472e-95f5-42fd-bf90-f390c04f7c53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51773
5145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_av_empty.517735145
Directory /workspace/1.usbdev_av_empty/latest

Test location /workspace/coverage/default/1.usbdev_bitstuff_err.3271019258
Short name T1223
Test name
Test status
Simulation time 157766511 ps
CPU time 0.79 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 05:56:20 PM PDT 24
Peak memory 206732 kb
Host smart-edb865bc-9da0-4d09-8b67-7dfc8df027ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32710
19258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_bitstuff_err.3271019258
Directory /workspace/1.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_clear.345777738
Short name T2736
Test name
Test status
Simulation time 287278621 ps
CPU time 1.03 seconds
Started Jul 22 05:56:20 PM PDT 24
Finished Jul 22 05:56:22 PM PDT 24
Peak memory 206752 kb
Host smart-c68c699e-05f4-4102-841c-fe1c499362bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34577
7738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_clear.345777738
Directory /workspace/1.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/1.usbdev_data_toggle_restore.4110948053
Short name T1168
Test name
Test status
Simulation time 1087415319 ps
CPU time 2.79 seconds
Started Jul 22 05:56:22 PM PDT 24
Finished Jul 22 05:56:26 PM PDT 24
Peak memory 206840 kb
Host smart-80e827d4-6f31-49e7-a477-1bd110f7bb9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
48053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_data_toggle_restore.4110948053
Directory /workspace/1.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/1.usbdev_device_address.1971276330
Short name T160
Test name
Test status
Simulation time 17727124566 ps
CPU time 36.27 seconds
Started Jul 22 05:56:21 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206964 kb
Host smart-6ae5a26d-6eea-4f54-a885-cb99d27d5aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19712
76330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_device_address.1971276330
Directory /workspace/1.usbdev_device_address/latest

Test location /workspace/coverage/default/1.usbdev_disable_endpoint.1581654803
Short name T986
Test name
Test status
Simulation time 336102785 ps
CPU time 1.24 seconds
Started Jul 22 05:58:08 PM PDT 24
Finished Jul 22 05:58:10 PM PDT 24
Peak memory 206748 kb
Host smart-af5d1fb7-cd15-41db-bb1b-1254c9eb9d79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15816
54803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disable_endpoint.1581654803
Directory /workspace/1.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/1.usbdev_disconnected.2103811540
Short name T1190
Test name
Test status
Simulation time 151590666 ps
CPU time 0.75 seconds
Started Jul 22 05:56:18 PM PDT 24
Finished Jul 22 05:56:19 PM PDT 24
Peak memory 206744 kb
Host smart-b6c25d34-3dac-48ba-86cb-dd5f6dab095f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21038
11540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_disconnected.2103811540
Directory /workspace/1.usbdev_disconnected/latest

Test location /workspace/coverage/default/1.usbdev_enable.3483820914
Short name T864
Test name
Test status
Simulation time 36644329 ps
CPU time 0.64 seconds
Started Jul 22 05:56:23 PM PDT 24
Finished Jul 22 05:56:24 PM PDT 24
Peak memory 206740 kb
Host smart-24ffcd1d-f335-4795-b5c5-2172698609a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34838
20914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_enable.3483820914
Directory /workspace/1.usbdev_enable/latest

Test location /workspace/coverage/default/1.usbdev_endpoint_access.1837531170
Short name T2447
Test name
Test status
Simulation time 878516451 ps
CPU time 2.13 seconds
Started Jul 22 05:56:17 PM PDT 24
Finished Jul 22 05:56:19 PM PDT 24
Peak memory 206884 kb
Host smart-7a64e591-eb4f-42ea-9ead-82cda5df0673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18375
31170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_endpoint_access.1837531170
Directory /workspace/1.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk.3105089121
Short name T1987
Test name
Test status
Simulation time 91177083078 ps
CPU time 115.28 seconds
Started Jul 22 05:58:08 PM PDT 24
Finished Jul 22 06:00:04 PM PDT 24
Peak memory 206936 kb
Host smart-09b16e30-394e-4012-b847-9729990f5dcd
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3105089121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk.3105089121
Directory /workspace/1.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_hiclk_max.3177547052
Short name T1422
Test name
Test status
Simulation time 92279255316 ps
CPU time 152.76 seconds
Started Jul 22 05:56:16 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 207124 kb
Host smart-0f8b4bf3-8900-46d5-a147-b8271d7b944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177547052 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_hiclk_max.3177547052
Directory /workspace/1.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk.2119216217
Short name T2666
Test name
Test status
Simulation time 112087734633 ps
CPU time 139.82 seconds
Started Jul 22 05:56:20 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206948 kb
Host smart-72cc137d-a62c-469e-9e4a-b2245cb11f87
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2119216217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk.2119216217
Directory /workspace/1.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/1.usbdev_freq_loclk_max.1621434697
Short name T415
Test name
Test status
Simulation time 81150119926 ps
CPU time 106.68 seconds
Started Jul 22 05:56:19 PM PDT 24
Finished Jul 22 05:58:06 PM PDT 24
Peak memory 206956 kb
Host smart-5e1b0270-f745-4970-b5c7-6fd374f758a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621434697 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_loclk_max.1621434697
Directory /workspace/1.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/1.usbdev_freq_phase.4223779993
Short name T218
Test name
Test status
Simulation time 84136086272 ps
CPU time 123.66 seconds
Started Jul 22 05:56:28 PM PDT 24
Finished Jul 22 05:58:32 PM PDT 24
Peak memory 206912 kb
Host smart-4b871380-b563-48a6-b941-2824330d65fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42237
79993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_freq_phase.4223779993
Directory /workspace/1.usbdev_freq_phase/latest

Test location /workspace/coverage/default/1.usbdev_in_iso.723215768
Short name T930
Test name
Test status
Simulation time 194749162 ps
CPU time 0.93 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:56:42 PM PDT 24
Peak memory 206780 kb
Host smart-f3d4b14a-0cc7-45a5-ba62-a395505b07be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72321
5768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_iso.723215768
Directory /workspace/1.usbdev_in_iso/latest

Test location /workspace/coverage/default/1.usbdev_in_stall.3428445393
Short name T1054
Test name
Test status
Simulation time 141130858 ps
CPU time 0.79 seconds
Started Jul 22 05:56:27 PM PDT 24
Finished Jul 22 05:56:29 PM PDT 24
Peak memory 206728 kb
Host smart-bab93cff-7e32-47d8-9f98-737d3c2a7171
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34284
45393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_stall.3428445393
Directory /workspace/1.usbdev_in_stall/latest

Test location /workspace/coverage/default/1.usbdev_in_trans.2097601111
Short name T1472
Test name
Test status
Simulation time 174636564 ps
CPU time 0.83 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:56:42 PM PDT 24
Peak memory 206712 kb
Host smart-57bc6a02-307a-4626-975d-10f4170d800f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20976
01111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_in_trans.2097601111
Directory /workspace/1.usbdev_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_invalid_sync.766821662
Short name T2391
Test name
Test status
Simulation time 7436322043 ps
CPU time 66.89 seconds
Started Jul 22 05:56:32 PM PDT 24
Finished Jul 22 05:57:39 PM PDT 24
Peak memory 206920 kb
Host smart-3540b2a1-1549-4024-9eca-a5db6d23cdb5
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=766821662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_invalid_sync.766821662
Directory /workspace/1.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/1.usbdev_iso_retraction.3439868897
Short name T91
Test name
Test status
Simulation time 8044375749 ps
CPU time 23.99 seconds
Started Jul 22 05:56:36 PM PDT 24
Finished Jul 22 05:57:00 PM PDT 24
Peak memory 206900 kb
Host smart-8f640921-aa16-4211-8c98-39043a2488bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34398
68897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_iso_retraction.3439868897
Directory /workspace/1.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/1.usbdev_link_in_err.580421424
Short name T1577
Test name
Test status
Simulation time 212822056 ps
CPU time 0.82 seconds
Started Jul 22 05:56:36 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206772 kb
Host smart-3ac731ad-86de-4ea2-b588-8a9dc1cbf39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58042
1424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_in_err.580421424
Directory /workspace/1.usbdev_link_in_err/latest

Test location /workspace/coverage/default/1.usbdev_link_resume.2909036259
Short name T1866
Test name
Test status
Simulation time 23402881623 ps
CPU time 22.88 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:57:02 PM PDT 24
Peak memory 206800 kb
Host smart-491ae6bf-95f5-4729-857b-e0d74a13ead4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29090
36259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_resume.2909036259
Directory /workspace/1.usbdev_link_resume/latest

Test location /workspace/coverage/default/1.usbdev_link_suspend.494299200
Short name T1744
Test name
Test status
Simulation time 3393496644 ps
CPU time 4.1 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:42 PM PDT 24
Peak memory 206768 kb
Host smart-934f6d2f-575a-46e9-b574-87715689aadb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49429
9200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_link_suspend.494299200
Directory /workspace/1.usbdev_link_suspend/latest

Test location /workspace/coverage/default/1.usbdev_low_speed_traffic.1832373651
Short name T695
Test name
Test status
Simulation time 9519024037 ps
CPU time 95.29 seconds
Started Jul 22 05:56:33 PM PDT 24
Finished Jul 22 05:58:09 PM PDT 24
Peak memory 206960 kb
Host smart-f5c4dcaf-c5aa-4b80-a663-3177b5cda61f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18323
73651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_low_speed_traffic.1832373651
Directory /workspace/1.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/1.usbdev_max_inter_pkt_delay.2268845657
Short name T653
Test name
Test status
Simulation time 5087352522 ps
CPU time 46.76 seconds
Started Jul 22 05:56:31 PM PDT 24
Finished Jul 22 05:57:18 PM PDT 24
Peak memory 206544 kb
Host smart-a45bbffc-7b44-4624-a562-a9536f20e32c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2268845657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_inter_pkt_delay.2268845657
Directory /workspace/1.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/1.usbdev_max_length_in_transaction.618154962
Short name T1566
Test name
Test status
Simulation time 247612028 ps
CPU time 0.92 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:43 PM PDT 24
Peak memory 206732 kb
Host smart-2134bc16-b40e-4006-bda9-d7edfab0e9ca
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=618154962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_in_transaction.618154962
Directory /workspace/1.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_length_out_transaction.2799678506
Short name T318
Test name
Test status
Simulation time 184504367 ps
CPU time 0.81 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206752 kb
Host smart-b8865ece-8054-4af1-8325-5005be12bb17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27996
78506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_length_out_transaction.2799678506
Directory /workspace/1.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_max_usb_traffic.2564115386
Short name T2697
Test name
Test status
Simulation time 4117865236 ps
CPU time 38.95 seconds
Started Jul 22 05:56:27 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206924 kb
Host smart-96a9ea59-2db4-4fd3-bd38-2a605c7b71d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25641
15386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_max_usb_traffic.2564115386
Directory /workspace/1.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/1.usbdev_min_length_in_transaction.3667352808
Short name T386
Test name
Test status
Simulation time 171994065 ps
CPU time 0.81 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206736 kb
Host smart-42e63a96-b40b-4c25-ae83-2dfbbcbda1e3
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3667352808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_in_transaction.3667352808
Directory /workspace/1.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_min_length_out_transaction.325185357
Short name T2140
Test name
Test status
Simulation time 145543119 ps
CPU time 0.86 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:56:37 PM PDT 24
Peak memory 206724 kb
Host smart-36aae945-fa5d-4473-bca6-dade32e727e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32518
5357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_min_length_out_transaction.325185357
Directory /workspace/1.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_out_iso.1760646956
Short name T1151
Test name
Test status
Simulation time 177825880 ps
CPU time 0.91 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206704 kb
Host smart-ec7c05a6-892d-447c-bdc3-6968be07a1ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
46956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_iso.1760646956
Directory /workspace/1.usbdev_out_iso/latest

Test location /workspace/coverage/default/1.usbdev_out_stall.720756262
Short name T2238
Test name
Test status
Simulation time 197911223 ps
CPU time 0.81 seconds
Started Jul 22 05:56:31 PM PDT 24
Finished Jul 22 05:56:32 PM PDT 24
Peak memory 206692 kb
Host smart-93617fe1-b17a-4672-a5fd-afa5ccbe97d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72075
6262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_stall.720756262
Directory /workspace/1.usbdev_out_stall/latest

Test location /workspace/coverage/default/1.usbdev_out_trans_nak.3733048471
Short name T1331
Test name
Test status
Simulation time 214099073 ps
CPU time 0.8 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:56:43 PM PDT 24
Peak memory 206724 kb
Host smart-eb6ae59a-dcad-4bfd-bdb0-480777c3322d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37330
48471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_out_trans_nak.3733048471
Directory /workspace/1.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/1.usbdev_pending_in_trans.1542773981
Short name T2533
Test name
Test status
Simulation time 150143025 ps
CPU time 0.77 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206708 kb
Host smart-8fa8851f-015e-4a77-9b0d-04c692c849ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15427
73981 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pending_in_trans.1542773981
Directory /workspace/1.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_pinflip.2872203695
Short name T521
Test name
Test status
Simulation time 264803563 ps
CPU time 1.04 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:56:40 PM PDT 24
Peak memory 206760 kb
Host smart-35a1868d-b1dc-478d-9d6b-60dd54cf9b3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2872203695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_pinflip.2872203695
Directory /workspace/1.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/1.usbdev_phy_config_rand_bus_type.885816797
Short name T2379
Test name
Test status
Simulation time 236488504 ps
CPU time 0.99 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:56:31 PM PDT 24
Peak memory 206696 kb
Host smart-a416d0c4-2e11-4a23-a6ba-849cd7caf846
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88581
6797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_config_rand_bus_type.885816797
Directory /workspace/1.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/1.usbdev_phy_pins_sense.550196568
Short name T1100
Test name
Test status
Simulation time 49044409 ps
CPU time 0.65 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:43 PM PDT 24
Peak memory 206712 kb
Host smart-5506b451-43a7-4646-981e-1083d4888f70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55019
6568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_phy_pins_sense.550196568
Directory /workspace/1.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/1.usbdev_pkt_buffer.4126536406
Short name T2546
Test name
Test status
Simulation time 14532930076 ps
CPU time 31.69 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:57:01 PM PDT 24
Peak memory 206996 kb
Host smart-b934c8ad-8ac8-43a9-870b-e5976219895c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41265
36406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_buffer.4126536406
Directory /workspace/1.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/1.usbdev_pkt_received.3909842512
Short name T847
Test name
Test status
Simulation time 218223545 ps
CPU time 0.92 seconds
Started Jul 22 05:56:27 PM PDT 24
Finished Jul 22 05:56:28 PM PDT 24
Peak memory 206688 kb
Host smart-1d8b1e97-22ad-41b9-b8d9-ca9b1338a67d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39098
42512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_received.3909842512
Directory /workspace/1.usbdev_pkt_received/latest

Test location /workspace/coverage/default/1.usbdev_pkt_sent.165474125
Short name T1106
Test name
Test status
Simulation time 307465688 ps
CPU time 1.02 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206688 kb
Host smart-dbef97af-d2a3-40e1-bae4-fdba0c5ca6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16547
4125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_pkt_sent.165474125
Directory /workspace/1.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_disconnects.2488927654
Short name T2649
Test name
Test status
Simulation time 11841266764 ps
CPU time 77.55 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:57:47 PM PDT 24
Peak memory 206896 kb
Host smart-64f4ba92-2c31-49bf-8121-eba4f37d7cd9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2488927654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_disconnects.2488927654
Directory /workspace/1.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/1.usbdev_rand_bus_resets.2186665403
Short name T1931
Test name
Test status
Simulation time 11563105857 ps
CPU time 71.58 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:57:53 PM PDT 24
Peak memory 206852 kb
Host smart-aa9265b9-f6cf-44a2-be5f-da98437a9410
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2186665403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_bus_resets.2186665403
Directory /workspace/1.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/1.usbdev_rand_suspends.3346169804
Short name T1363
Test name
Test status
Simulation time 11649405098 ps
CPU time 212.09 seconds
Started Jul 22 05:56:34 PM PDT 24
Finished Jul 22 06:00:07 PM PDT 24
Peak memory 206820 kb
Host smart-96be9c3d-95f5-4dc0-949d-e0aa87bb7d30
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3346169804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rand_suspends.3346169804
Directory /workspace/1.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/1.usbdev_random_length_in_transaction.118536319
Short name T1046
Test name
Test status
Simulation time 170900427 ps
CPU time 0.8 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:39 PM PDT 24
Peak memory 206772 kb
Host smart-ff5cf37e-e081-4d64-be23-ca215f73958b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11853
6319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_in_transaction.118536319
Directory /workspace/1.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/1.usbdev_random_length_out_transaction.982913681
Short name T2269
Test name
Test status
Simulation time 197702873 ps
CPU time 0.85 seconds
Started Jul 22 05:56:24 PM PDT 24
Finished Jul 22 05:56:25 PM PDT 24
Peak memory 206744 kb
Host smart-04d35faf-5422-4338-a174-c292fac16af9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98291
3681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_random_length_out_transaction.982913681
Directory /workspace/1.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/1.usbdev_rx_crc_err.592971137
Short name T505
Test name
Test status
Simulation time 167105199 ps
CPU time 0.8 seconds
Started Jul 22 05:56:27 PM PDT 24
Finished Jul 22 05:56:28 PM PDT 24
Peak memory 206696 kb
Host smart-ffce7239-79d7-40b4-ab2b-28d8c819b54c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59297
1137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_crc_err.592971137
Directory /workspace/1.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/1.usbdev_rx_pid_err.3748965615
Short name T39
Test name
Test status
Simulation time 175748706 ps
CPU time 0.79 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206712 kb
Host smart-7e5ab790-5d79-40e2-b2a0-7aabd96b64f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37489
65615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_rx_pid_err.3748965615
Directory /workspace/1.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/1.usbdev_sec_cm.811290324
Short name T206
Test name
Test status
Simulation time 523432991 ps
CPU time 1.5 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:56:31 PM PDT 24
Peak memory 224424 kb
Host smart-e9fdd36d-812b-4009-9d7f-9add392d8e8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=811290324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_sec_cm.811290324
Directory /workspace/1.usbdev_sec_cm/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority.1376802987
Short name T62
Test name
Test status
Simulation time 419880097 ps
CPU time 1.38 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:56:31 PM PDT 24
Peak memory 206632 kb
Host smart-615c761b-cd9f-49ca-a06f-ed1692143853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13768
02987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority.1376802987
Directory /workspace/1.usbdev_setup_priority/latest

Test location /workspace/coverage/default/1.usbdev_setup_priority_over_stall_response.564178345
Short name T1980
Test name
Test status
Simulation time 161590141 ps
CPU time 0.83 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 05:56:40 PM PDT 24
Peak memory 206804 kb
Host smart-d769889c-755d-4d84-bad3-5d8be7e2073d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56417
8345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_priority_over_stall_response.564178345
Directory /workspace/1.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/1.usbdev_setup_stage.497894983
Short name T989
Test name
Test status
Simulation time 152064414 ps
CPU time 0.8 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:56:40 PM PDT 24
Peak memory 206804 kb
Host smart-eaf59e90-d24a-4304-9a98-fb5035ee0410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49789
4983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_stage.497894983
Directory /workspace/1.usbdev_setup_stage/latest

Test location /workspace/coverage/default/1.usbdev_setup_trans_ignored.1262039977
Short name T2124
Test name
Test status
Simulation time 172674359 ps
CPU time 0.8 seconds
Started Jul 22 05:56:28 PM PDT 24
Finished Jul 22 05:56:30 PM PDT 24
Peak memory 206732 kb
Host smart-b2b034a4-6d34-478d-9abc-a2e17ab7181d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12620
39977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_setup_trans_ignored.1262039977
Directory /workspace/1.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/1.usbdev_smoke.3771018273
Short name T1740
Test name
Test status
Simulation time 228307942 ps
CPU time 0.93 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:56:30 PM PDT 24
Peak memory 206624 kb
Host smart-7cc307d2-de53-462b-83e4-3797e172149f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37710
18273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_smoke.3771018273
Directory /workspace/1.usbdev_smoke/latest

Test location /workspace/coverage/default/1.usbdev_spurious_pids_ignored.453756659
Short name T2190
Test name
Test status
Simulation time 3816379598 ps
CPU time 27.06 seconds
Started Jul 22 05:56:32 PM PDT 24
Finished Jul 22 05:56:59 PM PDT 24
Peak memory 206932 kb
Host smart-38438080-b0dd-41e5-9113-ddfa0a73efcb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=453756659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_spurious_pids_ignored.453756659
Directory /workspace/1.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/1.usbdev_stall_priority_over_nak.99980676
Short name T2291
Test name
Test status
Simulation time 180629195 ps
CPU time 0.82 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206804 kb
Host smart-6753886d-3600-4746-a7e6-43cc69609a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99980
676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_priority_over_nak.99980676
Directory /workspace/1.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/1.usbdev_stall_trans.1530349349
Short name T2692
Test name
Test status
Simulation time 165951892 ps
CPU time 0.82 seconds
Started Jul 22 05:56:36 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206736 kb
Host smart-d2f9e8d9-f317-464f-9a67-7fefe2d8f6d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15303
49349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stall_trans.1530349349
Directory /workspace/1.usbdev_stall_trans/latest

Test location /workspace/coverage/default/1.usbdev_stream_len_max.449236280
Short name T2179
Test name
Test status
Simulation time 437297498 ps
CPU time 1.3 seconds
Started Jul 22 05:56:28 PM PDT 24
Finished Jul 22 05:56:30 PM PDT 24
Peak memory 206704 kb
Host smart-f389153c-d0fd-475e-b8ed-10255a382230
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44923
6280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_stream_len_max.449236280
Directory /workspace/1.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/1.usbdev_streaming_out.1720075408
Short name T707
Test name
Test status
Simulation time 5065049725 ps
CPU time 143.87 seconds
Started Jul 22 05:56:28 PM PDT 24
Finished Jul 22 05:58:52 PM PDT 24
Peak memory 206912 kb
Host smart-86ad5f2f-ebad-4599-b29d-82759e46e09f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17200
75408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.usbdev_streaming_out.1720075408
Directory /workspace/1.usbdev_streaming_out/latest

Test location /workspace/coverage/default/10.usbdev_alert_test.509237775
Short name T1440
Test name
Test status
Simulation time 36850413 ps
CPU time 0.67 seconds
Started Jul 22 05:59:16 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206716 kb
Host smart-040a9e7f-19fc-468d-b557-06a7d136da31
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=509237775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_alert_test.509237775
Directory /workspace/10.usbdev_alert_test/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_disconnect.1000273931
Short name T2615
Test name
Test status
Simulation time 3716303464 ps
CPU time 5.08 seconds
Started Jul 22 05:57:53 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206732 kb
Host smart-4fdd7c6c-b2ee-4239-b9d2-509aa39bf510
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1000273931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_disconnect.1000273931
Directory /workspace/10.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_reset.1581140237
Short name T503
Test name
Test status
Simulation time 13338863409 ps
CPU time 12.46 seconds
Started Jul 22 05:57:53 PM PDT 24
Finished Jul 22 05:58:06 PM PDT 24
Peak memory 206816 kb
Host smart-5d2bb4ec-9149-43af-a7d7-822aadc45011
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1581140237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_reset.1581140237
Directory /workspace/10.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/10.usbdev_aon_wake_resume.1724279508
Short name T1758
Test name
Test status
Simulation time 23372305524 ps
CPU time 22.1 seconds
Started Jul 22 05:57:53 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206732 kb
Host smart-d160704e-fc91-4959-87c9-f3e1fb27376e
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1724279508 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_aon_wake_resume.1724279508
Directory /workspace/10.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/10.usbdev_av_buffer.3624677925
Short name T145
Test name
Test status
Simulation time 148540254 ps
CPU time 0.8 seconds
Started Jul 22 05:57:44 PM PDT 24
Finished Jul 22 05:57:47 PM PDT 24
Peak memory 206744 kb
Host smart-9617fa4c-5286-4505-89f7-cbcabeea6576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36246
77925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_av_buffer.3624677925
Directory /workspace/10.usbdev_av_buffer/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_clear.694589214
Short name T1861
Test name
Test status
Simulation time 463223715 ps
CPU time 1.32 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206724 kb
Host smart-87b4bd8c-dc4e-4f14-9ff4-b5f2fe42a125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69458
9214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_clear.694589214
Directory /workspace/10.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/10.usbdev_data_toggle_restore.824785566
Short name T831
Test name
Test status
Simulation time 1346703435 ps
CPU time 3.11 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:57:54 PM PDT 24
Peak memory 206852 kb
Host smart-9b498a8c-350e-4812-9ba3-da107ee3446e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82478
5566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_data_toggle_restore.824785566
Directory /workspace/10.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/10.usbdev_device_address.1307037375
Short name T1640
Test name
Test status
Simulation time 11454417687 ps
CPU time 20.98 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:58:12 PM PDT 24
Peak memory 206920 kb
Host smart-33a1e897-f561-496f-b284-29040abb6fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13070
37375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_device_address.1307037375
Directory /workspace/10.usbdev_device_address/latest

Test location /workspace/coverage/default/10.usbdev_disable_endpoint.3520277079
Short name T869
Test name
Test status
Simulation time 347442594 ps
CPU time 1.08 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206672 kb
Host smart-b86fbb1d-3b3f-43cd-8ee5-8a3b7dfa002d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35202
77079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disable_endpoint.3520277079
Directory /workspace/10.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/10.usbdev_disconnected.3674274218
Short name T1158
Test name
Test status
Simulation time 144688711 ps
CPU time 0.72 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206672 kb
Host smart-8506dfa9-4c6d-4fda-a0e6-c9518b2060d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36742
74218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_disconnected.3674274218
Directory /workspace/10.usbdev_disconnected/latest

Test location /workspace/coverage/default/10.usbdev_enable.352701753
Short name T227
Test name
Test status
Simulation time 38198753 ps
CPU time 0.66 seconds
Started Jul 22 05:57:50 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206724 kb
Host smart-ae45770d-6585-4654-b096-e4ce4bcf4869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35270
1753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_enable.352701753
Directory /workspace/10.usbdev_enable/latest

Test location /workspace/coverage/default/10.usbdev_endpoint_access.3828033417
Short name T2081
Test name
Test status
Simulation time 1067096690 ps
CPU time 2.43 seconds
Started Jul 22 05:57:53 PM PDT 24
Finished Jul 22 05:57:57 PM PDT 24
Peak memory 206796 kb
Host smart-84f6fb94-ad72-40ff-97d1-fd5dad47e435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38280
33417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_endpoint_access.3828033417
Directory /workspace/10.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/10.usbdev_fifo_rst.57060717
Short name T862
Test name
Test status
Simulation time 218020660 ps
CPU time 1.93 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206760 kb
Host smart-bd7a0ce4-80ce-4a95-92a3-f52ff90cd988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57060
717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_fifo_rst.57060717
Directory /workspace/10.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/10.usbdev_in_iso.2317357427
Short name T1567
Test name
Test status
Simulation time 165446316 ps
CPU time 0.79 seconds
Started Jul 22 05:57:57 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206692 kb
Host smart-c985ce70-ecea-40a9-b38f-3814c3ee64dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23173
57427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_iso.2317357427
Directory /workspace/10.usbdev_in_iso/latest

Test location /workspace/coverage/default/10.usbdev_in_stall.3236651539
Short name T2160
Test name
Test status
Simulation time 160621870 ps
CPU time 0.8 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206732 kb
Host smart-291cc4c6-bf66-4351-a9a2-6382183cc53e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32366
51539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_stall.3236651539
Directory /workspace/10.usbdev_in_stall/latest

Test location /workspace/coverage/default/10.usbdev_in_trans.972291577
Short name T859
Test name
Test status
Simulation time 224963554 ps
CPU time 0.87 seconds
Started Jul 22 05:58:01 PM PDT 24
Finished Jul 22 05:58:02 PM PDT 24
Peak memory 206732 kb
Host smart-b09e20fe-4fe9-4c77-8227-bb2e491b9d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97229
1577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_in_trans.972291577
Directory /workspace/10.usbdev_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_invalid_sync.1190126370
Short name T683
Test name
Test status
Simulation time 9796827746 ps
CPU time 92.1 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:59:29 PM PDT 24
Peak memory 206804 kb
Host smart-79ca7146-7196-488a-9f89-de6bdacee6fb
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1190126370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_invalid_sync.1190126370
Directory /workspace/10.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/10.usbdev_link_in_err.2366732106
Short name T795
Test name
Test status
Simulation time 273059260 ps
CPU time 0.98 seconds
Started Jul 22 05:57:59 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206728 kb
Host smart-6add9993-5885-4c60-afc4-8f3d3f789a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23667
32106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_in_err.2366732106
Directory /workspace/10.usbdev_link_in_err/latest

Test location /workspace/coverage/default/10.usbdev_link_resume.3556506418
Short name T2626
Test name
Test status
Simulation time 23345129583 ps
CPU time 23.54 seconds
Started Jul 22 05:57:57 PM PDT 24
Finished Jul 22 05:58:22 PM PDT 24
Peak memory 206800 kb
Host smart-58606a02-3a76-450d-971c-ea7f854903a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35565
06418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_resume.3556506418
Directory /workspace/10.usbdev_link_resume/latest

Test location /workspace/coverage/default/10.usbdev_link_suspend.1992969997
Short name T1080
Test name
Test status
Simulation time 3315456650 ps
CPU time 4.04 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:58:02 PM PDT 24
Peak memory 206816 kb
Host smart-fada680c-fc8f-479c-815f-2074f0021f86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19929
69997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_link_suspend.1992969997
Directory /workspace/10.usbdev_link_suspend/latest

Test location /workspace/coverage/default/10.usbdev_low_speed_traffic.2476873986
Short name T2389
Test name
Test status
Simulation time 6185619776 ps
CPU time 43.54 seconds
Started Jul 22 05:57:58 PM PDT 24
Finished Jul 22 05:58:42 PM PDT 24
Peak memory 206952 kb
Host smart-232eeb9d-3571-4bc1-8e83-4f81c5689938
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24768
73986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_low_speed_traffic.2476873986
Directory /workspace/10.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/10.usbdev_max_inter_pkt_delay.3028999369
Short name T953
Test name
Test status
Simulation time 5428689827 ps
CPU time 51.33 seconds
Started Jul 22 05:57:57 PM PDT 24
Finished Jul 22 05:58:50 PM PDT 24
Peak memory 206892 kb
Host smart-08a022a8-5617-47fb-ab54-846d24fb1446
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3028999369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_inter_pkt_delay.3028999369
Directory /workspace/10.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_max_length_in_transaction.1662985926
Short name T474
Test name
Test status
Simulation time 247259606 ps
CPU time 0.95 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206748 kb
Host smart-7cb1fa8c-889f-4329-a523-3b4cecfdc952
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1662985926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_in_transaction.1662985926
Directory /workspace/10.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_length_out_transaction.1779401547
Short name T1607
Test name
Test status
Simulation time 202048062 ps
CPU time 0.85 seconds
Started Jul 22 05:57:54 PM PDT 24
Finished Jul 22 05:57:55 PM PDT 24
Peak memory 206748 kb
Host smart-9cad48de-addd-4a66-8fdd-9257d7d3cc88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17794
01547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_length_out_transaction.1779401547
Directory /workspace/10.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_max_usb_traffic.2845226365
Short name T2132
Test name
Test status
Simulation time 7010074848 ps
CPU time 48.69 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:58:46 PM PDT 24
Peak memory 206952 kb
Host smart-0c9a016a-df96-43d9-b2ab-175f3f0e9610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28452
26365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_max_usb_traffic.2845226365
Directory /workspace/10.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/10.usbdev_min_inter_pkt_delay.3711464308
Short name T452
Test name
Test status
Simulation time 6316820056 ps
CPU time 174.78 seconds
Started Jul 22 05:57:59 PM PDT 24
Finished Jul 22 06:00:54 PM PDT 24
Peak memory 206896 kb
Host smart-5b38a7a1-54b9-4984-a287-0418f85df188
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3711464308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_inter_pkt_delay.3711464308
Directory /workspace/10.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/10.usbdev_min_length_in_transaction.634955143
Short name T1466
Test name
Test status
Simulation time 146441360 ps
CPU time 0.79 seconds
Started Jul 22 05:57:59 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206732 kb
Host smart-2d565d66-cba2-473b-b2a0-bf4dd533297a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=634955143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_in_transaction.634955143
Directory /workspace/10.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_min_length_out_transaction.3325456219
Short name T2436
Test name
Test status
Simulation time 150292168 ps
CPU time 0.8 seconds
Started Jul 22 05:57:58 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206736 kb
Host smart-a73ac335-63fb-4cd8-88c6-bbd35e957f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33254
56219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_min_length_out_transaction.3325456219
Directory /workspace/10.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_out_iso.443664582
Short name T600
Test name
Test status
Simulation time 233050134 ps
CPU time 0.89 seconds
Started Jul 22 05:58:00 PM PDT 24
Finished Jul 22 05:58:01 PM PDT 24
Peak memory 206744 kb
Host smart-3cee761a-20ea-492d-b148-a7ae7ab05d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44366
4582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_iso.443664582
Directory /workspace/10.usbdev_out_iso/latest

Test location /workspace/coverage/default/10.usbdev_out_stall.2326526443
Short name T1839
Test name
Test status
Simulation time 177923536 ps
CPU time 0.83 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206692 kb
Host smart-e63e5b96-c1f2-423e-9835-80bf8a1710c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23265
26443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_stall.2326526443
Directory /workspace/10.usbdev_out_stall/latest

Test location /workspace/coverage/default/10.usbdev_out_trans_nak.325736520
Short name T1932
Test name
Test status
Simulation time 200693757 ps
CPU time 0.85 seconds
Started Jul 22 05:57:58 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206728 kb
Host smart-33f7517a-540c-4750-966e-d41f0acfa63e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32573
6520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_out_trans_nak.325736520
Directory /workspace/10.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/10.usbdev_pending_in_trans.392123099
Short name T1765
Test name
Test status
Simulation time 179733127 ps
CPU time 0.86 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206684 kb
Host smart-8e1f11a2-cc6d-4d1f-a939-d1d2c212cf76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39212
3099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pending_in_trans.392123099
Directory /workspace/10.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_pinflip.1011244042
Short name T2733
Test name
Test status
Simulation time 208696652 ps
CPU time 1.01 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206748 kb
Host smart-2fe12afe-141a-453b-96b2-635e9b427a44
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1011244042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_pinflip.1011244042
Directory /workspace/10.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/10.usbdev_phy_config_usb_ref_disable.3302826124
Short name T1602
Test name
Test status
Simulation time 141570161 ps
CPU time 0.74 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206752 kb
Host smart-0ba04ae1-3940-45a3-836c-5f3f1fa45128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33028
26124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_config_usb_ref_disable.3302826124
Directory /workspace/10.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/10.usbdev_phy_pins_sense.2495029412
Short name T2287
Test name
Test status
Simulation time 60245788 ps
CPU time 0.71 seconds
Started Jul 22 05:57:54 PM PDT 24
Finished Jul 22 05:57:56 PM PDT 24
Peak memory 206744 kb
Host smart-c3aaab62-17bc-4711-b41b-94a7498f792d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24950
29412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_phy_pins_sense.2495029412
Directory /workspace/10.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/10.usbdev_pkt_buffer.2818099726
Short name T238
Test name
Test status
Simulation time 15518753039 ps
CPU time 31.62 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:58:28 PM PDT 24
Peak memory 206940 kb
Host smart-dee83b81-0451-4782-a8c4-21ce3c300f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28180
99726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_buffer.2818099726
Directory /workspace/10.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/10.usbdev_pkt_received.3152928889
Short name T1232
Test name
Test status
Simulation time 208701882 ps
CPU time 0.86 seconds
Started Jul 22 05:57:54 PM PDT 24
Finished Jul 22 05:57:55 PM PDT 24
Peak memory 206788 kb
Host smart-1eedf005-db46-45c6-97af-a75ea3a616a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31529
28889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_received.3152928889
Directory /workspace/10.usbdev_pkt_received/latest

Test location /workspace/coverage/default/10.usbdev_pkt_sent.257412106
Short name T2415
Test name
Test status
Simulation time 174406280 ps
CPU time 0.81 seconds
Started Jul 22 05:57:57 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206664 kb
Host smart-b994b75e-ceb7-4e7f-b577-1f90cfefd0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25741
2106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_pkt_sent.257412106
Directory /workspace/10.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/10.usbdev_random_length_in_transaction.1573128734
Short name T661
Test name
Test status
Simulation time 209613878 ps
CPU time 0.86 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:57 PM PDT 24
Peak memory 206728 kb
Host smart-a42f20b1-e476-42aa-af01-9f75ac022a60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15731
28734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_in_transaction.1573128734
Directory /workspace/10.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/10.usbdev_random_length_out_transaction.3630248406
Short name T2107
Test name
Test status
Simulation time 216046757 ps
CPU time 0.81 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206708 kb
Host smart-8a24501d-b709-4f5e-88bb-176c14cb131f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36302
48406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_random_length_out_transaction.3630248406
Directory /workspace/10.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/10.usbdev_rx_crc_err.4065025040
Short name T1804
Test name
Test status
Simulation time 218850449 ps
CPU time 0.84 seconds
Started Jul 22 05:57:59 PM PDT 24
Finished Jul 22 05:58:01 PM PDT 24
Peak memory 206724 kb
Host smart-e8fb3a3a-f57d-4cb2-a0c6-be4d34cb83d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40650
25040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_rx_crc_err.4065025040
Directory /workspace/10.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/10.usbdev_setup_stage.2522462950
Short name T1781
Test name
Test status
Simulation time 151909696 ps
CPU time 0.75 seconds
Started Jul 22 05:57:59 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206748 kb
Host smart-cdae228b-9b08-4a76-a9f3-e4f7ca3ba888
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25224
62950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_stage.2522462950
Directory /workspace/10.usbdev_setup_stage/latest

Test location /workspace/coverage/default/10.usbdev_setup_trans_ignored.4119261940
Short name T977
Test name
Test status
Simulation time 146709330 ps
CPU time 0.78 seconds
Started Jul 22 05:58:01 PM PDT 24
Finished Jul 22 05:58:02 PM PDT 24
Peak memory 206724 kb
Host smart-3e279019-fc00-44e5-b8e3-76bf5d35214b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41192
61940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_setup_trans_ignored.4119261940
Directory /workspace/10.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/10.usbdev_smoke.1081978560
Short name T2354
Test name
Test status
Simulation time 211522362 ps
CPU time 0.88 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206664 kb
Host smart-469045b6-c713-4488-9d28-aca3c379562c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10819
78560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_smoke.1081978560
Directory /workspace/10.usbdev_smoke/latest

Test location /workspace/coverage/default/10.usbdev_spurious_pids_ignored.2480205805
Short name T570
Test name
Test status
Simulation time 6312972169 ps
CPU time 61.02 seconds
Started Jul 22 05:57:53 PM PDT 24
Finished Jul 22 05:58:55 PM PDT 24
Peak memory 206760 kb
Host smart-70164682-b769-4093-a057-6325e6d8fc7a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2480205805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_spurious_pids_ignored.2480205805
Directory /workspace/10.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/10.usbdev_stall_priority_over_nak.1930287569
Short name T2390
Test name
Test status
Simulation time 167899585 ps
CPU time 0.78 seconds
Started Jul 22 05:57:54 PM PDT 24
Finished Jul 22 05:57:55 PM PDT 24
Peak memory 206792 kb
Host smart-c69305bd-37b4-44d4-bab7-b69bddee91c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19302
87569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_priority_over_nak.1930287569
Directory /workspace/10.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/10.usbdev_stall_trans.1225183085
Short name T1515
Test name
Test status
Simulation time 142233213 ps
CPU time 0.77 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:57 PM PDT 24
Peak memory 206752 kb
Host smart-e51337cb-c2f2-4a52-aee7-456913aa3d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12251
83085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stall_trans.1225183085
Directory /workspace/10.usbdev_stall_trans/latest

Test location /workspace/coverage/default/10.usbdev_stream_len_max.350630995
Short name T582
Test name
Test status
Simulation time 755899133 ps
CPU time 1.71 seconds
Started Jul 22 05:58:05 PM PDT 24
Finished Jul 22 05:58:07 PM PDT 24
Peak memory 206900 kb
Host smart-99b641f1-248e-4b2a-9350-a4e88b2b0ebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35063
0995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_stream_len_max.350630995
Directory /workspace/10.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/10.usbdev_streaming_out.3622170990
Short name T1381
Test name
Test status
Simulation time 4404759632 ps
CPU time 39.4 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 05:58:42 PM PDT 24
Peak memory 206960 kb
Host smart-5ca284f9-c42c-4c4c-b776-fcbf0046b78b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36221
70990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.usbdev_streaming_out.3622170990
Directory /workspace/10.usbdev_streaming_out/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_disconnect.3659710826
Short name T744
Test name
Test status
Simulation time 4255044398 ps
CPU time 5.17 seconds
Started Jul 22 05:58:05 PM PDT 24
Finished Jul 22 05:58:11 PM PDT 24
Peak memory 206820 kb
Host smart-67114eb6-e51e-4ee4-82cb-144841c96bd2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3659710826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_disconnect.3659710826
Directory /workspace/11.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_reset.489291964
Short name T2485
Test name
Test status
Simulation time 13462046214 ps
CPU time 12.82 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206936 kb
Host smart-af0157e6-9d0f-42f7-bfe6-038fc015e56f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=489291964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_reset.489291964
Directory /workspace/11.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/11.usbdev_aon_wake_resume.1644900240
Short name T741
Test name
Test status
Simulation time 23360181649 ps
CPU time 24.66 seconds
Started Jul 22 05:58:07 PM PDT 24
Finished Jul 22 05:58:32 PM PDT 24
Peak memory 206776 kb
Host smart-a8a8e72a-85bf-4196-9484-cecab34887b0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1644900240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_aon_wake_resume.1644900240
Directory /workspace/11.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/11.usbdev_av_buffer.52957823
Short name T618
Test name
Test status
Simulation time 147938385 ps
CPU time 0.78 seconds
Started Jul 22 05:58:16 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206736 kb
Host smart-7c190058-f3d9-4df5-91ba-776c8458b48d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52957
823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_av_buffer.52957823
Directory /workspace/11.usbdev_av_buffer/latest

Test location /workspace/coverage/default/11.usbdev_bitstuff_err.3283350978
Short name T2185
Test name
Test status
Simulation time 170512648 ps
CPU time 0.77 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 05:58:05 PM PDT 24
Peak memory 206740 kb
Host smart-fb4333a4-ae29-4917-8fcc-2df7a8248292
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32833
50978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_bitstuff_err.3283350978
Directory /workspace/11.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_clear.3043112993
Short name T622
Test name
Test status
Simulation time 584148428 ps
CPU time 1.58 seconds
Started Jul 22 05:58:05 PM PDT 24
Finished Jul 22 05:58:07 PM PDT 24
Peak memory 206896 kb
Host smart-c32720f4-e8fb-465f-9677-336f083e78b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30431
12993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_clear.3043112993
Directory /workspace/11.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/11.usbdev_data_toggle_restore.4130217984
Short name T549
Test name
Test status
Simulation time 1440528135 ps
CPU time 2.92 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 05:58:07 PM PDT 24
Peak memory 206856 kb
Host smart-7ae29dd0-a095-4de8-affe-edcdb950421a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41302
17984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_data_toggle_restore.4130217984
Directory /workspace/11.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/11.usbdev_device_address.2067865879
Short name T96
Test name
Test status
Simulation time 8969953764 ps
CPU time 17.65 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206952 kb
Host smart-66997ead-b80d-4380-8e9a-529031e2515f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20678
65879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_device_address.2067865879
Directory /workspace/11.usbdev_device_address/latest

Test location /workspace/coverage/default/11.usbdev_disable_endpoint.3754812298
Short name T737
Test name
Test status
Simulation time 346851613 ps
CPU time 1.15 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 05:58:04 PM PDT 24
Peak memory 206692 kb
Host smart-0a23ad25-2ae4-41f4-9076-8072091a0273
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37548
12298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disable_endpoint.3754812298
Directory /workspace/11.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/11.usbdev_disconnected.3937378420
Short name T769
Test name
Test status
Simulation time 139676221 ps
CPU time 0.76 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:05 PM PDT 24
Peak memory 206724 kb
Host smart-8538f147-ed07-48bb-9ddb-adadf2d09833
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39373
78420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_disconnected.3937378420
Directory /workspace/11.usbdev_disconnected/latest

Test location /workspace/coverage/default/11.usbdev_enable.2418903661
Short name T2548
Test name
Test status
Simulation time 40658932 ps
CPU time 0.69 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:05 PM PDT 24
Peak memory 206744 kb
Host smart-1d0e35b7-3872-4da9-9c53-22b9aad942a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24189
03661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_enable.2418903661
Directory /workspace/11.usbdev_enable/latest

Test location /workspace/coverage/default/11.usbdev_endpoint_access.1581437255
Short name T2528
Test name
Test status
Simulation time 860699427 ps
CPU time 1.99 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:07 PM PDT 24
Peak memory 206812 kb
Host smart-91d8da8b-84b0-4b0c-ba8e-3991620d4412
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15814
37255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_endpoint_access.1581437255
Directory /workspace/11.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/11.usbdev_fifo_rst.4115349377
Short name T2220
Test name
Test status
Simulation time 254459169 ps
CPU time 1.56 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:09 PM PDT 24
Peak memory 206848 kb
Host smart-b2e589b6-d791-416d-9b23-8826a5fe0a95
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41153
49377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_fifo_rst.4115349377
Directory /workspace/11.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/11.usbdev_in_iso.242239574
Short name T591
Test name
Test status
Simulation time 193632337 ps
CPU time 0.86 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 206728 kb
Host smart-11b7d93f-9791-43ee-bd04-0c638b9ce4e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24223
9574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_iso.242239574
Directory /workspace/11.usbdev_in_iso/latest

Test location /workspace/coverage/default/11.usbdev_in_stall.2325235480
Short name T2202
Test name
Test status
Simulation time 159992533 ps
CPU time 0.75 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 05:58:05 PM PDT 24
Peak memory 206756 kb
Host smart-4a3a4ccd-da95-4b5d-aa17-b0e628d31be3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23252
35480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_stall.2325235480
Directory /workspace/11.usbdev_in_stall/latest

Test location /workspace/coverage/default/11.usbdev_in_trans.3408145393
Short name T86
Test name
Test status
Simulation time 208955856 ps
CPU time 0.91 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:05 PM PDT 24
Peak memory 206724 kb
Host smart-7067a06f-2889-4358-954a-d7b168ae0503
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34081
45393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_in_trans.3408145393
Directory /workspace/11.usbdev_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_iso_retraction.1552156408
Short name T1071
Test name
Test status
Simulation time 12464826715 ps
CPU time 103.86 seconds
Started Jul 22 05:58:07 PM PDT 24
Finished Jul 22 05:59:51 PM PDT 24
Peak memory 206904 kb
Host smart-7963a111-a511-4b18-97f7-d5f3cd2ea68f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15521
56408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_iso_retraction.1552156408
Directory /workspace/11.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/11.usbdev_link_in_err.936930080
Short name T1842
Test name
Test status
Simulation time 157202676 ps
CPU time 0.88 seconds
Started Jul 22 05:58:07 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 206684 kb
Host smart-c49f7be7-80f1-4343-852b-cf3a78e69a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93693
0080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_in_err.936930080
Directory /workspace/11.usbdev_link_in_err/latest

Test location /workspace/coverage/default/11.usbdev_link_resume.450840633
Short name T1874
Test name
Test status
Simulation time 23329795737 ps
CPU time 22.24 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 05:58:26 PM PDT 24
Peak memory 206756 kb
Host smart-edc3bc86-8400-4400-ae44-8f34c8d4f885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45084
0633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_resume.450840633
Directory /workspace/11.usbdev_link_resume/latest

Test location /workspace/coverage/default/11.usbdev_link_suspend.1891688696
Short name T2231
Test name
Test status
Simulation time 3316974074 ps
CPU time 4.42 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:09 PM PDT 24
Peak memory 206836 kb
Host smart-2c52191b-9784-4c53-adfe-ec081c018859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18916
88696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_link_suspend.1891688696
Directory /workspace/11.usbdev_link_suspend/latest

Test location /workspace/coverage/default/11.usbdev_low_speed_traffic.1545964161
Short name T1201
Test name
Test status
Simulation time 10819972488 ps
CPU time 108.99 seconds
Started Jul 22 05:58:05 PM PDT 24
Finished Jul 22 05:59:55 PM PDT 24
Peak memory 206948 kb
Host smart-d6c168ca-17f1-4fc1-8a6d-0a18af274ed9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15459
64161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_low_speed_traffic.1545964161
Directory /workspace/11.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/11.usbdev_max_inter_pkt_delay.4160642717
Short name T730
Test name
Test status
Simulation time 7256660513 ps
CPU time 196.27 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 06:01:20 PM PDT 24
Peak memory 206888 kb
Host smart-aab47d16-9306-4908-9af4-d413ccd3afd0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4160642717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_inter_pkt_delay.4160642717
Directory /workspace/11.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_max_length_in_transaction.1051134021
Short name T2122
Test name
Test status
Simulation time 239992763 ps
CPU time 0.91 seconds
Started Jul 22 05:58:05 PM PDT 24
Finished Jul 22 05:58:06 PM PDT 24
Peak memory 206740 kb
Host smart-7eb8c9e2-3f8c-410f-9433-a862ed67f662
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1051134021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_in_transaction.1051134021
Directory /workspace/11.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_length_out_transaction.3891160358
Short name T2012
Test name
Test status
Simulation time 201646025 ps
CPU time 0.84 seconds
Started Jul 22 05:59:16 PM PDT 24
Finished Jul 22 05:59:18 PM PDT 24
Peak memory 206728 kb
Host smart-12e10454-cae3-4f9c-8afe-eb405f585e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38911
60358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_length_out_transaction.3891160358
Directory /workspace/11.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_max_usb_traffic.2484844314
Short name T2360
Test name
Test status
Simulation time 3331764624 ps
CPU time 24.59 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:32 PM PDT 24
Peak memory 206864 kb
Host smart-f3b830ef-b2fe-41f8-9448-61f7a6fc46a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24848
44314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_max_usb_traffic.2484844314
Directory /workspace/11.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/11.usbdev_min_inter_pkt_delay.3389489057
Short name T2141
Test name
Test status
Simulation time 5365980751 ps
CPU time 53.51 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206848 kb
Host smart-cab433d3-fc9d-4265-b137-5262972da450
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3389489057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_inter_pkt_delay.3389489057
Directory /workspace/11.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/11.usbdev_min_length_in_transaction.3309715472
Short name T1355
Test name
Test status
Simulation time 172402173 ps
CPU time 0.82 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:06 PM PDT 24
Peak memory 206724 kb
Host smart-9afd5746-6b9a-446a-9d14-4b3fad49ea7a
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3309715472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_in_transaction.3309715472
Directory /workspace/11.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_min_length_out_transaction.2971050017
Short name T1310
Test name
Test status
Simulation time 157804570 ps
CPU time 0.76 seconds
Started Jul 22 05:58:03 PM PDT 24
Finished Jul 22 05:58:05 PM PDT 24
Peak memory 206752 kb
Host smart-d0c88657-fbc9-4de3-98e0-575843739ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29710
50017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_min_length_out_transaction.2971050017
Directory /workspace/11.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_out_iso.2058601553
Short name T884
Test name
Test status
Simulation time 152485242 ps
CPU time 0.8 seconds
Started Jul 22 05:58:02 PM PDT 24
Finished Jul 22 05:58:04 PM PDT 24
Peak memory 206744 kb
Host smart-4234be67-0d4d-4646-bdf1-54d656b24ffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20586
01553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_iso.2058601553
Directory /workspace/11.usbdev_out_iso/latest

Test location /workspace/coverage/default/11.usbdev_out_stall.3995591497
Short name T410
Test name
Test status
Simulation time 228839332 ps
CPU time 0.88 seconds
Started Jul 22 05:58:05 PM PDT 24
Finished Jul 22 05:58:07 PM PDT 24
Peak memory 206752 kb
Host smart-7b83d64f-2c24-46af-9c3a-6d6d354bb33f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39955
91497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_stall.3995591497
Directory /workspace/11.usbdev_out_stall/latest

Test location /workspace/coverage/default/11.usbdev_out_trans_nak.3967367559
Short name T1154
Test name
Test status
Simulation time 199647097 ps
CPU time 0.85 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:05 PM PDT 24
Peak memory 206736 kb
Host smart-516aa8d6-8eaf-47fa-b215-cdb8ced44a08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39673
67559 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_out_trans_nak.3967367559
Directory /workspace/11.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/11.usbdev_pending_in_trans.2704865761
Short name T1049
Test name
Test status
Simulation time 159133496 ps
CPU time 0.85 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 206700 kb
Host smart-8cad2284-c067-4769-88c5-4206478447c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27048
65761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pending_in_trans.2704865761
Directory /workspace/11.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_pinflip.231953832
Short name T609
Test name
Test status
Simulation time 206923950 ps
CPU time 0.93 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 206704 kb
Host smart-82156da0-c0f7-41af-bd90-7864b3027b53
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=231953832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_pinflip.231953832
Directory /workspace/11.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/11.usbdev_phy_config_usb_ref_disable.76911531
Short name T45
Test name
Test status
Simulation time 148397179 ps
CPU time 0.79 seconds
Started Jul 22 05:58:05 PM PDT 24
Finished Jul 22 05:58:07 PM PDT 24
Peak memory 206752 kb
Host smart-cc46b71d-befa-4849-aac7-3cd753168a87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76911
531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_config_usb_ref_disable.76911531
Directory /workspace/11.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/11.usbdev_phy_pins_sense.1981744859
Short name T1323
Test name
Test status
Simulation time 36658986 ps
CPU time 0.67 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206636 kb
Host smart-321ea6f5-8f4a-4a66-a505-8ac604a86137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19817
44859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_phy_pins_sense.1981744859
Directory /workspace/11.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/11.usbdev_pkt_buffer.776996722
Short name T2618
Test name
Test status
Simulation time 9220279262 ps
CPU time 20.27 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:36 PM PDT 24
Peak memory 206944 kb
Host smart-7c9e7968-b6bb-4bab-a532-7284d26d79b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77699
6722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_buffer.776996722
Directory /workspace/11.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/11.usbdev_pkt_received.2455836201
Short name T58
Test name
Test status
Simulation time 168556708 ps
CPU time 0.81 seconds
Started Jul 22 05:58:13 PM PDT 24
Finished Jul 22 05:58:14 PM PDT 24
Peak memory 206756 kb
Host smart-79fe1208-4898-4b8c-bebd-0d55dfa85235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24558
36201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_received.2455836201
Directory /workspace/11.usbdev_pkt_received/latest

Test location /workspace/coverage/default/11.usbdev_pkt_sent.2193251068
Short name T1184
Test name
Test status
Simulation time 226292516 ps
CPU time 0.88 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206748 kb
Host smart-0a7a72d3-c4d7-4b0f-975b-965337d9d610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21932
51068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_pkt_sent.2193251068
Directory /workspace/11.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/11.usbdev_random_length_in_transaction.1350603138
Short name T1405
Test name
Test status
Simulation time 275781998 ps
CPU time 0.97 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206744 kb
Host smart-aba93cdb-986e-42f9-a0c7-e967e96d9f4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13506
03138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_in_transaction.1350603138
Directory /workspace/11.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/11.usbdev_random_length_out_transaction.927959041
Short name T2463
Test name
Test status
Simulation time 155553265 ps
CPU time 0.83 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:15 PM PDT 24
Peak memory 206776 kb
Host smart-3cb81aab-cc5f-43a6-82f7-f8e1f93c05b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92795
9041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_random_length_out_transaction.927959041
Directory /workspace/11.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/11.usbdev_rx_crc_err.778009748
Short name T2170
Test name
Test status
Simulation time 198288992 ps
CPU time 0.82 seconds
Started Jul 22 05:58:15 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206752 kb
Host smart-b26376f4-06cd-4398-a686-b0e767215715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77800
9748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_rx_crc_err.778009748
Directory /workspace/11.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/11.usbdev_setup_stage.218372898
Short name T580
Test name
Test status
Simulation time 198161228 ps
CPU time 0.8 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206736 kb
Host smart-f9a96d2e-b6ad-4664-aa60-4412b6ff6047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
2898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_stage.218372898
Directory /workspace/11.usbdev_setup_stage/latest

Test location /workspace/coverage/default/11.usbdev_setup_trans_ignored.1546763132
Short name T814
Test name
Test status
Simulation time 142175623 ps
CPU time 0.79 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206724 kb
Host smart-f20dc115-953b-49eb-9bb0-e9d42cb2b5c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15467
63132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_setup_trans_ignored.1546763132
Directory /workspace/11.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/11.usbdev_smoke.124463426
Short name T1961
Test name
Test status
Simulation time 201075698 ps
CPU time 0.95 seconds
Started Jul 22 05:58:15 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206732 kb
Host smart-121ddb17-bd9e-4656-8ab1-fcb414b60cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12446
3426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_smoke.124463426
Directory /workspace/11.usbdev_smoke/latest

Test location /workspace/coverage/default/11.usbdev_spurious_pids_ignored.887698084
Short name T1914
Test name
Test status
Simulation time 7054095274 ps
CPU time 51.36 seconds
Started Jul 22 05:58:17 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206904 kb
Host smart-5ebc71ae-37f3-4f4c-82bf-089ab5eaa3b1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=887698084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_spurious_pids_ignored.887698084
Directory /workspace/11.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/11.usbdev_stall_trans.931233184
Short name T2347
Test name
Test status
Simulation time 159453719 ps
CPU time 0.84 seconds
Started Jul 22 05:58:17 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206728 kb
Host smart-e00241b2-001b-4f87-bbd7-ab94fad0a547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93123
3184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stall_trans.931233184
Directory /workspace/11.usbdev_stall_trans/latest

Test location /workspace/coverage/default/11.usbdev_stream_len_max.94458356
Short name T1599
Test name
Test status
Simulation time 1250336095 ps
CPU time 2.57 seconds
Started Jul 22 05:58:13 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206860 kb
Host smart-6ecf0ba7-e2b4-4e08-9643-4a43ad9e3957
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94458
356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_stream_len_max.94458356
Directory /workspace/11.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/11.usbdev_streaming_out.3674475683
Short name T2386
Test name
Test status
Simulation time 5472811354 ps
CPU time 142.67 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206900 kb
Host smart-f14e3ac5-2545-4b18-8e3c-f1c243a14e42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36744
75683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.usbdev_streaming_out.3674475683
Directory /workspace/11.usbdev_streaming_out/latest

Test location /workspace/coverage/default/12.usbdev_alert_test.539572629
Short name T2272
Test name
Test status
Simulation time 87470556 ps
CPU time 0.73 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:58:25 PM PDT 24
Peak memory 206732 kb
Host smart-59108dd2-0325-4cdc-9316-c25ff40f6610
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=539572629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_alert_test.539572629
Directory /workspace/12.usbdev_alert_test/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_disconnect.2820642070
Short name T1773
Test name
Test status
Simulation time 4280820176 ps
CPU time 5.06 seconds
Started Jul 22 05:58:13 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206792 kb
Host smart-f816fbcc-9460-4a3e-a2f3-b9a9116aeeea
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2820642070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_disconnect.2820642070
Directory /workspace/12.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_reset.4013980651
Short name T1986
Test name
Test status
Simulation time 13363462500 ps
CPU time 13.05 seconds
Started Jul 22 05:58:26 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206800 kb
Host smart-cb23457f-fe29-44fb-b134-f93cbd278ce8
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4013980651 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_reset.4013980651
Directory /workspace/12.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/12.usbdev_aon_wake_resume.2735105664
Short name T2454
Test name
Test status
Simulation time 23506314664 ps
CPU time 24.79 seconds
Started Jul 22 05:58:13 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206892 kb
Host smart-df785d8a-cf79-4c6a-8854-d9e371ee40c7
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2735105664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_aon_wake_resume.2735105664
Directory /workspace/12.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/12.usbdev_av_buffer.3969969596
Short name T1202
Test name
Test status
Simulation time 202955806 ps
CPU time 0.77 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206712 kb
Host smart-3f5f38fe-4bfb-490c-9885-edea7d86f9b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39699
69596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_av_buffer.3969969596
Directory /workspace/12.usbdev_av_buffer/latest

Test location /workspace/coverage/default/12.usbdev_bitstuff_err.4042981942
Short name T2425
Test name
Test status
Simulation time 158334539 ps
CPU time 0.75 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:15 PM PDT 24
Peak memory 206700 kb
Host smart-897f191e-fff3-4e99-a996-98d97e071a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40429
81942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_bitstuff_err.4042981942
Directory /workspace/12.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/12.usbdev_data_toggle_restore.1385706799
Short name T1926
Test name
Test status
Simulation time 315523425 ps
CPU time 0.95 seconds
Started Jul 22 05:58:15 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206712 kb
Host smart-d9b2063b-96e8-44ed-a79b-9ff6d3813edd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13857
06799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_data_toggle_restore.1385706799
Directory /workspace/12.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/12.usbdev_device_address.3116586062
Short name T1340
Test name
Test status
Simulation time 16074352472 ps
CPU time 32.4 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206904 kb
Host smart-2b5ee361-dd34-4379-8be2-26ce242926cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31165
86062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_device_address.3116586062
Directory /workspace/12.usbdev_device_address/latest

Test location /workspace/coverage/default/12.usbdev_disable_endpoint.2214520103
Short name T1671
Test name
Test status
Simulation time 471550010 ps
CPU time 1.51 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206788 kb
Host smart-b44f1b34-1180-4e6d-a1bb-ba395bfa4005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22145
20103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disable_endpoint.2214520103
Directory /workspace/12.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/12.usbdev_disconnected.4017467365
Short name T889
Test name
Test status
Simulation time 155169515 ps
CPU time 0.78 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:15 PM PDT 24
Peak memory 206752 kb
Host smart-0d14b239-83f2-4a73-b7a9-367d262a5307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40174
67365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_disconnected.4017467365
Directory /workspace/12.usbdev_disconnected/latest

Test location /workspace/coverage/default/12.usbdev_enable.35244152
Short name T604
Test name
Test status
Simulation time 49642223 ps
CPU time 0.67 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:15 PM PDT 24
Peak memory 206732 kb
Host smart-c16ff716-ea8b-431a-af96-4f7f99845204
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35244
152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_enable.35244152
Directory /workspace/12.usbdev_enable/latest

Test location /workspace/coverage/default/12.usbdev_endpoint_access.2557153110
Short name T619
Test name
Test status
Simulation time 908596572 ps
CPU time 2.19 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206848 kb
Host smart-21bf4643-fd7d-4add-897a-e924c2caf63b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25571
53110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_endpoint_access.2557153110
Directory /workspace/12.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/12.usbdev_fifo_rst.1789750661
Short name T766
Test name
Test status
Simulation time 195110143 ps
CPU time 2.16 seconds
Started Jul 22 05:58:15 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206900 kb
Host smart-0b757b77-5e43-4535-8ae9-0289d0d60e07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17897
50661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_fifo_rst.1789750661
Directory /workspace/12.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/12.usbdev_in_iso.3559402672
Short name T1649
Test name
Test status
Simulation time 217936248 ps
CPU time 0.91 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206616 kb
Host smart-f46ef690-aafc-41f9-a82d-b06f25274518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35594
02672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_iso.3559402672
Directory /workspace/12.usbdev_in_iso/latest

Test location /workspace/coverage/default/12.usbdev_in_stall.2860407829
Short name T684
Test name
Test status
Simulation time 152688828 ps
CPU time 0.77 seconds
Started Jul 22 05:58:15 PM PDT 24
Finished Jul 22 05:58:17 PM PDT 24
Peak memory 206736 kb
Host smart-3a6595d1-74c9-4601-b711-54cb232f5f84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28604
07829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_stall.2860407829
Directory /workspace/12.usbdev_in_stall/latest

Test location /workspace/coverage/default/12.usbdev_in_trans.555236796
Short name T1680
Test name
Test status
Simulation time 193139205 ps
CPU time 0.88 seconds
Started Jul 22 05:58:12 PM PDT 24
Finished Jul 22 05:58:14 PM PDT 24
Peak memory 206860 kb
Host smart-f3eac4b4-a43d-4494-a8ba-5c6c6d63429c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55523
6796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_in_trans.555236796
Directory /workspace/12.usbdev_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_invalid_sync.1203708705
Short name T82
Test name
Test status
Simulation time 8272210380 ps
CPU time 60.15 seconds
Started Jul 22 05:58:12 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206936 kb
Host smart-19cd9181-519f-4194-9705-aee27b4dbb69
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1203708705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_invalid_sync.1203708705
Directory /workspace/12.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/12.usbdev_link_in_err.3497711280
Short name T2589
Test name
Test status
Simulation time 172700103 ps
CPU time 0.79 seconds
Started Jul 22 05:58:13 PM PDT 24
Finished Jul 22 05:58:15 PM PDT 24
Peak memory 206712 kb
Host smart-6c4c3181-f884-40ad-8fd2-32c369ca2e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34977
11280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_in_err.3497711280
Directory /workspace/12.usbdev_link_in_err/latest

Test location /workspace/coverage/default/12.usbdev_link_resume.2349505329
Short name T2607
Test name
Test status
Simulation time 23271070743 ps
CPU time 25.3 seconds
Started Jul 22 05:58:14 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206736 kb
Host smart-62c92033-bbc6-4bac-a472-9a245117f475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23495
05329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_resume.2349505329
Directory /workspace/12.usbdev_link_resume/latest

Test location /workspace/coverage/default/12.usbdev_link_suspend.715056692
Short name T2256
Test name
Test status
Simulation time 3332847583 ps
CPU time 4.84 seconds
Started Jul 22 05:58:13 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206804 kb
Host smart-15e323e6-85fa-4975-a15e-f90b6a66f13f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71505
6692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_link_suspend.715056692
Directory /workspace/12.usbdev_link_suspend/latest

Test location /workspace/coverage/default/12.usbdev_low_speed_traffic.3591707489
Short name T413
Test name
Test status
Simulation time 7641831334 ps
CPU time 204.02 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 06:01:46 PM PDT 24
Peak memory 206996 kb
Host smart-ee6c166a-489f-4602-be17-b1080aa1a2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35917
07489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_low_speed_traffic.3591707489
Directory /workspace/12.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/12.usbdev_max_inter_pkt_delay.2992145680
Short name T948
Test name
Test status
Simulation time 5937126735 ps
CPU time 44.28 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:59:08 PM PDT 24
Peak memory 206900 kb
Host smart-235046b8-526d-4387-8684-5b00c086c8ed
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2992145680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_inter_pkt_delay.2992145680
Directory /workspace/12.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_max_length_in_transaction.1433735526
Short name T786
Test name
Test status
Simulation time 247542373 ps
CPU time 0.87 seconds
Started Jul 22 05:58:28 PM PDT 24
Finished Jul 22 05:58:29 PM PDT 24
Peak memory 206920 kb
Host smart-7b1a97d9-d7a8-4a53-ba62-f4e11695cb1d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1433735526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_in_transaction.1433735526
Directory /workspace/12.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_length_out_transaction.222936066
Short name T753
Test name
Test status
Simulation time 182366236 ps
CPU time 0.84 seconds
Started Jul 22 05:58:19 PM PDT 24
Finished Jul 22 05:58:20 PM PDT 24
Peak memory 206744 kb
Host smart-c0426803-c1f5-4e70-af0f-ed97752ae210
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22293
6066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_length_out_transaction.222936066
Directory /workspace/12.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_max_usb_traffic.4024291204
Short name T1614
Test name
Test status
Simulation time 4914036873 ps
CPU time 137.44 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 06:00:41 PM PDT 24
Peak memory 206892 kb
Host smart-24b5402a-3d1f-4096-8df4-ea4da2e8353c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40242
91204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_max_usb_traffic.4024291204
Directory /workspace/12.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/12.usbdev_min_inter_pkt_delay.1361186015
Short name T2097
Test name
Test status
Simulation time 5025871202 ps
CPU time 139.93 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 06:00:44 PM PDT 24
Peak memory 206932 kb
Host smart-903668f6-3766-49f9-8684-670a3a5869a1
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1361186015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_inter_pkt_delay.1361186015
Directory /workspace/12.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/12.usbdev_min_length_in_transaction.2243439792
Short name T1420
Test name
Test status
Simulation time 154009532 ps
CPU time 0.79 seconds
Started Jul 22 05:58:20 PM PDT 24
Finished Jul 22 05:58:22 PM PDT 24
Peak memory 206708 kb
Host smart-98cbed03-d242-48a9-bccb-2cb5046e0eed
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2243439792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_in_transaction.2243439792
Directory /workspace/12.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_min_length_out_transaction.268599361
Short name T430
Test name
Test status
Simulation time 144281859 ps
CPU time 0.78 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206632 kb
Host smart-9c750597-c0e2-402c-9e4b-e1bbc1198dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26859
9361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_min_length_out_transaction.268599361
Directory /workspace/12.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_out_iso.3585486835
Short name T350
Test name
Test status
Simulation time 169243621 ps
CPU time 0.83 seconds
Started Jul 22 05:58:24 PM PDT 24
Finished Jul 22 05:58:26 PM PDT 24
Peak memory 206700 kb
Host smart-f7104e14-3d23-4248-89f9-812cbd19b9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35854
86835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_iso.3585486835
Directory /workspace/12.usbdev_out_iso/latest

Test location /workspace/coverage/default/12.usbdev_out_stall.3799941874
Short name T1132
Test name
Test status
Simulation time 274345643 ps
CPU time 0.9 seconds
Started Jul 22 05:58:20 PM PDT 24
Finished Jul 22 05:58:21 PM PDT 24
Peak memory 206756 kb
Host smart-8074dfcd-c6ad-44e8-b9c8-230428b2d6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37999
41874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_stall.3799941874
Directory /workspace/12.usbdev_out_stall/latest

Test location /workspace/coverage/default/12.usbdev_out_trans_nak.850638555
Short name T2601
Test name
Test status
Simulation time 214563344 ps
CPU time 0.81 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 05:58:22 PM PDT 24
Peak memory 206736 kb
Host smart-2247379c-be8c-4fbb-868f-d529abd8cba8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85063
8555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_out_trans_nak.850638555
Directory /workspace/12.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/12.usbdev_pending_in_trans.1959922187
Short name T533
Test name
Test status
Simulation time 152359716 ps
CPU time 0.79 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:58:25 PM PDT 24
Peak memory 206748 kb
Host smart-94305a41-158b-477c-85d7-f1d45728db18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19599
22187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pending_in_trans.1959922187
Directory /workspace/12.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_pinflip.4155470299
Short name T818
Test name
Test status
Simulation time 228157229 ps
CPU time 0.88 seconds
Started Jul 22 05:58:24 PM PDT 24
Finished Jul 22 05:58:26 PM PDT 24
Peak memory 206704 kb
Host smart-a6bfa12f-eec6-4ca1-a9fd-d58153ee0f70
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4155470299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_pinflip.4155470299
Directory /workspace/12.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/12.usbdev_phy_config_usb_ref_disable.2998386565
Short name T1212
Test name
Test status
Simulation time 233384497 ps
CPU time 0.85 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206736 kb
Host smart-5e42e6d0-ec9d-436b-b2b8-deec7c32d730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29983
86565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_config_usb_ref_disable.2998386565
Directory /workspace/12.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/12.usbdev_phy_pins_sense.261533099
Short name T2680
Test name
Test status
Simulation time 46188880 ps
CPU time 0.68 seconds
Started Jul 22 05:58:28 PM PDT 24
Finished Jul 22 05:58:29 PM PDT 24
Peak memory 206744 kb
Host smart-8897ac62-c425-4aaf-b9d7-15e82681d30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26153
3099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_phy_pins_sense.261533099
Directory /workspace/12.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/12.usbdev_pkt_buffer.370487168
Short name T888
Test name
Test status
Simulation time 15800426459 ps
CPU time 34.23 seconds
Started Jul 22 05:58:25 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 207000 kb
Host smart-871af1f9-0ac0-4e7a-a7a8-4c0223fb210c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37048
7168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_buffer.370487168
Directory /workspace/12.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/12.usbdev_pkt_received.2512502925
Short name T1916
Test name
Test status
Simulation time 169759580 ps
CPU time 0.79 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206712 kb
Host smart-10c9da0d-ddd9-4c7a-b828-1f7ee2089729
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25125
02925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_received.2512502925
Directory /workspace/12.usbdev_pkt_received/latest

Test location /workspace/coverage/default/12.usbdev_pkt_sent.3052679170
Short name T480
Test name
Test status
Simulation time 223853541 ps
CPU time 0.85 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206656 kb
Host smart-10cb4d6d-a89a-40d3-acde-f0d3da8cdc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30526
79170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_pkt_sent.3052679170
Directory /workspace/12.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/12.usbdev_random_length_in_transaction.580004562
Short name T481
Test name
Test status
Simulation time 182097953 ps
CPU time 0.84 seconds
Started Jul 22 05:58:26 PM PDT 24
Finished Jul 22 05:58:27 PM PDT 24
Peak memory 206752 kb
Host smart-e0244f02-5de7-4d7f-9d1d-1ca018379d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58000
4562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_in_transaction.580004562
Directory /workspace/12.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/12.usbdev_random_length_out_transaction.526996519
Short name T2551
Test name
Test status
Simulation time 207802739 ps
CPU time 0.86 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 05:58:22 PM PDT 24
Peak memory 206680 kb
Host smart-6ec71beb-d67e-44ad-a96e-ab36723a6f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52699
6519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_random_length_out_transaction.526996519
Directory /workspace/12.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/12.usbdev_rx_crc_err.3688069838
Short name T2284
Test name
Test status
Simulation time 176677357 ps
CPU time 0.77 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206736 kb
Host smart-fe4d8b12-9a1b-4bca-8810-260c956b8242
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36880
69838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_rx_crc_err.3688069838
Directory /workspace/12.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/12.usbdev_setup_stage.1704822175
Short name T790
Test name
Test status
Simulation time 152923240 ps
CPU time 0.8 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:58:25 PM PDT 24
Peak memory 206748 kb
Host smart-e5a28262-d262-4dc9-8f70-0f56816db791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
22175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_stage.1704822175
Directory /workspace/12.usbdev_setup_stage/latest

Test location /workspace/coverage/default/12.usbdev_setup_trans_ignored.1845967167
Short name T1664
Test name
Test status
Simulation time 150438435 ps
CPU time 0.84 seconds
Started Jul 22 05:58:25 PM PDT 24
Finished Jul 22 05:58:26 PM PDT 24
Peak memory 206736 kb
Host smart-b1c38abd-f689-4271-bd6c-4fb997aae2fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18459
67167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_setup_trans_ignored.1845967167
Directory /workspace/12.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/12.usbdev_smoke.2940282931
Short name T1550
Test name
Test status
Simulation time 194412282 ps
CPU time 0.84 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206728 kb
Host smart-66fdf731-881f-4697-b6c8-c248c1f77c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29402
82931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_smoke.2940282931
Directory /workspace/12.usbdev_smoke/latest

Test location /workspace/coverage/default/12.usbdev_spurious_pids_ignored.2352113354
Short name T2201
Test name
Test status
Simulation time 7474306330 ps
CPU time 205.98 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 06:01:47 PM PDT 24
Peak memory 206880 kb
Host smart-9f921275-34c6-4ab8-a558-d42142607f31
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2352113354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_spurious_pids_ignored.2352113354
Directory /workspace/12.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/12.usbdev_stall_priority_over_nak.818491680
Short name T2246
Test name
Test status
Simulation time 185879077 ps
CPU time 0.89 seconds
Started Jul 22 05:58:31 PM PDT 24
Finished Jul 22 05:58:32 PM PDT 24
Peak memory 206696 kb
Host smart-f8e912cf-c87c-4088-a8ce-fcfa7bc9fd92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81849
1680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_priority_over_nak.818491680
Directory /workspace/12.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/12.usbdev_stall_trans.1867819016
Short name T2243
Test name
Test status
Simulation time 162369318 ps
CPU time 0.78 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206744 kb
Host smart-25f4c5dc-cf68-40fa-b440-e5d9b195e8cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18678
19016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stall_trans.1867819016
Directory /workspace/12.usbdev_stall_trans/latest

Test location /workspace/coverage/default/12.usbdev_stream_len_max.3796557578
Short name T1582
Test name
Test status
Simulation time 568970992 ps
CPU time 1.63 seconds
Started Jul 22 05:58:25 PM PDT 24
Finished Jul 22 05:58:27 PM PDT 24
Peak memory 206712 kb
Host smart-60170e46-5d95-4b61-9a32-503de25580c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37965
57578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_stream_len_max.3796557578
Directory /workspace/12.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/12.usbdev_streaming_out.302008969
Short name T1426
Test name
Test status
Simulation time 4936464736 ps
CPU time 33.87 seconds
Started Jul 22 05:58:26 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 207088 kb
Host smart-a24614c3-8e96-413d-8404-37e342ea4a25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30200
8969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.usbdev_streaming_out.302008969
Directory /workspace/12.usbdev_streaming_out/latest

Test location /workspace/coverage/default/13.usbdev_alert_test.4193175005
Short name T1560
Test name
Test status
Simulation time 41042578 ps
CPU time 0.65 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206728 kb
Host smart-184f037b-2455-4bee-9085-16e2ee42e8cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4193175005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_alert_test.4193175005
Directory /workspace/13.usbdev_alert_test/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_disconnect.2823724899
Short name T641
Test name
Test status
Simulation time 3688400062 ps
CPU time 4.11 seconds
Started Jul 22 05:58:26 PM PDT 24
Finished Jul 22 05:58:31 PM PDT 24
Peak memory 207036 kb
Host smart-045840c1-7c08-43b7-a8f5-52ee2d8abe26
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2823724899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_disconnect.2823724899
Directory /workspace/13.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/13.usbdev_aon_wake_resume.3194122843
Short name T1327
Test name
Test status
Simulation time 23335342136 ps
CPU time 21.18 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:44 PM PDT 24
Peak memory 206896 kb
Host smart-233013af-c4ea-499e-b6a3-a71ef2fa5632
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3194122843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_aon_wake_resume.3194122843
Directory /workspace/13.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/13.usbdev_av_buffer.163076105
Short name T1347
Test name
Test status
Simulation time 160995182 ps
CPU time 0.8 seconds
Started Jul 22 05:58:26 PM PDT 24
Finished Jul 22 05:58:27 PM PDT 24
Peak memory 206856 kb
Host smart-286dc73c-bd57-4c5d-bb2b-a7ba54f3ca43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16307
6105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_av_buffer.163076105
Directory /workspace/13.usbdev_av_buffer/latest

Test location /workspace/coverage/default/13.usbdev_bitstuff_err.1239558869
Short name T1354
Test name
Test status
Simulation time 188764796 ps
CPU time 0.83 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206712 kb
Host smart-a579b207-4a80-42dc-8124-f3ca2768270f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12395
58869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_bitstuff_err.1239558869
Directory /workspace/13.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_clear.2237346650
Short name T2480
Test name
Test status
Simulation time 241377649 ps
CPU time 0.94 seconds
Started Jul 22 05:58:29 PM PDT 24
Finished Jul 22 05:58:30 PM PDT 24
Peak memory 206740 kb
Host smart-73a4fc13-494a-45a5-826f-65ca5cadf147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22373
46650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_clear.2237346650
Directory /workspace/13.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/13.usbdev_data_toggle_restore.3434246942
Short name T825
Test name
Test status
Simulation time 837199535 ps
CPU time 2.14 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206832 kb
Host smart-c3867740-1a1d-4814-9695-bd3a7827bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34342
46942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_data_toggle_restore.3434246942
Directory /workspace/13.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/13.usbdev_device_address.988903634
Short name T1487
Test name
Test status
Simulation time 19247953589 ps
CPU time 37.24 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:59:02 PM PDT 24
Peak memory 206944 kb
Host smart-f97547ce-b7a1-4a5a-9e49-d64c916196ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98890
3634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_device_address.988903634
Directory /workspace/13.usbdev_device_address/latest

Test location /workspace/coverage/default/13.usbdev_disable_endpoint.2636031329
Short name T2070
Test name
Test status
Simulation time 469793740 ps
CPU time 1.37 seconds
Started Jul 22 05:58:24 PM PDT 24
Finished Jul 22 05:58:26 PM PDT 24
Peak memory 206748 kb
Host smart-dcddeafd-fdcb-4a0b-93f9-a9a6852ed244
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26360
31329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disable_endpoint.2636031329
Directory /workspace/13.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/13.usbdev_disconnected.4249386538
Short name T1085
Test name
Test status
Simulation time 160801832 ps
CPU time 0.8 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:58:25 PM PDT 24
Peak memory 206700 kb
Host smart-aabbc795-32d9-44c4-a3db-54a5197fff72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42493
86538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_disconnected.4249386538
Directory /workspace/13.usbdev_disconnected/latest

Test location /workspace/coverage/default/13.usbdev_enable.2660869080
Short name T631
Test name
Test status
Simulation time 44089993 ps
CPU time 0.64 seconds
Started Jul 22 05:58:43 PM PDT 24
Finished Jul 22 05:58:44 PM PDT 24
Peak memory 206672 kb
Host smart-650f2e9d-6677-4c39-a588-bc0047bf6a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26608
69080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_enable.2660869080
Directory /workspace/13.usbdev_enable/latest

Test location /workspace/coverage/default/13.usbdev_endpoint_access.2696181593
Short name T2621
Test name
Test status
Simulation time 994538208 ps
CPU time 2.33 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206824 kb
Host smart-a0a56f30-0695-4433-894a-5c670ab50029
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26961
81593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_endpoint_access.2696181593
Directory /workspace/13.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/13.usbdev_fifo_rst.3558298745
Short name T2558
Test name
Test status
Simulation time 192535648 ps
CPU time 2.27 seconds
Started Jul 22 05:58:21 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206900 kb
Host smart-7cfff5ef-a72b-480c-9ea3-3f3af16616eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35582
98745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_fifo_rst.3558298745
Directory /workspace/13.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/13.usbdev_in_iso.661342242
Short name T321
Test name
Test status
Simulation time 185020187 ps
CPU time 0.83 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206740 kb
Host smart-a1b18c1b-d4d5-4a1f-8c90-4c74a18b020a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66134
2242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_iso.661342242
Directory /workspace/13.usbdev_in_iso/latest

Test location /workspace/coverage/default/13.usbdev_in_stall.532023994
Short name T2599
Test name
Test status
Simulation time 230863761 ps
CPU time 0.96 seconds
Started Jul 22 05:58:26 PM PDT 24
Finished Jul 22 05:58:27 PM PDT 24
Peak memory 206748 kb
Host smart-ce22b09c-bc95-4817-b0d1-b604e045f5c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53202
3994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_stall.532023994
Directory /workspace/13.usbdev_in_stall/latest

Test location /workspace/coverage/default/13.usbdev_in_trans.864545562
Short name T27
Test name
Test status
Simulation time 183274543 ps
CPU time 0.84 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206728 kb
Host smart-826157ac-bb9c-4444-9e46-a11fc17d2335
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86454
5562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_in_trans.864545562
Directory /workspace/13.usbdev_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_iso_retraction.4198686420
Short name T4
Test name
Test status
Simulation time 6653338215 ps
CPU time 54.77 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:59:18 PM PDT 24
Peak memory 206884 kb
Host smart-2d56c0e4-e40b-4bc3-b56d-c37d0d5d58e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41986
86420 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_iso_retraction.4198686420
Directory /workspace/13.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/13.usbdev_link_in_err.1831094436
Short name T2679
Test name
Test status
Simulation time 161240779 ps
CPU time 0.79 seconds
Started Jul 22 05:58:22 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206748 kb
Host smart-b6c39add-5c02-46a7-8c52-cf5445001594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18310
94436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_in_err.1831094436
Directory /workspace/13.usbdev_link_in_err/latest

Test location /workspace/coverage/default/13.usbdev_link_resume.3507875283
Short name T2300
Test name
Test status
Simulation time 23296619357 ps
CPU time 27.74 seconds
Started Jul 22 05:59:02 PM PDT 24
Finished Jul 22 05:59:30 PM PDT 24
Peak memory 206804 kb
Host smart-a4872718-55c8-4171-8b81-fe0c0173e281
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35078
75283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_resume.3507875283
Directory /workspace/13.usbdev_link_resume/latest

Test location /workspace/coverage/default/13.usbdev_link_suspend.4078535555
Short name T1352
Test name
Test status
Simulation time 3370261551 ps
CPU time 4.93 seconds
Started Jul 22 05:58:25 PM PDT 24
Finished Jul 22 05:58:31 PM PDT 24
Peak memory 206812 kb
Host smart-804212ca-23de-45c5-9565-ddd4a04da1eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40785
35555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_link_suspend.4078535555
Directory /workspace/13.usbdev_link_suspend/latest

Test location /workspace/coverage/default/13.usbdev_low_speed_traffic.2823485672
Short name T1048
Test name
Test status
Simulation time 6287812689 ps
CPU time 59.08 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:59:32 PM PDT 24
Peak memory 206908 kb
Host smart-320eda65-cd58-4b4e-9676-88e9559aeebd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28234
85672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_low_speed_traffic.2823485672
Directory /workspace/13.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/13.usbdev_max_inter_pkt_delay.368099450
Short name T2534
Test name
Test status
Simulation time 4371483914 ps
CPU time 40.08 seconds
Started Jul 22 05:58:31 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206876 kb
Host smart-6a6dc2e4-d065-4bdd-bc2d-3da776c51d36
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=368099450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_inter_pkt_delay.368099450
Directory /workspace/13.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_max_length_in_transaction.1540119764
Short name T962
Test name
Test status
Simulation time 317665901 ps
CPU time 0.95 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206748 kb
Host smart-424cab77-74de-4949-8326-c24d588fe201
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1540119764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_in_transaction.1540119764
Directory /workspace/13.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_length_out_transaction.137785162
Short name T1269
Test name
Test status
Simulation time 196625470 ps
CPU time 0.95 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206756 kb
Host smart-5cc266ab-98f1-40d2-9eef-2a7b804c3f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13778
5162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_length_out_transaction.137785162
Directory /workspace/13.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_max_usb_traffic.519373471
Short name T1415
Test name
Test status
Simulation time 3385979310 ps
CPU time 93.05 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 06:00:07 PM PDT 24
Peak memory 206864 kb
Host smart-9ac4e4cc-0d8a-4337-91c8-d829a892dd8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51937
3471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_max_usb_traffic.519373471
Directory /workspace/13.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/13.usbdev_min_inter_pkt_delay.2808793793
Short name T1304
Test name
Test status
Simulation time 4990018019 ps
CPU time 37.36 seconds
Started Jul 22 05:58:35 PM PDT 24
Finished Jul 22 05:59:13 PM PDT 24
Peak memory 206896 kb
Host smart-aa119ebf-08b0-4f4a-9904-760e6e073d00
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2808793793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_inter_pkt_delay.2808793793
Directory /workspace/13.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/13.usbdev_min_length_in_transaction.16111962
Short name T391
Test name
Test status
Simulation time 190675725 ps
CPU time 0.8 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206752 kb
Host smart-f6d0798b-a470-4b6e-965b-dc4dec1f3ccf
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=16111962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_in_transaction.16111962
Directory /workspace/13.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_min_length_out_transaction.3379796996
Short name T2658
Test name
Test status
Simulation time 207855731 ps
CPU time 0.83 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206704 kb
Host smart-c4874e2f-9c81-4d6d-baf3-042fe1edb523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33797
96996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_min_length_out_transaction.3379796996
Directory /workspace/13.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_nak_trans.1659104388
Short name T134
Test name
Test status
Simulation time 212088962 ps
CPU time 0.88 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206756 kb
Host smart-ffcc40d1-93bb-4345-981a-7ee971b817bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16591
04388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_nak_trans.1659104388
Directory /workspace/13.usbdev_nak_trans/latest

Test location /workspace/coverage/default/13.usbdev_out_iso.1354811918
Short name T1228
Test name
Test status
Simulation time 176610162 ps
CPU time 0.84 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206728 kb
Host smart-f531b584-63e5-42d9-8e29-1165c41affda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13548
11918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_iso.1354811918
Directory /workspace/13.usbdev_out_iso/latest

Test location /workspace/coverage/default/13.usbdev_out_stall.3415696172
Short name T522
Test name
Test status
Simulation time 184475437 ps
CPU time 0.85 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206756 kb
Host smart-232184a2-4bce-486e-b615-a5789d516e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34156
96172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_stall.3415696172
Directory /workspace/13.usbdev_out_stall/latest

Test location /workspace/coverage/default/13.usbdev_out_trans_nak.371172593
Short name T701
Test name
Test status
Simulation time 189880125 ps
CPU time 0.85 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206732 kb
Host smart-3294c5b4-898b-4096-af50-c1f6de6373ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37117
2593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_out_trans_nak.371172593
Directory /workspace/13.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/13.usbdev_pending_in_trans.3955330129
Short name T1238
Test name
Test status
Simulation time 163593607 ps
CPU time 0.77 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206660 kb
Host smart-5c978aba-3c01-4acb-885e-db2d1f40d39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39553
30129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pending_in_trans.3955330129
Directory /workspace/13.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_pinflip.4003306262
Short name T2322
Test name
Test status
Simulation time 203005997 ps
CPU time 0.85 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206744 kb
Host smart-0b12859b-e229-40d6-9922-eee99131b215
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4003306262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_pinflip.4003306262
Directory /workspace/13.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/13.usbdev_phy_config_usb_ref_disable.1788282630
Short name T819
Test name
Test status
Simulation time 144771964 ps
CPU time 0.77 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206748 kb
Host smart-70f17aed-1935-46be-905a-f85189eef716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17882
82630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_config_usb_ref_disable.1788282630
Directory /workspace/13.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/13.usbdev_phy_pins_sense.155992556
Short name T2294
Test name
Test status
Simulation time 34135444 ps
CPU time 0.67 seconds
Started Jul 22 05:58:34 PM PDT 24
Finished Jul 22 05:58:36 PM PDT 24
Peak memory 206760 kb
Host smart-ad96e2ea-277b-43e0-a5e8-a7a0ac996479
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15599
2556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_phy_pins_sense.155992556
Directory /workspace/13.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/13.usbdev_pkt_buffer.94156209
Short name T2064
Test name
Test status
Simulation time 14792695875 ps
CPU time 34.37 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:59:08 PM PDT 24
Peak memory 206920 kb
Host smart-22626f0b-b57a-42be-a3af-e6cf1e06f7ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94156
209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_buffer.94156209
Directory /workspace/13.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/13.usbdev_pkt_received.3129296671
Short name T767
Test name
Test status
Simulation time 176177646 ps
CPU time 0.85 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206764 kb
Host smart-ebca4871-1d0b-4689-89e5-259ca86d274e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31292
96671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_received.3129296671
Directory /workspace/13.usbdev_pkt_received/latest

Test location /workspace/coverage/default/13.usbdev_pkt_sent.1159511856
Short name T2048
Test name
Test status
Simulation time 259201375 ps
CPU time 0.93 seconds
Started Jul 22 05:58:31 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206712 kb
Host smart-dc5a6d33-31cc-4d5c-a8ba-afec014cb3a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11595
11856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_pkt_sent.1159511856
Directory /workspace/13.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/13.usbdev_random_length_in_transaction.4217865491
Short name T902
Test name
Test status
Simulation time 186703411 ps
CPU time 0.85 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206592 kb
Host smart-0f601aa9-961d-45b0-bc18-195a04b8db13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42178
65491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_in_transaction.4217865491
Directory /workspace/13.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/13.usbdev_random_length_out_transaction.1258079192
Short name T1678
Test name
Test status
Simulation time 188069694 ps
CPU time 0.87 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206740 kb
Host smart-4ce38c11-8416-414a-8af7-8395392d0ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12580
79192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_random_length_out_transaction.1258079192
Directory /workspace/13.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/13.usbdev_rx_crc_err.3584922547
Short name T2192
Test name
Test status
Simulation time 140589067 ps
CPU time 0.8 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206724 kb
Host smart-60f74393-a796-4eda-b320-0fac7c72497d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35849
22547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_rx_crc_err.3584922547
Directory /workspace/13.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/13.usbdev_setup_stage.4037676878
Short name T2375
Test name
Test status
Simulation time 154161954 ps
CPU time 0.8 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:31 PM PDT 24
Peak memory 206704 kb
Host smart-85c3d48c-3ebc-40d1-b147-37a3d6afff0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40376
76878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_stage.4037676878
Directory /workspace/13.usbdev_setup_stage/latest

Test location /workspace/coverage/default/13.usbdev_setup_trans_ignored.4068732825
Short name T393
Test name
Test status
Simulation time 180550196 ps
CPU time 0.81 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:32 PM PDT 24
Peak memory 206708 kb
Host smart-5bf736c7-557d-4c67-a3f7-81ba9235bcfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40687
32825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_setup_trans_ignored.4068732825
Directory /workspace/13.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/13.usbdev_smoke.318685771
Short name T1579
Test name
Test status
Simulation time 239222558 ps
CPU time 0.95 seconds
Started Jul 22 05:58:31 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206748 kb
Host smart-2f881650-8ef4-4e14-94f5-866ee02bc081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31868
5771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_smoke.318685771
Directory /workspace/13.usbdev_smoke/latest

Test location /workspace/coverage/default/13.usbdev_spurious_pids_ignored.1512927433
Short name T1660
Test name
Test status
Simulation time 5119386303 ps
CPU time 142.62 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 06:01:03 PM PDT 24
Peak memory 206860 kb
Host smart-74d9ebfc-78c9-4523-b556-ae6d0af876a1
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1512927433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_spurious_pids_ignored.1512927433
Directory /workspace/13.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/13.usbdev_stall_priority_over_nak.1780770014
Short name T2343
Test name
Test status
Simulation time 164748965 ps
CPU time 0.78 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:10 PM PDT 24
Peak memory 206728 kb
Host smart-1ea1c8f0-1a5e-49c2-b3aa-b1d2fd496d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17807
70014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_priority_over_nak.1780770014
Directory /workspace/13.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/13.usbdev_stall_trans.1944612394
Short name T1880
Test name
Test status
Simulation time 198830302 ps
CPU time 0.9 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:31 PM PDT 24
Peak memory 206704 kb
Host smart-34c3e09b-a8b4-45bb-95bb-6ae338c3e388
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19446
12394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stall_trans.1944612394
Directory /workspace/13.usbdev_stall_trans/latest

Test location /workspace/coverage/default/13.usbdev_stream_len_max.2243540614
Short name T1069
Test name
Test status
Simulation time 1273932588 ps
CPU time 2.78 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206944 kb
Host smart-5c1ee08b-e3b6-4b61-b863-66ba654d57e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22435
40614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_stream_len_max.2243540614
Directory /workspace/13.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/13.usbdev_streaming_out.90391356
Short name T565
Test name
Test status
Simulation time 4158073807 ps
CPU time 118.62 seconds
Started Jul 22 05:58:36 PM PDT 24
Finished Jul 22 06:00:35 PM PDT 24
Peak memory 206884 kb
Host smart-79db4ac1-041e-494a-8334-9515e7d30223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90391
356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.usbdev_streaming_out.90391356
Directory /workspace/13.usbdev_streaming_out/latest

Test location /workspace/coverage/default/14.usbdev_alert_test.2387779816
Short name T1554
Test name
Test status
Simulation time 115593890 ps
CPU time 0.74 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:43 PM PDT 24
Peak memory 206720 kb
Host smart-37c3193e-d737-4b6d-9ef2-06dad31f1b03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2387779816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_alert_test.2387779816
Directory /workspace/14.usbdev_alert_test/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_disconnect.295390076
Short name T1334
Test name
Test status
Simulation time 3806058875 ps
CPU time 4.46 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:36 PM PDT 24
Peak memory 206788 kb
Host smart-8a599010-892e-4077-9e75-c26f9760a48e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=295390076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_disconnect.295390076
Directory /workspace/14.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_reset.2522448829
Short name T2669
Test name
Test status
Simulation time 13420566639 ps
CPU time 15.89 seconds
Started Jul 22 05:58:34 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206980 kb
Host smart-4a12dfc1-d2b7-493f-9478-8935b198d7c6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2522448829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_reset.2522448829
Directory /workspace/14.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/14.usbdev_aon_wake_resume.1162147782
Short name T2657
Test name
Test status
Simulation time 23424258287 ps
CPU time 26.65 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:59:07 PM PDT 24
Peak memory 206800 kb
Host smart-167dd056-7516-4a7a-836b-39478055d0cb
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1162147782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_aon_wake_resume.1162147782
Directory /workspace/14.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/14.usbdev_av_buffer.1099023384
Short name T1188
Test name
Test status
Simulation time 152311165 ps
CPU time 0.84 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206732 kb
Host smart-1474164b-673c-421e-b141-daae12ddc944
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10990
23384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_av_buffer.1099023384
Directory /workspace/14.usbdev_av_buffer/latest

Test location /workspace/coverage/default/14.usbdev_bitstuff_err.3176244466
Short name T556
Test name
Test status
Simulation time 142684607 ps
CPU time 0.8 seconds
Started Jul 22 05:58:37 PM PDT 24
Finished Jul 22 05:58:38 PM PDT 24
Peak memory 206752 kb
Host smart-342c4fa7-7a2b-4a44-a56f-1976e7491e31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31762
44466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_bitstuff_err.3176244466
Directory /workspace/14.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_clear.3356569393
Short name T1167
Test name
Test status
Simulation time 477234564 ps
CPU time 1.44 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206656 kb
Host smart-d3d80fd1-e01b-429f-b24e-393512b5efb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33565
69393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_clear.3356569393
Directory /workspace/14.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/14.usbdev_data_toggle_restore.3508070028
Short name T174
Test name
Test status
Simulation time 1439779994 ps
CPU time 3.13 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206760 kb
Host smart-bec26238-3cd8-4aec-ba4c-21fde6d99ecc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35080
70028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_data_toggle_restore.3508070028
Directory /workspace/14.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/14.usbdev_device_address.3965916663
Short name T1302
Test name
Test status
Simulation time 20292031080 ps
CPU time 41.19 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206948 kb
Host smart-b3c272cd-ea13-41a6-8eb5-41bc6892e235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39659
16663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_device_address.3965916663
Directory /workspace/14.usbdev_device_address/latest

Test location /workspace/coverage/default/14.usbdev_disable_endpoint.1478397273
Short name T463
Test name
Test status
Simulation time 324769262 ps
CPU time 1.17 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206756 kb
Host smart-7ccfe14d-f1ae-448c-b6e1-3a44f68009f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14783
97273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disable_endpoint.1478397273
Directory /workspace/14.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/14.usbdev_disconnected.1535640349
Short name T1211
Test name
Test status
Simulation time 241910402 ps
CPU time 0.82 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206744 kb
Host smart-fbd6a138-f4e9-4621-8095-7590351e6c42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15356
40349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_disconnected.1535640349
Directory /workspace/14.usbdev_disconnected/latest

Test location /workspace/coverage/default/14.usbdev_enable.3170483330
Short name T1084
Test name
Test status
Simulation time 42512710 ps
CPU time 0.71 seconds
Started Jul 22 05:58:35 PM PDT 24
Finished Jul 22 05:58:37 PM PDT 24
Peak memory 206752 kb
Host smart-ffdbebd4-d0d6-4ee3-b884-34340f4b3db9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31704
83330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_enable.3170483330
Directory /workspace/14.usbdev_enable/latest

Test location /workspace/coverage/default/14.usbdev_endpoint_access.4173481793
Short name T455
Test name
Test status
Simulation time 987210244 ps
CPU time 2.41 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 05:58:37 PM PDT 24
Peak memory 206936 kb
Host smart-621502e3-3dd7-40d6-ab46-112f859dac7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41734
81793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_endpoint_access.4173481793
Directory /workspace/14.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/14.usbdev_fifo_rst.2807271356
Short name T1971
Test name
Test status
Simulation time 262533508 ps
CPU time 1.67 seconds
Started Jul 22 05:58:31 PM PDT 24
Finished Jul 22 05:58:34 PM PDT 24
Peak memory 206876 kb
Host smart-b88bec55-8e8e-4a5f-8c99-6744638a29d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28072
71356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_fifo_rst.2807271356
Directory /workspace/14.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/14.usbdev_in_iso.973908058
Short name T1230
Test name
Test status
Simulation time 224658181 ps
CPU time 0.89 seconds
Started Jul 22 05:58:34 PM PDT 24
Finished Jul 22 05:58:36 PM PDT 24
Peak memory 206752 kb
Host smart-d4ad37ef-1671-431f-b7e9-e545fc27aa3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97390
8058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_iso.973908058
Directory /workspace/14.usbdev_in_iso/latest

Test location /workspace/coverage/default/14.usbdev_in_stall.3307187788
Short name T2082
Test name
Test status
Simulation time 139583403 ps
CPU time 0.76 seconds
Started Jul 22 05:58:37 PM PDT 24
Finished Jul 22 05:58:38 PM PDT 24
Peak memory 206752 kb
Host smart-eaaeccaf-b737-4fb6-b056-2d40756c7df9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33071
87788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_stall.3307187788
Directory /workspace/14.usbdev_in_stall/latest

Test location /workspace/coverage/default/14.usbdev_in_trans.1097072408
Short name T2108
Test name
Test status
Simulation time 224571795 ps
CPU time 0.87 seconds
Started Jul 22 05:58:32 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206716 kb
Host smart-07662ec0-9050-4f29-8d6e-d60742ad4cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10970
72408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_in_trans.1097072408
Directory /workspace/14.usbdev_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_iso_retraction.1082500243
Short name T991
Test name
Test status
Simulation time 5431845010 ps
CPU time 20.46 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:29 PM PDT 24
Peak memory 206884 kb
Host smart-15b85918-cd6b-4a5f-b800-20e85e74c9f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10825
00243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_iso_retraction.1082500243
Directory /workspace/14.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/14.usbdev_link_in_err.3877311223
Short name T1142
Test name
Test status
Simulation time 248733848 ps
CPU time 0.97 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:32 PM PDT 24
Peak memory 206736 kb
Host smart-c08057ce-47d0-4f4f-a3b9-b4d3ac40136d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38773
11223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_in_err.3877311223
Directory /workspace/14.usbdev_link_in_err/latest

Test location /workspace/coverage/default/14.usbdev_link_resume.2990409767
Short name T1559
Test name
Test status
Simulation time 23320559943 ps
CPU time 23.39 seconds
Started Jul 22 05:58:30 PM PDT 24
Finished Jul 22 05:58:55 PM PDT 24
Peak memory 206780 kb
Host smart-707f02ef-1e26-4a08-bc21-4fffd9e2c6b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29904
09767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_resume.2990409767
Directory /workspace/14.usbdev_link_resume/latest

Test location /workspace/coverage/default/14.usbdev_link_suspend.177531042
Short name T2637
Test name
Test status
Simulation time 3396412692 ps
CPU time 4.02 seconds
Started Jul 22 05:58:35 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206764 kb
Host smart-04afd95b-d86c-4e49-81e9-ff62f9946c38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17753
1042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_link_suspend.177531042
Directory /workspace/14.usbdev_link_suspend/latest

Test location /workspace/coverage/default/14.usbdev_low_speed_traffic.3839857529
Short name T2336
Test name
Test status
Simulation time 7036206526 ps
CPU time 182.72 seconds
Started Jul 22 05:58:33 PM PDT 24
Finished Jul 22 06:01:37 PM PDT 24
Peak memory 206952 kb
Host smart-dade64a1-2671-43d3-84b8-8ec8983413e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38398
57529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_low_speed_traffic.3839857529
Directory /workspace/14.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/14.usbdev_max_inter_pkt_delay.1737782490
Short name T449
Test name
Test status
Simulation time 7506194451 ps
CPU time 72.52 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 206896 kb
Host smart-87086fda-39d6-4d47-b9a4-b55d0d9b7ce0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1737782490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_inter_pkt_delay.1737782490
Directory /workspace/14.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_max_length_in_transaction.2936491903
Short name T1169
Test name
Test status
Simulation time 253089645 ps
CPU time 0.91 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206704 kb
Host smart-dc42b0ab-8043-476b-9846-d9842bcdaf19
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2936491903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_in_transaction.2936491903
Directory /workspace/14.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_length_out_transaction.1918276715
Short name T2448
Test name
Test status
Simulation time 225351357 ps
CPU time 0.89 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206740 kb
Host smart-d3e306df-c780-4d8f-a003-4d24fd38e3ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19182
76715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_length_out_transaction.1918276715
Directory /workspace/14.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_max_usb_traffic.3999218631
Short name T771
Test name
Test status
Simulation time 4760865938 ps
CPU time 35.18 seconds
Started Jul 22 05:58:50 PM PDT 24
Finished Jul 22 05:59:26 PM PDT 24
Peak memory 206552 kb
Host smart-f456f2de-7dee-4371-a75e-cf9c500c30a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39992
18631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_max_usb_traffic.3999218631
Directory /workspace/14.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/14.usbdev_min_inter_pkt_delay.298734077
Short name T1970
Test name
Test status
Simulation time 4962113216 ps
CPU time 36.25 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:59:16 PM PDT 24
Peak memory 206916 kb
Host smart-417e8af5-8b38-4e24-be4e-21b26c6087d5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=298734077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_inter_pkt_delay.298734077
Directory /workspace/14.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/14.usbdev_min_length_in_transaction.1238360627
Short name T2568
Test name
Test status
Simulation time 154118758 ps
CPU time 0.81 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206744 kb
Host smart-c5941de8-2d52-486c-bc70-a96b224e7409
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1238360627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_in_transaction.1238360627
Directory /workspace/14.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_min_length_out_transaction.3628989759
Short name T1227
Test name
Test status
Simulation time 165650206 ps
CPU time 0.82 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206752 kb
Host smart-87fe05ad-ae82-4ba9-9dff-8dc7f66a9cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36289
89759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_min_length_out_transaction.3628989759
Directory /workspace/14.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_nak_trans.3100282065
Short name T115
Test name
Test status
Simulation time 178576085 ps
CPU time 0.88 seconds
Started Jul 22 05:58:41 PM PDT 24
Finished Jul 22 05:58:42 PM PDT 24
Peak memory 206732 kb
Host smart-034bdf16-16cb-47eb-a6c7-0268642a673d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31002
82065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_nak_trans.3100282065
Directory /workspace/14.usbdev_nak_trans/latest

Test location /workspace/coverage/default/14.usbdev_out_iso.596306522
Short name T655
Test name
Test status
Simulation time 189696498 ps
CPU time 0.87 seconds
Started Jul 22 05:58:43 PM PDT 24
Finished Jul 22 05:58:44 PM PDT 24
Peak memory 206748 kb
Host smart-025963f2-1e4d-444a-a124-23d590263484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59630
6522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_iso.596306522
Directory /workspace/14.usbdev_out_iso/latest

Test location /workspace/coverage/default/14.usbdev_out_stall.1277603385
Short name T2373
Test name
Test status
Simulation time 176532318 ps
CPU time 0.79 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206792 kb
Host smart-ea0544f4-e4db-46b9-98a5-9f846211e9fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12776
03385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_stall.1277603385
Directory /workspace/14.usbdev_out_stall/latest

Test location /workspace/coverage/default/14.usbdev_out_trans_nak.597308929
Short name T2732
Test name
Test status
Simulation time 148968989 ps
CPU time 0.8 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:43 PM PDT 24
Peak memory 206716 kb
Host smart-9471c02a-2976-4aeb-8640-8c72540c70e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59730
8929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_out_trans_nak.597308929
Directory /workspace/14.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/14.usbdev_pending_in_trans.2505184533
Short name T460
Test name
Test status
Simulation time 182806495 ps
CPU time 0.86 seconds
Started Jul 22 05:58:50 PM PDT 24
Finished Jul 22 05:58:52 PM PDT 24
Peak memory 206672 kb
Host smart-3aa42e3b-6abb-4896-bc46-5f1a0863081c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25051
84533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pending_in_trans.2505184533
Directory /workspace/14.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_pinflip.747170478
Short name T2439
Test name
Test status
Simulation time 276960025 ps
CPU time 0.92 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206740 kb
Host smart-da42fb98-614b-4549-a743-ce43c4a4f7bf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=747170478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_pinflip.747170478
Directory /workspace/14.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/14.usbdev_phy_config_usb_ref_disable.1581791352
Short name T1752
Test name
Test status
Simulation time 172269476 ps
CPU time 0.85 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206740 kb
Host smart-4c75c31f-87ec-421e-ad73-39cabd1697b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15817
91352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_phy_config_usb_ref_disable.1581791352
Directory /workspace/14.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/14.usbdev_pkt_buffer.3538285574
Short name T1216
Test name
Test status
Simulation time 11044292183 ps
CPU time 24.98 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:59:05 PM PDT 24
Peak memory 206932 kb
Host smart-1b4a2cb1-b834-442c-affc-bafba5ef42b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35382
85574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_buffer.3538285574
Directory /workspace/14.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/14.usbdev_pkt_received.2056167824
Short name T692
Test name
Test status
Simulation time 220365334 ps
CPU time 0.84 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206752 kb
Host smart-71b22842-3f79-49eb-9407-f341ead29a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20561
67824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_received.2056167824
Directory /workspace/14.usbdev_pkt_received/latest

Test location /workspace/coverage/default/14.usbdev_pkt_sent.528471360
Short name T1743
Test name
Test status
Simulation time 215943135 ps
CPU time 0.86 seconds
Started Jul 22 05:58:37 PM PDT 24
Finished Jul 22 05:58:38 PM PDT 24
Peak memory 206752 kb
Host smart-06dadf7a-de14-44dd-8ff8-9bc595e5a8cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52847
1360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_pkt_sent.528471360
Directory /workspace/14.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/14.usbdev_random_length_in_transaction.2603516779
Short name T976
Test name
Test status
Simulation time 227185725 ps
CPU time 0.94 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:43 PM PDT 24
Peak memory 206744 kb
Host smart-9f46c37a-bbc4-421b-a1ad-5738ab8dcdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26035
16779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_in_transaction.2603516779
Directory /workspace/14.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/14.usbdev_random_length_out_transaction.680745664
Short name T1284
Test name
Test status
Simulation time 158132610 ps
CPU time 0.81 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 05:59:33 PM PDT 24
Peak memory 206744 kb
Host smart-1246e87c-e8c0-4ee9-b8a3-96cbb432e734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68074
5664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_random_length_out_transaction.680745664
Directory /workspace/14.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/14.usbdev_rx_crc_err.1757527321
Short name T2065
Test name
Test status
Simulation time 180794213 ps
CPU time 0.79 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206728 kb
Host smart-812979a2-e314-4e00-bbdb-7584b1caaf64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17575
27321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_rx_crc_err.1757527321
Directory /workspace/14.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/14.usbdev_setup_stage.3057875550
Short name T2417
Test name
Test status
Simulation time 192223988 ps
CPU time 0.85 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206864 kb
Host smart-9e05aed2-4fc1-48a8-ba82-2a8c6e181b62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30578
75550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_stage.3057875550
Directory /workspace/14.usbdev_setup_stage/latest

Test location /workspace/coverage/default/14.usbdev_setup_trans_ignored.2527883650
Short name T1727
Test name
Test status
Simulation time 177532914 ps
CPU time 0.86 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206752 kb
Host smart-5c3702d1-5625-4d93-a2d5-c4f6fd0e209f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25278
83650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_setup_trans_ignored.2527883650
Directory /workspace/14.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/14.usbdev_smoke.431175354
Short name T398
Test name
Test status
Simulation time 236565237 ps
CPU time 1.05 seconds
Started Jul 22 05:59:00 PM PDT 24
Finished Jul 22 05:59:02 PM PDT 24
Peak memory 206732 kb
Host smart-6afa7f03-89ac-4278-9ebb-261943b59260
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43117
5354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_smoke.431175354
Directory /workspace/14.usbdev_smoke/latest

Test location /workspace/coverage/default/14.usbdev_spurious_pids_ignored.2068315293
Short name T2416
Test name
Test status
Simulation time 3105573496 ps
CPU time 22.12 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:59:02 PM PDT 24
Peak memory 206932 kb
Host smart-591bdef9-57b2-4a4f-bd98-424116ff6c32
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2068315293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_spurious_pids_ignored.2068315293
Directory /workspace/14.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/14.usbdev_stall_priority_over_nak.1415509441
Short name T2437
Test name
Test status
Simulation time 164777641 ps
CPU time 0.76 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206792 kb
Host smart-ed07a7d1-460d-45ec-9261-04088a5ebdd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14155
09441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_priority_over_nak.1415509441
Directory /workspace/14.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/14.usbdev_stall_trans.2887292472
Short name T1809
Test name
Test status
Simulation time 177740393 ps
CPU time 0.84 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:44 PM PDT 24
Peak memory 206664 kb
Host smart-9e0a99bf-76e9-4862-8585-b335d2a5fad7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28872
92472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stall_trans.2887292472
Directory /workspace/14.usbdev_stall_trans/latest

Test location /workspace/coverage/default/14.usbdev_stream_len_max.2404509090
Short name T1240
Test name
Test status
Simulation time 326472773 ps
CPU time 1.05 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:42 PM PDT 24
Peak memory 206788 kb
Host smart-c7e32c54-264a-46e9-8c7a-f6aeb750d8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24045
09090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_stream_len_max.2404509090
Directory /workspace/14.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/14.usbdev_streaming_out.802018262
Short name T1845
Test name
Test status
Simulation time 5592110480 ps
CPU time 53.54 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:59:33 PM PDT 24
Peak memory 206956 kb
Host smart-0c2a62e9-d58f-4571-ae1b-bb9a2f8a29f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80201
8262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.usbdev_streaming_out.802018262
Directory /workspace/14.usbdev_streaming_out/latest

Test location /workspace/coverage/default/15.usbdev_alert_test.589338216
Short name T733
Test name
Test status
Simulation time 107179166 ps
CPU time 0.74 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206744 kb
Host smart-df90ce43-2e2d-4389-ad4d-69daecf5aefe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=589338216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_alert_test.589338216
Directory /workspace/15.usbdev_alert_test/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_disconnect.439027896
Short name T1411
Test name
Test status
Simulation time 4141957473 ps
CPU time 6.06 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206788 kb
Host smart-a413ed42-0ac4-44f6-82db-bbee30292832
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=439027896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_disconnect.439027896
Directory /workspace/15.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_reset.1529534579
Short name T907
Test name
Test status
Simulation time 13379163561 ps
CPU time 15.53 seconds
Started Jul 22 05:58:43 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206964 kb
Host smart-84be546c-4895-4d1c-820a-006eb93a1c82
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1529534579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_reset.1529534579
Directory /workspace/15.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/15.usbdev_aon_wake_resume.425964082
Short name T211
Test name
Test status
Simulation time 23406721965 ps
CPU time 22.36 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206960 kb
Host smart-d5b04900-9bbf-481a-93d4-9aeb2f03bc52
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=425964082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_aon_wake_resume.425964082
Directory /workspace/15.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/15.usbdev_av_buffer.1511107100
Short name T1145
Test name
Test status
Simulation time 172131743 ps
CPU time 0.79 seconds
Started Jul 22 05:58:37 PM PDT 24
Finished Jul 22 05:58:38 PM PDT 24
Peak memory 206696 kb
Host smart-e938326d-cd0e-4f1f-96f4-073e41574f17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15111
07100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_av_buffer.1511107100
Directory /workspace/15.usbdev_av_buffer/latest

Test location /workspace/coverage/default/15.usbdev_bitstuff_err.3178767780
Short name T1476
Test name
Test status
Simulation time 161273688 ps
CPU time 0.8 seconds
Started Jul 22 05:58:43 PM PDT 24
Finished Jul 22 05:58:45 PM PDT 24
Peak memory 206728 kb
Host smart-1cc101b0-bad9-40d1-8876-a589c84d18da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31787
67780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_bitstuff_err.3178767780
Directory /workspace/15.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_clear.1261383887
Short name T1959
Test name
Test status
Simulation time 283870973 ps
CPU time 1.06 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:44 PM PDT 24
Peak memory 206648 kb
Host smart-deb2a92f-6964-4b09-90b9-ea87eb1e2f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12613
83887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_clear.1261383887
Directory /workspace/15.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/15.usbdev_data_toggle_restore.1379510706
Short name T1325
Test name
Test status
Simulation time 956769319 ps
CPU time 2.17 seconds
Started Jul 22 05:58:37 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206832 kb
Host smart-6aba478a-498f-4f91-99d9-da42153f7edc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13795
10706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_data_toggle_restore.1379510706
Directory /workspace/15.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/15.usbdev_device_address.2218741612
Short name T658
Test name
Test status
Simulation time 10063012174 ps
CPU time 21.19 seconds
Started Jul 22 05:58:50 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206884 kb
Host smart-ba2dfc5e-43ad-42f6-98f2-70a3b5ae35cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22187
41612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_device_address.2218741612
Directory /workspace/15.usbdev_device_address/latest

Test location /workspace/coverage/default/15.usbdev_disable_endpoint.4008140814
Short name T801
Test name
Test status
Simulation time 341013361 ps
CPU time 1.11 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206740 kb
Host smart-ba405d40-781e-44d7-ace0-4cfd594caaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40081
40814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disable_endpoint.4008140814
Directory /workspace/15.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/15.usbdev_disconnected.654351836
Short name T1613
Test name
Test status
Simulation time 174664838 ps
CPU time 0.78 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:43 PM PDT 24
Peak memory 206728 kb
Host smart-2bcb92e7-e95e-4652-b759-9615f6f8ed80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65435
1836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_disconnected.654351836
Directory /workspace/15.usbdev_disconnected/latest

Test location /workspace/coverage/default/15.usbdev_enable.216845547
Short name T1267
Test name
Test status
Simulation time 39405740 ps
CPU time 0.64 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206620 kb
Host smart-9d1b7af4-68b1-4245-9b16-69dfd82e15c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21684
5547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_enable.216845547
Directory /workspace/15.usbdev_enable/latest

Test location /workspace/coverage/default/15.usbdev_endpoint_access.3672509218
Short name T2041
Test name
Test status
Simulation time 795663948 ps
CPU time 1.91 seconds
Started Jul 22 05:58:43 PM PDT 24
Finished Jul 22 05:58:45 PM PDT 24
Peak memory 206880 kb
Host smart-e22097ad-9c65-45f9-83fd-af925402f9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36725
09218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_endpoint_access.3672509218
Directory /workspace/15.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/15.usbdev_fifo_rst.469351683
Short name T2560
Test name
Test status
Simulation time 257888600 ps
CPU time 2.07 seconds
Started Jul 22 05:58:50 PM PDT 24
Finished Jul 22 05:58:53 PM PDT 24
Peak memory 206312 kb
Host smart-c9535dca-7c8f-46a2-a755-609c788be384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46935
1683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_fifo_rst.469351683
Directory /workspace/15.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/15.usbdev_in_iso.2416419797
Short name T1778
Test name
Test status
Simulation time 218171196 ps
CPU time 0.86 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:44 PM PDT 24
Peak memory 206656 kb
Host smart-617c8d53-ce32-47d5-94dd-094ebbba8fe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24164
19797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_iso.2416419797
Directory /workspace/15.usbdev_in_iso/latest

Test location /workspace/coverage/default/15.usbdev_in_stall.3117080288
Short name T323
Test name
Test status
Simulation time 172438787 ps
CPU time 0.77 seconds
Started Jul 22 05:58:40 PM PDT 24
Finished Jul 22 05:58:42 PM PDT 24
Peak memory 206772 kb
Host smart-1a59c53a-2eae-48dc-b838-d5ebdac71462
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31170
80288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_stall.3117080288
Directory /workspace/15.usbdev_in_stall/latest

Test location /workspace/coverage/default/15.usbdev_in_trans.2795185759
Short name T1530
Test name
Test status
Simulation time 237772200 ps
CPU time 0.91 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:42 PM PDT 24
Peak memory 206712 kb
Host smart-bd5ad123-210c-4998-b495-d7dc63450a66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27951
85759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_in_trans.2795185759
Directory /workspace/15.usbdev_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_invalid_sync.2261339393
Short name T1705
Test name
Test status
Simulation time 5179207454 ps
CPU time 143.35 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206832 kb
Host smart-ea39652e-0695-4aa6-af26-4f0396180bb8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2261339393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_invalid_sync.2261339393
Directory /workspace/15.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/15.usbdev_iso_retraction.3426497939
Short name T2646
Test name
Test status
Simulation time 3887057241 ps
CPU time 29.39 seconds
Started Jul 22 05:58:40 PM PDT 24
Finished Jul 22 05:59:10 PM PDT 24
Peak memory 207088 kb
Host smart-e2a907a2-c025-46cc-b6f2-085acb217ede
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34264
97939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_iso_retraction.3426497939
Directory /workspace/15.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/15.usbdev_link_in_err.2274969215
Short name T499
Test name
Test status
Simulation time 302966639 ps
CPU time 1.05 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:42 PM PDT 24
Peak memory 206728 kb
Host smart-25d0273c-df03-4364-9847-80e5d3ce6bc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22749
69215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_in_err.2274969215
Directory /workspace/15.usbdev_link_in_err/latest

Test location /workspace/coverage/default/15.usbdev_link_resume.3660683020
Short name T2262
Test name
Test status
Simulation time 23292246639 ps
CPU time 26.74 seconds
Started Jul 22 05:58:48 PM PDT 24
Finished Jul 22 05:59:16 PM PDT 24
Peak memory 206728 kb
Host smart-4e278bda-4aa4-4ad4-b34b-0162a7436cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36606
83020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_resume.3660683020
Directory /workspace/15.usbdev_link_resume/latest

Test location /workspace/coverage/default/15.usbdev_link_suspend.4141462366
Short name T1953
Test name
Test status
Simulation time 3334040864 ps
CPU time 3.97 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 05:59:36 PM PDT 24
Peak memory 206812 kb
Host smart-19f2f4db-90eb-45b7-b78c-c3b6e870a2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41414
62366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_link_suspend.4141462366
Directory /workspace/15.usbdev_link_suspend/latest

Test location /workspace/coverage/default/15.usbdev_low_speed_traffic.661097011
Short name T2746
Test name
Test status
Simulation time 9275561574 ps
CPU time 63.93 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:59:55 PM PDT 24
Peak memory 206888 kb
Host smart-01dbcc09-3174-486b-a16b-5da5012f0c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66109
7011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_low_speed_traffic.661097011
Directory /workspace/15.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/15.usbdev_max_inter_pkt_delay.3640321360
Short name T2731
Test name
Test status
Simulation time 4030837543 ps
CPU time 37.54 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206888 kb
Host smart-4b7a73a1-1c2f-44a9-b804-7e91cb69c17b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3640321360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_inter_pkt_delay.3640321360
Directory /workspace/15.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_max_length_in_transaction.3155816172
Short name T856
Test name
Test status
Simulation time 243346975 ps
CPU time 0.95 seconds
Started Jul 22 05:58:37 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206748 kb
Host smart-aca4f46e-62e5-4c6c-a5f1-1af725a17fd8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3155816172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_in_transaction.3155816172
Directory /workspace/15.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_length_out_transaction.2026206014
Short name T358
Test name
Test status
Simulation time 198373648 ps
CPU time 0.9 seconds
Started Jul 22 05:58:39 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206628 kb
Host smart-9e7d838d-4c3e-49be-9c77-105fea1ce71c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20262
06014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_length_out_transaction.2026206014
Directory /workspace/15.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_max_usb_traffic.3372236239
Short name T1203
Test name
Test status
Simulation time 6647720271 ps
CPU time 181.72 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 06:01:49 PM PDT 24
Peak memory 206904 kb
Host smart-41fc421f-8f28-48bc-b62b-de79fe7b8773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
36239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_max_usb_traffic.3372236239
Directory /workspace/15.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/15.usbdev_min_inter_pkt_delay.2449427271
Short name T433
Test name
Test status
Simulation time 3248196233 ps
CPU time 23.74 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:59:06 PM PDT 24
Peak memory 206924 kb
Host smart-88202d0a-ae08-45bd-9d2a-db26e713f21a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2449427271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_inter_pkt_delay.2449427271
Directory /workspace/15.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/15.usbdev_min_length_in_transaction.752399742
Short name T1605
Test name
Test status
Simulation time 173081853 ps
CPU time 0.76 seconds
Started Jul 22 05:58:42 PM PDT 24
Finished Jul 22 05:58:43 PM PDT 24
Peak memory 206732 kb
Host smart-f9b679b7-6d0b-40cc-8d3e-90c17f6ca277
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=752399742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_in_transaction.752399742
Directory /workspace/15.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_min_length_out_transaction.2956059865
Short name T1272
Test name
Test status
Simulation time 159193571 ps
CPU time 0.8 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206788 kb
Host smart-3ad2a7e6-cd52-4dfd-b3a9-d3b8e448c1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29560
59865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_min_length_out_transaction.2956059865
Directory /workspace/15.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_nak_trans.1175507727
Short name T116
Test name
Test status
Simulation time 226609184 ps
CPU time 0.82 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206724 kb
Host smart-9b8042f1-4efd-4115-aa78-6e1d6a1a8e2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11755
07727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_nak_trans.1175507727
Directory /workspace/15.usbdev_nak_trans/latest

Test location /workspace/coverage/default/15.usbdev_out_iso.1936094155
Short name T915
Test name
Test status
Simulation time 165672512 ps
CPU time 0.82 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206736 kb
Host smart-ed857a10-3c55-44f1-b326-57a0e7d5bfdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19360
94155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_iso.1936094155
Directory /workspace/15.usbdev_out_iso/latest

Test location /workspace/coverage/default/15.usbdev_out_stall.3541761052
Short name T1518
Test name
Test status
Simulation time 142018299 ps
CPU time 0.76 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206756 kb
Host smart-d3dc1976-e621-4d01-bda9-2f0e2ed3aa9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
61052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_stall.3541761052
Directory /workspace/15.usbdev_out_stall/latest

Test location /workspace/coverage/default/15.usbdev_out_trans_nak.327459801
Short name T1222
Test name
Test status
Simulation time 184241764 ps
CPU time 0.84 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206736 kb
Host smart-1b211075-502b-4cbf-9a0e-f46e4f015dbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32745
9801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_out_trans_nak.327459801
Directory /workspace/15.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/15.usbdev_pending_in_trans.2086460965
Short name T2001
Test name
Test status
Simulation time 200795696 ps
CPU time 0.88 seconds
Started Jul 22 05:58:48 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206736 kb
Host smart-6c9c3bde-7219-4e33-b9fe-2d9372d6c3fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20864
60965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pending_in_trans.2086460965
Directory /workspace/15.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_pinflip.1645216532
Short name T471
Test name
Test status
Simulation time 209380367 ps
CPU time 0.89 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206744 kb
Host smart-c13f0a13-af24-4afb-8330-2d528969738e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1645216532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_pinflip.1645216532
Directory /workspace/15.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/15.usbdev_phy_config_usb_ref_disable.1625063120
Short name T1172
Test name
Test status
Simulation time 145640361 ps
CPU time 0.77 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206704 kb
Host smart-35563004-5c5e-4ac4-a500-5dd2b99cf46d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16250
63120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_config_usb_ref_disable.1625063120
Directory /workspace/15.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/15.usbdev_phy_pins_sense.49386026
Short name T2072
Test name
Test status
Simulation time 38451303 ps
CPU time 0.63 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206704 kb
Host smart-99d9fe30-0838-4fbe-b20d-836fa966c6f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49386
026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_phy_pins_sense.49386026
Directory /workspace/15.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/15.usbdev_pkt_buffer.3398469726
Short name T255
Test name
Test status
Simulation time 22151083153 ps
CPU time 44.06 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:59:31 PM PDT 24
Peak memory 206980 kb
Host smart-ef3990af-52a2-4a0a-847f-149aa9ec32ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33984
69726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_buffer.3398469726
Directory /workspace/15.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/15.usbdev_pkt_received.178501145
Short name T328
Test name
Test status
Simulation time 168173513 ps
CPU time 0.8 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206704 kb
Host smart-40282142-1db0-4c34-9b04-9ea7fd4d1b2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17850
1145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_received.178501145
Directory /workspace/15.usbdev_pkt_received/latest

Test location /workspace/coverage/default/15.usbdev_pkt_sent.2525766709
Short name T2227
Test name
Test status
Simulation time 207191874 ps
CPU time 0.92 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206724 kb
Host smart-50a91794-77f1-4a32-8247-36ab2bba2b6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25257
66709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_pkt_sent.2525766709
Directory /workspace/15.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/15.usbdev_random_length_in_transaction.2927771331
Short name T314
Test name
Test status
Simulation time 205546275 ps
CPU time 0.9 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206744 kb
Host smart-e6120135-807f-40a1-a06e-87330d9d0fdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29277
71331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_in_transaction.2927771331
Directory /workspace/15.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/15.usbdev_random_length_out_transaction.1766711031
Short name T1456
Test name
Test status
Simulation time 219703266 ps
CPU time 0.83 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:46 PM PDT 24
Peak memory 206756 kb
Host smart-df7e224b-16c9-4bfb-be31-a6aa48edf7ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17667
11031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_random_length_out_transaction.1766711031
Directory /workspace/15.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/15.usbdev_rx_crc_err.1270956819
Short name T1716
Test name
Test status
Simulation time 184072669 ps
CPU time 0.87 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206728 kb
Host smart-ad42e25e-563c-430d-b71c-83cc93e023c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12709
56819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_rx_crc_err.1270956819
Directory /workspace/15.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/15.usbdev_setup_stage.4204303999
Short name T1066
Test name
Test status
Simulation time 150685437 ps
CPU time 0.82 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206708 kb
Host smart-6b42d6ea-8fcc-4dd6-86bf-82932693a3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42043
03999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_stage.4204303999
Directory /workspace/15.usbdev_setup_stage/latest

Test location /workspace/coverage/default/15.usbdev_setup_trans_ignored.1138663794
Short name T761
Test name
Test status
Simulation time 155750672 ps
CPU time 0.78 seconds
Started Jul 22 05:59:35 PM PDT 24
Finished Jul 22 05:59:37 PM PDT 24
Peak memory 206732 kb
Host smart-1d270c63-fc9d-4d91-81f7-33cf471f5427
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11386
63794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_setup_trans_ignored.1138663794
Directory /workspace/15.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/15.usbdev_smoke.3074704780
Short name T1460
Test name
Test status
Simulation time 245964421 ps
CPU time 0.93 seconds
Started Jul 22 05:59:18 PM PDT 24
Finished Jul 22 05:59:20 PM PDT 24
Peak memory 206732 kb
Host smart-664af3b7-007b-4ef4-b9c7-ba336aacae23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30747
04780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_smoke.3074704780
Directory /workspace/15.usbdev_smoke/latest

Test location /workspace/coverage/default/15.usbdev_spurious_pids_ignored.2218474969
Short name T152
Test name
Test status
Simulation time 6584438742 ps
CPU time 63.59 seconds
Started Jul 22 05:58:48 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206852 kb
Host smart-ae2e4c6b-6e07-4f84-b118-8568ed1d5d23
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2218474969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_spurious_pids_ignored.2218474969
Directory /workspace/15.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/15.usbdev_stall_priority_over_nak.2049439659
Short name T2562
Test name
Test status
Simulation time 198067526 ps
CPU time 0.89 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206716 kb
Host smart-07fd8c2e-3e0a-4086-bdef-e94b83e1592e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20494
39659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_priority_over_nak.2049439659
Directory /workspace/15.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/15.usbdev_stall_trans.808468479
Short name T374
Test name
Test status
Simulation time 197268408 ps
CPU time 0.82 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206696 kb
Host smart-dbde7683-7c4e-45ac-8d43-02a874a3ef5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80846
8479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stall_trans.808468479
Directory /workspace/15.usbdev_stall_trans/latest

Test location /workspace/coverage/default/15.usbdev_stream_len_max.2721427175
Short name T322
Test name
Test status
Simulation time 1105184372 ps
CPU time 2.32 seconds
Started Jul 22 05:58:50 PM PDT 24
Finished Jul 22 05:58:54 PM PDT 24
Peak memory 206840 kb
Host smart-808c2b4b-97a2-480e-8189-5493c1ff4cc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27214
27175 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_stream_len_max.2721427175
Directory /workspace/15.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/15.usbdev_streaming_out.3088008148
Short name T804
Test name
Test status
Simulation time 3914016676 ps
CPU time 38.56 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 207008 kb
Host smart-2261ccb6-3adc-4503-8f67-e6fd7ca3b814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30880
08148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.usbdev_streaming_out.3088008148
Directory /workspace/15.usbdev_streaming_out/latest

Test location /workspace/coverage/default/16.usbdev_alert_test.2004641588
Short name T1539
Test name
Test status
Simulation time 36615023 ps
CPU time 0.67 seconds
Started Jul 22 05:58:59 PM PDT 24
Finished Jul 22 05:59:01 PM PDT 24
Peak memory 206784 kb
Host smart-99d2969b-8539-4733-a468-a05b0189c291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2004641588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_alert_test.2004641588
Directory /workspace/16.usbdev_alert_test/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_disconnect.1564102423
Short name T1416
Test name
Test status
Simulation time 3710303310 ps
CPU time 4.53 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:53 PM PDT 24
Peak memory 206908 kb
Host smart-33b75cbd-fb7c-43b1-9cce-4f1eac7a6306
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1564102423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_disconnect.1564102423
Directory /workspace/16.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_reset.2901061039
Short name T1812
Test name
Test status
Simulation time 13360568185 ps
CPU time 12.35 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:59:01 PM PDT 24
Peak memory 206768 kb
Host smart-0ad0bd4a-e397-4790-97db-6cc545c5e12a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2901061039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_reset.2901061039
Directory /workspace/16.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/16.usbdev_aon_wake_resume.594595043
Short name T873
Test name
Test status
Simulation time 23336360542 ps
CPU time 22.78 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:59:10 PM PDT 24
Peak memory 206968 kb
Host smart-0052579f-27d2-42e9-a044-68a11272b2f1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=594595043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_aon_wake_resume.594595043
Directory /workspace/16.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/16.usbdev_av_buffer.438330095
Short name T317
Test name
Test status
Simulation time 185917364 ps
CPU time 0.85 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:47 PM PDT 24
Peak memory 206756 kb
Host smart-7911714b-ea57-421f-b5da-5ff11d83a5fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43833
0095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_av_buffer.438330095
Directory /workspace/16.usbdev_av_buffer/latest

Test location /workspace/coverage/default/16.usbdev_bitstuff_err.3555763666
Short name T217
Test name
Test status
Simulation time 184447543 ps
CPU time 0.83 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:48 PM PDT 24
Peak memory 206684 kb
Host smart-596a7bfb-293e-4ff9-a5c8-618f35b8f93f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35557
63666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_bitstuff_err.3555763666
Directory /workspace/16.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_clear.2705968099
Short name T792
Test name
Test status
Simulation time 613843311 ps
CPU time 1.55 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:58:52 PM PDT 24
Peak memory 206880 kb
Host smart-4f62e613-0b08-4928-8f5a-a7fc2bd5a799
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27059
68099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_clear.2705968099
Directory /workspace/16.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/16.usbdev_data_toggle_restore.1498420639
Short name T466
Test name
Test status
Simulation time 1150582479 ps
CPU time 2.84 seconds
Started Jul 22 05:58:48 PM PDT 24
Finished Jul 22 05:58:53 PM PDT 24
Peak memory 206860 kb
Host smart-c6d789c9-94f4-4953-95c6-79c921af5603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14984
20639 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_data_toggle_restore.1498420639
Directory /workspace/16.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/16.usbdev_device_address.448159532
Short name T1777
Test name
Test status
Simulation time 10082310381 ps
CPU time 18.67 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206860 kb
Host smart-f9dffabc-f22c-4820-ad72-caec4d20c207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44815
9532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_device_address.448159532
Directory /workspace/16.usbdev_device_address/latest

Test location /workspace/coverage/default/16.usbdev_disable_endpoint.1896539265
Short name T1345
Test name
Test status
Simulation time 403980539 ps
CPU time 1.4 seconds
Started Jul 22 05:58:50 PM PDT 24
Finished Jul 22 05:58:53 PM PDT 24
Peak memory 206712 kb
Host smart-42ca2e43-8f03-4a84-88b6-791c5933c0b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18965
39265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disable_endpoint.1896539265
Directory /workspace/16.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/16.usbdev_disconnected.3577328964
Short name T1688
Test name
Test status
Simulation time 153013684 ps
CPU time 0.76 seconds
Started Jul 22 05:58:45 PM PDT 24
Finished Jul 22 05:58:46 PM PDT 24
Peak memory 206748 kb
Host smart-1066ccb9-a280-4d30-80aa-9feff0e91bab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35773
28964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_disconnected.3577328964
Directory /workspace/16.usbdev_disconnected/latest

Test location /workspace/coverage/default/16.usbdev_enable.2731979514
Short name T2301
Test name
Test status
Simulation time 40444286 ps
CPU time 0.63 seconds
Started Jul 22 05:58:50 PM PDT 24
Finished Jul 22 05:58:52 PM PDT 24
Peak memory 206688 kb
Host smart-662aa670-4a66-4e32-99ab-a43170f4849f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27319
79514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_enable.2731979514
Directory /workspace/16.usbdev_enable/latest

Test location /workspace/coverage/default/16.usbdev_endpoint_access.1496281317
Short name T1517
Test name
Test status
Simulation time 936506051 ps
CPU time 2.08 seconds
Started Jul 22 05:58:48 PM PDT 24
Finished Jul 22 05:58:52 PM PDT 24
Peak memory 206896 kb
Host smart-2eeb0e50-7a7e-43c1-945c-75541db4fb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14962
81317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_endpoint_access.1496281317
Directory /workspace/16.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/16.usbdev_fifo_rst.2750570920
Short name T1058
Test name
Test status
Simulation time 211135035 ps
CPU time 2.2 seconds
Started Jul 22 05:58:46 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206840 kb
Host smart-1d03d039-b45b-4616-9be6-44e37d055c6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27505
70920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_fifo_rst.2750570920
Directory /workspace/16.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/16.usbdev_in_iso.3807399986
Short name T326
Test name
Test status
Simulation time 277132465 ps
CPU time 0.95 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:58:49 PM PDT 24
Peak memory 206740 kb
Host smart-61280276-5366-4276-80fd-cd016cbf2401
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38073
99986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_iso.3807399986
Directory /workspace/16.usbdev_in_iso/latest

Test location /workspace/coverage/default/16.usbdev_in_stall.4106209463
Short name T2675
Test name
Test status
Simulation time 142751743 ps
CPU time 0.75 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206700 kb
Host smart-b7e37317-eb67-456a-ac01-8e0479de6c74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41062
09463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_stall.4106209463
Directory /workspace/16.usbdev_in_stall/latest

Test location /workspace/coverage/default/16.usbdev_in_trans.738187443
Short name T2531
Test name
Test status
Simulation time 157057231 ps
CPU time 0.81 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206732 kb
Host smart-7baf995f-f71d-4d34-aed3-6caf6a11c749
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73818
7443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_in_trans.738187443
Directory /workspace/16.usbdev_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_invalid_sync.2876620172
Short name T2198
Test name
Test status
Simulation time 5729572996 ps
CPU time 163.68 seconds
Started Jul 22 05:58:49 PM PDT 24
Finished Jul 22 06:01:34 PM PDT 24
Peak memory 206848 kb
Host smart-1a95841d-d195-4fcf-acb2-898589a80162
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2876620172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_invalid_sync.2876620172
Directory /workspace/16.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/16.usbdev_link_in_err.2642765915
Short name T1997
Test name
Test status
Simulation time 205347770 ps
CPU time 0.82 seconds
Started Jul 22 05:58:48 PM PDT 24
Finished Jul 22 05:58:50 PM PDT 24
Peak memory 206740 kb
Host smart-a24559c4-4475-4197-ab17-5a8c9096739e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26427
65915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_in_err.2642765915
Directory /workspace/16.usbdev_link_in_err/latest

Test location /workspace/coverage/default/16.usbdev_link_resume.543835694
Short name T1404
Test name
Test status
Simulation time 23299353170 ps
CPU time 21.36 seconds
Started Jul 22 05:58:47 PM PDT 24
Finished Jul 22 05:59:10 PM PDT 24
Peak memory 206792 kb
Host smart-57021701-b55f-470f-a68f-f16bbde9bb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54383
5694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_resume.543835694
Directory /workspace/16.usbdev_link_resume/latest

Test location /workspace/coverage/default/16.usbdev_link_suspend.773023029
Short name T1313
Test name
Test status
Simulation time 3332917006 ps
CPU time 4.07 seconds
Started Jul 22 05:58:48 PM PDT 24
Finished Jul 22 05:58:53 PM PDT 24
Peak memory 206808 kb
Host smart-6dcd64d9-d8aa-4ea8-8a76-cb3566b46da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77302
3029 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_link_suspend.773023029
Directory /workspace/16.usbdev_link_suspend/latest

Test location /workspace/coverage/default/16.usbdev_low_speed_traffic.1042956185
Short name T2387
Test name
Test status
Simulation time 9776849990 ps
CPU time 257.16 seconds
Started Jul 22 05:58:56 PM PDT 24
Finished Jul 22 06:03:13 PM PDT 24
Peak memory 206952 kb
Host smart-79cc52b5-0909-465a-9330-99e0bafc21bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10429
56185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_low_speed_traffic.1042956185
Directory /workspace/16.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/16.usbdev_max_inter_pkt_delay.759595830
Short name T649
Test name
Test status
Simulation time 5678124700 ps
CPU time 151.83 seconds
Started Jul 22 05:58:59 PM PDT 24
Finished Jul 22 06:01:32 PM PDT 24
Peak memory 206932 kb
Host smart-a8039789-50aa-4c7d-b34e-b394f8386807
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=759595830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_inter_pkt_delay.759595830
Directory /workspace/16.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_max_length_in_transaction.1961899998
Short name T1620
Test name
Test status
Simulation time 238406889 ps
CPU time 0.86 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206720 kb
Host smart-5a261e10-32e9-452e-ab7f-97be2974dcef
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1961899998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_in_transaction.1961899998
Directory /workspace/16.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_length_out_transaction.3598092162
Short name T1835
Test name
Test status
Simulation time 228571468 ps
CPU time 0.9 seconds
Started Jul 22 05:58:55 PM PDT 24
Finished Jul 22 05:58:57 PM PDT 24
Peak memory 206752 kb
Host smart-ec2fa0f7-9e39-41d0-96ee-9c37fc444962
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35980
92162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_length_out_transaction.3598092162
Directory /workspace/16.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_max_usb_traffic.3969048027
Short name T593
Test name
Test status
Simulation time 4705127299 ps
CPU time 33.08 seconds
Started Jul 22 05:59:32 PM PDT 24
Finished Jul 22 06:00:06 PM PDT 24
Peak memory 206932 kb
Host smart-a372a7f4-05e2-4768-b5d1-b4b4d39a7be9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39690
48027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_max_usb_traffic.3969048027
Directory /workspace/16.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/16.usbdev_min_inter_pkt_delay.2856883049
Short name T1171
Test name
Test status
Simulation time 4731242058 ps
CPU time 40.02 seconds
Started Jul 22 05:59:32 PM PDT 24
Finished Jul 22 06:00:13 PM PDT 24
Peak memory 206884 kb
Host smart-86cc8c10-0837-4fe4-a662-e6bf645ff852
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2856883049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_inter_pkt_delay.2856883049
Directory /workspace/16.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/16.usbdev_min_length_in_transaction.51540297
Short name T381
Test name
Test status
Simulation time 151673158 ps
CPU time 0.82 seconds
Started Jul 22 05:59:00 PM PDT 24
Finished Jul 22 05:59:01 PM PDT 24
Peak memory 206744 kb
Host smart-9368b540-40ac-48a2-ab29-7dce13b09cc4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=51540297 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_in_transaction.51540297
Directory /workspace/16.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_min_length_out_transaction.3978106035
Short name T573
Test name
Test status
Simulation time 162924543 ps
CPU time 0.86 seconds
Started Jul 22 05:58:58 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206736 kb
Host smart-0d625370-4ee6-4aef-b57f-bd4b6eea7310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39781
06035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_min_length_out_transaction.3978106035
Directory /workspace/16.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_out_iso.1963798614
Short name T2569
Test name
Test status
Simulation time 281382675 ps
CPU time 0.87 seconds
Started Jul 22 05:58:56 PM PDT 24
Finished Jul 22 05:58:57 PM PDT 24
Peak memory 206696 kb
Host smart-8356fc9d-293e-4e8c-a1d7-ba6007fa1d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19637
98614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_iso.1963798614
Directory /workspace/16.usbdev_out_iso/latest

Test location /workspace/coverage/default/16.usbdev_out_stall.3445780792
Short name T670
Test name
Test status
Simulation time 189674755 ps
CPU time 0.93 seconds
Started Jul 22 05:58:55 PM PDT 24
Finished Jul 22 05:58:56 PM PDT 24
Peak memory 206748 kb
Host smart-9b0851ec-3c9b-4c66-9161-271346a1523b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34457
80792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_stall.3445780792
Directory /workspace/16.usbdev_out_stall/latest

Test location /workspace/coverage/default/16.usbdev_out_trans_nak.1494191859
Short name T339
Test name
Test status
Simulation time 201513347 ps
CPU time 0.82 seconds
Started Jul 22 05:58:58 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206724 kb
Host smart-41d613f4-5c4a-44a9-ac8c-e18ac77db00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14941
91859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_out_trans_nak.1494191859
Directory /workspace/16.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/16.usbdev_pending_in_trans.98456977
Short name T179
Test name
Test status
Simulation time 158105666 ps
CPU time 0.81 seconds
Started Jul 22 05:59:00 PM PDT 24
Finished Jul 22 05:59:02 PM PDT 24
Peak memory 206732 kb
Host smart-0fade958-f5b1-4083-8a13-37de5db912f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98456
977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pending_in_trans.98456977
Directory /workspace/16.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_pinflip.1595107266
Short name T1403
Test name
Test status
Simulation time 247950257 ps
CPU time 0.93 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206668 kb
Host smart-aad9f1c3-2e2f-47ea-8b65-d93cf5767f3c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1595107266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_pinflip.1595107266
Directory /workspace/16.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/16.usbdev_phy_config_usb_ref_disable.3821969998
Short name T2623
Test name
Test status
Simulation time 151369725 ps
CPU time 0.77 seconds
Started Jul 22 05:58:58 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206736 kb
Host smart-b847e9f8-5601-4743-bfc3-2a8a3e58f9e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38219
69998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_config_usb_ref_disable.3821969998
Directory /workspace/16.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/16.usbdev_phy_pins_sense.295376707
Short name T1603
Test name
Test status
Simulation time 45764472 ps
CPU time 0.66 seconds
Started Jul 22 05:58:59 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206684 kb
Host smart-b7caf025-a126-40c7-a424-b1f347340681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29537
6707 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_phy_pins_sense.295376707
Directory /workspace/16.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/16.usbdev_pkt_buffer.2320298877
Short name T244
Test name
Test status
Simulation time 11831176824 ps
CPU time 26.32 seconds
Started Jul 22 05:58:55 PM PDT 24
Finished Jul 22 05:59:22 PM PDT 24
Peak memory 206924 kb
Host smart-6aef24c8-6ba9-42c0-a5c3-330b4aac2315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23202
98877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_buffer.2320298877
Directory /workspace/16.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/16.usbdev_pkt_received.1463585466
Short name T745
Test name
Test status
Simulation time 195119807 ps
CPU time 0.86 seconds
Started Jul 22 05:58:58 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206736 kb
Host smart-887030bd-33e4-41c6-b0c7-779eeaeda708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14635
85466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_received.1463585466
Directory /workspace/16.usbdev_pkt_received/latest

Test location /workspace/coverage/default/16.usbdev_pkt_sent.182381070
Short name T858
Test name
Test status
Simulation time 186849769 ps
CPU time 0.86 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206704 kb
Host smart-782dc467-030a-4278-93e4-9780f1cc656f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18238
1070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_pkt_sent.182381070
Directory /workspace/16.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/16.usbdev_random_length_in_transaction.1692140451
Short name T1906
Test name
Test status
Simulation time 239470527 ps
CPU time 0.92 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206744 kb
Host smart-79b2be8d-1afb-4baa-880f-f541df20c6e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16921
40451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_in_transaction.1692140451
Directory /workspace/16.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/16.usbdev_random_length_out_transaction.3053746182
Short name T2524
Test name
Test status
Simulation time 185327605 ps
CPU time 0.85 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:58 PM PDT 24
Peak memory 206736 kb
Host smart-d2aa3735-f185-4c83-97d9-661d0d35cd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30537
46182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_random_length_out_transaction.3053746182
Directory /workspace/16.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/16.usbdev_rx_crc_err.121022878
Short name T1544
Test name
Test status
Simulation time 143549639 ps
CPU time 0.83 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206804 kb
Host smart-5b9c926a-4616-492c-8ad7-c7421da2c18b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12102
2878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_rx_crc_err.121022878
Directory /workspace/16.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/16.usbdev_setup_stage.1501868278
Short name T1670
Test name
Test status
Simulation time 156003271 ps
CPU time 0.74 seconds
Started Jul 22 05:58:54 PM PDT 24
Finished Jul 22 05:58:56 PM PDT 24
Peak memory 206748 kb
Host smart-3fc56c27-7523-4a7c-baed-53b3eec1b829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15018
68278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_stage.1501868278
Directory /workspace/16.usbdev_setup_stage/latest

Test location /workspace/coverage/default/16.usbdev_setup_trans_ignored.2944601615
Short name T1762
Test name
Test status
Simulation time 153140584 ps
CPU time 0.84 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:58 PM PDT 24
Peak memory 206748 kb
Host smart-d731b2ec-f442-4960-b4ca-b930a82bb3a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29446
01615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_setup_trans_ignored.2944601615
Directory /workspace/16.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/16.usbdev_smoke.2757696099
Short name T1900
Test name
Test status
Simulation time 219828954 ps
CPU time 0.9 seconds
Started Jul 22 05:59:01 PM PDT 24
Finished Jul 22 05:59:02 PM PDT 24
Peak memory 206692 kb
Host smart-867acabc-eaa5-46f3-8701-7e9c0ccf4c85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27576
96099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_smoke.2757696099
Directory /workspace/16.usbdev_smoke/latest

Test location /workspace/coverage/default/16.usbdev_spurious_pids_ignored.2034649778
Short name T1074
Test name
Test status
Simulation time 6051276430 ps
CPU time 41.05 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206940 kb
Host smart-8368f369-3218-4018-bb6c-f7137c39a2e9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2034649778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_spurious_pids_ignored.2034649778
Directory /workspace/16.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/16.usbdev_stall_priority_over_nak.1446413801
Short name T454
Test name
Test status
Simulation time 163210841 ps
CPU time 0.82 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:58:58 PM PDT 24
Peak memory 206772 kb
Host smart-1b953965-97ef-410a-994d-1f1d10af874b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14464
13801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_priority_over_nak.1446413801
Directory /workspace/16.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/16.usbdev_stall_trans.3959472176
Short name T1730
Test name
Test status
Simulation time 254196523 ps
CPU time 0.85 seconds
Started Jul 22 05:59:06 PM PDT 24
Finished Jul 22 05:59:08 PM PDT 24
Peak memory 206704 kb
Host smart-5fd37ab1-a5d6-4cba-a520-4cb77056755c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39594
72176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stall_trans.3959472176
Directory /workspace/16.usbdev_stall_trans/latest

Test location /workspace/coverage/default/16.usbdev_stream_len_max.3627416487
Short name T1053
Test name
Test status
Simulation time 771198330 ps
CPU time 1.75 seconds
Started Jul 22 05:58:56 PM PDT 24
Finished Jul 22 05:58:58 PM PDT 24
Peak memory 206876 kb
Host smart-b405858e-a89c-4cb9-b2dc-6e7593bd4733
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36274
16487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_stream_len_max.3627416487
Directory /workspace/16.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/16.usbdev_streaming_out.2693962534
Short name T412
Test name
Test status
Simulation time 4249289411 ps
CPU time 39.69 seconds
Started Jul 22 05:58:57 PM PDT 24
Finished Jul 22 05:59:37 PM PDT 24
Peak memory 206888 kb
Host smart-029dd1a7-eb5c-4133-b8b1-b926348098f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26939
62534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.usbdev_streaming_out.2693962534
Directory /workspace/16.usbdev_streaming_out/latest

Test location /workspace/coverage/default/17.usbdev_alert_test.1978835146
Short name T1847
Test name
Test status
Simulation time 46993691 ps
CPU time 0.68 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:43 PM PDT 24
Peak memory 206692 kb
Host smart-e69563ce-eae6-429d-8c29-6e4b4521a108
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1978835146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_alert_test.1978835146
Directory /workspace/17.usbdev_alert_test/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_disconnect.824851419
Short name T1816
Test name
Test status
Simulation time 4476940882 ps
CPU time 5.59 seconds
Started Jul 22 05:58:59 PM PDT 24
Finished Jul 22 05:59:06 PM PDT 24
Peak memory 206948 kb
Host smart-98211116-6826-49b6-bcf5-f0d33273b071
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=824851419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_disconnect.824851419
Directory /workspace/17.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_reset.3191367601
Short name T2671
Test name
Test status
Simulation time 13349305633 ps
CPU time 12.91 seconds
Started Jul 22 05:58:55 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206776 kb
Host smart-f6f6e5a4-ef09-4dde-b0ea-4f89a474cb22
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3191367601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_reset.3191367601
Directory /workspace/17.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/17.usbdev_aon_wake_resume.70858079
Short name T1402
Test name
Test status
Simulation time 23377836447 ps
CPU time 25.91 seconds
Started Jul 22 05:58:58 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206800 kb
Host smart-aece8226-7d1b-4488-adcb-1fc7a0b0b540
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=70858079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_aon_wake_resume.70858079
Directory /workspace/17.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/17.usbdev_av_buffer.59747883
Short name T1818
Test name
Test status
Simulation time 166509174 ps
CPU time 0.83 seconds
Started Jul 22 05:58:59 PM PDT 24
Finished Jul 22 05:59:01 PM PDT 24
Peak memory 206712 kb
Host smart-ee6aaf31-fa6c-46d9-b5db-765bbc0a16ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59747
883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_av_buffer.59747883
Directory /workspace/17.usbdev_av_buffer/latest

Test location /workspace/coverage/default/17.usbdev_bitstuff_err.4206657671
Short name T2571
Test name
Test status
Simulation time 181545989 ps
CPU time 0.84 seconds
Started Jul 22 05:58:58 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206744 kb
Host smart-4334f4c4-240b-459a-9bb8-de75284f6d7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42066
57671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_bitstuff_err.4206657671
Directory /workspace/17.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/17.usbdev_data_toggle_clear.1923525666
Short name T2592
Test name
Test status
Simulation time 422509774 ps
CPU time 1.36 seconds
Started Jul 22 05:58:55 PM PDT 24
Finished Jul 22 05:58:57 PM PDT 24
Peak memory 206744 kb
Host smart-3b7605c8-1486-478b-a168-7d035ec0236e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19235
25666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_data_toggle_clear.1923525666
Directory /workspace/17.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/17.usbdev_device_address.1262532028
Short name T1745
Test name
Test status
Simulation time 19199356360 ps
CPU time 37.57 seconds
Started Jul 22 05:58:56 PM PDT 24
Finished Jul 22 05:59:34 PM PDT 24
Peak memory 207076 kb
Host smart-e844ef27-925f-461c-8ffe-a6adb267e0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12625
32028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_device_address.1262532028
Directory /workspace/17.usbdev_device_address/latest

Test location /workspace/coverage/default/17.usbdev_disable_endpoint.1752959809
Short name T1337
Test name
Test status
Simulation time 374358961 ps
CPU time 1.16 seconds
Started Jul 22 05:58:55 PM PDT 24
Finished Jul 22 05:58:57 PM PDT 24
Peak memory 206908 kb
Host smart-1e132ed2-9c42-4456-a904-6cd8db0c39e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17529
59809 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disable_endpoint.1752959809
Directory /workspace/17.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/17.usbdev_disconnected.1345945449
Short name T2182
Test name
Test status
Simulation time 142577892 ps
CPU time 0.76 seconds
Started Jul 22 05:59:10 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206752 kb
Host smart-7ea3c2d4-402a-40ee-8aac-4311863b821d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13459
45449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_disconnected.1345945449
Directory /workspace/17.usbdev_disconnected/latest

Test location /workspace/coverage/default/17.usbdev_enable.3317119856
Short name T1396
Test name
Test status
Simulation time 40361961 ps
CPU time 0.64 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206740 kb
Host smart-fedc25f4-4c4d-418e-8a7b-668eae7a43c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33171
19856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_enable.3317119856
Directory /workspace/17.usbdev_enable/latest

Test location /workspace/coverage/default/17.usbdev_endpoint_access.3484107196
Short name T904
Test name
Test status
Simulation time 897873000 ps
CPU time 2.04 seconds
Started Jul 22 05:59:07 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206840 kb
Host smart-d047aa4c-25c6-452b-a288-8f8544fdef39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34841
07196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_endpoint_access.3484107196
Directory /workspace/17.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/17.usbdev_fifo_rst.401770407
Short name T1890
Test name
Test status
Simulation time 372268696 ps
CPU time 2.27 seconds
Started Jul 22 05:59:10 PM PDT 24
Finished Jul 22 05:59:13 PM PDT 24
Peak memory 206848 kb
Host smart-cea09aea-61f5-46a7-bbf5-c711453ea201
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40177
0407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_fifo_rst.401770407
Directory /workspace/17.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/17.usbdev_in_iso.1476975949
Short name T1639
Test name
Test status
Simulation time 219433758 ps
CPU time 0.9 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:42 PM PDT 24
Peak memory 206760 kb
Host smart-e4b82ebd-367a-4bb9-acd5-9b4fe5eda823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14769
75949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_iso.1476975949
Directory /workspace/17.usbdev_in_iso/latest

Test location /workspace/coverage/default/17.usbdev_in_stall.3624941363
Short name T2718
Test name
Test status
Simulation time 152328429 ps
CPU time 0.8 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206780 kb
Host smart-e093d4ea-8336-4d06-913d-adc30c5f15e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36249
41363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_stall.3624941363
Directory /workspace/17.usbdev_in_stall/latest

Test location /workspace/coverage/default/17.usbdev_in_trans.1492745714
Short name T1887
Test name
Test status
Simulation time 233348787 ps
CPU time 0.87 seconds
Started Jul 22 05:59:10 PM PDT 24
Finished Jul 22 05:59:11 PM PDT 24
Peak memory 206760 kb
Host smart-b564e8f6-a384-4ef4-b588-a13166cb1249
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
45714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_in_trans.1492745714
Directory /workspace/17.usbdev_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_invalid_sync.1308741977
Short name T575
Test name
Test status
Simulation time 7763489631 ps
CPU time 225.78 seconds
Started Jul 22 05:59:13 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206904 kb
Host smart-ab5bfb5e-5ded-4ad3-a189-2db16503221d
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1308741977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_invalid_sync.1308741977
Directory /workspace/17.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/17.usbdev_iso_retraction.2012779949
Short name T212
Test name
Test status
Simulation time 3730754094 ps
CPU time 11.45 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:28 PM PDT 24
Peak memory 206892 kb
Host smart-5cca6c78-4f30-4b8a-8038-95642ab1f246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20127
79949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_iso_retraction.2012779949
Directory /workspace/17.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/17.usbdev_link_in_err.572023271
Short name T1286
Test name
Test status
Simulation time 185973920 ps
CPU time 0.84 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206712 kb
Host smart-f5f42ed0-c49a-49fc-9b96-34a1e184c78e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57202
3271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_in_err.572023271
Directory /workspace/17.usbdev_link_in_err/latest

Test location /workspace/coverage/default/17.usbdev_link_resume.448588033
Short name T2641
Test name
Test status
Simulation time 23322753353 ps
CPU time 28.83 seconds
Started Jul 22 05:59:10 PM PDT 24
Finished Jul 22 05:59:40 PM PDT 24
Peak memory 206772 kb
Host smart-0a7f4038-2356-4c15-836f-a2e0d136e009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44858
8033 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_resume.448588033
Directory /workspace/17.usbdev_link_resume/latest

Test location /workspace/coverage/default/17.usbdev_link_suspend.1425940092
Short name T502
Test name
Test status
Simulation time 3260906182 ps
CPU time 3.98 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:13 PM PDT 24
Peak memory 206836 kb
Host smart-f9b366df-a803-4e0e-b8d2-79374397ed0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14259
40092 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_link_suspend.1425940092
Directory /workspace/17.usbdev_link_suspend/latest

Test location /workspace/coverage/default/17.usbdev_low_speed_traffic.2605861600
Short name T1394
Test name
Test status
Simulation time 11488204221 ps
CPU time 88.28 seconds
Started Jul 22 05:59:07 PM PDT 24
Finished Jul 22 06:00:36 PM PDT 24
Peak memory 206984 kb
Host smart-5e025f65-7585-44f7-93cc-ebad77e09c0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26058
61600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_low_speed_traffic.2605861600
Directory /workspace/17.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/17.usbdev_max_inter_pkt_delay.2860339868
Short name T1610
Test name
Test status
Simulation time 5744184472 ps
CPU time 42.63 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 206828 kb
Host smart-1d5a35c3-7d1b-4571-b34a-79458aceb952
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2860339868 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_inter_pkt_delay.2860339868
Directory /workspace/17.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_max_length_in_transaction.3902617275
Short name T2527
Test name
Test status
Simulation time 288969528 ps
CPU time 0.95 seconds
Started Jul 22 05:59:14 PM PDT 24
Finished Jul 22 05:59:15 PM PDT 24
Peak memory 206740 kb
Host smart-0de3a827-ca77-434f-a62d-4b3d3fe215a5
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3902617275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_in_transaction.3902617275
Directory /workspace/17.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_length_out_transaction.2494355744
Short name T2055
Test name
Test status
Simulation time 192906999 ps
CPU time 0.87 seconds
Started Jul 22 05:59:10 PM PDT 24
Finished Jul 22 05:59:11 PM PDT 24
Peak memory 206704 kb
Host smart-b64dc71b-d4fd-4f63-b3ba-0343e96160e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24943
55744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_length_out_transaction.2494355744
Directory /workspace/17.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_max_usb_traffic.4285364943
Short name T2404
Test name
Test status
Simulation time 5952259983 ps
CPU time 41.17 seconds
Started Jul 22 05:59:10 PM PDT 24
Finished Jul 22 05:59:51 PM PDT 24
Peak memory 206816 kb
Host smart-10e89624-4a16-478f-b625-218a1e6800f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42853
64943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_max_usb_traffic.4285364943
Directory /workspace/17.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/17.usbdev_min_inter_pkt_delay.2534266517
Short name T2608
Test name
Test status
Simulation time 7200953634 ps
CPU time 50.33 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 06:00:08 PM PDT 24
Peak memory 206880 kb
Host smart-266929c0-66b3-4ed8-b977-3dc93e3d05e3
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2534266517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_inter_pkt_delay.2534266517
Directory /workspace/17.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/17.usbdev_min_length_in_transaction.1559633319
Short name T768
Test name
Test status
Simulation time 151280898 ps
CPU time 0.75 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206756 kb
Host smart-72c002c5-2290-4693-b5e7-7d2a2e5a0993
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1559633319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_in_transaction.1559633319
Directory /workspace/17.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_min_length_out_transaction.1651529581
Short name T1551
Test name
Test status
Simulation time 148799640 ps
CPU time 0.77 seconds
Started Jul 22 05:59:06 PM PDT 24
Finished Jul 22 05:59:08 PM PDT 24
Peak memory 206748 kb
Host smart-c04bc243-57e3-485f-8ff2-1a6e7d6705c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16515
29581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_min_length_out_transaction.1651529581
Directory /workspace/17.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_out_iso.3313423117
Short name T2267
Test name
Test status
Simulation time 191980279 ps
CPU time 0.85 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206676 kb
Host smart-20d447be-4e55-4a02-a103-8fc832029a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33134
23117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_iso.3313423117
Directory /workspace/17.usbdev_out_iso/latest

Test location /workspace/coverage/default/17.usbdev_out_stall.2898739775
Short name T647
Test name
Test status
Simulation time 171012837 ps
CPU time 0.82 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:10 PM PDT 24
Peak memory 206728 kb
Host smart-455e2ec6-c146-4f6c-9086-7852a2dbc1cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28987
39775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_stall.2898739775
Directory /workspace/17.usbdev_out_stall/latest

Test location /workspace/coverage/default/17.usbdev_out_trans_nak.396632774
Short name T2654
Test name
Test status
Simulation time 179152761 ps
CPU time 0.83 seconds
Started Jul 22 05:59:07 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206736 kb
Host smart-5fc01875-16bb-4a07-bdcd-c1e6342f5966
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39663
2774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_out_trans_nak.396632774
Directory /workspace/17.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/17.usbdev_pending_in_trans.3970820561
Short name T420
Test name
Test status
Simulation time 175881712 ps
CPU time 0.79 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206756 kb
Host smart-5d35146c-9eb6-43b6-80ad-e6292bce1dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39708
20561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pending_in_trans.3970820561
Directory /workspace/17.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_pinflip.2693570891
Short name T84
Test name
Test status
Simulation time 226493013 ps
CPU time 0.91 seconds
Started Jul 22 05:59:18 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206756 kb
Host smart-0c95f766-a83c-41ef-b602-d7ef10117131
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2693570891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_pinflip.2693570891
Directory /workspace/17.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/17.usbdev_phy_config_usb_ref_disable.3648323367
Short name T2596
Test name
Test status
Simulation time 157872878 ps
CPU time 0.75 seconds
Started Jul 22 05:59:11 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206664 kb
Host smart-c33ad47e-7346-4af6-8021-d3c3e605ff0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36483
23367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_config_usb_ref_disable.3648323367
Directory /workspace/17.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/17.usbdev_phy_pins_sense.3612428935
Short name T1001
Test name
Test status
Simulation time 55031593 ps
CPU time 0.71 seconds
Started Jul 22 05:59:07 PM PDT 24
Finished Jul 22 05:59:08 PM PDT 24
Peak memory 206676 kb
Host smart-25453ea0-cf3e-4eb1-8b02-1353b87b49ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36124
28935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_phy_pins_sense.3612428935
Directory /workspace/17.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/17.usbdev_pkt_buffer.2517628740
Short name T690
Test name
Test status
Simulation time 6569000737 ps
CPU time 14.33 seconds
Started Jul 22 05:59:23 PM PDT 24
Finished Jul 22 05:59:38 PM PDT 24
Peak memory 206920 kb
Host smart-f944d86f-e612-425a-9a40-973a138a7862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25176
28740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_buffer.2517628740
Directory /workspace/17.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/17.usbdev_pkt_received.542508289
Short name T965
Test name
Test status
Simulation time 190079523 ps
CPU time 0.85 seconds
Started Jul 22 05:59:09 PM PDT 24
Finished Jul 22 05:59:11 PM PDT 24
Peak memory 206724 kb
Host smart-a5724764-9133-40f6-bbd0-ffab716dfc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54250
8289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_received.542508289
Directory /workspace/17.usbdev_pkt_received/latest

Test location /workspace/coverage/default/17.usbdev_pkt_sent.3311733212
Short name T1608
Test name
Test status
Simulation time 198412072 ps
CPU time 0.88 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206676 kb
Host smart-7cebfd23-377d-4b76-bd6a-4d1b4662591b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33117
33212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_pkt_sent.3311733212
Directory /workspace/17.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/17.usbdev_random_length_in_transaction.647905604
Short name T2279
Test name
Test status
Simulation time 232592314 ps
CPU time 0.98 seconds
Started Jul 22 05:59:05 PM PDT 24
Finished Jul 22 05:59:06 PM PDT 24
Peak memory 206892 kb
Host smart-5a7182cf-91d6-415c-8c36-cb3d52059b2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64790
5604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_in_transaction.647905604
Directory /workspace/17.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/17.usbdev_random_length_out_transaction.1017338926
Short name T559
Test name
Test status
Simulation time 189666080 ps
CPU time 0.85 seconds
Started Jul 22 05:59:22 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206732 kb
Host smart-afa40246-f55f-42b5-ac12-3685f96e0b31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10173
38926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_random_length_out_transaction.1017338926
Directory /workspace/17.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/17.usbdev_rx_crc_err.2848512147
Short name T2265
Test name
Test status
Simulation time 200953226 ps
CPU time 0.87 seconds
Started Jul 22 05:59:07 PM PDT 24
Finished Jul 22 05:59:09 PM PDT 24
Peak memory 206732 kb
Host smart-919921f1-a89c-4a43-9989-66e17bc5239d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28485
12147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_rx_crc_err.2848512147
Directory /workspace/17.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/17.usbdev_setup_stage.3406296373
Short name T660
Test name
Test status
Simulation time 145265354 ps
CPU time 0.82 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206748 kb
Host smart-67a8466c-8ccb-4afc-baf6-6450e41d3cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
96373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_stage.3406296373
Directory /workspace/17.usbdev_setup_stage/latest

Test location /workspace/coverage/default/17.usbdev_setup_trans_ignored.1986463346
Short name T2706
Test name
Test status
Simulation time 152979312 ps
CPU time 0.85 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206712 kb
Host smart-da87a242-0fff-4da6-b7d1-cf399d3d7a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19864
63346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_setup_trans_ignored.1986463346
Directory /workspace/17.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/17.usbdev_smoke.1179382052
Short name T2492
Test name
Test status
Simulation time 225326171 ps
CPU time 0.9 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:10 PM PDT 24
Peak memory 206752 kb
Host smart-d70be981-7666-427b-9120-e0b182aff28f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11793
82052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_smoke.1179382052
Directory /workspace/17.usbdev_smoke/latest

Test location /workspace/coverage/default/17.usbdev_spurious_pids_ignored.2262580172
Short name T2423
Test name
Test status
Simulation time 4256322565 ps
CPU time 30.77 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:54 PM PDT 24
Peak memory 206964 kb
Host smart-9d1722fc-c40e-478f-a9bd-08ebcb4040bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2262580172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_spurious_pids_ignored.2262580172
Directory /workspace/17.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/17.usbdev_stall_priority_over_nak.3478979640
Short name T1494
Test name
Test status
Simulation time 210788234 ps
CPU time 0.95 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 05:59:30 PM PDT 24
Peak memory 206692 kb
Host smart-02cdd1ff-4ad8-447c-b721-7d1dff921457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34789
79640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_priority_over_nak.3478979640
Directory /workspace/17.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/17.usbdev_stall_trans.402070879
Short name T1669
Test name
Test status
Simulation time 159788263 ps
CPU time 0.78 seconds
Started Jul 22 05:59:19 PM PDT 24
Finished Jul 22 05:59:21 PM PDT 24
Peak memory 206624 kb
Host smart-04d94016-0c30-4b9b-a649-6581318d8ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40207
0879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stall_trans.402070879
Directory /workspace/17.usbdev_stall_trans/latest

Test location /workspace/coverage/default/17.usbdev_stream_len_max.3572142865
Short name T1103
Test name
Test status
Simulation time 1194842386 ps
CPU time 2.45 seconds
Started Jul 22 05:59:14 PM PDT 24
Finished Jul 22 05:59:18 PM PDT 24
Peak memory 206880 kb
Host smart-8a4d5958-3203-4987-a241-6add397241d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35721
42865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_stream_len_max.3572142865
Directory /workspace/17.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/17.usbdev_streaming_out.2129367384
Short name T1300
Test name
Test status
Simulation time 4254180106 ps
CPU time 40.19 seconds
Started Jul 22 05:59:12 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206904 kb
Host smart-5bee585b-52a0-420c-a2b2-74ca7ed7f270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21293
67384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.usbdev_streaming_out.2129367384
Directory /workspace/17.usbdev_streaming_out/latest

Test location /workspace/coverage/default/18.usbdev_alert_test.2067549462
Short name T1499
Test name
Test status
Simulation time 52963065 ps
CPU time 0.67 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 05:59:18 PM PDT 24
Peak memory 206772 kb
Host smart-e23c9dee-d76d-4b60-a8dd-2c34843bc1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2067549462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_alert_test.2067549462
Directory /workspace/18.usbdev_alert_test/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_disconnect.1277286562
Short name T1176
Test name
Test status
Simulation time 3516328373 ps
CPU time 3.87 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:26 PM PDT 24
Peak memory 206964 kb
Host smart-84d8adb7-cf3f-4084-bacd-e742e1b33544
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1277286562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_disconnect.1277286562
Directory /workspace/18.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_reset.991301840
Short name T824
Test name
Test status
Simulation time 13318739510 ps
CPU time 13.44 seconds
Started Jul 22 05:59:12 PM PDT 24
Finished Jul 22 05:59:26 PM PDT 24
Peak memory 206968 kb
Host smart-654c4357-f545-485b-9f04-7ffff16cb77e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=991301840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_reset.991301840
Directory /workspace/18.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/18.usbdev_aon_wake_resume.2688360247
Short name T2445
Test name
Test status
Simulation time 23375808070 ps
CPU time 30.72 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:57 PM PDT 24
Peak memory 206796 kb
Host smart-8e5f5af2-8e60-4e25-9e84-9835f1f35063
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2688360247 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_aon_wake_resume.2688360247
Directory /workspace/18.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/18.usbdev_av_buffer.801657256
Short name T614
Test name
Test status
Simulation time 148216557 ps
CPU time 0.79 seconds
Started Jul 22 06:00:33 PM PDT 24
Finished Jul 22 06:00:35 PM PDT 24
Peak memory 206728 kb
Host smart-ff346929-6185-4d40-8051-479a56d55e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80165
7256 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_av_buffer.801657256
Directory /workspace/18.usbdev_av_buffer/latest

Test location /workspace/coverage/default/18.usbdev_bitstuff_err.1066818193
Short name T1578
Test name
Test status
Simulation time 155027530 ps
CPU time 0.83 seconds
Started Jul 22 05:59:06 PM PDT 24
Finished Jul 22 05:59:08 PM PDT 24
Peak memory 206744 kb
Host smart-5f39f184-fb70-4590-9fed-05191bd8dc87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10668
18193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_bitstuff_err.1066818193
Directory /workspace/18.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_clear.3790555641
Short name T1814
Test name
Test status
Simulation time 366704957 ps
CPU time 1.25 seconds
Started Jul 22 05:59:27 PM PDT 24
Finished Jul 22 05:59:29 PM PDT 24
Peak memory 206732 kb
Host smart-b61d1f4b-c999-4445-a2f6-13a2817b098a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37905
55641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_clear.3790555641
Directory /workspace/18.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/18.usbdev_data_toggle_restore.2323248264
Short name T1029
Test name
Test status
Simulation time 834268023 ps
CPU time 1.89 seconds
Started Jul 22 05:59:13 PM PDT 24
Finished Jul 22 05:59:16 PM PDT 24
Peak memory 206876 kb
Host smart-805d6618-2d15-488a-b897-e3f42a679d7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23232
48264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_data_toggle_restore.2323248264
Directory /workspace/18.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/18.usbdev_device_address.1094385677
Short name T2519
Test name
Test status
Simulation time 19277824317 ps
CPU time 31.68 seconds
Started Jul 22 05:59:12 PM PDT 24
Finished Jul 22 05:59:45 PM PDT 24
Peak memory 206948 kb
Host smart-14ee506a-07b7-45ee-bd98-4fb8571df16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10943
85677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_device_address.1094385677
Directory /workspace/18.usbdev_device_address/latest

Test location /workspace/coverage/default/18.usbdev_disable_endpoint.1539913078
Short name T1417
Test name
Test status
Simulation time 477715045 ps
CPU time 1.51 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206744 kb
Host smart-fece0829-ac5d-46e3-bdb7-a1dc8d9690cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15399
13078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disable_endpoint.1539913078
Directory /workspace/18.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/18.usbdev_disconnected.242105504
Short name T1810
Test name
Test status
Simulation time 168402561 ps
CPU time 0.8 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:22 PM PDT 24
Peak memory 206668 kb
Host smart-0e8125a2-8b66-4845-a305-85d025de5839
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24210
5504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_disconnected.242105504
Directory /workspace/18.usbdev_disconnected/latest

Test location /workspace/coverage/default/18.usbdev_enable.3158623917
Short name T399
Test name
Test status
Simulation time 38272169 ps
CPU time 0.67 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 05:59:10 PM PDT 24
Peak memory 206736 kb
Host smart-6a45abb9-e170-4143-808f-5af671ea79b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31586
23917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_enable.3158623917
Directory /workspace/18.usbdev_enable/latest

Test location /workspace/coverage/default/18.usbdev_endpoint_access.3295357467
Short name T2443
Test name
Test status
Simulation time 771511420 ps
CPU time 2.1 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 207024 kb
Host smart-b2e38dbe-b1ba-44e7-88d6-41a7c332750a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32953
57467 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_endpoint_access.3295357467
Directory /workspace/18.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/18.usbdev_fifo_rst.3703818819
Short name T914
Test name
Test status
Simulation time 187807123 ps
CPU time 2.24 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206876 kb
Host smart-9e86349c-7830-4dd9-8287-d97c09344e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37038
18819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_fifo_rst.3703818819
Directory /workspace/18.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/18.usbdev_in_iso.2528421158
Short name T495
Test name
Test status
Simulation time 254119088 ps
CPU time 0.98 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206780 kb
Host smart-3034cf57-9a13-4b8d-98e4-c315461df7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25284
21158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_iso.2528421158
Directory /workspace/18.usbdev_in_iso/latest

Test location /workspace/coverage/default/18.usbdev_in_stall.2569616160
Short name T2655
Test name
Test status
Simulation time 169881724 ps
CPU time 0.77 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:27 PM PDT 24
Peak memory 206720 kb
Host smart-84cf989b-ffcc-40a5-8259-8bb24d8a93e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25696
16160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_stall.2569616160
Directory /workspace/18.usbdev_in_stall/latest

Test location /workspace/coverage/default/18.usbdev_in_trans.848830607
Short name T887
Test name
Test status
Simulation time 185393463 ps
CPU time 0.89 seconds
Started Jul 22 05:59:12 PM PDT 24
Finished Jul 22 05:59:13 PM PDT 24
Peak memory 206740 kb
Host smart-2ff66d95-0632-4e09-8464-5f042c7fb699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84883
0607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_in_trans.848830607
Directory /workspace/18.usbdev_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_iso_retraction.4132189494
Short name T1266
Test name
Test status
Simulation time 11363398440 ps
CPU time 32.81 seconds
Started Jul 22 05:59:19 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 206904 kb
Host smart-62965401-e346-4bcf-9c62-639f78460416
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41321
89494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_iso_retraction.4132189494
Directory /workspace/18.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/18.usbdev_link_in_err.4201149318
Short name T1531
Test name
Test status
Simulation time 151440810 ps
CPU time 0.79 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:27 PM PDT 24
Peak memory 206720 kb
Host smart-cc96a2a0-294f-462e-be34-80d9b17c464d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42011
49318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_in_err.4201149318
Directory /workspace/18.usbdev_link_in_err/latest

Test location /workspace/coverage/default/18.usbdev_link_resume.1635432298
Short name T713
Test name
Test status
Simulation time 23330807756 ps
CPU time 23.28 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:45 PM PDT 24
Peak memory 206732 kb
Host smart-850dc343-81cf-456f-8c1a-1130b2ce6564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16354
32298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_resume.1635432298
Directory /workspace/18.usbdev_link_resume/latest

Test location /workspace/coverage/default/18.usbdev_link_suspend.2964079263
Short name T2451
Test name
Test status
Simulation time 3329600933 ps
CPU time 3.89 seconds
Started Jul 22 05:59:14 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206800 kb
Host smart-0dfd8a9d-786d-479f-a24a-8f04e8580dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29640
79263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_link_suspend.2964079263
Directory /workspace/18.usbdev_link_suspend/latest

Test location /workspace/coverage/default/18.usbdev_low_speed_traffic.3848148663
Short name T1045
Test name
Test status
Simulation time 6413136102 ps
CPU time 62.01 seconds
Started Jul 22 05:59:09 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206960 kb
Host smart-98147c9a-42f2-4b7a-be1a-f28c6396791b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38481
48663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_low_speed_traffic.3848148663
Directory /workspace/18.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/18.usbdev_max_inter_pkt_delay.636231124
Short name T1591
Test name
Test status
Simulation time 6602183944 ps
CPU time 180.06 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206876 kb
Host smart-d0e21939-21ed-4cf9-a836-eb56141543ee
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=636231124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_inter_pkt_delay.636231124
Directory /workspace/18.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_max_length_in_transaction.2607453121
Short name T1177
Test name
Test status
Simulation time 271323979 ps
CPU time 0.92 seconds
Started Jul 22 05:59:27 PM PDT 24
Finished Jul 22 05:59:29 PM PDT 24
Peak memory 206744 kb
Host smart-7b3923cd-f8fa-4641-be4d-7c8f5d51f943
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2607453121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_in_transaction.2607453121
Directory /workspace/18.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_length_out_transaction.4272997993
Short name T1099
Test name
Test status
Simulation time 200192740 ps
CPU time 0.82 seconds
Started Jul 22 05:59:23 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206748 kb
Host smart-f853fa89-3c80-4306-97c2-fd1a9df3f18e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42729
97993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_length_out_transaction.4272997993
Directory /workspace/18.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_max_usb_traffic.4094182693
Short name T1271
Test name
Test status
Simulation time 4610212624 ps
CPU time 44.24 seconds
Started Jul 22 05:59:14 PM PDT 24
Finished Jul 22 05:59:59 PM PDT 24
Peak memory 206896 kb
Host smart-f7138c48-71d3-45c7-8015-3f610697a638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40941
82693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_max_usb_traffic.4094182693
Directory /workspace/18.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/18.usbdev_min_inter_pkt_delay.3035293718
Short name T729
Test name
Test status
Simulation time 3270061125 ps
CPU time 89.98 seconds
Started Jul 22 05:59:08 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206888 kb
Host smart-ffc25f1c-349b-4a45-be30-061856fda2ef
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3035293718 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_inter_pkt_delay.3035293718
Directory /workspace/18.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/18.usbdev_min_length_in_transaction.3763958032
Short name T2232
Test name
Test status
Simulation time 181761030 ps
CPU time 0.81 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206756 kb
Host smart-99ccfabf-f364-49e8-a232-2d8ecf8630fc
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3763958032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_in_transaction.3763958032
Directory /workspace/18.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_min_length_out_transaction.2992885742
Short name T1205
Test name
Test status
Simulation time 144379930 ps
CPU time 0.76 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:28 PM PDT 24
Peak memory 206600 kb
Host smart-ed40a943-6ef3-4748-9317-dab083080331
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29928
85742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_min_length_out_transaction.2992885742
Directory /workspace/18.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_nak_trans.686728200
Short name T132
Test name
Test status
Simulation time 214381736 ps
CPU time 0.87 seconds
Started Jul 22 05:59:13 PM PDT 24
Finished Jul 22 05:59:14 PM PDT 24
Peak memory 206744 kb
Host smart-2fc547c4-1021-4967-9fba-d2862ef88fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68672
8200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_nak_trans.686728200
Directory /workspace/18.usbdev_nak_trans/latest

Test location /workspace/coverage/default/18.usbdev_out_iso.4288062800
Short name T588
Test name
Test status
Simulation time 144279456 ps
CPU time 0.8 seconds
Started Jul 22 05:59:10 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206628 kb
Host smart-a24407bc-f4b2-4112-964f-6116307c94ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880
62800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_iso.4288062800
Directory /workspace/18.usbdev_out_iso/latest

Test location /workspace/coverage/default/18.usbdev_out_stall.1840603783
Short name T1231
Test name
Test status
Simulation time 185085742 ps
CPU time 0.87 seconds
Started Jul 22 05:59:13 PM PDT 24
Finished Jul 22 05:59:14 PM PDT 24
Peak memory 206736 kb
Host smart-307f30a4-51e9-4291-b718-665f113a3948
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18406
03783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_stall.1840603783
Directory /workspace/18.usbdev_out_stall/latest

Test location /workspace/coverage/default/18.usbdev_out_trans_nak.3721268773
Short name T1348
Test name
Test status
Simulation time 185191453 ps
CPU time 0.8 seconds
Started Jul 22 05:59:12 PM PDT 24
Finished Jul 22 05:59:13 PM PDT 24
Peak memory 206728 kb
Host smart-1f87bfe0-c531-4d94-a881-46918171d9f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37212
68773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_out_trans_nak.3721268773
Directory /workspace/18.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/18.usbdev_pending_in_trans.3237128192
Short name T1541
Test name
Test status
Simulation time 145454899 ps
CPU time 0.82 seconds
Started Jul 22 05:59:17 PM PDT 24
Finished Jul 22 05:59:19 PM PDT 24
Peak memory 206788 kb
Host smart-c50dc138-4ab5-4596-9a98-100ff1559ee7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32371
28192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pending_in_trans.3237128192
Directory /workspace/18.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_pinflip.3162036978
Short name T892
Test name
Test status
Simulation time 215141606 ps
CPU time 0.96 seconds
Started Jul 22 05:59:14 PM PDT 24
Finished Jul 22 05:59:15 PM PDT 24
Peak memory 206740 kb
Host smart-be19d4d7-43e2-45d6-a9e2-61385e9d6a38
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3162036978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_pinflip.3162036978
Directory /workspace/18.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/18.usbdev_phy_config_usb_ref_disable.2339328285
Short name T1116
Test name
Test status
Simulation time 152606107 ps
CPU time 0.75 seconds
Started Jul 22 05:59:11 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206656 kb
Host smart-eeedc376-432a-4531-b69c-1e8d5ff96011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23393
28285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_config_usb_ref_disable.2339328285
Directory /workspace/18.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/18.usbdev_phy_pins_sense.4175051336
Short name T1095
Test name
Test status
Simulation time 43566530 ps
CPU time 0.67 seconds
Started Jul 22 05:59:19 PM PDT 24
Finished Jul 22 05:59:20 PM PDT 24
Peak memory 206552 kb
Host smart-2b5aca15-3e6d-4177-8ab9-9bf55f7bb235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41750
51336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_phy_pins_sense.4175051336
Directory /workspace/18.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/18.usbdev_pkt_buffer.3044736611
Short name T1938
Test name
Test status
Simulation time 8548254151 ps
CPU time 19.19 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206980 kb
Host smart-8a109bc3-dccf-4aca-8e46-da4a21cb9946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30447
36611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_buffer.3044736611
Directory /workspace/18.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/18.usbdev_pkt_received.361953649
Short name T2025
Test name
Test status
Simulation time 212416305 ps
CPU time 0.87 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:28 PM PDT 24
Peak memory 206724 kb
Host smart-47b8a4b7-8356-42a9-ae01-acfc07ad6eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36195
3649 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_received.361953649
Directory /workspace/18.usbdev_pkt_received/latest

Test location /workspace/coverage/default/18.usbdev_pkt_sent.63517385
Short name T2645
Test name
Test status
Simulation time 182356756 ps
CPU time 0.87 seconds
Started Jul 22 05:59:16 PM PDT 24
Finished Jul 22 05:59:18 PM PDT 24
Peak memory 206864 kb
Host smart-a4b83a1a-4254-4767-b6c7-d861593f1cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63517
385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_pkt_sent.63517385
Directory /workspace/18.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/18.usbdev_random_length_in_transaction.888880638
Short name T356
Test name
Test status
Simulation time 184619305 ps
CPU time 0.85 seconds
Started Jul 22 05:59:12 PM PDT 24
Finished Jul 22 05:59:14 PM PDT 24
Peak memory 206720 kb
Host smart-6391d35e-2f9c-4fb6-98eb-f1dd6982f6d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88888
0638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_in_transaction.888880638
Directory /workspace/18.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/18.usbdev_random_length_out_transaction.4146378787
Short name T2359
Test name
Test status
Simulation time 170565139 ps
CPU time 0.81 seconds
Started Jul 22 05:59:19 PM PDT 24
Finished Jul 22 05:59:21 PM PDT 24
Peak memory 206612 kb
Host smart-3b5732f1-2166-4230-bf41-1cbedd8f1ead
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
78787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_random_length_out_transaction.4146378787
Directory /workspace/18.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/18.usbdev_rx_crc_err.1536052665
Short name T966
Test name
Test status
Simulation time 197625169 ps
CPU time 0.85 seconds
Started Jul 22 05:59:13 PM PDT 24
Finished Jul 22 05:59:15 PM PDT 24
Peak memory 206752 kb
Host smart-b245e559-e061-4c3c-89bc-51f171d65213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15360
52665 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_rx_crc_err.1536052665
Directory /workspace/18.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/18.usbdev_setup_stage.1042341759
Short name T1344
Test name
Test status
Simulation time 157954935 ps
CPU time 0.8 seconds
Started Jul 22 05:59:11 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206656 kb
Host smart-d39e43c7-9063-47aa-9a7a-a8f2cc7d2ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10423
41759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_stage.1042341759
Directory /workspace/18.usbdev_setup_stage/latest

Test location /workspace/coverage/default/18.usbdev_setup_trans_ignored.3049554881
Short name T429
Test name
Test status
Simulation time 156371677 ps
CPU time 0.77 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206748 kb
Host smart-edfbb03f-ad7c-43cd-9de8-092d0b7e0619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30495
54881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_setup_trans_ignored.3049554881
Directory /workspace/18.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/18.usbdev_smoke.2894276485
Short name T1129
Test name
Test status
Simulation time 226338840 ps
CPU time 0.99 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206740 kb
Host smart-5731caee-46c8-4ce8-a705-3bc91608d3db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28942
76485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_smoke.2894276485
Directory /workspace/18.usbdev_smoke/latest

Test location /workspace/coverage/default/18.usbdev_spurious_pids_ignored.806937091
Short name T2651
Test name
Test status
Simulation time 6511867011 ps
CPU time 55.9 seconds
Started Jul 22 05:59:24 PM PDT 24
Finished Jul 22 06:00:21 PM PDT 24
Peak memory 206876 kb
Host smart-32cf3aa8-8537-4d91-b2bf-60382c8d725d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=806937091 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_spurious_pids_ignored.806937091
Directory /workspace/18.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/18.usbdev_stall_priority_over_nak.730953022
Short name T2015
Test name
Test status
Simulation time 149232518 ps
CPU time 0.79 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206724 kb
Host smart-e867b9b3-0ced-4744-918f-0596c485ce5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73095
3022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_priority_over_nak.730953022
Directory /workspace/18.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/18.usbdev_stall_trans.3750290848
Short name T376
Test name
Test status
Simulation time 164507350 ps
CPU time 0.81 seconds
Started Jul 22 05:59:13 PM PDT 24
Finished Jul 22 05:59:15 PM PDT 24
Peak memory 206752 kb
Host smart-a11b1b2c-7f93-4f1f-8478-5067d289745f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37502
90848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stall_trans.3750290848
Directory /workspace/18.usbdev_stall_trans/latest

Test location /workspace/coverage/default/18.usbdev_stream_len_max.3995721523
Short name T1449
Test name
Test status
Simulation time 1078580652 ps
CPU time 2.33 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206860 kb
Host smart-fe223646-016f-4490-8f6c-f983a6f89b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39957
21523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_stream_len_max.3995721523
Directory /workspace/18.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/18.usbdev_streaming_out.2052351714
Short name T1679
Test name
Test status
Simulation time 3203879320 ps
CPU time 30.34 seconds
Started Jul 22 05:59:13 PM PDT 24
Finished Jul 22 05:59:44 PM PDT 24
Peak memory 206880 kb
Host smart-5c95fdd7-2961-49ba-8487-4f38d4e2b81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20523
51714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.usbdev_streaming_out.2052351714
Directory /workspace/18.usbdev_streaming_out/latest

Test location /workspace/coverage/default/19.usbdev_alert_test.646394962
Short name T2701
Test name
Test status
Simulation time 50279093 ps
CPU time 0.66 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206704 kb
Host smart-6bfb61c7-f13e-42a3-b7ff-a363aae85c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=646394962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_alert_test.646394962
Directory /workspace/19.usbdev_alert_test/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_reset.1529773135
Short name T1912
Test name
Test status
Simulation time 13355772505 ps
CPU time 13.15 seconds
Started Jul 22 05:59:24 PM PDT 24
Finished Jul 22 05:59:38 PM PDT 24
Peak memory 206816 kb
Host smart-53bbd0bc-8e64-4d3f-b28b-b459c2951e05
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1529773135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_reset.1529773135
Directory /workspace/19.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/19.usbdev_aon_wake_resume.2330301309
Short name T1435
Test name
Test status
Simulation time 23422186284 ps
CPU time 28.36 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:55 PM PDT 24
Peak memory 206936 kb
Host smart-32af6474-c6e0-4920-9460-8b31f4625c64
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2330301309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_aon_wake_resume.2330301309
Directory /workspace/19.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/19.usbdev_av_buffer.897853816
Short name T926
Test name
Test status
Simulation time 149088592 ps
CPU time 0.8 seconds
Started Jul 22 05:59:15 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206744 kb
Host smart-422cbae5-6d04-42c3-b7f8-f29d152a9c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89785
3816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_av_buffer.897853816
Directory /workspace/19.usbdev_av_buffer/latest

Test location /workspace/coverage/default/19.usbdev_bitstuff_err.2270677578
Short name T1954
Test name
Test status
Simulation time 190984073 ps
CPU time 0.84 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:22 PM PDT 24
Peak memory 206732 kb
Host smart-39a997d8-0f6d-49a0-9b7b-5cf19e403ab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22706
77578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_bitstuff_err.2270677578
Directory /workspace/19.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_clear.3638849309
Short name T652
Test name
Test status
Simulation time 284223667 ps
CPU time 1.01 seconds
Started Jul 22 05:59:23 PM PDT 24
Finished Jul 22 05:59:25 PM PDT 24
Peak memory 206744 kb
Host smart-865ccee9-68c1-4279-9eb6-af5e8c042371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36388
49309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_clear.3638849309
Directory /workspace/19.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/19.usbdev_data_toggle_restore.3824984153
Short name T2595
Test name
Test status
Simulation time 573894131 ps
CPU time 1.48 seconds
Started Jul 22 05:59:51 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206748 kb
Host smart-5b7b4006-5d25-40f5-87e3-c93d7fb7170e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38249
84153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_data_toggle_restore.3824984153
Directory /workspace/19.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/19.usbdev_device_address.2462513043
Short name T1378
Test name
Test status
Simulation time 22364033270 ps
CPU time 41.23 seconds
Started Jul 22 05:59:19 PM PDT 24
Finished Jul 22 06:00:01 PM PDT 24
Peak memory 206908 kb
Host smart-e096946a-32d2-4285-8f3f-f8c3d1e8cf80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24625
13043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_device_address.2462513043
Directory /workspace/19.usbdev_device_address/latest

Test location /workspace/coverage/default/19.usbdev_disable_endpoint.3146881810
Short name T1037
Test name
Test status
Simulation time 500751777 ps
CPU time 1.42 seconds
Started Jul 22 05:59:27 PM PDT 24
Finished Jul 22 05:59:29 PM PDT 24
Peak memory 206740 kb
Host smart-00e407b8-d695-4d9c-a769-c66027108a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31468
81810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disable_endpoint.3146881810
Directory /workspace/19.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/19.usbdev_disconnected.2987451907
Short name T2573
Test name
Test status
Simulation time 155044907 ps
CPU time 0.78 seconds
Started Jul 22 05:59:19 PM PDT 24
Finished Jul 22 05:59:20 PM PDT 24
Peak memory 206672 kb
Host smart-ca00c05c-ef03-4f71-a7f0-f3b90c6fc27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29874
51907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_disconnected.2987451907
Directory /workspace/19.usbdev_disconnected/latest

Test location /workspace/coverage/default/19.usbdev_enable.3801315048
Short name T1444
Test name
Test status
Simulation time 41023996 ps
CPU time 0.67 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:27 PM PDT 24
Peak memory 206736 kb
Host smart-240bea70-4739-4775-bd67-426db91d8a78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38013
15048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_enable.3801315048
Directory /workspace/19.usbdev_enable/latest

Test location /workspace/coverage/default/19.usbdev_endpoint_access.3439581781
Short name T1221
Test name
Test status
Simulation time 868009089 ps
CPU time 1.96 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206812 kb
Host smart-89a76642-fbf8-44b7-80d9-2b3765ad2bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34395
81781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_endpoint_access.3439581781
Directory /workspace/19.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/19.usbdev_fifo_rst.612176883
Short name T2102
Test name
Test status
Simulation time 254162459 ps
CPU time 2.05 seconds
Started Jul 22 05:59:19 PM PDT 24
Finished Jul 22 05:59:22 PM PDT 24
Peak memory 206888 kb
Host smart-1742a3b5-8a91-4729-aba0-ffe985ca3fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61217
6883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_fifo_rst.612176883
Directory /workspace/19.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/19.usbdev_in_iso.288650040
Short name T931
Test name
Test status
Simulation time 155633739 ps
CPU time 0.89 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:28 PM PDT 24
Peak memory 206732 kb
Host smart-56c0c442-5329-4128-94b5-649ece4b8e64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28865
0040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_iso.288650040
Directory /workspace/19.usbdev_in_iso/latest

Test location /workspace/coverage/default/19.usbdev_in_stall.2919231219
Short name T2178
Test name
Test status
Simulation time 156519631 ps
CPU time 0.78 seconds
Started Jul 22 05:59:24 PM PDT 24
Finished Jul 22 05:59:25 PM PDT 24
Peak memory 206704 kb
Host smart-0fc17b72-fa86-453d-af06-e0b100472b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29192
31219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_stall.2919231219
Directory /workspace/19.usbdev_in_stall/latest

Test location /workspace/coverage/default/19.usbdev_in_trans.3642925384
Short name T2748
Test name
Test status
Simulation time 204883699 ps
CPU time 0.88 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:22 PM PDT 24
Peak memory 206692 kb
Host smart-d18f6adb-b513-4ce0-a52b-546c93868d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36429
25384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_in_trans.3642925384
Directory /workspace/19.usbdev_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_invalid_sync.1187058381
Short name T1584
Test name
Test status
Simulation time 9144439298 ps
CPU time 258.23 seconds
Started Jul 22 05:59:24 PM PDT 24
Finished Jul 22 06:03:43 PM PDT 24
Peak memory 206936 kb
Host smart-5b5f4842-41e3-41ea-b50e-26b38f8f3921
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1187058381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_invalid_sync.1187058381
Directory /workspace/19.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/19.usbdev_iso_retraction.3365970094
Short name T385
Test name
Test status
Simulation time 12159137221 ps
CPU time 38.53 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206928 kb
Host smart-e0dcfafd-7b0c-48ce-9057-f1f988ed0265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
70094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_iso_retraction.3365970094
Directory /workspace/19.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/19.usbdev_link_in_err.363891181
Short name T1215
Test name
Test status
Simulation time 259151234 ps
CPU time 0.93 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206664 kb
Host smart-dcc4c52f-8258-4a11-8c51-6100e9139a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36389
1181 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_in_err.363891181
Directory /workspace/19.usbdev_link_in_err/latest

Test location /workspace/coverage/default/19.usbdev_link_resume.1430137836
Short name T312
Test name
Test status
Simulation time 23290600608 ps
CPU time 22.21 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:49 PM PDT 24
Peak memory 206800 kb
Host smart-1f9b1dfc-8e52-4d67-a242-2e5b176df754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14301
37836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_resume.1430137836
Directory /workspace/19.usbdev_link_resume/latest

Test location /workspace/coverage/default/19.usbdev_link_suspend.3483810372
Short name T1233
Test name
Test status
Simulation time 3293740343 ps
CPU time 3.88 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:14 PM PDT 24
Peak memory 206556 kb
Host smart-fd560502-eac9-4aaf-a666-1094074d31c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34838
10372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_link_suspend.3483810372
Directory /workspace/19.usbdev_link_suspend/latest

Test location /workspace/coverage/default/19.usbdev_max_inter_pkt_delay.692823688
Short name T1013
Test name
Test status
Simulation time 5060073058 ps
CPU time 35.47 seconds
Started Jul 22 05:59:51 PM PDT 24
Finished Jul 22 06:00:27 PM PDT 24
Peak memory 206888 kb
Host smart-1fb14cc5-7fb3-4b4a-90cd-8addb9e58622
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=692823688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_inter_pkt_delay.692823688
Directory /workspace/19.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_max_length_in_transaction.3782370698
Short name T2525
Test name
Test status
Simulation time 233878265 ps
CPU time 0.9 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206748 kb
Host smart-cae2330f-02bd-481d-976d-9e3517e76bbd
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3782370698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_in_transaction.3782370698
Directory /workspace/19.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_length_out_transaction.2912360757
Short name T1431
Test name
Test status
Simulation time 204209293 ps
CPU time 1 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:28 PM PDT 24
Peak memory 206744 kb
Host smart-f1b29435-fa95-4756-bc1d-544c49edb49d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29123
60757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_length_out_transaction.2912360757
Directory /workspace/19.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_max_usb_traffic.3608253080
Short name T2432
Test name
Test status
Simulation time 6151251671 ps
CPU time 158.58 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206656 kb
Host smart-d000d409-8ae9-43bc-80ae-48a221287a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36082
53080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_max_usb_traffic.3608253080
Directory /workspace/19.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/19.usbdev_min_inter_pkt_delay.2111186168
Short name T2241
Test name
Test status
Simulation time 7989302658 ps
CPU time 56.88 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206932 kb
Host smart-504f54ca-0103-45aa-bde7-43ea75204b13
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2111186168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_inter_pkt_delay.2111186168
Directory /workspace/19.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/19.usbdev_min_length_in_transaction.2900258977
Short name T1101
Test name
Test status
Simulation time 171369627 ps
CPU time 0.83 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206732 kb
Host smart-8bb855d1-65f3-4068-973a-2098105a5063
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2900258977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_in_transaction.2900258977
Directory /workspace/19.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_min_length_out_transaction.1495290683
Short name T1759
Test name
Test status
Simulation time 177701324 ps
CPU time 0.8 seconds
Started Jul 22 05:59:24 PM PDT 24
Finished Jul 22 05:59:26 PM PDT 24
Peak memory 206748 kb
Host smart-48b41249-dc84-40f7-9be8-41434440c1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14952
90683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_min_length_out_transaction.1495290683
Directory /workspace/19.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_nak_trans.3002223720
Short name T1946
Test name
Test status
Simulation time 202547037 ps
CPU time 0.85 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206628 kb
Host smart-c7bfda54-030e-432c-8b55-41e996db8fdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30022
23720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_nak_trans.3002223720
Directory /workspace/19.usbdev_nak_trans/latest

Test location /workspace/coverage/default/19.usbdev_out_iso.40672810
Short name T927
Test name
Test status
Simulation time 173342241 ps
CPU time 0.81 seconds
Started Jul 22 05:59:34 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206748 kb
Host smart-a66df868-1b67-41a0-aadc-9b794aa228e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672
810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_iso.40672810
Directory /workspace/19.usbdev_out_iso/latest

Test location /workspace/coverage/default/19.usbdev_out_stall.4129948827
Short name T1884
Test name
Test status
Simulation time 160326734 ps
CPU time 0.77 seconds
Started Jul 22 05:59:23 PM PDT 24
Finished Jul 22 05:59:25 PM PDT 24
Peak memory 206748 kb
Host smart-ab8ca82e-de02-4189-a9f6-7411f94deb1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41299
48827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_stall.4129948827
Directory /workspace/19.usbdev_out_stall/latest

Test location /workspace/coverage/default/19.usbdev_out_trans_nak.2896761621
Short name T2374
Test name
Test status
Simulation time 177697726 ps
CPU time 0.81 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206736 kb
Host smart-cf644436-44dd-44e2-85cd-009c915ee801
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28967
61621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_out_trans_nak.2896761621
Directory /workspace/19.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/19.usbdev_pending_in_trans.1621604729
Short name T2328
Test name
Test status
Simulation time 148612676 ps
CPU time 0.79 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206908 kb
Host smart-91c06e8b-56e2-41cf-9001-51d063af394b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216
04729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pending_in_trans.1621604729
Directory /workspace/19.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_pinflip.3457445074
Short name T608
Test name
Test status
Simulation time 239132857 ps
CPU time 0.99 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206740 kb
Host smart-10874107-42bb-4581-ab01-6080a3a5d982
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3457445074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_pinflip.3457445074
Directory /workspace/19.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/19.usbdev_phy_config_usb_ref_disable.1929697951
Short name T2153
Test name
Test status
Simulation time 159779820 ps
CPU time 0.77 seconds
Started Jul 22 05:59:22 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206740 kb
Host smart-3603abdf-0020-4a01-b61b-6de164f24643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19296
97951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_config_usb_ref_disable.1929697951
Directory /workspace/19.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/19.usbdev_phy_pins_sense.1916882705
Short name T811
Test name
Test status
Simulation time 35513417 ps
CPU time 0.64 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:27 PM PDT 24
Peak memory 206600 kb
Host smart-5d0b2dc0-e0c6-4162-9480-f5531afc438e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19168
82705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_phy_pins_sense.1916882705
Directory /workspace/19.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/19.usbdev_pkt_buffer.2212574951
Short name T2331
Test name
Test status
Simulation time 19627805392 ps
CPU time 50.02 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206924 kb
Host smart-f79da9e3-3cf0-4bfb-8fc6-2e3ba40a4f5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22125
74951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_buffer.2212574951
Directory /workspace/19.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/19.usbdev_pkt_received.3315930755
Short name T974
Test name
Test status
Simulation time 159571435 ps
CPU time 0.8 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 205760 kb
Host smart-5f0fe9c1-797e-440e-be47-b7ed2ab4365c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33159
30755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_received.3315930755
Directory /workspace/19.usbdev_pkt_received/latest

Test location /workspace/coverage/default/19.usbdev_pkt_sent.2123599134
Short name T2380
Test name
Test status
Simulation time 213335613 ps
CPU time 0.84 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:21 PM PDT 24
Peak memory 206752 kb
Host smart-1790b2df-16f6-4fe1-aa12-d416c3807fef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21235
99134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_pkt_sent.2123599134
Directory /workspace/19.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/19.usbdev_random_length_in_transaction.3848999413
Short name T757
Test name
Test status
Simulation time 211157366 ps
CPU time 0.85 seconds
Started Jul 22 05:59:18 PM PDT 24
Finished Jul 22 05:59:20 PM PDT 24
Peak memory 206752 kb
Host smart-fdb9571c-6625-4cb5-9059-7519f2d86349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38489
99413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_in_transaction.3848999413
Directory /workspace/19.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/19.usbdev_random_length_out_transaction.1274021023
Short name T1008
Test name
Test status
Simulation time 231162106 ps
CPU time 0.96 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206632 kb
Host smart-2f4ccd93-75ac-442b-a04a-c184619c3df4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12740
21023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_random_length_out_transaction.1274021023
Directory /workspace/19.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/19.usbdev_rx_crc_err.224185386
Short name T912
Test name
Test status
Simulation time 152211392 ps
CPU time 0.83 seconds
Started Jul 22 05:59:23 PM PDT 24
Finished Jul 22 05:59:25 PM PDT 24
Peak memory 206760 kb
Host smart-5b8977fb-b276-4438-ba21-6d0dc404ae44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22418
5386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_rx_crc_err.224185386
Directory /workspace/19.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/19.usbdev_setup_stage.2559923826
Short name T2579
Test name
Test status
Simulation time 166239862 ps
CPU time 0.78 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:27 PM PDT 24
Peak memory 206736 kb
Host smart-dd1f2492-1503-4d3e-84cd-ae0fa5213bda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25599
23826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_stage.2559923826
Directory /workspace/19.usbdev_setup_stage/latest

Test location /workspace/coverage/default/19.usbdev_setup_trans_ignored.3104463071
Short name T997
Test name
Test status
Simulation time 193884792 ps
CPU time 0.83 seconds
Started Jul 22 05:59:23 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206748 kb
Host smart-e6ec7d37-d6ec-482e-bfa3-581b93df5e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31044
63071 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_setup_trans_ignored.3104463071
Directory /workspace/19.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/19.usbdev_smoke.2287777423
Short name T1367
Test name
Test status
Simulation time 233696588 ps
CPU time 0.99 seconds
Started Jul 22 05:59:24 PM PDT 24
Finished Jul 22 05:59:26 PM PDT 24
Peak memory 206744 kb
Host smart-d11bdb5d-9b36-4742-8ca4-3f4d8122380c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
77423 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_smoke.2287777423
Directory /workspace/19.usbdev_smoke/latest

Test location /workspace/coverage/default/19.usbdev_spurious_pids_ignored.4130216160
Short name T1886
Test name
Test status
Simulation time 3693055314 ps
CPU time 34.63 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:55 PM PDT 24
Peak memory 206984 kb
Host smart-e74209c7-0efb-4d9b-b31f-5c206e27fef0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4130216160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_spurious_pids_ignored.4130216160
Directory /workspace/19.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/19.usbdev_stall_priority_over_nak.2171479581
Short name T2042
Test name
Test status
Simulation time 233743261 ps
CPU time 0.86 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206764 kb
Host smart-68fe6963-686d-4cbf-b37e-a8773e677554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21714
79581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_priority_over_nak.2171479581
Directory /workspace/19.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/19.usbdev_stall_trans.1955395852
Short name T352
Test name
Test status
Simulation time 167430578 ps
CPU time 0.78 seconds
Started Jul 22 05:59:50 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 206708 kb
Host smart-81ebc430-5773-49f0-a0f4-910f23d88395
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19553
95852 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stall_trans.1955395852
Directory /workspace/19.usbdev_stall_trans/latest

Test location /workspace/coverage/default/19.usbdev_stream_len_max.3403091079
Short name T347
Test name
Test status
Simulation time 513319992 ps
CPU time 1.33 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206504 kb
Host smart-ab7f049c-9f68-48a7-9aa0-c7896a22d00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34030
91079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_stream_len_max.3403091079
Directory /workspace/19.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/19.usbdev_streaming_out.3994878040
Short name T973
Test name
Test status
Simulation time 5977950164 ps
CPU time 55.25 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206960 kb
Host smart-0b353222-f5a5-4bd2-9dd4-a38322271f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39948
78040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.usbdev_streaming_out.3994878040
Directory /workspace/19.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_alert_test.3203066757
Short name T1893
Test name
Test status
Simulation time 41696402 ps
CPU time 0.67 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:45 PM PDT 24
Peak memory 206736 kb
Host smart-f6365ad9-8d24-44a3-b32c-405bb7b91dec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3203066757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_alert_test.3203066757
Directory /workspace/2.usbdev_alert_test/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_disconnect.2749374131
Short name T1646
Test name
Test status
Simulation time 3707086565 ps
CPU time 4.41 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:42 PM PDT 24
Peak memory 206872 kb
Host smart-da790b52-bfa6-4236-9f75-2162cb835ce6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2749374131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_disconnect.2749374131
Directory /workspace/2.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_reset.2610905285
Short name T2183
Test name
Test status
Simulation time 13390256971 ps
CPU time 12.93 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:56:42 PM PDT 24
Peak memory 206840 kb
Host smart-85abb7fe-5c2b-4900-9735-cf9108e67506
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2610905285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_reset.2610905285
Directory /workspace/2.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/2.usbdev_aon_wake_resume.1986811946
Short name T53
Test name
Test status
Simulation time 23377914340 ps
CPU time 26.06 seconds
Started Jul 22 05:56:36 PM PDT 24
Finished Jul 22 05:57:03 PM PDT 24
Peak memory 206760 kb
Host smart-990f4227-ccfa-421f-8d63-39e21261b105
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1986811946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_aon_wake_resume.1986811946
Directory /workspace/2.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/2.usbdev_av_buffer.2381294454
Short name T800
Test name
Test status
Simulation time 169522518 ps
CPU time 0.79 seconds
Started Jul 22 05:56:42 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206740 kb
Host smart-37b5714c-5af5-419f-be4f-d97fcec81f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23812
94454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_buffer.2381294454
Directory /workspace/2.usbdev_av_buffer/latest

Test location /workspace/coverage/default/2.usbdev_av_empty.2288988614
Short name T61
Test name
Test status
Simulation time 196930151 ps
CPU time 0.82 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206792 kb
Host smart-5ebe6b62-8645-403d-8c05-41ccea8ada53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22889
88614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_empty.2288988614
Directory /workspace/2.usbdev_av_empty/latest

Test location /workspace/coverage/default/2.usbdev_av_overflow.1515188450
Short name T56
Test name
Test status
Simulation time 180230020 ps
CPU time 0.79 seconds
Started Jul 22 05:56:27 PM PDT 24
Finished Jul 22 05:56:28 PM PDT 24
Peak memory 206740 kb
Host smart-154cd578-ad63-4dfa-b70f-16248ab79896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151
88450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_av_overflow.1515188450
Directory /workspace/2.usbdev_av_overflow/latest

Test location /workspace/coverage/default/2.usbdev_bitstuff_err.3091615563
Short name T998
Test name
Test status
Simulation time 189844258 ps
CPU time 0.81 seconds
Started Jul 22 05:56:42 PM PDT 24
Finished Jul 22 05:56:45 PM PDT 24
Peak memory 206752 kb
Host smart-287a27be-dfde-411a-8e48-9a3e250141ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30916
15563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_bitstuff_err.3091615563
Directory /workspace/2.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_clear.1468284623
Short name T2644
Test name
Test status
Simulation time 308308371 ps
CPU time 1.1 seconds
Started Jul 22 05:56:31 PM PDT 24
Finished Jul 22 05:56:32 PM PDT 24
Peak memory 206752 kb
Host smart-dfe6aa76-ce9d-4c0a-ad36-2164b1f40a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14682
84623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_clear.1468284623
Directory /workspace/2.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/2.usbdev_data_toggle_restore.3324239391
Short name T2068
Test name
Test status
Simulation time 1131740892 ps
CPU time 2.51 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206896 kb
Host smart-6b074b4f-81bd-4855-86c7-bde62ecd0301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33242
39391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_data_toggle_restore.3324239391
Directory /workspace/2.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/2.usbdev_device_address.4173194517
Short name T2186
Test name
Test status
Simulation time 13991721255 ps
CPU time 24.49 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:57:10 PM PDT 24
Peak memory 206892 kb
Host smart-c90eb48c-83ba-420a-8d5b-2f1f4bcde015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41731
94517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_device_address.4173194517
Directory /workspace/2.usbdev_device_address/latest

Test location /workspace/coverage/default/2.usbdev_disable_endpoint.1601131154
Short name T1423
Test name
Test status
Simulation time 324559997 ps
CPU time 1.1 seconds
Started Jul 22 05:56:29 PM PDT 24
Finished Jul 22 05:56:30 PM PDT 24
Peak memory 206708 kb
Host smart-bfd166de-f1f4-4ebe-981a-c5451bb03390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16011
31154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disable_endpoint.1601131154
Directory /workspace/2.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/2.usbdev_disconnected.2367333338
Short name T2079
Test name
Test status
Simulation time 179243700 ps
CPU time 0.78 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:56:37 PM PDT 24
Peak memory 206752 kb
Host smart-f66eff03-ed13-4b60-b468-b4ffc2d0c1a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23673
33338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_disconnected.2367333338
Directory /workspace/2.usbdev_disconnected/latest

Test location /workspace/coverage/default/2.usbdev_enable.2569960024
Short name T851
Test name
Test status
Simulation time 39282685 ps
CPU time 0.67 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:56:36 PM PDT 24
Peak memory 206736 kb
Host smart-61cc78d8-af49-48cb-b62e-4b28289ebac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25699
60024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_enable.2569960024
Directory /workspace/2.usbdev_enable/latest

Test location /workspace/coverage/default/2.usbdev_endpoint_access.1704849844
Short name T1250
Test name
Test status
Simulation time 666297563 ps
CPU time 1.89 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206812 kb
Host smart-da272a42-17f1-44c0-8fc7-435365fbf136
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17048
49844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_endpoint_access.1704849844
Directory /workspace/2.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/2.usbdev_fifo_rst.2537687950
Short name T1807
Test name
Test status
Simulation time 161524981 ps
CPU time 1.6 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:45 PM PDT 24
Peak memory 206836 kb
Host smart-616dc1fc-8d49-4475-9fbd-e6397c1d225f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25376
87950 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_fifo_rst.2537687950
Directory /workspace/2.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk.985743196
Short name T2557
Test name
Test status
Simulation time 115196326825 ps
CPU time 186.9 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:59:45 PM PDT 24
Peak memory 206924 kb
Host smart-32e56261-f76d-425d-91f2-f33f0fe24c46
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=985743196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk.985743196
Directory /workspace/2.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_hiclk_max.2143314902
Short name T536
Test name
Test status
Simulation time 97035589612 ps
CPU time 119.3 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:58:45 PM PDT 24
Peak memory 206924 kb
Host smart-b9baf25a-69d0-4ce2-b26f-62c8b90c3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143314902 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_hiclk_max.2143314902
Directory /workspace/2.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk.4267210488
Short name T1467
Test name
Test status
Simulation time 95156239062 ps
CPU time 124.34 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:58:50 PM PDT 24
Peak memory 206912 kb
Host smart-a741bd05-3f24-473e-870e-642dd8d3bf3e
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4267210488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk.4267210488
Directory /workspace/2.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/2.usbdev_freq_loclk_max.1297553283
Short name T616
Test name
Test status
Simulation time 113252881880 ps
CPU time 155.69 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:59:11 PM PDT 24
Peak memory 206892 kb
Host smart-a5ca037a-d3a8-4d19-8eb4-99ec8f1ab62f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297553283 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_loclk_max.1297553283
Directory /workspace/2.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/2.usbdev_freq_phase.3224676536
Short name T1309
Test name
Test status
Simulation time 118153189033 ps
CPU time 150.85 seconds
Started Jul 22 05:56:34 PM PDT 24
Finished Jul 22 05:59:05 PM PDT 24
Peak memory 207008 kb
Host smart-47268739-cfcb-45e3-81f7-fabf03d45028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32246
76536 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_freq_phase.3224676536
Directory /workspace/2.usbdev_freq_phase/latest

Test location /workspace/coverage/default/2.usbdev_in_iso.297245850
Short name T35
Test name
Test status
Simulation time 192602510 ps
CPU time 0.86 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206544 kb
Host smart-58ca755e-7a91-4aeb-9530-864049b615e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29724
5850 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_iso.297245850
Directory /workspace/2.usbdev_in_iso/latest

Test location /workspace/coverage/default/2.usbdev_in_stall.680912044
Short name T1200
Test name
Test status
Simulation time 161861200 ps
CPU time 0.76 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206696 kb
Host smart-2151e69d-8a96-488c-ac3c-1b4c66cd0b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68091
2044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_stall.680912044
Directory /workspace/2.usbdev_in_stall/latest

Test location /workspace/coverage/default/2.usbdev_in_trans.1334382378
Short name T1656
Test name
Test status
Simulation time 186034203 ps
CPU time 0.82 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206712 kb
Host smart-b87e6a99-d9a6-4372-8117-5c1a5db84657
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13343
82378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_in_trans.1334382378
Directory /workspace/2.usbdev_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_iso_retraction.3987484089
Short name T791
Test name
Test status
Simulation time 11003591425 ps
CPU time 39.94 seconds
Started Jul 22 05:56:45 PM PDT 24
Finished Jul 22 05:57:26 PM PDT 24
Peak memory 206836 kb
Host smart-18cb1b9d-1063-4cfe-a091-e47d25025c2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39874
84089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_iso_retraction.3987484089
Directory /workspace/2.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/2.usbdev_link_in_err.316358966
Short name T1585
Test name
Test status
Simulation time 180346756 ps
CPU time 0.83 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206704 kb
Host smart-d2b778e5-562b-47e8-9515-63515b256b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31635
8966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_in_err.316358966
Directory /workspace/2.usbdev_link_in_err/latest

Test location /workspace/coverage/default/2.usbdev_link_resume.1416323051
Short name T2325
Test name
Test status
Simulation time 23297817735 ps
CPU time 23.48 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206740 kb
Host smart-d1409ba6-9705-4eee-a4b2-ce67bab686f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14163
23051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_resume.1416323051
Directory /workspace/2.usbdev_link_resume/latest

Test location /workspace/coverage/default/2.usbdev_link_suspend.4081119903
Short name T1287
Test name
Test status
Simulation time 3344414475 ps
CPU time 3.74 seconds
Started Jul 22 05:56:34 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206796 kb
Host smart-2c4aa518-1107-4b46-b75e-3457b34db7e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811
19903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_link_suspend.4081119903
Directory /workspace/2.usbdev_link_suspend/latest

Test location /workspace/coverage/default/2.usbdev_low_speed_traffic.3450940081
Short name T2497
Test name
Test status
Simulation time 12699907153 ps
CPU time 113.73 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206188 kb
Host smart-5360f534-3446-4fcf-afd4-e8bc995b8bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34509
40081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_low_speed_traffic.3450940081
Directory /workspace/2.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/2.usbdev_max_inter_pkt_delay.4123561021
Short name T404
Test name
Test status
Simulation time 7978496760 ps
CPU time 77.81 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 05:59:01 PM PDT 24
Peak memory 206960 kb
Host smart-c3905791-6fc2-40c7-b177-a897d291a2f2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4123561021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_inter_pkt_delay.4123561021
Directory /workspace/2.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_max_length_in_transaction.1878734988
Short name T2007
Test name
Test status
Simulation time 246385375 ps
CPU time 0.88 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206672 kb
Host smart-b95ab952-ca49-471f-a804-7e74a0e36e69
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1878734988 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_in_transaction.1878734988
Directory /workspace/2.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_length_out_transaction.4114594510
Short name T636
Test name
Test status
Simulation time 204376175 ps
CPU time 0.9 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:43 PM PDT 24
Peak memory 206664 kb
Host smart-7a531ec9-eee2-4031-8029-f6753c25c3c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41145
94510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_length_out_transaction.4114594510
Directory /workspace/2.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_max_usb_traffic.4052171395
Short name T2514
Test name
Test status
Simulation time 5984050874 ps
CPU time 54.46 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:57:35 PM PDT 24
Peak memory 206148 kb
Host smart-ae039872-5c5d-4114-9f42-0743a9fc4bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40521
71395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_max_usb_traffic.4052171395
Directory /workspace/2.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/2.usbdev_min_inter_pkt_delay.4001239498
Short name T643
Test name
Test status
Simulation time 6984541143 ps
CPU time 189.57 seconds
Started Jul 22 05:58:34 PM PDT 24
Finished Jul 22 06:01:44 PM PDT 24
Peak memory 206828 kb
Host smart-155c5714-8dc3-489d-8ba5-33853d5ab4b0
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4001239498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_inter_pkt_delay.4001239498
Directory /workspace/2.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/2.usbdev_min_length_in_transaction.3322025703
Short name T624
Test name
Test status
Simulation time 151265969 ps
CPU time 0.81 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206764 kb
Host smart-a889e2c6-2491-4822-8cb3-572ed54325d8
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3322025703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_in_transaction.3322025703
Directory /workspace/2.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_min_length_out_transaction.1881965930
Short name T1187
Test name
Test status
Simulation time 150927564 ps
CPU time 0.76 seconds
Started Jul 22 05:58:37 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206680 kb
Host smart-252e4252-22ac-4064-ac90-60e7157e0950
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18819
65930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_min_length_out_transaction.1881965930
Directory /workspace/2.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_out_iso.2752041627
Short name T1709
Test name
Test status
Simulation time 179376202 ps
CPU time 0.8 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206744 kb
Host smart-ad72c206-978b-41c9-8cf5-34c1c2767513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27520
41627 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_iso.2752041627
Directory /workspace/2.usbdev_out_iso/latest

Test location /workspace/coverage/default/2.usbdev_out_stall.3724928883
Short name T983
Test name
Test status
Simulation time 181397000 ps
CPU time 0.8 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:56:37 PM PDT 24
Peak memory 206664 kb
Host smart-392dc7bf-7ad2-4c58-9277-50d7094170a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37249
28883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_stall.3724928883
Directory /workspace/2.usbdev_out_stall/latest

Test location /workspace/coverage/default/2.usbdev_out_trans_nak.3153284321
Short name T1823
Test name
Test status
Simulation time 168496322 ps
CPU time 0.82 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:56:39 PM PDT 24
Peak memory 206740 kb
Host smart-b81a0ed1-ceda-4ca9-a9b2-9e76c5240933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31532
84321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_out_trans_nak.3153284321
Directory /workspace/2.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/2.usbdev_pending_in_trans.1903834624
Short name T151
Test name
Test status
Simulation time 174449062 ps
CPU time 0.78 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:45 PM PDT 24
Peak memory 206744 kb
Host smart-2747df0a-b787-4dad-acfb-04bce0dc8ee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19038
34624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pending_in_trans.1903834624
Directory /workspace/2.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_pinflip.2901185611
Short name T940
Test name
Test status
Simulation time 198456298 ps
CPU time 0.88 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:46 PM PDT 24
Peak memory 206756 kb
Host smart-a1679a75-642a-4eec-a970-fe65fffaefae
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2901185611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_pinflip.2901185611
Directory /workspace/2.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_rand_bus_type.1940221919
Short name T870
Test name
Test status
Simulation time 218669174 ps
CPU time 0.94 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206684 kb
Host smart-e43c30e3-49e0-4558-88b1-ba016bda2362
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19402
21919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_rand_bus_type.1940221919
Directory /workspace/2.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/2.usbdev_phy_config_usb_ref_disable.2252793435
Short name T2206
Test name
Test status
Simulation time 153871711 ps
CPU time 0.78 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:39 PM PDT 24
Peak memory 206752 kb
Host smart-75366291-a52d-413f-bfdd-4ac860b29f72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22527
93435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_config_usb_ref_disable.2252793435
Directory /workspace/2.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/2.usbdev_phy_pins_sense.3057908815
Short name T42
Test name
Test status
Simulation time 76171687 ps
CPU time 0.74 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:43 PM PDT 24
Peak memory 206680 kb
Host smart-5285a501-b772-4a1b-b001-d17d9abe881a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30579
08815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_phy_pins_sense.3057908815
Directory /workspace/2.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/2.usbdev_pkt_buffer.394832816
Short name T2653
Test name
Test status
Simulation time 18924455097 ps
CPU time 42.19 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:57:17 PM PDT 24
Peak memory 206932 kb
Host smart-eb3099f8-7d18-4c8f-93b3-91d4fa699f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
2816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_buffer.394832816
Directory /workspace/2.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/2.usbdev_pkt_received.3630758754
Short name T2744
Test name
Test status
Simulation time 192847478 ps
CPU time 0.87 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206740 kb
Host smart-12adf27c-beef-469b-94f7-a3f291079612
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36307
58754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_received.3630758754
Directory /workspace/2.usbdev_pkt_received/latest

Test location /workspace/coverage/default/2.usbdev_pkt_sent.1221853402
Short name T1254
Test name
Test status
Simulation time 267350275 ps
CPU time 0.96 seconds
Started Jul 22 05:56:33 PM PDT 24
Finished Jul 22 05:56:35 PM PDT 24
Peak memory 206736 kb
Host smart-73afdf14-daf2-4578-ab41-2b4e3d56e7a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12218
53402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_pkt_sent.1221853402
Directory /workspace/2.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_disconnects.2172222102
Short name T163
Test name
Test status
Simulation time 14755296564 ps
CPU time 79.66 seconds
Started Jul 22 05:56:32 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206908 kb
Host smart-6914fa87-f2be-4067-9c0d-68b808ab9dd6
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2172222102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_disconnects.2172222102
Directory /workspace/2.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/2.usbdev_rand_bus_resets.2677475465
Short name T167
Test name
Test status
Simulation time 12784835041 ps
CPU time 85.76 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:58:11 PM PDT 24
Peak memory 206952 kb
Host smart-3a0d455e-8785-44c5-bc87-72ee2f9d1004
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2677475465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_bus_resets.2677475465
Directory /workspace/2.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/2.usbdev_rand_suspends.4242794903
Short name T2120
Test name
Test status
Simulation time 15583630185 ps
CPU time 317.48 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 06:01:57 PM PDT 24
Peak memory 206896 kb
Host smart-3c2d71f2-cae0-4396-89f0-c735b1b708c3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4242794903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rand_suspends.4242794903
Directory /workspace/2.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/2.usbdev_random_length_in_transaction.3897804612
Short name T2700
Test name
Test status
Simulation time 291223159 ps
CPU time 0.96 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:39 PM PDT 24
Peak memory 206752 kb
Host smart-bfcc3ee0-10ec-47f5-a1ce-e4aa2028af0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38978
04612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_in_transaction.3897804612
Directory /workspace/2.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/2.usbdev_random_length_out_transaction.756530291
Short name T1534
Test name
Test status
Simulation time 177421090 ps
CPU time 0.91 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:56:55 PM PDT 24
Peak memory 206740 kb
Host smart-d211ba34-2f43-4aa0-a9e5-d111a6b32d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75653
0291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_random_length_out_transaction.756530291
Directory /workspace/2.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/2.usbdev_rx_crc_err.3346769569
Short name T1386
Test name
Test status
Simulation time 164752446 ps
CPU time 0.77 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 05:56:40 PM PDT 24
Peak memory 206692 kb
Host smart-5c6472c2-c814-45b3-8285-0eac4cd94df7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33467
69569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_crc_err.3346769569
Directory /workspace/2.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/2.usbdev_rx_pid_err.2675622329
Short name T80
Test name
Test status
Simulation time 181101911 ps
CPU time 0.8 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:38 PM PDT 24
Peak memory 206676 kb
Host smart-bf5a6d6b-7541-4f96-9c98-522bef7d19ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26756
22329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_rx_pid_err.2675622329
Directory /workspace/2.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/2.usbdev_sec_cm.329867987
Short name T205
Test name
Test status
Simulation time 1052028843 ps
CPU time 1.8 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 224416 kb
Host smart-8bf12556-7895-4f9d-b305-907c0c5a98db
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=329867987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_sec_cm.329867987
Directory /workspace/2.usbdev_sec_cm/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority.2066284015
Short name T2530
Test name
Test status
Simulation time 399740821 ps
CPU time 1.28 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:56:42 PM PDT 24
Peak memory 205824 kb
Host smart-5b2804a4-9560-433e-ada8-bea039ebf1af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20662
84015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority.2066284015
Directory /workspace/2.usbdev_setup_priority/latest

Test location /workspace/coverage/default/2.usbdev_setup_priority_over_stall_response.3224144513
Short name T1079
Test name
Test status
Simulation time 235525568 ps
CPU time 0.92 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:46 PM PDT 24
Peak memory 206672 kb
Host smart-faf0650a-342b-419b-8273-cd66dbba775f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32241
44513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_priority_over_stall_response.3224144513
Directory /workspace/2.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/2.usbdev_setup_stage.2192397563
Short name T32
Test name
Test status
Simulation time 168073162 ps
CPU time 0.8 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:45 PM PDT 24
Peak memory 206740 kb
Host smart-55ee2770-8003-4d82-b3ac-8c0c587a29ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21923
97563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_stage.2192397563
Directory /workspace/2.usbdev_setup_stage/latest

Test location /workspace/coverage/default/2.usbdev_setup_trans_ignored.1568038223
Short name T490
Test name
Test status
Simulation time 153707412 ps
CPU time 0.8 seconds
Started Jul 22 05:56:39 PM PDT 24
Finished Jul 22 05:56:41 PM PDT 24
Peak memory 206700 kb
Host smart-92d793c6-dadb-4337-8826-fa1f5084e85a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15680
38223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_setup_trans_ignored.1568038223
Directory /workspace/2.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/2.usbdev_smoke.2570265752
Short name T2489
Test name
Test status
Simulation time 257192493 ps
CPU time 0.97 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:56:36 PM PDT 24
Peak memory 206908 kb
Host smart-05ff81d9-802b-46fd-877d-ca8c40c81abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25702
65752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_smoke.2570265752
Directory /workspace/2.usbdev_smoke/latest

Test location /workspace/coverage/default/2.usbdev_spurious_pids_ignored.3458388143
Short name T494
Test name
Test status
Simulation time 4701981284 ps
CPU time 133.75 seconds
Started Jul 22 05:56:40 PM PDT 24
Finished Jul 22 05:58:55 PM PDT 24
Peak memory 206084 kb
Host smart-409adbb2-c290-411c-bee9-764f71098481
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3458388143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_spurious_pids_ignored.3458388143
Directory /workspace/2.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/2.usbdev_stall_priority_over_nak.1925595079
Short name T2364
Test name
Test status
Simulation time 163813819 ps
CPU time 0.82 seconds
Started Jul 22 05:58:38 PM PDT 24
Finished Jul 22 05:58:39 PM PDT 24
Peak memory 206684 kb
Host smart-595ab8ca-eab1-4185-a906-5654bec8aae8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19255
95079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_priority_over_nak.1925595079
Directory /workspace/2.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/2.usbdev_stall_trans.2230476129
Short name T2535
Test name
Test status
Simulation time 155386665 ps
CPU time 0.77 seconds
Started Jul 22 05:56:42 PM PDT 24
Finished Jul 22 05:56:45 PM PDT 24
Peak memory 206764 kb
Host smart-4b2d0db6-9741-4446-a393-d8c5f8be9dd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22304
76129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stall_trans.2230476129
Directory /workspace/2.usbdev_stall_trans/latest

Test location /workspace/coverage/default/2.usbdev_stream_len_max.114461595
Short name T897
Test name
Test status
Simulation time 563007902 ps
CPU time 1.44 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:46 PM PDT 24
Peak memory 206732 kb
Host smart-5b76a73f-05df-4980-a127-b44424360a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11446
1595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stream_len_max.114461595
Directory /workspace/2.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/2.usbdev_streaming_out.2386288141
Short name T749
Test name
Test status
Simulation time 4244723821 ps
CPU time 40.53 seconds
Started Jul 22 05:56:35 PM PDT 24
Finished Jul 22 05:57:17 PM PDT 24
Peak memory 206812 kb
Host smart-df7f42ee-3d5d-4f71-80ec-74f806c258a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23862
88141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_streaming_out.2386288141
Directory /workspace/2.usbdev_streaming_out/latest

Test location /workspace/coverage/default/2.usbdev_stress_usb_traffic.3436524977
Short name T236
Test name
Test status
Simulation time 26333948850 ps
CPU time 239.03 seconds
Started Jul 22 05:56:36 PM PDT 24
Finished Jul 22 06:00:35 PM PDT 24
Peak memory 207008 kb
Host smart-18723f50-ecf1-45ed-b0f9-c88906aa17f8
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3436524977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.usbdev_stress_usb_traffic.3436524977
Directory /workspace/2.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_alert_test.14196641
Short name T2578
Test name
Test status
Simulation time 64072486 ps
CPU time 0.68 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 05:59:32 PM PDT 24
Peak memory 206724 kb
Host smart-65e1b30d-4f33-4d26-8360-1f015000929d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=14196641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_alert_test.14196641
Directory /workspace/20.usbdev_alert_test/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_disconnect.398460147
Short name T708
Test name
Test status
Simulation time 3757368971 ps
CPU time 4.52 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:13 PM PDT 24
Peak memory 206900 kb
Host smart-eb60a5ae-ae6a-49fc-8b6b-0228d76e34fc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=398460147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_disconnect.398460147
Directory /workspace/20.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_reset.100878563
Short name T1365
Test name
Test status
Simulation time 13355459577 ps
CPU time 13.05 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:40 PM PDT 24
Peak memory 206780 kb
Host smart-4eb80537-be9f-4dcd-8f07-ac5935ba75df
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=100878563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_reset.100878563
Directory /workspace/20.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/20.usbdev_aon_wake_resume.1426435139
Short name T1700
Test name
Test status
Simulation time 23393672227 ps
CPU time 24.42 seconds
Started Jul 22 05:59:35 PM PDT 24
Finished Jul 22 06:00:00 PM PDT 24
Peak memory 206816 kb
Host smart-fdfe3cd0-c046-4379-8a16-ff5b10a4ef58
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1426435139 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_aon_wake_resume.1426435139
Directory /workspace/20.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/20.usbdev_av_buffer.1352931080
Short name T2734
Test name
Test status
Simulation time 156422285 ps
CPU time 0.75 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:21 PM PDT 24
Peak memory 206752 kb
Host smart-6db9d7b9-f097-4cf5-aea8-7a6f1c2b853a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13529
31080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_av_buffer.1352931080
Directory /workspace/20.usbdev_av_buffer/latest

Test location /workspace/coverage/default/20.usbdev_bitstuff_err.1589895758
Short name T68
Test name
Test status
Simulation time 211887378 ps
CPU time 0.86 seconds
Started Jul 22 05:59:24 PM PDT 24
Finished Jul 22 05:59:25 PM PDT 24
Peak memory 206708 kb
Host smart-d5cf0020-4af4-44fd-b7e3-59712f5f3842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15898
95758 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_bitstuff_err.1589895758
Directory /workspace/20.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_clear.2034288455
Short name T106
Test name
Test status
Simulation time 390954037 ps
CPU time 1.24 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:22 PM PDT 24
Peak memory 206788 kb
Host smart-61f808a0-2834-4aec-a5dc-09ca552e80f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20342
88455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_clear.2034288455
Directory /workspace/20.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/20.usbdev_data_toggle_restore.2308554549
Short name T437
Test name
Test status
Simulation time 315285566 ps
CPU time 0.99 seconds
Started Jul 22 05:59:26 PM PDT 24
Finished Jul 22 05:59:28 PM PDT 24
Peak memory 206752 kb
Host smart-ff850ebc-6f46-4ca9-9df5-39d51ad7d2ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23085
54549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_data_toggle_restore.2308554549
Directory /workspace/20.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/20.usbdev_device_address.820292662
Short name T1779
Test name
Test status
Simulation time 10791574141 ps
CPU time 21.94 seconds
Started Jul 22 05:59:20 PM PDT 24
Finished Jul 22 05:59:43 PM PDT 24
Peak memory 206920 kb
Host smart-321bbcda-876e-4377-b596-01f57524f642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82029
2662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_device_address.820292662
Directory /workspace/20.usbdev_device_address/latest

Test location /workspace/coverage/default/20.usbdev_disable_endpoint.3596130922
Short name T1683
Test name
Test status
Simulation time 543074431 ps
CPU time 1.52 seconds
Started Jul 22 05:59:18 PM PDT 24
Finished Jul 22 05:59:20 PM PDT 24
Peak memory 206752 kb
Host smart-1c116397-6f61-492a-a88e-1d3cf4d5cc93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35961
30922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disable_endpoint.3596130922
Directory /workspace/20.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/20.usbdev_disconnected.3783363152
Short name T1791
Test name
Test status
Simulation time 137939080 ps
CPU time 0.74 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 05:59:32 PM PDT 24
Peak memory 206752 kb
Host smart-8a7fd64e-8a7a-42d3-8fea-6b78bd2f32e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37833
63152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_disconnected.3783363152
Directory /workspace/20.usbdev_disconnected/latest

Test location /workspace/coverage/default/20.usbdev_enable.1762499096
Short name T606
Test name
Test status
Simulation time 34652448 ps
CPU time 0.65 seconds
Started Jul 22 05:59:21 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206720 kb
Host smart-943159af-4923-49f0-8be3-3d88c2055172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17624
99096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_enable.1762499096
Directory /workspace/20.usbdev_enable/latest

Test location /workspace/coverage/default/20.usbdev_endpoint_access.3359183499
Short name T313
Test name
Test status
Simulation time 851638708 ps
CPU time 1.94 seconds
Started Jul 22 05:59:37 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206896 kb
Host smart-ac9f2bd5-c1b2-44bd-b8d1-b60e8c8a8fda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33591
83499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_endpoint_access.3359183499
Directory /workspace/20.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/20.usbdev_fifo_rst.1391873014
Short name T1033
Test name
Test status
Simulation time 270740763 ps
CPU time 1.58 seconds
Started Jul 22 05:59:35 PM PDT 24
Finished Jul 22 05:59:37 PM PDT 24
Peak memory 206880 kb
Host smart-7db104f0-71f6-442d-9cee-8f0162b0f6af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13918
73014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_fifo_rst.1391873014
Directory /workspace/20.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/20.usbdev_in_iso.1242755615
Short name T346
Test name
Test status
Simulation time 164824544 ps
CPU time 0.89 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 05:59:31 PM PDT 24
Peak memory 206780 kb
Host smart-b8a89517-7d91-474a-b021-fa28676d902c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12427
55615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_iso.1242755615
Directory /workspace/20.usbdev_in_iso/latest

Test location /workspace/coverage/default/20.usbdev_in_stall.36602096
Short name T646
Test name
Test status
Simulation time 169087992 ps
CPU time 0.8 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 05:59:31 PM PDT 24
Peak memory 206744 kb
Host smart-95c6dd41-ea01-458f-9529-460be4a4f4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36602
096 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_stall.36602096
Directory /workspace/20.usbdev_in_stall/latest

Test location /workspace/coverage/default/20.usbdev_in_trans.597190436
Short name T382
Test name
Test status
Simulation time 227136675 ps
CPU time 0.92 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 05:59:33 PM PDT 24
Peak memory 206708 kb
Host smart-857e0d00-03a7-4059-96d6-a2c119cc5644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59719
0436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_in_trans.597190436
Directory /workspace/20.usbdev_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_iso_retraction.4262337045
Short name T860
Test name
Test status
Simulation time 6009550521 ps
CPU time 49.69 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 06:00:24 PM PDT 24
Peak memory 206936 kb
Host smart-247eba71-3317-408c-9a3a-a91ccd67ddeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42623
37045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_iso_retraction.4262337045
Directory /workspace/20.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/20.usbdev_link_in_err.2597393902
Short name T1280
Test name
Test status
Simulation time 243493461 ps
CPU time 0.86 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206676 kb
Host smart-259ed95c-3099-431a-a2d5-27271354584a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25973
93902 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_in_err.2597393902
Directory /workspace/20.usbdev_link_in_err/latest

Test location /workspace/coverage/default/20.usbdev_link_resume.272553156
Short name T1239
Test name
Test status
Simulation time 23338672755 ps
CPU time 22.43 seconds
Started Jul 22 05:59:28 PM PDT 24
Finished Jul 22 05:59:51 PM PDT 24
Peak memory 206800 kb
Host smart-9eab97d3-d0ff-454f-8595-ecf3e6496294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27255
3156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_resume.272553156
Directory /workspace/20.usbdev_link_resume/latest

Test location /workspace/coverage/default/20.usbdev_link_suspend.1258698361
Short name T1990
Test name
Test status
Simulation time 3274032123 ps
CPU time 4.1 seconds
Started Jul 22 05:59:32 PM PDT 24
Finished Jul 22 05:59:42 PM PDT 24
Peak memory 206812 kb
Host smart-c8ccb524-846c-4bc5-ba79-e3c161fb9095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12586
98361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_link_suspend.1258698361
Directory /workspace/20.usbdev_link_suspend/latest

Test location /workspace/coverage/default/20.usbdev_low_speed_traffic.2397782242
Short name T2516
Test name
Test status
Simulation time 10737152225 ps
CPU time 288.02 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 206920 kb
Host smart-949dad94-7637-440c-9045-78885aaa19dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23977
82242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_low_speed_traffic.2397782242
Directory /workspace/20.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/20.usbdev_max_inter_pkt_delay.82299284
Short name T1950
Test name
Test status
Simulation time 4989266893 ps
CPU time 139.74 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 06:01:50 PM PDT 24
Peak memory 206948 kb
Host smart-b5e89338-7006-4cf8-920c-d9a9146e782c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=82299284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_inter_pkt_delay.82299284
Directory /workspace/20.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_max_length_in_transaction.1340780186
Short name T457
Test name
Test status
Simulation time 239925749 ps
CPU time 0.96 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206732 kb
Host smart-b96c6ca9-524a-4cd6-9007-452a6ceb9a23
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1340780186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_in_transaction.1340780186
Directory /workspace/20.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_length_out_transaction.1176765085
Short name T595
Test name
Test status
Simulation time 245571053 ps
CPU time 0.97 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206704 kb
Host smart-bc72ae4a-37ed-4450-80cb-22afc18302af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11767
65085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_length_out_transaction.1176765085
Directory /workspace/20.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_max_usb_traffic.3068630483
Short name T899
Test name
Test status
Simulation time 5306053747 ps
CPU time 147.62 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206928 kb
Host smart-c49fe35a-955e-42ae-8990-e5e3246cfef1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30686
30483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_max_usb_traffic.3068630483
Directory /workspace/20.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/20.usbdev_min_inter_pkt_delay.2139482255
Short name T2133
Test name
Test status
Simulation time 3578021314 ps
CPU time 25.31 seconds
Started Jul 22 05:59:53 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206912 kb
Host smart-24fa46f5-9f8a-4e04-9d00-72042172296c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2139482255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_inter_pkt_delay.2139482255
Directory /workspace/20.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/20.usbdev_min_length_in_transaction.280596744
Short name T752
Test name
Test status
Simulation time 164643563 ps
CPU time 0.77 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 05:59:33 PM PDT 24
Peak memory 206756 kb
Host smart-686ecc11-183d-44cb-9b9b-6b8b0411c824
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=280596744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_in_transaction.280596744
Directory /workspace/20.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_min_length_out_transaction.3897746804
Short name T1121
Test name
Test status
Simulation time 155974622 ps
CPU time 0.79 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 05:59:32 PM PDT 24
Peak memory 206736 kb
Host smart-1ed79d73-369c-4764-a31d-8a305cf5c1c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38977
46804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_min_length_out_transaction.3897746804
Directory /workspace/20.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_out_iso.3614524266
Short name T1901
Test name
Test status
Simulation time 169511178 ps
CPU time 0.83 seconds
Started Jul 22 05:59:35 PM PDT 24
Finished Jul 22 05:59:37 PM PDT 24
Peak memory 206732 kb
Host smart-c1dbfc8f-bdac-4a0d-bfb0-5f9559667bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36145
24266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_iso.3614524266
Directory /workspace/20.usbdev_out_iso/latest

Test location /workspace/coverage/default/20.usbdev_out_stall.4044645173
Short name T2175
Test name
Test status
Simulation time 199416688 ps
CPU time 0.87 seconds
Started Jul 22 05:59:34 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206664 kb
Host smart-48d085da-f1a9-4484-9d15-71ba65e35fb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40446
45173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_stall.4044645173
Directory /workspace/20.usbdev_out_stall/latest

Test location /workspace/coverage/default/20.usbdev_out_trans_nak.3212664666
Short name T882
Test name
Test status
Simulation time 168180665 ps
CPU time 0.83 seconds
Started Jul 22 05:59:32 PM PDT 24
Finished Jul 22 05:59:33 PM PDT 24
Peak memory 206708 kb
Host smart-c0d6325e-2c8d-451b-ad88-01acfdb48717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32126
64666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_out_trans_nak.3212664666
Directory /workspace/20.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/20.usbdev_pending_in_trans.3955198318
Short name T1697
Test name
Test status
Simulation time 153971905 ps
CPU time 0.78 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 05:59:30 PM PDT 24
Peak memory 206748 kb
Host smart-6283c715-8f87-4ba4-9e87-e605d77224a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39551
98318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pending_in_trans.3955198318
Directory /workspace/20.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_pinflip.360653583
Short name T1028
Test name
Test status
Simulation time 204447960 ps
CPU time 0.86 seconds
Started Jul 22 06:00:17 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206744 kb
Host smart-e881850a-e125-4fd7-9c8d-9f4f1ad597c7
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=360653583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_pinflip.360653583
Directory /workspace/20.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/20.usbdev_phy_config_usb_ref_disable.1922553240
Short name T1529
Test name
Test status
Simulation time 148550478 ps
CPU time 0.75 seconds
Started Jul 22 05:59:34 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206748 kb
Host smart-c500c110-16d0-4130-81c6-4ced7645d47c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19225
53240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_config_usb_ref_disable.1922553240
Directory /workspace/20.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/20.usbdev_phy_pins_sense.1451481534
Short name T41
Test name
Test status
Simulation time 65650962 ps
CPU time 0.7 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 05:59:34 PM PDT 24
Peak memory 206740 kb
Host smart-93fcb512-b19b-4085-be77-ba75a94fc62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14514
81534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_phy_pins_sense.1451481534
Directory /workspace/20.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/20.usbdev_pkt_buffer.3934445463
Short name T1575
Test name
Test status
Simulation time 11942497451 ps
CPU time 29.57 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 06:00:02 PM PDT 24
Peak memory 206912 kb
Host smart-5a6a5129-7219-4646-a8a8-e07f24197d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39344
45463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_buffer.3934445463
Directory /workspace/20.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/20.usbdev_pkt_received.4109815197
Short name T1841
Test name
Test status
Simulation time 155880245 ps
CPU time 0.8 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 05:59:32 PM PDT 24
Peak memory 206684 kb
Host smart-92253d90-1433-44e8-99e0-dbfd34ddd438
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41098
15197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_received.4109815197
Directory /workspace/20.usbdev_pkt_received/latest

Test location /workspace/coverage/default/20.usbdev_pkt_sent.2286266567
Short name T2421
Test name
Test status
Simulation time 195371689 ps
CPU time 0.82 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 05:59:31 PM PDT 24
Peak memory 206696 kb
Host smart-b88be2df-fdf0-44f3-a6cf-efbac32266e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22862
66567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_pkt_sent.2286266567
Directory /workspace/20.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/20.usbdev_random_length_in_transaction.213561341
Short name T1102
Test name
Test status
Simulation time 241112093 ps
CPU time 0.93 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 05:59:32 PM PDT 24
Peak memory 206708 kb
Host smart-56f2219e-9da3-4edb-bd09-61384a8e8a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21356
1341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_in_transaction.213561341
Directory /workspace/20.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/20.usbdev_random_length_out_transaction.479145967
Short name T1391
Test name
Test status
Simulation time 151657981 ps
CPU time 0.83 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 05:59:31 PM PDT 24
Peak memory 206776 kb
Host smart-3dd7a3b1-82d9-4404-841c-903f05459141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47914
5967 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_random_length_out_transaction.479145967
Directory /workspace/20.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/20.usbdev_rx_crc_err.1117821017
Short name T665
Test name
Test status
Simulation time 172993714 ps
CPU time 0.79 seconds
Started Jul 22 05:59:35 PM PDT 24
Finished Jul 22 05:59:36 PM PDT 24
Peak memory 206732 kb
Host smart-b390d611-916a-4512-b2fc-aff17205d41a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11178
21017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_rx_crc_err.1117821017
Directory /workspace/20.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/20.usbdev_setup_stage.2711356101
Short name T1892
Test name
Test status
Simulation time 165943676 ps
CPU time 0.85 seconds
Started Jul 22 05:59:32 PM PDT 24
Finished Jul 22 05:59:34 PM PDT 24
Peak memory 206732 kb
Host smart-88e058c4-5f93-46e5-8d95-2b99b99a7baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27113
56101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_stage.2711356101
Directory /workspace/20.usbdev_setup_stage/latest

Test location /workspace/coverage/default/20.usbdev_setup_trans_ignored.3379128798
Short name T1104
Test name
Test status
Simulation time 207709437 ps
CPU time 0.82 seconds
Started Jul 22 05:59:32 PM PDT 24
Finished Jul 22 05:59:34 PM PDT 24
Peak memory 206732 kb
Host smart-137c940a-6906-419a-b1f9-3c161a121fcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33791
28798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_setup_trans_ignored.3379128798
Directory /workspace/20.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/20.usbdev_smoke.1895367338
Short name T1629
Test name
Test status
Simulation time 217351544 ps
CPU time 0.95 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206728 kb
Host smart-34b3f6a9-8e70-4a19-a569-af10247de4af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18953
67338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_smoke.1895367338
Directory /workspace/20.usbdev_smoke/latest

Test location /workspace/coverage/default/20.usbdev_spurious_pids_ignored.381303186
Short name T731
Test name
Test status
Simulation time 5795887614 ps
CPU time 41.85 seconds
Started Jul 22 05:59:32 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206920 kb
Host smart-cbec6a28-7c65-4d2f-b1ea-432fd0530bd0
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=381303186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_spurious_pids_ignored.381303186
Directory /workspace/20.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/20.usbdev_stall_priority_over_nak.862643290
Short name T2550
Test name
Test status
Simulation time 189944614 ps
CPU time 0.9 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206724 kb
Host smart-d9c32251-7377-46e9-8ba4-0ec301cbdad2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86264
3290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_priority_over_nak.862643290
Directory /workspace/20.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/20.usbdev_stall_trans.1458483244
Short name T868
Test name
Test status
Simulation time 154643693 ps
CPU time 0.79 seconds
Started Jul 22 05:59:34 PM PDT 24
Finished Jul 22 05:59:36 PM PDT 24
Peak memory 206740 kb
Host smart-3f7b7a76-57ee-4549-8928-52466b8dbe5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584
83244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stall_trans.1458483244
Directory /workspace/20.usbdev_stall_trans/latest

Test location /workspace/coverage/default/20.usbdev_stream_len_max.1120656588
Short name T1234
Test name
Test status
Simulation time 1387894856 ps
CPU time 2.73 seconds
Started Jul 22 06:00:15 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206868 kb
Host smart-483a780c-0182-4e38-ae64-b943da3da6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11206
56588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_stream_len_max.1120656588
Directory /workspace/20.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/20.usbdev_streaming_out.199390120
Short name T414
Test name
Test status
Simulation time 6725053512 ps
CPU time 193.21 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 06:02:46 PM PDT 24
Peak memory 206856 kb
Host smart-efe17853-1591-4499-aa54-e6b31063c4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19939
0120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.usbdev_streaming_out.199390120
Directory /workspace/20.usbdev_streaming_out/latest

Test location /workspace/coverage/default/21.usbdev_alert_test.1795915878
Short name T828
Test name
Test status
Simulation time 32851767 ps
CPU time 0.71 seconds
Started Jul 22 05:59:48 PM PDT 24
Finished Jul 22 05:59:49 PM PDT 24
Peak memory 206724 kb
Host smart-8619a2b9-9901-43b9-8d0c-7353157b53d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1795915878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_alert_test.1795915878
Directory /workspace/21.usbdev_alert_test/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_disconnect.2288376991
Short name T1592
Test name
Test status
Simulation time 3788727998 ps
CPU time 4.37 seconds
Started Jul 22 06:00:03 PM PDT 24
Finished Jul 22 06:00:08 PM PDT 24
Peak memory 206800 kb
Host smart-384e0719-3b4a-46f0-856c-a3abaceb728c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2288376991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_disconnect.2288376991
Directory /workspace/21.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_reset.3246975460
Short name T666
Test name
Test status
Simulation time 13307947199 ps
CPU time 13.21 seconds
Started Jul 22 05:59:36 PM PDT 24
Finished Jul 22 05:59:49 PM PDT 24
Peak memory 206948 kb
Host smart-f1194042-ade7-423d-b38c-f554dac1b1c9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3246975460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_reset.3246975460
Directory /workspace/21.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/21.usbdev_aon_wake_resume.3260463774
Short name T2545
Test name
Test status
Simulation time 23346350422 ps
CPU time 23.14 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206968 kb
Host smart-0c5da46e-e4dd-4005-bee9-06d45b485126
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3260463774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_aon_wake_resume.3260463774
Directory /workspace/21.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/21.usbdev_av_buffer.3154413976
Short name T351
Test name
Test status
Simulation time 209157989 ps
CPU time 0.89 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:43 PM PDT 24
Peak memory 206752 kb
Host smart-d6684888-3d6b-4346-9227-31bd7413f792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
13976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_av_buffer.3154413976
Directory /workspace/21.usbdev_av_buffer/latest

Test location /workspace/coverage/default/21.usbdev_bitstuff_err.4141642401
Short name T579
Test name
Test status
Simulation time 147650074 ps
CPU time 0.76 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 05:59:34 PM PDT 24
Peak memory 206752 kb
Host smart-b29a7ee4-128f-4dd9-9f90-1cd1828fb5bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
42401 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_bitstuff_err.4141642401
Directory /workspace/21.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_clear.890467705
Short name T1011
Test name
Test status
Simulation time 152041477 ps
CPU time 0.79 seconds
Started Jul 22 05:59:34 PM PDT 24
Finished Jul 22 05:59:35 PM PDT 24
Peak memory 206704 kb
Host smart-ab131dca-c34e-4991-8ccb-ec1992be798a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89046
7705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_clear.890467705
Directory /workspace/21.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/21.usbdev_data_toggle_restore.3332581890
Short name T1137
Test name
Test status
Simulation time 840849342 ps
CPU time 2 seconds
Started Jul 22 05:59:31 PM PDT 24
Finished Jul 22 05:59:34 PM PDT 24
Peak memory 206900 kb
Host smart-eb9daac7-d64b-4ba0-9d5d-0fcaaf8938d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33325
81890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_data_toggle_restore.3332581890
Directory /workspace/21.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/21.usbdev_disable_endpoint.4112078986
Short name T423
Test name
Test status
Simulation time 358588501 ps
CPU time 1.16 seconds
Started Jul 22 05:59:34 PM PDT 24
Finished Jul 22 05:59:36 PM PDT 24
Peak memory 206708 kb
Host smart-e78b443d-8cb0-4c7f-a310-5210de00334a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41120
78986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_disable_endpoint.4112078986
Directory /workspace/21.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/21.usbdev_enable.3238700409
Short name T2420
Test name
Test status
Simulation time 32972084 ps
CPU time 0.63 seconds
Started Jul 22 05:59:30 PM PDT 24
Finished Jul 22 05:59:31 PM PDT 24
Peak memory 206732 kb
Host smart-8d1af21b-144f-4cb2-8cd4-a657dec44bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32387
00409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_enable.3238700409
Directory /workspace/21.usbdev_enable/latest

Test location /workspace/coverage/default/21.usbdev_endpoint_access.2025753240
Short name T1485
Test name
Test status
Simulation time 830682541 ps
CPU time 2.02 seconds
Started Jul 22 05:59:29 PM PDT 24
Finished Jul 22 05:59:32 PM PDT 24
Peak memory 206856 kb
Host smart-33ffba88-585d-4b67-9bbd-a381f09250fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20257
53240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_endpoint_access.2025753240
Directory /workspace/21.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/21.usbdev_fifo_rst.518946655
Short name T1573
Test name
Test status
Simulation time 208039582 ps
CPU time 2.27 seconds
Started Jul 22 05:59:33 PM PDT 24
Finished Jul 22 05:59:36 PM PDT 24
Peak memory 206888 kb
Host smart-448cb9ba-5a56-4b68-99a4-98ce54aabfe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51894
6655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_fifo_rst.518946655
Directory /workspace/21.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/21.usbdev_in_iso.2544939225
Short name T1642
Test name
Test status
Simulation time 155521617 ps
CPU time 0.82 seconds
Started Jul 22 05:59:38 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206732 kb
Host smart-1a1b1e8a-7901-463a-85b9-2cc474d9badd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25449
39225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_iso.2544939225
Directory /workspace/21.usbdev_in_iso/latest

Test location /workspace/coverage/default/21.usbdev_in_stall.118930642
Short name T2118
Test name
Test status
Simulation time 160390804 ps
CPU time 0.84 seconds
Started Jul 22 05:59:45 PM PDT 24
Finished Jul 22 05:59:47 PM PDT 24
Peak memory 206756 kb
Host smart-4ca4b6ea-9adf-4458-bb05-dc590b1e72f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11893
0642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_stall.118930642
Directory /workspace/21.usbdev_in_stall/latest

Test location /workspace/coverage/default/21.usbdev_in_trans.3211046495
Short name T877
Test name
Test status
Simulation time 243716022 ps
CPU time 0.92 seconds
Started Jul 22 05:59:37 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206800 kb
Host smart-e81deca5-59ec-4e11-8656-a8cbb5ed6b4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32110
46495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_in_trans.3211046495
Directory /workspace/21.usbdev_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_invalid_sync.3746156877
Short name T2292
Test name
Test status
Simulation time 7894609602 ps
CPU time 70.96 seconds
Started Jul 22 05:59:35 PM PDT 24
Finished Jul 22 06:00:47 PM PDT 24
Peak memory 206936 kb
Host smart-bc832425-1198-4050-8c21-38926a771bc6
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3746156877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_invalid_sync.3746156877
Directory /workspace/21.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/21.usbdev_iso_retraction.369318435
Short name T605
Test name
Test status
Simulation time 10748349769 ps
CPU time 95.29 seconds
Started Jul 22 05:59:36 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206940 kb
Host smart-a86be3e9-b4ce-4629-af88-988a6462ada7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36931
8435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_iso_retraction.369318435
Directory /workspace/21.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/21.usbdev_link_in_err.1525797728
Short name T1491
Test name
Test status
Simulation time 210644700 ps
CPU time 0.89 seconds
Started Jul 22 05:59:39 PM PDT 24
Finished Jul 22 05:59:40 PM PDT 24
Peak memory 206656 kb
Host smart-1ec7e922-503a-484c-b13c-241002084277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15257
97728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_in_err.1525797728
Directory /workspace/21.usbdev_link_in_err/latest

Test location /workspace/coverage/default/21.usbdev_link_resume.2936378375
Short name T1717
Test name
Test status
Simulation time 23317272985 ps
CPU time 23.13 seconds
Started Jul 22 05:59:37 PM PDT 24
Finished Jul 22 06:00:01 PM PDT 24
Peak memory 206856 kb
Host smart-52937dfb-38d9-4b99-a89b-744b866bd3e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363
78375 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_resume.2936378375
Directory /workspace/21.usbdev_link_resume/latest

Test location /workspace/coverage/default/21.usbdev_link_suspend.3266836784
Short name T1761
Test name
Test status
Simulation time 3327996508 ps
CPU time 4.76 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 206816 kb
Host smart-d4c34f50-cc0e-4698-8106-56b9f7781de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32668
36784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_link_suspend.3266836784
Directory /workspace/21.usbdev_link_suspend/latest

Test location /workspace/coverage/default/21.usbdev_low_speed_traffic.1847164755
Short name T1525
Test name
Test status
Simulation time 9607207305 ps
CPU time 73.58 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 06:00:59 PM PDT 24
Peak memory 206968 kb
Host smart-c862c631-6ee3-49ae-bf96-db3eb31ce8a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18471
64755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_low_speed_traffic.1847164755
Directory /workspace/21.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/21.usbdev_max_inter_pkt_delay.3364160469
Short name T613
Test name
Test status
Simulation time 4508954199 ps
CPU time 30.22 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206944 kb
Host smart-66eb6f16-322e-4c3c-9b99-df8e883e1e12
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3364160469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_inter_pkt_delay.3364160469
Directory /workspace/21.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_max_length_in_transaction.662788262
Short name T1753
Test name
Test status
Simulation time 247073964 ps
CPU time 1 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:23 PM PDT 24
Peak memory 206636 kb
Host smart-ae54a4b7-7e7d-4e2b-842b-84090fe83a62
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=662788262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_in_transaction.662788262
Directory /workspace/21.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_length_out_transaction.394604670
Short name T1388
Test name
Test status
Simulation time 206487288 ps
CPU time 0.89 seconds
Started Jul 22 05:59:38 PM PDT 24
Finished Jul 22 05:59:40 PM PDT 24
Peak memory 206724 kb
Host smart-6a429c5a-a731-4d91-b51d-5c823e7321a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39460
4670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_length_out_transaction.394604670
Directory /workspace/21.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_max_usb_traffic.4055476216
Short name T718
Test name
Test status
Simulation time 4445738545 ps
CPU time 127.37 seconds
Started Jul 22 05:59:45 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206916 kb
Host smart-ce3cbb1c-c293-4512-aa3b-63540e1829fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40554
76216 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_max_usb_traffic.4055476216
Directory /workspace/21.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/21.usbdev_min_inter_pkt_delay.1492128146
Short name T146
Test name
Test status
Simulation time 4841237661 ps
CPU time 43.9 seconds
Started Jul 22 05:59:38 PM PDT 24
Finished Jul 22 06:00:23 PM PDT 24
Peak memory 206876 kb
Host smart-c138b474-1ac3-4a04-b157-5953694c595b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1492128146 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_inter_pkt_delay.1492128146
Directory /workspace/21.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/21.usbdev_min_length_in_transaction.1409870316
Short name T576
Test name
Test status
Simulation time 153509864 ps
CPU time 0.77 seconds
Started Jul 22 05:59:42 PM PDT 24
Finished Jul 22 05:59:43 PM PDT 24
Peak memory 206748 kb
Host smart-e24134c0-fbd4-4c77-8d28-47d436a07833
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1409870316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_in_transaction.1409870316
Directory /workspace/21.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_min_length_out_transaction.784207131
Short name T371
Test name
Test status
Simulation time 187686104 ps
CPU time 0.81 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:42 PM PDT 24
Peak memory 206740 kb
Host smart-980b3e03-aa83-430d-bdde-7a1c688e53e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78420
7131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_min_length_out_transaction.784207131
Directory /workspace/21.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_nak_trans.4095894787
Short name T118
Test name
Test status
Simulation time 233171582 ps
CPU time 0.96 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:42 PM PDT 24
Peak memory 206664 kb
Host smart-162d7a8f-dd28-4fe0-a6e8-5c41a74f5cdd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40958
94787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_nak_trans.4095894787
Directory /workspace/21.usbdev_nak_trans/latest

Test location /workspace/coverage/default/21.usbdev_out_iso.2287076712
Short name T2317
Test name
Test status
Simulation time 166189416 ps
CPU time 0.87 seconds
Started Jul 22 05:59:55 PM PDT 24
Finished Jul 22 05:59:57 PM PDT 24
Peak memory 206708 kb
Host smart-c6dd8530-2ad1-435f-9e01-1ca50ee9b8e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22870
76712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_iso.2287076712
Directory /workspace/21.usbdev_out_iso/latest

Test location /workspace/coverage/default/21.usbdev_out_stall.3266249160
Short name T2144
Test name
Test status
Simulation time 177322254 ps
CPU time 0.83 seconds
Started Jul 22 05:59:40 PM PDT 24
Finished Jul 22 05:59:41 PM PDT 24
Peak memory 206668 kb
Host smart-43d2a426-5739-4fe4-83e1-ff57deb3c515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
49160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_stall.3266249160
Directory /workspace/21.usbdev_out_stall/latest

Test location /workspace/coverage/default/21.usbdev_out_trans_nak.4218360479
Short name T610
Test name
Test status
Simulation time 232388937 ps
CPU time 0.84 seconds
Started Jul 22 06:00:03 PM PDT 24
Finished Jul 22 06:00:04 PM PDT 24
Peak memory 206772 kb
Host smart-f4709445-acd3-403a-913b-d236abc8ef5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42183
60479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_out_trans_nak.4218360479
Directory /workspace/21.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/21.usbdev_pending_in_trans.1469833548
Short name T2643
Test name
Test status
Simulation time 153977554 ps
CPU time 0.81 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:43 PM PDT 24
Peak memory 206712 kb
Host smart-0d7481a7-c1b2-4c09-8d7a-54c09d4fecb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14698
33548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pending_in_trans.1469833548
Directory /workspace/21.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_pinflip.1843618136
Short name T1684
Test name
Test status
Simulation time 211311191 ps
CPU time 0.93 seconds
Started Jul 22 05:59:36 PM PDT 24
Finished Jul 22 05:59:37 PM PDT 24
Peak memory 206752 kb
Host smart-84e8475d-e268-437c-bd1a-98f01ba3694a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1843618136 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_pinflip.1843618136
Directory /workspace/21.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/21.usbdev_phy_config_usb_ref_disable.3502743700
Short name T2465
Test name
Test status
Simulation time 141298425 ps
CPU time 0.77 seconds
Started Jul 22 05:59:38 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206744 kb
Host smart-9638b8d0-fa69-4580-86b0-98256ff57b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35027
43700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_config_usb_ref_disable.3502743700
Directory /workspace/21.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/21.usbdev_phy_pins_sense.1773198862
Short name T2632
Test name
Test status
Simulation time 56777284 ps
CPU time 0.68 seconds
Started Jul 22 05:59:40 PM PDT 24
Finished Jul 22 05:59:41 PM PDT 24
Peak memory 206700 kb
Host smart-d2c08b9e-4ccb-41c9-9172-c7dc26bbca64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17731
98862 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_phy_pins_sense.1773198862
Directory /workspace/21.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/21.usbdev_pkt_buffer.251181689
Short name T1652
Test name
Test status
Simulation time 14777921003 ps
CPU time 32.7 seconds
Started Jul 22 05:59:39 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206920 kb
Host smart-adc2ea8d-83ba-44dd-bb7c-1ebd3edf03a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25118
1689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_buffer.251181689
Directory /workspace/21.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/21.usbdev_pkt_received.1351649174
Short name T440
Test name
Test status
Simulation time 193875526 ps
CPU time 0.89 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:42 PM PDT 24
Peak memory 206740 kb
Host smart-7d411b5a-c3db-45d7-9575-af1550c0208a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13516
49174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_received.1351649174
Directory /workspace/21.usbdev_pkt_received/latest

Test location /workspace/coverage/default/21.usbdev_pkt_sent.1284744209
Short name T487
Test name
Test status
Simulation time 186682650 ps
CPU time 0.89 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206728 kb
Host smart-d5541965-eab2-4130-8a08-c293fb8898cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12847
44209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_pkt_sent.1284744209
Directory /workspace/21.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/21.usbdev_random_length_in_transaction.2738715503
Short name T2393
Test name
Test status
Simulation time 163822371 ps
CPU time 0.76 seconds
Started Jul 22 05:59:38 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206752 kb
Host smart-f837c56a-ddc6-4ef4-9ea6-f77a9107f51a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27387
15503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_in_transaction.2738715503
Directory /workspace/21.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/21.usbdev_random_length_out_transaction.663965310
Short name T511
Test name
Test status
Simulation time 159633709 ps
CPU time 0.76 seconds
Started Jul 22 05:59:42 PM PDT 24
Finished Jul 22 05:59:43 PM PDT 24
Peak memory 206736 kb
Host smart-4d84f81d-2e1a-42c3-a2c2-d729aac2bf7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66396
5310 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_random_length_out_transaction.663965310
Directory /workspace/21.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/21.usbdev_setup_stage.1670699269
Short name T626
Test name
Test status
Simulation time 148769569 ps
CPU time 0.76 seconds
Started Jul 22 05:59:39 PM PDT 24
Finished Jul 22 05:59:41 PM PDT 24
Peak memory 206748 kb
Host smart-618a1579-8af2-42cd-96e4-9aadc19ab8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16706
99269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_stage.1670699269
Directory /workspace/21.usbdev_setup_stage/latest

Test location /workspace/coverage/default/21.usbdev_setup_trans_ignored.664336246
Short name T2150
Test name
Test status
Simulation time 201623689 ps
CPU time 0.81 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 206756 kb
Host smart-cd0001cf-12eb-4fbc-8ae1-112ccad4251a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66433
6246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_setup_trans_ignored.664336246
Directory /workspace/21.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/21.usbdev_smoke.825575070
Short name T2410
Test name
Test status
Simulation time 279390884 ps
CPU time 0.98 seconds
Started Jul 22 05:59:39 PM PDT 24
Finished Jul 22 05:59:41 PM PDT 24
Peak memory 206740 kb
Host smart-d738aea0-4c31-4354-8f8a-7fb84294b8e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82557
5070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_smoke.825575070
Directory /workspace/21.usbdev_smoke/latest

Test location /workspace/coverage/default/21.usbdev_spurious_pids_ignored.1607979744
Short name T104
Test name
Test status
Simulation time 6427529919 ps
CPU time 48.01 seconds
Started Jul 22 05:59:40 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206892 kb
Host smart-70113006-0c15-4d06-bc4f-919f48d3a213
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1607979744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_spurious_pids_ignored.1607979744
Directory /workspace/21.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/21.usbdev_stall_priority_over_nak.124659686
Short name T2355
Test name
Test status
Simulation time 191462853 ps
CPU time 0.84 seconds
Started Jul 22 06:01:04 PM PDT 24
Finished Jul 22 06:01:05 PM PDT 24
Peak memory 206756 kb
Host smart-003dea77-9a18-400f-a1ef-23fd118394d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
9686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_priority_over_nak.124659686
Directory /workspace/21.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/21.usbdev_stall_trans.2962483135
Short name T1012
Test name
Test status
Simulation time 198574201 ps
CPU time 0.83 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:42 PM PDT 24
Peak memory 206752 kb
Host smart-c7c42d8d-3341-4e5e-a7fb-883ac737198b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29624
83135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stall_trans.2962483135
Directory /workspace/21.usbdev_stall_trans/latest

Test location /workspace/coverage/default/21.usbdev_stream_len_max.3384688591
Short name T1676
Test name
Test status
Simulation time 1164314979 ps
CPU time 2.44 seconds
Started Jul 22 05:59:36 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206884 kb
Host smart-7615b72b-e42b-49ce-b221-e39e90d0d574
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33846
88591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_stream_len_max.3384688591
Directory /workspace/21.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/21.usbdev_streaming_out.3328693664
Short name T944
Test name
Test status
Simulation time 4387347784 ps
CPU time 42.39 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:01:04 PM PDT 24
Peak memory 206856 kb
Host smart-b1b898d5-59d7-4933-bac2-854cae254662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33286
93664 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.usbdev_streaming_out.3328693664
Directory /workspace/21.usbdev_streaming_out/latest

Test location /workspace/coverage/default/22.usbdev_alert_test.352112198
Short name T1428
Test name
Test status
Simulation time 53192854 ps
CPU time 0.65 seconds
Started Jul 22 05:59:50 PM PDT 24
Finished Jul 22 05:59:51 PM PDT 24
Peak memory 206672 kb
Host smart-9a5ea7e4-9b04-4de2-81a5-d04fef1c90e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=352112198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_alert_test.352112198
Directory /workspace/22.usbdev_alert_test/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_disconnect.3059676925
Short name T2588
Test name
Test status
Simulation time 4374069482 ps
CPU time 6.1 seconds
Started Jul 22 05:59:38 PM PDT 24
Finished Jul 22 05:59:44 PM PDT 24
Peak memory 207112 kb
Host smart-95ed7c17-35ed-4dde-ac88-a728b93e2cd5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3059676925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_disconnect.3059676925
Directory /workspace/22.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_reset.2361527081
Short name T1595
Test name
Test status
Simulation time 13507494539 ps
CPU time 15.21 seconds
Started Jul 22 05:59:43 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206940 kb
Host smart-298359b1-ad46-4b16-9017-6a161491119e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2361527081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_reset.2361527081
Directory /workspace/22.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/22.usbdev_aon_wake_resume.4110946596
Short name T1776
Test name
Test status
Simulation time 23347163321 ps
CPU time 28.36 seconds
Started Jul 22 05:59:39 PM PDT 24
Finished Jul 22 06:00:08 PM PDT 24
Peak memory 206804 kb
Host smart-6b957fdb-211a-48f8-82f9-afdb97c02fc5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4110946596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_aon_wake_resume.4110946596
Directory /workspace/22.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/22.usbdev_av_buffer.567184080
Short name T1125
Test name
Test status
Simulation time 161224359 ps
CPU time 0.92 seconds
Started Jul 22 06:00:03 PM PDT 24
Finished Jul 22 06:00:04 PM PDT 24
Peak memory 206768 kb
Host smart-19535362-2fa3-42e6-b13e-b281abdf5e6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56718
4080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_av_buffer.567184080
Directory /workspace/22.usbdev_av_buffer/latest

Test location /workspace/coverage/default/22.usbdev_bitstuff_err.3892852733
Short name T1496
Test name
Test status
Simulation time 151314853 ps
CPU time 0.77 seconds
Started Jul 22 05:59:38 PM PDT 24
Finished Jul 22 05:59:39 PM PDT 24
Peak memory 206908 kb
Host smart-f3345455-b883-4e93-bc96-e982b1cc2d74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38928
52733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_bitstuff_err.3892852733
Directory /workspace/22.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_clear.3277872511
Short name T770
Test name
Test status
Simulation time 254876223 ps
CPU time 0.94 seconds
Started Jul 22 06:02:08 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206572 kb
Host smart-3195cfec-b881-46ed-b712-ccd5e424f282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32778
72511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_clear.3277872511
Directory /workspace/22.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/22.usbdev_data_toggle_restore.1865476414
Short name T23
Test name
Test status
Simulation time 1202036478 ps
CPU time 2.69 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206848 kb
Host smart-03d7b3f5-07b7-4c56-8e5a-1b3d8a66f6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18654
76414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_data_toggle_restore.1865476414
Directory /workspace/22.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/22.usbdev_device_address.3825502013
Short name T1295
Test name
Test status
Simulation time 19816006705 ps
CPU time 41.19 seconds
Started Jul 22 05:59:45 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206972 kb
Host smart-883d63d6-3048-42b6-a52a-ffb9d012be4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38255
02013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_device_address.3825502013
Directory /workspace/22.usbdev_device_address/latest

Test location /workspace/coverage/default/22.usbdev_disable_endpoint.3064737061
Short name T1183
Test name
Test status
Simulation time 466638059 ps
CPU time 1.3 seconds
Started Jul 22 05:59:48 PM PDT 24
Finished Jul 22 05:59:50 PM PDT 24
Peak memory 206752 kb
Host smart-da727e5a-d7ea-4259-9c08-3cf50cf3cd0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30647
37061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disable_endpoint.3064737061
Directory /workspace/22.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/22.usbdev_disconnected.4188951230
Short name T2092
Test name
Test status
Simulation time 151373350 ps
CPU time 0.73 seconds
Started Jul 22 06:00:59 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 206756 kb
Host smart-03c270b1-b793-420d-845b-519280b768b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41889
51230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_disconnected.4188951230
Directory /workspace/22.usbdev_disconnected/latest

Test location /workspace/coverage/default/22.usbdev_enable.904977657
Short name T2261
Test name
Test status
Simulation time 46849664 ps
CPU time 0.73 seconds
Started Jul 22 05:59:39 PM PDT 24
Finished Jul 22 05:59:40 PM PDT 24
Peak memory 206684 kb
Host smart-277c03c0-2655-4aa7-b062-e5380367f554
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90497
7657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_enable.904977657
Directory /workspace/22.usbdev_enable/latest

Test location /workspace/coverage/default/22.usbdev_endpoint_access.3531324225
Short name T949
Test name
Test status
Simulation time 857547834 ps
CPU time 1.96 seconds
Started Jul 22 05:59:42 PM PDT 24
Finished Jul 22 05:59:44 PM PDT 24
Peak memory 206840 kb
Host smart-0252a168-229a-4dfd-a166-5b86e4c1bda2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35313
24225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_endpoint_access.3531324225
Directory /workspace/22.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/22.usbdev_fifo_rst.1804358539
Short name T1019
Test name
Test status
Simulation time 287376258 ps
CPU time 2.13 seconds
Started Jul 22 05:59:42 PM PDT 24
Finished Jul 22 05:59:45 PM PDT 24
Peak memory 206804 kb
Host smart-90c032cb-f054-41d2-919f-afa9bb8fa717
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18043
58539 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_fifo_rst.1804358539
Directory /workspace/22.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/22.usbdev_in_iso.2916048342
Short name T1634
Test name
Test status
Simulation time 222406001 ps
CPU time 0.82 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 05:59:49 PM PDT 24
Peak memory 206740 kb
Host smart-417aeaa1-4ade-4cb9-8877-69ecb1d45e8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29160
48342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_iso.2916048342
Directory /workspace/22.usbdev_in_iso/latest

Test location /workspace/coverage/default/22.usbdev_in_stall.1174652975
Short name T1785
Test name
Test status
Simulation time 158685814 ps
CPU time 0.76 seconds
Started Jul 22 05:59:41 PM PDT 24
Finished Jul 22 05:59:42 PM PDT 24
Peak memory 206756 kb
Host smart-2c70226a-949b-44d0-8462-c0a2a1da0dfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11746
52975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_stall.1174652975
Directory /workspace/22.usbdev_in_stall/latest

Test location /workspace/coverage/default/22.usbdev_in_trans.3640980188
Short name T338
Test name
Test status
Simulation time 209229913 ps
CPU time 0.84 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 05:59:49 PM PDT 24
Peak memory 206748 kb
Host smart-5001e5e1-2f54-4e48-8c4c-d02712224367
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36409
80188 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_in_trans.3640980188
Directory /workspace/22.usbdev_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_iso_retraction.261545599
Short name T1321
Test name
Test status
Simulation time 11348822008 ps
CPU time 95.9 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 06:01:24 PM PDT 24
Peak memory 206828 kb
Host smart-d76b5dda-4889-4dce-afe9-cd01a107409e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26154
5599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_iso_retraction.261545599
Directory /workspace/22.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/22.usbdev_link_in_err.1433067558
Short name T2583
Test name
Test status
Simulation time 227635485 ps
CPU time 0.8 seconds
Started Jul 22 05:59:37 PM PDT 24
Finished Jul 22 05:59:38 PM PDT 24
Peak memory 206876 kb
Host smart-5e327623-87a0-424d-a720-e6b58ca6674f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14330
67558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_in_err.1433067558
Directory /workspace/22.usbdev_link_in_err/latest

Test location /workspace/coverage/default/22.usbdev_link_resume.3476046088
Short name T1612
Test name
Test status
Simulation time 23343237388 ps
CPU time 30.19 seconds
Started Jul 22 05:59:48 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206804 kb
Host smart-54e654fe-c89c-46c6-b678-6ce3dae78c12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34760
46088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_resume.3476046088
Directory /workspace/22.usbdev_link_resume/latest

Test location /workspace/coverage/default/22.usbdev_link_suspend.3596385
Short name T1414
Test name
Test status
Simulation time 3301072474 ps
CPU time 3.38 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 206768 kb
Host smart-86633f52-2392-4105-8b79-d21125d4cda5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35963
85 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_link_suspend.3596385
Directory /workspace/22.usbdev_link_suspend/latest

Test location /workspace/coverage/default/22.usbdev_low_speed_traffic.698995499
Short name T2155
Test name
Test status
Simulation time 8129695950 ps
CPU time 219.28 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 06:03:28 PM PDT 24
Peak memory 206912 kb
Host smart-1e0c92e4-37b4-44ab-885a-999e40a6874b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69899
5499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_low_speed_traffic.698995499
Directory /workspace/22.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/22.usbdev_max_inter_pkt_delay.4220566210
Short name T2143
Test name
Test status
Simulation time 7502411951 ps
CPU time 69.26 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 06:00:57 PM PDT 24
Peak memory 206896 kb
Host smart-962261d4-5794-4652-adb0-1ba9dff185d6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4220566210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_inter_pkt_delay.4220566210
Directory /workspace/22.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_max_length_in_transaction.827676672
Short name T1850
Test name
Test status
Simulation time 267376905 ps
CPU time 0.91 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:04 PM PDT 24
Peak memory 206752 kb
Host smart-27386f13-1f07-4cc0-b9f1-c14f452f9b00
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=827676672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_in_transaction.827676672
Directory /workspace/22.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_length_out_transaction.2346528370
Short name T325
Test name
Test status
Simulation time 183297867 ps
CPU time 0.82 seconds
Started Jul 22 05:59:48 PM PDT 24
Finished Jul 22 05:59:50 PM PDT 24
Peak memory 206752 kb
Host smart-5c8834be-75eb-49c3-b0d9-795ed07e1a45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23465
28370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_length_out_transaction.2346528370
Directory /workspace/22.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_max_usb_traffic.2595161261
Short name T148
Test name
Test status
Simulation time 4506099309 ps
CPU time 41.14 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 06:00:36 PM PDT 24
Peak memory 206888 kb
Host smart-cae88489-9e99-434d-b7e1-99462c7961ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25951
61261 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_max_usb_traffic.2595161261
Directory /workspace/22.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/22.usbdev_min_inter_pkt_delay.2938754813
Short name T421
Test name
Test status
Simulation time 3944063315 ps
CPU time 28.15 seconds
Started Jul 22 05:59:53 PM PDT 24
Finished Jul 22 06:00:22 PM PDT 24
Peak memory 206900 kb
Host smart-219a7bcf-b79d-44c8-be4e-e40308eaef7b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2938754813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_inter_pkt_delay.2938754813
Directory /workspace/22.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/22.usbdev_min_length_in_transaction.1873879006
Short name T954
Test name
Test status
Simulation time 154639176 ps
CPU time 0.74 seconds
Started Jul 22 05:59:51 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 206724 kb
Host smart-86d90996-0396-4290-be34-7ae1f948e314
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1873879006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_in_transaction.1873879006
Directory /workspace/22.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_min_length_out_transaction.2591743557
Short name T657
Test name
Test status
Simulation time 164780027 ps
CPU time 0.8 seconds
Started Jul 22 05:59:46 PM PDT 24
Finished Jul 22 05:59:47 PM PDT 24
Peak memory 206728 kb
Host smart-4090a39d-1ab1-48e8-a1a9-142325da7198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25917
43557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_min_length_out_transaction.2591743557
Directory /workspace/22.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_nak_trans.3255954306
Short name T1377
Test name
Test status
Simulation time 202597486 ps
CPU time 0.86 seconds
Started Jul 22 05:59:45 PM PDT 24
Finished Jul 22 05:59:47 PM PDT 24
Peak memory 206768 kb
Host smart-099d673e-9262-4082-9b2f-f7586bf77b2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32559
54306 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_nak_trans.3255954306
Directory /workspace/22.usbdev_nak_trans/latest

Test location /workspace/coverage/default/22.usbdev_out_iso.415581233
Short name T2435
Test name
Test status
Simulation time 189849817 ps
CPU time 0.83 seconds
Started Jul 22 06:00:17 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206704 kb
Host smart-8c20e786-61c7-4c55-8d29-addf798b0d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41558
1233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_iso.415581233
Directory /workspace/22.usbdev_out_iso/latest

Test location /workspace/coverage/default/22.usbdev_out_stall.2395444815
Short name T2722
Test name
Test status
Simulation time 186960701 ps
CPU time 0.85 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206752 kb
Host smart-63c6154c-9e45-41f8-8b8a-d98c39a54071
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23954
44815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_stall.2395444815
Directory /workspace/22.usbdev_out_stall/latest

Test location /workspace/coverage/default/22.usbdev_out_trans_nak.772819241
Short name T1004
Test name
Test status
Simulation time 185811945 ps
CPU time 0.8 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206736 kb
Host smart-d2822ece-5206-4938-8132-9cde2064029b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77281
9241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_out_trans_nak.772819241
Directory /workspace/22.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/22.usbdev_pending_in_trans.928121982
Short name T34
Test name
Test status
Simulation time 156112330 ps
CPU time 0.78 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 206748 kb
Host smart-cc7ef0c2-eea3-4d2e-87c4-5e80c8a116ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92812
1982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pending_in_trans.928121982
Directory /workspace/22.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_pinflip.1694390470
Short name T1580
Test name
Test status
Simulation time 267761762 ps
CPU time 0.94 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 206748 kb
Host smart-4ab1ed72-b384-4b2b-bfd4-70b7f20b8ea9
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1694390470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_pinflip.1694390470
Directory /workspace/22.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/22.usbdev_phy_config_usb_ref_disable.3471331122
Short name T486
Test name
Test status
Simulation time 143349714 ps
CPU time 0.81 seconds
Started Jul 22 05:59:43 PM PDT 24
Finished Jul 22 05:59:45 PM PDT 24
Peak memory 206748 kb
Host smart-63b9c180-bd17-4cbd-9082-a387e7820d14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34713
31122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_config_usb_ref_disable.3471331122
Directory /workspace/22.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/22.usbdev_phy_pins_sense.523325469
Short name T1330
Test name
Test status
Simulation time 53243107 ps
CPU time 0.69 seconds
Started Jul 22 05:59:45 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 206760 kb
Host smart-3a5516b8-67c3-4d03-a4e7-d28598b87329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52332
5469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_phy_pins_sense.523325469
Directory /workspace/22.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/22.usbdev_pkt_buffer.1489516214
Short name T2457
Test name
Test status
Simulation time 8622445643 ps
CPU time 19.13 seconds
Started Jul 22 05:59:49 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 207016 kb
Host smart-ee06af5f-7fcf-4bfb-8780-9a19d23c93aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14895
16214 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_buffer.1489516214
Directory /workspace/22.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/22.usbdev_pkt_received.62152666
Short name T489
Test name
Test status
Simulation time 188006383 ps
CPU time 0.87 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 05:59:45 PM PDT 24
Peak memory 206688 kb
Host smart-aaec5bd7-eb12-4911-875b-528da00c95b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62152
666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_received.62152666
Directory /workspace/22.usbdev_pkt_received/latest

Test location /workspace/coverage/default/22.usbdev_pkt_sent.2883508205
Short name T497
Test name
Test status
Simulation time 201707581 ps
CPU time 0.86 seconds
Started Jul 22 06:00:17 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206708 kb
Host smart-50dd8e11-b5a7-48b7-8290-424de7fe3055
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28835
08205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_pkt_sent.2883508205
Directory /workspace/22.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/22.usbdev_random_length_in_transaction.137181166
Short name T1677
Test name
Test status
Simulation time 217566233 ps
CPU time 0.92 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206752 kb
Host smart-f0667da0-df3a-4786-983d-fe69124d6337
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13718
1166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_in_transaction.137181166
Directory /workspace/22.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/22.usbdev_random_length_out_transaction.2076695607
Short name T710
Test name
Test status
Simulation time 204452706 ps
CPU time 0.88 seconds
Started Jul 22 05:59:50 PM PDT 24
Finished Jul 22 05:59:52 PM PDT 24
Peak memory 206696 kb
Host smart-4d626658-b9e4-466c-8ba6-e629a1923e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20766
95607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_random_length_out_transaction.2076695607
Directory /workspace/22.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/22.usbdev_rx_crc_err.3446844719
Short name T1268
Test name
Test status
Simulation time 150333465 ps
CPU time 0.75 seconds
Started Jul 22 05:59:53 PM PDT 24
Finished Jul 22 05:59:55 PM PDT 24
Peak memory 206736 kb
Host smart-14de7c23-bc8a-48f0-a5c1-e21b1d26e3be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34468
44719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_rx_crc_err.3446844719
Directory /workspace/22.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/22.usbdev_setup_stage.2824229904
Short name T1379
Test name
Test status
Simulation time 148177946 ps
CPU time 0.76 seconds
Started Jul 22 05:59:52 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206732 kb
Host smart-202c9aa9-c6f2-4dad-97f4-5b4707b56d38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28242
29904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_stage.2824229904
Directory /workspace/22.usbdev_setup_stage/latest

Test location /workspace/coverage/default/22.usbdev_setup_trans_ignored.4041420985
Short name T607
Test name
Test status
Simulation time 143982475 ps
CPU time 0.78 seconds
Started Jul 22 05:59:45 PM PDT 24
Finished Jul 22 05:59:47 PM PDT 24
Peak memory 206748 kb
Host smart-f4dbe074-1460-4071-adc2-8e7e5698ef8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40414
20985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_setup_trans_ignored.4041420985
Directory /workspace/22.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/22.usbdev_smoke.398573109
Short name T1947
Test name
Test status
Simulation time 231875129 ps
CPU time 0.94 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 206700 kb
Host smart-d47e1de3-a36d-45c5-bace-8e1288a995c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39857
3109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_smoke.398573109
Directory /workspace/22.usbdev_smoke/latest

Test location /workspace/coverage/default/22.usbdev_spurious_pids_ignored.2793243090
Short name T2046
Test name
Test status
Simulation time 4849707681 ps
CPU time 35.37 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206964 kb
Host smart-74b4908f-4b84-4b92-a356-84d8fc37fbc8
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2793243090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_spurious_pids_ignored.2793243090
Directory /workspace/22.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/22.usbdev_stall_priority_over_nak.3723511980
Short name T1735
Test name
Test status
Simulation time 204447119 ps
CPU time 0.83 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 05:59:45 PM PDT 24
Peak memory 206736 kb
Host smart-6bed6244-dc06-42b9-8e61-4af17d9e8ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37235
11980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_priority_over_nak.3723511980
Directory /workspace/22.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/22.usbdev_stall_trans.2841238094
Short name T693
Test name
Test status
Simulation time 169040872 ps
CPU time 0.87 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 05:59:49 PM PDT 24
Peak memory 206740 kb
Host smart-f3a99588-4d2b-45db-8930-5a3c8e15d44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28412
38094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stall_trans.2841238094
Directory /workspace/22.usbdev_stall_trans/latest

Test location /workspace/coverage/default/22.usbdev_stream_len_max.602176369
Short name T1772
Test name
Test status
Simulation time 962524656 ps
CPU time 2.12 seconds
Started Jul 22 05:59:48 PM PDT 24
Finished Jul 22 05:59:51 PM PDT 24
Peak memory 206884 kb
Host smart-e4fc3ad8-1fcd-4c52-8a47-d8263c74ca9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60217
6369 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_stream_len_max.602176369
Directory /workspace/22.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/22.usbdev_streaming_out.595874489
Short name T527
Test name
Test status
Simulation time 5972915797 ps
CPU time 169.03 seconds
Started Jul 22 05:59:44 PM PDT 24
Finished Jul 22 06:02:34 PM PDT 24
Peak memory 207020 kb
Host smart-b3690d69-9502-493b-8e53-94f0582c3266
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59587
4489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.usbdev_streaming_out.595874489
Directory /workspace/22.usbdev_streaming_out/latest

Test location /workspace/coverage/default/23.usbdev_alert_test.214844394
Short name T2366
Test name
Test status
Simulation time 61464455 ps
CPU time 0.71 seconds
Started Jul 22 06:00:02 PM PDT 24
Finished Jul 22 06:00:03 PM PDT 24
Peak memory 206928 kb
Host smart-818d241a-7f0a-4f42-bf78-a3cb9d97e06d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=214844394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_alert_test.214844394
Directory /workspace/23.usbdev_alert_test/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_disconnect.3133293260
Short name T1873
Test name
Test status
Simulation time 4289867672 ps
CPU time 4.98 seconds
Started Jul 22 05:59:47 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206792 kb
Host smart-9b7b5997-9b71-4753-9540-079dffbf3aaa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3133293260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_disconnect.3133293260
Directory /workspace/23.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_reset.406716603
Short name T866
Test name
Test status
Simulation time 13376695343 ps
CPU time 12.69 seconds
Started Jul 22 05:59:53 PM PDT 24
Finished Jul 22 06:00:06 PM PDT 24
Peak memory 206968 kb
Host smart-2403fd8a-dcdd-48e5-9733-facdbe2d924f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=406716603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_reset.406716603
Directory /workspace/23.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/23.usbdev_aon_wake_resume.2277569319
Short name T2590
Test name
Test status
Simulation time 23371353139 ps
CPU time 25.6 seconds
Started Jul 22 06:00:02 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206816 kb
Host smart-9d0483ef-e087-4c1b-a5e5-986211079e71
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2277569319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_aon_wake_resume.2277569319
Directory /workspace/23.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/23.usbdev_av_buffer.1160952973
Short name T2471
Test name
Test status
Simulation time 210414531 ps
CPU time 0.84 seconds
Started Jul 22 05:59:48 PM PDT 24
Finished Jul 22 05:59:50 PM PDT 24
Peak memory 206732 kb
Host smart-d40dbf53-f7fd-4781-9354-170aa0b7298b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11609
52973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_av_buffer.1160952973
Directory /workspace/23.usbdev_av_buffer/latest

Test location /workspace/coverage/default/23.usbdev_bitstuff_err.2839362808
Short name T67
Test name
Test status
Simulation time 153329429 ps
CPU time 0.79 seconds
Started Jul 22 05:59:46 PM PDT 24
Finished Jul 22 05:59:48 PM PDT 24
Peak memory 206760 kb
Host smart-4ec00fac-ff29-43e7-9853-f2c94249aa8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28393
62808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_bitstuff_err.2839362808
Directory /workspace/23.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_clear.2693644778
Short name T2021
Test name
Test status
Simulation time 447043717 ps
CPU time 1.36 seconds
Started Jul 22 05:59:50 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206692 kb
Host smart-07401798-ea9d-4521-bc21-b8ad3ab6d618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26936
44778 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_clear.2693644778
Directory /workspace/23.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/23.usbdev_data_toggle_restore.2724419769
Short name T1484
Test name
Test status
Simulation time 313408179 ps
CPU time 0.99 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206752 kb
Host smart-914c811a-ad05-4ac2-8ffc-9934dc46c3f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27244
19769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_data_toggle_restore.2724419769
Directory /workspace/23.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/23.usbdev_device_address.530944666
Short name T162
Test name
Test status
Simulation time 22721522506 ps
CPU time 42.21 seconds
Started Jul 22 05:59:42 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206948 kb
Host smart-9db1250e-2969-4d09-9711-d9327e16ae65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53094
4666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_device_address.530944666
Directory /workspace/23.usbdev_device_address/latest

Test location /workspace/coverage/default/23.usbdev_disable_endpoint.4195345105
Short name T939
Test name
Test status
Simulation time 335611033 ps
CPU time 1.12 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206700 kb
Host smart-6a6d2707-f204-4a68-a824-eec27f7cd2c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41953
45105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disable_endpoint.4195345105
Directory /workspace/23.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/23.usbdev_disconnected.113711723
Short name T1549
Test name
Test status
Simulation time 141072780 ps
CPU time 0.8 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206748 kb
Host smart-64ac2503-c332-49c8-8992-2f91dcc0da9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11371
1723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_disconnected.113711723
Directory /workspace/23.usbdev_disconnected/latest

Test location /workspace/coverage/default/23.usbdev_enable.3282837746
Short name T453
Test name
Test status
Simulation time 39142497 ps
CPU time 0.66 seconds
Started Jul 22 06:00:02 PM PDT 24
Finished Jul 22 06:00:03 PM PDT 24
Peak memory 206736 kb
Host smart-99617586-ca05-4608-90ad-533ce4035610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32828
37746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_enable.3282837746
Directory /workspace/23.usbdev_enable/latest

Test location /workspace/coverage/default/23.usbdev_endpoint_access.4273036773
Short name T2575
Test name
Test status
Simulation time 1047732152 ps
CPU time 2.41 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 06:00:00 PM PDT 24
Peak memory 206884 kb
Host smart-8d37f346-50e7-43a0-a874-34211269907d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42730
36773 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_endpoint_access.4273036773
Directory /workspace/23.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/23.usbdev_fifo_rst.4283488446
Short name T2378
Test name
Test status
Simulation time 220859976 ps
CPU time 1.32 seconds
Started Jul 22 05:59:55 PM PDT 24
Finished Jul 22 05:59:57 PM PDT 24
Peak memory 206772 kb
Host smart-a65996ba-411a-4df7-b157-acd93746a998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42834
88446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_fifo_rst.4283488446
Directory /workspace/23.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/23.usbdev_in_iso.3337613677
Short name T246
Test name
Test status
Simulation time 301769298 ps
CPU time 0.94 seconds
Started Jul 22 06:00:00 PM PDT 24
Finished Jul 22 06:00:01 PM PDT 24
Peak memory 206740 kb
Host smart-2d08b04a-a569-4c1e-a31f-5dc354ebd29c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33376
13677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_iso.3337613677
Directory /workspace/23.usbdev_in_iso/latest

Test location /workspace/coverage/default/23.usbdev_in_stall.1719445965
Short name T919
Test name
Test status
Simulation time 184168109 ps
CPU time 0.83 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206704 kb
Host smart-24d66228-3e07-444b-a9a7-81d5ea0dd7da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17194
45965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_stall.1719445965
Directory /workspace/23.usbdev_in_stall/latest

Test location /workspace/coverage/default/23.usbdev_in_trans.1977542039
Short name T995
Test name
Test status
Simulation time 196549727 ps
CPU time 0.93 seconds
Started Jul 22 06:00:02 PM PDT 24
Finished Jul 22 06:00:03 PM PDT 24
Peak memory 206712 kb
Host smart-0dac5877-15f4-47d5-9692-4602e7c2a596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19775
42039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_in_trans.1977542039
Directory /workspace/23.usbdev_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_invalid_sync.2759017158
Short name T2026
Test name
Test status
Simulation time 7857217482 ps
CPU time 222.24 seconds
Started Jul 22 06:00:19 PM PDT 24
Finished Jul 22 06:04:02 PM PDT 24
Peak memory 206904 kb
Host smart-2482cf14-aab6-4a40-bb3d-270524f51978
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2759017158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_invalid_sync.2759017158
Directory /workspace/23.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/23.usbdev_iso_retraction.3133272746
Short name T1909
Test name
Test status
Simulation time 12599375750 ps
CPU time 108.78 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 06:01:46 PM PDT 24
Peak memory 206888 kb
Host smart-94a858c8-b714-43c4-8d22-4343790de393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31332
72746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_iso_retraction.3133272746
Directory /workspace/23.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/23.usbdev_link_in_err.3521158471
Short name T493
Test name
Test status
Simulation time 270303841 ps
CPU time 0.97 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206752 kb
Host smart-54fa2a7b-1827-4610-a603-310ec0c8d690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35211
58471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_in_err.3521158471
Directory /workspace/23.usbdev_link_in_err/latest

Test location /workspace/coverage/default/23.usbdev_link_resume.262776781
Short name T445
Test name
Test status
Simulation time 23322904491 ps
CPU time 22.2 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206788 kb
Host smart-864147bc-661e-4731-b3a2-f533eb374bf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
6781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_resume.262776781
Directory /workspace/23.usbdev_link_resume/latest

Test location /workspace/coverage/default/23.usbdev_link_suspend.401787046
Short name T443
Test name
Test status
Simulation time 3347260724 ps
CPU time 3.88 seconds
Started Jul 22 05:59:57 PM PDT 24
Finished Jul 22 06:00:02 PM PDT 24
Peak memory 206792 kb
Host smart-830d546f-e707-454c-9859-27077b55f2bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40178
7046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_link_suspend.401787046
Directory /workspace/23.usbdev_link_suspend/latest

Test location /workspace/coverage/default/23.usbdev_low_speed_traffic.3408438994
Short name T2166
Test name
Test status
Simulation time 8427522324 ps
CPU time 74.15 seconds
Started Jul 22 06:00:19 PM PDT 24
Finished Jul 22 06:01:34 PM PDT 24
Peak memory 206908 kb
Host smart-9b12f685-f54b-42f3-97b8-7b3e904b4256
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34084
38994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_low_speed_traffic.3408438994
Directory /workspace/23.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/23.usbdev_max_inter_pkt_delay.1216965641
Short name T1092
Test name
Test status
Simulation time 4346495090 ps
CPU time 122.44 seconds
Started Jul 22 05:59:55 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206772 kb
Host smart-b7007840-744a-4268-8dc1-a84b36d4805d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1216965641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_inter_pkt_delay.1216965641
Directory /workspace/23.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_max_length_in_transaction.2798282204
Short name T669
Test name
Test status
Simulation time 237927587 ps
CPU time 0.93 seconds
Started Jul 22 06:00:06 PM PDT 24
Finished Jul 22 06:00:08 PM PDT 24
Peak memory 206748 kb
Host smart-831ecfbc-a7ac-480a-bc63-eb696700e312
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2798282204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_in_transaction.2798282204
Directory /workspace/23.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_length_out_transaction.229287582
Short name T1320
Test name
Test status
Simulation time 202795279 ps
CPU time 0.88 seconds
Started Jul 22 06:00:03 PM PDT 24
Finished Jul 22 06:00:04 PM PDT 24
Peak memory 206728 kb
Host smart-ea6000c3-be0e-489f-88e4-b5710f1d64e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22928
7582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_length_out_transaction.229287582
Directory /workspace/23.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_max_usb_traffic.601681186
Short name T1050
Test name
Test status
Simulation time 4450140116 ps
CPU time 32.48 seconds
Started Jul 22 06:00:01 PM PDT 24
Finished Jul 22 06:00:34 PM PDT 24
Peak memory 206940 kb
Host smart-24fe4bbf-b140-4b30-98a5-f21dd44276d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60168
1186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_max_usb_traffic.601681186
Directory /workspace/23.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/23.usbdev_min_inter_pkt_delay.1951050185
Short name T542
Test name
Test status
Simulation time 5872912122 ps
CPU time 159.68 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206864 kb
Host smart-3d3eafe2-d450-414f-a825-5a9f8e8776cd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1951050185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_inter_pkt_delay.1951050185
Directory /workspace/23.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/23.usbdev_min_length_in_transaction.4234298239
Short name T723
Test name
Test status
Simulation time 188891059 ps
CPU time 0.82 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206744 kb
Host smart-09ddd617-34ba-4a31-8557-9b1925ba2197
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4234298239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_in_transaction.4234298239
Directory /workspace/23.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_min_length_out_transaction.757023415
Short name T1719
Test name
Test status
Simulation time 162571252 ps
CPU time 0.79 seconds
Started Jul 22 05:59:55 PM PDT 24
Finished Jul 22 05:59:57 PM PDT 24
Peak memory 206740 kb
Host smart-d3d8b19d-8a7e-41d8-8e9a-fe8cddf1421e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75702
3415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_min_length_out_transaction.757023415
Directory /workspace/23.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_nak_trans.1219104635
Short name T1715
Test name
Test status
Simulation time 168237251 ps
CPU time 0.89 seconds
Started Jul 22 05:59:57 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206724 kb
Host smart-63c3bbcb-f951-4b7b-a6ea-fda75249c09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12191
04635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_nak_trans.1219104635
Directory /workspace/23.usbdev_nak_trans/latest

Test location /workspace/coverage/default/23.usbdev_out_iso.3167223577
Short name T861
Test name
Test status
Simulation time 180110583 ps
CPU time 0.84 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206696 kb
Host smart-6f9a42b2-b96f-42e0-bead-24c89e5628a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31672
23577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_iso.3167223577
Directory /workspace/23.usbdev_out_iso/latest

Test location /workspace/coverage/default/23.usbdev_out_stall.2175883760
Short name T632
Test name
Test status
Simulation time 186723070 ps
CPU time 0.9 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206748 kb
Host smart-0d0cca76-c70f-4c22-9676-d42e52906076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21758
83760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_stall.2175883760
Directory /workspace/23.usbdev_out_stall/latest

Test location /workspace/coverage/default/23.usbdev_out_trans_nak.3542423675
Short name T1685
Test name
Test status
Simulation time 152298462 ps
CPU time 0.8 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206684 kb
Host smart-adba6d32-d399-400c-a589-bd2d6376b0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35424
23675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_out_trans_nak.3542423675
Directory /workspace/23.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/23.usbdev_pending_in_trans.190685769
Short name T1051
Test name
Test status
Simulation time 156406454 ps
CPU time 0.78 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206672 kb
Host smart-cc83b39e-7ad9-4fec-8ffe-7709852ccfee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19068
5769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pending_in_trans.190685769
Directory /workspace/23.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_pinflip.2883557164
Short name T1775
Test name
Test status
Simulation time 233497367 ps
CPU time 0.96 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206524 kb
Host smart-bacb3bd6-3059-40de-8b0d-7e309e8caf0e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2883557164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_pinflip.2883557164
Directory /workspace/23.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/23.usbdev_phy_config_usb_ref_disable.3543701164
Short name T2458
Test name
Test status
Simulation time 142027724 ps
CPU time 0.78 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206748 kb
Host smart-c6704516-2867-4c67-8208-b18ca5e59c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35437
01164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_config_usb_ref_disable.3543701164
Directory /workspace/23.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/23.usbdev_phy_pins_sense.3718598962
Short name T1159
Test name
Test status
Simulation time 51671175 ps
CPU time 0.69 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206724 kb
Host smart-2ca65ffc-1b19-41f4-91ca-b98306fe7b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37185
98962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_phy_pins_sense.3718598962
Directory /workspace/23.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/23.usbdev_pkt_buffer.2184167464
Short name T2222
Test name
Test status
Simulation time 11349691980 ps
CPU time 24.54 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 06:00:20 PM PDT 24
Peak memory 206892 kb
Host smart-ba8494d4-dcd4-461b-978e-25aebaecd761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21841
67464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_buffer.2184167464
Directory /workspace/23.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/23.usbdev_pkt_received.4230594828
Short name T742
Test name
Test status
Simulation time 198031126 ps
CPU time 0.96 seconds
Started Jul 22 06:00:05 PM PDT 24
Finished Jul 22 06:00:07 PM PDT 24
Peak memory 206756 kb
Host smart-c571b42a-775d-48e0-aafe-8f36468d8fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42305
94828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_received.4230594828
Directory /workspace/23.usbdev_pkt_received/latest

Test location /workspace/coverage/default/23.usbdev_pkt_sent.952881731
Short name T1244
Test name
Test status
Simulation time 173086638 ps
CPU time 0.88 seconds
Started Jul 22 05:59:55 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206736 kb
Host smart-86feecce-a88e-4ef1-bda4-bc74502ef2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95288
1731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_pkt_sent.952881731
Directory /workspace/23.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/23.usbdev_random_length_in_transaction.1305174242
Short name T893
Test name
Test status
Simulation time 193249758 ps
CPU time 0.85 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206756 kb
Host smart-1b92be9a-e894-4f91-83bf-79277ade6058
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13051
74242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_in_transaction.1305174242
Directory /workspace/23.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/23.usbdev_random_length_out_transaction.2574890925
Short name T491
Test name
Test status
Simulation time 206883433 ps
CPU time 0.86 seconds
Started Jul 22 05:59:59 PM PDT 24
Finished Jul 22 06:00:00 PM PDT 24
Peak memory 206728 kb
Host smart-568a6d61-3b1c-40cf-b71f-27ee58e80ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25748
90925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_random_length_out_transaction.2574890925
Directory /workspace/23.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/23.usbdev_rx_crc_err.393399141
Short name T650
Test name
Test status
Simulation time 150184497 ps
CPU time 0.83 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206716 kb
Host smart-69f74bde-45cd-4a7f-ac80-cbdd3ffe7343
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39339
9141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_rx_crc_err.393399141
Directory /workspace/23.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/23.usbdev_setup_stage.1589415798
Short name T689
Test name
Test status
Simulation time 154028520 ps
CPU time 0.78 seconds
Started Jul 22 05:59:56 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206668 kb
Host smart-c3ef62c1-8588-4da5-9594-ea82e24e1848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15894
15798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_stage.1589415798
Directory /workspace/23.usbdev_setup_stage/latest

Test location /workspace/coverage/default/23.usbdev_setup_trans_ignored.3853072202
Short name T1017
Test name
Test status
Simulation time 147168419 ps
CPU time 0.78 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:10 PM PDT 24
Peak memory 206756 kb
Host smart-458c1965-af32-4593-9f9f-0bf4a44b2189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38530
72202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_setup_trans_ignored.3853072202
Directory /workspace/23.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/23.usbdev_smoke.1260015372
Short name T2667
Test name
Test status
Simulation time 221998601 ps
CPU time 0.92 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:00:24 PM PDT 24
Peak memory 206700 kb
Host smart-ff7bb96b-9bdc-490e-8dba-fa53f31baef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12600
15372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_smoke.1260015372
Directory /workspace/23.usbdev_smoke/latest

Test location /workspace/coverage/default/23.usbdev_spurious_pids_ignored.2847933324
Short name T2252
Test name
Test status
Simulation time 3263974116 ps
CPU time 28.99 seconds
Started Jul 22 06:00:03 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206876 kb
Host smart-d12a2092-bb70-4196-a027-23c7fb8abaf9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2847933324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_spurious_pids_ignored.2847933324
Directory /workspace/23.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/23.usbdev_stall_priority_over_nak.2553171609
Short name T1833
Test name
Test status
Simulation time 154494163 ps
CPU time 0.77 seconds
Started Jul 22 05:59:54 PM PDT 24
Finished Jul 22 05:59:56 PM PDT 24
Peak memory 206748 kb
Host smart-81efb1c6-5612-4ae5-86be-0aab89c5f3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25531
71609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_priority_over_nak.2553171609
Directory /workspace/23.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/23.usbdev_stall_trans.3973799754
Short name T316
Test name
Test status
Simulation time 201696286 ps
CPU time 0.81 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206748 kb
Host smart-fdb1c5ae-91a8-400c-b443-f04e886ced38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39737
99754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stall_trans.3973799754
Directory /workspace/23.usbdev_stall_trans/latest

Test location /workspace/coverage/default/23.usbdev_stream_len_max.1094555000
Short name T1332
Test name
Test status
Simulation time 659502325 ps
CPU time 1.62 seconds
Started Jul 22 05:59:55 PM PDT 24
Finished Jul 22 05:59:58 PM PDT 24
Peak memory 206660 kb
Host smart-561a47ff-8694-4fd0-aa05-dc6abf9c369c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10945
55000 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_stream_len_max.1094555000
Directory /workspace/23.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/23.usbdev_streaming_out.4141058882
Short name T2351
Test name
Test status
Simulation time 4687972931 ps
CPU time 42.36 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:57 PM PDT 24
Peak memory 206904 kb
Host smart-92020ca8-6149-4deb-9f85-b12e4d461caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41410
58882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.usbdev_streaming_out.4141058882
Directory /workspace/23.usbdev_streaming_out/latest

Test location /workspace/coverage/default/24.usbdev_alert_test.2387323333
Short name T1834
Test name
Test status
Simulation time 44725051 ps
CPU time 0.66 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206724 kb
Host smart-d5609e2d-58b3-4921-b2af-9b4c2196b0af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2387323333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_alert_test.2387323333
Directory /workspace/24.usbdev_alert_test/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_disconnect.1236704927
Short name T1644
Test name
Test status
Simulation time 3954401955 ps
CPU time 4.48 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206796 kb
Host smart-8314bfc4-c997-4e16-9338-1cef8fd0f8e9
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1236704927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_disconnect.1236704927
Directory /workspace/24.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_reset.1987877699
Short name T473
Test name
Test status
Simulation time 13328888034 ps
CPU time 11.98 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:22 PM PDT 24
Peak memory 206900 kb
Host smart-fd868a70-9a7f-4518-b0eb-8e418a3ca929
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1987877699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_reset.1987877699
Directory /workspace/24.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/24.usbdev_aon_wake_resume.3508254712
Short name T2054
Test name
Test status
Simulation time 23326339648 ps
CPU time 23.81 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:34 PM PDT 24
Peak memory 206740 kb
Host smart-f733bfab-b4eb-4b54-8944-95ed495d0615
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3508254712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_aon_wake_resume.3508254712
Directory /workspace/24.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/24.usbdev_av_buffer.3228080591
Short name T799
Test name
Test status
Simulation time 188821872 ps
CPU time 0.83 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:16 PM PDT 24
Peak memory 206744 kb
Host smart-77b2abca-6764-413b-8170-6579f6c1c00d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32280
80591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_av_buffer.3228080591
Directory /workspace/24.usbdev_av_buffer/latest

Test location /workspace/coverage/default/24.usbdev_bitstuff_err.3505353250
Short name T1627
Test name
Test status
Simulation time 163223956 ps
CPU time 0.75 seconds
Started Jul 22 06:00:34 PM PDT 24
Finished Jul 22 06:00:35 PM PDT 24
Peak memory 206748 kb
Host smart-fd6c458d-3648-4ebf-bbbf-c793ad0c665f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35053
53250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_bitstuff_err.3505353250
Directory /workspace/24.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_clear.2442791621
Short name T1958
Test name
Test status
Simulation time 365247058 ps
CPU time 1.18 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206724 kb
Host smart-c37aa487-92bf-4bf3-ab77-9031efde300f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24427
91621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_clear.2442791621
Directory /workspace/24.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/24.usbdev_data_toggle_restore.3451655940
Short name T1329
Test name
Test status
Simulation time 892980184 ps
CPU time 1.97 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:13 PM PDT 24
Peak memory 206832 kb
Host smart-e299343e-941a-4918-8fe6-406ce4bfadb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34516
55940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_data_toggle_restore.3451655940
Directory /workspace/24.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/24.usbdev_device_address.3405370414
Short name T2251
Test name
Test status
Simulation time 22877326224 ps
CPU time 47.73 seconds
Started Jul 22 06:00:11 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 206940 kb
Host smart-62514911-8232-42c8-ad11-4b1bd56fd641
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34053
70414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_device_address.3405370414
Directory /workspace/24.usbdev_device_address/latest

Test location /workspace/coverage/default/24.usbdev_disable_endpoint.740020003
Short name T475
Test name
Test status
Simulation time 352914436 ps
CPU time 1.2 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206736 kb
Host smart-2be1fe36-5ecc-473a-b4fa-ada063d9ba11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74002
0003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disable_endpoint.740020003
Directory /workspace/24.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/24.usbdev_disconnected.1584428993
Short name T1478
Test name
Test status
Simulation time 172376900 ps
CPU time 0.82 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:10 PM PDT 24
Peak memory 206764 kb
Host smart-5e4ec598-2dad-4888-9816-faf5cd0c7125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15844
28993 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_disconnected.1584428993
Directory /workspace/24.usbdev_disconnected/latest

Test location /workspace/coverage/default/24.usbdev_enable.1434623808
Short name T1557
Test name
Test status
Simulation time 40745979 ps
CPU time 0.67 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:14 PM PDT 24
Peak memory 206744 kb
Host smart-b6dbe105-8bb9-4f1c-9390-0bf4a1bf0a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14346
23808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_enable.1434623808
Directory /workspace/24.usbdev_enable/latest

Test location /workspace/coverage/default/24.usbdev_endpoint_access.2214094278
Short name T712
Test name
Test status
Simulation time 1072894740 ps
CPU time 2.14 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:13 PM PDT 24
Peak memory 206804 kb
Host smart-8cd42fc4-b7b1-400a-8787-731b343db4ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22140
94278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_endpoint_access.2214094278
Directory /workspace/24.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/24.usbdev_fifo_rst.1611579881
Short name T1170
Test name
Test status
Simulation time 369967753 ps
CPU time 2.26 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206812 kb
Host smart-8f600457-fe55-4ed1-8d23-d91e04a346ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16115
79881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_fifo_rst.1611579881
Directory /workspace/24.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/24.usbdev_in_iso.543168113
Short name T537
Test name
Test status
Simulation time 241206762 ps
CPU time 0.99 seconds
Started Jul 22 06:00:05 PM PDT 24
Finished Jul 22 06:00:07 PM PDT 24
Peak memory 206748 kb
Host smart-8783746e-e190-413a-bd78-a4f5e68d364f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54316
8113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_iso.543168113
Directory /workspace/24.usbdev_in_iso/latest

Test location /workspace/coverage/default/24.usbdev_in_stall.2914519882
Short name T834
Test name
Test status
Simulation time 224110125 ps
CPU time 0.86 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206732 kb
Host smart-bb5aebe6-3145-47d6-9c69-b3d35c2808ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29145
19882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_stall.2914519882
Directory /workspace/24.usbdev_in_stall/latest

Test location /workspace/coverage/default/24.usbdev_in_trans.2782857361
Short name T2743
Test name
Test status
Simulation time 243363516 ps
CPU time 0.95 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:17 PM PDT 24
Peak memory 206772 kb
Host smart-bb777b03-064a-4fd9-a86f-cee96467345f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27828
57361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_in_trans.2782857361
Directory /workspace/24.usbdev_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_invalid_sync.71992431
Short name T696
Test name
Test status
Simulation time 7036299679 ps
CPU time 189.68 seconds
Started Jul 22 06:00:11 PM PDT 24
Finished Jul 22 06:03:21 PM PDT 24
Peak memory 206880 kb
Host smart-22004fee-0482-4658-9cff-c816d5f858be
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=71992431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_invalid_sync.71992431
Directory /workspace/24.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/24.usbdev_link_in_err.462790124
Short name T355
Test name
Test status
Simulation time 198950918 ps
CPU time 0.83 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206732 kb
Host smart-d23931dd-912b-4297-8745-932ce4e49fcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46279
0124 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_in_err.462790124
Directory /workspace/24.usbdev_link_in_err/latest

Test location /workspace/coverage/default/24.usbdev_link_resume.1164524154
Short name T507
Test name
Test status
Simulation time 23368655705 ps
CPU time 26.41 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:41 PM PDT 24
Peak memory 206768 kb
Host smart-92bafda7-3e64-4ed7-b903-9c59629c7a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11645
24154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_resume.1164524154
Directory /workspace/24.usbdev_link_resume/latest

Test location /workspace/coverage/default/24.usbdev_link_suspend.3039325564
Short name T1306
Test name
Test status
Simulation time 3378283127 ps
CPU time 3.64 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206768 kb
Host smart-ae3d36cd-3d4c-43dc-9cfe-0a6159170490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30393
25564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_link_suspend.3039325564
Directory /workspace/24.usbdev_link_suspend/latest

Test location /workspace/coverage/default/24.usbdev_low_speed_traffic.2844387925
Short name T2137
Test name
Test status
Simulation time 11476257734 ps
CPU time 304.69 seconds
Started Jul 22 06:00:05 PM PDT 24
Finished Jul 22 06:05:10 PM PDT 24
Peak memory 206984 kb
Host smart-f1d8d299-084a-4c64-a365-37ebc51c0895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28443
87925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_low_speed_traffic.2844387925
Directory /workspace/24.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/24.usbdev_max_inter_pkt_delay.2238703109
Short name T1044
Test name
Test status
Simulation time 6981097308 ps
CPU time 62.14 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206956 kb
Host smart-d08e9df6-fd41-4dfb-ba6b-3f00bec17d6d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2238703109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_inter_pkt_delay.2238703109
Directory /workspace/24.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_max_length_in_transaction.1106773527
Short name T936
Test name
Test status
Simulation time 244791762 ps
CPU time 0.91 seconds
Started Jul 22 06:00:06 PM PDT 24
Finished Jul 22 06:00:07 PM PDT 24
Peak memory 206744 kb
Host smart-b99c78b2-6bbb-47bf-93af-f28d63b5f0fe
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1106773527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_in_transaction.1106773527
Directory /workspace/24.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_length_out_transaction.710091567
Short name T2407
Test name
Test status
Simulation time 212235913 ps
CPU time 0.87 seconds
Started Jul 22 06:00:10 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206748 kb
Host smart-6593509f-03b5-487b-97b1-8439f78ab153
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71009
1567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_length_out_transaction.710091567
Directory /workspace/24.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_max_usb_traffic.2617194115
Short name T509
Test name
Test status
Simulation time 4269455523 ps
CPU time 115.93 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:02:07 PM PDT 24
Peak memory 206896 kb
Host smart-01f71bcb-b405-46b6-b172-88dd39b6c279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26171
94115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_max_usb_traffic.2617194115
Directory /workspace/24.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/24.usbdev_min_inter_pkt_delay.984564974
Short name T630
Test name
Test status
Simulation time 7586351234 ps
CPU time 54.61 seconds
Started Jul 22 06:00:15 PM PDT 24
Finished Jul 22 06:01:11 PM PDT 24
Peak memory 207004 kb
Host smart-3d16e53e-6c36-4a50-9836-119e6e0adc89
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=984564974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_inter_pkt_delay.984564974
Directory /workspace/24.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/24.usbdev_min_length_in_transaction.4003271351
Short name T341
Test name
Test status
Simulation time 160295594 ps
CPU time 0.76 seconds
Started Jul 22 06:00:17 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206756 kb
Host smart-080169a4-1cd7-4b48-96be-c45d7c527c84
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4003271351 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_in_transaction.4003271351
Directory /workspace/24.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_min_length_out_transaction.2602645356
Short name T2321
Test name
Test status
Simulation time 140552489 ps
CPU time 0.77 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206708 kb
Host smart-451453c4-94a5-4a7e-bc96-bf0daa0ea008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26026
45356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_min_length_out_transaction.2602645356
Directory /workspace/24.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_nak_trans.3891081594
Short name T128
Test name
Test status
Simulation time 188416622 ps
CPU time 0.85 seconds
Started Jul 22 06:00:10 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206752 kb
Host smart-f80d1073-8b93-4db5-8547-91d2417bca58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38910
81594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_nak_trans.3891081594
Directory /workspace/24.usbdev_nak_trans/latest

Test location /workspace/coverage/default/24.usbdev_out_iso.2661671118
Short name T1797
Test name
Test status
Simulation time 220148864 ps
CPU time 0.87 seconds
Started Jul 22 06:00:10 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206748 kb
Host smart-585c0354-0cce-4aee-9828-16e8d2e12010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26616
71118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_iso.2661671118
Directory /workspace/24.usbdev_out_iso/latest

Test location /workspace/coverage/default/24.usbdev_out_stall.3886339793
Short name T2228
Test name
Test status
Simulation time 151263177 ps
CPU time 0.78 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:09 PM PDT 24
Peak memory 206760 kb
Host smart-4b2fbc6e-a83a-4aae-8614-0e3c68b4c95d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38863
39793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_stall.3886339793
Directory /workspace/24.usbdev_out_stall/latest

Test location /workspace/coverage/default/24.usbdev_out_trans_nak.1983925615
Short name T2074
Test name
Test status
Simulation time 154360073 ps
CPU time 0.75 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:08 PM PDT 24
Peak memory 206632 kb
Host smart-7a4fe420-e281-4d89-93e8-fa2a2e669960
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19839
25615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_out_trans_nak.1983925615
Directory /workspace/24.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/24.usbdev_pending_in_trans.2887973734
Short name T165
Test name
Test status
Simulation time 145588637 ps
CPU time 0.78 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206736 kb
Host smart-6d9b0643-0432-4a75-9fbe-0ba43c1aa84b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28879
73734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pending_in_trans.2887973734
Directory /workspace/24.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_pinflip.1157612283
Short name T2703
Test name
Test status
Simulation time 249709909 ps
CPU time 0.91 seconds
Started Jul 22 06:00:06 PM PDT 24
Finished Jul 22 06:00:08 PM PDT 24
Peak memory 206708 kb
Host smart-aeac1e63-817f-4f0f-89a7-8ec44dd0695c
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1157612283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_pinflip.1157612283
Directory /workspace/24.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/24.usbdev_phy_config_usb_ref_disable.214217704
Short name T1543
Test name
Test status
Simulation time 164452833 ps
CPU time 0.77 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206672 kb
Host smart-e8e900b6-bf4e-4d6e-9a11-c1589c9f5ac2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21421
7704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_config_usb_ref_disable.214217704
Directory /workspace/24.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/24.usbdev_phy_pins_sense.2237246342
Short name T1020
Test name
Test status
Simulation time 60249757 ps
CPU time 0.71 seconds
Started Jul 22 06:00:16 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206708 kb
Host smart-212d9db5-cb67-4f06-ab95-32f77ceebaab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22372
46342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_phy_pins_sense.2237246342
Directory /workspace/24.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/24.usbdev_pkt_buffer.3943150066
Short name T252
Test name
Test status
Simulation time 11393550533 ps
CPU time 24.56 seconds
Started Jul 22 06:00:47 PM PDT 24
Finished Jul 22 06:01:13 PM PDT 24
Peak memory 206916 kb
Host smart-24d48eeb-1d9a-4185-8395-926995b9c015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39431
50066 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_buffer.3943150066
Directory /workspace/24.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/24.usbdev_pkt_received.1239957356
Short name T544
Test name
Test status
Simulation time 173852961 ps
CPU time 0.87 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:10 PM PDT 24
Peak memory 206700 kb
Host smart-a8ca816f-7ecf-44df-8579-15b1e062f8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12399
57356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_received.1239957356
Directory /workspace/24.usbdev_pkt_received/latest

Test location /workspace/coverage/default/24.usbdev_pkt_sent.6783421
Short name T2145
Test name
Test status
Simulation time 238155461 ps
CPU time 0.92 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:11 PM PDT 24
Peak memory 206752 kb
Host smart-66f01003-d063-4e9c-9c91-8e5a37895667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67834
21 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_pkt_sent.6783421
Directory /workspace/24.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/24.usbdev_random_length_in_transaction.599783493
Short name T2515
Test name
Test status
Simulation time 220998916 ps
CPU time 0.91 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:10 PM PDT 24
Peak memory 206696 kb
Host smart-ec8f7886-a973-43d0-8a93-6040b97fe57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59978
3493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_in_transaction.599783493
Directory /workspace/24.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/24.usbdev_random_length_out_transaction.3562259884
Short name T1736
Test name
Test status
Simulation time 205910145 ps
CPU time 0.86 seconds
Started Jul 22 06:00:04 PM PDT 24
Finished Jul 22 06:00:05 PM PDT 24
Peak memory 206684 kb
Host smart-c7d31d2a-307f-4b9b-9493-87181e2473e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35622
59884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_random_length_out_transaction.3562259884
Directory /workspace/24.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/24.usbdev_rx_crc_err.1018539728
Short name T2197
Test name
Test status
Simulation time 136557970 ps
CPU time 0.74 seconds
Started Jul 22 06:00:04 PM PDT 24
Finished Jul 22 06:00:06 PM PDT 24
Peak memory 206740 kb
Host smart-da519ab7-c7fe-436b-aab5-df56bdb11ac7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10185
39728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_rx_crc_err.1018539728
Directory /workspace/24.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/24.usbdev_setup_stage.1198325864
Short name T2159
Test name
Test status
Simulation time 146262215 ps
CPU time 0.75 seconds
Started Jul 22 06:00:08 PM PDT 24
Finished Jul 22 06:00:10 PM PDT 24
Peak memory 206732 kb
Host smart-6ca7d81f-5fe2-413d-a5f9-8c3af6ef99b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11983
25864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_stage.1198325864
Directory /workspace/24.usbdev_setup_stage/latest

Test location /workspace/coverage/default/24.usbdev_setup_trans_ignored.2626789470
Short name T2726
Test name
Test status
Simulation time 152751029 ps
CPU time 0.81 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206736 kb
Host smart-9f4aba09-a345-4b9a-82fb-d9fb95b5c6f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26267
89470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_setup_trans_ignored.2626789470
Directory /workspace/24.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/24.usbdev_smoke.446268642
Short name T1015
Test name
Test status
Simulation time 246326348 ps
CPU time 0.93 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206728 kb
Host smart-9f24f1c2-452c-40bf-bf82-b1242e06ae53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44626
8642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_smoke.446268642
Directory /workspace/24.usbdev_smoke/latest

Test location /workspace/coverage/default/24.usbdev_spurious_pids_ignored.1735108311
Short name T1869
Test name
Test status
Simulation time 4571530632 ps
CPU time 32.22 seconds
Started Jul 22 06:00:07 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206892 kb
Host smart-da4595df-52b8-4572-9080-c1bd5ba6688a
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1735108311 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_spurious_pids_ignored.1735108311
Directory /workspace/24.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/24.usbdev_stall_priority_over_nak.1626205309
Short name T1974
Test name
Test status
Simulation time 200315571 ps
CPU time 0.83 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206764 kb
Host smart-30b86b75-f9b6-414e-8f17-751e57e6142a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16262
05309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_priority_over_nak.1626205309
Directory /workspace/24.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/24.usbdev_stall_trans.2409244692
Short name T1182
Test name
Test status
Simulation time 206608287 ps
CPU time 0.82 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206728 kb
Host smart-f458c083-204c-457f-bbfe-91b843000c61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24092
44692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stall_trans.2409244692
Directory /workspace/24.usbdev_stall_trans/latest

Test location /workspace/coverage/default/24.usbdev_stream_len_max.1143751921
Short name T1204
Test name
Test status
Simulation time 937516841 ps
CPU time 2.02 seconds
Started Jul 22 06:00:09 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206896 kb
Host smart-133fdb92-25c5-4f51-93aa-ef1e19bd0dda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11437
51921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_stream_len_max.1143751921
Directory /workspace/24.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/24.usbdev_streaming_out.892283965
Short name T1133
Test name
Test status
Simulation time 7270465521 ps
CPU time 71.73 seconds
Started Jul 22 06:00:03 PM PDT 24
Finished Jul 22 06:01:15 PM PDT 24
Peak memory 206960 kb
Host smart-382e5853-e982-4006-9644-fe7c2c7268dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89228
3965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.usbdev_streaming_out.892283965
Directory /workspace/24.usbdev_streaming_out/latest

Test location /workspace/coverage/default/25.usbdev_alert_test.1068063168
Short name T1630
Test name
Test status
Simulation time 48862109 ps
CPU time 0.69 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206736 kb
Host smart-a22f6885-6cac-44c7-a711-7829df58012d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1068063168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_alert_test.1068063168
Directory /workspace/25.usbdev_alert_test/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_disconnect.3774488285
Short name T496
Test name
Test status
Simulation time 4368587440 ps
CPU time 5.13 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:00:47 PM PDT 24
Peak memory 206796 kb
Host smart-6adbbe83-0f24-4fcd-97b1-0703cd596574
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3774488285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_disconnect.3774488285
Directory /workspace/25.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_reset.1621767089
Short name T16
Test name
Test status
Simulation time 13357995177 ps
CPU time 12.44 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206964 kb
Host smart-ad949fab-1907-427c-b5e3-526753269aa6
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1621767089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_reset.1621767089
Directory /workspace/25.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/25.usbdev_aon_wake_resume.2346877677
Short name T2019
Test name
Test status
Simulation time 23365596076 ps
CPU time 23.78 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206908 kb
Host smart-19aea5a2-0d99-45d2-ab45-d006d4b635ff
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2346877677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_aon_wake_resume.2346877677
Directory /workspace/25.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/25.usbdev_av_buffer.3681116372
Short name T1461
Test name
Test status
Simulation time 148342698 ps
CPU time 0.76 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206748 kb
Host smart-55bfefbf-1b72-4c78-9843-7a314da86031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36811
16372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_av_buffer.3681116372
Directory /workspace/25.usbdev_av_buffer/latest

Test location /workspace/coverage/default/25.usbdev_bitstuff_err.1458773648
Short name T2707
Test name
Test status
Simulation time 190806668 ps
CPU time 0.8 seconds
Started Jul 22 06:00:05 PM PDT 24
Finished Jul 22 06:00:06 PM PDT 24
Peak memory 206788 kb
Host smart-9ae7f99f-2cf9-4149-b9f5-10b4a72d5172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14587
73648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_bitstuff_err.1458773648
Directory /workspace/25.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_clear.2677219848
Short name T803
Test name
Test status
Simulation time 294789939 ps
CPU time 1.1 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:00:41 PM PDT 24
Peak memory 206712 kb
Host smart-117e7d05-2665-4169-9829-c75ebf1ddda8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26772
19848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_clear.2677219848
Directory /workspace/25.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/25.usbdev_data_toggle_restore.2593494634
Short name T2169
Test name
Test status
Simulation time 1489034683 ps
CPU time 3.06 seconds
Started Jul 22 06:00:40 PM PDT 24
Finished Jul 22 06:00:44 PM PDT 24
Peak memory 206880 kb
Host smart-6c484a48-e2af-492d-8991-48b3a98c72ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
94634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_data_toggle_restore.2593494634
Directory /workspace/25.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/25.usbdev_device_address.4084412723
Short name T1490
Test name
Test status
Simulation time 15643136247 ps
CPU time 32.32 seconds
Started Jul 22 06:00:05 PM PDT 24
Finished Jul 22 06:00:38 PM PDT 24
Peak memory 206916 kb
Host smart-5b4701c6-7f3c-46e6-b664-1fef0460b349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40844
12723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_device_address.4084412723
Directory /workspace/25.usbdev_device_address/latest

Test location /workspace/coverage/default/25.usbdev_disable_endpoint.4285264906
Short name T2635
Test name
Test status
Simulation time 412192067 ps
CPU time 1.23 seconds
Started Jul 22 06:00:17 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206668 kb
Host smart-b8cf1b19-61be-4a76-a190-26f8c056a87a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42852
64906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disable_endpoint.4285264906
Directory /workspace/25.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/25.usbdev_disconnected.3411896542
Short name T1479
Test name
Test status
Simulation time 133976936 ps
CPU time 0.76 seconds
Started Jul 22 06:00:11 PM PDT 24
Finished Jul 22 06:00:12 PM PDT 24
Peak memory 206748 kb
Host smart-5c0bd65b-4a08-413f-8098-f9263f581405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34118
96542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_disconnected.3411896542
Directory /workspace/25.usbdev_disconnected/latest

Test location /workspace/coverage/default/25.usbdev_enable.833421416
Short name T1820
Test name
Test status
Simulation time 31079378 ps
CPU time 0.64 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:17 PM PDT 24
Peak memory 206728 kb
Host smart-774c9197-5182-4dbc-9527-897beb9658e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83342
1416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_enable.833421416
Directory /workspace/25.usbdev_enable/latest

Test location /workspace/coverage/default/25.usbdev_endpoint_access.3314926966
Short name T2672
Test name
Test status
Simulation time 753591275 ps
CPU time 1.85 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:22 PM PDT 24
Peak memory 206896 kb
Host smart-60d0b221-3220-4a86-a8d5-aa9a4fc9288a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33149
26966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_endpoint_access.3314926966
Directory /workspace/25.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/25.usbdev_fifo_rst.3116979225
Short name T913
Test name
Test status
Simulation time 327896547 ps
CPU time 2.2 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:24 PM PDT 24
Peak memory 206792 kb
Host smart-d66fe678-c4d0-4f8b-884c-578fb7bc94ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31169
79225 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_fifo_rst.3116979225
Directory /workspace/25.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/25.usbdev_in_iso.348269721
Short name T823
Test name
Test status
Simulation time 172030068 ps
CPU time 0.83 seconds
Started Jul 22 06:00:16 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206744 kb
Host smart-8b58dbd5-fbbb-4c99-b186-dab45f93e7e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34826
9721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_iso.348269721
Directory /workspace/25.usbdev_in_iso/latest

Test location /workspace/coverage/default/25.usbdev_in_stall.776220603
Short name T2248
Test name
Test status
Simulation time 136303828 ps
CPU time 0.76 seconds
Started Jul 22 06:00:53 PM PDT 24
Finished Jul 22 06:00:54 PM PDT 24
Peak memory 206748 kb
Host smart-9d48b99e-1dd6-47b3-b0f9-b9b0e0cc305e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77622
0603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_stall.776220603
Directory /workspace/25.usbdev_in_stall/latest

Test location /workspace/coverage/default/25.usbdev_in_trans.2347121145
Short name T2466
Test name
Test status
Simulation time 220269097 ps
CPU time 0.95 seconds
Started Jul 22 06:00:11 PM PDT 24
Finished Jul 22 06:00:13 PM PDT 24
Peak memory 206748 kb
Host smart-f2693ee5-de4b-4389-ad2d-5204d17500c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23471
21145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_in_trans.2347121145
Directory /workspace/25.usbdev_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_iso_retraction.1037110828
Short name T2470
Test name
Test status
Simulation time 12471698722 ps
CPU time 100.25 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206892 kb
Host smart-2f7403c3-5e50-4528-8737-853b42cb3d86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10371
10828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_iso_retraction.1037110828
Directory /workspace/25.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/25.usbdev_link_in_err.1099306548
Short name T2713
Test name
Test status
Simulation time 214856132 ps
CPU time 0.92 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206756 kb
Host smart-38fd8d2f-de4c-4f96-b42d-5e2c238bf3d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10993
06548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_in_err.1099306548
Directory /workspace/25.usbdev_link_in_err/latest

Test location /workspace/coverage/default/25.usbdev_link_resume.232617013
Short name T1282
Test name
Test status
Simulation time 23363118904 ps
CPU time 24.04 seconds
Started Jul 22 06:00:17 PM PDT 24
Finished Jul 22 06:00:42 PM PDT 24
Peak memory 206780 kb
Host smart-d0ba7b18-13ad-49f3-b672-51118f8288bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23261
7013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_resume.232617013
Directory /workspace/25.usbdev_link_resume/latest

Test location /workspace/coverage/default/25.usbdev_link_suspend.1507968230
Short name T2148
Test name
Test status
Simulation time 3286977604 ps
CPU time 3.45 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:24 PM PDT 24
Peak memory 206788 kb
Host smart-6f392300-70e8-4a47-a9ca-2c726ecc98a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15079
68230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_link_suspend.1507968230
Directory /workspace/25.usbdev_link_suspend/latest

Test location /workspace/coverage/default/25.usbdev_low_speed_traffic.4044061791
Short name T1654
Test name
Test status
Simulation time 10480011890 ps
CPU time 299.36 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:05:28 PM PDT 24
Peak memory 206940 kb
Host smart-19ff22ed-af72-4cdb-876f-afae241b232d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
61791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_low_speed_traffic.4044061791
Directory /workspace/25.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/25.usbdev_max_inter_pkt_delay.88363057
Short name T1253
Test name
Test status
Simulation time 3087266475 ps
CPU time 82.2 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:01:45 PM PDT 24
Peak memory 206892 kb
Host smart-12136eaa-973f-4dc5-a090-0c34b4b0f32e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=88363057 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_inter_pkt_delay.88363057
Directory /workspace/25.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_max_length_in_transaction.4223907226
Short name T342
Test name
Test status
Simulation time 240874746 ps
CPU time 0.91 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:22 PM PDT 24
Peak memory 206744 kb
Host smart-67028e8f-0694-4000-a540-3619a1af9f23
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4223907226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_in_transaction.4223907226
Directory /workspace/25.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_length_out_transaction.1230775635
Short name T360
Test name
Test status
Simulation time 197897773 ps
CPU time 0.86 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:22 PM PDT 24
Peak memory 206748 kb
Host smart-2766d204-4a8f-4a9b-bd96-aa7533d29841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12307
75635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_length_out_transaction.1230775635
Directory /workspace/25.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_max_usb_traffic.2668446775
Short name T1635
Test name
Test status
Simulation time 3813071949 ps
CPU time 104.88 seconds
Started Jul 22 06:00:19 PM PDT 24
Finished Jul 22 06:02:04 PM PDT 24
Peak memory 206952 kb
Host smart-2368491b-8b64-4669-896b-e2693d756f9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26684
46775 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_max_usb_traffic.2668446775
Directory /workspace/25.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/25.usbdev_min_inter_pkt_delay.1627176334
Short name T1162
Test name
Test status
Simulation time 5401732907 ps
CPU time 152.66 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206828 kb
Host smart-e8994ce8-0098-4a7a-b2a4-8fd80bb84f11
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1627176334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_inter_pkt_delay.1627176334
Directory /workspace/25.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/25.usbdev_min_length_in_transaction.2823709701
Short name T1256
Test name
Test status
Simulation time 149005187 ps
CPU time 0.75 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:14 PM PDT 24
Peak memory 206668 kb
Host smart-11992b10-8b55-40a5-9c9a-51776cb2eddb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2823709701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_in_transaction.2823709701
Directory /workspace/25.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_min_length_out_transaction.4241602966
Short name T1113
Test name
Test status
Simulation time 160255206 ps
CPU time 0.8 seconds
Started Jul 22 06:00:16 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206796 kb
Host smart-564a9f5f-83ef-4f30-bddd-74ffb39a9862
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42416
02966 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_min_length_out_transaction.4241602966
Directory /workspace/25.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_nak_trans.2823240590
Short name T1979
Test name
Test status
Simulation time 212855726 ps
CPU time 0.89 seconds
Started Jul 22 06:00:33 PM PDT 24
Finished Jul 22 06:00:35 PM PDT 24
Peak memory 206744 kb
Host smart-22f9c90c-0734-4ddb-8344-10d2239cf2a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28232
40590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_nak_trans.2823240590
Directory /workspace/25.usbdev_nak_trans/latest

Test location /workspace/coverage/default/25.usbdev_out_iso.1597205483
Short name T1424
Test name
Test status
Simulation time 183759509 ps
CPU time 0.87 seconds
Started Jul 22 06:00:15 PM PDT 24
Finished Jul 22 06:00:17 PM PDT 24
Peak memory 206744 kb
Host smart-9cd53dc4-da5f-4d1c-829a-63479c02687c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15972
05483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_iso.1597205483
Directory /workspace/25.usbdev_out_iso/latest

Test location /workspace/coverage/default/25.usbdev_out_stall.390040193
Short name T74
Test name
Test status
Simulation time 183318193 ps
CPU time 0.79 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:16 PM PDT 24
Peak memory 206740 kb
Host smart-cb2c423b-38e0-4eca-a123-3484e1f8d2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39004
0193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_stall.390040193
Directory /workspace/25.usbdev_out_stall/latest

Test location /workspace/coverage/default/25.usbdev_out_trans_nak.3908035084
Short name T1860
Test name
Test status
Simulation time 181831384 ps
CPU time 0.77 seconds
Started Jul 22 06:00:16 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206772 kb
Host smart-633bcaaf-4c5e-4a8f-9fb9-7beecbff42bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39080
35084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_out_trans_nak.3908035084
Directory /workspace/25.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/25.usbdev_pending_in_trans.3728549700
Short name T1928
Test name
Test status
Simulation time 155544781 ps
CPU time 0.83 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:14 PM PDT 24
Peak memory 206884 kb
Host smart-c111737a-2377-42c1-9de0-10ff9e773fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37285
49700 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pending_in_trans.3728549700
Directory /workspace/25.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_pinflip.2259214162
Short name T1596
Test name
Test status
Simulation time 206852939 ps
CPU time 0.92 seconds
Started Jul 22 06:00:15 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206748 kb
Host smart-41240ebe-43ec-42f9-8f26-5140621d70b1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2259214162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_pinflip.2259214162
Directory /workspace/25.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/25.usbdev_phy_config_usb_ref_disable.1815317978
Short name T1991
Test name
Test status
Simulation time 159873708 ps
CPU time 0.79 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:00:29 PM PDT 24
Peak memory 206720 kb
Host smart-1c62bae5-e856-440c-b9bf-cc96d362a14d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18153
17978 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_config_usb_ref_disable.1815317978
Directory /workspace/25.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/25.usbdev_phy_pins_sense.4205016815
Short name T2629
Test name
Test status
Simulation time 69885625 ps
CPU time 0.7 seconds
Started Jul 22 06:00:16 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206744 kb
Host smart-562858d5-04ba-4cf1-aefe-230f41644d3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42050
16815 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_phy_pins_sense.4205016815
Directory /workspace/25.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/25.usbdev_pkt_buffer.1247935640
Short name T247
Test name
Test status
Simulation time 12990091471 ps
CPU time 28.93 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:42 PM PDT 24
Peak memory 206868 kb
Host smart-26bc4d72-abc1-4c9a-9558-303610d0c057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12479
35640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_buffer.1247935640
Directory /workspace/25.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/25.usbdev_pkt_received.133339851
Short name T2704
Test name
Test status
Simulation time 220825016 ps
CPU time 0.88 seconds
Started Jul 22 06:00:19 PM PDT 24
Finished Jul 22 06:00:21 PM PDT 24
Peak memory 206772 kb
Host smart-81811849-cf55-494c-a572-4f31c845c51e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13333
9851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_received.133339851
Directory /workspace/25.usbdev_pkt_received/latest

Test location /workspace/coverage/default/25.usbdev_pkt_sent.634101693
Short name T807
Test name
Test status
Simulation time 238357130 ps
CPU time 0.92 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:00:24 PM PDT 24
Peak memory 206748 kb
Host smart-17933f50-23a5-48bd-8972-f54fb11f3e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63410
1693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_pkt_sent.634101693
Directory /workspace/25.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/25.usbdev_random_length_in_transaction.3613875802
Short name T2161
Test name
Test status
Simulation time 190447464 ps
CPU time 0.84 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:14 PM PDT 24
Peak memory 206744 kb
Host smart-7f3c35de-e02a-495d-8275-9abbd10aa0d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36138
75802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_in_transaction.3613875802
Directory /workspace/25.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/25.usbdev_random_length_out_transaction.2680608062
Short name T674
Test name
Test status
Simulation time 209070813 ps
CPU time 0.92 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:16 PM PDT 24
Peak memory 206736 kb
Host smart-9765affc-27bd-438a-a4ce-c2efc542f68a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26806
08062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_random_length_out_transaction.2680608062
Directory /workspace/25.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/25.usbdev_rx_crc_err.3976920991
Short name T1972
Test name
Test status
Simulation time 144562937 ps
CPU time 0.74 seconds
Started Jul 22 06:00:15 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206744 kb
Host smart-88607995-a66c-4d71-a95d-6830b2d8080a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39769
20991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_rx_crc_err.3976920991
Directory /workspace/25.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/25.usbdev_setup_stage.2109531239
Short name T2460
Test name
Test status
Simulation time 165955682 ps
CPU time 0.79 seconds
Started Jul 22 06:00:32 PM PDT 24
Finished Jul 22 06:00:34 PM PDT 24
Peak memory 206696 kb
Host smart-ce4b43b2-7103-4ee6-b23f-4cd8fddfabe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21095
31239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_stage.2109531239
Directory /workspace/25.usbdev_setup_stage/latest

Test location /workspace/coverage/default/25.usbdev_setup_trans_ignored.203317079
Short name T1131
Test name
Test status
Simulation time 151009010 ps
CPU time 0.79 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:14 PM PDT 24
Peak memory 206724 kb
Host smart-79ff6efa-b128-4546-a469-f6e8673bd1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20331
7079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_setup_trans_ignored.203317079
Directory /workspace/25.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/25.usbdev_smoke.1084138255
Short name T958
Test name
Test status
Simulation time 208975286 ps
CPU time 0.94 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206732 kb
Host smart-b05607a2-2328-4229-90f2-208eb1c385e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10841
38255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_smoke.1084138255
Directory /workspace/25.usbdev_smoke/latest

Test location /workspace/coverage/default/25.usbdev_spurious_pids_ignored.2829316415
Short name T1856
Test name
Test status
Simulation time 3142791467 ps
CPU time 78.18 seconds
Started Jul 22 06:01:08 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206856 kb
Host smart-8796cac9-5148-44c4-91f9-bca9607dd932
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2829316415 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_spurious_pids_ignored.2829316415
Directory /workspace/25.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/25.usbdev_stall_priority_over_nak.1603198239
Short name T2438
Test name
Test status
Simulation time 187895406 ps
CPU time 0.83 seconds
Started Jul 22 06:01:08 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206720 kb
Host smart-bbcf7044-6dec-4353-a78a-a9f4ceec58d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16031
98239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_priority_over_nak.1603198239
Directory /workspace/25.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/25.usbdev_stall_trans.2869955269
Short name T1298
Test name
Test status
Simulation time 170201983 ps
CPU time 0.87 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:15 PM PDT 24
Peak memory 206736 kb
Host smart-3ca5d7dc-66d3-4217-a65d-705772342303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28699
55269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stall_trans.2869955269
Directory /workspace/25.usbdev_stall_trans/latest

Test location /workspace/coverage/default/25.usbdev_stream_len_max.3204105159
Short name T592
Test name
Test status
Simulation time 647615481 ps
CPU time 1.59 seconds
Started Jul 22 06:00:34 PM PDT 24
Finished Jul 22 06:00:36 PM PDT 24
Peak memory 206728 kb
Host smart-3fded1b8-10e6-4bbf-ad1e-97dc0669d06d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32041
05159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_stream_len_max.3204105159
Directory /workspace/25.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/25.usbdev_streaming_out.2697685022
Short name T2052
Test name
Test status
Simulation time 7715227643 ps
CPU time 74.89 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:01:29 PM PDT 24
Peak memory 206852 kb
Host smart-8d799a56-7042-4113-a081-33df1bca61d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26976
85022 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.usbdev_streaming_out.2697685022
Directory /workspace/25.usbdev_streaming_out/latest

Test location /workspace/coverage/default/26.usbdev_alert_test.2990851693
Short name T784
Test name
Test status
Simulation time 38060027 ps
CPU time 0.71 seconds
Started Jul 22 06:00:27 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206700 kb
Host smart-1b175980-c32c-479e-977f-0a4ec0648cd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2990851693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_alert_test.2990851693
Directory /workspace/26.usbdev_alert_test/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_disconnect.2333346332
Short name T2199
Test name
Test status
Simulation time 3587123649 ps
CPU time 5 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206860 kb
Host smart-4572d77f-96e0-4b57-859e-5a4f32d4e47a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2333346332 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_disconnect.2333346332
Directory /workspace/26.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_reset.1321556010
Short name T2413
Test name
Test status
Simulation time 13342676336 ps
CPU time 11.95 seconds
Started Jul 22 06:00:13 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206968 kb
Host smart-4b62edde-dc8f-4ce9-a163-70ac4a4a1de7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1321556010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_reset.1321556010
Directory /workspace/26.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/26.usbdev_aon_wake_resume.1298242238
Short name T743
Test name
Test status
Simulation time 23339969344 ps
CPU time 25.04 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:00:52 PM PDT 24
Peak memory 206908 kb
Host smart-4f7094c2-cd71-4ecc-aa8b-dd7889636485
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1298242238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_aon_wake_resume.1298242238
Directory /workspace/26.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/26.usbdev_av_buffer.1544437106
Short name T875
Test name
Test status
Simulation time 154753197 ps
CPU time 0.76 seconds
Started Jul 22 06:00:15 PM PDT 24
Finished Jul 22 06:00:17 PM PDT 24
Peak memory 206708 kb
Host smart-98c27b72-5c20-4b10-921e-e3b68a8a576d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15444
37106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_av_buffer.1544437106
Directory /workspace/26.usbdev_av_buffer/latest

Test location /workspace/coverage/default/26.usbdev_bitstuff_err.131318086
Short name T2061
Test name
Test status
Simulation time 143619308 ps
CPU time 0.78 seconds
Started Jul 22 06:00:17 PM PDT 24
Finished Jul 22 06:00:19 PM PDT 24
Peak memory 206748 kb
Host smart-8c48e5f3-2138-46c1-9117-eb85b518d817
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13131
8086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_bitstuff_err.131318086
Directory /workspace/26.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_clear.3371008330
Short name T2684
Test name
Test status
Simulation time 290185040 ps
CPU time 1.12 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206744 kb
Host smart-d69e8137-ecbf-4d45-a1fb-2ff579334548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33710
08330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_clear.3371008330
Directory /workspace/26.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/26.usbdev_data_toggle_restore.3996022656
Short name T651
Test name
Test status
Simulation time 567999445 ps
CPU time 1.41 seconds
Started Jul 22 06:00:14 PM PDT 24
Finished Jul 22 06:00:17 PM PDT 24
Peak memory 206708 kb
Host smart-40d372f8-57cd-45c9-9017-30bccd845ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39960
22656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_data_toggle_restore.3996022656
Directory /workspace/26.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/26.usbdev_device_address.2600733869
Short name T1848
Test name
Test status
Simulation time 22740889414 ps
CPU time 45.26 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:01:13 PM PDT 24
Peak memory 206860 kb
Host smart-6acd9b78-f3eb-40ec-9a61-3f74b62a2329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26007
33869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_device_address.2600733869
Directory /workspace/26.usbdev_device_address/latest

Test location /workspace/coverage/default/26.usbdev_disable_endpoint.1475976614
Short name T2541
Test name
Test status
Simulation time 343062407 ps
CPU time 1.14 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206752 kb
Host smart-2fb4828c-ba22-447e-8351-64790357bb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14759
76614 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disable_endpoint.1475976614
Directory /workspace/26.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/26.usbdev_disconnected.3552251266
Short name T796
Test name
Test status
Simulation time 174095851 ps
CPU time 0.78 seconds
Started Jul 22 06:00:16 PM PDT 24
Finished Jul 22 06:00:18 PM PDT 24
Peak memory 206748 kb
Host smart-9c706705-9b41-4ef3-b77d-6025b552a4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35522
51266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_disconnected.3552251266
Directory /workspace/26.usbdev_disconnected/latest

Test location /workspace/coverage/default/26.usbdev_enable.1507926408
Short name T857
Test name
Test status
Simulation time 60275227 ps
CPU time 0.66 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206744 kb
Host smart-6f2ba775-8557-4528-b46b-2043e6fb28a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15079
26408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_enable.1507926408
Directory /workspace/26.usbdev_enable/latest

Test location /workspace/coverage/default/26.usbdev_endpoint_access.3300670825
Short name T1657
Test name
Test status
Simulation time 996637764 ps
CPU time 2.53 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206916 kb
Host smart-f651ff6a-02c0-449f-81ba-3c45d9706a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33006
70825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_endpoint_access.3300670825
Directory /workspace/26.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/26.usbdev_fifo_rst.2894941388
Short name T746
Test name
Test status
Simulation time 228971412 ps
CPU time 2.27 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:00:16 PM PDT 24
Peak memory 206924 kb
Host smart-30607bd6-34f5-4e62-933f-998f6b23e8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28949
41388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_fifo_rst.2894941388
Directory /workspace/26.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/26.usbdev_in_iso.3473673509
Short name T2255
Test name
Test status
Simulation time 189465947 ps
CPU time 0.8 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206740 kb
Host smart-2f389ba6-2380-4c20-a308-43ebb567f5f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34736
73509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_iso.3473673509
Directory /workspace/26.usbdev_in_iso/latest

Test location /workspace/coverage/default/26.usbdev_in_stall.1242097015
Short name T467
Test name
Test status
Simulation time 144468657 ps
CPU time 0.74 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206740 kb
Host smart-3de02f38-b3fe-4e1c-a031-36a79d176f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12420
97015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_stall.1242097015
Directory /workspace/26.usbdev_in_stall/latest

Test location /workspace/coverage/default/26.usbdev_in_trans.2934679853
Short name T484
Test name
Test status
Simulation time 163007327 ps
CPU time 0.79 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206740 kb
Host smart-141581ba-2dde-4677-894d-f831b83016b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29346
79853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_in_trans.2934679853
Directory /workspace/26.usbdev_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_invalid_sync.2067980551
Short name T1923
Test name
Test status
Simulation time 8923493728 ps
CPU time 80.57 seconds
Started Jul 22 06:00:12 PM PDT 24
Finished Jul 22 06:01:34 PM PDT 24
Peak memory 206884 kb
Host smart-a406bad7-76ee-4c19-8616-b39c8dbfca14
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2067980551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_invalid_sync.2067980551
Directory /workspace/26.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/26.usbdev_link_in_err.3363300900
Short name T329
Test name
Test status
Simulation time 213280313 ps
CPU time 0.89 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206748 kb
Host smart-87ca7cef-e136-4c2b-8556-482c5c8bf6e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33633
00900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_in_err.3363300900
Directory /workspace/26.usbdev_link_in_err/latest

Test location /workspace/coverage/default/26.usbdev_link_resume.15762577
Short name T2619
Test name
Test status
Simulation time 23375515152 ps
CPU time 22.9 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:55 PM PDT 24
Peak memory 206748 kb
Host smart-cf3d1b1a-2f50-46ca-8d57-da5485409e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15762
577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_resume.15762577
Directory /workspace/26.usbdev_link_resume/latest

Test location /workspace/coverage/default/26.usbdev_link_suspend.2996742425
Short name T898
Test name
Test status
Simulation time 3327785016 ps
CPU time 4.02 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:35 PM PDT 24
Peak memory 206788 kb
Host smart-7531e824-2aef-4a21-acc1-0fc62a87e525
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29967
42425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_link_suspend.2996742425
Directory /workspace/26.usbdev_link_suspend/latest

Test location /workspace/coverage/default/26.usbdev_low_speed_traffic.1788041900
Short name T153
Test name
Test status
Simulation time 11940914014 ps
CPU time 110.89 seconds
Started Jul 22 06:01:11 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206960 kb
Host smart-122abcdc-0078-4282-9974-8ac492663d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17880
41900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_low_speed_traffic.1788041900
Directory /workspace/26.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/26.usbdev_max_inter_pkt_delay.3578412772
Short name T1511
Test name
Test status
Simulation time 4372540695 ps
CPU time 123.05 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:02:26 PM PDT 24
Peak memory 206956 kb
Host smart-46a734b2-0d8b-415a-9e66-88b33edf270c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3578412772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_inter_pkt_delay.3578412772
Directory /workspace/26.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_max_length_in_transaction.306662977
Short name T2352
Test name
Test status
Simulation time 291192335 ps
CPU time 0.88 seconds
Started Jul 22 06:00:19 PM PDT 24
Finished Jul 22 06:00:20 PM PDT 24
Peak memory 206740 kb
Host smart-66e5874d-7115-48c7-b10e-4041eaf6820b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=306662977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_in_transaction.306662977
Directory /workspace/26.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_length_out_transaction.1368468871
Short name T85
Test name
Test status
Simulation time 201247430 ps
CPU time 0.87 seconds
Started Jul 22 06:00:19 PM PDT 24
Finished Jul 22 06:00:21 PM PDT 24
Peak memory 206752 kb
Host smart-33641da9-116f-4c57-9dca-cc93872dee02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13684
68871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_length_out_transaction.1368468871
Directory /workspace/26.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_max_usb_traffic.2940998520
Short name T2234
Test name
Test status
Simulation time 5744857290 ps
CPU time 53.78 seconds
Started Jul 22 06:00:20 PM PDT 24
Finished Jul 22 06:01:15 PM PDT 24
Peak memory 206848 kb
Host smart-a3072e64-53e9-4a51-95de-945db70e5a0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29409
98520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_max_usb_traffic.2940998520
Directory /workspace/26.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/26.usbdev_min_inter_pkt_delay.2689331975
Short name T842
Test name
Test status
Simulation time 4786478257 ps
CPU time 45.34 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206856 kb
Host smart-9aa49bf5-3157-420e-87dd-9f9014a6faaf
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2689331975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_inter_pkt_delay.2689331975
Directory /workspace/26.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/26.usbdev_min_length_in_transaction.892342556
Short name T465
Test name
Test status
Simulation time 160313854 ps
CPU time 0.84 seconds
Started Jul 22 06:00:38 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206504 kb
Host smart-9f7cef12-07b8-43e9-a9a1-2cff03898712
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=892342556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_in_transaction.892342556
Directory /workspace/26.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_min_length_out_transaction.3972117102
Short name T2606
Test name
Test status
Simulation time 185054860 ps
CPU time 0.79 seconds
Started Jul 22 06:00:21 PM PDT 24
Finished Jul 22 06:00:23 PM PDT 24
Peak memory 206744 kb
Host smart-819c43e5-1a29-4ee9-8faf-6239c5cf404c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39721
17102 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_min_length_out_transaction.3972117102
Directory /workspace/26.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_out_iso.1889759207
Short name T813
Test name
Test status
Simulation time 183305636 ps
CPU time 0.83 seconds
Started Jul 22 06:00:27 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206704 kb
Host smart-d4e271ca-ab12-4c88-8107-a1d5ea4df9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18897
59207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_iso.1889759207
Directory /workspace/26.usbdev_out_iso/latest

Test location /workspace/coverage/default/26.usbdev_out_stall.3952531624
Short name T367
Test name
Test status
Simulation time 190368176 ps
CPU time 0.83 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:27 PM PDT 24
Peak memory 206736 kb
Host smart-b8c2b635-6e89-4eb1-8961-f1165974c321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39525
31624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_stall.3952531624
Directory /workspace/26.usbdev_out_stall/latest

Test location /workspace/coverage/default/26.usbdev_out_trans_nak.1485913485
Short name T2600
Test name
Test status
Simulation time 183247503 ps
CPU time 0.82 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:00:27 PM PDT 24
Peak memory 206708 kb
Host smart-b94dd9ca-46e4-418e-9028-f732dbdb2823
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14859
13485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_out_trans_nak.1485913485
Directory /workspace/26.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/26.usbdev_pending_in_trans.83826283
Short name T171
Test name
Test status
Simulation time 151545535 ps
CPU time 0.79 seconds
Started Jul 22 06:00:19 PM PDT 24
Finished Jul 22 06:00:21 PM PDT 24
Peak memory 206736 kb
Host smart-22ea07cb-4cd6-4a91-bfc6-9f6402a66406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83826
283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pending_in_trans.83826283
Directory /workspace/26.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_pinflip.406479844
Short name T805
Test name
Test status
Simulation time 282809632 ps
CPU time 1 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206704 kb
Host smart-c6faeb16-46c8-4468-8ce0-59e4fc750a78
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=406479844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_pinflip.406479844
Directory /workspace/26.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/26.usbdev_phy_config_usb_ref_disable.2809763287
Short name T188
Test name
Test status
Simulation time 144566822 ps
CPU time 0.75 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206744 kb
Host smart-9ab69534-0632-4d1d-b6dd-31111e919cf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28097
63287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_config_usb_ref_disable.2809763287
Directory /workspace/26.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/26.usbdev_phy_pins_sense.3212744698
Short name T1788
Test name
Test status
Simulation time 43575607 ps
CPU time 0.68 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206644 kb
Host smart-484efe35-25aa-4eb8-baf0-c868d0a5b4a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32127
44698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_phy_pins_sense.3212744698
Directory /workspace/26.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/26.usbdev_pkt_buffer.3686666877
Short name T277
Test name
Test status
Simulation time 7619892441 ps
CPU time 19.34 seconds
Started Jul 22 06:00:21 PM PDT 24
Finished Jul 22 06:00:42 PM PDT 24
Peak memory 215036 kb
Host smart-50ed91b4-0702-4534-8380-9ef51c64707e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36866
66877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_buffer.3686666877
Directory /workspace/26.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/26.usbdev_pkt_received.214034741
Short name T470
Test name
Test status
Simulation time 224484829 ps
CPU time 0.85 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206744 kb
Host smart-accffb38-457a-4cea-b22c-6f8287751759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21403
4741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_received.214034741
Directory /workspace/26.usbdev_pkt_received/latest

Test location /workspace/coverage/default/26.usbdev_pkt_sent.3790198583
Short name T1322
Test name
Test status
Simulation time 180623511 ps
CPU time 0.82 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206700 kb
Host smart-b5d6ee43-6475-4503-acc4-dfae065ca473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37901
98583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_pkt_sent.3790198583
Directory /workspace/26.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/26.usbdev_random_length_in_transaction.2746189925
Short name T2577
Test name
Test status
Simulation time 199360184 ps
CPU time 0.87 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206752 kb
Host smart-9a75ff5e-f0e2-4333-a564-b3e03dcf363a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27461
89925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_in_transaction.2746189925
Directory /workspace/26.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/26.usbdev_random_length_out_transaction.3009115969
Short name T905
Test name
Test status
Simulation time 144314196 ps
CPU time 0.82 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:00:25 PM PDT 24
Peak memory 206736 kb
Host smart-eab063d0-740f-4d93-a6ae-5c71f25a8bba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30091
15969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_random_length_out_transaction.3009115969
Directory /workspace/26.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/26.usbdev_rx_crc_err.2863129184
Short name T2602
Test name
Test status
Simulation time 149593995 ps
CPU time 0.76 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206732 kb
Host smart-096e06c9-3b81-475c-adcf-da10634b9c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28631
29184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_rx_crc_err.2863129184
Directory /workspace/26.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/26.usbdev_setup_stage.2051503005
Short name T2346
Test name
Test status
Simulation time 160943860 ps
CPU time 0.78 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206708 kb
Host smart-6fb64473-81e5-4966-a5fa-dd3a0d18ef3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20515
03005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_stage.2051503005
Directory /workspace/26.usbdev_setup_stage/latest

Test location /workspace/coverage/default/26.usbdev_setup_trans_ignored.1772892750
Short name T1936
Test name
Test status
Simulation time 156510976 ps
CPU time 0.77 seconds
Started Jul 22 06:00:27 PM PDT 24
Finished Jul 22 06:00:29 PM PDT 24
Peak memory 206752 kb
Host smart-0044bac4-39ab-4107-84cc-08782df34dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17728
92750 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_setup_trans_ignored.1772892750
Directory /workspace/26.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/26.usbdev_smoke.3743225010
Short name T844
Test name
Test status
Simulation time 219264208 ps
CPU time 0.93 seconds
Started Jul 22 06:00:21 PM PDT 24
Finished Jul 22 06:00:23 PM PDT 24
Peak memory 206652 kb
Host smart-f2b65988-4603-4965-8d23-d0ce4ac686cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37432
25010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_smoke.3743225010
Directory /workspace/26.usbdev_smoke/latest

Test location /workspace/coverage/default/26.usbdev_spurious_pids_ignored.4137595940
Short name T392
Test name
Test status
Simulation time 3888278573 ps
CPU time 27.49 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:00:51 PM PDT 24
Peak memory 206944 kb
Host smart-e12e706d-61e5-4f4b-8293-50d97f6f5ee9
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4137595940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_spurious_pids_ignored.4137595940
Directory /workspace/26.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/26.usbdev_stall_priority_over_nak.1115797109
Short name T2462
Test name
Test status
Simulation time 185537362 ps
CPU time 0.84 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206700 kb
Host smart-c0ba6b7e-002a-43e6-b488-a43c8b7218d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11157
97109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_priority_over_nak.1115797109
Directory /workspace/26.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/26.usbdev_stall_trans.2429024844
Short name T1532
Test name
Test status
Simulation time 168110235 ps
CPU time 0.82 seconds
Started Jul 22 06:01:47 PM PDT 24
Finished Jul 22 06:01:48 PM PDT 24
Peak memory 206748 kb
Host smart-9429e265-47bd-448d-84a5-8d4c85469b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24290
24844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stall_trans.2429024844
Directory /workspace/26.usbdev_stall_trans/latest

Test location /workspace/coverage/default/26.usbdev_stream_len_max.3845709538
Short name T446
Test name
Test status
Simulation time 297116605 ps
CPU time 0.96 seconds
Started Jul 22 06:00:23 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206688 kb
Host smart-b9f64595-5ca1-43e0-b728-7c5ef8934757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38457
09538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_stream_len_max.3845709538
Directory /workspace/26.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/26.usbdev_streaming_out.3204845813
Short name T2694
Test name
Test status
Simulation time 4334047854 ps
CPU time 37.56 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206816 kb
Host smart-f362ffb9-79eb-477a-b5bc-3c6fa6508bdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32048
45813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.usbdev_streaming_out.3204845813
Directory /workspace/26.usbdev_streaming_out/latest

Test location /workspace/coverage/default/27.usbdev_alert_test.3989313088
Short name T871
Test name
Test status
Simulation time 49129986 ps
CPU time 0.71 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206712 kb
Host smart-a8165876-c42e-4806-ba1b-1746643fbaa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3989313088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_alert_test.3989313088
Directory /workspace/27.usbdev_alert_test/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_disconnect.4262212083
Short name T210
Test name
Test status
Simulation time 4215699603 ps
CPU time 5.29 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:00:34 PM PDT 24
Peak memory 206896 kb
Host smart-0eec4cef-d782-4900-ba28-12ed84a02a9f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4262212083 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_disconnect.4262212083
Directory /workspace/27.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_reset.2443528693
Short name T1540
Test name
Test status
Simulation time 13400727559 ps
CPU time 11.96 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:44 PM PDT 24
Peak memory 206912 kb
Host smart-38113403-a35b-4ba7-9d9f-27995888b48f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2443528693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_reset.2443528693
Directory /workspace/27.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/27.usbdev_aon_wake_resume.3067803975
Short name T1623
Test name
Test status
Simulation time 23412092274 ps
CPU time 23.81 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:54 PM PDT 24
Peak memory 206800 kb
Host smart-4ab07ed2-d0a7-4ab9-9a28-84253b5b2e30
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3067803975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_aon_wake_resume.3067803975
Directory /workspace/27.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/27.usbdev_av_buffer.2527674907
Short name T1052
Test name
Test status
Simulation time 157877965 ps
CPU time 0.81 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206744 kb
Host smart-9b5da930-1c4d-418b-897f-0e85e493c1aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25276
74907 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_av_buffer.2527674907
Directory /workspace/27.usbdev_av_buffer/latest

Test location /workspace/coverage/default/27.usbdev_bitstuff_err.2763197879
Short name T2188
Test name
Test status
Simulation time 143293276 ps
CPU time 0.78 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206748 kb
Host smart-856e09f8-6529-4f9c-b8c7-c2e9bb65fc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27631
97879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_bitstuff_err.2763197879
Directory /workspace/27.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_clear.2074764418
Short name T37
Test name
Test status
Simulation time 253106318 ps
CPU time 0.92 seconds
Started Jul 22 06:00:25 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206748 kb
Host smart-3a6eba86-2490-4ea5-8166-826f176c60a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20747
64418 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_clear.2074764418
Directory /workspace/27.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/27.usbdev_data_toggle_restore.2565057352
Short name T779
Test name
Test status
Simulation time 1097756223 ps
CPU time 2.75 seconds
Started Jul 22 06:00:22 PM PDT 24
Finished Jul 22 06:00:26 PM PDT 24
Peak memory 206896 kb
Host smart-a79398be-5297-426a-8110-43f19b1cfe44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
57352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_data_toggle_restore.2565057352
Directory /workspace/27.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/27.usbdev_device_address.1078167741
Short name T164
Test name
Test status
Simulation time 17074549676 ps
CPU time 33.2 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206944 kb
Host smart-8a767eec-58e6-4fc2-9c2b-ff829aeb7ec5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10781
67741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_device_address.1078167741
Directory /workspace/27.usbdev_device_address/latest

Test location /workspace/coverage/default/27.usbdev_disable_endpoint.937067249
Short name T1968
Test name
Test status
Simulation time 470216548 ps
CPU time 1.42 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206752 kb
Host smart-07cb02b9-5039-49e8-9768-fbe31f710b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93706
7249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disable_endpoint.937067249
Directory /workspace/27.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/27.usbdev_disconnected.97737487
Short name T2367
Test name
Test status
Simulation time 146607151 ps
CPU time 0.8 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206732 kb
Host smart-4f513b82-e1fc-4f9f-979f-d9c77412e5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97737
487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_disconnected.97737487
Directory /workspace/27.usbdev_disconnected/latest

Test location /workspace/coverage/default/27.usbdev_enable.413543983
Short name T903
Test name
Test status
Simulation time 39627136 ps
CPU time 0.7 seconds
Started Jul 22 06:00:38 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206536 kb
Host smart-e3052996-e135-4b98-9ca1-b4fc85748d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41354
3983 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_enable.413543983
Directory /workspace/27.usbdev_enable/latest

Test location /workspace/coverage/default/27.usbdev_endpoint_access.3906825628
Short name T957
Test name
Test status
Simulation time 834389195 ps
CPU time 1.95 seconds
Started Jul 22 06:00:24 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206808 kb
Host smart-63260649-22ad-4c47-8c2f-405fd2e2605e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39068
25628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_endpoint_access.3906825628
Directory /workspace/27.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/27.usbdev_fifo_rst.2254860843
Short name T181
Test name
Test status
Simulation time 205165747 ps
CPU time 1.79 seconds
Started Jul 22 06:00:21 PM PDT 24
Finished Jul 22 06:00:24 PM PDT 24
Peak memory 206844 kb
Host smart-640d76eb-a124-4efc-872b-447605b4c7e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22548
60843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_fifo_rst.2254860843
Directory /workspace/27.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/27.usbdev_in_iso.1367837779
Short name T1622
Test name
Test status
Simulation time 254413428 ps
CPU time 1 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:00:29 PM PDT 24
Peak memory 206736 kb
Host smart-bdc55997-c12f-42ca-ac77-af8d3fb333e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13678
37779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_iso.1367837779
Directory /workspace/27.usbdev_in_iso/latest

Test location /workspace/coverage/default/27.usbdev_in_stall.1114485741
Short name T659
Test name
Test status
Simulation time 161130225 ps
CPU time 0.79 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:00:28 PM PDT 24
Peak memory 206744 kb
Host smart-2e7af1b9-3f6d-431b-b738-6caa2af6f51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11144
85741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_stall.1114485741
Directory /workspace/27.usbdev_in_stall/latest

Test location /workspace/coverage/default/27.usbdev_in_trans.4210230059
Short name T720
Test name
Test status
Simulation time 224994190 ps
CPU time 0.91 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206744 kb
Host smart-f9c32123-592c-41a8-8a77-80ac11a71d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42102
30059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_in_trans.4210230059
Directory /workspace/27.usbdev_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_invalid_sync.3154540941
Short name T996
Test name
Test status
Simulation time 6314510027 ps
CPU time 58.88 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206960 kb
Host smart-b8951915-4389-45e1-882a-2e305f9aeeb3
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3154540941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_invalid_sync.3154540941
Directory /workspace/27.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/27.usbdev_iso_retraction.2161090759
Short name T1185
Test name
Test status
Simulation time 5062173190 ps
CPU time 46.85 seconds
Started Jul 22 06:00:21 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206944 kb
Host smart-b83044c1-73dc-42fc-b340-7543c8cb9c3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21610
90759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_iso_retraction.2161090759
Directory /workspace/27.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/27.usbdev_link_in_err.3799910680
Short name T2022
Test name
Test status
Simulation time 190725358 ps
CPU time 0.91 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:00:34 PM PDT 24
Peak memory 206716 kb
Host smart-fae4f77a-1ea8-410b-9240-de390a9a2d92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37999
10680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_in_err.3799910680
Directory /workspace/27.usbdev_link_in_err/latest

Test location /workspace/coverage/default/27.usbdev_link_resume.3650963409
Short name T845
Test name
Test status
Simulation time 23333239565 ps
CPU time 22.62 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:52 PM PDT 24
Peak memory 206800 kb
Host smart-21611f0d-9045-40b1-a4cb-4a83a733d2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36509
63409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_resume.3650963409
Directory /workspace/27.usbdev_link_resume/latest

Test location /workspace/coverage/default/27.usbdev_link_suspend.4256798085
Short name T662
Test name
Test status
Simulation time 3337074300 ps
CPU time 4.22 seconds
Started Jul 22 06:00:27 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206808 kb
Host smart-84173cbb-1783-4e15-a417-b5c2d5095fae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42567
98085 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_link_suspend.4256798085
Directory /workspace/27.usbdev_link_suspend/latest

Test location /workspace/coverage/default/27.usbdev_low_speed_traffic.3113714187
Short name T2479
Test name
Test status
Simulation time 12727872397 ps
CPU time 88.11 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:02:01 PM PDT 24
Peak memory 206908 kb
Host smart-d194b759-0099-4eca-8db0-c209b6d084eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31137
14187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_low_speed_traffic.3113714187
Directory /workspace/27.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/27.usbdev_max_inter_pkt_delay.1815895563
Short name T442
Test name
Test status
Simulation time 6617697345 ps
CPU time 181.92 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:03:30 PM PDT 24
Peak memory 207072 kb
Host smart-0e5f40c2-392d-46d7-9963-c76375d7a57a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1815895563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_inter_pkt_delay.1815895563
Directory /workspace/27.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_max_length_in_transaction.1678924082
Short name T1307
Test name
Test status
Simulation time 241333650 ps
CPU time 0.96 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206744 kb
Host smart-4d25a668-ade5-4f0a-83c1-dced84abef25
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1678924082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_in_transaction.1678924082
Directory /workspace/27.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_length_out_transaction.777149683
Short name T1751
Test name
Test status
Simulation time 185869318 ps
CPU time 0.94 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206788 kb
Host smart-cc32b886-8fce-4b47-82c1-e28cba49275f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77714
9683 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_length_out_transaction.777149683
Directory /workspace/27.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_max_usb_traffic.2794233687
Short name T2664
Test name
Test status
Simulation time 4889581181 ps
CPU time 128.57 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206916 kb
Host smart-52f0f4c1-8505-4e97-9abb-92c8933769f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27942
33687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_max_usb_traffic.2794233687
Directory /workspace/27.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/27.usbdev_min_inter_pkt_delay.2344593861
Short name T1806
Test name
Test status
Simulation time 3776242772 ps
CPU time 28.21 seconds
Started Jul 22 06:00:33 PM PDT 24
Finished Jul 22 06:01:02 PM PDT 24
Peak memory 206904 kb
Host smart-2edd4db3-60ff-4ea7-be58-29507ce8cf34
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2344593861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_inter_pkt_delay.2344593861
Directory /workspace/27.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/27.usbdev_min_length_in_transaction.2655922933
Short name T599
Test name
Test status
Simulation time 185280137 ps
CPU time 0.84 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206752 kb
Host smart-7a857241-145d-4d65-882e-1db99ff4a240
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2655922933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_in_transaction.2655922933
Directory /workspace/27.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_min_length_out_transaction.1600728720
Short name T462
Test name
Test status
Simulation time 160119282 ps
CPU time 0.75 seconds
Started Jul 22 06:00:35 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206736 kb
Host smart-ecf61af1-b484-461a-9b60-c0b412cf9355
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16007
28720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_min_length_out_transaction.1600728720
Directory /workspace/27.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_nak_trans.3405612593
Short name T2486
Test name
Test status
Simulation time 204774476 ps
CPU time 0.96 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206756 kb
Host smart-eb06b5bf-4f5c-4254-a462-1cf8bcdac34e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34056
12593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_nak_trans.3405612593
Directory /workspace/27.usbdev_nak_trans/latest

Test location /workspace/coverage/default/27.usbdev_out_iso.1989786003
Short name T1383
Test name
Test status
Simulation time 185544317 ps
CPU time 0.9 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206708 kb
Host smart-32aea904-8d2e-4244-bd00-75150a0e4d04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19897
86003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_iso.1989786003
Directory /workspace/27.usbdev_out_iso/latest

Test location /workspace/coverage/default/27.usbdev_out_stall.3368619663
Short name T2045
Test name
Test status
Simulation time 173344829 ps
CPU time 0.87 seconds
Started Jul 22 06:00:27 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206700 kb
Host smart-f1d49086-dea4-46ed-b680-e85d2284f386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33686
19663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_stall.3368619663
Directory /workspace/27.usbdev_out_stall/latest

Test location /workspace/coverage/default/27.usbdev_out_trans_nak.2670440108
Short name T2591
Test name
Test status
Simulation time 182900266 ps
CPU time 0.92 seconds
Started Jul 22 06:00:33 PM PDT 24
Finished Jul 22 06:00:34 PM PDT 24
Peak memory 206752 kb
Host smart-a75d1937-cfd1-48e8-b59d-8fec573353f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26704
40108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_out_trans_nak.2670440108
Directory /workspace/27.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/27.usbdev_pending_in_trans.3072758791
Short name T1143
Test name
Test status
Simulation time 146979860 ps
CPU time 0.79 seconds
Started Jul 22 06:00:27 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206748 kb
Host smart-15bb7d84-604a-4aa7-8c98-36548609353b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30727
58791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pending_in_trans.3072758791
Directory /workspace/27.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_pinflip.4250669802
Short name T1299
Test name
Test status
Simulation time 232674642 ps
CPU time 0.91 seconds
Started Jul 22 06:00:36 PM PDT 24
Finished Jul 22 06:00:38 PM PDT 24
Peak memory 206752 kb
Host smart-934e66d6-0d74-4377-9b2a-53938799a7ff
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4250669802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_pinflip.4250669802
Directory /workspace/27.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/27.usbdev_phy_config_usb_ref_disable.3251328144
Short name T1702
Test name
Test status
Simulation time 199692395 ps
CPU time 0.78 seconds
Started Jul 22 06:00:27 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206660 kb
Host smart-747654c6-3ada-4e46-aebc-abb24b4cad28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32513
28144 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_config_usb_ref_disable.3251328144
Directory /workspace/27.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/27.usbdev_phy_pins_sense.970458747
Short name T2306
Test name
Test status
Simulation time 32997223 ps
CPU time 0.66 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206688 kb
Host smart-823eb46c-a9bb-4b97-8c53-b9b8decbcd51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97045
8747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_phy_pins_sense.970458747
Directory /workspace/27.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/27.usbdev_pkt_received.3427255118
Short name T1261
Test name
Test status
Simulation time 247528600 ps
CPU time 0.94 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206736 kb
Host smart-373796cd-cb50-42ae-8fad-bf0d246bb84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34272
55118 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_received.3427255118
Directory /workspace/27.usbdev_pkt_received/latest

Test location /workspace/coverage/default/27.usbdev_pkt_sent.3159977686
Short name T432
Test name
Test status
Simulation time 237126130 ps
CPU time 0.9 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206724 kb
Host smart-151be515-c364-480f-9b0f-f4ba9c10c887
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31599
77686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_pkt_sent.3159977686
Directory /workspace/27.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/27.usbdev_random_length_in_transaction.29698031
Short name T704
Test name
Test status
Simulation time 233426509 ps
CPU time 0.86 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206696 kb
Host smart-12e95bf4-8534-4101-b9ce-608606fc4dee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29698
031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_in_transaction.29698031
Directory /workspace/27.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/27.usbdev_random_length_out_transaction.3395207731
Short name T1960
Test name
Test status
Simulation time 151236519 ps
CPU time 0.77 seconds
Started Jul 22 06:00:29 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206744 kb
Host smart-00d9b85f-f45d-4848-ac4e-4a9dacfed954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33952
07731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_random_length_out_transaction.3395207731
Directory /workspace/27.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/27.usbdev_rx_crc_err.2532658710
Short name T2030
Test name
Test status
Simulation time 161708889 ps
CPU time 0.77 seconds
Started Jul 22 06:00:26 PM PDT 24
Finished Jul 22 06:00:29 PM PDT 24
Peak memory 206760 kb
Host smart-6adadb61-0aaf-4f33-9dc9-7027365d84e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25326
58710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_rx_crc_err.2532658710
Directory /workspace/27.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/27.usbdev_setup_stage.1771262300
Short name T929
Test name
Test status
Simulation time 161298172 ps
CPU time 0.83 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206728 kb
Host smart-902b68ca-4e70-4199-8267-674276dad18f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17712
62300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_stage.1771262300
Directory /workspace/27.usbdev_setup_stage/latest

Test location /workspace/coverage/default/27.usbdev_setup_trans_ignored.3055238705
Short name T1124
Test name
Test status
Simulation time 145858316 ps
CPU time 0.73 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:31 PM PDT 24
Peak memory 206748 kb
Host smart-fa65501e-8ebe-4a2e-9d5e-b174c4e105bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30552
38705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_setup_trans_ignored.3055238705
Directory /workspace/27.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/27.usbdev_smoke.1942379334
Short name T2035
Test name
Test status
Simulation time 217689283 ps
CPU time 0.97 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206716 kb
Host smart-aa4a36b1-d01d-4c78-b210-67e3791595a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19423
79334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_smoke.1942379334
Directory /workspace/27.usbdev_smoke/latest

Test location /workspace/coverage/default/27.usbdev_spurious_pids_ignored.1351715393
Short name T2442
Test name
Test status
Simulation time 7158109197 ps
CPU time 50.42 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:01:23 PM PDT 24
Peak memory 206932 kb
Host smart-aa74018d-65cb-472c-8fa0-d34346686598
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1351715393 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_spurious_pids_ignored.1351715393
Directory /workspace/27.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/27.usbdev_stall_priority_over_nak.3519819590
Short name T881
Test name
Test status
Simulation time 195752000 ps
CPU time 0.86 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206712 kb
Host smart-23bb62df-519c-4935-8367-30632b37ba81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35198
19590 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_priority_over_nak.3519819590
Directory /workspace/27.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/27.usbdev_stall_trans.3538402692
Short name T1867
Test name
Test status
Simulation time 183432148 ps
CPU time 0.9 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:00:33 PM PDT 24
Peak memory 206744 kb
Host smart-f788ad64-20d1-4443-9e8c-28d79ee6b7a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35384
02692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stall_trans.3538402692
Directory /workspace/27.usbdev_stall_trans/latest

Test location /workspace/coverage/default/27.usbdev_stream_len_max.4131590684
Short name T1501
Test name
Test status
Simulation time 629310924 ps
CPU time 1.64 seconds
Started Jul 22 06:00:33 PM PDT 24
Finished Jul 22 06:00:36 PM PDT 24
Peak memory 206772 kb
Host smart-556f818b-dde5-41df-b30f-48a5b087857f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41315
90684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_stream_len_max.4131590684
Directory /workspace/27.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/27.usbdev_streaming_out.2635949899
Short name T349
Test name
Test status
Simulation time 7672890535 ps
CPU time 70.53 seconds
Started Jul 22 06:00:28 PM PDT 24
Finished Jul 22 06:01:40 PM PDT 24
Peak memory 206892 kb
Host smart-28b4bf92-4edd-4561-a897-7113fd91fc26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26359
49899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.usbdev_streaming_out.2635949899
Directory /workspace/27.usbdev_streaming_out/latest

Test location /workspace/coverage/default/28.usbdev_alert_test.3296456089
Short name T2656
Test name
Test status
Simulation time 40941502 ps
CPU time 0.66 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:00:40 PM PDT 24
Peak memory 206872 kb
Host smart-965b64d4-af48-45e7-aa8b-4d63dd1ededd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3296456089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_alert_test.3296456089
Directory /workspace/28.usbdev_alert_test/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_disconnect.2014910836
Short name T2444
Test name
Test status
Simulation time 3678923722 ps
CPU time 4.51 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:36 PM PDT 24
Peak memory 206860 kb
Host smart-a0f49f0b-530e-4ddd-bbd5-480436f33004
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2014910836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_disconnect.2014910836
Directory /workspace/28.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_reset.833467329
Short name T513
Test name
Test status
Simulation time 13315699355 ps
CPU time 13.24 seconds
Started Jul 22 06:00:31 PM PDT 24
Finished Jul 22 06:00:45 PM PDT 24
Peak memory 206784 kb
Host smart-65f11319-5634-4d84-aeba-56550b6f5bcc
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=833467329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_reset.833467329
Directory /workspace/28.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/28.usbdev_aon_wake_resume.4095627845
Short name T1896
Test name
Test status
Simulation time 23406220169 ps
CPU time 24.15 seconds
Started Jul 22 06:02:03 PM PDT 24
Finished Jul 22 06:02:28 PM PDT 24
Peak memory 206904 kb
Host smart-73ab0498-63d8-4c3a-97b8-e987c8831224
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4095627845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_aon_wake_resume.4095627845
Directory /workspace/28.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/28.usbdev_av_buffer.446113521
Short name T515
Test name
Test status
Simulation time 165826092 ps
CPU time 0.82 seconds
Started Jul 22 06:02:03 PM PDT 24
Finished Jul 22 06:02:05 PM PDT 24
Peak memory 206660 kb
Host smart-214c0975-2242-4cd1-b222-b5b5f4cf9182
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44611
3521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_av_buffer.446113521
Directory /workspace/28.usbdev_av_buffer/latest

Test location /workspace/coverage/default/28.usbdev_bitstuff_err.195178110
Short name T1859
Test name
Test status
Simulation time 146137652 ps
CPU time 0.77 seconds
Started Jul 22 06:00:30 PM PDT 24
Finished Jul 22 06:00:32 PM PDT 24
Peak memory 206748 kb
Host smart-40af4c03-2319-49db-bdc9-4688ff7b68bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19517
8110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_bitstuff_err.195178110
Directory /workspace/28.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_clear.2993309290
Short name T2699
Test name
Test status
Simulation time 369136287 ps
CPU time 1.26 seconds
Started Jul 22 06:00:36 PM PDT 24
Finished Jul 22 06:00:38 PM PDT 24
Peak memory 206776 kb
Host smart-5c69cb81-974f-46dc-bbcd-98896f56abfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29933
09290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_clear.2993309290
Directory /workspace/28.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/28.usbdev_data_toggle_restore.2599665169
Short name T1767
Test name
Test status
Simulation time 1517682891 ps
CPU time 3.77 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:00:41 PM PDT 24
Peak memory 206892 kb
Host smart-c348b119-33df-4e43-895b-66850fcaefc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25996
65169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_data_toggle_restore.2599665169
Directory /workspace/28.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/28.usbdev_device_address.1414102221
Short name T176
Test name
Test status
Simulation time 16284812318 ps
CPU time 35.09 seconds
Started Jul 22 06:00:34 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206932 kb
Host smart-9b73db06-4bac-4085-bcbc-c9c09c9ec2ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
02221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_device_address.1414102221
Directory /workspace/28.usbdev_device_address/latest

Test location /workspace/coverage/default/28.usbdev_disable_endpoint.3759322714
Short name T663
Test name
Test status
Simulation time 516708392 ps
CPU time 1.54 seconds
Started Jul 22 06:00:35 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206756 kb
Host smart-0a1f5b92-aa7d-471d-b99c-a8e8ba033b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37593
22714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disable_endpoint.3759322714
Directory /workspace/28.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/28.usbdev_disconnected.1438486007
Short name T867
Test name
Test status
Simulation time 143699401 ps
CPU time 0.77 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:00:38 PM PDT 24
Peak memory 206632 kb
Host smart-55529ec7-8f46-41f5-a595-f5679d488c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14384
86007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_disconnected.1438486007
Directory /workspace/28.usbdev_disconnected/latest

Test location /workspace/coverage/default/28.usbdev_enable.929331346
Short name T2053
Test name
Test status
Simulation time 52303005 ps
CPU time 0.68 seconds
Started Jul 22 06:00:33 PM PDT 24
Finished Jul 22 06:00:34 PM PDT 24
Peak memory 206900 kb
Host smart-59e340b9-1aa9-4531-9eca-0d9156b810ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92933
1346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_enable.929331346
Directory /workspace/28.usbdev_enable/latest

Test location /workspace/coverage/default/28.usbdev_endpoint_access.3805374001
Short name T855
Test name
Test status
Simulation time 966571502 ps
CPU time 2.1 seconds
Started Jul 22 06:00:36 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206840 kb
Host smart-3fd8a02c-4ea8-4835-8787-27e5a1f2cd61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38053
74001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_endpoint_access.3805374001
Directory /workspace/28.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/28.usbdev_fifo_rst.1731845353
Short name T2388
Test name
Test status
Simulation time 412323805 ps
CPU time 2.43 seconds
Started Jul 22 06:00:34 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206812 kb
Host smart-c3175431-3db2-43e0-8ab1-131c5735caf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17318
45353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_fifo_rst.1731845353
Directory /workspace/28.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/28.usbdev_in_iso.1077148228
Short name T1497
Test name
Test status
Simulation time 191318856 ps
CPU time 0.87 seconds
Started Jul 22 06:02:03 PM PDT 24
Finished Jul 22 06:02:05 PM PDT 24
Peak memory 206688 kb
Host smart-8bacdf87-7957-48fe-a258-3a940a5fee70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10771
48228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_iso.1077148228
Directory /workspace/28.usbdev_in_iso/latest

Test location /workspace/coverage/default/28.usbdev_in_stall.1875128884
Short name T2686
Test name
Test status
Simulation time 152206613 ps
CPU time 0.79 seconds
Started Jul 22 06:00:35 PM PDT 24
Finished Jul 22 06:00:36 PM PDT 24
Peak memory 206732 kb
Host smart-b17bce97-ad6c-4c6b-afca-f8023ea925d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18751
28884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_stall.1875128884
Directory /workspace/28.usbdev_in_stall/latest

Test location /workspace/coverage/default/28.usbdev_in_trans.2170450220
Short name T642
Test name
Test status
Simulation time 224649742 ps
CPU time 0.89 seconds
Started Jul 22 06:00:35 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206800 kb
Host smart-8914fd27-4bf7-45fa-bdee-b8b7162bf6c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21704
50220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_in_trans.2170450220
Directory /workspace/28.usbdev_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_invalid_sync.356991167
Short name T627
Test name
Test status
Simulation time 5537516700 ps
CPU time 38.87 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:01:19 PM PDT 24
Peak memory 206920 kb
Host smart-3a133c92-beff-426a-b081-dc2ad4bf1068
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=356991167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_invalid_sync.356991167
Directory /workspace/28.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/28.usbdev_iso_retraction.1945366359
Short name T2475
Test name
Test status
Simulation time 13854475685 ps
CPU time 45.6 seconds
Started Jul 22 06:00:35 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206908 kb
Host smart-d3c1628e-bf2f-41cb-934b-e3edc212f0b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19453
66359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_iso_retraction.1945366359
Directory /workspace/28.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/28.usbdev_link_in_err.1568771039
Short name T1574
Test name
Test status
Simulation time 234402678 ps
CPU time 0.86 seconds
Started Jul 22 06:00:35 PM PDT 24
Finished Jul 22 06:00:36 PM PDT 24
Peak memory 206732 kb
Host smart-95314d53-c87b-495b-8e07-a1a1f834e0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15687
71039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_in_err.1568771039
Directory /workspace/28.usbdev_link_in_err/latest

Test location /workspace/coverage/default/28.usbdev_link_resume.2092597870
Short name T1180
Test name
Test status
Simulation time 23305060112 ps
CPU time 29.41 seconds
Started Jul 22 06:00:36 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206736 kb
Host smart-a06a9be1-cb5f-4a87-b005-eb9b34378bdf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20925
97870 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_resume.2092597870
Directory /workspace/28.usbdev_link_resume/latest

Test location /workspace/coverage/default/28.usbdev_link_suspend.3687254996
Short name T1273
Test name
Test status
Simulation time 3385414597 ps
CPU time 4.62 seconds
Started Jul 22 06:01:11 PM PDT 24
Finished Jul 22 06:01:17 PM PDT 24
Peak memory 206812 kb
Host smart-715230da-9650-4fb8-b6e9-8695a7fd9e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
54996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_link_suspend.3687254996
Directory /workspace/28.usbdev_link_suspend/latest

Test location /workspace/coverage/default/28.usbdev_low_speed_traffic.2759701786
Short name T560
Test name
Test status
Simulation time 10890315336 ps
CPU time 104.66 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206952 kb
Host smart-cd595fe3-5205-4e09-818c-6777cedccd0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27597
01786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_low_speed_traffic.2759701786
Directory /workspace/28.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/28.usbdev_max_inter_pkt_delay.3008902112
Short name T380
Test name
Test status
Simulation time 4260231153 ps
CPU time 40.94 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:01:18 PM PDT 24
Peak memory 206848 kb
Host smart-ab3ae854-1cff-4660-8b33-e1ab1358a697
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3008902112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_inter_pkt_delay.3008902112
Directory /workspace/28.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_max_length_in_transaction.682387358
Short name T1291
Test name
Test status
Simulation time 263467205 ps
CPU time 0.91 seconds
Started Jul 22 06:00:40 PM PDT 24
Finished Jul 22 06:00:41 PM PDT 24
Peak memory 206876 kb
Host smart-65f21675-1841-41eb-b5c0-2404132b276b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=682387358 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_in_transaction.682387358
Directory /workspace/28.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_length_out_transaction.586003805
Short name T1296
Test name
Test status
Simulation time 210667299 ps
CPU time 0.87 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206688 kb
Host smart-d0d997f4-fb37-4197-b3ee-1b38af3f9091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58600
3805 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_length_out_transaction.586003805
Directory /workspace/28.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_max_usb_traffic.2528879642
Short name T1708
Test name
Test status
Simulation time 4553723070 ps
CPU time 116.07 seconds
Started Jul 22 06:02:47 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 206868 kb
Host smart-2ac59a45-b8db-4d50-841f-02431f5ac844
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25288
79642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_max_usb_traffic.2528879642
Directory /workspace/28.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/28.usbdev_min_inter_pkt_delay.3768750147
Short name T539
Test name
Test status
Simulation time 5518720093 ps
CPU time 39.76 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206868 kb
Host smart-bd323181-dc4c-432c-9ddd-74e7eda0da0a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3768750147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_inter_pkt_delay.3768750147
Directory /workspace/28.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/28.usbdev_min_length_in_transaction.3235381192
Short name T2611
Test name
Test status
Simulation time 163152985 ps
CPU time 0.8 seconds
Started Jul 22 06:00:36 PM PDT 24
Finished Jul 22 06:00:37 PM PDT 24
Peak memory 206712 kb
Host smart-1d96e8a1-c942-49d9-af59-1aa57df02ed1
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3235381192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_in_transaction.3235381192
Directory /workspace/28.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_min_length_out_transaction.505482628
Short name T942
Test name
Test status
Simulation time 141096267 ps
CPU time 0.75 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:00:40 PM PDT 24
Peak memory 206876 kb
Host smart-9142609e-eb02-43e4-b778-67dea5239e4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50548
2628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_min_length_out_transaction.505482628
Directory /workspace/28.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_out_iso.2817455061
Short name T99
Test name
Test status
Simulation time 183219420 ps
CPU time 0.86 seconds
Started Jul 22 06:00:43 PM PDT 24
Finished Jul 22 06:00:45 PM PDT 24
Peak memory 206724 kb
Host smart-4272b779-26fd-4fc3-9c9e-1ebfce665586
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28174
55061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_iso.2817455061
Directory /workspace/28.usbdev_out_iso/latest

Test location /workspace/coverage/default/28.usbdev_out_stall.1338842560
Short name T1636
Test name
Test status
Simulation time 156995049 ps
CPU time 0.82 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:00:42 PM PDT 24
Peak memory 206696 kb
Host smart-6e6d3105-8e06-4057-9164-64b76cd64aad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13388
42560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_stall.1338842560
Directory /workspace/28.usbdev_out_stall/latest

Test location /workspace/coverage/default/28.usbdev_out_trans_nak.3748535036
Short name T1146
Test name
Test status
Simulation time 174897273 ps
CPU time 0.85 seconds
Started Jul 22 06:00:40 PM PDT 24
Finished Jul 22 06:00:42 PM PDT 24
Peak memory 206740 kb
Host smart-066a321b-b377-404d-9373-c7e3d93c69d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37485
35036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_out_trans_nak.3748535036
Directory /workspace/28.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/28.usbdev_pending_in_trans.2845737583
Short name T789
Test name
Test status
Simulation time 232126596 ps
CPU time 0.88 seconds
Started Jul 22 06:00:40 PM PDT 24
Finished Jul 22 06:00:42 PM PDT 24
Peak memory 206736 kb
Host smart-e2e9f64c-a05d-4426-b206-65af841c8ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28457
37583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pending_in_trans.2845737583
Directory /workspace/28.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_pinflip.432879084
Short name T1255
Test name
Test status
Simulation time 243994220 ps
CPU time 0.98 seconds
Started Jul 22 06:00:40 PM PDT 24
Finished Jul 22 06:00:42 PM PDT 24
Peak memory 206728 kb
Host smart-2ef6ce59-aa97-478e-9d54-9d4965bcb5d6
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=432879084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_pinflip.432879084
Directory /workspace/28.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/28.usbdev_phy_config_usb_ref_disable.1569357843
Short name T2613
Test name
Test status
Simulation time 148354449 ps
CPU time 0.81 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206752 kb
Host smart-f1b9ea2a-58b5-40b1-ba35-e529b99e53ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15693
57843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_config_usb_ref_disable.1569357843
Directory /workspace/28.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/28.usbdev_phy_pins_sense.2000754480
Short name T928
Test name
Test status
Simulation time 92626274 ps
CPU time 0.75 seconds
Started Jul 22 06:00:36 PM PDT 24
Finished Jul 22 06:00:38 PM PDT 24
Peak memory 206760 kb
Host smart-4d9d438f-0f1a-4bc4-b658-888bbfe6a928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20007
54480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_phy_pins_sense.2000754480
Directory /workspace/28.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/28.usbdev_pkt_buffer.3367420376
Short name T2174
Test name
Test status
Simulation time 17454045044 ps
CPU time 37.35 seconds
Started Jul 22 06:00:47 PM PDT 24
Finished Jul 22 06:01:25 PM PDT 24
Peak memory 215264 kb
Host smart-c8a90ecd-30ee-49db-9821-a672c4e83d0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33674
20376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_buffer.3367420376
Directory /workspace/28.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/28.usbdev_pkt_received.2668357785
Short name T1645
Test name
Test status
Simulation time 211080494 ps
CPU time 0.93 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206632 kb
Host smart-4a685f24-cc0c-49a3-bdf8-065264f6770c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26683
57785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_received.2668357785
Directory /workspace/28.usbdev_pkt_received/latest

Test location /workspace/coverage/default/28.usbdev_pkt_sent.1740529264
Short name T2216
Test name
Test status
Simulation time 231533628 ps
CPU time 0.88 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206748 kb
Host smart-6d51ba52-58b0-4706-b375-d951ca2d0b7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17405
29264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_pkt_sent.1740529264
Directory /workspace/28.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/28.usbdev_random_length_in_transaction.3881187199
Short name T2149
Test name
Test status
Simulation time 177537837 ps
CPU time 0.83 seconds
Started Jul 22 06:00:37 PM PDT 24
Finished Jul 22 06:00:38 PM PDT 24
Peak memory 206700 kb
Host smart-2f7c9a98-8365-4816-8204-758e04fb9d13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38811
87199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_in_transaction.3881187199
Directory /workspace/28.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/28.usbdev_random_length_out_transaction.1706789706
Short name T1782
Test name
Test status
Simulation time 202996931 ps
CPU time 0.88 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:00:43 PM PDT 24
Peak memory 206704 kb
Host smart-395cf5c5-3f08-407d-9a1d-96f4f00436a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17067
89706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_random_length_out_transaction.1706789706
Directory /workspace/28.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/28.usbdev_rx_crc_err.3886460303
Short name T1995
Test name
Test status
Simulation time 162613388 ps
CPU time 0.79 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:00:43 PM PDT 24
Peak memory 206704 kb
Host smart-559db1a5-501f-434a-ae99-173b767cf954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38864
60303 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_rx_crc_err.3886460303
Directory /workspace/28.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/28.usbdev_setup_stage.3768466168
Short name T1962
Test name
Test status
Simulation time 158627750 ps
CPU time 0.8 seconds
Started Jul 22 06:00:49 PM PDT 24
Finished Jul 22 06:00:50 PM PDT 24
Peak memory 206720 kb
Host smart-985f3f37-e93c-4e1f-815f-0256372a488e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37684
66168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_stage.3768466168
Directory /workspace/28.usbdev_setup_stage/latest

Test location /workspace/coverage/default/28.usbdev_setup_trans_ignored.1269194436
Short name T2316
Test name
Test status
Simulation time 150765649 ps
CPU time 0.79 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:00:40 PM PDT 24
Peak memory 206760 kb
Host smart-d47c4d6a-88af-4d16-a7ba-d73476ad53c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12691
94436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_setup_trans_ignored.1269194436
Directory /workspace/28.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/28.usbdev_smoke.2042957252
Short name T1733
Test name
Test status
Simulation time 218419878 ps
CPU time 0.88 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:00:43 PM PDT 24
Peak memory 206692 kb
Host smart-ddb1e975-a8ef-4b50-ac4c-c4cc96a0794c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20429
57252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_smoke.2042957252
Directory /workspace/28.usbdev_smoke/latest

Test location /workspace/coverage/default/28.usbdev_spurious_pids_ignored.4076463609
Short name T2016
Test name
Test status
Simulation time 4264700285 ps
CPU time 113.14 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:02:35 PM PDT 24
Peak memory 206656 kb
Host smart-9faf4261-2cb9-44a1-84e2-d3bd11692b44
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4076463609 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_spurious_pids_ignored.4076463609
Directory /workspace/28.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/28.usbdev_stall_priority_over_nak.3888198616
Short name T1710
Test name
Test status
Simulation time 165065809 ps
CPU time 0.78 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:00:41 PM PDT 24
Peak memory 206660 kb
Host smart-38839c64-1600-42ed-bd13-a77047f74050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38881
98616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_priority_over_nak.3888198616
Directory /workspace/28.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/28.usbdev_stall_trans.1211128405
Short name T634
Test name
Test status
Simulation time 182866462 ps
CPU time 0.82 seconds
Started Jul 22 06:00:41 PM PDT 24
Finished Jul 22 06:00:43 PM PDT 24
Peak memory 206552 kb
Host smart-4adb25b9-9296-4858-8426-4bc9407eaf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12111
28405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stall_trans.1211128405
Directory /workspace/28.usbdev_stall_trans/latest

Test location /workspace/coverage/default/28.usbdev_stream_len_max.2861831975
Short name T2487
Test name
Test status
Simulation time 253635033 ps
CPU time 0.94 seconds
Started Jul 22 06:00:38 PM PDT 24
Finished Jul 22 06:00:40 PM PDT 24
Peak memory 206660 kb
Host smart-79a6ad54-be64-411b-b1a8-060b64d1b946
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
31975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_stream_len_max.2861831975
Directory /workspace/28.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/28.usbdev_streaming_out.1052385728
Short name T2314
Test name
Test status
Simulation time 5439332656 ps
CPU time 150.43 seconds
Started Jul 22 06:00:35 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206904 kb
Host smart-3188f6a9-3e9d-4712-8df5-b312982a5a06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10523
85728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.usbdev_streaming_out.1052385728
Directory /workspace/28.usbdev_streaming_out/latest

Test location /workspace/coverage/default/29.usbdev_alert_test.2050941291
Short name T1512
Test name
Test status
Simulation time 39357298 ps
CPU time 0.73 seconds
Started Jul 22 06:02:23 PM PDT 24
Finished Jul 22 06:02:25 PM PDT 24
Peak memory 206740 kb
Host smart-7330efdc-5690-4880-9b88-1d2bb4f2df00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2050941291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_alert_test.2050941291
Directory /workspace/29.usbdev_alert_test/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_disconnect.80485109
Short name T1275
Test name
Test status
Simulation time 4299240604 ps
CPU time 4.71 seconds
Started Jul 22 06:00:40 PM PDT 24
Finished Jul 22 06:00:45 PM PDT 24
Peak memory 206948 kb
Host smart-0d24c4fe-2072-4ca6-a072-2e7c19bc9964
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=80485109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_disconnect.80485109
Directory /workspace/29.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_reset.2187672497
Short name T2194
Test name
Test status
Simulation time 13345110545 ps
CPU time 12.84 seconds
Started Jul 22 06:00:39 PM PDT 24
Finished Jul 22 06:00:53 PM PDT 24
Peak memory 206828 kb
Host smart-4b028931-25a4-4228-aa11-07c0229c1e60
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2187672497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_reset.2187672497
Directory /workspace/29.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/29.usbdev_aon_wake_resume.3125534886
Short name T1127
Test name
Test status
Simulation time 23420512560 ps
CPU time 27.76 seconds
Started Jul 22 06:00:44 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206816 kb
Host smart-87e04ba0-2280-4101-9d0c-075dfaf739c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3125534886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_aon_wake_resume.3125534886
Directory /workspace/29.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/29.usbdev_av_buffer.967912708
Short name T1895
Test name
Test status
Simulation time 151091293 ps
CPU time 0.77 seconds
Started Jul 22 06:00:36 PM PDT 24
Finished Jul 22 06:00:38 PM PDT 24
Peak memory 206756 kb
Host smart-9e23a731-b71a-4640-b604-7713a3653d42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96791
2708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_av_buffer.967912708
Directory /workspace/29.usbdev_av_buffer/latest

Test location /workspace/coverage/default/29.usbdev_bitstuff_err.3971175584
Short name T1305
Test name
Test status
Simulation time 151868247 ps
CPU time 0.77 seconds
Started Jul 22 06:00:52 PM PDT 24
Finished Jul 22 06:00:53 PM PDT 24
Peak memory 206756 kb
Host smart-b653100a-07f6-4e23-b381-24bd6ac95d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39711
75584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_bitstuff_err.3971175584
Directory /workspace/29.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_clear.4202695126
Short name T1173
Test name
Test status
Simulation time 418166888 ps
CPU time 1.34 seconds
Started Jul 22 06:00:46 PM PDT 24
Finished Jul 22 06:00:47 PM PDT 24
Peak memory 206788 kb
Host smart-58ea3789-9364-4ca5-b0ee-5eb7a4685fa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42026
95126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_clear.4202695126
Directory /workspace/29.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/29.usbdev_data_toggle_restore.1870136810
Short name T1
Test name
Test status
Simulation time 579680500 ps
CPU time 1.63 seconds
Started Jul 22 06:00:48 PM PDT 24
Finished Jul 22 06:00:51 PM PDT 24
Peak memory 206756 kb
Host smart-9a295ea7-ce7d-4d29-bd21-5f03fabf978f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18701
36810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_data_toggle_restore.1870136810
Directory /workspace/29.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/29.usbdev_device_address.3273045070
Short name T2365
Test name
Test status
Simulation time 6531579574 ps
CPU time 12.93 seconds
Started Jul 22 06:00:48 PM PDT 24
Finished Jul 22 06:01:03 PM PDT 24
Peak memory 206956 kb
Host smart-f98b8f81-9f16-4755-9511-2e0fd3d7a3e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32730
45070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_device_address.3273045070
Directory /workspace/29.usbdev_device_address/latest

Test location /workspace/coverage/default/29.usbdev_disable_endpoint.4117042405
Short name T1741
Test name
Test status
Simulation time 366625202 ps
CPU time 1.17 seconds
Started Jul 22 06:00:47 PM PDT 24
Finished Jul 22 06:00:49 PM PDT 24
Peak memory 206684 kb
Host smart-87e7df1f-8791-452a-93cc-a6d21c54041b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41170
42405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disable_endpoint.4117042405
Directory /workspace/29.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/29.usbdev_disconnected.3969995048
Short name T1439
Test name
Test status
Simulation time 152964430 ps
CPU time 0.81 seconds
Started Jul 22 06:00:50 PM PDT 24
Finished Jul 22 06:00:52 PM PDT 24
Peak memory 206756 kb
Host smart-dd951662-5115-46a8-b2f8-864f366af168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39699
95048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_disconnected.3969995048
Directory /workspace/29.usbdev_disconnected/latest

Test location /workspace/coverage/default/29.usbdev_enable.4216452849
Short name T1448
Test name
Test status
Simulation time 31257400 ps
CPU time 0.68 seconds
Started Jul 22 06:00:58 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 206732 kb
Host smart-87865ce0-4197-4366-913d-fca37723cfa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42164
52849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_enable.4216452849
Directory /workspace/29.usbdev_enable/latest

Test location /workspace/coverage/default/29.usbdev_endpoint_access.1976980263
Short name T1038
Test name
Test status
Simulation time 1007855027 ps
CPU time 2.26 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206836 kb
Host smart-03aa3179-c249-4351-ac3c-4ff27a6a7e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19769
80263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_endpoint_access.1976980263
Directory /workspace/29.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/29.usbdev_fifo_rst.3935225761
Short name T180
Test name
Test status
Simulation time 287444301 ps
CPU time 2.18 seconds
Started Jul 22 06:00:46 PM PDT 24
Finished Jul 22 06:00:49 PM PDT 24
Peak memory 206816 kb
Host smart-8a73421e-7534-4744-99f3-ee9b0e9ad71b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39352
25761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_fifo_rst.3935225761
Directory /workspace/29.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/29.usbdev_in_iso.1902619969
Short name T762
Test name
Test status
Simulation time 213595249 ps
CPU time 0.88 seconds
Started Jul 22 06:01:00 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206728 kb
Host smart-5c6dd120-eebb-4019-a180-f2edde8dd907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19026
19969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_iso.1902619969
Directory /workspace/29.usbdev_in_iso/latest

Test location /workspace/coverage/default/29.usbdev_in_stall.2578449954
Short name T1081
Test name
Test status
Simulation time 141112966 ps
CPU time 0.8 seconds
Started Jul 22 06:00:48 PM PDT 24
Finished Jul 22 06:00:49 PM PDT 24
Peak memory 206628 kb
Host smart-5e8258be-3313-4810-bd94-03466c016d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25784
49954 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_stall.2578449954
Directory /workspace/29.usbdev_in_stall/latest

Test location /workspace/coverage/default/29.usbdev_in_trans.4191981580
Short name T1130
Test name
Test status
Simulation time 191307277 ps
CPU time 0.86 seconds
Started Jul 22 06:00:47 PM PDT 24
Finished Jul 22 06:00:49 PM PDT 24
Peak memory 206696 kb
Host smart-39019ca9-31db-4793-bc53-fdd7cfc9707c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41919
81580 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_in_trans.4191981580
Directory /workspace/29.usbdev_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_invalid_sync.2202362322
Short name T781
Test name
Test status
Simulation time 8065758235 ps
CPU time 74.41 seconds
Started Jul 22 06:00:48 PM PDT 24
Finished Jul 22 06:02:03 PM PDT 24
Peak memory 206860 kb
Host smart-f195e1ac-03bf-4ba3-a6f6-083dba866773
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2202362322 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_invalid_sync.2202362322
Directory /workspace/29.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/29.usbdev_iso_retraction.4034780869
Short name T754
Test name
Test status
Simulation time 6379586613 ps
CPU time 23.55 seconds
Started Jul 22 06:02:31 PM PDT 24
Finished Jul 22 06:02:55 PM PDT 24
Peak memory 206820 kb
Host smart-77c5f074-d6c9-4916-9f67-8a8421415d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40347
80869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_iso_retraction.4034780869
Directory /workspace/29.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/29.usbdev_link_in_err.1695726798
Short name T2329
Test name
Test status
Simulation time 259211699 ps
CPU time 0.95 seconds
Started Jul 22 06:00:51 PM PDT 24
Finished Jul 22 06:00:53 PM PDT 24
Peak memory 206732 kb
Host smart-43286617-7c4d-479f-b257-4ab5e13928fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16957
26798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_in_err.1695726798
Directory /workspace/29.usbdev_link_in_err/latest

Test location /workspace/coverage/default/29.usbdev_link_resume.2338335285
Short name T2320
Test name
Test status
Simulation time 23375888817 ps
CPU time 22.62 seconds
Started Jul 22 06:00:49 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206768 kb
Host smart-810e74b1-9e2f-42e9-b516-1fc7e41808f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23383
35285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_resume.2338335285
Directory /workspace/29.usbdev_link_resume/latest

Test location /workspace/coverage/default/29.usbdev_link_suspend.1690232772
Short name T214
Test name
Test status
Simulation time 3345946262 ps
CPU time 3.99 seconds
Started Jul 22 06:00:56 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206820 kb
Host smart-2a19adf5-4ead-4329-9cf2-f3bd1e5c1e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16902
32772 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_link_suspend.1690232772
Directory /workspace/29.usbdev_link_suspend/latest

Test location /workspace/coverage/default/29.usbdev_low_speed_traffic.726708458
Short name T2422
Test name
Test status
Simulation time 11910142100 ps
CPU time 312.58 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:06:40 PM PDT 24
Peak memory 206968 kb
Host smart-97fbc588-872e-495b-9ed5-70b984879ef7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72670
8458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_low_speed_traffic.726708458
Directory /workspace/29.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/29.usbdev_max_inter_pkt_delay.1745718996
Short name T1699
Test name
Test status
Simulation time 3794287845 ps
CPU time 101 seconds
Started Jul 22 06:00:55 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206852 kb
Host smart-2a2bf9c6-2a92-4cad-a744-27ff343be350
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1745718996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_inter_pkt_delay.1745718996
Directory /workspace/29.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_max_length_in_transaction.1499634647
Short name T1014
Test name
Test status
Simulation time 243225094 ps
CPU time 0.97 seconds
Started Jul 22 06:00:51 PM PDT 24
Finished Jul 22 06:00:52 PM PDT 24
Peak memory 206756 kb
Host smart-e1da3f45-3ff4-46e5-87cf-42b5872f19bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1499634647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_in_transaction.1499634647
Directory /workspace/29.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_length_out_transaction.3136945010
Short name T2126
Test name
Test status
Simulation time 200693380 ps
CPU time 0.85 seconds
Started Jul 22 06:00:49 PM PDT 24
Finished Jul 22 06:00:51 PM PDT 24
Peak memory 206740 kb
Host smart-f7d5239e-e84c-4707-966c-8bd605f0d540
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31369
45010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_length_out_transaction.3136945010
Directory /workspace/29.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_max_usb_traffic.376944356
Short name T1128
Test name
Test status
Simulation time 3878608731 ps
CPU time 104.8 seconds
Started Jul 22 06:00:47 PM PDT 24
Finished Jul 22 06:02:32 PM PDT 24
Peak memory 206948 kb
Host smart-1819b8b8-5fd5-4390-b890-22d56b0db62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37694
4356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_max_usb_traffic.376944356
Directory /workspace/29.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/29.usbdev_min_inter_pkt_delay.3782939863
Short name T1673
Test name
Test status
Simulation time 3485472958 ps
CPU time 93.84 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:02:32 PM PDT 24
Peak memory 206952 kb
Host smart-92845590-63ab-464e-9942-19baa766200f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3782939863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_inter_pkt_delay.3782939863
Directory /workspace/29.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/29.usbdev_min_length_in_transaction.1505428725
Short name T748
Test name
Test status
Simulation time 191274571 ps
CPU time 0.89 seconds
Started Jul 22 06:00:47 PM PDT 24
Finished Jul 22 06:00:49 PM PDT 24
Peak memory 206696 kb
Host smart-28595b39-ef57-454f-b146-4699f30514cd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1505428725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_in_transaction.1505428725
Directory /workspace/29.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_min_length_out_transaction.47886710
Short name T336
Test name
Test status
Simulation time 148556804 ps
CPU time 0.84 seconds
Started Jul 22 06:00:48 PM PDT 24
Finished Jul 22 06:00:50 PM PDT 24
Peak memory 206860 kb
Host smart-755f3059-6c68-4563-ab49-10b824a6acd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47886
710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_min_length_out_transaction.47886710
Directory /workspace/29.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_nak_trans.4237369763
Short name T130
Test name
Test status
Simulation time 168723821 ps
CPU time 0.83 seconds
Started Jul 22 06:00:55 PM PDT 24
Finished Jul 22 06:00:56 PM PDT 24
Peak memory 206736 kb
Host smart-b910a9b9-d28e-436e-b612-73b372725e2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42373
69763 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_nak_trans.4237369763
Directory /workspace/29.usbdev_nak_trans/latest

Test location /workspace/coverage/default/29.usbdev_out_iso.2065463210
Short name T2023
Test name
Test status
Simulation time 155238813 ps
CPU time 0.78 seconds
Started Jul 22 06:00:50 PM PDT 24
Finished Jul 22 06:00:52 PM PDT 24
Peak memory 206744 kb
Host smart-5571cad7-c400-4223-b47d-b7129a593bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20654
63210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_iso.2065463210
Directory /workspace/29.usbdev_out_iso/latest

Test location /workspace/coverage/default/29.usbdev_out_stall.57643068
Short name T1966
Test name
Test status
Simulation time 158440659 ps
CPU time 0.78 seconds
Started Jul 22 06:02:17 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206756 kb
Host smart-9dee8520-eec1-40c4-9059-371901cb5858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57643
068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_stall.57643068
Directory /workspace/29.usbdev_out_stall/latest

Test location /workspace/coverage/default/29.usbdev_out_trans_nak.3229376047
Short name T1770
Test name
Test status
Simulation time 196845950 ps
CPU time 0.8 seconds
Started Jul 22 06:00:46 PM PDT 24
Finished Jul 22 06:00:47 PM PDT 24
Peak memory 206752 kb
Host smart-97a30d4d-c5a8-47f2-b211-a5a8a4bac106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32293
76047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_out_trans_nak.3229376047
Directory /workspace/29.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/29.usbdev_pending_in_trans.2072209221
Short name T2274
Test name
Test status
Simulation time 191923224 ps
CPU time 0.81 seconds
Started Jul 22 06:00:55 PM PDT 24
Finished Jul 22 06:00:57 PM PDT 24
Peak memory 206732 kb
Host smart-0fe0b635-0963-4a40-814d-18bc0e3fd57f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20722
09221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pending_in_trans.2072209221
Directory /workspace/29.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_pinflip.4190157682
Short name T2258
Test name
Test status
Simulation time 262642118 ps
CPU time 1 seconds
Started Jul 22 06:00:56 PM PDT 24
Finished Jul 22 06:00:58 PM PDT 24
Peak memory 206684 kb
Host smart-a576bd9f-ada7-4a4c-b3aa-ff1de71c7db4
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4190157682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_pinflip.4190157682
Directory /workspace/29.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/29.usbdev_phy_config_usb_ref_disable.2419488784
Short name T1976
Test name
Test status
Simulation time 161892001 ps
CPU time 0.8 seconds
Started Jul 22 06:02:44 PM PDT 24
Finished Jul 22 06:02:45 PM PDT 24
Peak memory 206696 kb
Host smart-d1ad880e-e013-477d-ac86-67a17370a822
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24194
88784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_config_usb_ref_disable.2419488784
Directory /workspace/29.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/29.usbdev_phy_pins_sense.697267421
Short name T1714
Test name
Test status
Simulation time 44241401 ps
CPU time 0.64 seconds
Started Jul 22 06:00:56 PM PDT 24
Finished Jul 22 06:00:57 PM PDT 24
Peak memory 206756 kb
Host smart-5c1e3938-cf21-4496-adea-37981247c654
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69726
7421 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_phy_pins_sense.697267421
Directory /workspace/29.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/29.usbdev_pkt_buffer.1546092222
Short name T1153
Test name
Test status
Simulation time 13272123788 ps
CPU time 27.22 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:31 PM PDT 24
Peak memory 206952 kb
Host smart-204c5918-76ab-442d-bf43-7692b12897a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15460
92222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_buffer.1546092222
Directory /workspace/29.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/29.usbdev_pkt_received.375273793
Short name T764
Test name
Test status
Simulation time 189678594 ps
CPU time 0.85 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:00:58 PM PDT 24
Peak memory 206724 kb
Host smart-2ae3b28e-0105-484f-8d01-2fcebbe97ef5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37527
3793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_received.375273793
Directory /workspace/29.usbdev_pkt_received/latest

Test location /workspace/coverage/default/29.usbdev_pkt_sent.2996876484
Short name T2574
Test name
Test status
Simulation time 239361214 ps
CPU time 0.85 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:00:59 PM PDT 24
Peak memory 206736 kb
Host smart-2c4c589a-5cd6-432d-886f-d28404260559
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29968
76484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_pkt_sent.2996876484
Directory /workspace/29.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/29.usbdev_random_length_in_transaction.213438456
Short name T1083
Test name
Test status
Simulation time 166977647 ps
CPU time 0.77 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:23 PM PDT 24
Peak memory 206756 kb
Host smart-8294f581-0374-45f2-8593-d2b75878da8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21343
8456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_in_transaction.213438456
Directory /workspace/29.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/29.usbdev_random_length_out_transaction.503312871
Short name T846
Test name
Test status
Simulation time 177823616 ps
CPU time 0.83 seconds
Started Jul 22 06:00:58 PM PDT 24
Finished Jul 22 06:00:59 PM PDT 24
Peak memory 206736 kb
Host smart-36ab6a8e-47bd-428b-b3b7-4822a9303c9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50331
2871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_random_length_out_transaction.503312871
Directory /workspace/29.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/29.usbdev_rx_crc_err.1478777141
Short name T935
Test name
Test status
Simulation time 193430068 ps
CPU time 0.85 seconds
Started Jul 22 06:00:56 PM PDT 24
Finished Jul 22 06:00:58 PM PDT 24
Peak memory 206628 kb
Host smart-5f158e79-7ed7-447a-b85f-8c33efe312bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14787
77141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_rx_crc_err.1478777141
Directory /workspace/29.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/29.usbdev_setup_stage.24688192
Short name T149
Test name
Test status
Simulation time 165240608 ps
CPU time 0.83 seconds
Started Jul 22 06:01:01 PM PDT 24
Finished Jul 22 06:01:03 PM PDT 24
Peak memory 206736 kb
Host smart-2a0b621c-1824-4062-8092-746e276f2131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24688
192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_stage.24688192
Directory /workspace/29.usbdev_setup_stage/latest

Test location /workspace/coverage/default/29.usbdev_setup_trans_ignored.3925804791
Short name T525
Test name
Test status
Simulation time 158752327 ps
CPU time 0.79 seconds
Started Jul 22 06:02:40 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206748 kb
Host smart-aa2918cb-900e-4324-80ad-f4a939d3f8de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39258
04791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_setup_trans_ignored.3925804791
Directory /workspace/29.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/29.usbdev_smoke.2164992027
Short name T1706
Test name
Test status
Simulation time 237833779 ps
CPU time 0.96 seconds
Started Jul 22 06:02:40 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206740 kb
Host smart-0129a695-741a-419e-95ab-78617b65b2bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21649
92027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_smoke.2164992027
Directory /workspace/29.usbdev_smoke/latest

Test location /workspace/coverage/default/29.usbdev_spurious_pids_ignored.3530842147
Short name T1090
Test name
Test status
Simulation time 3363658384 ps
CPU time 94.27 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:02:33 PM PDT 24
Peak memory 206840 kb
Host smart-be24585b-143a-405b-8891-803f3b488876
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3530842147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_spurious_pids_ignored.3530842147
Directory /workspace/29.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/29.usbdev_stall_priority_over_nak.3911808528
Short name T2298
Test name
Test status
Simulation time 173664623 ps
CPU time 0.83 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:00:59 PM PDT 24
Peak memory 206740 kb
Host smart-e215fc37-b8a1-40f9-8413-ec9f573406fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39118
08528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_priority_over_nak.3911808528
Directory /workspace/29.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/29.usbdev_stall_trans.1579592786
Short name T988
Test name
Test status
Simulation time 174869099 ps
CPU time 0.89 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:08 PM PDT 24
Peak memory 206748 kb
Host smart-fc5afcc7-72ce-4a0e-81c1-d7d83004f8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15795
92786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stall_trans.1579592786
Directory /workspace/29.usbdev_stall_trans/latest

Test location /workspace/coverage/default/29.usbdev_stream_len_max.3450436340
Short name T2302
Test name
Test status
Simulation time 559507637 ps
CPU time 1.41 seconds
Started Jul 22 06:02:44 PM PDT 24
Finished Jul 22 06:02:46 PM PDT 24
Peak memory 206772 kb
Host smart-6d81526f-4cce-473d-b9d1-b6e517d921b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34504
36340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_stream_len_max.3450436340
Directory /workspace/29.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/29.usbdev_streaming_out.3344844828
Short name T354
Test name
Test status
Simulation time 5616958017 ps
CPU time 39.15 seconds
Started Jul 22 06:01:00 PM PDT 24
Finished Jul 22 06:01:40 PM PDT 24
Peak memory 206952 kb
Host smart-13e01baf-ce17-42dd-9969-7c9b2155c379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33448
44828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.usbdev_streaming_out.3344844828
Directory /workspace/29.usbdev_streaming_out/latest

Test location /workspace/coverage/default/3.usbdev_alert_test.2229149041
Short name T1526
Test name
Test status
Simulation time 38455536 ps
CPU time 0.66 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 05:56:57 PM PDT 24
Peak memory 206708 kb
Host smart-1c33e65b-9c0e-44ef-a3ec-eb3973e620f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2229149041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_alert_test.2229149041
Directory /workspace/3.usbdev_alert_test/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_disconnect.2300190177
Short name T1606
Test name
Test status
Simulation time 3741880757 ps
CPU time 4.5 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:48 PM PDT 24
Peak memory 206748 kb
Host smart-5a3c1f54-0ad5-4e04-92ee-af6cb04235cf
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2300190177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_disconnect.2300190177
Directory /workspace/3.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_reset.1076864816
Short name T13
Test name
Test status
Simulation time 13441886137 ps
CPU time 14.03 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206932 kb
Host smart-8cf78e2e-1c8f-4f16-87f5-e14e8d44d355
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1076864816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_reset.1076864816
Directory /workspace/3.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/3.usbdev_aon_wake_resume.3853520823
Short name T2559
Test name
Test status
Simulation time 23345776707 ps
CPU time 23.21 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:57:08 PM PDT 24
Peak memory 206840 kb
Host smart-aa011b8d-40fc-4c40-b0d3-1c7e30acf0b1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3853520823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_aon_wake_resume.3853520823
Directory /workspace/3.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/3.usbdev_av_buffer.1179372488
Short name T2567
Test name
Test status
Simulation time 158301329 ps
CPU time 0.82 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206712 kb
Host smart-c9d9057b-4183-456a-805a-0c688f09f16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11793
72488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_buffer.1179372488
Directory /workspace/3.usbdev_av_buffer/latest

Test location /workspace/coverage/default/3.usbdev_av_overflow.2234205328
Short name T70
Test name
Test status
Simulation time 161052990 ps
CPU time 0.78 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:56:40 PM PDT 24
Peak memory 206756 kb
Host smart-0a6fd8b1-7f64-4031-b13a-2f8e88ed9ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22342
05328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_av_overflow.2234205328
Directory /workspace/3.usbdev_av_overflow/latest

Test location /workspace/coverage/default/3.usbdev_bitstuff_err.1622850807
Short name T2318
Test name
Test status
Simulation time 191894131 ps
CPU time 0.84 seconds
Started Jul 22 05:56:38 PM PDT 24
Finished Jul 22 05:56:40 PM PDT 24
Peak memory 206692 kb
Host smart-4f5a9b73-cc2d-44cc-8f61-54361796f8fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16228
50807 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_bitstuff_err.1622850807
Directory /workspace/3.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_clear.1262115226
Short name T820
Test name
Test status
Simulation time 222302231 ps
CPU time 1.02 seconds
Started Jul 22 05:56:37 PM PDT 24
Finished Jul 22 05:56:39 PM PDT 24
Peak memory 206700 kb
Host smart-7e8dbf1c-0025-4864-8a78-65ff37818461
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12621
15226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_clear.1262115226
Directory /workspace/3.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/3.usbdev_data_toggle_restore.1121949801
Short name T1924
Test name
Test status
Simulation time 714434184 ps
CPU time 1.7 seconds
Started Jul 22 05:56:48 PM PDT 24
Finished Jul 22 05:56:50 PM PDT 24
Peak memory 206900 kb
Host smart-ed32dc9b-dee0-45a5-bef1-9037e48f64ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11219
49801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_data_toggle_restore.1121949801
Directory /workspace/3.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/3.usbdev_device_address.2405247825
Short name T1297
Test name
Test status
Simulation time 21016984670 ps
CPU time 38.73 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:57:24 PM PDT 24
Peak memory 206944 kb
Host smart-7d9fcfff-9f26-4ad6-9b38-ba89dafc2020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24052
47825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_device_address.2405247825
Directory /workspace/3.usbdev_device_address/latest

Test location /workspace/coverage/default/3.usbdev_disable_endpoint.1962922025
Short name T923
Test name
Test status
Simulation time 399905510 ps
CPU time 1.21 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:46 PM PDT 24
Peak memory 206744 kb
Host smart-681ec575-4d73-4bac-b844-fa8399a98605
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19629
22025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disable_endpoint.1962922025
Directory /workspace/3.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/3.usbdev_disconnected.2893054235
Short name T1565
Test name
Test status
Simulation time 184995738 ps
CPU time 0.79 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206748 kb
Host smart-f3aef1aa-d31a-4ef4-83b9-6309e37c1400
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28930
54235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_disconnected.2893054235
Directory /workspace/3.usbdev_disconnected/latest

Test location /workspace/coverage/default/3.usbdev_enable.3607700921
Short name T2309
Test name
Test status
Simulation time 86061717 ps
CPU time 0.75 seconds
Started Jul 22 05:56:47 PM PDT 24
Finished Jul 22 05:56:48 PM PDT 24
Peak memory 206740 kb
Host smart-994bf994-1b32-4d9c-8dd1-0fc85f6c82af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36077
00921 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_enable.3607700921
Directory /workspace/3.usbdev_enable/latest

Test location /workspace/coverage/default/3.usbdev_endpoint_access.380331379
Short name T566
Test name
Test status
Simulation time 973492563 ps
CPU time 2.13 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:48 PM PDT 24
Peak memory 206852 kb
Host smart-99a7ecf5-878a-480c-bad3-0ad5381a59f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38033
1379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_endpoint_access.380331379
Directory /workspace/3.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/3.usbdev_fifo_rst.1407908792
Short name T2
Test name
Test status
Simulation time 250748068 ps
CPU time 1.87 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:48 PM PDT 24
Peak memory 206796 kb
Host smart-fc41fad4-6a29-4cd3-9c0b-682c810f1a9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14079
08792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_fifo_rst.1407908792
Directory /workspace/3.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk.608519153
Short name T2693
Test name
Test status
Simulation time 82215173951 ps
CPU time 107.51 seconds
Started Jul 22 05:56:47 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206972 kb
Host smart-3b88198e-c8ad-4eb3-880f-d188e83169ea
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=608519153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk.608519153
Directory /workspace/3.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_hiclk_max.2868497672
Short name T821
Test name
Test status
Simulation time 92361185231 ps
CPU time 137.56 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:59:07 PM PDT 24
Peak memory 206968 kb
Host smart-95d2c5b7-4276-4c89-9aaf-50f6116c9227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868497672 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_hiclk_max.2868497672
Directory /workspace/3.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk.2474222640
Short name T1604
Test name
Test status
Simulation time 86112948576 ps
CPU time 116.04 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:58:50 PM PDT 24
Peak memory 206832 kb
Host smart-2b612209-9a0c-47ab-a093-c95f8cf51152
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2474222640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk.2474222640
Directory /workspace/3.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/3.usbdev_freq_loclk_max.3237761955
Short name T1108
Test name
Test status
Simulation time 91232428382 ps
CPU time 114.16 seconds
Started Jul 22 05:56:46 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206964 kb
Host smart-be094bf3-e3d5-40b5-8839-77870f0d949c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237761955 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_loclk_max.3237761955
Directory /workspace/3.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/3.usbdev_freq_phase.3510918121
Short name T2323
Test name
Test status
Simulation time 113133388420 ps
CPU time 151.09 seconds
Started Jul 22 05:56:45 PM PDT 24
Finished Jul 22 05:59:17 PM PDT 24
Peak memory 206848 kb
Host smart-dc3377f6-9256-4476-b4d4-d30ba2083422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35109
18121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_freq_phase.3510918121
Directory /workspace/3.usbdev_freq_phase/latest

Test location /workspace/coverage/default/3.usbdev_in_iso.1171546205
Short name T1509
Test name
Test status
Simulation time 214487563 ps
CPU time 0.9 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:46 PM PDT 24
Peak memory 206672 kb
Host smart-1f366a70-0a6d-4eb1-9cf3-477c0f35c0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11715
46205 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_iso.1171546205
Directory /workspace/3.usbdev_in_iso/latest

Test location /workspace/coverage/default/3.usbdev_in_stall.2422609488
Short name T319
Test name
Test status
Simulation time 148856817 ps
CPU time 0.79 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 05:56:52 PM PDT 24
Peak memory 206708 kb
Host smart-474fa481-dcdc-40c3-9662-b5bab622a8db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24226
09488 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_stall.2422609488
Directory /workspace/3.usbdev_in_stall/latest

Test location /workspace/coverage/default/3.usbdev_in_trans.213522845
Short name T333
Test name
Test status
Simulation time 191488061 ps
CPU time 0.87 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:56:50 PM PDT 24
Peak memory 206744 kb
Host smart-aa98748d-e3a4-4c1d-bc2e-285d44dd5805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21352
2845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_in_trans.213522845
Directory /workspace/3.usbdev_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_link_in_err.2758255073
Short name T2383
Test name
Test status
Simulation time 260537399 ps
CPU time 0.89 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206736 kb
Host smart-7d618b32-e3d7-4ddd-8c58-20eb7570b59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27582
55073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_in_err.2758255073
Directory /workspace/3.usbdev_link_in_err/latest

Test location /workspace/coverage/default/3.usbdev_link_resume.1725840589
Short name T901
Test name
Test status
Simulation time 23342260484 ps
CPU time 24.9 seconds
Started Jul 22 05:56:46 PM PDT 24
Finished Jul 22 05:57:12 PM PDT 24
Peak memory 206804 kb
Host smart-42c7655d-0f16-40ce-a53a-43ef64897b9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17258
40589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_resume.1725840589
Directory /workspace/3.usbdev_link_resume/latest

Test location /workspace/coverage/default/3.usbdev_link_suspend.3722409608
Short name T1840
Test name
Test status
Simulation time 3303768726 ps
CPU time 3.8 seconds
Started Jul 22 05:56:48 PM PDT 24
Finished Jul 22 05:56:52 PM PDT 24
Peak memory 206804 kb
Host smart-af5ba6b1-1675-4a17-a0fe-2823cb95c0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37224
09608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_link_suspend.3722409608
Directory /workspace/3.usbdev_link_suspend/latest

Test location /workspace/coverage/default/3.usbdev_low_speed_traffic.1779686667
Short name T1123
Test name
Test status
Simulation time 13170679780 ps
CPU time 116.61 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:58:43 PM PDT 24
Peak memory 206900 kb
Host smart-8ba88d35-d206-4929-8c64-c9e8bb493a8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17796
86667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_low_speed_traffic.1779686667
Directory /workspace/3.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/3.usbdev_max_inter_pkt_delay.1373550654
Short name T2614
Test name
Test status
Simulation time 4275554637 ps
CPU time 42.13 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:57:28 PM PDT 24
Peak memory 206880 kb
Host smart-07ccabf1-1b56-47ba-ab9f-d068e503966a
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1373550654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_inter_pkt_delay.1373550654
Directory /workspace/3.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_max_length_in_transaction.1971227865
Short name T2506
Test name
Test status
Simulation time 249560203 ps
CPU time 0.89 seconds
Started Jul 22 05:56:41 PM PDT 24
Finished Jul 22 05:56:44 PM PDT 24
Peak memory 206764 kb
Host smart-103e14b0-79cc-4ea8-b43b-72a9f2abce50
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1971227865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_in_transaction.1971227865
Directory /workspace/3.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_length_out_transaction.1160457490
Short name T1800
Test name
Test status
Simulation time 210824738 ps
CPU time 0.93 seconds
Started Jul 22 05:56:42 PM PDT 24
Finished Jul 22 05:56:45 PM PDT 24
Peak memory 206760 kb
Host smart-1a1710a6-8999-410f-bafa-39a36a0fdde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11604
57490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_length_out_transaction.1160457490
Directory /workspace/3.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_max_usb_traffic.3016826985
Short name T1624
Test name
Test status
Simulation time 4708104835 ps
CPU time 134.12 seconds
Started Jul 22 05:56:45 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 206860 kb
Host smart-64dee9d0-dbfb-4224-980e-d8962ae43a88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30168
26985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_max_usb_traffic.3016826985
Directory /workspace/3.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/3.usbdev_min_inter_pkt_delay.3623674592
Short name T1067
Test name
Test status
Simulation time 5099870203 ps
CPU time 47.55 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:57:37 PM PDT 24
Peak memory 206888 kb
Host smart-b269433c-6143-4161-a249-7c31fd49dfcd
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3623674592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_inter_pkt_delay.3623674592
Directory /workspace/3.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/3.usbdev_min_length_in_transaction.3822627725
Short name T1696
Test name
Test status
Simulation time 217783005 ps
CPU time 0.85 seconds
Started Jul 22 05:56:47 PM PDT 24
Finished Jul 22 05:56:48 PM PDT 24
Peak memory 206596 kb
Host smart-46af5351-d2bf-4f89-b4f0-ffc9138c3903
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3822627725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_in_transaction.3822627725
Directory /workspace/3.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_min_length_out_transaction.1836709219
Short name T425
Test name
Test status
Simulation time 164468187 ps
CPU time 0.79 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206740 kb
Host smart-4da93e6f-f121-43f3-a392-0ed962b9dab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18367
09219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_min_length_out_transaction.1836709219
Directory /workspace/3.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_nak_trans.202592080
Short name T102
Test name
Test status
Simulation time 193728294 ps
CPU time 0.91 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206748 kb
Host smart-519ea215-a463-4ed5-aa36-194da6e380e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20259
2080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_nak_trans.202592080
Directory /workspace/3.usbdev_nak_trans/latest

Test location /workspace/coverage/default/3.usbdev_out_iso.1392805689
Short name T2449
Test name
Test status
Simulation time 166065808 ps
CPU time 0.8 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206740 kb
Host smart-e9ebf717-984e-4f79-a34e-5c22b63ffa59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13928
05689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_iso.1392805689
Directory /workspace/3.usbdev_out_iso/latest

Test location /workspace/coverage/default/3.usbdev_out_stall.3927689312
Short name T272
Test name
Test status
Simulation time 184524598 ps
CPU time 0.86 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:56:55 PM PDT 24
Peak memory 206740 kb
Host smart-1a6a7b5d-172b-4bff-8c94-2ff01170081b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39276
89312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_stall.3927689312
Directory /workspace/3.usbdev_out_stall/latest

Test location /workspace/coverage/default/3.usbdev_out_trans_nak.1828440881
Short name T1598
Test name
Test status
Simulation time 151696329 ps
CPU time 0.74 seconds
Started Jul 22 05:56:50 PM PDT 24
Finished Jul 22 05:56:51 PM PDT 24
Peak memory 206736 kb
Host smart-c4d7dcdf-194f-4932-816e-7713e791b169
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18284
40881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_out_trans_nak.1828440881
Directory /workspace/3.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/3.usbdev_pending_in_trans.116923894
Short name T2474
Test name
Test status
Simulation time 158860688 ps
CPU time 0.84 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:56:50 PM PDT 24
Peak memory 206748 kb
Host smart-54ad2ae8-08ff-4873-a205-f418be63016c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11692
3894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pending_in_trans.116923894
Directory /workspace/3.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_pinflip.4270476682
Short name T878
Test name
Test status
Simulation time 223382818 ps
CPU time 0.9 seconds
Started Jul 22 05:56:45 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206704 kb
Host smart-8ceb6ff8-cd7a-425f-b63c-bb23622ef38b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4270476682 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_pinflip.4270476682
Directory /workspace/3.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_rand_bus_type.2810936738
Short name T199
Test name
Test status
Simulation time 223243129 ps
CPU time 0.9 seconds
Started Jul 22 05:56:50 PM PDT 24
Finished Jul 22 05:56:52 PM PDT 24
Peak memory 206692 kb
Host smart-4223c0e3-6973-4204-abec-60aaca914e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28109
36738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_rand_bus_type.2810936738
Directory /workspace/3.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/3.usbdev_phy_config_usb_ref_disable.3984715979
Short name T2168
Test name
Test status
Simulation time 149428848 ps
CPU time 0.81 seconds
Started Jul 22 05:56:45 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206748 kb
Host smart-97a7f9e5-60cf-455a-9415-490946896cf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39847
15979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_config_usb_ref_disable.3984715979
Directory /workspace/3.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/3.usbdev_phy_pins_sense.3124247218
Short name T1981
Test name
Test status
Simulation time 35723412 ps
CPU time 0.71 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:56:50 PM PDT 24
Peak memory 206688 kb
Host smart-a55e6f5a-d28d-4c84-ae80-95d007d401bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31242
47218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_phy_pins_sense.3124247218
Directory /workspace/3.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/3.usbdev_pkt_buffer.916116708
Short name T251
Test name
Test status
Simulation time 9081466646 ps
CPU time 20.43 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:57:10 PM PDT 24
Peak memory 215136 kb
Host smart-f37215cc-b146-4f3e-a67c-a1ce7f20a20d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91611
6708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_buffer.916116708
Directory /workspace/3.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/3.usbdev_pkt_received.1495804860
Short name T676
Test name
Test status
Simulation time 215909996 ps
CPU time 0.87 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:53 PM PDT 24
Peak memory 206728 kb
Host smart-8c336495-e71c-4b49-8a25-9c51d750df82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14958
04860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_received.1495804860
Directory /workspace/3.usbdev_pkt_received/latest

Test location /workspace/coverage/default/3.usbdev_pkt_sent.2234959705
Short name T2586
Test name
Test status
Simulation time 198077875 ps
CPU time 0.9 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:56:51 PM PDT 24
Peak memory 206748 kb
Host smart-fed0d6ec-a007-4a7f-825f-e64697d7ef7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22349
59705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_pkt_sent.2234959705
Directory /workspace/3.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/3.usbdev_rand_bus_resets.2004199405
Short name T922
Test name
Test status
Simulation time 13774647861 ps
CPU time 74.26 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:58:09 PM PDT 24
Peak memory 206964 kb
Host smart-119b5de7-278f-4c3d-b552-2978391ff46b
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2004199405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_bus_resets.2004199405
Directory /workspace/3.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/3.usbdev_rand_suspends.2101544752
Short name T2187
Test name
Test status
Simulation time 6677541748 ps
CPU time 98.53 seconds
Started Jul 22 05:56:46 PM PDT 24
Finished Jul 22 05:58:25 PM PDT 24
Peak memory 206900 kb
Host smart-21153ad2-ff3e-4778-b9a1-e05d2c3fa660
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2101544752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rand_suspends.2101544752
Directory /workspace/3.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/3.usbdev_random_length_in_transaction.466517673
Short name T1666
Test name
Test status
Simulation time 208004712 ps
CPU time 0.82 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206728 kb
Host smart-a9f63c59-96fd-4c0f-880b-fcce2db47546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46651
7673 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_in_transaction.466517673
Directory /workspace/3.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/3.usbdev_random_length_out_transaction.2165973781
Short name T2139
Test name
Test status
Simulation time 209998278 ps
CPU time 0.93 seconds
Started Jul 22 05:56:44 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206744 kb
Host smart-e432be8a-976c-4258-8ba3-56c84ebaee23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21659
73781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_random_length_out_transaction.2165973781
Directory /workspace/3.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/3.usbdev_rx_crc_err.503580182
Short name T2088
Test name
Test status
Simulation time 199624930 ps
CPU time 0.88 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:56:50 PM PDT 24
Peak memory 206712 kb
Host smart-3a9bae72-c36a-43b3-ab26-9e2ba4f49d5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50358
0182 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_crc_err.503580182
Directory /workspace/3.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/3.usbdev_rx_pid_err.3496384487
Short name T2203
Test name
Test status
Simulation time 161773591 ps
CPU time 0.78 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:57 PM PDT 24
Peak memory 206700 kb
Host smart-23679884-b247-4f26-b7ec-fbb9e58503a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34963
84487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_rx_pid_err.3496384487
Directory /workspace/3.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/3.usbdev_sec_cm.3990405005
Short name T191
Test name
Test status
Simulation time 1399835863 ps
CPU time 2.21 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:56:59 PM PDT 24
Peak memory 224376 kb
Host smart-b32ea706-7615-48b1-b885-d58b87fb95b8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3990405005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_sec_cm.3990405005
Directory /workspace/3.usbdev_sec_cm/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority.3225290355
Short name T63
Test name
Test status
Simulation time 371110679 ps
CPU time 1.31 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 05:56:53 PM PDT 24
Peak memory 206764 kb
Host smart-1e98140b-7738-4cf4-a79f-c6d035fdeebf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32252
90355 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority.3225290355
Directory /workspace/3.usbdev_setup_priority/latest

Test location /workspace/coverage/default/3.usbdev_setup_priority_over_stall_response.442155012
Short name T2087
Test name
Test status
Simulation time 202639401 ps
CPU time 0.88 seconds
Started Jul 22 05:56:50 PM PDT 24
Finished Jul 22 05:56:51 PM PDT 24
Peak memory 206704 kb
Host smart-d2748c38-551f-4a1b-897a-582b7b0b5394
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44215
5012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_priority_over_stall_response.442155012
Directory /workspace/3.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/3.usbdev_setup_stage.1853636733
Short name T1027
Test name
Test status
Simulation time 183543029 ps
CPU time 0.85 seconds
Started Jul 22 05:56:49 PM PDT 24
Finished Jul 22 05:56:50 PM PDT 24
Peak memory 206744 kb
Host smart-e80de559-67be-473d-b68a-dd2763a7a531
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18536
36733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_stage.1853636733
Directory /workspace/3.usbdev_setup_stage/latest

Test location /workspace/coverage/default/3.usbdev_setup_trans_ignored.787466591
Short name T1283
Test name
Test status
Simulation time 157637355 ps
CPU time 0.8 seconds
Started Jul 22 05:56:43 PM PDT 24
Finished Jul 22 05:56:46 PM PDT 24
Peak memory 206724 kb
Host smart-71718c98-c447-4fb0-bb93-783b99e0a9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78746
6591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_setup_trans_ignored.787466591
Directory /workspace/3.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/3.usbdev_smoke.425783686
Short name T578
Test name
Test status
Simulation time 185617105 ps
CPU time 0.91 seconds
Started Jul 22 05:56:47 PM PDT 24
Finished Jul 22 05:56:48 PM PDT 24
Peak memory 206564 kb
Host smart-eef13436-80c2-4e23-8c94-e9f711f8da25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42578
3686 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_smoke.425783686
Directory /workspace/3.usbdev_smoke/latest

Test location /workspace/coverage/default/3.usbdev_spurious_pids_ignored.3701852319
Short name T1967
Test name
Test status
Simulation time 5965918638 ps
CPU time 160.23 seconds
Started Jul 22 05:56:50 PM PDT 24
Finished Jul 22 05:59:31 PM PDT 24
Peak memory 206880 kb
Host smart-6cbe1103-f30b-4956-88e3-f187524fb465
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3701852319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_spurious_pids_ignored.3701852319
Directory /workspace/3.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/3.usbdev_stall_priority_over_nak.671230414
Short name T427
Test name
Test status
Simulation time 154186625 ps
CPU time 0.79 seconds
Started Jul 22 05:56:45 PM PDT 24
Finished Jul 22 05:56:47 PM PDT 24
Peak memory 206696 kb
Host smart-2bdad535-395f-48e0-b51c-f847b8c2c7d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67123
0414 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_priority_over_nak.671230414
Directory /workspace/3.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/3.usbdev_stall_trans.606310645
Short name T2239
Test name
Test status
Simulation time 196890488 ps
CPU time 0.83 seconds
Started Jul 22 05:56:48 PM PDT 24
Finished Jul 22 05:56:49 PM PDT 24
Peak memory 206752 kb
Host smart-e4c63170-f313-492b-b1ba-d9597e685dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60631
0645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stall_trans.606310645
Directory /workspace/3.usbdev_stall_trans/latest

Test location /workspace/coverage/default/3.usbdev_stream_len_max.2236686601
Short name T1650
Test name
Test status
Simulation time 527472943 ps
CPU time 1.41 seconds
Started Jul 22 05:56:50 PM PDT 24
Finished Jul 22 05:56:52 PM PDT 24
Peak memory 206732 kb
Host smart-1dbc8aa9-53da-418a-838a-74856b25672f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22366
86601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_stream_len_max.2236686601
Directory /workspace/3.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/3.usbdev_streaming_out.2542791339
Short name T2412
Test name
Test status
Simulation time 3904746562 ps
CPU time 36.1 seconds
Started Jul 22 05:56:47 PM PDT 24
Finished Jul 22 05:57:24 PM PDT 24
Peak memory 206960 kb
Host smart-3fae7f27-08e9-4ae4-83c4-34fb9f5d4320
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25427
91339 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.usbdev_streaming_out.2542791339
Directory /workspace/3.usbdev_streaming_out/latest

Test location /workspace/coverage/default/30.usbdev_alert_test.363183119
Short name T2039
Test name
Test status
Simulation time 60167913 ps
CPU time 0.69 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206740 kb
Host smart-402e0c2e-d007-43e0-b610-99326c34d33e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=363183119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_alert_test.363183119
Directory /workspace/30.usbdev_alert_test/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_disconnect.1696286864
Short name T1220
Test name
Test status
Simulation time 3756398643 ps
CPU time 4.56 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 206680 kb
Host smart-9454cc64-bb98-44ac-9008-ba6312e33014
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1696286864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_disconnect.1696286864
Directory /workspace/30.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_reset.394727827
Short name T2440
Test name
Test status
Simulation time 13455045465 ps
CPU time 15.97 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:20 PM PDT 24
Peak memory 206968 kb
Host smart-b4ae17af-51b3-4d0e-9431-1d1ea6cd22d9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=394727827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_reset.394727827
Directory /workspace/30.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/30.usbdev_aon_wake_resume.410268968
Short name T2075
Test name
Test status
Simulation time 23374755519 ps
CPU time 29.03 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:36 PM PDT 24
Peak memory 206844 kb
Host smart-ad05d58d-6524-4454-af50-30064ec96e24
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=410268968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_aon_wake_resume.410268968
Directory /workspace/30.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/30.usbdev_av_buffer.1582506760
Short name T144
Test name
Test status
Simulation time 156710476 ps
CPU time 0.75 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:00:59 PM PDT 24
Peak memory 206724 kb
Host smart-f6b08611-e7b4-4c6f-b8a5-43f0bc8bb511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15825
06760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_av_buffer.1582506760
Directory /workspace/30.usbdev_av_buffer/latest

Test location /workspace/coverage/default/30.usbdev_bitstuff_err.157211199
Short name T2473
Test name
Test status
Simulation time 199117546 ps
CPU time 0.86 seconds
Started Jul 22 06:00:56 PM PDT 24
Finished Jul 22 06:00:57 PM PDT 24
Peak memory 206704 kb
Host smart-4cb9e0b7-2c3b-4710-8a07-ccb6057093f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15721
1199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_bitstuff_err.157211199
Directory /workspace/30.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_clear.3074856026
Short name T758
Test name
Test status
Simulation time 296514401 ps
CPU time 1.02 seconds
Started Jul 22 06:02:44 PM PDT 24
Finished Jul 22 06:02:46 PM PDT 24
Peak memory 206768 kb
Host smart-6e354a78-8444-4e18-a315-5dd7a17e4fce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30748
56026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_clear.3074856026
Directory /workspace/30.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/30.usbdev_data_toggle_restore.2694890196
Short name T2268
Test name
Test status
Simulation time 282682630 ps
CPU time 0.91 seconds
Started Jul 22 06:00:56 PM PDT 24
Finished Jul 22 06:00:57 PM PDT 24
Peak memory 206708 kb
Host smart-f1b113b6-a22d-4c03-800d-34037bd390d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26948
90196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_data_toggle_restore.2694890196
Directory /workspace/30.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/30.usbdev_device_address.323962014
Short name T156
Test name
Test status
Simulation time 7326194947 ps
CPU time 13.51 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:25 PM PDT 24
Peak memory 206772 kb
Host smart-f58064b7-9a15-4151-b84f-f8f9d1b394c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32396
2014 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_device_address.323962014
Directory /workspace/30.usbdev_device_address/latest

Test location /workspace/coverage/default/30.usbdev_disable_endpoint.3571750695
Short name T2136
Test name
Test status
Simulation time 438895583 ps
CPU time 1.32 seconds
Started Jul 22 06:01:12 PM PDT 24
Finished Jul 22 06:01:14 PM PDT 24
Peak memory 206796 kb
Host smart-a97948b6-4628-4d70-8309-d498a7885dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
50695 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disable_endpoint.3571750695
Directory /workspace/30.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/30.usbdev_disconnected.3914406589
Short name T2674
Test name
Test status
Simulation time 137289821 ps
CPU time 0.76 seconds
Started Jul 22 06:01:00 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206728 kb
Host smart-b7342a18-96d0-41ae-88cc-da7176249d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39144
06589 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_disconnected.3914406589
Directory /workspace/30.usbdev_disconnected/latest

Test location /workspace/coverage/default/30.usbdev_enable.2452440886
Short name T1252
Test name
Test status
Simulation time 44353040 ps
CPU time 0.68 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:00:58 PM PDT 24
Peak memory 206740 kb
Host smart-0fc5ce25-8538-41c3-9ca3-33ed2fa46173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24524
40886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_enable.2452440886
Directory /workspace/30.usbdev_enable/latest

Test location /workspace/coverage/default/30.usbdev_endpoint_access.3060561463
Short name T1086
Test name
Test status
Simulation time 806724124 ps
CPU time 1.9 seconds
Started Jul 22 06:00:59 PM PDT 24
Finished Jul 22 06:01:02 PM PDT 24
Peak memory 206796 kb
Host smart-7f04fdc6-3142-4e38-8810-104ce9f8f77c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30605
61463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_endpoint_access.3060561463
Directory /workspace/30.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/30.usbdev_fifo_rst.369086574
Short name T478
Test name
Test status
Simulation time 369456554 ps
CPU time 2.3 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 206888 kb
Host smart-e46e5b36-e5cc-426b-b18a-c013aa5202ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36908
6574 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_fifo_rst.369086574
Directory /workspace/30.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/30.usbdev_in_iso.1194624956
Short name T1502
Test name
Test status
Simulation time 204569407 ps
CPU time 0.9 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:00:59 PM PDT 24
Peak memory 206860 kb
Host smart-9cda14ee-c305-425f-b40f-8de8ec5f84d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11946
24956 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_iso.1194624956
Directory /workspace/30.usbdev_in_iso/latest

Test location /workspace/coverage/default/30.usbdev_in_stall.1498637603
Short name T1160
Test name
Test status
Simulation time 140860894 ps
CPU time 0.77 seconds
Started Jul 22 06:00:56 PM PDT 24
Finished Jul 22 06:00:58 PM PDT 24
Peak memory 206744 kb
Host smart-88331dad-3998-45af-a8b4-5c8b42040293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
37603 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_stall.1498637603
Directory /workspace/30.usbdev_in_stall/latest

Test location /workspace/coverage/default/30.usbdev_in_trans.1347000538
Short name T2004
Test name
Test status
Simulation time 247942222 ps
CPU time 0.93 seconds
Started Jul 22 06:00:58 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 206760 kb
Host smart-ebcc6ca0-a837-4161-8be3-c23269254240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13470
00538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_in_trans.1347000538
Directory /workspace/30.usbdev_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_link_in_err.2744785599
Short name T2397
Test name
Test status
Simulation time 275000409 ps
CPU time 1 seconds
Started Jul 22 06:00:57 PM PDT 24
Finished Jul 22 06:00:59 PM PDT 24
Peak memory 206860 kb
Host smart-231c33c9-9b36-40af-b373-8b0abd234624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27447
85599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_in_err.2744785599
Directory /workspace/30.usbdev_link_in_err/latest

Test location /workspace/coverage/default/30.usbdev_link_resume.1075374464
Short name T2128
Test name
Test status
Simulation time 23394372319 ps
CPU time 25.3 seconds
Started Jul 22 06:01:01 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206812 kb
Host smart-f3855eb2-e5ea-43b2-82a1-1b3c7f722e7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10753
74464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_resume.1075374464
Directory /workspace/30.usbdev_link_resume/latest

Test location /workspace/coverage/default/30.usbdev_link_suspend.2273454389
Short name T2717
Test name
Test status
Simulation time 3296630393 ps
CPU time 4.53 seconds
Started Jul 22 06:01:14 PM PDT 24
Finished Jul 22 06:01:19 PM PDT 24
Peak memory 206816 kb
Host smart-facde319-4b30-4c1c-8802-d27ceeef082c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22734
54389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_link_suspend.2273454389
Directory /workspace/30.usbdev_link_suspend/latest

Test location /workspace/coverage/default/30.usbdev_low_speed_traffic.4250233074
Short name T1704
Test name
Test status
Simulation time 9696516122 ps
CPU time 276.93 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:05:47 PM PDT 24
Peak memory 207016 kb
Host smart-886364be-d66f-431a-8a0b-5287c6264fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
33074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_low_speed_traffic.4250233074
Directory /workspace/30.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/30.usbdev_max_inter_pkt_delay.700765132
Short name T1140
Test name
Test status
Simulation time 4960178202 ps
CPU time 136.76 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:03:27 PM PDT 24
Peak memory 206812 kb
Host smart-00ac27a3-afeb-486c-bdbb-577a4dbc4898
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=700765132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_inter_pkt_delay.700765132
Directory /workspace/30.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_max_length_in_transaction.1419981573
Short name T1208
Test name
Test status
Simulation time 246276296 ps
CPU time 0.99 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:04 PM PDT 24
Peak memory 206740 kb
Host smart-6f8ab124-272f-4bbe-befe-a01c1664fce3
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1419981573 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_in_transaction.1419981573
Directory /workspace/30.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_length_out_transaction.1130139238
Short name T668
Test name
Test status
Simulation time 201143104 ps
CPU time 0.9 seconds
Started Jul 22 06:01:14 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206748 kb
Host smart-52ca2f46-88a5-46dd-82de-4dfb114e5bcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11301
39238 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_length_out_transaction.1130139238
Directory /workspace/30.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_max_usb_traffic.128800530
Short name T1236
Test name
Test status
Simulation time 6181662446 ps
CPU time 44.42 seconds
Started Jul 22 06:01:01 PM PDT 24
Finished Jul 22 06:01:46 PM PDT 24
Peak memory 206924 kb
Host smart-5a46e38e-4936-4fff-86aa-ff391ae8b045
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12880
0530 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_max_usb_traffic.128800530
Directory /workspace/30.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/30.usbdev_min_inter_pkt_delay.3751235405
Short name T1109
Test name
Test status
Simulation time 5040589430 ps
CPU time 134.08 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:03:24 PM PDT 24
Peak memory 206900 kb
Host smart-a8bf1008-1957-4699-89c3-695e0c055b05
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3751235405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_inter_pkt_delay.3751235405
Directory /workspace/30.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/30.usbdev_min_length_in_transaction.1239031396
Short name T2313
Test name
Test status
Simulation time 149905264 ps
CPU time 0.78 seconds
Started Jul 22 06:01:17 PM PDT 24
Finished Jul 22 06:01:18 PM PDT 24
Peak memory 206748 kb
Host smart-3487740a-3339-445f-a660-598e6e8002ec
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1239031396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_in_transaction.1239031396
Directory /workspace/30.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_min_length_out_transaction.1553895173
Short name T1701
Test name
Test status
Simulation time 161679116 ps
CPU time 0.85 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:04 PM PDT 24
Peak memory 206732 kb
Host smart-d6620a0b-b17c-4930-a78f-e3aa5eca973e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
95173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_min_length_out_transaction.1553895173
Directory /workspace/30.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_nak_trans.3802322444
Short name T110
Test name
Test status
Simulation time 205698843 ps
CPU time 0.84 seconds
Started Jul 22 06:01:15 PM PDT 24
Finished Jul 22 06:01:17 PM PDT 24
Peak memory 206752 kb
Host smart-58234846-a8c0-4461-8b7b-e17cd77acb24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38023
22444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_nak_trans.3802322444
Directory /workspace/30.usbdev_nak_trans/latest

Test location /workspace/coverage/default/30.usbdev_out_iso.3380526680
Short name T2724
Test name
Test status
Simulation time 158168017 ps
CPU time 0.84 seconds
Started Jul 22 06:01:01 PM PDT 24
Finished Jul 22 06:01:03 PM PDT 24
Peak memory 206788 kb
Host smart-849dd6bd-69bc-465f-925c-eb6e1987b49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33805
26680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_iso.3380526680
Directory /workspace/30.usbdev_out_iso/latest

Test location /workspace/coverage/default/30.usbdev_out_stall.4062646262
Short name T213
Test name
Test status
Simulation time 186952497 ps
CPU time 0.92 seconds
Started Jul 22 06:01:00 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206724 kb
Host smart-64d608cd-cdb4-495e-aecf-8eebf5d2f980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40626
46262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_stall.4062646262
Directory /workspace/30.usbdev_out_stall/latest

Test location /workspace/coverage/default/30.usbdev_out_trans_nak.1440232257
Short name T1787
Test name
Test status
Simulation time 179301980 ps
CPU time 0.92 seconds
Started Jul 22 06:01:01 PM PDT 24
Finished Jul 22 06:01:03 PM PDT 24
Peak memory 206716 kb
Host smart-f54fefe2-afe6-49e1-b5f1-f30feea6c01c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14402
32257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_out_trans_nak.1440232257
Directory /workspace/30.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/30.usbdev_pending_in_trans.3423412725
Short name T611
Test name
Test status
Simulation time 155908695 ps
CPU time 0.83 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:05 PM PDT 24
Peak memory 206736 kb
Host smart-a2cbe2b0-0342-4638-af1c-977a89c02656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34234
12725 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pending_in_trans.3423412725
Directory /workspace/30.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_pinflip.3333665919
Short name T2350
Test name
Test status
Simulation time 201312099 ps
CPU time 0.94 seconds
Started Jul 22 06:01:05 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206756 kb
Host smart-74f43a5d-140d-4cb6-a3d9-32a0c2fbc48a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3333665919 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_pinflip.3333665919
Directory /workspace/30.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/30.usbdev_phy_config_usb_ref_disable.82838442
Short name T2419
Test name
Test status
Simulation time 148472838 ps
CPU time 0.86 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:04 PM PDT 24
Peak memory 206744 kb
Host smart-8449e0cb-bec3-4ff3-ac6c-21b44f153f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82838
442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_config_usb_ref_disable.82838442
Directory /workspace/30.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/30.usbdev_phy_pins_sense.1831226880
Short name T1063
Test name
Test status
Simulation time 37198606 ps
CPU time 0.65 seconds
Started Jul 22 06:01:03 PM PDT 24
Finished Jul 22 06:01:05 PM PDT 24
Peak memory 206728 kb
Host smart-0a5b20ab-025f-4e8c-b849-4b7fba261d72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18312
26880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_phy_pins_sense.1831226880
Directory /workspace/30.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/30.usbdev_pkt_buffer.1740331555
Short name T250
Test name
Test status
Simulation time 18525919268 ps
CPU time 44.26 seconds
Started Jul 22 06:00:58 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 215132 kb
Host smart-6373bcfd-c1d8-4ce8-9c33-9bae3e438b06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17403
31555 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_buffer.1740331555
Directory /workspace/30.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/30.usbdev_pkt_received.3465582160
Short name T2678
Test name
Test status
Simulation time 240805051 ps
CPU time 0.96 seconds
Started Jul 22 06:01:08 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206732 kb
Host smart-46f08345-cc5c-46f2-8b09-c90e89ed5aea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655
82160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_received.3465582160
Directory /workspace/30.usbdev_pkt_received/latest

Test location /workspace/coverage/default/30.usbdev_pkt_sent.1221454493
Short name T1089
Test name
Test status
Simulation time 278780758 ps
CPU time 1.01 seconds
Started Jul 22 06:01:01 PM PDT 24
Finished Jul 22 06:01:02 PM PDT 24
Peak memory 206740 kb
Host smart-96bdb3e1-b6d9-45a1-a27f-ea85de80e3e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12214
54493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_pkt_sent.1221454493
Directory /workspace/30.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/30.usbdev_random_length_in_transaction.2838626487
Short name T1590
Test name
Test status
Simulation time 233896687 ps
CPU time 0.86 seconds
Started Jul 22 06:01:19 PM PDT 24
Finished Jul 22 06:01:20 PM PDT 24
Peak memory 206704 kb
Host smart-f88c1d51-9e17-4ba9-b278-1a9d34ccf31c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28386
26487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_in_transaction.2838626487
Directory /workspace/30.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/30.usbdev_random_length_out_transaction.3792846395
Short name T686
Test name
Test status
Simulation time 183688537 ps
CPU time 0.79 seconds
Started Jul 22 06:01:05 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206716 kb
Host smart-651b6d54-4825-475b-b600-d98fcc63fd13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37928
46395 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_random_length_out_transaction.3792846395
Directory /workspace/30.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/30.usbdev_rx_crc_err.2788856842
Short name T2051
Test name
Test status
Simulation time 143652155 ps
CPU time 0.73 seconds
Started Jul 22 06:01:00 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206744 kb
Host smart-d851811d-a174-4e2a-8d16-199e75582d98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27888
56842 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_rx_crc_err.2788856842
Directory /workspace/30.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/30.usbdev_setup_stage.3797164235
Short name T739
Test name
Test status
Simulation time 154251067 ps
CPU time 0.76 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206744 kb
Host smart-1d8561d8-2067-4fff-abbc-4db9a9225851
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37971
64235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_stage.3797164235
Directory /workspace/30.usbdev_setup_stage/latest

Test location /workspace/coverage/default/30.usbdev_setup_trans_ignored.2768019910
Short name T2461
Test name
Test status
Simulation time 162023577 ps
CPU time 0.8 seconds
Started Jul 22 06:01:00 PM PDT 24
Finished Jul 22 06:01:02 PM PDT 24
Peak memory 206740 kb
Host smart-ea4bb15c-c63b-4f30-8686-915225fdef85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27680
19910 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_setup_trans_ignored.2768019910
Directory /workspace/30.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/30.usbdev_smoke.963454744
Short name T2038
Test name
Test status
Simulation time 228907718 ps
CPU time 0.94 seconds
Started Jul 22 06:01:02 PM PDT 24
Finished Jul 22 06:01:03 PM PDT 24
Peak memory 206748 kb
Host smart-dcf28175-7781-498c-8bfc-a108ed04ca2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96345
4744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_smoke.963454744
Directory /workspace/30.usbdev_smoke/latest

Test location /workspace/coverage/default/30.usbdev_spurious_pids_ignored.2311242005
Short name T1498
Test name
Test status
Simulation time 4742144869 ps
CPU time 33.2 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:41 PM PDT 24
Peak memory 206956 kb
Host smart-c6441501-1227-46d9-9aca-6bff1b55f154
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2311242005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_spurious_pids_ignored.2311242005
Directory /workspace/30.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/30.usbdev_stall_priority_over_nak.2187371625
Short name T1469
Test name
Test status
Simulation time 184078976 ps
CPU time 0.83 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206400 kb
Host smart-f5bf39d9-d79e-449b-9636-c071736acb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21873
71625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_priority_over_nak.2187371625
Directory /workspace/30.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/30.usbdev_stall_trans.2772217817
Short name T1483
Test name
Test status
Simulation time 163422218 ps
CPU time 0.8 seconds
Started Jul 22 06:00:58 PM PDT 24
Finished Jul 22 06:01:00 PM PDT 24
Peak memory 206704 kb
Host smart-85d0cf3c-3ed4-462a-a1fe-dc92cb1e1419
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27722
17817 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stall_trans.2772217817
Directory /workspace/30.usbdev_stall_trans/latest

Test location /workspace/coverage/default/30.usbdev_stream_len_max.3701701137
Short name T2476
Test name
Test status
Simulation time 946051828 ps
CPU time 2.15 seconds
Started Jul 22 06:00:58 PM PDT 24
Finished Jul 22 06:01:01 PM PDT 24
Peak memory 206772 kb
Host smart-61cf4a35-3bf5-4c40-b3dc-6e30fc654118
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37017
01137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_stream_len_max.3701701137
Directory /workspace/30.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/30.usbdev_streaming_out.1308173374
Short name T2662
Test name
Test status
Simulation time 4678653860 ps
CPU time 44.37 seconds
Started Jul 22 06:01:08 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206900 kb
Host smart-776bda92-5ec9-4484-b246-b3a6b2faab16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13081
73374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.usbdev_streaming_out.1308173374
Directory /workspace/30.usbdev_streaming_out/latest

Test location /workspace/coverage/default/31.usbdev_alert_test.1147234511
Short name T2696
Test name
Test status
Simulation time 38353692 ps
CPU time 0.72 seconds
Started Jul 22 06:01:15 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206724 kb
Host smart-3ef5b7b8-758b-4f58-912e-168497510b14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1147234511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_alert_test.1147234511
Directory /workspace/31.usbdev_alert_test/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_disconnect.3333924275
Short name T2311
Test name
Test status
Simulation time 3780690534 ps
CPU time 4.8 seconds
Started Jul 22 06:00:58 PM PDT 24
Finished Jul 22 06:01:04 PM PDT 24
Peak memory 206864 kb
Host smart-e3f11a5e-8d35-4c6f-8ec4-75fb7037853e
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3333924275 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_disconnect.3333924275
Directory /workspace/31.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_reset.175680187
Short name T15
Test name
Test status
Simulation time 13494802954 ps
CPU time 13.38 seconds
Started Jul 22 06:01:05 PM PDT 24
Finished Jul 22 06:01:19 PM PDT 24
Peak memory 206944 kb
Host smart-8798dfa7-b6dd-48ab-b060-595723f96646
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=175680187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_reset.175680187
Directory /workspace/31.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/31.usbdev_aon_wake_resume.2090847818
Short name T8
Test name
Test status
Simulation time 23405173262 ps
CPU time 24.3 seconds
Started Jul 22 06:00:59 PM PDT 24
Finished Jul 22 06:01:24 PM PDT 24
Peak memory 206808 kb
Host smart-ae1faa2b-7959-4546-94f8-3a0996026e01
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2090847818 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_aon_wake_resume.2090847818
Directory /workspace/31.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/31.usbdev_av_buffer.4253232232
Short name T1281
Test name
Test status
Simulation time 173815578 ps
CPU time 0.8 seconds
Started Jul 22 06:01:02 PM PDT 24
Finished Jul 22 06:01:03 PM PDT 24
Peak memory 206704 kb
Host smart-f409a2b8-87ab-496b-9c2a-fc09daaf7c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42532
32232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_av_buffer.4253232232
Directory /workspace/31.usbdev_av_buffer/latest

Test location /workspace/coverage/default/31.usbdev_bitstuff_err.1085414938
Short name T1564
Test name
Test status
Simulation time 166207167 ps
CPU time 0.79 seconds
Started Jul 22 06:01:05 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206720 kb
Host smart-9d842354-a90d-4852-989c-315cb7e38841
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10854
14938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_bitstuff_err.1085414938
Directory /workspace/31.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_clear.3228957228
Short name T1949
Test name
Test status
Simulation time 542466389 ps
CPU time 1.49 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206724 kb
Host smart-9932e1cb-083e-435c-8a1d-751b51554556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32289
57228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_clear.3228957228
Directory /workspace/31.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/31.usbdev_data_toggle_restore.257147783
Short name T1698
Test name
Test status
Simulation time 1210900234 ps
CPU time 2.62 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206448 kb
Host smart-c1804181-39f5-40e8-b413-f34a5a388f89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25714
7783 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_data_toggle_restore.257147783
Directory /workspace/31.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/31.usbdev_device_address.79677526
Short name T2146
Test name
Test status
Simulation time 8132768422 ps
CPU time 17.32 seconds
Started Jul 22 06:01:19 PM PDT 24
Finished Jul 22 06:01:37 PM PDT 24
Peak memory 206896 kb
Host smart-3e91856a-afc0-486c-b18f-dfd37394a7b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79677
526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_device_address.79677526
Directory /workspace/31.usbdev_device_address/latest

Test location /workspace/coverage/default/31.usbdev_disable_endpoint.3787272072
Short name T1338
Test name
Test status
Simulation time 433355800 ps
CPU time 1.36 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206352 kb
Host smart-24b8c0cc-085a-4096-905f-a11d2b9effb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37872
72072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disable_endpoint.3787272072
Directory /workspace/31.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/31.usbdev_disconnected.2346498113
Short name T2609
Test name
Test status
Simulation time 141310158 ps
CPU time 0.72 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206756 kb
Host smart-f1e781fe-d5c5-46e0-a487-0d9f9dc4262f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23464
98113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_disconnected.2346498113
Directory /workspace/31.usbdev_disconnected/latest

Test location /workspace/coverage/default/31.usbdev_enable.1340694027
Short name T418
Test name
Test status
Simulation time 37816266 ps
CPU time 0.69 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206652 kb
Host smart-1c697945-f815-448b-82a5-298462b01b30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13406
94027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_enable.1340694027
Directory /workspace/31.usbdev_enable/latest

Test location /workspace/coverage/default/31.usbdev_endpoint_access.2203671558
Short name T2335
Test name
Test status
Simulation time 894824837 ps
CPU time 2.03 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206796 kb
Host smart-f9ee8378-f00c-496e-9a49-6ef35b980996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22036
71558 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_endpoint_access.2203671558
Directory /workspace/31.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/31.usbdev_fifo_rst.3990493340
Short name T2151
Test name
Test status
Simulation time 310182359 ps
CPU time 2.08 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206800 kb
Host smart-80bd9865-224e-4500-9dbf-2dd85ec630e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39904
93340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_fifo_rst.3990493340
Directory /workspace/31.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/31.usbdev_in_iso.4138595168
Short name T2049
Test name
Test status
Simulation time 167262783 ps
CPU time 0.78 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206744 kb
Host smart-4c60a97b-2c17-4b36-ab9a-d76fa3645d1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41385
95168 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_iso.4138595168
Directory /workspace/31.usbdev_in_iso/latest

Test location /workspace/coverage/default/31.usbdev_in_stall.2082719227
Short name T2237
Test name
Test status
Simulation time 145060940 ps
CPU time 0.75 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206752 kb
Host smart-a468a026-da74-4106-bc47-5d40db46a2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20827
19227 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_stall.2082719227
Directory /workspace/31.usbdev_in_stall/latest

Test location /workspace/coverage/default/31.usbdev_in_trans.3220050094
Short name T1935
Test name
Test status
Simulation time 211935073 ps
CPU time 0.95 seconds
Started Jul 22 06:01:28 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206752 kb
Host smart-33fd76fd-5ace-4583-8446-f88333332368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32200
50094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_in_trans.3220050094
Directory /workspace/31.usbdev_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_iso_retraction.2984353636
Short name T538
Test name
Test status
Simulation time 4252245937 ps
CPU time 16.46 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:24 PM PDT 24
Peak memory 206964 kb
Host smart-3c7d634a-3510-422d-8b8e-801bcf2b1e04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29843
53636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_iso_retraction.2984353636
Directory /workspace/31.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/31.usbdev_link_in_err.2673090523
Short name T1278
Test name
Test status
Simulation time 253535571 ps
CPU time 0.92 seconds
Started Jul 22 06:01:08 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206788 kb
Host smart-0fad2d04-4649-45b1-80c4-5d9fb5becb88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26730
90523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_in_err.2673090523
Directory /workspace/31.usbdev_link_in_err/latest

Test location /workspace/coverage/default/31.usbdev_link_resume.1724866043
Short name T1738
Test name
Test status
Simulation time 23334419264 ps
CPU time 28.18 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:36 PM PDT 24
Peak memory 206452 kb
Host smart-f6627387-7871-4d35-99d2-928a2e5dc770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17248
66043 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_resume.1724866043
Directory /workspace/31.usbdev_link_resume/latest

Test location /workspace/coverage/default/31.usbdev_link_suspend.4090249409
Short name T1851
Test name
Test status
Simulation time 3367703149 ps
CPU time 4.35 seconds
Started Jul 22 06:01:01 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206852 kb
Host smart-5eb6b5be-0a46-419a-b91b-09217d17254b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40902
49409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_link_suspend.4090249409
Directory /workspace/31.usbdev_link_suspend/latest

Test location /workspace/coverage/default/31.usbdev_low_speed_traffic.2653914584
Short name T1276
Test name
Test status
Simulation time 8248334917 ps
CPU time 79.24 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206972 kb
Host smart-d080065b-10e2-46fd-82fd-c84b3cfb1a00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26539
14584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_low_speed_traffic.2653914584
Directory /workspace/31.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/31.usbdev_max_inter_pkt_delay.438042309
Short name T675
Test name
Test status
Simulation time 6448894734 ps
CPU time 47.72 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206896 kb
Host smart-71e82717-6a90-4dcf-8e45-1a9ac676d00b
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=438042309 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_inter_pkt_delay.438042309
Directory /workspace/31.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_max_length_in_transaction.402562824
Short name T2405
Test name
Test status
Simulation time 293157512 ps
CPU time 0.98 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206748 kb
Host smart-4b2e3247-5924-4c18-9806-3a720df967a9
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=402562824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_in_transaction.402562824
Directory /workspace/31.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_length_out_transaction.2258505285
Short name T1803
Test name
Test status
Simulation time 195935928 ps
CPU time 0.91 seconds
Started Jul 22 06:01:11 PM PDT 24
Finished Jul 22 06:01:13 PM PDT 24
Peak memory 206732 kb
Host smart-7badafcc-ec9a-4397-bf1b-31dac1e25fc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22585
05285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_length_out_transaction.2258505285
Directory /workspace/31.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_max_usb_traffic.3916631304
Short name T1022
Test name
Test status
Simulation time 4174344386 ps
CPU time 119.81 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206864 kb
Host smart-db33f134-b2ff-415d-98d7-70cfc7d45a8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39166
31304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_max_usb_traffic.3916631304
Directory /workspace/31.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/31.usbdev_min_inter_pkt_delay.827773076
Short name T1175
Test name
Test status
Simulation time 5123554541 ps
CPU time 139 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206988 kb
Host smart-27cb8205-e494-4925-8fae-eec4fa7ecdde
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=827773076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_inter_pkt_delay.827773076
Directory /workspace/31.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/31.usbdev_min_length_in_transaction.697124965
Short name T1410
Test name
Test status
Simulation time 172721639 ps
CPU time 0.8 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206632 kb
Host smart-ec85d851-159d-4750-b557-376843974676
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=697124965 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_in_transaction.697124965
Directory /workspace/31.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_min_length_out_transaction.1458479587
Short name T397
Test name
Test status
Simulation time 161006341 ps
CPU time 0.78 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:08 PM PDT 24
Peak memory 206752 kb
Host smart-c550953f-6ffb-4d8a-b1f6-35247245df52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14584
79587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_min_length_out_transaction.1458479587
Directory /workspace/31.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_nak_trans.550373800
Short name T124
Test name
Test status
Simulation time 229716216 ps
CPU time 0.9 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206708 kb
Host smart-deee38ec-53a1-4561-bb6f-f10120007ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55037
3800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_nak_trans.550373800
Directory /workspace/31.usbdev_nak_trans/latest

Test location /workspace/coverage/default/31.usbdev_out_iso.2958035894
Short name T1120
Test name
Test status
Simulation time 186626450 ps
CPU time 0.88 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:08 PM PDT 24
Peak memory 206752 kb
Host smart-2a8cc9a6-3ead-4c72-a521-d61a9cd72291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29580
35894 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_iso.2958035894
Directory /workspace/31.usbdev_out_iso/latest

Test location /workspace/coverage/default/31.usbdev_out_stall.890184111
Short name T952
Test name
Test status
Simulation time 210861836 ps
CPU time 0.84 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:08 PM PDT 24
Peak memory 206696 kb
Host smart-da47dc21-8bc1-40eb-a656-e09b11022481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89018
4111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_stall.890184111
Directory /workspace/31.usbdev_out_stall/latest

Test location /workspace/coverage/default/31.usbdev_out_trans_nak.2481685764
Short name T1110
Test name
Test status
Simulation time 173790430 ps
CPU time 0.82 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:11 PM PDT 24
Peak memory 206752 kb
Host smart-e5338519-af61-44ff-8d78-15089a1dd602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24816
85764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_out_trans_nak.2481685764
Directory /workspace/31.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/31.usbdev_pending_in_trans.1402570771
Short name T1769
Test name
Test status
Simulation time 154311610 ps
CPU time 0.77 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:11 PM PDT 24
Peak memory 206692 kb
Host smart-79679d69-2745-43d0-ba70-a9df787d8956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14025
70771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pending_in_trans.1402570771
Directory /workspace/31.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_pinflip.284907326
Short name T1481
Test name
Test status
Simulation time 215855373 ps
CPU time 0.88 seconds
Started Jul 22 06:01:04 PM PDT 24
Finished Jul 22 06:01:05 PM PDT 24
Peak memory 206704 kb
Host smart-34e38651-bbef-418d-ae6e-82aef8475787
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=284907326 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_pinflip.284907326
Directory /workspace/31.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/31.usbdev_phy_config_usb_ref_disable.3058375864
Short name T968
Test name
Test status
Simulation time 190554937 ps
CPU time 0.78 seconds
Started Jul 22 06:01:18 PM PDT 24
Finished Jul 22 06:01:19 PM PDT 24
Peak memory 206744 kb
Host smart-edf2bd43-7c07-4795-8ae9-7f52813f005c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30583
75864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_config_usb_ref_disable.3058375864
Directory /workspace/31.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/31.usbdev_phy_pins_sense.1467174321
Short name T721
Test name
Test status
Simulation time 46778821 ps
CPU time 0.66 seconds
Started Jul 22 06:01:36 PM PDT 24
Finished Jul 22 06:01:37 PM PDT 24
Peak memory 206728 kb
Host smart-387d79c9-2a83-4a4b-a315-d5bf744d1317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14671
74321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_phy_pins_sense.1467174321
Directory /workspace/31.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/31.usbdev_pkt_buffer.160910007
Short name T1088
Test name
Test status
Simulation time 10105767464 ps
CPU time 24.21 seconds
Started Jul 22 06:01:31 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206920 kb
Host smart-412ad129-48b4-4682-83d5-96cb545bfe94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16091
0007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_buffer.160910007
Directory /workspace/31.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/31.usbdev_pkt_received.2052226098
Short name T2027
Test name
Test status
Simulation time 180419512 ps
CPU time 0.91 seconds
Started Jul 22 06:01:13 PM PDT 24
Finished Jul 22 06:01:15 PM PDT 24
Peak memory 206712 kb
Host smart-56865be0-d586-4ce8-8fb2-ac584f887623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20522
26098 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_received.2052226098
Directory /workspace/31.usbdev_pkt_received/latest

Test location /workspace/coverage/default/31.usbdev_pkt_sent.2635199444
Short name T2552
Test name
Test status
Simulation time 226323058 ps
CPU time 0.84 seconds
Started Jul 22 06:02:13 PM PDT 24
Finished Jul 22 06:02:15 PM PDT 24
Peak memory 206744 kb
Host smart-eb821a47-9694-4657-b97e-be643c33164a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26351
99444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_pkt_sent.2635199444
Directory /workspace/31.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/31.usbdev_random_length_in_transaction.2890826833
Short name T2747
Test name
Test status
Simulation time 261233329 ps
CPU time 0.95 seconds
Started Jul 22 06:01:15 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206744 kb
Host smart-27360a10-a67c-4e0b-bb97-250286609021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28908
26833 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_in_transaction.2890826833
Directory /workspace/31.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/31.usbdev_random_length_out_transaction.3320275694
Short name T500
Test name
Test status
Simulation time 213988801 ps
CPU time 0.83 seconds
Started Jul 22 06:02:50 PM PDT 24
Finished Jul 22 06:02:51 PM PDT 24
Peak memory 206680 kb
Host smart-5c81b227-c647-43e4-bcc0-37e1c90bd628
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33202
75694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_random_length_out_transaction.3320275694
Directory /workspace/31.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/31.usbdev_rx_crc_err.3658868244
Short name T734
Test name
Test status
Simulation time 147992536 ps
CPU time 0.79 seconds
Started Jul 22 06:01:14 PM PDT 24
Finished Jul 22 06:01:15 PM PDT 24
Peak memory 206744 kb
Host smart-fb8cfcf8-335e-483e-bafe-9b5646ccf12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36588
68244 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_rx_crc_err.3658868244
Directory /workspace/31.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/31.usbdev_setup_stage.4068093874
Short name T943
Test name
Test status
Simulation time 151608834 ps
CPU time 0.79 seconds
Started Jul 22 06:01:05 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206740 kb
Host smart-5336592c-6568-4ed2-ba67-6a75dd42b26a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40680
93874 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_stage.4068093874
Directory /workspace/31.usbdev_setup_stage/latest

Test location /workspace/coverage/default/31.usbdev_setup_trans_ignored.4268876710
Short name T1163
Test name
Test status
Simulation time 148993276 ps
CPU time 0.74 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206748 kb
Host smart-a45ccc7c-bf80-40ea-86e6-72095655e650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42688
76710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_setup_trans_ignored.4268876710
Directory /workspace/31.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/31.usbdev_smoke.3738889290
Short name T1263
Test name
Test status
Simulation time 240197918 ps
CPU time 0.95 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:13 PM PDT 24
Peak memory 206640 kb
Host smart-5cb0a44b-3469-4d56-a3ce-40bae43e16eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37388
89290 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_smoke.3738889290
Directory /workspace/31.usbdev_smoke/latest

Test location /workspace/coverage/default/31.usbdev_spurious_pids_ignored.4193679604
Short name T1948
Test name
Test status
Simulation time 3414456367 ps
CPU time 96.44 seconds
Started Jul 22 06:01:31 PM PDT 24
Finished Jul 22 06:03:08 PM PDT 24
Peak memory 206908 kb
Host smart-6cdd26b9-fe0e-48c0-8263-d87095cf747b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4193679604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_spurious_pids_ignored.4193679604
Directory /workspace/31.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/31.usbdev_stall_priority_over_nak.477397753
Short name T1510
Test name
Test status
Simulation time 179667051 ps
CPU time 0.81 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206656 kb
Host smart-cf367d31-40e3-45ad-a0a3-e12ba770dc21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47739
7753 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_priority_over_nak.477397753
Directory /workspace/31.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/31.usbdev_stall_trans.3489594667
Short name T335
Test name
Test status
Simulation time 170012702 ps
CPU time 0.78 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 206632 kb
Host smart-4335e499-20ca-4dc3-bfaa-52744d9a6831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34895
94667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stall_trans.3489594667
Directory /workspace/31.usbdev_stall_trans/latest

Test location /workspace/coverage/default/31.usbdev_stream_len_max.493924556
Short name T2428
Test name
Test status
Simulation time 520113927 ps
CPU time 1.45 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206692 kb
Host smart-a6bdd5fd-561e-4970-9f36-788e1713d063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49392
4556 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_stream_len_max.493924556
Directory /workspace/31.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/31.usbdev_streaming_out.1752064035
Short name T2650
Test name
Test status
Simulation time 5734696285 ps
CPU time 59.2 seconds
Started Jul 22 06:01:08 PM PDT 24
Finished Jul 22 06:02:09 PM PDT 24
Peak memory 206900 kb
Host smart-73c46c22-d26a-4523-bcbd-dcae6262ed8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17520
64035 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.usbdev_streaming_out.1752064035
Directory /workspace/31.usbdev_streaming_out/latest

Test location /workspace/coverage/default/32.usbdev_alert_test.4035191643
Short name T2594
Test name
Test status
Simulation time 48734361 ps
CPU time 0.67 seconds
Started Jul 22 06:01:15 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206692 kb
Host smart-7a1264b3-67ae-47cb-a3c6-548d5d5c2748
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4035191643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_alert_test.4035191643
Directory /workspace/32.usbdev_alert_test/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_disconnect.2399060058
Short name T981
Test name
Test status
Simulation time 4211043592 ps
CPU time 4.49 seconds
Started Jul 22 06:02:46 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206764 kb
Host smart-a208279d-9d9c-4241-bff4-6c349cd86114
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2399060058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_disconnect.2399060058
Directory /workspace/32.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_reset.3139654384
Short name T2544
Test name
Test status
Simulation time 13371645748 ps
CPU time 13.08 seconds
Started Jul 22 06:02:52 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206884 kb
Host smart-823ba010-b881-4782-a095-be3120740b1e
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3139654384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_reset.3139654384
Directory /workspace/32.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/32.usbdev_aon_wake_resume.3034690485
Short name T773
Test name
Test status
Simulation time 23396843973 ps
CPU time 25.03 seconds
Started Jul 22 06:01:16 PM PDT 24
Finished Jul 22 06:01:42 PM PDT 24
Peak memory 206816 kb
Host smart-810a04eb-a118-4d8b-9eb2-081af7b239c5
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3034690485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_aon_wake_resume.3034690485
Directory /workspace/32.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/32.usbdev_av_buffer.2463502126
Short name T1369
Test name
Test status
Simulation time 151958675 ps
CPU time 0.8 seconds
Started Jul 22 06:03:10 PM PDT 24
Finished Jul 22 06:03:12 PM PDT 24
Peak memory 206684 kb
Host smart-6142ad50-b8f5-4503-b6dd-06696b2face4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24635
02126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_av_buffer.2463502126
Directory /workspace/32.usbdev_av_buffer/latest

Test location /workspace/coverage/default/32.usbdev_bitstuff_err.674070863
Short name T2297
Test name
Test status
Simulation time 189933618 ps
CPU time 0.83 seconds
Started Jul 22 06:01:40 PM PDT 24
Finished Jul 22 06:01:41 PM PDT 24
Peak memory 206744 kb
Host smart-1d14c7da-9854-47d2-81ae-404779b89072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67407
0863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_bitstuff_err.674070863
Directory /workspace/32.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_clear.3710009837
Short name T984
Test name
Test status
Simulation time 370425482 ps
CPU time 1.24 seconds
Started Jul 22 06:01:15 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206744 kb
Host smart-f69be082-ef89-4f18-82ec-de771ecaeb64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37100
09837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_clear.3710009837
Directory /workspace/32.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/32.usbdev_data_toggle_restore.2295620425
Short name T105
Test name
Test status
Simulation time 430696530 ps
CPU time 1.25 seconds
Started Jul 22 06:01:08 PM PDT 24
Finished Jul 22 06:01:10 PM PDT 24
Peak memory 206712 kb
Host smart-7df29153-7ed9-4375-a4f9-21eb2e632ec7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
20425 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_data_toggle_restore.2295620425
Directory /workspace/32.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/32.usbdev_device_address.270462081
Short name T1451
Test name
Test status
Simulation time 15675822632 ps
CPU time 30.31 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:37 PM PDT 24
Peak memory 206888 kb
Host smart-9c201dc8-81ca-46db-aaef-9239f47d4698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27046
2081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_device_address.270462081
Directory /workspace/32.usbdev_device_address/latest

Test location /workspace/coverage/default/32.usbdev_disable_endpoint.1540613884
Short name T1241
Test name
Test status
Simulation time 310240196 ps
CPU time 1.14 seconds
Started Jul 22 06:01:20 PM PDT 24
Finished Jul 22 06:01:22 PM PDT 24
Peak memory 206748 kb
Host smart-32406ca5-704c-4ecd-bae3-379e468f02e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15406
13884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disable_endpoint.1540613884
Directory /workspace/32.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/32.usbdev_disconnected.551833535
Short name T681
Test name
Test status
Simulation time 148635946 ps
CPU time 0.75 seconds
Started Jul 22 06:01:16 PM PDT 24
Finished Jul 22 06:01:18 PM PDT 24
Peak memory 206748 kb
Host smart-4d622adb-1a2c-4123-9f5f-c7fa73778067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55183
3535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_disconnected.551833535
Directory /workspace/32.usbdev_disconnected/latest

Test location /workspace/coverage/default/32.usbdev_enable.3341329032
Short name T2659
Test name
Test status
Simulation time 43283015 ps
CPU time 0.66 seconds
Started Jul 22 06:01:17 PM PDT 24
Finished Jul 22 06:01:18 PM PDT 24
Peak memory 206740 kb
Host smart-3b5b16b4-195b-4dea-9809-1493d66461a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33413
29032 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_enable.3341329032
Directory /workspace/32.usbdev_enable/latest

Test location /workspace/coverage/default/32.usbdev_endpoint_access.2229840771
Short name T596
Test name
Test status
Simulation time 1060580037 ps
CPU time 2.58 seconds
Started Jul 22 06:01:13 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206840 kb
Host smart-9d0ba540-7c9b-420d-969a-31e10765bc12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22298
40771 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_endpoint_access.2229840771
Directory /workspace/32.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/32.usbdev_fifo_rst.3229214422
Short name T816
Test name
Test status
Simulation time 267491604 ps
CPU time 1.29 seconds
Started Jul 22 06:01:37 PM PDT 24
Finished Jul 22 06:01:38 PM PDT 24
Peak memory 206896 kb
Host smart-4eede066-2c5b-483c-ad50-94e7eea29b7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32292
14422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_fifo_rst.3229214422
Directory /workspace/32.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/32.usbdev_in_iso.1531516367
Short name T2510
Test name
Test status
Simulation time 169374558 ps
CPU time 0.89 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206704 kb
Host smart-f5a19b45-a6d0-48fb-b325-d6baf95213ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15315
16367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_iso.1531516367
Directory /workspace/32.usbdev_in_iso/latest

Test location /workspace/coverage/default/32.usbdev_in_stall.3063584724
Short name T1463
Test name
Test status
Simulation time 147134222 ps
CPU time 0.77 seconds
Started Jul 22 06:01:17 PM PDT 24
Finished Jul 22 06:01:18 PM PDT 24
Peak memory 206744 kb
Host smart-eb1377a8-1aa9-4f6f-9a01-a0bf4adaaf63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30635
84724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_stall.3063584724
Directory /workspace/32.usbdev_in_stall/latest

Test location /workspace/coverage/default/32.usbdev_in_trans.2180998802
Short name T1734
Test name
Test status
Simulation time 263299194 ps
CPU time 0.97 seconds
Started Jul 22 06:01:07 PM PDT 24
Finished Jul 22 06:01:09 PM PDT 24
Peak memory 206744 kb
Host smart-95310bf4-1dee-46bf-9f97-b3bc4ce1b0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21809
98802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_in_trans.2180998802
Directory /workspace/32.usbdev_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_invalid_sync.825830075
Short name T400
Test name
Test status
Simulation time 9169302606 ps
CPU time 68.05 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:02:15 PM PDT 24
Peak memory 206956 kb
Host smart-29097962-9423-4984-a191-192bd30fc9de
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=825830075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_invalid_sync.825830075
Directory /workspace/32.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/32.usbdev_iso_retraction.111632379
Short name T830
Test name
Test status
Simulation time 6729351866 ps
CPU time 55.85 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:02:07 PM PDT 24
Peak memory 206904 kb
Host smart-90131460-a423-4cea-8fd4-c85105e6b935
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11163
2379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_iso_retraction.111632379
Directory /workspace/32.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/32.usbdev_link_in_err.1217346053
Short name T1455
Test name
Test status
Simulation time 193493625 ps
CPU time 0.86 seconds
Started Jul 22 06:03:10 PM PDT 24
Finished Jul 22 06:03:12 PM PDT 24
Peak memory 206680 kb
Host smart-87d05caf-b235-4528-9aed-ac23478f52ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12173
46053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_in_err.1217346053
Directory /workspace/32.usbdev_link_in_err/latest

Test location /workspace/coverage/default/32.usbdev_link_resume.1952998209
Short name T2009
Test name
Test status
Simulation time 23291786385 ps
CPU time 26.45 seconds
Started Jul 22 06:03:10 PM PDT 24
Finished Jul 22 06:03:38 PM PDT 24
Peak memory 206728 kb
Host smart-88813086-616e-4e0e-94d3-fa89f157ab56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19529
98209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_resume.1952998209
Directory /workspace/32.usbdev_link_resume/latest

Test location /workspace/coverage/default/32.usbdev_link_suspend.1231885784
Short name T2556
Test name
Test status
Simulation time 3349106290 ps
CPU time 3.57 seconds
Started Jul 22 06:01:17 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206808 kb
Host smart-0f5e05aa-d772-4fe0-ab2b-23f7763d3150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12318
85784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_link_suspend.1231885784
Directory /workspace/32.usbdev_link_suspend/latest

Test location /workspace/coverage/default/32.usbdev_low_speed_traffic.1023533717
Short name T379
Test name
Test status
Simulation time 9680580397 ps
CPU time 66.5 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:02:17 PM PDT 24
Peak memory 206920 kb
Host smart-1b2a9973-15c6-41df-807d-6b91691d824b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10235
33717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_low_speed_traffic.1023533717
Directory /workspace/32.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/32.usbdev_max_inter_pkt_delay.1157052012
Short name T2249
Test name
Test status
Simulation time 5872688716 ps
CPU time 161.51 seconds
Started Jul 22 06:03:10 PM PDT 24
Finished Jul 22 06:05:53 PM PDT 24
Peak memory 206824 kb
Host smart-83b7d2ea-33e7-43d4-aa18-17d2dccf95d1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1157052012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_inter_pkt_delay.1157052012
Directory /workspace/32.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_max_length_in_transaction.1403150970
Short name T2429
Test name
Test status
Simulation time 262376666 ps
CPU time 1.04 seconds
Started Jul 22 06:01:10 PM PDT 24
Finished Jul 22 06:01:12 PM PDT 24
Peak memory 206672 kb
Host smart-f5792221-6d70-48d0-a4c7-cc10ac4ce718
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1403150970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_in_transaction.1403150970
Directory /workspace/32.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_length_out_transaction.3296906674
Short name T2661
Test name
Test status
Simulation time 195712891 ps
CPU time 0.84 seconds
Started Jul 22 06:01:06 PM PDT 24
Finished Jul 22 06:01:08 PM PDT 24
Peak memory 206728 kb
Host smart-6a23ce84-ffab-4a38-ad8b-c5701aab0a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32969
06674 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_length_out_transaction.3296906674
Directory /workspace/32.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_max_usb_traffic.1526126769
Short name T1117
Test name
Test status
Simulation time 4326455959 ps
CPU time 40.29 seconds
Started Jul 22 06:01:09 PM PDT 24
Finished Jul 22 06:01:50 PM PDT 24
Peak memory 206952 kb
Host smart-3df43e8b-6751-4d8e-ad11-9040cb556adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15261
26769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_max_usb_traffic.1526126769
Directory /workspace/32.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/32.usbdev_min_inter_pkt_delay.1695103229
Short name T1209
Test name
Test status
Simulation time 7973963465 ps
CPU time 74.37 seconds
Started Jul 22 06:01:11 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206868 kb
Host smart-df55e110-6385-4337-a65f-d98d0573be4c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1695103229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_inter_pkt_delay.1695103229
Directory /workspace/32.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/32.usbdev_min_length_in_transaction.3592025402
Short name T1196
Test name
Test status
Simulation time 159704083 ps
CPU time 0.83 seconds
Started Jul 22 06:01:12 PM PDT 24
Finished Jul 22 06:01:14 PM PDT 24
Peak memory 206768 kb
Host smart-2aa685cc-23a6-4571-9df7-965cf7d40f67
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3592025402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_in_transaction.3592025402
Directory /workspace/32.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_min_length_out_transaction.3134474417
Short name T677
Test name
Test status
Simulation time 159380137 ps
CPU time 0.81 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:28 PM PDT 24
Peak memory 206744 kb
Host smart-13c00cc2-5b1c-49b6-8d9b-73d71a44754a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31344
74417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_min_length_out_transaction.3134474417
Directory /workspace/32.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_nak_trans.4151584381
Short name T2356
Test name
Test status
Simulation time 252556266 ps
CPU time 0.92 seconds
Started Jul 22 06:02:47 PM PDT 24
Finished Jul 22 06:02:49 PM PDT 24
Peak memory 206736 kb
Host smart-ad5784e9-6f40-45bc-9f08-aee4a0984ab4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41515
84381 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_nak_trans.4151584381
Directory /workspace/32.usbdev_nak_trans/latest

Test location /workspace/coverage/default/32.usbdev_out_iso.3456030948
Short name T945
Test name
Test status
Simulation time 162202106 ps
CPU time 0.78 seconds
Started Jul 22 06:01:20 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206752 kb
Host smart-08b29cb0-0877-4368-9b16-8ea590985eef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34560
30948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_iso.3456030948
Directory /workspace/32.usbdev_out_iso/latest

Test location /workspace/coverage/default/32.usbdev_out_stall.2416544441
Short name T548
Test name
Test status
Simulation time 226755365 ps
CPU time 0.86 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206728 kb
Host smart-e1517d21-0a6c-4a22-9d50-474508533453
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24165
44441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_stall.2416544441
Directory /workspace/32.usbdev_out_stall/latest

Test location /workspace/coverage/default/32.usbdev_out_trans_nak.806449554
Short name T394
Test name
Test status
Simulation time 175720601 ps
CPU time 0.79 seconds
Started Jul 22 06:01:12 PM PDT 24
Finished Jul 22 06:01:14 PM PDT 24
Peak memory 206752 kb
Host smart-47e55563-57f5-4bae-93e3-ac39fe5a4bc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80644
9554 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_out_trans_nak.806449554
Directory /workspace/32.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/32.usbdev_pending_in_trans.3269207313
Short name T166
Test name
Test status
Simulation time 155198267 ps
CPU time 0.8 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206748 kb
Host smart-2b786657-2dd0-4096-9504-04e24d885d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32692
07313 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pending_in_trans.3269207313
Directory /workspace/32.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_pinflip.175210523
Short name T1043
Test name
Test status
Simulation time 199135345 ps
CPU time 0.95 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206720 kb
Host smart-5da066ae-2596-4e81-9886-4c7b14ad4c64
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=175210523 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_pinflip.175210523
Directory /workspace/32.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/32.usbdev_phy_config_usb_ref_disable.3494701650
Short name T597
Test name
Test status
Simulation time 145665473 ps
CPU time 0.79 seconds
Started Jul 22 06:01:29 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206744 kb
Host smart-7261b0b5-e482-40ac-abb8-eb0bee961a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34947
01650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_config_usb_ref_disable.3494701650
Directory /workspace/32.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/32.usbdev_phy_pins_sense.1612221208
Short name T2660
Test name
Test status
Simulation time 42445205 ps
CPU time 0.67 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206744 kb
Host smart-d3dc8302-39e6-4546-acd0-30308fa7a16d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16122
21208 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_phy_pins_sense.1612221208
Directory /workspace/32.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/32.usbdev_pkt_buffer.2044628495
Short name T2396
Test name
Test status
Simulation time 15427302461 ps
CPU time 35.39 seconds
Started Jul 22 06:01:16 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206988 kb
Host smart-5e7f67d3-7656-4c06-8d07-6793d2a23007
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20446
28495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_buffer.2044628495
Directory /workspace/32.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/32.usbdev_pkt_received.1343412061
Short name T2315
Test name
Test status
Simulation time 155106925 ps
CPU time 0.82 seconds
Started Jul 22 06:01:13 PM PDT 24
Finished Jul 22 06:01:15 PM PDT 24
Peak memory 206904 kb
Host smart-edeeb088-f22d-40f4-8574-12124ad89cfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13434
12061 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_received.1343412061
Directory /workspace/32.usbdev_pkt_received/latest

Test location /workspace/coverage/default/32.usbdev_pkt_sent.3346629534
Short name T2111
Test name
Test status
Simulation time 237518267 ps
CPU time 0.92 seconds
Started Jul 22 06:01:15 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206732 kb
Host smart-51f662fb-ab3a-40a3-a7ef-8ce8fced574f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33466
29534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_pkt_sent.3346629534
Directory /workspace/32.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/32.usbdev_random_length_in_transaction.619369250
Short name T822
Test name
Test status
Simulation time 206166440 ps
CPU time 0.9 seconds
Started Jul 22 06:01:16 PM PDT 24
Finished Jul 22 06:01:18 PM PDT 24
Peak memory 206744 kb
Host smart-200e44e5-a594-45ef-999f-5058e926127a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61936
9250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_in_transaction.619369250
Directory /workspace/32.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/32.usbdev_random_length_out_transaction.1130964074
Short name T2362
Test name
Test status
Simulation time 231340632 ps
CPU time 0.88 seconds
Started Jul 22 06:01:20 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206724 kb
Host smart-7b33948a-7e7c-44af-8edd-e377a59a253d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11309
64074 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_random_length_out_transaction.1130964074
Directory /workspace/32.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/32.usbdev_rx_crc_err.1724145194
Short name T57
Test name
Test status
Simulation time 133393312 ps
CPU time 0.77 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 206720 kb
Host smart-249f5d2d-1262-424f-926c-cfe6720f71a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17241
45194 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_rx_crc_err.1724145194
Directory /workspace/32.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/32.usbdev_setup_stage.738976422
Short name T1096
Test name
Test status
Simulation time 150446906 ps
CPU time 0.75 seconds
Started Jul 22 06:01:18 PM PDT 24
Finished Jul 22 06:01:19 PM PDT 24
Peak memory 206752 kb
Host smart-c80abf1b-5d8a-4dbc-a8ee-1c9dac7231f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73897
6422 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_stage.738976422
Directory /workspace/32.usbdev_setup_stage/latest

Test location /workspace/coverage/default/32.usbdev_setup_trans_ignored.1960635489
Short name T2566
Test name
Test status
Simulation time 150074748 ps
CPU time 0.77 seconds
Started Jul 22 06:02:33 PM PDT 24
Finished Jul 22 06:02:34 PM PDT 24
Peak memory 206536 kb
Host smart-392cd714-16e7-47bd-8e47-d371d32ca994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19606
35489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_setup_trans_ignored.1960635489
Directory /workspace/32.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/32.usbdev_smoke.3887489349
Short name T1643
Test name
Test status
Simulation time 175007968 ps
CPU time 0.82 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 206732 kb
Host smart-c73b4e53-b8b7-479b-bafe-9231271511db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38874
89349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_smoke.3887489349
Directory /workspace/32.usbdev_smoke/latest

Test location /workspace/coverage/default/32.usbdev_spurious_pids_ignored.1031191483
Short name T1217
Test name
Test status
Simulation time 3125176701 ps
CPU time 82.77 seconds
Started Jul 22 06:02:46 PM PDT 24
Finished Jul 22 06:04:10 PM PDT 24
Peak memory 206760 kb
Host smart-076428eb-564b-4ac3-a5ee-094331f8dfc5
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1031191483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_spurious_pids_ignored.1031191483
Directory /workspace/32.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/32.usbdev_stall_priority_over_nak.280274148
Short name T1843
Test name
Test status
Simulation time 146263056 ps
CPU time 0.76 seconds
Started Jul 22 06:01:14 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206756 kb
Host smart-9c1da852-34c4-49ab-89c9-ce045c21edc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28027
4148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_priority_over_nak.280274148
Directory /workspace/32.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/32.usbdev_stall_trans.1482709484
Short name T439
Test name
Test status
Simulation time 205623163 ps
CPU time 0.86 seconds
Started Jul 22 06:01:16 PM PDT 24
Finished Jul 22 06:01:17 PM PDT 24
Peak memory 206732 kb
Host smart-0b4ff43f-0d4e-400b-b370-f64e28568f09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14827
09484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stall_trans.1482709484
Directory /workspace/32.usbdev_stall_trans/latest

Test location /workspace/coverage/default/32.usbdev_stream_len_max.1047250974
Short name T2565
Test name
Test status
Simulation time 952518747 ps
CPU time 2.26 seconds
Started Jul 22 06:01:21 PM PDT 24
Finished Jul 22 06:01:24 PM PDT 24
Peak memory 206880 kb
Host smart-dd954339-9f90-44b2-821c-b171be239f6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10472
50974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_stream_len_max.1047250974
Directory /workspace/32.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/32.usbdev_streaming_out.3801342869
Short name T1593
Test name
Test status
Simulation time 4868368639 ps
CPU time 44.24 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206788 kb
Host smart-d2e2afc4-7a59-4253-b065-4e3981c9114f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38013
42869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.usbdev_streaming_out.3801342869
Directory /workspace/32.usbdev_streaming_out/latest

Test location /workspace/coverage/default/33.usbdev_alert_test.33329097
Short name T183
Test name
Test status
Simulation time 42977454 ps
CPU time 0.7 seconds
Started Jul 22 06:01:29 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206744 kb
Host smart-11de14a5-243d-4e69-92ed-26968b332668
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=33329097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_alert_test.33329097
Directory /workspace/33.usbdev_alert_test/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_disconnect.1175294397
Short name T195
Test name
Test status
Simulation time 3630696975 ps
CPU time 4.71 seconds
Started Jul 22 06:01:18 PM PDT 24
Finished Jul 22 06:01:23 PM PDT 24
Peak memory 206880 kb
Host smart-fe2ae53c-f21a-4472-8892-a5ca54fd8750
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1175294397 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_disconnect.1175294397
Directory /workspace/33.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_reset.3069505743
Short name T2482
Test name
Test status
Simulation time 13433512192 ps
CPU time 12.96 seconds
Started Jul 22 06:01:20 PM PDT 24
Finished Jul 22 06:01:34 PM PDT 24
Peak memory 206912 kb
Host smart-d99ddf55-87d2-4235-8550-a9c4393bdee1
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3069505743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_reset.3069505743
Directory /workspace/33.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/33.usbdev_aon_wake_resume.2361243237
Short name T639
Test name
Test status
Simulation time 23306804907 ps
CPU time 21.53 seconds
Started Jul 22 06:01:20 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206860 kb
Host smart-2ecfbe58-94ed-49bd-a64e-16fdde6811c0
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2361243237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_aon_wake_resume.2361243237
Directory /workspace/33.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/33.usbdev_av_buffer.1198635072
Short name T568
Test name
Test status
Simulation time 195680200 ps
CPU time 0.9 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206728 kb
Host smart-d920a8a8-e9f8-4e2d-8233-759993c8750a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11986
35072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_av_buffer.1198635072
Directory /workspace/33.usbdev_av_buffer/latest

Test location /workspace/coverage/default/33.usbdev_bitstuff_err.591927149
Short name T620
Test name
Test status
Simulation time 190212781 ps
CPU time 0.85 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:28 PM PDT 24
Peak memory 206748 kb
Host smart-4757e5ac-c661-474e-bfeb-035b53fdc914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59192
7149 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_bitstuff_err.591927149
Directory /workspace/33.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_clear.3017325731
Short name T107
Test name
Test status
Simulation time 492512335 ps
CPU time 1.4 seconds
Started Jul 22 06:01:40 PM PDT 24
Finished Jul 22 06:01:42 PM PDT 24
Peak memory 206852 kb
Host smart-d29a5abb-5540-4765-9d99-d9b23934eb34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30173
25731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_clear.3017325731
Directory /workspace/33.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/33.usbdev_data_toggle_restore.3835149791
Short name T2624
Test name
Test status
Simulation time 1070300956 ps
CPU time 2.46 seconds
Started Jul 22 06:01:18 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206816 kb
Host smart-290ac1c9-8fc3-4761-a827-0936e99f9cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38351
49791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_data_toggle_restore.3835149791
Directory /workspace/33.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/33.usbdev_device_address.3298467004
Short name T2735
Test name
Test status
Simulation time 14283579458 ps
CPU time 28.66 seconds
Started Jul 22 06:01:16 PM PDT 24
Finished Jul 22 06:01:45 PM PDT 24
Peak memory 206940 kb
Host smart-7f05cc0e-630e-478e-90b3-f29529d1195c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32984
67004 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_device_address.3298467004
Directory /workspace/33.usbdev_device_address/latest

Test location /workspace/coverage/default/33.usbdev_disable_endpoint.4175273834
Short name T1065
Test name
Test status
Simulation time 464686947 ps
CPU time 1.5 seconds
Started Jul 22 06:01:22 PM PDT 24
Finished Jul 22 06:01:24 PM PDT 24
Peak memory 206724 kb
Host smart-0390e4f1-f966-4f51-928a-7826e939e0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41752
73834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disable_endpoint.4175273834
Directory /workspace/33.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/33.usbdev_disconnected.4012536283
Short name T841
Test name
Test status
Simulation time 144699035 ps
CPU time 0.75 seconds
Started Jul 22 06:01:21 PM PDT 24
Finished Jul 22 06:01:22 PM PDT 24
Peak memory 206752 kb
Host smart-a74e1fcf-4520-455b-84e7-f8f0d5c549f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40125
36283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_disconnected.4012536283
Directory /workspace/33.usbdev_disconnected/latest

Test location /workspace/coverage/default/33.usbdev_enable.1572985201
Short name T672
Test name
Test status
Simulation time 55184392 ps
CPU time 0.68 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 206724 kb
Host smart-a2e852cd-a8ec-4f0e-a112-a5497490e9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15729
85201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_enable.1572985201
Directory /workspace/33.usbdev_enable/latest

Test location /workspace/coverage/default/33.usbdev_endpoint_access.1192646468
Short name T759
Test name
Test status
Simulation time 792948807 ps
CPU time 2 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:28 PM PDT 24
Peak memory 206868 kb
Host smart-8e04f6af-2f76-4ccf-9af1-30aeb5118d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11926
46468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_endpoint_access.1192646468
Directory /workspace/33.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/33.usbdev_fifo_rst.2886043790
Short name T2450
Test name
Test status
Simulation time 264174452 ps
CPU time 1.61 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 206828 kb
Host smart-dbf211c0-dbde-45ef-a1c1-aebf1448a20f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28860
43790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_fifo_rst.2886043790
Directory /workspace/33.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/33.usbdev_in_iso.3394251823
Short name T1087
Test name
Test status
Simulation time 161407433 ps
CPU time 0.83 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206664 kb
Host smart-47cc734f-5d18-417b-8169-90ff52c99165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33942
51823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_iso.3394251823
Directory /workspace/33.usbdev_in_iso/latest

Test location /workspace/coverage/default/33.usbdev_in_stall.2886144688
Short name T2494
Test name
Test status
Simulation time 142593509 ps
CPU time 0.74 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:01:25 PM PDT 24
Peak memory 206728 kb
Host smart-20ccf096-6e5b-4b34-81cd-144071c94c4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28861
44688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_stall.2886144688
Directory /workspace/33.usbdev_in_stall/latest

Test location /workspace/coverage/default/33.usbdev_in_trans.768584354
Short name T2337
Test name
Test status
Simulation time 204694217 ps
CPU time 0.83 seconds
Started Jul 22 06:03:08 PM PDT 24
Finished Jul 22 06:03:11 PM PDT 24
Peak memory 206728 kb
Host smart-3e1e15f1-c2e7-475a-ade9-87122514a686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76858
4354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_in_trans.768584354
Directory /workspace/33.usbdev_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_iso_retraction.3205280512
Short name T2213
Test name
Test status
Simulation time 5859262828 ps
CPU time 17.87 seconds
Started Jul 22 06:01:27 PM PDT 24
Finished Jul 22 06:01:46 PM PDT 24
Peak memory 206884 kb
Host smart-f68bae06-2378-40f7-9fd0-56aceab0a0f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32052
80512 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_iso_retraction.3205280512
Directory /workspace/33.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/33.usbdev_link_in_err.3071624302
Short name T215
Test name
Test status
Simulation time 203690874 ps
CPU time 0.87 seconds
Started Jul 22 06:01:19 PM PDT 24
Finished Jul 22 06:01:20 PM PDT 24
Peak memory 206728 kb
Host smart-43edde82-4c73-4c5c-a335-a5c4c7e2b549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30716
24302 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_in_err.3071624302
Directory /workspace/33.usbdev_link_in_err/latest

Test location /workspace/coverage/default/33.usbdev_link_resume.1294356024
Short name T535
Test name
Test status
Simulation time 23359445859 ps
CPU time 25.27 seconds
Started Jul 22 06:01:17 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206848 kb
Host smart-23bae554-8e7d-49bf-afea-b5629a0ec8d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12943
56024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_resume.1294356024
Directory /workspace/33.usbdev_link_resume/latest

Test location /workspace/coverage/default/33.usbdev_link_suspend.2310989272
Short name T2032
Test name
Test status
Simulation time 3276086494 ps
CPU time 3.83 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206808 kb
Host smart-ae2e992d-3b18-4cac-b72c-ceba9cc05ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23109
89272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_link_suspend.2310989272
Directory /workspace/33.usbdev_link_suspend/latest

Test location /workspace/coverage/default/33.usbdev_low_speed_traffic.2944744025
Short name T1572
Test name
Test status
Simulation time 8467663689 ps
CPU time 79.02 seconds
Started Jul 22 06:01:21 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206960 kb
Host smart-b25f0cc1-96a9-42e3-9c90-313d6a0165b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
44025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_low_speed_traffic.2944744025
Directory /workspace/33.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/33.usbdev_max_inter_pkt_delay.764716932
Short name T1360
Test name
Test status
Simulation time 3411125097 ps
CPU time 31.24 seconds
Started Jul 22 06:01:19 PM PDT 24
Finished Jul 22 06:01:51 PM PDT 24
Peak memory 206868 kb
Host smart-6ff6650a-7826-41b7-870a-7569e54fa08e
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=764716932 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_inter_pkt_delay.764716932
Directory /workspace/33.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_max_length_in_transaction.1331745823
Short name T785
Test name
Test status
Simulation time 282086007 ps
CPU time 0.96 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:28 PM PDT 24
Peak memory 206748 kb
Host smart-86677545-aa25-4dbc-ac2a-fd668f15bcb2
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1331745823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_in_transaction.1331745823
Directory /workspace/33.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_length_out_transaction.2994725517
Short name T1633
Test name
Test status
Simulation time 200793526 ps
CPU time 0.86 seconds
Started Jul 22 06:01:19 PM PDT 24
Finished Jul 22 06:01:20 PM PDT 24
Peak memory 206752 kb
Host smart-489ccf78-f02e-411a-aec1-2b3d7b7ca000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29947
25517 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_length_out_transaction.2994725517
Directory /workspace/33.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_max_usb_traffic.459255625
Short name T1915
Test name
Test status
Simulation time 4593740402 ps
CPU time 44.68 seconds
Started Jul 22 06:01:17 PM PDT 24
Finished Jul 22 06:02:02 PM PDT 24
Peak memory 207000 kb
Host smart-9f45e441-e228-4d44-a544-f9926abbd392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45925
5625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_max_usb_traffic.459255625
Directory /workspace/33.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/33.usbdev_min_inter_pkt_delay.1553906129
Short name T699
Test name
Test status
Simulation time 3034261468 ps
CPU time 82.57 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:02:49 PM PDT 24
Peak memory 206888 kb
Host smart-c0cc2720-d304-4f00-b17b-23c0317867eb
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1553906129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_inter_pkt_delay.1553906129
Directory /workspace/33.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/33.usbdev_min_length_in_transaction.3999849705
Short name T1147
Test name
Test status
Simulation time 165587886 ps
CPU time 0.83 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:29 PM PDT 24
Peak memory 206672 kb
Host smart-4cd1ddc0-312e-43d4-a1f2-23792ce30fad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3999849705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_in_transaction.3999849705
Directory /workspace/33.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_min_length_out_transaction.3741693360
Short name T1811
Test name
Test status
Simulation time 150834292 ps
CPU time 0.74 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206732 kb
Host smart-136d066a-7ac5-4248-8288-b89b33285c22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37416
93360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_min_length_out_transaction.3741693360
Directory /workspace/33.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_nak_trans.2032156190
Short name T135
Test name
Test status
Simulation time 195564816 ps
CPU time 0.84 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206724 kb
Host smart-ebc5ab9e-9134-40f0-bbc7-d55868ec3834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20321
56190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_nak_trans.2032156190
Directory /workspace/33.usbdev_nak_trans/latest

Test location /workspace/coverage/default/33.usbdev_out_iso.4253498453
Short name T1194
Test name
Test status
Simulation time 166774879 ps
CPU time 0.82 seconds
Started Jul 22 06:02:43 PM PDT 24
Finished Jul 22 06:02:44 PM PDT 24
Peak memory 206724 kb
Host smart-ad869f82-e2c0-4b1c-9a79-74f11477e6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42534
98453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_iso.4253498453
Directory /workspace/33.usbdev_out_iso/latest

Test location /workspace/coverage/default/33.usbdev_out_stall.1173669007
Short name T1855
Test name
Test status
Simulation time 191609697 ps
CPU time 0.79 seconds
Started Jul 22 06:01:20 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206728 kb
Host smart-da913378-6dc9-4eb1-853f-a4529f35bbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11736
69007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_stall.1173669007
Directory /workspace/33.usbdev_out_stall/latest

Test location /workspace/coverage/default/33.usbdev_out_trans_nak.1087727266
Short name T648
Test name
Test status
Simulation time 153775610 ps
CPU time 0.76 seconds
Started Jul 22 06:01:18 PM PDT 24
Finished Jul 22 06:01:19 PM PDT 24
Peak memory 206708 kb
Host smart-cc0a7a47-f5a7-4a28-85e9-045a89ea832f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10877
27266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_out_trans_nak.1087727266
Directory /workspace/33.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/33.usbdev_pending_in_trans.2017786734
Short name T175
Test name
Test status
Simulation time 149043190 ps
CPU time 0.81 seconds
Started Jul 22 06:01:20 PM PDT 24
Finished Jul 22 06:01:22 PM PDT 24
Peak memory 206752 kb
Host smart-18ce2987-ae6a-4ddb-99c5-8bca33b4b732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20177
86734 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pending_in_trans.2017786734
Directory /workspace/33.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_pinflip.2622370704
Short name T947
Test name
Test status
Simulation time 180777926 ps
CPU time 0.89 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:28 PM PDT 24
Peak memory 206672 kb
Host smart-0550deee-aa8f-4631-8c4b-fcc49ca0f518
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2622370704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_pinflip.2622370704
Directory /workspace/33.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/33.usbdev_phy_config_usb_ref_disable.3151187939
Short name T2242
Test name
Test status
Simulation time 201794084 ps
CPU time 0.83 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:29 PM PDT 24
Peak memory 206668 kb
Host smart-be152364-b233-4add-a857-ef9696bc3d68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31511
87939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_config_usb_ref_disable.3151187939
Directory /workspace/33.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/33.usbdev_phy_pins_sense.1456134456
Short name T850
Test name
Test status
Simulation time 36240743 ps
CPU time 0.68 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:01:26 PM PDT 24
Peak memory 206748 kb
Host smart-25188ca9-b546-48d0-845c-dc466952df16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14561
34456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_phy_pins_sense.1456134456
Directory /workspace/33.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/33.usbdev_pkt_buffer.3528648791
Short name T2585
Test name
Test status
Simulation time 21819232180 ps
CPU time 49.59 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206912 kb
Host smart-5cb6035c-32b2-458c-8e56-1d3ab70b1b0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35286
48791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_buffer.3528648791
Directory /workspace/33.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/33.usbdev_pkt_received.1703349534
Short name T1399
Test name
Test status
Simulation time 176134228 ps
CPU time 0.82 seconds
Started Jul 22 06:02:46 PM PDT 24
Finished Jul 22 06:02:48 PM PDT 24
Peak memory 206620 kb
Host smart-fc6f5a0b-1c82-403f-968d-0ac992723e4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17033
49534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_received.1703349534
Directory /workspace/33.usbdev_pkt_received/latest

Test location /workspace/coverage/default/33.usbdev_pkt_sent.244079908
Short name T563
Test name
Test status
Simulation time 210217595 ps
CPU time 0.84 seconds
Started Jul 22 06:01:18 PM PDT 24
Finished Jul 22 06:01:19 PM PDT 24
Peak memory 206748 kb
Host smart-9e2ded40-2ab6-46ff-bc77-24b1e4306875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24407
9908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_pkt_sent.244079908
Directory /workspace/33.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/33.usbdev_random_length_in_transaction.816375585
Short name T1506
Test name
Test status
Simulation time 210828240 ps
CPU time 0.85 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:01:25 PM PDT 24
Peak memory 206748 kb
Host smart-10b221f4-b74b-4926-a7a8-a591c4c1019b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81637
5585 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_in_transaction.816375585
Directory /workspace/33.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/33.usbdev_random_length_out_transaction.723514499
Short name T1262
Test name
Test status
Simulation time 164564203 ps
CPU time 0.79 seconds
Started Jul 22 06:01:14 PM PDT 24
Finished Jul 22 06:01:16 PM PDT 24
Peak memory 206876 kb
Host smart-bc4b3ce2-7342-4357-a274-e67f85a7c42e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72351
4499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_random_length_out_transaction.723514499
Directory /workspace/33.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/33.usbdev_rx_crc_err.904735378
Short name T2123
Test name
Test status
Simulation time 137240946 ps
CPU time 0.82 seconds
Started Jul 22 06:02:43 PM PDT 24
Finished Jul 22 06:02:44 PM PDT 24
Peak memory 206716 kb
Host smart-1ff138df-f5c8-4125-b1ad-380e4d61217c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90473
5378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_rx_crc_err.904735378
Directory /workspace/33.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/33.usbdev_setup_stage.3617329460
Short name T2395
Test name
Test status
Simulation time 157845979 ps
CPU time 0.79 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206668 kb
Host smart-ad2e2b78-f49c-4884-a8f6-3d10324ccfce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36173
29460 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_stage.3617329460
Directory /workspace/33.usbdev_setup_stage/latest

Test location /workspace/coverage/default/33.usbdev_setup_trans_ignored.3959823235
Short name T320
Test name
Test status
Simulation time 175967938 ps
CPU time 0.84 seconds
Started Jul 22 06:01:15 PM PDT 24
Finished Jul 22 06:01:17 PM PDT 24
Peak memory 206628 kb
Host smart-f13bc4c1-797b-4722-b272-ddeaae150b17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39598
23235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_setup_trans_ignored.3959823235
Directory /workspace/33.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/33.usbdev_smoke.773943291
Short name T2034
Test name
Test status
Simulation time 249066132 ps
CPU time 0.93 seconds
Started Jul 22 06:01:19 PM PDT 24
Finished Jul 22 06:01:21 PM PDT 24
Peak memory 206716 kb
Host smart-ceb15a5f-2567-42d3-bba9-201716aa44cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77394
3291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_smoke.773943291
Directory /workspace/33.usbdev_smoke/latest

Test location /workspace/coverage/default/33.usbdev_spurious_pids_ignored.2054987055
Short name T1005
Test name
Test status
Simulation time 5338841417 ps
CPU time 146.48 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:06:42 PM PDT 24
Peak memory 206864 kb
Host smart-17cce420-034d-497b-9be6-9cc9f03109bf
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2054987055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_spurious_pids_ignored.2054987055
Directory /workspace/33.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/33.usbdev_stall_priority_over_nak.2652001459
Short name T2691
Test name
Test status
Simulation time 187479384 ps
CPU time 0.79 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:01:25 PM PDT 24
Peak memory 206752 kb
Host smart-ce8032d7-a627-473d-ba47-10fcd070486c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26520
01459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_priority_over_nak.2652001459
Directory /workspace/33.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/33.usbdev_stall_trans.3123439598
Short name T809
Test name
Test status
Simulation time 167603968 ps
CPU time 0.84 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:26 PM PDT 24
Peak memory 206744 kb
Host smart-4ed38446-b9ca-4b83-a4f8-0430b13c9620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31234
39598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stall_trans.3123439598
Directory /workspace/33.usbdev_stall_trans/latest

Test location /workspace/coverage/default/33.usbdev_stream_len_max.3909305253
Short name T1538
Test name
Test status
Simulation time 591086547 ps
CPU time 1.6 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:01:26 PM PDT 24
Peak memory 206864 kb
Host smart-779db1df-dcfb-45e8-aaea-84795b01cc88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
05253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_stream_len_max.3909305253
Directory /workspace/33.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/33.usbdev_streaming_out.1256218053
Short name T327
Test name
Test status
Simulation time 5728746983 ps
CPU time 40.09 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206784 kb
Host smart-6333c6d0-7185-4e7a-be12-0e64384ef7a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
18053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.usbdev_streaming_out.1256218053
Directory /workspace/33.usbdev_streaming_out/latest

Test location /workspace/coverage/default/34.usbdev_alert_test.1496631196
Short name T2504
Test name
Test status
Simulation time 53966315 ps
CPU time 0.67 seconds
Started Jul 22 06:03:08 PM PDT 24
Finished Jul 22 06:03:11 PM PDT 24
Peak memory 206684 kb
Host smart-ea975c40-f655-4727-b75f-573fd52aa7e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1496631196 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_alert_test.1496631196
Directory /workspace/34.usbdev_alert_test/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_disconnect.2143710336
Short name T827
Test name
Test status
Simulation time 4425568939 ps
CPU time 5.5 seconds
Started Jul 22 06:02:21 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206964 kb
Host smart-f5eaa2c6-2b78-452e-be1a-e7ef67f3f86a
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2143710336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_disconnect.2143710336
Directory /workspace/34.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_reset.3148221278
Short name T1513
Test name
Test status
Simulation time 13409979213 ps
CPU time 14.01 seconds
Started Jul 22 06:01:30 PM PDT 24
Finished Jul 22 06:01:45 PM PDT 24
Peak memory 206908 kb
Host smart-4b8b9598-44b3-4435-a929-c32e49ce1e60
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3148221278 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_reset.3148221278
Directory /workspace/34.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/34.usbdev_aon_wake_resume.820062321
Short name T52
Test name
Test status
Simulation time 23317673287 ps
CPU time 22.83 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:49 PM PDT 24
Peak memory 206868 kb
Host smart-8f753712-ffca-46a2-9f88-96883f3c7929
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=820062321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_aon_wake_resume.820062321
Directory /workspace/34.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/34.usbdev_av_buffer.296681160
Short name T308
Test name
Test status
Simulation time 172346651 ps
CPU time 0.82 seconds
Started Jul 22 06:02:33 PM PDT 24
Finished Jul 22 06:02:34 PM PDT 24
Peak memory 206512 kb
Host smart-6c656502-c816-4473-a171-4bd02df947d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29668
1160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_av_buffer.296681160
Directory /workspace/34.usbdev_av_buffer/latest

Test location /workspace/coverage/default/34.usbdev_bitstuff_err.389939123
Short name T1198
Test name
Test status
Simulation time 148640430 ps
CPU time 0.84 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:29 PM PDT 24
Peak memory 206668 kb
Host smart-8d4a58f8-3a88-4032-a0fd-da45b6b2efbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38993
9123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_bitstuff_err.389939123
Directory /workspace/34.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_clear.2184845515
Short name T1356
Test name
Test status
Simulation time 173495999 ps
CPU time 0.83 seconds
Started Jul 22 06:03:18 PM PDT 24
Finished Jul 22 06:03:19 PM PDT 24
Peak memory 206712 kb
Host smart-f0f9b8a7-787d-47a1-b706-b3eae30276c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21848
45515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_clear.2184845515
Directory /workspace/34.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/34.usbdev_data_toggle_restore.36177444
Short name T2211
Test name
Test status
Simulation time 576226775 ps
CPU time 1.46 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:29 PM PDT 24
Peak memory 206732 kb
Host smart-2cc6aeaf-b203-46ee-8be9-2fda1427e5d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36177
444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_data_toggle_restore.36177444
Directory /workspace/34.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/34.usbdev_device_address.2642109474
Short name T577
Test name
Test status
Simulation time 18056875231 ps
CPU time 34.79 seconds
Started Jul 22 06:01:29 PM PDT 24
Finished Jul 22 06:02:05 PM PDT 24
Peak memory 206968 kb
Host smart-c68ab0e0-c418-4809-af3a-91fffb7aea63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26421
09474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_device_address.2642109474
Directory /workspace/34.usbdev_device_address/latest

Test location /workspace/coverage/default/34.usbdev_disable_endpoint.961108471
Short name T1819
Test name
Test status
Simulation time 503634815 ps
CPU time 1.46 seconds
Started Jul 22 06:02:23 PM PDT 24
Finished Jul 22 06:02:26 PM PDT 24
Peak memory 206752 kb
Host smart-e9226a33-0f61-474c-bb54-9a239eef031b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96110
8471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disable_endpoint.961108471
Directory /workspace/34.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/34.usbdev_disconnected.116568472
Short name T512
Test name
Test status
Simulation time 143004212 ps
CPU time 0.73 seconds
Started Jul 22 06:01:31 PM PDT 24
Finished Jul 22 06:01:32 PM PDT 24
Peak memory 206724 kb
Host smart-009d9606-911f-4b80-8ae6-362610ec71d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11656
8472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_disconnected.116568472
Directory /workspace/34.usbdev_disconnected/latest

Test location /workspace/coverage/default/34.usbdev_enable.379078427
Short name T602
Test name
Test status
Simulation time 37413451 ps
CPU time 0.67 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 206728 kb
Host smart-b65734cb-99c5-4206-9aab-abbf0fdbffd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37907
8427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_enable.379078427
Directory /workspace/34.usbdev_enable/latest

Test location /workspace/coverage/default/34.usbdev_endpoint_access.681917652
Short name T384
Test name
Test status
Simulation time 853710460 ps
CPU time 2.06 seconds
Started Jul 22 06:01:27 PM PDT 24
Finished Jul 22 06:01:31 PM PDT 24
Peak memory 206848 kb
Host smart-bd17377f-de24-46d2-a8a5-86f544e9cea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68191
7652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_endpoint_access.681917652
Directory /workspace/34.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/34.usbdev_fifo_rst.3460254429
Short name T2176
Test name
Test status
Simulation time 202247557 ps
CPU time 1.83 seconds
Started Jul 22 06:01:27 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206800 kb
Host smart-06af5cec-c1d5-4346-aa77-107b1a380a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34602
54429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_fifo_rst.3460254429
Directory /workspace/34.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/34.usbdev_in_iso.2806638784
Short name T372
Test name
Test status
Simulation time 254218392 ps
CPU time 0.96 seconds
Started Jul 22 06:01:33 PM PDT 24
Finished Jul 22 06:01:35 PM PDT 24
Peak memory 206748 kb
Host smart-5ca91cbe-e6c1-40ce-8ffd-59aac971d1b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28066
38784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_iso.2806638784
Directory /workspace/34.usbdev_in_iso/latest

Test location /workspace/coverage/default/34.usbdev_in_stall.3229123794
Short name T2233
Test name
Test status
Simulation time 137009237 ps
CPU time 0.74 seconds
Started Jul 22 06:01:31 PM PDT 24
Finished Jul 22 06:01:32 PM PDT 24
Peak memory 206724 kb
Host smart-e5d8ad16-aa52-4156-9f3f-50db93f8a583
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32291
23794 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_stall.3229123794
Directory /workspace/34.usbdev_in_stall/latest

Test location /workspace/coverage/default/34.usbdev_in_trans.955870928
Short name T365
Test name
Test status
Simulation time 177533242 ps
CPU time 0.81 seconds
Started Jul 22 06:01:31 PM PDT 24
Finished Jul 22 06:01:33 PM PDT 24
Peak memory 206704 kb
Host smart-3aa983c4-9072-4bc1-9df6-e42acb485275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95587
0928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_in_trans.955870928
Directory /workspace/34.usbdev_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_invalid_sync.2679629269
Short name T101
Test name
Test status
Simulation time 6400764979 ps
CPU time 178.47 seconds
Started Jul 22 06:01:27 PM PDT 24
Finished Jul 22 06:04:27 PM PDT 24
Peak memory 206844 kb
Host smart-74f928f8-6192-481e-8e40-93fab6d9db68
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2679629269 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_invalid_sync.2679629269
Directory /workspace/34.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/34.usbdev_iso_retraction.4037318493
Short name T1774
Test name
Test status
Simulation time 13910744787 ps
CPU time 53.57 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206972 kb
Host smart-c58d8dfd-83c3-4340-b123-da024f8097b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40373
18493 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_iso_retraction.4037318493
Directory /workspace/34.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/34.usbdev_link_in_err.2984499587
Short name T528
Test name
Test status
Simulation time 269148356 ps
CPU time 0.98 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:26 PM PDT 24
Peak memory 206724 kb
Host smart-7a3fc4d6-fc62-4cf7-868d-f26e080346e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29844
99587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_in_err.2984499587
Directory /workspace/34.usbdev_link_in_err/latest

Test location /workspace/coverage/default/34.usbdev_link_resume.4107258607
Short name T1542
Test name
Test status
Simulation time 23283539326 ps
CPU time 25.87 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206768 kb
Host smart-8031b8e2-1564-4e48-a8f9-8f749df84111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41072
58607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_resume.4107258607
Directory /workspace/34.usbdev_link_resume/latest

Test location /workspace/coverage/default/34.usbdev_link_suspend.3908780786
Short name T20
Test name
Test status
Simulation time 3407590857 ps
CPU time 4.28 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:32 PM PDT 24
Peak memory 206828 kb
Host smart-27040154-5fc0-474a-8529-6c95b60ce832
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39087
80786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_link_suspend.3908780786
Directory /workspace/34.usbdev_link_suspend/latest

Test location /workspace/coverage/default/34.usbdev_low_speed_traffic.2816227362
Short name T2338
Test name
Test status
Simulation time 8671291740 ps
CPU time 62.73 seconds
Started Jul 22 06:01:29 PM PDT 24
Finished Jul 22 06:02:32 PM PDT 24
Peak memory 206880 kb
Host smart-f14c67bf-ff72-4fd0-b454-b260e27785ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28162
27362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_low_speed_traffic.2816227362
Directory /workspace/34.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/34.usbdev_max_inter_pkt_delay.970503450
Short name T1837
Test name
Test status
Simulation time 7258557817 ps
CPU time 66.55 seconds
Started Jul 22 06:01:28 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206900 kb
Host smart-4ab85535-f81f-4313-b6b6-bb26ad0e2fb2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=970503450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_inter_pkt_delay.970503450
Directory /workspace/34.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_max_length_in_transaction.1395938897
Short name T2167
Test name
Test status
Simulation time 264027117 ps
CPU time 0.93 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:27 PM PDT 24
Peak memory 206584 kb
Host smart-3b9fcaba-c928-422b-b0f5-9d6b02e10a71
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1395938897 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_in_transaction.1395938897
Directory /workspace/34.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_length_out_transaction.441187848
Short name T679
Test name
Test status
Simulation time 216963667 ps
CPU time 0.85 seconds
Started Jul 22 06:01:29 PM PDT 24
Finished Jul 22 06:01:31 PM PDT 24
Peak memory 206700 kb
Host smart-f1766f44-aa63-4410-a2e7-5a5b1baf0585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44118
7848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_length_out_transaction.441187848
Directory /workspace/34.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_max_usb_traffic.3296621920
Short name T477
Test name
Test status
Simulation time 3690905774 ps
CPU time 26.48 seconds
Started Jul 22 06:01:29 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206924 kb
Host smart-7e0f9426-2d3a-4414-b4f2-2eadb57a0e61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32966
21920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_max_usb_traffic.3296621920
Directory /workspace/34.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/34.usbdev_min_inter_pkt_delay.2168041788
Short name T2547
Test name
Test status
Simulation time 5611218376 ps
CPU time 39.77 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206856 kb
Host smart-a505a67e-b032-4749-a915-d5394d274581
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2168041788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_inter_pkt_delay.2168041788
Directory /workspace/34.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/34.usbdev_min_length_in_transaction.2496026806
Short name T2584
Test name
Test status
Simulation time 164705970 ps
CPU time 0.84 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:29 PM PDT 24
Peak memory 206632 kb
Host smart-61d1b5fc-35f1-4d6a-b673-35f7b5c3457e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2496026806 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_in_transaction.2496026806
Directory /workspace/34.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_min_length_out_transaction.875933821
Short name T1918
Test name
Test status
Simulation time 148744621 ps
CPU time 0.76 seconds
Started Jul 22 06:01:28 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206764 kb
Host smart-d2de2cb3-dbaf-427d-a223-dd3bea6e2fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87593
3821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_min_length_out_transaction.875933821
Directory /workspace/34.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_nak_trans.3131430399
Short name T1687
Test name
Test status
Simulation time 221055021 ps
CPU time 0.92 seconds
Started Jul 22 06:01:29 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206708 kb
Host smart-a6f2826e-f5a5-48ea-b48d-cbad311a84b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31314
30399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_nak_trans.3131430399
Directory /workspace/34.usbdev_nak_trans/latest

Test location /workspace/coverage/default/34.usbdev_out_iso.709832898
Short name T2620
Test name
Test status
Simulation time 208983569 ps
CPU time 0.88 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:01:26 PM PDT 24
Peak memory 206756 kb
Host smart-db56b254-f068-4be4-a100-f2d2a3ffd41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70983
2898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_iso.709832898
Directory /workspace/34.usbdev_out_iso/latest

Test location /workspace/coverage/default/34.usbdev_out_stall.4152520262
Short name T2716
Test name
Test status
Simulation time 194617342 ps
CPU time 0.81 seconds
Started Jul 22 06:01:31 PM PDT 24
Finished Jul 22 06:01:32 PM PDT 24
Peak memory 206724 kb
Host smart-f2cb614e-c70c-4e9c-8768-27ef29ce1a7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41525
20262 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_stall.4152520262
Directory /workspace/34.usbdev_out_stall/latest

Test location /workspace/coverage/default/34.usbdev_out_trans_nak.857741040
Short name T1359
Test name
Test status
Simulation time 190311588 ps
CPU time 0.83 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:37 PM PDT 24
Peak memory 206720 kb
Host smart-8d39e7ee-d9fe-402a-a94c-29cc5ffc16d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85774
1040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_out_trans_nak.857741040
Directory /workspace/34.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/34.usbdev_pending_in_trans.2376886793
Short name T2501
Test name
Test status
Simulation time 152063904 ps
CPU time 0.76 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 206740 kb
Host smart-f96eba18-bb15-47c2-90bc-05b5df1337e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23768
86793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pending_in_trans.2376886793
Directory /workspace/34.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_pinflip.2714021779
Short name T2402
Test name
Test status
Simulation time 288804925 ps
CPU time 1.02 seconds
Started Jul 22 06:01:24 PM PDT 24
Finished Jul 22 06:01:26 PM PDT 24
Peak memory 206740 kb
Host smart-f04c1c40-eb77-4af2-9abc-96bc9cb1aebf
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2714021779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_pinflip.2714021779
Directory /workspace/34.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/34.usbdev_phy_config_usb_ref_disable.1349887889
Short name T1548
Test name
Test status
Simulation time 160311258 ps
CPU time 0.8 seconds
Started Jul 22 06:01:26 PM PDT 24
Finished Jul 22 06:01:28 PM PDT 24
Peak memory 206740 kb
Host smart-d62556b6-687d-45b3-9472-d2e27d43d7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13498
87889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_config_usb_ref_disable.1349887889
Directory /workspace/34.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/34.usbdev_phy_pins_sense.86370596
Short name T1353
Test name
Test status
Simulation time 27774130 ps
CPU time 0.68 seconds
Started Jul 22 06:01:27 PM PDT 24
Finished Jul 22 06:01:29 PM PDT 24
Peak memory 206688 kb
Host smart-63ae6518-386d-4a7d-9765-818e263799ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86370
596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_phy_pins_sense.86370596
Directory /workspace/34.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/34.usbdev_pkt_buffer.2829172006
Short name T2304
Test name
Test status
Simulation time 14052141123 ps
CPU time 31.59 seconds
Started Jul 22 06:01:28 PM PDT 24
Finished Jul 22 06:02:01 PM PDT 24
Peak memory 206980 kb
Host smart-a730bbeb-fc90-4925-857b-a182f268bae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28291
72006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_buffer.2829172006
Directory /workspace/34.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/34.usbdev_pkt_received.1481454392
Short name T29
Test name
Test status
Simulation time 157157739 ps
CPU time 0.85 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:37 PM PDT 24
Peak memory 206740 kb
Host smart-8f9bae33-b35e-459c-aae0-40a84c457cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14814
54392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_received.1481454392
Directory /workspace/34.usbdev_pkt_received/latest

Test location /workspace/coverage/default/34.usbdev_pkt_sent.100983442
Short name T711
Test name
Test status
Simulation time 285899194 ps
CPU time 0.98 seconds
Started Jul 22 06:04:14 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 206728 kb
Host smart-cd8d8870-0416-48a0-affe-d204d00cf61e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10098
3442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_pkt_sent.100983442
Directory /workspace/34.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/34.usbdev_random_length_in_transaction.402265930
Short name T1516
Test name
Test status
Simulation time 223843238 ps
CPU time 0.85 seconds
Started Jul 22 06:02:34 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206748 kb
Host smart-c52aeee7-9028-44b3-9754-18f07cb08fbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40226
5930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_in_transaction.402265930
Directory /workspace/34.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/34.usbdev_random_length_out_transaction.3713297632
Short name T1956
Test name
Test status
Simulation time 182618692 ps
CPU time 0.85 seconds
Started Jul 22 06:01:27 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206732 kb
Host smart-d8c3454c-2531-4982-92c2-caa437c91c2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37132
97632 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_random_length_out_transaction.3713297632
Directory /workspace/34.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/34.usbdev_rx_crc_err.3367310286
Short name T1002
Test name
Test status
Simulation time 143929558 ps
CPU time 0.74 seconds
Started Jul 22 06:01:28 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206704 kb
Host smart-a86a2dc8-8597-4133-aea5-285033d4d52b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33673
10286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_rx_crc_err.3367310286
Directory /workspace/34.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/34.usbdev_setup_stage.3467907353
Short name T2581
Test name
Test status
Simulation time 185416151 ps
CPU time 0.91 seconds
Started Jul 22 06:01:27 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206708 kb
Host smart-7b97ff11-ba59-452c-838c-7994718e9f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
07353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_stage.3467907353
Directory /workspace/34.usbdev_setup_stage/latest

Test location /workspace/coverage/default/34.usbdev_setup_trans_ignored.2563533276
Short name T468
Test name
Test status
Simulation time 172429630 ps
CPU time 0.78 seconds
Started Jul 22 06:03:18 PM PDT 24
Finished Jul 22 06:03:19 PM PDT 24
Peak memory 206732 kb
Host smart-59ce8905-f275-42a1-9223-ba382bfad6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25635
33276 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_setup_trans_ignored.2563533276
Directory /workspace/34.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/34.usbdev_smoke.3801897506
Short name T1648
Test name
Test status
Simulation time 211400497 ps
CPU time 0.94 seconds
Started Jul 22 06:01:28 PM PDT 24
Finished Jul 22 06:01:30 PM PDT 24
Peak memory 206748 kb
Host smart-bfe77968-2381-444f-b8d1-67d7a085c4cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38018
97506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_smoke.3801897506
Directory /workspace/34.usbdev_smoke/latest

Test location /workspace/coverage/default/34.usbdev_spurious_pids_ignored.635144155
Short name T1524
Test name
Test status
Simulation time 3366155408 ps
CPU time 23.16 seconds
Started Jul 22 06:01:46 PM PDT 24
Finished Jul 22 06:02:09 PM PDT 24
Peak memory 206960 kb
Host smart-72d8e719-0d31-46ed-a209-7601cfb63cff
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=635144155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_spurious_pids_ignored.635144155
Directory /workspace/34.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/34.usbdev_stall_priority_over_nak.3849479834
Short name T2037
Test name
Test status
Simulation time 160019948 ps
CPU time 0.76 seconds
Started Jul 22 06:02:34 PM PDT 24
Finished Jul 22 06:02:35 PM PDT 24
Peak memory 206728 kb
Host smart-0309aec8-1550-41aa-82c0-ecf7ec7e4f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38494
79834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_priority_over_nak.3849479834
Directory /workspace/34.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/34.usbdev_stall_trans.234289106
Short name T879
Test name
Test status
Simulation time 152778591 ps
CPU time 0.78 seconds
Started Jul 22 06:01:25 PM PDT 24
Finished Jul 22 06:01:28 PM PDT 24
Peak memory 206724 kb
Host smart-08cfb583-2683-4b67-b58b-669d2f4373c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23428
9106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stall_trans.234289106
Directory /workspace/34.usbdev_stall_trans/latest

Test location /workspace/coverage/default/34.usbdev_stream_len_max.3840611593
Short name T2739
Test name
Test status
Simulation time 753191976 ps
CPU time 1.9 seconds
Started Jul 22 06:01:42 PM PDT 24
Finished Jul 22 06:01:44 PM PDT 24
Peak memory 206876 kb
Host smart-59094c80-2255-48ec-af2a-aceffe229dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38406
11593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_stream_len_max.3840611593
Directory /workspace/34.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/34.usbdev_streaming_out.2810471142
Short name T2616
Test name
Test status
Simulation time 4847587331 ps
CPU time 34.13 seconds
Started Jul 22 06:01:28 PM PDT 24
Finished Jul 22 06:02:03 PM PDT 24
Peak memory 206920 kb
Host smart-f09b39e8-f244-4499-bea5-543181fac6a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28104
71142 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.usbdev_streaming_out.2810471142
Directory /workspace/34.usbdev_streaming_out/latest

Test location /workspace/coverage/default/35.usbdev_alert_test.2252882534
Short name T2633
Test name
Test status
Simulation time 96616115 ps
CPU time 0.71 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206724 kb
Host smart-6fd9c236-96eb-4f44-8c08-9d04e474c930
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2252882534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_alert_test.2252882534
Directory /workspace/35.usbdev_alert_test/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_disconnect.2110733053
Short name T1902
Test name
Test status
Simulation time 4001049553 ps
CPU time 4.96 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:47 PM PDT 24
Peak memory 206904 kb
Host smart-13be7f06-366a-46fc-be33-6240c0390cfa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2110733053 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_disconnect.2110733053
Directory /workspace/35.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_reset.2306912264
Short name T1400
Test name
Test status
Simulation time 13398793187 ps
CPU time 13.69 seconds
Started Jul 22 06:01:42 PM PDT 24
Finished Jul 22 06:01:57 PM PDT 24
Peak memory 206796 kb
Host smart-d2c50eec-53c5-48c4-b63a-7885e3a98404
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2306912264 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_reset.2306912264
Directory /workspace/35.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/35.usbdev_aon_wake_resume.3097701459
Short name T510
Test name
Test status
Simulation time 23399985900 ps
CPU time 28.51 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206808 kb
Host smart-d06d9823-9654-46fc-91b1-c90b2e884394
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3097701459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_aon_wake_resume.3097701459
Directory /workspace/35.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/35.usbdev_av_buffer.2669586411
Short name T492
Test name
Test status
Simulation time 151668696 ps
CPU time 0.78 seconds
Started Jul 22 06:01:42 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206724 kb
Host smart-398490e1-a113-4007-8270-d1ca6cc7f8aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26695
86411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_av_buffer.2669586411
Directory /workspace/35.usbdev_av_buffer/latest

Test location /workspace/coverage/default/35.usbdev_bitstuff_err.1304256094
Short name T1786
Test name
Test status
Simulation time 151728295 ps
CPU time 0.75 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206740 kb
Host smart-18486746-7414-44b3-9604-a4255c54fccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13042
56094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_bitstuff_err.1304256094
Directory /workspace/35.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_clear.2186103786
Short name T1862
Test name
Test status
Simulation time 213332653 ps
CPU time 0.88 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206636 kb
Host smart-aa2b9e4a-8392-46f3-9700-e919cbfc95f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21861
03786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_clear.2186103786
Directory /workspace/35.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/35.usbdev_data_toggle_restore.3829622372
Short name T2688
Test name
Test status
Simulation time 1170305035 ps
CPU time 2.75 seconds
Started Jul 22 06:01:44 PM PDT 24
Finished Jul 22 06:01:47 PM PDT 24
Peak memory 206900 kb
Host smart-748c0a1f-d7fd-4a56-9206-c09221a21359
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38296
22372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_data_toggle_restore.3829622372
Directory /workspace/35.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/35.usbdev_device_address.1051080777
Short name T1504
Test name
Test status
Simulation time 7958712144 ps
CPU time 16.03 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206940 kb
Host smart-ac17d63b-a5ce-4401-91b8-6c62916e69e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10510
80777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_device_address.1051080777
Directory /workspace/35.usbdev_device_address/latest

Test location /workspace/coverage/default/35.usbdev_disable_endpoint.1312110612
Short name T1952
Test name
Test status
Simulation time 372375516 ps
CPU time 1.32 seconds
Started Jul 22 06:01:40 PM PDT 24
Finished Jul 22 06:01:42 PM PDT 24
Peak memory 206732 kb
Host smart-f8489eff-b64e-4351-9140-b917d4aa7085
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13121
10612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disable_endpoint.1312110612
Directory /workspace/35.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/35.usbdev_disconnected.3488104854
Short name T1251
Test name
Test status
Simulation time 152670019 ps
CPU time 0.75 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:42 PM PDT 24
Peak memory 206660 kb
Host smart-e1acc6c3-a9d4-4a65-8c78-e80772c3ce6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34881
04854 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_disconnected.3488104854
Directory /workspace/35.usbdev_disconnected/latest

Test location /workspace/coverage/default/35.usbdev_enable.3919862328
Short name T2224
Test name
Test status
Simulation time 33400286 ps
CPU time 0.68 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:24 PM PDT 24
Peak memory 206764 kb
Host smart-a68eebf5-5049-47e5-8892-b54e964b19de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39198
62328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_enable.3919862328
Directory /workspace/35.usbdev_enable/latest

Test location /workspace/coverage/default/35.usbdev_endpoint_access.3654160890
Short name T1876
Test name
Test status
Simulation time 800650820 ps
CPU time 1.82 seconds
Started Jul 22 06:02:57 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206880 kb
Host smart-848f8ba8-a253-4c92-b7f9-db7d9f46496c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36541
60890 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_endpoint_access.3654160890
Directory /workspace/35.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/35.usbdev_fifo_rst.2406914161
Short name T2189
Test name
Test status
Simulation time 180448053 ps
CPU time 2.17 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:44 PM PDT 24
Peak memory 207008 kb
Host smart-2813224a-e103-43f5-b9b3-1e48ee87c2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24069
14161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_fifo_rst.2406914161
Directory /workspace/35.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/35.usbdev_in_iso.2190956176
Short name T2682
Test name
Test status
Simulation time 241464599 ps
CPU time 0.9 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206760 kb
Host smart-a5f426b7-c4e8-487e-9831-bda20889363d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21909
56176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_iso.2190956176
Directory /workspace/35.usbdev_in_iso/latest

Test location /workspace/coverage/default/35.usbdev_in_stall.3035452047
Short name T2098
Test name
Test status
Simulation time 142021106 ps
CPU time 0.73 seconds
Started Jul 22 06:03:17 PM PDT 24
Finished Jul 22 06:03:19 PM PDT 24
Peak memory 206732 kb
Host smart-bb93e209-7c03-44ea-8f9c-eff37fddf704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30354
52047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_stall.3035452047
Directory /workspace/35.usbdev_in_stall/latest

Test location /workspace/coverage/default/35.usbdev_in_trans.2846154286
Short name T755
Test name
Test status
Simulation time 247929868 ps
CPU time 0.95 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:24 PM PDT 24
Peak memory 206768 kb
Host smart-97e0d924-8d35-4c67-b407-d21e6bef99d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28461
54286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_in_trans.2846154286
Directory /workspace/35.usbdev_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_invalid_sync.3843963676
Short name T216
Test name
Test status
Simulation time 10093918927 ps
CPU time 74.23 seconds
Started Jul 22 06:03:17 PM PDT 24
Finished Jul 22 06:04:32 PM PDT 24
Peak memory 206972 kb
Host smart-e6d1a4a0-a16a-4e82-84c0-08b45fbb6a7b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3843963676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_invalid_sync.3843963676
Directory /workspace/35.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/35.usbdev_iso_retraction.835984357
Short name T1076
Test name
Test status
Simulation time 5969937782 ps
CPU time 44.14 seconds
Started Jul 22 06:01:44 PM PDT 24
Finished Jul 22 06:02:29 PM PDT 24
Peak memory 206860 kb
Host smart-e392ade6-0965-4f8a-98a6-cee170bf75b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83598
4357 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_iso_retraction.835984357
Directory /workspace/35.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/35.usbdev_link_in_err.1072111582
Short name T1963
Test name
Test status
Simulation time 176757864 ps
CPU time 0.84 seconds
Started Jul 22 06:01:40 PM PDT 24
Finished Jul 22 06:01:41 PM PDT 24
Peak memory 206628 kb
Host smart-1f0b9af6-854d-410b-87d4-d5cd8e9741fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10721
11582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_in_err.1072111582
Directory /workspace/35.usbdev_link_in_err/latest

Test location /workspace/coverage/default/35.usbdev_link_resume.484702340
Short name T2334
Test name
Test status
Simulation time 23289672128 ps
CPU time 28.7 seconds
Started Jul 22 06:01:44 PM PDT 24
Finished Jul 22 06:02:13 PM PDT 24
Peak memory 206768 kb
Host smart-4652fbfe-9774-4af2-b404-43c98a9795d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48470
2340 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_resume.484702340
Directory /workspace/35.usbdev_link_resume/latest

Test location /workspace/coverage/default/35.usbdev_link_suspend.2945810432
Short name T1186
Test name
Test status
Simulation time 3339752606 ps
CPU time 3.9 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:45 PM PDT 24
Peak memory 206968 kb
Host smart-715917bb-e1d6-44dc-8e46-1f53a11dc16f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29458
10432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_link_suspend.2945810432
Directory /workspace/35.usbdev_link_suspend/latest

Test location /workspace/coverage/default/35.usbdev_low_speed_traffic.904877337
Short name T550
Test name
Test status
Simulation time 9874107965 ps
CPU time 279.19 seconds
Started Jul 22 06:01:38 PM PDT 24
Finished Jul 22 06:06:18 PM PDT 24
Peak memory 206984 kb
Host smart-8dd512cd-fd46-4ff5-942c-989309c88ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90487
7337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_low_speed_traffic.904877337
Directory /workspace/35.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/35.usbdev_max_inter_pkt_delay.3918405384
Short name T357
Test name
Test status
Simulation time 6831012980 ps
CPU time 186.34 seconds
Started Jul 22 06:03:18 PM PDT 24
Finished Jul 22 06:06:25 PM PDT 24
Peak memory 206876 kb
Host smart-6194d7f0-acd1-4366-9277-00708370a5d9
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3918405384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_inter_pkt_delay.3918405384
Directory /workspace/35.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_max_length_in_transaction.702531633
Short name T469
Test name
Test status
Simulation time 277298719 ps
CPU time 1 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206668 kb
Host smart-30cfb4f6-163b-4e94-9356-23b4aad285da
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=702531633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_in_transaction.702531633
Directory /workspace/35.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_length_out_transaction.3997925489
Short name T389
Test name
Test status
Simulation time 199419503 ps
CPU time 0.88 seconds
Started Jul 22 06:01:43 PM PDT 24
Finished Jul 22 06:01:44 PM PDT 24
Peak memory 206704 kb
Host smart-880512b8-7f12-4ae2-a9b9-18d2f3e4ecac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39979
25489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_length_out_transaction.3997925489
Directory /workspace/35.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_max_usb_traffic.2362158367
Short name T2029
Test name
Test status
Simulation time 4466279886 ps
CPU time 125.19 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:03:47 PM PDT 24
Peak memory 206976 kb
Host smart-20e3839a-284d-4d4f-a669-16373def0762
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23621
58367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_max_usb_traffic.2362158367
Directory /workspace/35.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/35.usbdev_min_inter_pkt_delay.3634831857
Short name T1277
Test name
Test status
Simulation time 3877814113 ps
CPU time 40.01 seconds
Started Jul 22 06:01:39 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206880 kb
Host smart-78a3c290-7ac5-4519-9467-73fe3e6826c8
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3634831857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_inter_pkt_delay.3634831857
Directory /workspace/35.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/35.usbdev_min_length_in_transaction.2577415648
Short name T2640
Test name
Test status
Simulation time 186494090 ps
CPU time 0.83 seconds
Started Jul 22 06:01:39 PM PDT 24
Finished Jul 22 06:01:40 PM PDT 24
Peak memory 206768 kb
Host smart-6e16bcd4-a59b-4ca0-b9c3-1f99be232feb
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2577415648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_in_transaction.2577415648
Directory /workspace/35.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_min_length_out_transaction.3374641714
Short name T2523
Test name
Test status
Simulation time 153623241 ps
CPU time 0.84 seconds
Started Jul 22 06:01:41 PM PDT 24
Finished Jul 22 06:01:43 PM PDT 24
Peak memory 206720 kb
Host smart-e0066d6d-e3c4-4da8-ac53-923050c503d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33746
41714 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_min_length_out_transaction.3374641714
Directory /workspace/35.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_nak_trans.2483791365
Short name T1021
Test name
Test status
Simulation time 225132947 ps
CPU time 0.9 seconds
Started Jul 22 06:01:42 PM PDT 24
Finished Jul 22 06:01:44 PM PDT 24
Peak memory 206752 kb
Host smart-f465c3fb-68b4-4995-a438-8d9fb53d12f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24837
91365 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_nak_trans.2483791365
Directory /workspace/35.usbdev_nak_trans/latest

Test location /workspace/coverage/default/35.usbdev_out_iso.2555823857
Short name T1764
Test name
Test status
Simulation time 187546071 ps
CPU time 0.94 seconds
Started Jul 22 06:01:42 PM PDT 24
Finished Jul 22 06:01:44 PM PDT 24
Peak memory 206752 kb
Host smart-7466a8c7-b76c-43ed-83d6-41d027498f90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25558
23857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_iso.2555823857
Directory /workspace/35.usbdev_out_iso/latest

Test location /workspace/coverage/default/35.usbdev_out_stall.1709580908
Short name T1546
Test name
Test status
Simulation time 177868466 ps
CPU time 0.82 seconds
Started Jul 22 06:01:44 PM PDT 24
Finished Jul 22 06:01:45 PM PDT 24
Peak memory 206756 kb
Host smart-5faa251a-b221-4573-a410-b46810a32fd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17095
80908 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_stall.1709580908
Directory /workspace/35.usbdev_out_stall/latest

Test location /workspace/coverage/default/35.usbdev_out_trans_nak.3303264646
Short name T2327
Test name
Test status
Simulation time 152827708 ps
CPU time 0.8 seconds
Started Jul 22 06:01:44 PM PDT 24
Finished Jul 22 06:01:45 PM PDT 24
Peak memory 206740 kb
Host smart-99c0bfcc-61e9-4194-b999-2dac61a41fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33032
64646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_out_trans_nak.3303264646
Directory /workspace/35.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/35.usbdev_pending_in_trans.3210058601
Short name T2099
Test name
Test status
Simulation time 160945435 ps
CPU time 0.81 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:01:55 PM PDT 24
Peak memory 206708 kb
Host smart-7c7ff2ee-d1fe-4690-9cd0-0ebf9458fc43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32100
58601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pending_in_trans.3210058601
Directory /workspace/35.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_pinflip.267924922
Short name T1006
Test name
Test status
Simulation time 235072319 ps
CPU time 0.95 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206752 kb
Host smart-75ab713a-a7e7-47dd-94b8-9b98dca41694
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=267924922 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_pinflip.267924922
Directory /workspace/35.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/35.usbdev_phy_config_usb_ref_disable.106421121
Short name T1957
Test name
Test status
Simulation time 147435172 ps
CPU time 0.71 seconds
Started Jul 22 06:01:56 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206728 kb
Host smart-da2d73ab-e4a0-4baa-8679-64cf6559bd6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10642
1121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_config_usb_ref_disable.106421121
Directory /workspace/35.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/35.usbdev_phy_pins_sense.2723165468
Short name T1243
Test name
Test status
Simulation time 63746329 ps
CPU time 0.71 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206744 kb
Host smart-dbb94da0-d201-4455-b678-b5cf0c680297
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27231
65468 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_phy_pins_sense.2723165468
Directory /workspace/35.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/35.usbdev_pkt_buffer.1121584345
Short name T1600
Test name
Test status
Simulation time 16824008949 ps
CPU time 38.45 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:02:30 PM PDT 24
Peak memory 206924 kb
Host smart-2137a889-485d-47e8-b265-834ef442a3f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11215
84345 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_buffer.1121584345
Directory /workspace/35.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/35.usbdev_pkt_received.3830444785
Short name T459
Test name
Test status
Simulation time 188535418 ps
CPU time 0.82 seconds
Started Jul 22 06:01:56 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206712 kb
Host smart-3ac41618-7dff-41e4-8455-11e1396a9523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38304
44785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_received.3830444785
Directory /workspace/35.usbdev_pkt_received/latest

Test location /workspace/coverage/default/35.usbdev_pkt_sent.1913190798
Short name T345
Test name
Test status
Simulation time 213577316 ps
CPU time 0.87 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206736 kb
Host smart-59f93f1e-8f6f-46c8-9445-f118006d6e52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19131
90798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_pkt_sent.1913190798
Directory /workspace/35.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/35.usbdev_random_length_in_transaction.2602876271
Short name T993
Test name
Test status
Simulation time 209885154 ps
CPU time 0.86 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206784 kb
Host smart-8a97dd70-d267-403a-ab0a-c286a2781d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26028
76271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_in_transaction.2602876271
Directory /workspace/35.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/35.usbdev_random_length_out_transaction.2455719659
Short name T1849
Test name
Test status
Simulation time 159170561 ps
CPU time 0.83 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206692 kb
Host smart-941b1ba7-5dfc-49ff-9929-2de8452cc39f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24557
19659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_random_length_out_transaction.2455719659
Directory /workspace/35.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/35.usbdev_rx_crc_err.3853657161
Short name T2319
Test name
Test status
Simulation time 162936635 ps
CPU time 0.76 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206724 kb
Host smart-747584be-bc5d-485e-8e00-2ff4873f63bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38536
57161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_rx_crc_err.3853657161
Directory /workspace/35.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/35.usbdev_setup_stage.18124522
Short name T89
Test name
Test status
Simulation time 164594143 ps
CPU time 0.77 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206792 kb
Host smart-c105eabe-0b91-4142-92f0-140fc4d13d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18124
522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_stage.18124522
Directory /workspace/35.usbdev_setup_stage/latest

Test location /workspace/coverage/default/35.usbdev_setup_trans_ignored.71511545
Short name T2196
Test name
Test status
Simulation time 179490596 ps
CPU time 0.82 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206700 kb
Host smart-681cb9d1-b639-4041-871b-03b7eeaa5d6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71511
545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_setup_trans_ignored.71511545
Directory /workspace/35.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/35.usbdev_smoke.591604316
Short name T1747
Test name
Test status
Simulation time 195443298 ps
CPU time 0.88 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206748 kb
Host smart-7cde453f-152f-400c-a99e-91b5eae03b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59160
4316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_smoke.591604316
Directory /workspace/35.usbdev_smoke/latest

Test location /workspace/coverage/default/35.usbdev_spurious_pids_ignored.4206895248
Short name T1978
Test name
Test status
Simulation time 6497886933 ps
CPU time 45.96 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206936 kb
Host smart-1b8335e6-6719-4eba-8a6f-6c22397d1572
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4206895248 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_spurious_pids_ignored.4206895248
Directory /workspace/35.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/35.usbdev_stall_priority_over_nak.1835606816
Short name T1459
Test name
Test status
Simulation time 182560679 ps
CPU time 0.84 seconds
Started Jul 22 06:01:49 PM PDT 24
Finished Jul 22 06:01:50 PM PDT 24
Peak memory 206700 kb
Host smart-bf43928c-08f6-4286-a12c-854fb86f9f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18356
06816 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_priority_over_nak.1835606816
Directory /workspace/35.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/35.usbdev_stall_trans.801054566
Short name T1865
Test name
Test status
Simulation time 198199104 ps
CPU time 0.84 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206732 kb
Host smart-7d72b1d6-66e8-4973-a67e-89e246c646e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80105
4566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stall_trans.801054566
Directory /workspace/35.usbdev_stall_trans/latest

Test location /workspace/coverage/default/35.usbdev_stream_len_max.3514006938
Short name T1545
Test name
Test status
Simulation time 898902077 ps
CPU time 2.18 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206896 kb
Host smart-50e297e3-7a7e-4143-96d8-97029d173b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35140
06938 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_stream_len_max.3514006938
Directory /workspace/35.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/35.usbdev_streaming_out.4164766731
Short name T1335
Test name
Test status
Simulation time 5686112503 ps
CPU time 55.68 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:02:47 PM PDT 24
Peak memory 206812 kb
Host smart-400341d9-72cb-4d05-8f1c-4fa8aa4600db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41647
66731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.usbdev_streaming_out.4164766731
Directory /workspace/35.usbdev_streaming_out/latest

Test location /workspace/coverage/default/36.usbdev_alert_test.910437281
Short name T2014
Test name
Test status
Simulation time 74873197 ps
CPU time 0.76 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:01:59 PM PDT 24
Peak memory 206740 kb
Host smart-5b9f83dc-bd51-48fd-9d19-11a620b85d6e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=910437281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_alert_test.910437281
Directory /workspace/36.usbdev_alert_test/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_disconnect.1117613215
Short name T2344
Test name
Test status
Simulation time 4242591776 ps
CPU time 5.95 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206724 kb
Host smart-b001c81c-b226-4260-b3c2-a748753f025d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1117613215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_disconnect.1117613215
Directory /workspace/36.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_reset.3640965782
Short name T2221
Test name
Test status
Simulation time 13415600462 ps
CPU time 14.24 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:17 PM PDT 24
Peak memory 206964 kb
Host smart-847961e9-c994-4ab4-ab27-d5c8dac40add
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3640965782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_reset.3640965782
Directory /workspace/36.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/36.usbdev_aon_wake_resume.3258653784
Short name T1919
Test name
Test status
Simulation time 23317767105 ps
CPU time 27.06 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206868 kb
Host smart-54d6dc3f-b96e-4afe-a0de-3b02efd63e21
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3258653784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_aon_wake_resume.3258653784
Directory /workspace/36.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/36.usbdev_av_buffer.3323415735
Short name T918
Test name
Test status
Simulation time 205362789 ps
CPU time 0.84 seconds
Started Jul 22 06:01:49 PM PDT 24
Finished Jul 22 06:01:50 PM PDT 24
Peak memory 206744 kb
Host smart-aaef66c7-aac7-4e3e-8b55-22b1d44ec294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33234
15735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_av_buffer.3323415735
Directory /workspace/36.usbdev_av_buffer/latest

Test location /workspace/coverage/default/36.usbdev_bitstuff_err.1591350006
Short name T362
Test name
Test status
Simulation time 155195895 ps
CPU time 0.79 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206672 kb
Host smart-e4ef297f-bd2d-49be-bd7b-3049047b2cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15913
50006 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_bitstuff_err.1591350006
Directory /workspace/36.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_clear.1122179408
Short name T1899
Test name
Test status
Simulation time 465577762 ps
CPU time 1.31 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206748 kb
Host smart-31a38d71-bd1b-46b8-abdb-14189afeaa37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11221
79408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_clear.1122179408
Directory /workspace/36.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/36.usbdev_data_toggle_restore.1015626710
Short name T2399
Test name
Test status
Simulation time 428114790 ps
CPU time 1.33 seconds
Started Jul 22 06:01:48 PM PDT 24
Finished Jul 22 06:01:50 PM PDT 24
Peak memory 206744 kb
Host smart-79ba7370-f320-43d2-a9a5-9005baa53b5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10156
26710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_data_toggle_restore.1015626710
Directory /workspace/36.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/36.usbdev_device_address.1168781398
Short name T571
Test name
Test status
Simulation time 7974527914 ps
CPU time 15.68 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:02:07 PM PDT 24
Peak memory 206972 kb
Host smart-3c1e13f6-4379-4e31-a172-0864375887d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11687
81398 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_device_address.1168781398
Directory /workspace/36.usbdev_device_address/latest

Test location /workspace/coverage/default/36.usbdev_disable_endpoint.4204978070
Short name T2520
Test name
Test status
Simulation time 364804565 ps
CPU time 1.18 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206508 kb
Host smart-1de3e664-633d-4865-b9a0-0aea842babd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42049
78070 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disable_endpoint.4204978070
Directory /workspace/36.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/36.usbdev_disconnected.1462136492
Short name T1094
Test name
Test status
Simulation time 149825465 ps
CPU time 0.76 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206744 kb
Host smart-df474216-d63a-46dd-b933-ad73e98ccb2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14621
36492 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_disconnected.1462136492
Directory /workspace/36.usbdev_disconnected/latest

Test location /workspace/coverage/default/36.usbdev_enable.1179738180
Short name T1795
Test name
Test status
Simulation time 31196678 ps
CPU time 0.66 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:04 PM PDT 24
Peak memory 206736 kb
Host smart-09a102ca-eb46-41be-861d-72d936a94bae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11797
38180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_enable.1179738180
Directory /workspace/36.usbdev_enable/latest

Test location /workspace/coverage/default/36.usbdev_endpoint_access.1338540432
Short name T1667
Test name
Test status
Simulation time 965547222 ps
CPU time 2.29 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:55 PM PDT 24
Peak memory 206940 kb
Host smart-24c03cf8-89d8-4906-91f3-17be1be42a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13385
40432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_endpoint_access.1338540432
Directory /workspace/36.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/36.usbdev_fifo_rst.1783065187
Short name T508
Test name
Test status
Simulation time 171958983 ps
CPU time 1.68 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:11 PM PDT 24
Peak memory 206788 kb
Host smart-d8767ea7-8a5c-41ca-a9c4-b42500ca7587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17830
65187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_fifo_rst.1783065187
Directory /workspace/36.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/36.usbdev_in_iso.346793109
Short name T2332
Test name
Test status
Simulation time 235798135 ps
CPU time 0.95 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206620 kb
Host smart-b7866f2e-5db3-4e30-8872-99f3361d1cce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34679
3109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_iso.346793109
Directory /workspace/36.usbdev_in_iso/latest

Test location /workspace/coverage/default/36.usbdev_in_stall.3149165689
Short name T109
Test name
Test status
Simulation time 141290762 ps
CPU time 0.74 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206748 kb
Host smart-af5e7d2e-3beb-4827-8544-baacbef17b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31491
65689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_stall.3149165689
Directory /workspace/36.usbdev_in_stall/latest

Test location /workspace/coverage/default/36.usbdev_in_trans.951438439
Short name T1030
Test name
Test status
Simulation time 172885071 ps
CPU time 0.79 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206660 kb
Host smart-70a8c647-6c1d-4e8a-9d3d-a7767af386cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95143
8439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_in_trans.951438439
Directory /workspace/36.usbdev_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_invalid_sync.1899899236
Short name T682
Test name
Test status
Simulation time 8978263395 ps
CPU time 252.13 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:06:04 PM PDT 24
Peak memory 206844 kb
Host smart-ed5b06bc-9748-4171-8d20-c95e2d0d4fe4
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1899899236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_invalid_sync.1899899236
Directory /workspace/36.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/36.usbdev_iso_retraction.2946027409
Short name T2663
Test name
Test status
Simulation time 5302603024 ps
CPU time 43.09 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206864 kb
Host smart-d0dfb5a9-d191-45fe-85b2-fadb91df8f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29460
27409 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_iso_retraction.2946027409
Directory /workspace/36.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/36.usbdev_link_in_err.621889706
Short name T1210
Test name
Test status
Simulation time 184540258 ps
CPU time 0.87 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206688 kb
Host smart-2f1f7299-d51c-437a-8ead-2efddf29fffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62188
9706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_in_err.621889706
Directory /workspace/36.usbdev_link_in_err/latest

Test location /workspace/coverage/default/36.usbdev_link_resume.1241576731
Short name T18
Test name
Test status
Simulation time 23323090220 ps
CPU time 24.24 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:02:16 PM PDT 24
Peak memory 206604 kb
Host smart-11f71eef-c54b-469f-81c5-6957d1571792
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12415
76731 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_resume.1241576731
Directory /workspace/36.usbdev_link_resume/latest

Test location /workspace/coverage/default/36.usbdev_link_suspend.3264679047
Short name T2282
Test name
Test status
Simulation time 3304529818 ps
CPU time 4.72 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:57 PM PDT 24
Peak memory 206820 kb
Host smart-f2e929ce-5bdf-4d02-b68e-59aa61999e08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32646
79047 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_link_suspend.3264679047
Directory /workspace/36.usbdev_link_suspend/latest

Test location /workspace/coverage/default/36.usbdev_low_speed_traffic.4000616229
Short name T2180
Test name
Test status
Simulation time 6662818208 ps
CPU time 174.85 seconds
Started Jul 22 06:01:49 PM PDT 24
Finished Jul 22 06:04:45 PM PDT 24
Peak memory 206900 kb
Host smart-24b36d3e-d738-4d3e-b0cd-abbf30b225dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40006
16229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_low_speed_traffic.4000616229
Directory /workspace/36.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/36.usbdev_max_inter_pkt_delay.3367079634
Short name T1259
Test name
Test status
Simulation time 4209959797 ps
CPU time 38.36 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:02:33 PM PDT 24
Peak memory 206892 kb
Host smart-49556a0a-19c7-4c84-a5e5-ec7113716a6f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3367079634 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_inter_pkt_delay.3367079634
Directory /workspace/36.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_max_length_in_transaction.2621348145
Short name T1729
Test name
Test status
Simulation time 281564791 ps
CPU time 0.97 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:01:55 PM PDT 24
Peak memory 206704 kb
Host smart-53c92a85-d187-4f0c-b878-c1338e5193ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2621348145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_in_transaction.2621348145
Directory /workspace/36.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_length_out_transaction.104459232
Short name T1942
Test name
Test status
Simulation time 206764972 ps
CPU time 0.9 seconds
Started Jul 22 06:01:48 PM PDT 24
Finished Jul 22 06:01:50 PM PDT 24
Peak memory 206748 kb
Host smart-4c44ca61-963c-4623-a409-78c588d1f223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10445
9232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_length_out_transaction.104459232
Directory /workspace/36.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_max_usb_traffic.2858888299
Short name T2080
Test name
Test status
Simulation time 3694681845 ps
CPU time 33.3 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:02:26 PM PDT 24
Peak memory 206856 kb
Host smart-9059e416-665f-4355-891a-c9557fbaa686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28588
88299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_max_usb_traffic.2858888299
Directory /workspace/36.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/36.usbdev_min_inter_pkt_delay.1169813761
Short name T969
Test name
Test status
Simulation time 6119721423 ps
CPU time 163.9 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:04:37 PM PDT 24
Peak memory 206888 kb
Host smart-9d1396f2-5259-42bc-8109-ffb9014405b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1169813761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_inter_pkt_delay.1169813761
Directory /workspace/36.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/36.usbdev_min_length_in_transaction.1442556637
Short name T30
Test name
Test status
Simulation time 156367070 ps
CPU time 0.78 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206728 kb
Host smart-cc05246b-a5a3-4faa-93c5-fe9f6cdcfa5b
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1442556637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_in_transaction.1442556637
Directory /workspace/36.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_min_length_out_transaction.3560691926
Short name T685
Test name
Test status
Simulation time 225103619 ps
CPU time 0.89 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206744 kb
Host smart-246b8ff0-2198-4d69-83bc-96a681098941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35606
91926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_min_length_out_transaction.3560691926
Directory /workspace/36.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_nak_trans.1944356865
Short name T125
Test name
Test status
Simulation time 256621468 ps
CPU time 1.11 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206772 kb
Host smart-6509896a-70aa-416b-b657-db5b56eb76b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19443
56865 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_nak_trans.1944356865
Directory /workspace/36.usbdev_nak_trans/latest

Test location /workspace/coverage/default/36.usbdev_out_iso.4162041174
Short name T2263
Test name
Test status
Simulation time 264483122 ps
CPU time 0.91 seconds
Started Jul 22 06:02:00 PM PDT 24
Finished Jul 22 06:02:01 PM PDT 24
Peak memory 206632 kb
Host smart-e45addf2-656f-47d7-baa1-3eea9c026eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41620
41174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_iso.4162041174
Directory /workspace/36.usbdev_out_iso/latest

Test location /workspace/coverage/default/36.usbdev_out_stall.1129217234
Short name T1413
Test name
Test status
Simulation time 173692797 ps
CPU time 0.82 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:01:55 PM PDT 24
Peak memory 206668 kb
Host smart-6a55048f-0db5-473d-a57f-7e555f708f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11292
17234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_stall.1129217234
Directory /workspace/36.usbdev_out_stall/latest

Test location /workspace/coverage/default/36.usbdev_out_trans_nak.194313363
Short name T1489
Test name
Test status
Simulation time 222673176 ps
CPU time 0.87 seconds
Started Jul 22 06:01:59 PM PDT 24
Finished Jul 22 06:02:01 PM PDT 24
Peak memory 206728 kb
Host smart-586f7a2e-4e15-474c-8998-d6332069c750
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19431
3363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_out_trans_nak.194313363
Directory /workspace/36.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/36.usbdev_pending_in_trans.3269463899
Short name T896
Test name
Test status
Simulation time 149452799 ps
CPU time 0.76 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206712 kb
Host smart-2961dd03-d6ba-47bc-aff3-f72574e7c753
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32694
63899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pending_in_trans.3269463899
Directory /workspace/36.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_pinflip.2890336654
Short name T1191
Test name
Test status
Simulation time 174472915 ps
CPU time 0.85 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206152 kb
Host smart-68c5b6a6-3a63-4746-a849-d7b03381385e
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2890336654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_pinflip.2890336654
Directory /workspace/36.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/36.usbdev_phy_config_usb_ref_disable.3951517525
Short name T1316
Test name
Test status
Simulation time 150610667 ps
CPU time 0.76 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206256 kb
Host smart-d6948137-2f5d-4ff1-ab5d-adf7214e52a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39515
17525 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_config_usb_ref_disable.3951517525
Directory /workspace/36.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/36.usbdev_phy_pins_sense.3824934114
Short name T2368
Test name
Test status
Simulation time 37391759 ps
CPU time 0.64 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:01:54 PM PDT 24
Peak memory 206636 kb
Host smart-b9efb2c5-e0cd-411f-8c97-0a1a8e30b860
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38249
34114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_phy_pins_sense.3824934114
Directory /workspace/36.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/36.usbdev_pkt_buffer.1485728996
Short name T253
Test name
Test status
Simulation time 17486623883 ps
CPU time 38.11 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:02:32 PM PDT 24
Peak memory 206948 kb
Host smart-312108a5-c9f0-418d-8932-62421b1d35e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14857
28996 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_buffer.1485728996
Directory /workspace/36.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/36.usbdev_pkt_received.3401428743
Short name T2723
Test name
Test status
Simulation time 158758531 ps
CPU time 0.8 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:01:59 PM PDT 24
Peak memory 206700 kb
Host smart-b12d9fca-6f3a-4d80-b037-2a84ca4f760c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34014
28743 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_received.3401428743
Directory /workspace/36.usbdev_pkt_received/latest

Test location /workspace/coverage/default/36.usbdev_pkt_sent.3462885787
Short name T434
Test name
Test status
Simulation time 209009636 ps
CPU time 0.83 seconds
Started Jul 22 06:02:00 PM PDT 24
Finished Jul 22 06:02:01 PM PDT 24
Peak memory 206576 kb
Host smart-cc9054b0-1c78-4442-847a-730cd1bfea7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34628
85787 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_pkt_sent.3462885787
Directory /workspace/36.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/36.usbdev_random_length_in_transaction.3315093010
Short name T1375
Test name
Test status
Simulation time 154382139 ps
CPU time 0.84 seconds
Started Jul 22 06:01:59 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206708 kb
Host smart-61037562-76f8-45c0-9c18-b62ff5928b1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33150
93010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_in_transaction.3315093010
Directory /workspace/36.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/36.usbdev_random_length_out_transaction.3715928969
Short name T1588
Test name
Test status
Simulation time 160374545 ps
CPU time 0.79 seconds
Started Jul 22 06:01:56 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206692 kb
Host smart-457f3090-4ac6-4b52-9aea-f2b78db3df5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37159
28969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_random_length_out_transaction.3715928969
Directory /workspace/36.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/36.usbdev_rx_crc_err.1120467379
Short name T1339
Test name
Test status
Simulation time 172584292 ps
CPU time 0.8 seconds
Started Jul 22 06:01:56 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206700 kb
Host smart-07b09fd1-0557-4331-9ea9-92218d20d722
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11204
67379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_rx_crc_err.1120467379
Directory /workspace/36.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/36.usbdev_setup_stage.4087978701
Short name T2625
Test name
Test status
Simulation time 210761805 ps
CPU time 0.86 seconds
Started Jul 22 06:01:50 PM PDT 24
Finished Jul 22 06:01:52 PM PDT 24
Peak memory 206792 kb
Host smart-8aa58598-91e2-473d-8de0-b424871f5cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40879
78701 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_stage.4087978701
Directory /workspace/36.usbdev_setup_stage/latest

Test location /workspace/coverage/default/36.usbdev_setup_trans_ignored.1422824380
Short name T1308
Test name
Test status
Simulation time 150480956 ps
CPU time 0.82 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206760 kb
Host smart-7e37cbce-7a3f-4672-8816-1fa7f7614768
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14228
24380 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_setup_trans_ignored.1422824380
Directory /workspace/36.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/36.usbdev_smoke.3529492441
Short name T2431
Test name
Test status
Simulation time 244010735 ps
CPU time 0.9 seconds
Started Jul 22 06:01:52 PM PDT 24
Finished Jul 22 06:01:53 PM PDT 24
Peak memory 206860 kb
Host smart-adcc7445-8278-4f1b-bd4d-7ad70404d107
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35294
92441 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_smoke.3529492441
Directory /workspace/36.usbdev_smoke/latest

Test location /workspace/coverage/default/36.usbdev_spurious_pids_ignored.1456919299
Short name T540
Test name
Test status
Simulation time 5271005047 ps
CPU time 38.41 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:02:34 PM PDT 24
Peak memory 206880 kb
Host smart-5f92db55-3880-4185-b276-eb971da9db45
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1456919299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_spurious_pids_ignored.1456919299
Directory /workspace/36.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/36.usbdev_stall_priority_over_nak.1982162848
Short name T1570
Test name
Test status
Simulation time 184664313 ps
CPU time 0.79 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:01:57 PM PDT 24
Peak memory 206732 kb
Host smart-e07be535-58d9-47c0-b03a-74821addacac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19821
62848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_priority_over_nak.1982162848
Directory /workspace/36.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/36.usbdev_stall_trans.2327002887
Short name T760
Test name
Test status
Simulation time 160201501 ps
CPU time 0.78 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206744 kb
Host smart-3b7a54f4-8570-4b35-8dce-d0ded987246c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23270
02887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stall_trans.2327002887
Directory /workspace/36.usbdev_stall_trans/latest

Test location /workspace/coverage/default/36.usbdev_stream_len_max.3728698724
Short name T2031
Test name
Test status
Simulation time 1020908939 ps
CPU time 2.6 seconds
Started Jul 22 06:02:01 PM PDT 24
Finished Jul 22 06:02:04 PM PDT 24
Peak memory 206876 kb
Host smart-f83cb0e7-3f04-4d34-81c7-f3b0654fc4c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37286
98724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_stream_len_max.3728698724
Directory /workspace/36.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/36.usbdev_streaming_out.4156846367
Short name T1419
Test name
Test status
Simulation time 8132046652 ps
CPU time 61.22 seconds
Started Jul 22 06:01:51 PM PDT 24
Finished Jul 22 06:02:54 PM PDT 24
Peak memory 206948 kb
Host smart-c7e95320-57fd-4e4a-b1fb-8ba075ddf163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41568
46367 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.usbdev_streaming_out.4156846367
Directory /workspace/36.usbdev_streaming_out/latest

Test location /workspace/coverage/default/37.usbdev_alert_test.2549233742
Short name T2008
Test name
Test status
Simulation time 49685310 ps
CPU time 0.67 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 206696 kb
Host smart-28f00e9c-da44-46d8-bf53-81c5de31f3c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2549233742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_alert_test.2549233742
Directory /workspace/37.usbdev_alert_test/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_disconnect.32780756
Short name T2295
Test name
Test status
Simulation time 4363618758 ps
CPU time 5.05 seconds
Started Jul 22 06:01:59 PM PDT 24
Finished Jul 22 06:02:05 PM PDT 24
Peak memory 206916 kb
Host smart-8daeb44f-222a-4c91-87e0-e94954a2d9ae
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=32780756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_disconnect.32780756
Directory /workspace/37.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_reset.866159161
Short name T1418
Test name
Test status
Simulation time 13333179884 ps
CPU time 14.73 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206880 kb
Host smart-cada968c-a512-4f5d-9860-ad40c59f7c06
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=866159161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_reset.866159161
Directory /workspace/37.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/37.usbdev_aon_wake_resume.1482270742
Short name T628
Test name
Test status
Simulation time 23396881491 ps
CPU time 24.59 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206820 kb
Host smart-0d05a6af-83b0-4d13-b1f7-d07d4fea17aa
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1482270742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_aon_wake_resume.1482270742
Directory /workspace/37.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/37.usbdev_av_buffer.156674359
Short name T2195
Test name
Test status
Simulation time 207967933 ps
CPU time 0.86 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:01:59 PM PDT 24
Peak memory 206744 kb
Host smart-9843b6c0-579c-46ac-8f89-48de88a80321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15667
4359 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_av_buffer.156674359
Directory /workspace/37.usbdev_av_buffer/latest

Test location /workspace/coverage/default/37.usbdev_bitstuff_err.107010587
Short name T69
Test name
Test status
Simulation time 149203080 ps
CPU time 0.78 seconds
Started Jul 22 06:01:55 PM PDT 24
Finished Jul 22 06:01:57 PM PDT 24
Peak memory 206748 kb
Host smart-236c4b95-3f36-4d46-b976-ac9e9680c2a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10701
0587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_bitstuff_err.107010587
Directory /workspace/37.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_clear.2926381435
Short name T835
Test name
Test status
Simulation time 237355492 ps
CPU time 1.01 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206756 kb
Host smart-91f264cd-8828-4542-b1c3-d62d34c677a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29263
81435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_clear.2926381435
Directory /workspace/37.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/37.usbdev_data_toggle_restore.1471438193
Short name T959
Test name
Test status
Simulation time 498878380 ps
CPU time 1.23 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:01:56 PM PDT 24
Peak memory 206776 kb
Host smart-573e557f-3830-4706-ae4d-f5fe536ebd8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14714
38193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_data_toggle_restore.1471438193
Directory /workspace/37.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/37.usbdev_device_address.2816586830
Short name T1911
Test name
Test status
Simulation time 23539806068 ps
CPU time 47.35 seconds
Started Jul 22 06:01:54 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206844 kb
Host smart-37d3f4fa-583f-4797-96e3-b700455f7b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28165
86830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_device_address.2816586830
Directory /workspace/37.usbdev_device_address/latest

Test location /workspace/coverage/default/37.usbdev_disable_endpoint.2788517502
Short name T1464
Test name
Test status
Simulation time 304032477 ps
CPU time 1.14 seconds
Started Jul 22 06:01:59 PM PDT 24
Finished Jul 22 06:02:01 PM PDT 24
Peak memory 206712 kb
Host smart-800fceba-0ee5-4f6e-b8fe-4a43e511cddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27885
17502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disable_endpoint.2788517502
Directory /workspace/37.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/37.usbdev_disconnected.3706007250
Short name T2472
Test name
Test status
Simulation time 148994344 ps
CPU time 0.77 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206752 kb
Host smart-ca73bc19-b86d-4864-948b-94e50231979f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37060
07250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_disconnected.3706007250
Directory /workspace/37.usbdev_disconnected/latest

Test location /workspace/coverage/default/37.usbdev_enable.1354578866
Short name T2071
Test name
Test status
Simulation time 42615942 ps
CPU time 0.64 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206752 kb
Host smart-7ca2c538-8f2f-4c9b-9107-83069672aab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13545
78866 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_enable.1354578866
Directory /workspace/37.usbdev_enable/latest

Test location /workspace/coverage/default/37.usbdev_endpoint_access.2403000237
Short name T142
Test name
Test status
Simulation time 964892108 ps
CPU time 2.4 seconds
Started Jul 22 06:01:56 PM PDT 24
Finished Jul 22 06:01:59 PM PDT 24
Peak memory 206828 kb
Host smart-b4af101e-39c1-40fe-b857-81538aa45533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24030
00237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_endpoint_access.2403000237
Directory /workspace/37.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/37.usbdev_fifo_rst.4235290314
Short name T1343
Test name
Test status
Simulation time 221846505 ps
CPU time 1.25 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206856 kb
Host smart-69baf6cb-0c0c-4f0d-ab23-f27b2c90dd40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
90314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_fifo_rst.4235290314
Directory /workspace/37.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/37.usbdev_in_iso.1363004869
Short name T530
Test name
Test status
Simulation time 215459629 ps
CPU time 0.92 seconds
Started Jul 22 06:01:56 PM PDT 24
Finished Jul 22 06:01:58 PM PDT 24
Peak memory 206736 kb
Host smart-9682ff1c-00e6-4680-9fa3-a940410d7d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13630
04869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_iso.1363004869
Directory /workspace/37.usbdev_in_iso/latest

Test location /workspace/coverage/default/37.usbdev_in_stall.503406535
Short name T1047
Test name
Test status
Simulation time 153860675 ps
CPU time 0.75 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206756 kb
Host smart-6ae8a85d-a256-439d-88a0-6623839674c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50340
6535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_stall.503406535
Directory /workspace/37.usbdev_in_stall/latest

Test location /workspace/coverage/default/37.usbdev_in_trans.676214111
Short name T2215
Test name
Test status
Simulation time 268433160 ps
CPU time 0.95 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206748 kb
Host smart-cda11da2-9cbd-4fa3-abe9-81d4f95eaa48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67621
4111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_in_trans.676214111
Directory /workspace/37.usbdev_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_invalid_sync.3664514733
Short name T1412
Test name
Test status
Simulation time 5002322081 ps
CPU time 35.96 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:02:34 PM PDT 24
Peak memory 206876 kb
Host smart-ce80e3c4-d6ff-4d2e-bed1-cf0c8bdd685f
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3664514733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_invalid_sync.3664514733
Directory /workspace/37.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/37.usbdev_link_in_err.1640757274
Short name T407
Test name
Test status
Simulation time 233499515 ps
CPU time 0.89 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206748 kb
Host smart-bcb70931-e842-4800-ad9f-98ae9c2d4b9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16407
57274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_in_err.1640757274
Directory /workspace/37.usbdev_link_in_err/latest

Test location /workspace/coverage/default/37.usbdev_link_resume.2424441641
Short name T2217
Test name
Test status
Simulation time 23355427502 ps
CPU time 28.01 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206784 kb
Host smart-1e252b25-7069-403d-af09-75fc509e42ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24244
41641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_resume.2424441641
Directory /workspace/37.usbdev_link_resume/latest

Test location /workspace/coverage/default/37.usbdev_link_suspend.1112546103
Short name T728
Test name
Test status
Simulation time 3333564447 ps
CPU time 3.92 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:02:03 PM PDT 24
Peak memory 206816 kb
Host smart-74fc1893-3025-4fe6-96d2-e05e4ce3b334
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11125
46103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_link_suspend.1112546103
Directory /workspace/37.usbdev_link_suspend/latest

Test location /workspace/coverage/default/37.usbdev_low_speed_traffic.660912704
Short name T147
Test name
Test status
Simulation time 6257143497 ps
CPU time 41.66 seconds
Started Jul 22 06:01:56 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206964 kb
Host smart-1b36da44-3280-47b0-98cb-091591b88716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66091
2704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_low_speed_traffic.660912704
Directory /workspace/37.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/37.usbdev_max_inter_pkt_delay.1726014444
Short name T173
Test name
Test status
Simulation time 5865082392 ps
CPU time 153.99 seconds
Started Jul 22 06:02:02 PM PDT 24
Finished Jul 22 06:04:36 PM PDT 24
Peak memory 206900 kb
Host smart-83a64529-ba05-45f7-89e4-4bbace3ebef5
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1726014444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_inter_pkt_delay.1726014444
Directory /workspace/37.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_max_length_in_transaction.1682427620
Short name T1057
Test name
Test status
Simulation time 246508146 ps
CPU time 0.9 seconds
Started Jul 22 06:01:58 PM PDT 24
Finished Jul 22 06:02:00 PM PDT 24
Peak memory 206752 kb
Host smart-75ccbade-3d1b-4326-bbdc-423f66f14eb8
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1682427620 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_in_transaction.1682427620
Directory /workspace/37.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_length_out_transaction.3649551119
Short name T424
Test name
Test status
Simulation time 192126344 ps
CPU time 0.94 seconds
Started Jul 22 06:01:57 PM PDT 24
Finished Jul 22 06:01:59 PM PDT 24
Peak memory 206752 kb
Host smart-47ed9513-a502-47e3-96b8-78c123ac2e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36495
51119 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_length_out_transaction.3649551119
Directory /workspace/37.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_max_usb_traffic.4250246242
Short name T777
Test name
Test status
Simulation time 5142325640 ps
CPU time 142.77 seconds
Started Jul 22 06:01:53 PM PDT 24
Finished Jul 22 06:04:17 PM PDT 24
Peak memory 206908 kb
Host smart-d2038680-b30d-443e-9441-bff94636f4b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42502
46242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_max_usb_traffic.4250246242
Directory /workspace/37.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/37.usbdev_min_inter_pkt_delay.2615508538
Short name T2056
Test name
Test status
Simulation time 5104177477 ps
CPU time 145.16 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:04:33 PM PDT 24
Peak memory 206932 kb
Host smart-905d89b6-ac15-4ebb-a666-2ef7b7866f1f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2615508538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_inter_pkt_delay.2615508538
Directory /workspace/37.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/37.usbdev_min_length_in_transaction.1837093462
Short name T2652
Test name
Test status
Simulation time 159453613 ps
CPU time 0.8 seconds
Started Jul 22 06:02:02 PM PDT 24
Finished Jul 22 06:02:03 PM PDT 24
Peak memory 206748 kb
Host smart-7de9f57e-612b-4c6c-aaae-7c32ef1f8c3f
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1837093462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_in_transaction.1837093462
Directory /workspace/37.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_min_length_out_transaction.4001874284
Short name T359
Test name
Test status
Simulation time 157691338 ps
CPU time 0.8 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206752 kb
Host smart-4e51dfbe-b04d-4fcb-85bf-af79ede7c6b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40018
74284 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_min_length_out_transaction.4001874284
Directory /workspace/37.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_nak_trans.517029990
Short name T1711
Test name
Test status
Simulation time 215451462 ps
CPU time 0.85 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206724 kb
Host smart-f29c96ef-4020-4de1-b319-f4365f84de1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51702
9990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_nak_trans.517029990
Directory /workspace/37.usbdev_nak_trans/latest

Test location /workspace/coverage/default/37.usbdev_out_iso.995168796
Short name T2219
Test name
Test status
Simulation time 203886226 ps
CPU time 0.95 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206744 kb
Host smart-059f925c-0bf0-4230-8137-a07e21e50046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99516
8796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_iso.995168796
Directory /workspace/37.usbdev_out_iso/latest

Test location /workspace/coverage/default/37.usbdev_out_stall.195449698
Short name T2499
Test name
Test status
Simulation time 254946539 ps
CPU time 0.87 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206752 kb
Host smart-b1220f80-a4ca-49f6-972b-9d5c156c5c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19544
9698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_stall.195449698
Directory /workspace/37.usbdev_out_stall/latest

Test location /workspace/coverage/default/37.usbdev_out_trans_nak.1856402933
Short name T1553
Test name
Test status
Simulation time 192836616 ps
CPU time 0.88 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206756 kb
Host smart-4b3337cd-554a-4057-a26a-5031fafb1eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18564
02933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_out_trans_nak.1856402933
Directory /workspace/37.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/37.usbdev_pending_in_trans.2048685179
Short name T1242
Test name
Test status
Simulation time 149568914 ps
CPU time 0.79 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206756 kb
Host smart-2f4ee77a-ef8c-47db-91b3-25fb3b2452f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
85179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pending_in_trans.2048685179
Directory /workspace/37.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_pinflip.130559984
Short name T1503
Test name
Test status
Simulation time 217187328 ps
CPU time 0.95 seconds
Started Jul 22 06:02:08 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206756 kb
Host smart-38d27b91-4843-4d9e-b120-d31a7698351a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=130559984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_pinflip.130559984
Directory /workspace/37.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/37.usbdev_phy_config_usb_ref_disable.3160175377
Short name T863
Test name
Test status
Simulation time 176022466 ps
CPU time 0.79 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206720 kb
Host smart-49e9ab7c-1371-47d5-9287-6188ed7ca5f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31601
75377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_config_usb_ref_disable.3160175377
Directory /workspace/37.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/37.usbdev_phy_pins_sense.2534435689
Short name T2330
Test name
Test status
Simulation time 36984552 ps
CPU time 0.69 seconds
Started Jul 22 06:02:01 PM PDT 24
Finished Jul 22 06:02:03 PM PDT 24
Peak memory 206680 kb
Host smart-12b35318-82d2-4f81-8d96-461658d20c68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25344
35689 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_phy_pins_sense.2534435689
Directory /workspace/37.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/37.usbdev_pkt_buffer.2046519187
Short name T2464
Test name
Test status
Simulation time 20457055907 ps
CPU time 43.39 seconds
Started Jul 22 06:04:12 PM PDT 24
Finished Jul 22 06:04:56 PM PDT 24
Peak memory 206940 kb
Host smart-0761fb56-4a59-46f6-b309-bb6b82ffe7a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20465
19187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_buffer.2046519187
Directory /workspace/37.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/37.usbdev_pkt_received.962221811
Short name T431
Test name
Test status
Simulation time 175416142 ps
CPU time 0.86 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206756 kb
Host smart-702c201b-e1b3-495c-98ef-8686a9d5e4c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96222
1811 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_received.962221811
Directory /workspace/37.usbdev_pkt_received/latest

Test location /workspace/coverage/default/37.usbdev_pkt_sent.20339255
Short name T2712
Test name
Test status
Simulation time 214862313 ps
CPU time 0.89 seconds
Started Jul 22 06:02:01 PM PDT 24
Finished Jul 22 06:02:03 PM PDT 24
Peak memory 206904 kb
Host smart-5e146b64-8fe9-4b5a-95c3-e21759323302
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20339
255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_pkt_sent.20339255
Directory /workspace/37.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/37.usbdev_random_length_in_transaction.3815382219
Short name T1393
Test name
Test status
Simulation time 227844075 ps
CPU time 0.89 seconds
Started Jul 22 06:02:05 PM PDT 24
Finished Jul 22 06:02:07 PM PDT 24
Peak memory 206728 kb
Host smart-f5d090e9-e8e3-412f-b94b-9138e21834ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38153
82219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_in_transaction.3815382219
Directory /workspace/37.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/37.usbdev_random_length_out_transaction.4134856738
Short name T1432
Test name
Test status
Simulation time 167932278 ps
CPU time 0.83 seconds
Started Jul 22 06:02:03 PM PDT 24
Finished Jul 22 06:02:04 PM PDT 24
Peak memory 206724 kb
Host smart-e002255a-d932-4f96-ba98-dfb52bc85489
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41348
56738 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_random_length_out_transaction.4134856738
Directory /workspace/37.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/37.usbdev_rx_crc_err.3282049727
Short name T2408
Test name
Test status
Simulation time 132128798 ps
CPU time 0.74 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206752 kb
Host smart-66f50432-4b38-48c2-9443-14c63675dd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32820
49727 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_rx_crc_err.3282049727
Directory /workspace/37.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/37.usbdev_setup_stage.235372545
Short name T1438
Test name
Test status
Simulation time 148113678 ps
CPU time 0.8 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206732 kb
Host smart-fedc4cb2-a548-4a75-a169-bfa5e315c4b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23537
2545 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_stage.235372545
Directory /workspace/37.usbdev_setup_stage/latest

Test location /workspace/coverage/default/37.usbdev_setup_trans_ignored.744703844
Short name T1010
Test name
Test status
Simulation time 161408804 ps
CPU time 0.77 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:09 PM PDT 24
Peak memory 206744 kb
Host smart-992aed3e-2c02-45dd-a278-6b16912885c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74470
3844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_setup_trans_ignored.744703844
Directory /workspace/37.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/37.usbdev_smoke.1824748754
Short name T2060
Test name
Test status
Simulation time 213877474 ps
CPU time 0.93 seconds
Started Jul 22 06:02:10 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206596 kb
Host smart-217e4dd8-a20b-4aa2-95f0-38c153ef1fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247
48754 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_smoke.1824748754
Directory /workspace/37.usbdev_smoke/latest

Test location /workspace/coverage/default/37.usbdev_spurious_pids_ignored.2702501726
Short name T2681
Test name
Test status
Simulation time 5654713006 ps
CPU time 49.99 seconds
Started Jul 22 06:02:05 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206956 kb
Host smart-01aaf66d-b437-4217-9a16-a7fc8f199213
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2702501726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_spurious_pids_ignored.2702501726
Directory /workspace/37.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/37.usbdev_stall_priority_over_nak.921787532
Short name T829
Test name
Test status
Simulation time 177347746 ps
CPU time 0.8 seconds
Started Jul 22 06:04:07 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 206712 kb
Host smart-e26108fb-c1fa-4589-96cd-14705ba00c8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92178
7532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_priority_over_nak.921787532
Directory /workspace/37.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/37.usbdev_stall_trans.742142552
Short name T422
Test name
Test status
Simulation time 156151834 ps
CPU time 0.8 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206752 kb
Host smart-0ed0570c-799b-46a9-a100-2ccc314bef0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74214
2552 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stall_trans.742142552
Directory /workspace/37.usbdev_stall_trans/latest

Test location /workspace/coverage/default/37.usbdev_stream_len_max.3571755849
Short name T2529
Test name
Test status
Simulation time 1376646394 ps
CPU time 2.92 seconds
Started Jul 22 06:02:04 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206888 kb
Host smart-1215c342-f414-4f43-85e5-6b52c26d5f21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
55849 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_stream_len_max.3571755849
Directory /workspace/37.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/37.usbdev_streaming_out.104180232
Short name T910
Test name
Test status
Simulation time 5577884632 ps
CPU time 146.43 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:04:36 PM PDT 24
Peak memory 207064 kb
Host smart-f52184a8-aee1-484c-84bb-dee21177fe6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10418
0232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.usbdev_streaming_out.104180232
Directory /workspace/37.usbdev_streaming_out/latest

Test location /workspace/coverage/default/38.usbdev_alert_test.83502622
Short name T1927
Test name
Test status
Simulation time 61716677 ps
CPU time 0.68 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206748 kb
Host smart-ce00e753-df78-441a-bfae-1a909307b207
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=83502622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_alert_test.83502622
Directory /workspace/38.usbdev_alert_test/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_disconnect.3323359579
Short name T2737
Test name
Test status
Simulation time 4345005310 ps
CPU time 5.1 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:13 PM PDT 24
Peak memory 206828 kb
Host smart-6968a015-5b2c-4b6f-be97-1fb87e992d59
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3323359579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_disconnect.3323359579
Directory /workspace/38.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_reset.1118490599
Short name T1658
Test name
Test status
Simulation time 13374275042 ps
CPU time 12.54 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206820 kb
Host smart-07fc68cd-bf0b-4d54-bcee-41219853b50a
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1118490599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_reset.1118490599
Directory /workspace/38.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/38.usbdev_aon_wake_resume.1892439855
Short name T2024
Test name
Test status
Simulation time 23343502984 ps
CPU time 29.8 seconds
Started Jul 22 06:02:08 PM PDT 24
Finished Jul 22 06:02:39 PM PDT 24
Peak memory 206812 kb
Host smart-4fd23d98-9697-4ce7-8a13-8235fc0d42e1
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1892439855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_aon_wake_resume.1892439855
Directory /workspace/38.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/38.usbdev_av_buffer.2965280703
Short name T1193
Test name
Test status
Simulation time 181302887 ps
CPU time 0.85 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206736 kb
Host smart-2c76fd2f-fa9f-4421-b6b2-a42d56d7b7a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29652
80703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_av_buffer.2965280703
Directory /workspace/38.usbdev_av_buffer/latest

Test location /workspace/coverage/default/38.usbdev_bitstuff_err.67757847
Short name T1527
Test name
Test status
Simulation time 179041273 ps
CPU time 0.8 seconds
Started Jul 22 06:02:03 PM PDT 24
Finished Jul 22 06:02:04 PM PDT 24
Peak memory 206748 kb
Host smart-8f501a03-d357-4b8a-b9e3-4bfe288bd008
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67757
847 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_bitstuff_err.67757847
Directory /workspace/38.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_clear.2667076483
Short name T951
Test name
Test status
Simulation time 471506083 ps
CPU time 1.35 seconds
Started Jul 22 06:04:07 PM PDT 24
Finished Jul 22 06:04:09 PM PDT 24
Peak memory 206692 kb
Host smart-8519ccab-200a-4598-8a93-0cfc1cb1896a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26670
76483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_clear.2667076483
Directory /workspace/38.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/38.usbdev_data_toggle_restore.2613693454
Short name T849
Test name
Test status
Simulation time 719892266 ps
CPU time 1.96 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206876 kb
Host smart-b00042e5-4564-4abd-b453-f88be6d8cfc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26136
93454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_data_toggle_restore.2613693454
Directory /workspace/38.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/38.usbdev_device_address.3172921506
Short name T95
Test name
Test status
Simulation time 17416553214 ps
CPU time 31.69 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:46 PM PDT 24
Peak memory 206848 kb
Host smart-c64c9904-2d6e-461b-b288-d77935254f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31729
21506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_device_address.3172921506
Directory /workspace/38.usbdev_device_address/latest

Test location /workspace/coverage/default/38.usbdev_disable_endpoint.4263418846
Short name T598
Test name
Test status
Simulation time 487526303 ps
CPU time 1.55 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:02:13 PM PDT 24
Peak memory 206708 kb
Host smart-44cfedf8-a1e8-4440-8c2e-9400f319c70f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42634
18846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disable_endpoint.4263418846
Directory /workspace/38.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/38.usbdev_disconnected.2365009126
Short name T1219
Test name
Test status
Simulation time 150574135 ps
CPU time 0.76 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206752 kb
Host smart-dfa333fa-09f5-4b62-8478-081683bf4d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23650
09126 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_disconnected.2365009126
Directory /workspace/38.usbdev_disconnected/latest

Test location /workspace/coverage/default/38.usbdev_enable.4238066007
Short name T1813
Test name
Test status
Simulation time 31334197 ps
CPU time 0.65 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206740 kb
Host smart-d8462c36-a5cb-4079-a7cf-055f558239f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42380
66007 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_enable.4238066007
Directory /workspace/38.usbdev_enable/latest

Test location /workspace/coverage/default/38.usbdev_endpoint_access.2474320388
Short name T2597
Test name
Test status
Simulation time 864849660 ps
CPU time 1.98 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206860 kb
Host smart-32fbec83-c8dd-4104-8bb1-9cf89bb06c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24743
20388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_endpoint_access.2474320388
Directory /workspace/38.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/38.usbdev_fifo_rst.471153063
Short name T1989
Test name
Test status
Simulation time 260647655 ps
CPU time 1.59 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206964 kb
Host smart-08af6962-bf1f-4b6a-b79c-9af5b9d7f0b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47115
3063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_fifo_rst.471153063
Directory /workspace/38.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/38.usbdev_in_iso.3028266267
Short name T1844
Test name
Test status
Simulation time 180375561 ps
CPU time 0.83 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206744 kb
Host smart-095e4f35-ed49-4dd8-bd42-f3ddc3770c26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30282
66267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_iso.3028266267
Directory /workspace/38.usbdev_in_iso/latest

Test location /workspace/coverage/default/38.usbdev_in_stall.1033355920
Short name T248
Test name
Test status
Simulation time 146725987 ps
CPU time 0.74 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206748 kb
Host smart-667d48c8-81ef-49a1-b902-cc585f71f53f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10333
55920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_stall.1033355920
Directory /workspace/38.usbdev_in_stall/latest

Test location /workspace/coverage/default/38.usbdev_in_trans.3298811698
Short name T2077
Test name
Test status
Simulation time 219012676 ps
CPU time 0.85 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206724 kb
Host smart-fc005a64-6597-4fbb-959b-edee7f72cace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32988
11698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_in_trans.3298811698
Directory /workspace/38.usbdev_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_invalid_sync.1946284450
Short name T1757
Test name
Test status
Simulation time 7080745419 ps
CPU time 63.92 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:03:15 PM PDT 24
Peak memory 206892 kb
Host smart-7c2cb118-1c16-4f7c-9c4a-87bf7c125c79
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1946284450 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_invalid_sync.1946284450
Directory /workspace/38.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/38.usbdev_iso_retraction.4154461677
Short name T170
Test name
Test status
Simulation time 6276060173 ps
CPU time 58.63 seconds
Started Jul 22 06:02:08 PM PDT 24
Finished Jul 22 06:03:08 PM PDT 24
Peak memory 206900 kb
Host smart-ac499300-c343-4cef-b084-db868f0f85eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41544
61677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_iso_retraction.4154461677
Directory /workspace/38.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/38.usbdev_link_in_err.1283181513
Short name T2100
Test name
Test status
Simulation time 241144957 ps
CPU time 0.88 seconds
Started Jul 22 06:02:08 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206868 kb
Host smart-1ec92c65-04e5-490f-b625-c13e27666f97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12831
81513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_in_err.1283181513
Directory /workspace/38.usbdev_link_in_err/latest

Test location /workspace/coverage/default/38.usbdev_link_resume.1329945121
Short name T694
Test name
Test status
Simulation time 23337370005 ps
CPU time 26.96 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:44 PM PDT 24
Peak memory 206796 kb
Host smart-059fd28d-4a26-4a16-a10c-a54100549bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
45121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_resume.1329945121
Directory /workspace/38.usbdev_link_resume/latest

Test location /workspace/coverage/default/38.usbdev_link_suspend.3789144588
Short name T524
Test name
Test status
Simulation time 3341555390 ps
CPU time 4.08 seconds
Started Jul 22 06:04:06 PM PDT 24
Finished Jul 22 06:04:11 PM PDT 24
Peak memory 206776 kb
Host smart-57f04786-9477-404e-85d8-360fac26f6fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37891
44588 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_link_suspend.3789144588
Directory /workspace/38.usbdev_link_suspend/latest

Test location /workspace/coverage/default/38.usbdev_low_speed_traffic.2108865835
Short name T1290
Test name
Test status
Simulation time 6705949898 ps
CPU time 64.35 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206948 kb
Host smart-4346c6dc-c6c4-432f-b033-079d77cb8c5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21088
65835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_low_speed_traffic.2108865835
Directory /workspace/38.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/38.usbdev_max_inter_pkt_delay.252995100
Short name T625
Test name
Test status
Simulation time 7519033691 ps
CPU time 206.16 seconds
Started Jul 22 06:02:04 PM PDT 24
Finished Jul 22 06:05:31 PM PDT 24
Peak memory 206880 kb
Host smart-c280b99b-9f65-4ba1-b9e5-f500e41a6c0c
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=252995100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_inter_pkt_delay.252995100
Directory /workspace/38.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_max_length_in_transaction.926246509
Short name T1443
Test name
Test status
Simulation time 240586803 ps
CPU time 0.96 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206752 kb
Host smart-b85f07d8-7cd8-460e-8f3d-cc150807c377
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=926246509 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_in_transaction.926246509
Directory /workspace/38.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_length_out_transaction.2070062352
Short name T1301
Test name
Test status
Simulation time 213448958 ps
CPU time 0.87 seconds
Started Jul 22 06:02:10 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206708 kb
Host smart-648456ee-0721-401c-88be-c7d5f77df961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20700
62352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_length_out_transaction.2070062352
Directory /workspace/38.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_max_usb_traffic.899090903
Short name T584
Test name
Test status
Simulation time 6371998237 ps
CPU time 57.26 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:03:14 PM PDT 24
Peak memory 206888 kb
Host smart-5024f128-23bc-46e1-a0f8-2f478b5b21d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89909
0903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_max_usb_traffic.899090903
Directory /workspace/38.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/38.usbdev_min_inter_pkt_delay.2908658687
Short name T488
Test name
Test status
Simulation time 5419243300 ps
CPU time 38.77 seconds
Started Jul 22 06:02:12 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206900 kb
Host smart-3e8714e7-5a03-402a-a3df-7b9c68f5c0b6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2908658687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_inter_pkt_delay.2908658687
Directory /workspace/38.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/38.usbdev_min_length_in_transaction.1304326407
Short name T1303
Test name
Test status
Simulation time 153076279 ps
CPU time 0.8 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206580 kb
Host smart-a8dbdc31-5585-4e8c-be9f-98f684ba2536
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1304326407 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_in_transaction.1304326407
Directory /workspace/38.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_min_length_out_transaction.428056995
Short name T2369
Test name
Test status
Simulation time 146457124 ps
CPU time 0.78 seconds
Started Jul 22 06:04:07 PM PDT 24
Finished Jul 22 06:04:09 PM PDT 24
Peak memory 206708 kb
Host smart-7daaed8d-97a9-4ab0-ab7c-f98e10c9e9cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42805
6995 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_min_length_out_transaction.428056995
Directory /workspace/38.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_nak_trans.3967219726
Short name T120
Test name
Test status
Simulation time 217789732 ps
CPU time 0.85 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206720 kb
Host smart-32650a9d-c951-40bb-9c07-f54632be70c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39672
19726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_nak_trans.3967219726
Directory /workspace/38.usbdev_nak_trans/latest

Test location /workspace/coverage/default/38.usbdev_out_iso.1434524769
Short name T98
Test name
Test status
Simulation time 157537417 ps
CPU time 0.84 seconds
Started Jul 22 06:02:12 PM PDT 24
Finished Jul 22 06:02:14 PM PDT 24
Peak memory 206748 kb
Host smart-1647d630-7b91-4caa-b028-950822f45597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14345
24769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_iso.1434524769
Directory /workspace/38.usbdev_out_iso/latest

Test location /workspace/coverage/default/38.usbdev_out_stall.3493651282
Short name T1690
Test name
Test status
Simulation time 177181086 ps
CPU time 0.75 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206876 kb
Host smart-f227f759-a2f8-4a5e-97f6-b32e8e348d56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34936
51282 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_stall.3493651282
Directory /workspace/38.usbdev_out_stall/latest

Test location /workspace/coverage/default/38.usbdev_out_trans_nak.2092988913
Short name T2342
Test name
Test status
Simulation time 155077465 ps
CPU time 0.76 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206708 kb
Host smart-7245721b-7f5c-4b72-ab57-cbf3d435d389
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20929
88913 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_out_trans_nak.2092988913
Directory /workspace/38.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/38.usbdev_pending_in_trans.3598695145
Short name T1571
Test name
Test status
Simulation time 152902845 ps
CPU time 0.77 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206724 kb
Host smart-ed5de153-2c20-4c03-9b67-38e849d1ce2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35986
95145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pending_in_trans.3598695145
Directory /workspace/38.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_pinflip.848897688
Short name T1357
Test name
Test status
Simulation time 219718552 ps
CPU time 0.89 seconds
Started Jul 22 06:02:06 PM PDT 24
Finished Jul 22 06:02:08 PM PDT 24
Peak memory 206676 kb
Host smart-978af7e2-2295-4606-ab18-007d3f151f14
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=848897688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_pinflip.848897688
Directory /workspace/38.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/38.usbdev_phy_config_usb_ref_disable.3245543704
Short name T1594
Test name
Test status
Simulation time 195813387 ps
CPU time 0.81 seconds
Started Jul 22 06:02:12 PM PDT 24
Finished Jul 22 06:02:14 PM PDT 24
Peak memory 206748 kb
Host smart-3e68b8d1-005f-4839-9dbc-d2e0be4089b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32455
43704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_config_usb_ref_disable.3245543704
Directory /workspace/38.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/38.usbdev_phy_pins_sense.2918102670
Short name T1072
Test name
Test status
Simulation time 88129341 ps
CPU time 0.66 seconds
Started Jul 22 06:02:07 PM PDT 24
Finished Jul 22 06:02:10 PM PDT 24
Peak memory 206740 kb
Host smart-771473c7-c655-41ad-af90-c4d9be88ae20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29181
02670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_phy_pins_sense.2918102670
Directory /workspace/38.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/38.usbdev_pkt_buffer.1624462785
Short name T2593
Test name
Test status
Simulation time 7945894436 ps
CPU time 17.21 seconds
Started Jul 22 06:02:12 PM PDT 24
Finished Jul 22 06:02:30 PM PDT 24
Peak memory 206936 kb
Host smart-361b2490-bec1-4419-a5fc-2377adcc061a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16244
62785 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_buffer.1624462785
Directory /workspace/38.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/38.usbdev_pkt_received.3675446972
Short name T2500
Test name
Test status
Simulation time 151637127 ps
CPU time 0.87 seconds
Started Jul 22 06:02:05 PM PDT 24
Finished Jul 22 06:02:07 PM PDT 24
Peak memory 206724 kb
Host smart-998db490-b5d9-4e49-a57e-55343c660f13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36754
46972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_received.3675446972
Directory /workspace/38.usbdev_pkt_received/latest

Test location /workspace/coverage/default/38.usbdev_pkt_sent.3879818722
Short name T1854
Test name
Test status
Simulation time 214795857 ps
CPU time 0.85 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206744 kb
Host smart-2b6a3419-d93e-46b9-b672-00c74558d7c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38798
18722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_pkt_sent.3879818722
Directory /workspace/38.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/38.usbdev_random_length_in_transaction.3822414886
Short name T843
Test name
Test status
Simulation time 234621710 ps
CPU time 0.85 seconds
Started Jul 22 06:02:05 PM PDT 24
Finished Jul 22 06:02:07 PM PDT 24
Peak memory 206732 kb
Host smart-3ea3221c-e9e1-4129-ac12-4f06b714efe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38224
14886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_in_transaction.3822414886
Directory /workspace/38.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/38.usbdev_random_length_out_transaction.941090405
Short name T2280
Test name
Test status
Simulation time 180114994 ps
CPU time 0.9 seconds
Started Jul 22 06:02:12 PM PDT 24
Finished Jul 22 06:02:14 PM PDT 24
Peak memory 206692 kb
Host smart-3c7386b9-48e0-4197-9e34-debb0cecc564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94109
0405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_random_length_out_transaction.941090405
Directory /workspace/38.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/38.usbdev_rx_crc_err.3796857935
Short name T1637
Test name
Test status
Simulation time 172065873 ps
CPU time 0.86 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206540 kb
Host smart-a659e8fd-5dec-4389-bf9a-9e0eb3be3f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37968
57935 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_rx_crc_err.3796857935
Directory /workspace/38.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/38.usbdev_setup_stage.3490975082
Short name T383
Test name
Test status
Simulation time 152890218 ps
CPU time 0.82 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206120 kb
Host smart-689f85c2-27da-4ff9-a2f4-ecb1562a097b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34909
75082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_stage.3490975082
Directory /workspace/38.usbdev_setup_stage/latest

Test location /workspace/coverage/default/38.usbdev_setup_trans_ignored.3187381055
Short name T1351
Test name
Test status
Simulation time 164391537 ps
CPU time 0.8 seconds
Started Jul 22 06:02:08 PM PDT 24
Finished Jul 22 06:02:11 PM PDT 24
Peak memory 206748 kb
Host smart-d5531812-5e1f-4a26-8d2d-93e9defeeed3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31873
81055 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_setup_trans_ignored.3187381055
Directory /workspace/38.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/38.usbdev_smoke.2142727232
Short name T798
Test name
Test status
Simulation time 265682784 ps
CPU time 1.01 seconds
Started Jul 22 06:02:09 PM PDT 24
Finished Jul 22 06:02:12 PM PDT 24
Peak memory 206044 kb
Host smart-4d535182-0bc4-4e35-b932-1ee005d70d93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21427
27232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_smoke.2142727232
Directory /workspace/38.usbdev_smoke/latest

Test location /workspace/coverage/default/38.usbdev_spurious_pids_ignored.2128096565
Short name T1157
Test name
Test status
Simulation time 5505200365 ps
CPU time 148.07 seconds
Started Jul 22 06:02:18 PM PDT 24
Finished Jul 22 06:04:47 PM PDT 24
Peak memory 206828 kb
Host smart-2696d009-29df-400f-8a92-5830ec4bc5e4
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2128096565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_spurious_pids_ignored.2128096565
Directory /workspace/38.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/38.usbdev_stall_priority_over_nak.2057700968
Short name T516
Test name
Test status
Simulation time 199162325 ps
CPU time 0.83 seconds
Started Jul 22 06:02:12 PM PDT 24
Finished Jul 22 06:02:13 PM PDT 24
Peak memory 206748 kb
Host smart-2c0052e5-c954-450b-85a9-f513e3825fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20577
00968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_priority_over_nak.2057700968
Directory /workspace/38.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/38.usbdev_stall_trans.173507433
Short name T2361
Test name
Test status
Simulation time 223626899 ps
CPU time 0.89 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206724 kb
Host smart-b164af24-6dce-486b-b316-34b1f2a29494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17350
7433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stall_trans.173507433
Directory /workspace/38.usbdev_stall_trans/latest

Test location /workspace/coverage/default/38.usbdev_stream_len_max.2310801204
Short name T1707
Test name
Test status
Simulation time 470944102 ps
CPU time 1.37 seconds
Started Jul 22 06:02:21 PM PDT 24
Finished Jul 22 06:02:23 PM PDT 24
Peak memory 206684 kb
Host smart-e673b711-10f5-427b-94a5-bc9e707f9ea3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23108
01204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_stream_len_max.2310801204
Directory /workspace/38.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/38.usbdev_streaming_out.125029650
Short name T1522
Test name
Test status
Simulation time 7202776074 ps
CPU time 199.56 seconds
Started Jul 22 06:02:13 PM PDT 24
Finished Jul 22 06:05:33 PM PDT 24
Peak memory 206892 kb
Host smart-a5b59666-7435-4dd8-ab04-c1ca4d5e89ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12502
9650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.usbdev_streaming_out.125029650
Directory /workspace/38.usbdev_streaming_out/latest

Test location /workspace/coverage/default/39.usbdev_alert_test.1211220249
Short name T1136
Test name
Test status
Simulation time 75242258 ps
CPU time 0.68 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206676 kb
Host smart-64a5d60a-19c2-4da0-8975-16aad06d0210
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1211220249 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_alert_test.1211220249
Directory /workspace/39.usbdev_alert_test/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_disconnect.1706577500
Short name T1586
Test name
Test status
Simulation time 3878298609 ps
CPU time 4.7 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206688 kb
Host smart-60246ba4-e9fd-4b27-9b6c-9eb4404c89bd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1706577500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_disconnect.1706577500
Directory /workspace/39.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_reset.2078311857
Short name T2264
Test name
Test status
Simulation time 13286653907 ps
CPU time 13.08 seconds
Started Jul 22 06:02:19 PM PDT 24
Finished Jul 22 06:02:33 PM PDT 24
Peak memory 206888 kb
Host smart-e031dc50-8c0a-4d6c-aa56-8fd308ad9f5f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2078311857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_reset.2078311857
Directory /workspace/39.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/39.usbdev_aon_wake_resume.1373906501
Short name T14
Test name
Test status
Simulation time 23388055164 ps
CPU time 21.29 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206900 kb
Host smart-a53c223f-262c-4273-9912-36a583a57c0b
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1373906501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_aon_wake_resume.1373906501
Directory /workspace/39.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/39.usbdev_av_buffer.2956296120
Short name T1055
Test name
Test status
Simulation time 179345944 ps
CPU time 0.83 seconds
Started Jul 22 06:02:15 PM PDT 24
Finished Jul 22 06:02:17 PM PDT 24
Peak memory 206752 kb
Host smart-e66eb6d6-c2da-4722-bd05-cdc35e68fd09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29562
96120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_av_buffer.2956296120
Directory /workspace/39.usbdev_av_buffer/latest

Test location /workspace/coverage/default/39.usbdev_bitstuff_err.2542091570
Short name T1913
Test name
Test status
Simulation time 152140486 ps
CPU time 0.76 seconds
Started Jul 22 06:02:19 PM PDT 24
Finished Jul 22 06:02:20 PM PDT 24
Peak memory 206672 kb
Host smart-36458e71-57a5-4523-b8f5-411fb903c7fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25420
91570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_bitstuff_err.2542091570
Directory /workspace/39.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_clear.677115872
Short name T435
Test name
Test status
Simulation time 174596896 ps
CPU time 0.81 seconds
Started Jul 22 06:02:14 PM PDT 24
Finished Jul 22 06:02:15 PM PDT 24
Peak memory 206660 kb
Host smart-5a0a6844-2064-4500-b65a-55d97fe77c77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67711
5872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_clear.677115872
Directory /workspace/39.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/39.usbdev_data_toggle_restore.4235282892
Short name T348
Test name
Test status
Simulation time 1486370916 ps
CPU time 3.16 seconds
Started Jul 22 06:02:12 PM PDT 24
Finished Jul 22 06:02:16 PM PDT 24
Peak memory 206824 kb
Host smart-dff85f0b-a9ea-4c1f-b884-684db0c8cb74
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42352
82892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_data_toggle_restore.4235282892
Directory /workspace/39.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/39.usbdev_device_address.2321476230
Short name T2094
Test name
Test status
Simulation time 15884722722 ps
CPU time 32.87 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:50 PM PDT 24
Peak memory 206888 kb
Host smart-ea75fb76-602f-4ce2-aeeb-141f83ea69f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23214
76230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_device_address.2321476230
Directory /workspace/39.usbdev_device_address/latest

Test location /workspace/coverage/default/39.usbdev_disable_endpoint.4090657608
Short name T2003
Test name
Test status
Simulation time 450216002 ps
CPU time 1.34 seconds
Started Jul 22 06:02:15 PM PDT 24
Finished Jul 22 06:02:17 PM PDT 24
Peak memory 206752 kb
Host smart-202acb78-e889-407d-a171-ad97b5211ab9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40906
57608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disable_endpoint.4090657608
Directory /workspace/39.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/39.usbdev_disconnected.1725153563
Short name T688
Test name
Test status
Simulation time 136951927 ps
CPU time 0.77 seconds
Started Jul 22 06:02:19 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206700 kb
Host smart-dc5703aa-0cec-4a37-8120-cc7e37b01119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17251
53563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_disconnected.1725153563
Directory /workspace/39.usbdev_disconnected/latest

Test location /workspace/coverage/default/39.usbdev_enable.2811821177
Short name T2310
Test name
Test status
Simulation time 37577698 ps
CPU time 0.65 seconds
Started Jul 22 06:02:19 PM PDT 24
Finished Jul 22 06:02:20 PM PDT 24
Peak memory 206700 kb
Host smart-f163dbc7-ae0a-467f-a29d-c320fb479591
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28118
21177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_enable.2811821177
Directory /workspace/39.usbdev_enable/latest

Test location /workspace/coverage/default/39.usbdev_endpoint_access.1090583643
Short name T2266
Test name
Test status
Simulation time 942450855 ps
CPU time 2.41 seconds
Started Jul 22 06:02:13 PM PDT 24
Finished Jul 22 06:02:16 PM PDT 24
Peak memory 206780 kb
Host smart-120ccd46-6a8d-4748-ab19-74d3e1e1b568
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10905
83643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_endpoint_access.1090583643
Directory /workspace/39.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/39.usbdev_fifo_rst.921782143
Short name T1495
Test name
Test status
Simulation time 332660878 ps
CPU time 2.22 seconds
Started Jul 22 06:02:13 PM PDT 24
Finished Jul 22 06:02:16 PM PDT 24
Peak memory 206888 kb
Host smart-10d2e3d2-6d79-4d30-b4b5-98a15fff66cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92178
2143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_fifo_rst.921782143
Directory /workspace/39.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/39.usbdev_in_iso.4290896859
Short name T1324
Test name
Test status
Simulation time 222323247 ps
CPU time 0.93 seconds
Started Jul 22 06:02:19 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206608 kb
Host smart-9db69e9b-24d0-4e52-8c89-7394288f802f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42908
96859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_iso.4290896859
Directory /workspace/39.usbdev_in_iso/latest

Test location /workspace/coverage/default/39.usbdev_in_stall.2800845109
Short name T555
Test name
Test status
Simulation time 202810966 ps
CPU time 0.8 seconds
Started Jul 22 06:02:13 PM PDT 24
Finished Jul 22 06:02:15 PM PDT 24
Peak memory 206668 kb
Host smart-72b068e0-e1ce-49e8-8024-5f0a2c7740be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28008
45109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_stall.2800845109
Directory /workspace/39.usbdev_in_stall/latest

Test location /workspace/coverage/default/39.usbdev_in_trans.2266783496
Short name T390
Test name
Test status
Simulation time 230153956 ps
CPU time 0.92 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206732 kb
Host smart-9f3f2c25-58ff-4851-81b2-47fd79bc3bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22667
83496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_in_trans.2266783496
Directory /workspace/39.usbdev_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_invalid_sync.3336594553
Short name T765
Test name
Test status
Simulation time 8750868800 ps
CPU time 229.72 seconds
Started Jul 22 06:04:19 PM PDT 24
Finished Jul 22 06:08:09 PM PDT 24
Peak memory 206880 kb
Host smart-760a9a13-1494-4b8f-aeab-ba5ea1e3341c
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3336594553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_invalid_sync.3336594553
Directory /workspace/39.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/39.usbdev_iso_retraction.3511928694
Short name T1292
Test name
Test status
Simulation time 12593817373 ps
CPU time 38.59 seconds
Started Jul 22 06:02:18 PM PDT 24
Finished Jul 22 06:02:57 PM PDT 24
Peak memory 206884 kb
Host smart-f50b53d0-53f9-4917-9c5e-3e35ca6777f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35119
28694 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_iso_retraction.3511928694
Directory /workspace/39.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/39.usbdev_link_in_err.2269853569
Short name T36
Test name
Test status
Simulation time 208573866 ps
CPU time 0.91 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206664 kb
Host smart-891d80f6-40a6-451a-86eb-8b5a51039709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22698
53569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_in_err.2269853569
Directory /workspace/39.usbdev_link_in_err/latest

Test location /workspace/coverage/default/39.usbdev_link_resume.985306969
Short name T1453
Test name
Test status
Simulation time 23324277352 ps
CPU time 30.49 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206804 kb
Host smart-31beefc0-5657-4815-ada0-ae2fb8f270db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98530
6969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_resume.985306969
Directory /workspace/39.usbdev_link_resume/latest

Test location /workspace/coverage/default/39.usbdev_link_suspend.3646680062
Short name T1427
Test name
Test status
Simulation time 3262774580 ps
CPU time 3.68 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:20 PM PDT 24
Peak memory 206788 kb
Host smart-84b02b07-2cee-4e26-aec4-7220e43443cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36466
80062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_link_suspend.3646680062
Directory /workspace/39.usbdev_link_suspend/latest

Test location /workspace/coverage/default/39.usbdev_low_speed_traffic.712790987
Short name T1905
Test name
Test status
Simulation time 8246855272 ps
CPU time 74.13 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:03:35 PM PDT 24
Peak memory 206936 kb
Host smart-35ff8abd-fde4-4e52-8b88-96a3aa79d3bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71279
0987 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_low_speed_traffic.712790987
Directory /workspace/39.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/39.usbdev_max_inter_pkt_delay.3073173830
Short name T1119
Test name
Test status
Simulation time 4726332355 ps
CPU time 131.99 seconds
Started Jul 22 06:02:14 PM PDT 24
Finished Jul 22 06:04:27 PM PDT 24
Peak memory 206848 kb
Host smart-f100a564-c79d-4b23-8fb2-05a1df07cdaf
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3073173830 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_inter_pkt_delay.3073173830
Directory /workspace/39.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_max_length_in_transaction.52969599
Short name T703
Test name
Test status
Simulation time 247865866 ps
CPU time 0.92 seconds
Started Jul 22 06:02:13 PM PDT 24
Finished Jul 22 06:02:14 PM PDT 24
Peak memory 206756 kb
Host smart-45100944-3fa0-45dd-bdb3-e505e212c9bb
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=52969599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_in_transaction.52969599
Directory /workspace/39.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_length_out_transaction.2296201749
Short name T1023
Test name
Test status
Simulation time 189327991 ps
CPU time 0.82 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:23 PM PDT 24
Peak memory 206680 kb
Host smart-0d66c81b-23d9-4e8a-ab89-0b43688da8a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22962
01749 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_length_out_transaction.2296201749
Directory /workspace/39.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_max_usb_traffic.3319562123
Short name T2477
Test name
Test status
Simulation time 4140319745 ps
CPU time 115.98 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 206888 kb
Host smart-cda1618f-8581-4b0f-8313-bf06094d5693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33195
62123 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_max_usb_traffic.3319562123
Directory /workspace/39.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/39.usbdev_min_inter_pkt_delay.3184896737
Short name T1556
Test name
Test status
Simulation time 4829848493 ps
CPU time 131.22 seconds
Started Jul 22 06:04:21 PM PDT 24
Finished Jul 22 06:06:33 PM PDT 24
Peak memory 206900 kb
Host smart-9a656f5e-5250-4d92-a8a9-91270132856b
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3184896737 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_inter_pkt_delay.3184896737
Directory /workspace/39.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/39.usbdev_min_length_in_transaction.2238284631
Short name T1808
Test name
Test status
Simulation time 156520816 ps
CPU time 0.76 seconds
Started Jul 22 06:02:17 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206760 kb
Host smart-59e22384-b857-46dd-a81e-b0d15ae6f0bd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2238284631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_in_transaction.2238284631
Directory /workspace/39.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_min_length_out_transaction.2413481863
Short name T1505
Test name
Test status
Simulation time 158521682 ps
CPU time 0.8 seconds
Started Jul 22 06:02:18 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206708 kb
Host smart-7a41d61b-5b55-415c-a7aa-de91d6d532d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24134
81863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_min_length_out_transaction.2413481863
Directory /workspace/39.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_nak_trans.3074078319
Short name T2543
Test name
Test status
Simulation time 189648511 ps
CPU time 0.83 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206764 kb
Host smart-b87a3c48-dfaa-4b95-a8fe-42ce0e9b08df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30740
78319 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_nak_trans.3074078319
Directory /workspace/39.usbdev_nak_trans/latest

Test location /workspace/coverage/default/39.usbdev_out_iso.2377893210
Short name T1863
Test name
Test status
Simulation time 172522734 ps
CPU time 0.86 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206708 kb
Host smart-c0c368cb-afe1-4467-9c0b-8db9806036e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23778
93210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_iso.2377893210
Directory /workspace/39.usbdev_out_iso/latest

Test location /workspace/coverage/default/39.usbdev_out_stall.1586127147
Short name T1480
Test name
Test status
Simulation time 180311576 ps
CPU time 0.82 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206720 kb
Host smart-23dd6559-37f2-438f-84b0-11eb77fc08bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15861
27147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_stall.1586127147
Directory /workspace/39.usbdev_out_stall/latest

Test location /workspace/coverage/default/39.usbdev_out_trans_nak.3872421051
Short name T1112
Test name
Test status
Simulation time 181818253 ps
CPU time 0.81 seconds
Started Jul 22 06:02:19 PM PDT 24
Finished Jul 22 06:02:21 PM PDT 24
Peak memory 206644 kb
Host smart-8635fbcb-4c19-4d87-8a91-53750c786ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38724
21051 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_out_trans_nak.3872421051
Directory /workspace/39.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/39.usbdev_pending_in_trans.915312858
Short name T782
Test name
Test status
Simulation time 166570257 ps
CPU time 0.78 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:23 PM PDT 24
Peak memory 206684 kb
Host smart-1a644ba4-7014-4fb2-a86d-d8c1fd021eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91531
2858 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pending_in_trans.915312858
Directory /workspace/39.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_pinflip.1844031005
Short name T1725
Test name
Test status
Simulation time 202366600 ps
CPU time 0.95 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206732 kb
Host smart-505a7fe8-3259-48e8-9cce-d9d68a19329a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1844031005 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_pinflip.1844031005
Directory /workspace/39.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/39.usbdev_phy_config_usb_ref_disable.360794647
Short name T1374
Test name
Test status
Simulation time 141960013 ps
CPU time 0.79 seconds
Started Jul 22 06:02:19 PM PDT 24
Finished Jul 22 06:02:20 PM PDT 24
Peak memory 206684 kb
Host smart-af391af9-d9c5-4db0-93a7-37cfeda342db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36079
4647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_config_usb_ref_disable.360794647
Directory /workspace/39.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/39.usbdev_phy_pins_sense.1162471869
Short name T1838
Test name
Test status
Simulation time 40907191 ps
CPU time 0.7 seconds
Started Jul 22 06:04:38 PM PDT 24
Finished Jul 22 06:04:39 PM PDT 24
Peak memory 206732 kb
Host smart-f001d87e-063a-40d4-b4f8-61523b53f920
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11624
71869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_phy_pins_sense.1162471869
Directory /workspace/39.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/39.usbdev_pkt_buffer.3358131153
Short name T254
Test name
Test status
Simulation time 11664450158 ps
CPU time 28.31 seconds
Started Jul 22 06:02:18 PM PDT 24
Finished Jul 22 06:02:47 PM PDT 24
Peak memory 215140 kb
Host smart-a23b1844-7ff4-43b5-b8de-cec7c42eac3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33581
31153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_buffer.3358131153
Directory /workspace/39.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/39.usbdev_pkt_received.335544578
Short name T2296
Test name
Test status
Simulation time 164686389 ps
CPU time 0.8 seconds
Started Jul 22 06:02:14 PM PDT 24
Finished Jul 22 06:02:15 PM PDT 24
Peak memory 206740 kb
Host smart-1502e4df-5cfc-4bec-a420-83d1b23626a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33554
4578 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_received.335544578
Directory /workspace/39.usbdev_pkt_received/latest

Test location /workspace/coverage/default/39.usbdev_pkt_sent.2055648911
Short name T2312
Test name
Test status
Simulation time 189659014 ps
CPU time 0.82 seconds
Started Jul 22 06:02:17 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206696 kb
Host smart-9ca7a8d8-90a0-4035-883d-0c8eb164fc3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20556
48911 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_pkt_sent.2055648911
Directory /workspace/39.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/39.usbdev_random_length_in_transaction.3287131222
Short name T2285
Test name
Test status
Simulation time 266733355 ps
CPU time 0.9 seconds
Started Jul 22 06:02:15 PM PDT 24
Finished Jul 22 06:02:17 PM PDT 24
Peak memory 206784 kb
Host smart-a99c49a9-97c4-4d5e-b5e7-e5dfb18a63a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32871
31222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_in_transaction.3287131222
Directory /workspace/39.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/39.usbdev_random_length_out_transaction.4060145786
Short name T1465
Test name
Test status
Simulation time 170269672 ps
CPU time 0.81 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:23 PM PDT 24
Peak memory 206732 kb
Host smart-f5134ae0-779a-4898-8d88-c0f77519a936
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40601
45786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_random_length_out_transaction.4060145786
Directory /workspace/39.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/39.usbdev_rx_crc_err.155394382
Short name T2028
Test name
Test status
Simulation time 155600109 ps
CPU time 0.8 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206704 kb
Host smart-33d8ce44-4045-494d-8954-8a6c2d64a0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15539
4382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_rx_crc_err.155394382
Directory /workspace/39.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/39.usbdev_setup_stage.1313482190
Short name T2687
Test name
Test status
Simulation time 150331688 ps
CPU time 0.79 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:23 PM PDT 24
Peak memory 206532 kb
Host smart-4a0b1a01-ded1-484f-b55c-9f3a3946d2dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13134
82190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_stage.1313482190
Directory /workspace/39.usbdev_setup_stage/latest

Test location /workspace/coverage/default/39.usbdev_setup_trans_ignored.701752474
Short name T1318
Test name
Test status
Simulation time 153052215 ps
CPU time 0.82 seconds
Started Jul 22 06:02:15 PM PDT 24
Finished Jul 22 06:02:17 PM PDT 24
Peak memory 206776 kb
Host smart-359bbbb4-e5ef-403d-9905-ad1b70442bde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70175
2474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_setup_trans_ignored.701752474
Directory /workspace/39.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/39.usbdev_smoke.3940790617
Short name T2121
Test name
Test status
Simulation time 261628347 ps
CPU time 0.94 seconds
Started Jul 22 06:02:17 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206752 kb
Host smart-2c43e23c-29fe-4ea9-949a-aa80d72d64d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39407
90617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_smoke.3940790617
Directory /workspace/39.usbdev_smoke/latest

Test location /workspace/coverage/default/39.usbdev_spurious_pids_ignored.3118349879
Short name T2093
Test name
Test status
Simulation time 6628070485 ps
CPU time 64.15 seconds
Started Jul 22 06:02:13 PM PDT 24
Finished Jul 22 06:03:18 PM PDT 24
Peak memory 207004 kb
Host smart-a8c08142-d168-43bd-a0f5-ff4467286623
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3118349879 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_spurious_pids_ignored.3118349879
Directory /workspace/39.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/39.usbdev_stall_priority_over_nak.1265904626
Short name T1441
Test name
Test status
Simulation time 191459269 ps
CPU time 0.82 seconds
Started Jul 22 06:02:16 PM PDT 24
Finished Jul 22 06:02:18 PM PDT 24
Peak memory 206700 kb
Host smart-3a2e2bb3-841a-4833-aad2-d556dd678d57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12659
04626 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_priority_over_nak.1265904626
Directory /workspace/39.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/39.usbdev_stall_trans.1111603518
Short name T2193
Test name
Test status
Simulation time 184246995 ps
CPU time 0.83 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:24 PM PDT 24
Peak memory 206712 kb
Host smart-db334d6f-621a-4a30-b78a-2e53a3e6a889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11116
03518 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stall_trans.1111603518
Directory /workspace/39.usbdev_stall_trans/latest

Test location /workspace/coverage/default/39.usbdev_stream_len_max.3032429411
Short name T504
Test name
Test status
Simulation time 449069729 ps
CPU time 1.35 seconds
Started Jul 22 06:02:17 PM PDT 24
Finished Jul 22 06:02:19 PM PDT 24
Peak memory 206700 kb
Host smart-34164fc5-8508-47b9-a0cd-0984e99495b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30324
29411 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_stream_len_max.3032429411
Directory /workspace/39.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/39.usbdev_streaming_out.453993808
Short name T2165
Test name
Test status
Simulation time 3704354848 ps
CPU time 103.88 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:04:06 PM PDT 24
Peak memory 206760 kb
Host smart-0548a3aa-0772-4a60-959c-197d4efb8d88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45399
3808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.usbdev_streaming_out.453993808
Directory /workspace/39.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_alert_test.431570662
Short name T1382
Test name
Test status
Simulation time 38598734 ps
CPU time 0.67 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:05 PM PDT 24
Peak memory 206744 kb
Host smart-e9291e4f-cb43-4e55-932f-4feddcf465fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=431570662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_alert_test.431570662
Directory /workspace/4.usbdev_alert_test/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_disconnect.2101633497
Short name T1387
Test name
Test status
Simulation time 3471783269 ps
CPU time 5.12 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 05:57:02 PM PDT 24
Peak memory 206884 kb
Host smart-cabf8587-ae92-4375-9bc2-f24c209636bc
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2101633497 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_disconnect.2101633497
Directory /workspace/4.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_reset.1648957081
Short name T956
Test name
Test status
Simulation time 13367554069 ps
CPU time 16.84 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:57:10 PM PDT 24
Peak memory 206744 kb
Host smart-566dd4b0-aa62-49d0-b3eb-2720d8d56a27
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1648957081 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_reset.1648957081
Directory /workspace/4.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/4.usbdev_aon_wake_resume.121828569
Short name T1442
Test name
Test status
Simulation time 23282278335 ps
CPU time 22.7 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:57:17 PM PDT 24
Peak memory 206964 kb
Host smart-398f7444-aa31-4204-9249-992c548f7574
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=121828569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_aon_wake_resume.121828569
Directory /workspace/4.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/4.usbdev_av_buffer.3875921180
Short name T402
Test name
Test status
Simulation time 152531495 ps
CPU time 0.79 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206724 kb
Host smart-c13c7d0b-99ea-44bb-bf6d-03e43dc101fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38759
21180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_buffer.3875921180
Directory /workspace/4.usbdev_av_buffer/latest

Test location /workspace/coverage/default/4.usbdev_av_empty.4261277696
Short name T65
Test name
Test status
Simulation time 164540858 ps
CPU time 0.79 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:54 PM PDT 24
Peak memory 206704 kb
Host smart-9b4d588b-20ab-4b47-908d-754aa358daa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42612
77696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_empty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_empty.4261277696
Directory /workspace/4.usbdev_av_empty/latest

Test location /workspace/coverage/default/4.usbdev_av_overflow.3038643520
Short name T88
Test name
Test status
Simulation time 150492340 ps
CPU time 0.79 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:54 PM PDT 24
Peak memory 206696 kb
Host smart-c7392ef8-7290-4357-8e95-6c1c9e80109a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30386
43520 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_overflow_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_av_overflow.3038643520
Directory /workspace/4.usbdev_av_overflow/latest

Test location /workspace/coverage/default/4.usbdev_bitstuff_err.831065688
Short name T2427
Test name
Test status
Simulation time 149480119 ps
CPU time 0.85 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:56:55 PM PDT 24
Peak memory 206748 kb
Host smart-59dca064-73ed-49d6-b897-6cb2793e2357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83106
5688 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_bitstuff_err.831065688
Directory /workspace/4.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_clear.1823833480
Short name T1447
Test name
Test status
Simulation time 622876339 ps
CPU time 1.65 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:55 PM PDT 24
Peak memory 206844 kb
Host smart-181d5aa8-89d6-41e5-ae3a-68ced3e1daf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18238
33480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_clear.1823833480
Directory /workspace/4.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/4.usbdev_data_toggle_restore.2015512250
Short name T1888
Test name
Test status
Simulation time 1271190123 ps
CPU time 2.63 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 05:56:55 PM PDT 24
Peak memory 206788 kb
Host smart-57c359c3-e796-477c-b423-f8d9b9b03db1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20155
12250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_data_toggle_restore.2015512250
Directory /workspace/4.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/4.usbdev_device_address.1696988308
Short name T1904
Test name
Test status
Simulation time 21437120263 ps
CPU time 41.08 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:57:38 PM PDT 24
Peak memory 206956 kb
Host smart-658df612-ccef-491a-93f2-a3ce89abae2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16969
88308 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_device_address.1696988308
Directory /workspace/4.usbdev_device_address/latest

Test location /workspace/coverage/default/4.usbdev_disable_endpoint.1760661354
Short name T1655
Test name
Test status
Simulation time 468854028 ps
CPU time 1.41 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 05:56:54 PM PDT 24
Peak memory 206748 kb
Host smart-f7f2e8e2-9347-4188-9d21-74ff6f7af87b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17606
61354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disable_endpoint.1760661354
Directory /workspace/4.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/4.usbdev_disconnected.2762004042
Short name T51
Test name
Test status
Simulation time 180798022 ps
CPU time 0.8 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:56 PM PDT 24
Peak memory 206704 kb
Host smart-e4085fa3-720e-4a34-b88a-533d04536a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27620
04042 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_disconnected.2762004042
Directory /workspace/4.usbdev_disconnected/latest

Test location /workspace/coverage/default/4.usbdev_enable.3013487944
Short name T2384
Test name
Test status
Simulation time 78675914 ps
CPU time 0.69 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:53 PM PDT 24
Peak memory 206696 kb
Host smart-9ef52ac4-8061-4509-a2f4-b8d2d09888c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30134
87944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_enable.3013487944
Directory /workspace/4.usbdev_enable/latest

Test location /workspace/coverage/default/4.usbdev_endpoint_access.4259364067
Short name T1178
Test name
Test status
Simulation time 988405377 ps
CPU time 2.35 seconds
Started Jul 22 05:57:12 PM PDT 24
Finished Jul 22 05:57:15 PM PDT 24
Peak memory 206824 kb
Host smart-3d3b4e5e-edcf-4be9-bc8e-1ed128c3482e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42593
64067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_endpoint_access.4259364067
Directory /workspace/4.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/4.usbdev_fifo_rst.1329919062
Short name T1898
Test name
Test status
Simulation time 279818362 ps
CPU time 2.24 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206868 kb
Host smart-2fa96cc5-660f-4e50-b98f-159f8b42e3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13299
19062 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_fifo_rst.1329919062
Directory /workspace/4.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk.2130896377
Short name T2708
Test name
Test status
Simulation time 103181990525 ps
CPU time 150.81 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:59:33 PM PDT 24
Peak memory 206936 kb
Host smart-ce4cc137-d891-41df-ba00-6b139896e2f0
User root
Command /workspace/default/simv +host_freq_delta=-18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2130896377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk.2130896377
Directory /workspace/4.usbdev_freq_hiclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_hiclk_max.3580276875
Short name T2106
Test name
Test status
Simulation time 96396871208 ps
CPU time 119.89 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 05:58:56 PM PDT 24
Peak memory 206948 kb
Host smart-45a1cbeb-51b9-4129-a114-0e359c389b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +host_drifting=1 +host_freq_delta=-120000 +osc_tracking=1 +reset_recovery=1 +usb_freq_delta=+12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580276875 -assert n
opostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_hiclk_max.3580276875
Directory /workspace/4.usbdev_freq_hiclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk.3138442195
Short name T1371
Test name
Test status
Simulation time 116104018669 ps
CPU time 163.72 seconds
Started Jul 22 05:57:01 PM PDT 24
Finished Jul 22 05:59:46 PM PDT 24
Peak memory 206908 kb
Host smart-66be59fc-5c25-437b-ab2c-e9e5fb38bf7a
User root
Command /workspace/default/simv +host_freq_delta=+18500 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3138442195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk.3138442195
Directory /workspace/4.usbdev_freq_loclk/latest

Test location /workspace/coverage/default/4.usbdev_freq_loclk_max.320834839
Short name T894
Test name
Test status
Simulation time 107109484718 ps
CPU time 137.35 seconds
Started Jul 22 05:56:58 PM PDT 24
Finished Jul 22 05:59:16 PM PDT 24
Peak memory 206968 kb
Host smart-61cee6fd-349d-4f45-acff-f2bd940a73e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=0 +osc_tracking=1 +host_drifting=1 +host_freq_delta=+120000 +reset_recovery=1 +usb_freq_delta=-12
0000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320834839 -assert no
postproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
e/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_loclk_max.320834839
Directory /workspace/4.usbdev_freq_loclk_max/latest

Test location /workspace/coverage/default/4.usbdev_freq_phase.2994401017
Short name T2636
Test name
Test status
Simulation time 121232608966 ps
CPU time 172.81 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:59:47 PM PDT 24
Peak memory 206976 kb
Host smart-dc70d32e-4835-40c8-9f0a-cd10ea16cf6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29944
01017 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_freq_phase_delta_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_freq_phase.2994401017
Directory /workspace/4.usbdev_freq_phase/latest

Test location /workspace/coverage/default/4.usbdev_in_iso.4073120075
Short name T2283
Test name
Test status
Simulation time 173118902 ps
CPU time 0.82 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:56 PM PDT 24
Peak memory 206724 kb
Host smart-5e47fb7b-da67-4c3c-92de-a45c3e9215fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40731
20075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_iso.4073120075
Directory /workspace/4.usbdev_in_iso/latest

Test location /workspace/coverage/default/4.usbdev_in_stall.583215213
Short name T1871
Test name
Test status
Simulation time 206986259 ps
CPU time 0.83 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206736 kb
Host smart-a260bd4f-55bc-49d7-9d1c-33f6da95c32b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58321
5213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_stall.583215213
Directory /workspace/4.usbdev_in_stall/latest

Test location /workspace/coverage/default/4.usbdev_in_trans.3518121338
Short name T2105
Test name
Test status
Simulation time 212621527 ps
CPU time 0.83 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206724 kb
Host smart-5c217e6d-41c6-430c-a89c-2216178fd7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35181
21338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_in_trans.3518121338
Directory /workspace/4.usbdev_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_link_in_err.2530347934
Short name T531
Test name
Test status
Simulation time 190462859 ps
CPU time 0.85 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:57 PM PDT 24
Peak memory 206732 kb
Host smart-eed5fda5-a516-4e8c-ac48-74908dc9a025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25303
47934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_in_err.2530347934
Directory /workspace/4.usbdev_link_in_err/latest

Test location /workspace/coverage/default/4.usbdev_link_resume.4044001903
Short name T2290
Test name
Test status
Simulation time 23328646916 ps
CPU time 29.34 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:57:23 PM PDT 24
Peak memory 206808 kb
Host smart-7c099a42-1e2f-4074-80b7-19657476e715
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40440
01903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_resume.4044001903
Directory /workspace/4.usbdev_link_resume/latest

Test location /workspace/coverage/default/4.usbdev_link_suspend.2268264245
Short name T1370
Test name
Test status
Simulation time 3300672789 ps
CPU time 4.85 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206816 kb
Host smart-535dc815-8a06-4496-925c-61908852f794
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22682
64245 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_link_suspend.2268264245
Directory /workspace/4.usbdev_link_suspend/latest

Test location /workspace/coverage/default/4.usbdev_low_speed_traffic.841150386
Short name T1908
Test name
Test status
Simulation time 5154979538 ps
CPU time 49.17 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206960 kb
Host smart-f6074b29-295f-4075-a523-406d894869f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84115
0386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_low_speed_traffic.841150386
Directory /workspace/4.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/4.usbdev_max_inter_pkt_delay.2721958909
Short name T2236
Test name
Test status
Simulation time 7508208192 ps
CPU time 204.32 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 06:00:20 PM PDT 24
Peak memory 206772 kb
Host smart-88374250-6394-45b9-ae8d-c3833a726626
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2721958909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_inter_pkt_delay.2721958909
Directory /workspace/4.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_max_length_in_transaction.3525642296
Short name T2341
Test name
Test status
Simulation time 248054623 ps
CPU time 0.95 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 05:56:53 PM PDT 24
Peak memory 206744 kb
Host smart-95a0a7cc-9e0d-49b3-840f-5f5e7db18c80
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3525642296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_in_transaction.3525642296
Directory /workspace/4.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_length_out_transaction.421294054
Short name T1945
Test name
Test status
Simulation time 188732020 ps
CPU time 0.9 seconds
Started Jul 22 05:56:58 PM PDT 24
Finished Jul 22 05:56:59 PM PDT 24
Peak memory 206724 kb
Host smart-21f6aaec-0e86-4b9d-b0f1-629c1dee3291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42129
4054 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_length_out_transaction.421294054
Directory /workspace/4.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_max_usb_traffic.3813948040
Short name T2184
Test name
Test status
Simulation time 5030582306 ps
CPU time 134.64 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:59:12 PM PDT 24
Peak memory 206872 kb
Host smart-0a30a9fe-b69d-4193-a112-586a6aeb9bc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38139
48040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_max_usb_traffic.3813948040
Directory /workspace/4.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/4.usbdev_min_inter_pkt_delay.4043911968
Short name T2059
Test name
Test status
Simulation time 4800705212 ps
CPU time 35.14 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:57:29 PM PDT 24
Peak memory 206944 kb
Host smart-75b56d7d-c11b-4b38-a885-92fcad9150d6
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4043911968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_inter_pkt_delay.4043911968
Directory /workspace/4.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/4.usbdev_min_length_in_transaction.1845945784
Short name T1672
Test name
Test status
Simulation time 190179130 ps
CPU time 0.8 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:56 PM PDT 24
Peak memory 206664 kb
Host smart-8c2eb806-e284-4da3-bbc2-e10725ea1e83
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1845945784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_in_transaction.1845945784
Directory /workspace/4.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_min_length_out_transaction.3535337886
Short name T1973
Test name
Test status
Simulation time 149238165 ps
CPU time 0.8 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:05 PM PDT 24
Peak memory 206748 kb
Host smart-b6ee0d23-df3f-4f7d-8ec5-09dc8b87c0c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35353
37886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_min_length_out_transaction.3535337886
Directory /workspace/4.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_nak_trans.420721059
Short name T113
Test name
Test status
Simulation time 204430089 ps
CPU time 0.87 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206672 kb
Host smart-470663de-ba6d-4f14-a866-cab84e916305
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
1059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_nak_trans.420721059
Directory /workspace/4.usbdev_nak_trans/latest

Test location /workspace/coverage/default/4.usbdev_out_iso.2550943953
Short name T2542
Test name
Test status
Simulation time 174893849 ps
CPU time 0.83 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 05:56:57 PM PDT 24
Peak memory 206676 kb
Host smart-88e7df76-4154-485a-a8c4-2177e05b9ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25509
43953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_iso.2550943953
Directory /workspace/4.usbdev_out_iso/latest

Test location /workspace/coverage/default/4.usbdev_out_stall.2077301563
Short name T2212
Test name
Test status
Simulation time 164085155 ps
CPU time 0.84 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:56:55 PM PDT 24
Peak memory 206756 kb
Host smart-77b37121-41c9-43de-a428-608c2b916cf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20773
01563 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_stall.2077301563
Directory /workspace/4.usbdev_out_stall/latest

Test location /workspace/coverage/default/4.usbdev_out_trans_nak.1464785197
Short name T985
Test name
Test status
Simulation time 210453178 ps
CPU time 0.85 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:04 PM PDT 24
Peak memory 206748 kb
Host smart-50bbc799-56e2-43c4-9ac7-c49151fe747c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14647
85197 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_out_trans_nak.1464785197
Directory /workspace/4.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/4.usbdev_pending_in_trans.2543181924
Short name T1507
Test name
Test status
Simulation time 161389690 ps
CPU time 0.78 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:54 PM PDT 24
Peak memory 206756 kb
Host smart-f376314e-73e9-4cc1-a6df-2ffa187d48e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25431
81924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pending_in_trans.2543181924
Directory /workspace/4.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_pinflip.1584128192
Short name T1695
Test name
Test status
Simulation time 221157362 ps
CPU time 0.9 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206676 kb
Host smart-944067b1-6317-4388-884e-61babd8fec6d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1584128192 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_pinflip.1584128192
Directory /workspace/4.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_rand_bus_type.3194382172
Short name T198
Test name
Test status
Simulation time 196785647 ps
CPU time 0.9 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:56 PM PDT 24
Peak memory 206728 kb
Host smart-f0008a37-3cec-4937-87d9-f029868dc4a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31943
82172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_rand_bus_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_rand_bus_type.3194382172
Directory /workspace/4.usbdev_phy_config_rand_bus_type/latest

Test location /workspace/coverage/default/4.usbdev_phy_config_usb_ref_disable.2959712173
Short name T876
Test name
Test status
Simulation time 155015280 ps
CPU time 0.8 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:58:25 PM PDT 24
Peak memory 206728 kb
Host smart-804792fb-5baa-467d-8ab8-cd22c1433b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29597
12173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_config_usb_ref_disable.2959712173
Directory /workspace/4.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/4.usbdev_phy_pins_sense.2560857538
Short name T715
Test name
Test status
Simulation time 38261358 ps
CPU time 0.65 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 05:56:52 PM PDT 24
Peak memory 206684 kb
Host smart-96892d72-1247-4eac-833b-aaea3df6d94c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25608
57538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_phy_pins_sense.2560857538
Directory /workspace/4.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/4.usbdev_pkt_buffer.3375211294
Short name T2668
Test name
Test status
Simulation time 22395081741 ps
CPU time 59.01 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206904 kb
Host smart-f5202677-dc53-4a21-a6d9-6cb551db76cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33752
11294 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_buffer.3375211294
Directory /workspace/4.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/4.usbdev_pkt_received.1768550631
Short name T271
Test name
Test status
Simulation time 149949743 ps
CPU time 0.82 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:56 PM PDT 24
Peak memory 206704 kb
Host smart-e08fd768-938d-49b4-b357-900f49664b78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17685
50631 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_received.1768550631
Directory /workspace/4.usbdev_pkt_received/latest

Test location /workspace/coverage/default/4.usbdev_pkt_sent.2936369514
Short name T637
Test name
Test status
Simulation time 185035300 ps
CPU time 0.9 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 05:56:57 PM PDT 24
Peak memory 206736 kb
Host smart-12a0c40e-67ed-4356-b192-38c08c38db93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29363
69514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_pkt_sent.2936369514
Directory /workspace/4.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_disconnects.1223751952
Short name T1060
Test name
Test status
Simulation time 7511753556 ps
CPU time 34.32 seconds
Started Jul 22 05:58:23 PM PDT 24
Finished Jul 22 05:58:59 PM PDT 24
Peak memory 206976 kb
Host smart-94d81dd9-3bcc-40fe-8314-24fccef151de
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1223751952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_disconnects.1223751952
Directory /workspace/4.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/4.usbdev_rand_bus_resets.2252897478
Short name T186
Test name
Test status
Simulation time 16763933561 ps
CPU time 120.41 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:58:56 PM PDT 24
Peak memory 206980 kb
Host smart-07d52642-daa9-4ce5-97d2-62fd926340f4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2252897478 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_bus_resets.2252897478
Directory /workspace/4.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/4.usbdev_rand_suspends.4284668337
Short name T526
Test name
Test status
Simulation time 12450956916 ps
CPU time 87.22 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:58:33 PM PDT 24
Peak memory 206860 kb
Host smart-a15bf0ff-9139-4ece-989e-0f3d2ccd9780
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4284668337 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rand_suspends.4284668337
Directory /workspace/4.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/4.usbdev_random_length_in_transaction.721034550
Short name T2110
Test name
Test status
Simulation time 249487375 ps
CPU time 0.92 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206736 kb
Host smart-c66cfe61-af99-421c-be46-c90dc24e440a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72103
4550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_in_transaction.721034550
Directory /workspace/4.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/4.usbdev_random_length_out_transaction.444189193
Short name T409
Test name
Test status
Simulation time 185477162 ps
CPU time 0.88 seconds
Started Jul 22 05:56:58 PM PDT 24
Finished Jul 22 05:56:59 PM PDT 24
Peak memory 206728 kb
Host smart-373cc5a0-466d-459d-8040-34626100640c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44418
9193 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_random_length_out_transaction.444189193
Directory /workspace/4.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/4.usbdev_rx_crc_err.2264353840
Short name T1493
Test name
Test status
Simulation time 191176615 ps
CPU time 0.88 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206740 kb
Host smart-1b8b479e-ea08-466f-b12e-bd255d9ae386
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22643
53840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_crc_err.2264353840
Directory /workspace/4.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/4.usbdev_rx_pid_err.2695353713
Short name T81
Test name
Test status
Simulation time 186108843 ps
CPU time 0.82 seconds
Started Jul 22 05:56:53 PM PDT 24
Finished Jul 22 05:56:55 PM PDT 24
Peak memory 206680 kb
Host smart-d178571f-2ee7-40d4-84fc-94a4a4a696f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26953
53713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_pid_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_rx_pid_err.2695353713
Directory /workspace/4.usbdev_rx_pid_err/latest

Test location /workspace/coverage/default/4.usbdev_sec_cm.3096595604
Short name T189
Test name
Test status
Simulation time 261123156 ps
CPU time 1.12 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 224428 kb
Host smart-a3b11273-527c-4322-a50c-020fa6d2393b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3096595604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_sec_cm.3096595604
Directory /workspace/4.usbdev_sec_cm/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority.1524932856
Short name T2333
Test name
Test status
Simulation time 404167280 ps
CPU time 1.32 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:07 PM PDT 24
Peak memory 206672 kb
Host smart-701eb75e-c278-4c0d-bdda-448aacd62901
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15249
32856 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority.1524932856
Directory /workspace/4.usbdev_setup_priority/latest

Test location /workspace/coverage/default/4.usbdev_setup_priority_over_stall_response.1223629277
Short name T2043
Test name
Test status
Simulation time 338427152 ps
CPU time 0.99 seconds
Started Jul 22 05:56:51 PM PDT 24
Finished Jul 22 05:56:53 PM PDT 24
Peak memory 206932 kb
Host smart-075ec085-655e-454c-a304-cec516cd2209
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12236
29277 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_priority_over_stall_response_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_priority_over_stall_response.1223629277
Directory /workspace/4.usbdev_setup_priority_over_stall_response/latest

Test location /workspace/coverage/default/4.usbdev_setup_stage.1293122495
Short name T2005
Test name
Test status
Simulation time 156890936 ps
CPU time 0.81 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:03 PM PDT 24
Peak memory 206744 kb
Host smart-b48876b0-e6a7-4fef-942a-dd193d2a83d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12931
22495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_stage.1293122495
Directory /workspace/4.usbdev_setup_stage/latest

Test location /workspace/coverage/default/4.usbdev_setup_trans_ignored.2360209986
Short name T826
Test name
Test status
Simulation time 152454779 ps
CPU time 0.75 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 05:56:57 PM PDT 24
Peak memory 206752 kb
Host smart-2c851100-cfd0-41db-b940-6b405d91cc2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23602
09986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_setup_trans_ignored.2360209986
Directory /workspace/4.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/4.usbdev_smoke.3956131916
Short name T1032
Test name
Test status
Simulation time 242187095 ps
CPU time 1.03 seconds
Started Jul 22 05:56:52 PM PDT 24
Finished Jul 22 05:56:54 PM PDT 24
Peak memory 206740 kb
Host smart-81cc62a4-a262-4851-84b7-6f65802525a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39561
31916 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_smoke.3956131916
Directory /workspace/4.usbdev_smoke/latest

Test location /workspace/coverage/default/4.usbdev_spurious_pids_ignored.3351080796
Short name T1078
Test name
Test status
Simulation time 5229268823 ps
CPU time 144.09 seconds
Started Jul 22 05:57:11 PM PDT 24
Finished Jul 22 05:59:36 PM PDT 24
Peak memory 206876 kb
Host smart-60f8f7bf-56e7-46d5-9419-d75affeb4d35
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3351080796 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_spurious_pids_ignored.3351080796
Directory /workspace/4.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/4.usbdev_stall_priority_over_nak.1047152667
Short name T1457
Test name
Test status
Simulation time 172644992 ps
CPU time 0.8 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:56 PM PDT 24
Peak memory 206704 kb
Host smart-be99a93f-4bbe-4fbc-b4ae-e0b8484e77ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10471
52667 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_priority_over_nak.1047152667
Directory /workspace/4.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/4.usbdev_stall_trans.188307971
Short name T1885
Test name
Test status
Simulation time 215120506 ps
CPU time 0.92 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206632 kb
Host smart-b60d900e-d6c0-4959-92b8-59339a2cd4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18830
7971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stall_trans.188307971
Directory /workspace/4.usbdev_stall_trans/latest

Test location /workspace/coverage/default/4.usbdev_stream_len_max.900134020
Short name T1659
Test name
Test status
Simulation time 1101502395 ps
CPU time 2.31 seconds
Started Jul 22 05:56:54 PM PDT 24
Finished Jul 22 05:56:58 PM PDT 24
Peak memory 206880 kb
Host smart-882865f6-2f48-41a7-9380-4c1e40b05c59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90013
4020 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stream_len_max.900134020
Directory /workspace/4.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/4.usbdev_streaming_out.3365983844
Short name T1134
Test name
Test status
Simulation time 4413617728 ps
CPU time 41.7 seconds
Started Jul 22 05:56:55 PM PDT 24
Finished Jul 22 05:57:38 PM PDT 24
Peak memory 206944 kb
Host smart-8236cd0d-33f6-418e-a91d-094d0a7e40ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
83844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_streaming_out.3365983844
Directory /workspace/4.usbdev_streaming_out/latest

Test location /workspace/coverage/default/4.usbdev_stress_usb_traffic.2723434419
Short name T2512
Test name
Test status
Simulation time 13375910008 ps
CPU time 65.83 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:58:10 PM PDT 24
Peak memory 206992 kb
Host smart-a89e29b7-7181-45d3-adf8-3123dd15b18e
User root
Command /workspace/default/simv +do_resume_signaling=1 +do_reset_signaling=1 +do_vbus_disconnects=1 +wt_bad_syncs=1 +wt_bad_pids=1 +wt_spurious_pids=1 +wt_bad
_crc5=1 +wt_bad_crc16=1 +wt_bitstuff_errs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2723434419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.usbdev_stress_usb_traffic.2723434419
Directory /workspace/4.usbdev_stress_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_alert_test.1367641370
Short name T361
Test name
Test status
Simulation time 49949409 ps
CPU time 0.69 seconds
Started Jul 22 06:02:27 PM PDT 24
Finished Jul 22 06:02:29 PM PDT 24
Peak memory 206732 kb
Host smart-dc25e4a1-8dd0-42b9-bfb8-dfd076717014
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1367641370 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_alert_test.1367641370
Directory /workspace/40.usbdev_alert_test/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_disconnect.3539269174
Short name T1576
Test name
Test status
Simulation time 3676589049 ps
CPU time 4.46 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:25 PM PDT 24
Peak memory 206820 kb
Host smart-7bd2df4b-b819-4e02-8f44-09b7de832efd
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3539269174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_disconnect.3539269174
Directory /workspace/40.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_reset.1806860635
Short name T1225
Test name
Test status
Simulation time 13417478031 ps
CPU time 13.58 seconds
Started Jul 22 06:02:23 PM PDT 24
Finished Jul 22 06:02:37 PM PDT 24
Peak memory 206800 kb
Host smart-d9427964-3719-46f4-968d-ac2196ce460f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1806860635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_reset.1806860635
Directory /workspace/40.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/40.usbdev_aon_wake_resume.2541383760
Short name T1674
Test name
Test status
Simulation time 23370149687 ps
CPU time 23.3 seconds
Started Jul 22 06:02:36 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206964 kb
Host smart-c17c2639-2ffb-4ada-98c3-3cb7840ee4c3
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2541383760 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_aon_wake_resume.2541383760
Directory /workspace/40.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/40.usbdev_av_buffer.2918927501
Short name T1397
Test name
Test status
Simulation time 167806236 ps
CPU time 0.88 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:24 PM PDT 24
Peak memory 206476 kb
Host smart-62fc1f83-5fed-40a9-b8b4-1091803b32e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29189
27501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_av_buffer.2918927501
Directory /workspace/40.usbdev_av_buffer/latest

Test location /workspace/coverage/default/40.usbdev_bitstuff_err.3675050456
Short name T1093
Test name
Test status
Simulation time 146217050 ps
CPU time 0.78 seconds
Started Jul 22 06:02:36 PM PDT 24
Finished Jul 22 06:02:37 PM PDT 24
Peak memory 206752 kb
Host smart-39cdae9a-e336-4cb8-8f55-58e0d9fe6c47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36750
50456 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_bitstuff_err.3675050456
Directory /workspace/40.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_clear.1108505886
Short name T2254
Test name
Test status
Simulation time 530142004 ps
CPU time 1.51 seconds
Started Jul 22 06:02:23 PM PDT 24
Finished Jul 22 06:02:25 PM PDT 24
Peak memory 206716 kb
Host smart-92978937-5563-4436-9bcf-768fee2dcba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11085
05886 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_clear.1108505886
Directory /workspace/40.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/40.usbdev_data_toggle_restore.3102836656
Short name T586
Test name
Test status
Simulation time 1330206072 ps
CPU time 2.83 seconds
Started Jul 22 06:02:22 PM PDT 24
Finished Jul 22 06:02:26 PM PDT 24
Peak memory 206588 kb
Host smart-85a9fb9a-0d49-46a4-a853-17a707222757
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31028
36656 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_data_toggle_restore.3102836656
Directory /workspace/40.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/40.usbdev_device_address.1902244953
Short name T886
Test name
Test status
Simulation time 19730157745 ps
CPU time 38.89 seconds
Started Jul 22 06:02:17 PM PDT 24
Finished Jul 22 06:02:57 PM PDT 24
Peak memory 206904 kb
Host smart-f63d1784-34d4-4b00-a5e3-246a3104cb52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19022
44953 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_device_address.1902244953
Directory /workspace/40.usbdev_device_address/latest

Test location /workspace/coverage/default/40.usbdev_disable_endpoint.4085294482
Short name T802
Test name
Test status
Simulation time 398874821 ps
CPU time 1.26 seconds
Started Jul 22 06:02:20 PM PDT 24
Finished Jul 22 06:02:22 PM PDT 24
Peak memory 206756 kb
Host smart-9b71338f-d12f-40bf-b431-6b9127e46e06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40852
94482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disable_endpoint.4085294482
Directory /workspace/40.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/40.usbdev_disconnected.299021100
Short name T1409
Test name
Test status
Simulation time 128968521 ps
CPU time 0.74 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:02:25 PM PDT 24
Peak memory 206736 kb
Host smart-4b66c5e5-6954-41d9-930d-51b1f34d7ce4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29902
1100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_disconnected.299021100
Directory /workspace/40.usbdev_disconnected/latest

Test location /workspace/coverage/default/40.usbdev_enable.1010093331
Short name T2526
Test name
Test status
Simulation time 30363764 ps
CPU time 0.65 seconds
Started Jul 22 06:02:25 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206780 kb
Host smart-46091bdf-13a3-4990-82bf-8e105aad2b03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10100
93331 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_enable.1010093331
Directory /workspace/40.usbdev_enable/latest

Test location /workspace/coverage/default/40.usbdev_endpoint_access.2774492399
Short name T2513
Test name
Test status
Simulation time 876784877 ps
CPU time 2.12 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:02:28 PM PDT 24
Peak memory 206844 kb
Host smart-8f3036d6-d17c-4836-8cf7-af99607822a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27744
92399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_endpoint_access.2774492399
Directory /workspace/40.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/40.usbdev_fifo_rst.3224600562
Short name T1939
Test name
Test status
Simulation time 381451107 ps
CPU time 2.29 seconds
Started Jul 22 06:02:27 PM PDT 24
Finished Jul 22 06:02:30 PM PDT 24
Peak memory 206888 kb
Host smart-800a62c2-3465-4848-b958-252ff97ba151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32246
00562 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_fifo_rst.3224600562
Directory /workspace/40.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/40.usbdev_in_iso.1162696046
Short name T2468
Test name
Test status
Simulation time 228482368 ps
CPU time 0.92 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206488 kb
Host smart-b74b41b6-c083-43fe-988d-2ae9647cc9c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11626
96046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_iso.1162696046
Directory /workspace/40.usbdev_in_iso/latest

Test location /workspace/coverage/default/40.usbdev_in_stall.973402122
Short name T2058
Test name
Test status
Simulation time 139128116 ps
CPU time 0.75 seconds
Started Jul 22 06:02:28 PM PDT 24
Finished Jul 22 06:02:29 PM PDT 24
Peak memory 206748 kb
Host smart-65c97b35-d95d-4cf3-b6c7-efc327cc5bd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97340
2122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_stall.973402122
Directory /workspace/40.usbdev_in_stall/latest

Test location /workspace/coverage/default/40.usbdev_in_trans.1560347019
Short name T1864
Test name
Test status
Simulation time 192592954 ps
CPU time 0.94 seconds
Started Jul 22 06:02:50 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206752 kb
Host smart-816fde0f-4bf6-47d0-b4b5-66da3ada395b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15603
47019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_in_trans.1560347019
Directory /workspace/40.usbdev_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_invalid_sync.2767285167
Short name T207
Test name
Test status
Simulation time 7530887226 ps
CPU time 52.46 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:03:18 PM PDT 24
Peak memory 206944 kb
Host smart-856772c8-e7ed-4f72-9ea4-bcebeeebaefd
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2767285167 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_invalid_sync.2767285167
Directory /workspace/40.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/40.usbdev_iso_retraction.3098016232
Short name T1875
Test name
Test status
Simulation time 5685942914 ps
CPU time 48.09 seconds
Started Jul 22 06:02:28 PM PDT 24
Finished Jul 22 06:03:17 PM PDT 24
Peak memory 206940 kb
Host smart-48fe67df-83e2-4c09-acb4-3ae50fff1275
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30980
16232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_iso_retraction.3098016232
Directory /workspace/40.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/40.usbdev_link_in_err.572262679
Short name T2488
Test name
Test status
Simulation time 242329096 ps
CPU time 0.92 seconds
Started Jul 22 06:02:25 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206692 kb
Host smart-84fb8b60-e5a7-499c-b311-7ebc5c399b56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57226
2679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_in_err.572262679
Directory /workspace/40.usbdev_link_in_err/latest

Test location /workspace/coverage/default/40.usbdev_link_resume.1826388708
Short name T1492
Test name
Test status
Simulation time 23394819282 ps
CPU time 29.17 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:02:54 PM PDT 24
Peak memory 206764 kb
Host smart-7b7550e5-741f-4b5c-91b9-c28ae286029a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18263
88708 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_resume.1826388708
Directory /workspace/40.usbdev_link_resume/latest

Test location /workspace/coverage/default/40.usbdev_link_suspend.3432164384
Short name T2349
Test name
Test status
Simulation time 3299105408 ps
CPU time 4.17 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:45 PM PDT 24
Peak memory 206556 kb
Host smart-c7774c02-1bdf-44ae-8733-6d76754cd1de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34321
64384 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_link_suspend.3432164384
Directory /workspace/40.usbdev_link_suspend/latest

Test location /workspace/coverage/default/40.usbdev_low_speed_traffic.398772457
Short name T485
Test name
Test status
Simulation time 11218615573 ps
CPU time 295.42 seconds
Started Jul 22 06:02:26 PM PDT 24
Finished Jul 22 06:07:23 PM PDT 24
Peak memory 207000 kb
Host smart-6791df85-4355-4daf-bee6-d8d969800c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39877
2457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_low_speed_traffic.398772457
Directory /workspace/40.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/40.usbdev_max_inter_pkt_delay.1405987606
Short name T2561
Test name
Test status
Simulation time 6931408118 ps
CPU time 191.14 seconds
Started Jul 22 06:02:23 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 207072 kb
Host smart-8bb84480-d2c2-401e-9eb9-7e61441876aa
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1405987606 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_inter_pkt_delay.1405987606
Directory /workspace/40.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_max_length_in_transaction.3633347362
Short name T1082
Test name
Test status
Simulation time 274348795 ps
CPU time 0.92 seconds
Started Jul 22 06:02:27 PM PDT 24
Finished Jul 22 06:02:29 PM PDT 24
Peak memory 206680 kb
Host smart-f318a311-c6ef-4acc-89da-b008dd88bd62
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3633347362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_in_transaction.3633347362
Directory /workspace/40.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_length_out_transaction.2202074241
Short name T315
Test name
Test status
Simulation time 203389773 ps
CPU time 0.86 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206480 kb
Host smart-36780ff2-8149-421e-9834-6a4101c2eca8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22020
74241 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_length_out_transaction.2202074241
Directory /workspace/40.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_max_usb_traffic.4183053099
Short name T2385
Test name
Test status
Simulation time 7216739665 ps
CPU time 50.2 seconds
Started Jul 22 06:02:23 PM PDT 24
Finished Jul 22 06:03:15 PM PDT 24
Peak memory 206952 kb
Host smart-e6ca5d7e-1b32-42d9-8001-b92b4e28fc40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41830
53099 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_max_usb_traffic.4183053099
Directory /workspace/40.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/40.usbdev_min_inter_pkt_delay.3705884984
Short name T656
Test name
Test status
Simulation time 4274932317 ps
CPU time 37.42 seconds
Started Jul 22 06:02:32 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206812 kb
Host smart-86975801-25ec-4715-83b6-694400df8685
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3705884984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_inter_pkt_delay.3705884984
Directory /workspace/40.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/40.usbdev_min_length_in_transaction.2432274851
Short name T2508
Test name
Test status
Simulation time 156422057 ps
CPU time 0.85 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:02:25 PM PDT 24
Peak memory 206924 kb
Host smart-caf74cf1-89be-435b-8bb5-46832ecac889
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2432274851 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_in_transaction.2432274851
Directory /workspace/40.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_min_length_out_transaction.2349163979
Short name T1247
Test name
Test status
Simulation time 183321635 ps
CPU time 0.79 seconds
Started Jul 22 06:02:25 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206728 kb
Host smart-513583f3-2513-4dc6-920c-b522d18b0326
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23491
63979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_min_length_out_transaction.2349163979
Directory /workspace/40.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_nak_trans.1185173039
Short name T139
Test name
Test status
Simulation time 192357036 ps
CPU time 0.86 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:02:25 PM PDT 24
Peak memory 206744 kb
Host smart-d9174cd4-25e2-45e7-8008-c22aa5ccf791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
73039 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_nak_trans.1185173039
Directory /workspace/40.usbdev_nak_trans/latest

Test location /workspace/coverage/default/40.usbdev_out_iso.1293634998
Short name T921
Test name
Test status
Simulation time 199666975 ps
CPU time 0.82 seconds
Started Jul 22 06:02:28 PM PDT 24
Finished Jul 22 06:02:30 PM PDT 24
Peak memory 206696 kb
Host smart-33663d40-88cc-4028-beeb-c70a4c21a667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12936
34998 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_iso.1293634998
Directory /workspace/40.usbdev_out_iso/latest

Test location /workspace/coverage/default/40.usbdev_out_stall.4115946475
Short name T1703
Test name
Test status
Simulation time 187936810 ps
CPU time 0.82 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:02:26 PM PDT 24
Peak memory 206756 kb
Host smart-00bfd470-24cc-4f83-89e6-f90f5889e46b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41159
46475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_stall.4115946475
Directory /workspace/40.usbdev_out_stall/latest

Test location /workspace/coverage/default/40.usbdev_out_trans_nak.3749410073
Short name T1903
Test name
Test status
Simulation time 171002259 ps
CPU time 0.84 seconds
Started Jul 22 06:02:25 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206636 kb
Host smart-95c2f342-67df-4c0e-a180-9061558d7a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37494
10073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_out_trans_nak.3749410073
Directory /workspace/40.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/40.usbdev_pending_in_trans.3291869155
Short name T441
Test name
Test status
Simulation time 147072378 ps
CPU time 0.75 seconds
Started Jul 22 06:02:26 PM PDT 24
Finished Jul 22 06:02:28 PM PDT 24
Peak memory 206668 kb
Host smart-8a79f2ad-3216-4564-8881-c7da0c47fcf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
69155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pending_in_trans.3291869155
Directory /workspace/40.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_pinflip.2972323840
Short name T2381
Test name
Test status
Simulation time 248945694 ps
CPU time 0.97 seconds
Started Jul 22 06:02:34 PM PDT 24
Finished Jul 22 06:02:35 PM PDT 24
Peak memory 206756 kb
Host smart-d9c2411d-8503-4f21-aaa3-6eefc3b893b1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2972323840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_pinflip.2972323840
Directory /workspace/40.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/40.usbdev_phy_config_usb_ref_disable.4136034652
Short name T967
Test name
Test status
Simulation time 190558148 ps
CPU time 0.8 seconds
Started Jul 22 06:02:42 PM PDT 24
Finished Jul 22 06:02:43 PM PDT 24
Peak memory 206476 kb
Host smart-bb7d1119-f819-44a6-8279-3c1b909888a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41360
34652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_config_usb_ref_disable.4136034652
Directory /workspace/40.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/40.usbdev_phy_pins_sense.3113379427
Short name T43
Test name
Test status
Simulation time 60367676 ps
CPU time 0.66 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:39 PM PDT 24
Peak memory 206476 kb
Host smart-3912e21e-ca15-4cd7-9128-ded1db1fa690
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31133
79427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_phy_pins_sense.3113379427
Directory /workspace/40.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/40.usbdev_pkt_buffer.2480418937
Short name T249
Test name
Test status
Simulation time 7957092731 ps
CPU time 19.95 seconds
Started Jul 22 06:02:30 PM PDT 24
Finished Jul 22 06:02:50 PM PDT 24
Peak memory 206952 kb
Host smart-621dab82-ac76-42f3-afe2-8ed9412d270c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24804
18937 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_buffer.2480418937
Directory /workspace/40.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/40.usbdev_pkt_received.2443890190
Short name T2604
Test name
Test status
Simulation time 168475394 ps
CPU time 0.77 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206496 kb
Host smart-868ac211-b11c-4b59-bf43-5f0f5e9091a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24438
90190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_received.2443890190
Directory /workspace/40.usbdev_pkt_received/latest

Test location /workspace/coverage/default/40.usbdev_pkt_sent.1447565372
Short name T1350
Test name
Test status
Simulation time 241451875 ps
CPU time 0.94 seconds
Started Jul 22 06:02:28 PM PDT 24
Finished Jul 22 06:02:30 PM PDT 24
Peak memory 206668 kb
Host smart-d42ca0a2-15e2-45a8-94e7-197646da988f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14475
65372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_pkt_sent.1447565372
Directory /workspace/40.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/40.usbdev_random_length_in_transaction.2827865114
Short name T2725
Test name
Test status
Simulation time 211596479 ps
CPU time 0.91 seconds
Started Jul 22 06:02:24 PM PDT 24
Finished Jul 22 06:02:26 PM PDT 24
Peak memory 206796 kb
Host smart-ed3c2fd2-6611-4acb-8e6c-b0fab85f2f25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28278
65114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_in_transaction.2827865114
Directory /workspace/40.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/40.usbdev_random_length_out_transaction.1137303800
Short name T334
Test name
Test status
Simulation time 202363661 ps
CPU time 0.87 seconds
Started Jul 22 06:02:25 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206732 kb
Host smart-9314e7cf-b8b3-4f97-aba2-886a9c1890ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11373
03800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_random_length_out_transaction.1137303800
Directory /workspace/40.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/40.usbdev_rx_crc_err.980778909
Short name T416
Test name
Test status
Simulation time 138604084 ps
CPU time 0.73 seconds
Started Jul 22 06:02:26 PM PDT 24
Finished Jul 22 06:02:28 PM PDT 24
Peak memory 206732 kb
Host smart-add77074-c159-4ec5-b09b-8330c4a5b64f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98077
8909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_rx_crc_err.980778909
Directory /workspace/40.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/40.usbdev_setup_stage.318797657
Short name T865
Test name
Test status
Simulation time 185239080 ps
CPU time 0.77 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206484 kb
Host smart-ad64f813-04f1-42f7-beca-e1520e5ab1f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31879
7657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_stage.318797657
Directory /workspace/40.usbdev_setup_stage/latest

Test location /workspace/coverage/default/40.usbdev_setup_trans_ignored.4012672594
Short name T38
Test name
Test status
Simulation time 174416431 ps
CPU time 0.82 seconds
Started Jul 22 06:02:32 PM PDT 24
Finished Jul 22 06:02:33 PM PDT 24
Peak memory 206728 kb
Host smart-092a5c4d-c058-4c48-a5e9-f04b91718bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40126
72594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_setup_trans_ignored.4012672594
Directory /workspace/40.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/40.usbdev_smoke.2775108115
Short name T963
Test name
Test status
Simulation time 281905635 ps
CPU time 1.04 seconds
Started Jul 22 06:02:26 PM PDT 24
Finished Jul 22 06:02:28 PM PDT 24
Peak memory 206748 kb
Host smart-eaea968a-87c1-40bb-b5a0-bd9e7bda00ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27751
08115 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_smoke.2775108115
Directory /workspace/40.usbdev_smoke/latest

Test location /workspace/coverage/default/40.usbdev_spurious_pids_ignored.2496030354
Short name T955
Test name
Test status
Simulation time 3991641712 ps
CPU time 36.45 seconds
Started Jul 22 06:02:29 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206880 kb
Host smart-0b47fd6c-aff8-483d-a88c-a761556b4cfb
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2496030354 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_spurious_pids_ignored.2496030354
Directory /workspace/40.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/40.usbdev_stall_priority_over_nak.2698001073
Short name T1366
Test name
Test status
Simulation time 183909208 ps
CPU time 0.82 seconds
Started Jul 22 06:02:25 PM PDT 24
Finished Jul 22 06:02:27 PM PDT 24
Peak memory 206732 kb
Host smart-fe7ad6a4-9399-461d-afce-c24948441327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26980
01073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_priority_over_nak.2698001073
Directory /workspace/40.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/40.usbdev_stall_trans.2098997519
Short name T2749
Test name
Test status
Simulation time 165153830 ps
CPU time 0.77 seconds
Started Jul 22 06:02:28 PM PDT 24
Finished Jul 22 06:02:30 PM PDT 24
Peak memory 206748 kb
Host smart-08ceed21-29cd-4fff-b3f9-b6b50ed180b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20989
97519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stall_trans.2098997519
Directory /workspace/40.usbdev_stall_trans/latest

Test location /workspace/coverage/default/40.usbdev_stream_len_max.1218818599
Short name T2345
Test name
Test status
Simulation time 378129411 ps
CPU time 1.12 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206504 kb
Host smart-3239c3b3-54eb-4842-ac93-f8946d5f6227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12188
18599 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_stream_len_max.1218818599
Directory /workspace/40.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/40.usbdev_streaming_out.1576727529
Short name T1555
Test name
Test status
Simulation time 3950490919 ps
CPU time 107.9 seconds
Started Jul 22 06:02:30 PM PDT 24
Finished Jul 22 06:04:18 PM PDT 24
Peak memory 206904 kb
Host smart-9b26d7c5-a78b-4a29-b276-2fdf8ea87d22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15767
27529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.usbdev_streaming_out.1576727529
Directory /workspace/40.usbdev_streaming_out/latest

Test location /workspace/coverage/default/41.usbdev_alert_test.4182336861
Short name T483
Test name
Test status
Simulation time 53250991 ps
CPU time 0.68 seconds
Started Jul 22 06:02:43 PM PDT 24
Finished Jul 22 06:02:44 PM PDT 24
Peak memory 206740 kb
Host smart-cedf4f1c-5f03-48bc-9ee4-ce86faccbd10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4182336861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_alert_test.4182336861
Directory /workspace/41.usbdev_alert_test/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_disconnect.3776857797
Short name T808
Test name
Test status
Simulation time 3671433552 ps
CPU time 4.32 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206696 kb
Host smart-b8619581-ebc7-4210-9318-01a520637586
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3776857797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_disconnect.3776857797
Directory /workspace/41.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_reset.3745902291
Short name T2572
Test name
Test status
Simulation time 13345794309 ps
CPU time 12.61 seconds
Started Jul 22 06:02:34 PM PDT 24
Finished Jul 22 06:02:48 PM PDT 24
Peak memory 206968 kb
Host smart-17ff5985-c654-41d2-8f48-2fe67f809cdf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3745902291 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_reset.3745902291
Directory /workspace/41.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/41.usbdev_aon_wake_resume.3688414246
Short name T1389
Test name
Test status
Simulation time 23311665662 ps
CPU time 22.33 seconds
Started Jul 22 06:02:45 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206924 kb
Host smart-6c9af3bb-c867-444c-b57e-3ed624d91fa4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3688414246 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_aon_wake_resume.3688414246
Directory /workspace/41.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/41.usbdev_av_buffer.1975546009
Short name T514
Test name
Test status
Simulation time 164243426 ps
CPU time 0.85 seconds
Started Jul 22 06:02:46 PM PDT 24
Finished Jul 22 06:02:48 PM PDT 24
Peak memory 206712 kb
Host smart-de88c756-66b9-4a48-897d-51bc726aaf20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19755
46009 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_av_buffer.1975546009
Directory /workspace/41.usbdev_av_buffer/latest

Test location /workspace/coverage/default/41.usbdev_bitstuff_err.1223566548
Short name T2157
Test name
Test status
Simulation time 153281612 ps
CPU time 0.81 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206744 kb
Host smart-c3ad8c07-cd95-439e-8455-1e1d077e1333
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12235
66548 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_bitstuff_err.1223566548
Directory /workspace/41.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_clear.3143391710
Short name T797
Test name
Test status
Simulation time 328213575 ps
CPU time 1.17 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206648 kb
Host smart-7b47dcad-df53-474a-99fa-877d60293660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31433
91710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_clear.3143391710
Directory /workspace/41.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/41.usbdev_data_toggle_restore.2209732567
Short name T1694
Test name
Test status
Simulation time 462157803 ps
CPU time 1.29 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206752 kb
Host smart-668b214f-f1a2-429c-9069-130b0039affb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22097
32567 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_data_toggle_restore.2209732567
Directory /workspace/41.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/41.usbdev_device_address.2114414164
Short name T2521
Test name
Test status
Simulation time 7365049435 ps
CPU time 14.46 seconds
Started Jul 22 06:02:40 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206856 kb
Host smart-e59b7041-27ba-4aeb-a0ba-84f669a11610
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21144
14164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_device_address.2114414164
Directory /workspace/41.usbdev_device_address/latest

Test location /workspace/coverage/default/41.usbdev_disable_endpoint.3363272449
Short name T1746
Test name
Test status
Simulation time 486509189 ps
CPU time 1.53 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206724 kb
Host smart-2d8c5309-37a3-4ca0-92ea-98f7e372b542
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33632
72449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disable_endpoint.3363272449
Directory /workspace/41.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/41.usbdev_disconnected.1437357135
Short name T1749
Test name
Test status
Simulation time 182206646 ps
CPU time 0.75 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206760 kb
Host smart-cdad0cde-fbee-467d-b7fa-2ac84b4c083b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14373
57135 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_disconnected.1437357135
Directory /workspace/41.usbdev_disconnected/latest

Test location /workspace/coverage/default/41.usbdev_enable.439107285
Short name T1681
Test name
Test status
Simulation time 43416117 ps
CPU time 0.68 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206740 kb
Host smart-d0845348-ed11-4954-b1cb-70905ce9701c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43910
7285 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_enable.439107285
Directory /workspace/41.usbdev_enable/latest

Test location /workspace/coverage/default/41.usbdev_endpoint_access.3267325975
Short name T1601
Test name
Test status
Simulation time 907502902 ps
CPU time 1.93 seconds
Started Jul 22 06:02:36 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206904 kb
Host smart-2fd51c9c-23f5-4feb-afff-4a118b32d313
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32673
25975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_endpoint_access.3267325975
Directory /workspace/41.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/41.usbdev_fifo_rst.1905899452
Short name T1552
Test name
Test status
Simulation time 303422519 ps
CPU time 2.15 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206880 kb
Host smart-389e1411-6165-405f-90b5-53b074993626
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19058
99452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_fifo_rst.1905899452
Directory /workspace/41.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/41.usbdev_in_iso.3953718394
Short name T2204
Test name
Test status
Simulation time 205447284 ps
CPU time 0.84 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206748 kb
Host smart-0dd33ed6-bcb7-4451-b87d-ff271aa5bd46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39537
18394 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_iso.3953718394
Directory /workspace/41.usbdev_in_iso/latest

Test location /workspace/coverage/default/41.usbdev_in_stall.950903980
Short name T705
Test name
Test status
Simulation time 160605481 ps
CPU time 0.86 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206796 kb
Host smart-a913e4db-39e8-443d-8d43-4b67d5acad29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95090
3980 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_stall.950903980
Directory /workspace/41.usbdev_in_stall/latest

Test location /workspace/coverage/default/41.usbdev_in_trans.4098548566
Short name T1713
Test name
Test status
Simulation time 200973095 ps
CPU time 0.85 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206756 kb
Host smart-d465931a-bf8f-4a2e-8f07-6bc9af4abdc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40985
48566 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_in_trans.4098548566
Directory /workspace/41.usbdev_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_iso_retraction.2254151646
Short name T2638
Test name
Test status
Simulation time 4166742154 ps
CPU time 13.09 seconds
Started Jul 22 06:02:41 PM PDT 24
Finished Jul 22 06:02:55 PM PDT 24
Peak memory 206848 kb
Host smart-f8bdfb71-f67e-49ff-ab23-7b6f42582949
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22541
51646 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_iso_retraction.2254151646
Directory /workspace/41.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/41.usbdev_link_in_err.3755177495
Short name T1156
Test name
Test status
Simulation time 233521605 ps
CPU time 0.92 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206700 kb
Host smart-3566a4d9-90ea-495e-96b0-5b6c849a86f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37551
77495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_in_err.3755177495
Directory /workspace/41.usbdev_link_in_err/latest

Test location /workspace/coverage/default/41.usbdev_link_resume.3822888899
Short name T273
Test name
Test status
Simulation time 23311150398 ps
CPU time 23.05 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206816 kb
Host smart-13f8c0db-4420-4a56-9baa-3891bb8732da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38228
88899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_resume.3822888899
Directory /workspace/41.usbdev_link_resume/latest

Test location /workspace/coverage/default/41.usbdev_link_suspend.4290619090
Short name T709
Test name
Test status
Simulation time 3313386437 ps
CPU time 3.82 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:39 PM PDT 24
Peak memory 206820 kb
Host smart-5e64e091-9937-4a6a-b968-095e63f08912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42906
19090 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_link_suspend.4290619090
Directory /workspace/41.usbdev_link_suspend/latest

Test location /workspace/coverage/default/41.usbdev_low_speed_traffic.1659042270
Short name T1333
Test name
Test status
Simulation time 9741523525 ps
CPU time 67.25 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:03:46 PM PDT 24
Peak memory 206920 kb
Host smart-15edf742-5e00-464f-abf0-3e84ac402511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16590
42270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_low_speed_traffic.1659042270
Directory /workspace/41.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/41.usbdev_max_inter_pkt_delay.2925303026
Short name T2062
Test name
Test status
Simulation time 3500680353 ps
CPU time 94.17 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:04:13 PM PDT 24
Peak memory 206892 kb
Host smart-cfbf5c19-3e04-43bf-8bb0-7d1e5d5c9c6f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2925303026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_inter_pkt_delay.2925303026
Directory /workspace/41.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_max_length_in_transaction.1074258436
Short name T1368
Test name
Test status
Simulation time 298532478 ps
CPU time 0.9 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206748 kb
Host smart-13c4a966-1070-44d5-bbc6-ccfa43a48c00
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1074258436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_in_transaction.1074258436
Directory /workspace/41.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_length_out_transaction.3581022433
Short name T615
Test name
Test status
Simulation time 205913691 ps
CPU time 0.86 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206752 kb
Host smart-058156d6-9e35-4707-b154-8bdd511086b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35810
22433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_length_out_transaction.3581022433
Directory /workspace/41.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_max_usb_traffic.4253611097
Short name T911
Test name
Test status
Simulation time 4320802226 ps
CPU time 41.04 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206884 kb
Host smart-746b620e-3458-4840-9eb6-3744ac72089a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42536
11097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_max_usb_traffic.4253611097
Directory /workspace/41.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/41.usbdev_min_inter_pkt_delay.2525218526
Short name T890
Test name
Test status
Simulation time 7813309874 ps
CPU time 53.39 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:03:31 PM PDT 24
Peak memory 206876 kb
Host smart-38d915c7-856e-4846-90cd-e4561541686a
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2525218526 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_inter_pkt_delay.2525218526
Directory /workspace/41.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/41.usbdev_min_length_in_transaction.944700433
Short name T436
Test name
Test status
Simulation time 153976996 ps
CPU time 0.76 seconds
Started Jul 22 06:02:34 PM PDT 24
Finished Jul 22 06:02:35 PM PDT 24
Peak memory 206756 kb
Host smart-d77acc27-db68-449e-b80c-6de43987483c
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=944700433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_in_transaction.944700433
Directory /workspace/41.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_min_length_out_transaction.1332385314
Short name T1536
Test name
Test status
Simulation time 158153265 ps
CPU time 0.8 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206748 kb
Host smart-fef9ef2c-f143-4caf-a29d-39d20023edeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13323
85314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_min_length_out_transaction.1332385314
Directory /workspace/41.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_out_iso.1228605455
Short name T1395
Test name
Test status
Simulation time 189664290 ps
CPU time 0.86 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206628 kb
Host smart-fbfbf2f4-af9e-4c67-8b04-ca3454af7156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12286
05455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_iso.1228605455
Directory /workspace/41.usbdev_out_iso/latest

Test location /workspace/coverage/default/41.usbdev_out_stall.4046751486
Short name T1474
Test name
Test status
Simulation time 170759395 ps
CPU time 0.85 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206748 kb
Host smart-e612f76f-5be5-4ad3-8f88-bce0f03ad8fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40467
51486 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_stall.4046751486
Directory /workspace/41.usbdev_out_stall/latest

Test location /workspace/coverage/default/41.usbdev_out_trans_nak.432680156
Short name T2728
Test name
Test status
Simulation time 171870279 ps
CPU time 0.82 seconds
Started Jul 22 06:02:40 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206692 kb
Host smart-787b96d3-d9b0-4ad0-ac71-0c6518e43165
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43268
0156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_out_trans_nak.432680156
Directory /workspace/41.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/41.usbdev_pending_in_trans.3421320164
Short name T2517
Test name
Test status
Simulation time 151440694 ps
CPU time 0.78 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:36 PM PDT 24
Peak memory 206748 kb
Host smart-88f6baed-b24a-4f50-8e30-261ba996e2d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34213
20164 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pending_in_trans.3421320164
Directory /workspace/41.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_pinflip.2949671594
Short name T950
Test name
Test status
Simulation time 240179889 ps
CPU time 0.94 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206756 kb
Host smart-9f380891-d0d0-4897-aa76-b6429f9e9ac2
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2949671594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_pinflip.2949671594
Directory /workspace/41.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/41.usbdev_phy_config_usb_ref_disable.1016453881
Short name T1218
Test name
Test status
Simulation time 144020295 ps
CPU time 0.82 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206724 kb
Host smart-2227d6ad-7eb3-491a-88e4-80fe4549f45f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
53881 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_config_usb_ref_disable.1016453881
Directory /workspace/41.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/41.usbdev_phy_pins_sense.3358204221
Short name T1921
Test name
Test status
Simulation time 54023610 ps
CPU time 0.69 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206644 kb
Host smart-fec859e0-8797-4080-bbc8-84ac675f9d90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33582
04221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_phy_pins_sense.3358204221
Directory /workspace/41.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/41.usbdev_pkt_buffer.190595761
Short name T2090
Test name
Test status
Simulation time 13373043002 ps
CPU time 27.91 seconds
Started Jul 22 06:02:42 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206896 kb
Host smart-6b2d70d5-dc45-4c7c-87f3-bff6ff28e1a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19059
5761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_buffer.190595761
Directory /workspace/41.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/41.usbdev_pkt_received.151543834
Short name T1148
Test name
Test status
Simulation time 169422027 ps
CPU time 0.81 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206752 kb
Host smart-1de0b107-a4d9-42f5-bc9d-d0f815dca150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15154
3834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_received.151543834
Directory /workspace/41.usbdev_pkt_received/latest

Test location /workspace/coverage/default/41.usbdev_pkt_sent.2190754341
Short name T1822
Test name
Test status
Simulation time 163065036 ps
CPU time 0.81 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:39 PM PDT 24
Peak memory 206720 kb
Host smart-0c29d84c-1728-4e00-a33f-102aac4d8ed4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21907
54341 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_pkt_sent.2190754341
Directory /workspace/41.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/41.usbdev_random_length_in_transaction.3994119782
Short name T1994
Test name
Test status
Simulation time 209484706 ps
CPU time 0.89 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:37 PM PDT 24
Peak memory 206796 kb
Host smart-4ba13e19-8510-4428-af3c-a8363d72fcac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39941
19782 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_in_transaction.3994119782
Directory /workspace/41.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/41.usbdev_random_length_out_transaction.123903016
Short name T401
Test name
Test status
Simulation time 196950017 ps
CPU time 0.85 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206744 kb
Host smart-0814d051-f636-44d5-bf58-dd4b8e8d0047
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12390
3016 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_random_length_out_transaction.123903016
Directory /workspace/41.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/41.usbdev_rx_crc_err.4226049706
Short name T1993
Test name
Test status
Simulation time 260524596 ps
CPU time 0.99 seconds
Started Jul 22 06:02:40 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206556 kb
Host smart-41ae6f7f-563a-451c-a779-fca8f5b49dd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42260
49706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_rx_crc_err.4226049706
Directory /workspace/41.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/41.usbdev_setup_stage.3266268963
Short name T1174
Test name
Test status
Simulation time 179735677 ps
CPU time 0.76 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:02:41 PM PDT 24
Peak memory 206744 kb
Host smart-ce1b450c-a4d0-453f-8a37-3f2239a1b7c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
68963 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_stage.3266268963
Directory /workspace/41.usbdev_setup_stage/latest

Test location /workspace/coverage/default/41.usbdev_setup_trans_ignored.824491453
Short name T2109
Test name
Test status
Simulation time 163073159 ps
CPU time 0.84 seconds
Started Jul 22 06:02:45 PM PDT 24
Finished Jul 22 06:02:46 PM PDT 24
Peak memory 206724 kb
Host smart-fcf2fd24-7323-4999-829b-b09c4af092dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82449
1453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_setup_trans_ignored.824491453
Directory /workspace/41.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/41.usbdev_smoke.626997692
Short name T2253
Test name
Test status
Simulation time 204258714 ps
CPU time 0.87 seconds
Started Jul 22 06:02:34 PM PDT 24
Finished Jul 22 06:02:35 PM PDT 24
Peak memory 206652 kb
Host smart-1e581737-2306-4bed-913c-1dd1604ba7cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62699
7692 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_smoke.626997692
Directory /workspace/41.usbdev_smoke/latest

Test location /workspace/coverage/default/41.usbdev_spurious_pids_ignored.1266688884
Short name T787
Test name
Test status
Simulation time 5360885602 ps
CPU time 147.07 seconds
Started Jul 22 06:02:39 PM PDT 24
Finished Jul 22 06:05:08 PM PDT 24
Peak memory 206800 kb
Host smart-51476f7a-050b-4f97-add0-e1d811150ee2
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1266688884 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_spurious_pids_ignored.1266688884
Directory /workspace/41.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/41.usbdev_stall_priority_over_nak.185032436
Short name T2683
Test name
Test status
Simulation time 202827560 ps
CPU time 0.8 seconds
Started Jul 22 06:02:34 PM PDT 24
Finished Jul 22 06:02:35 PM PDT 24
Peak memory 206724 kb
Host smart-3db666c8-dea2-4ca0-80be-4b2bbfdea30d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18503
2436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_priority_over_nak.185032436
Directory /workspace/41.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/41.usbdev_stall_trans.1109335143
Short name T2690
Test name
Test status
Simulation time 178050767 ps
CPU time 0.82 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206744 kb
Host smart-e1d7181d-712b-4628-9887-50d1a2af31e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11093
35143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stall_trans.1109335143
Directory /workspace/41.usbdev_stall_trans/latest

Test location /workspace/coverage/default/41.usbdev_stream_len_max.1733409469
Short name T2158
Test name
Test status
Simulation time 965983278 ps
CPU time 2.2 seconds
Started Jul 22 06:02:48 PM PDT 24
Finished Jul 22 06:02:51 PM PDT 24
Peak memory 206880 kb
Host smart-39e3b638-0966-4b83-a5ff-4d20ecb4347e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17334
09469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_stream_len_max.1733409469
Directory /workspace/41.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/41.usbdev_streaming_out.404481140
Short name T1514
Test name
Test status
Simulation time 5319718626 ps
CPU time 40.81 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:03:19 PM PDT 24
Peak memory 206892 kb
Host smart-601d8ea4-9c08-4c4a-8be2-9e805217d09d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40448
1140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.usbdev_streaming_out.404481140
Directory /workspace/41.usbdev_streaming_out/latest

Test location /workspace/coverage/default/42.usbdev_alert_test.3360169350
Short name T184
Test name
Test status
Simulation time 62871987 ps
CPU time 0.71 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206724 kb
Host smart-81fb0c93-771f-4dfb-9434-35ffc8e9d22e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3360169350 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_alert_test.3360169350
Directory /workspace/42.usbdev_alert_test/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_disconnect.1828318629
Short name T12
Test name
Test status
Simulation time 3674031096 ps
CPU time 4.72 seconds
Started Jul 22 06:02:40 PM PDT 24
Finished Jul 22 06:02:46 PM PDT 24
Peak memory 206772 kb
Host smart-6afef5f9-e0f1-4024-b09f-615ad18603a5
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1828318629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_disconnect.1828318629
Directory /workspace/42.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_reset.2153867361
Short name T1722
Test name
Test status
Simulation time 13319824952 ps
CPU time 11.53 seconds
Started Jul 22 06:02:46 PM PDT 24
Finished Jul 22 06:02:59 PM PDT 24
Peak memory 206924 kb
Host smart-861fec26-6284-4ac6-bf52-3823ed782336
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2153867361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_reset.2153867361
Directory /workspace/42.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/42.usbdev_aon_wake_resume.9021685
Short name T10
Test name
Test status
Simulation time 23395740473 ps
CPU time 23.81 seconds
Started Jul 22 06:02:38 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206876 kb
Host smart-e85e8da8-77fb-4ee1-9ae7-113462b666ef
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=9021685 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_aon_wake_resume.9021685
Directory /workspace/42.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/42.usbdev_av_buffer.2773719052
Short name T2113
Test name
Test status
Simulation time 175331782 ps
CPU time 0.86 seconds
Started Jul 22 06:02:40 PM PDT 24
Finished Jul 22 06:02:42 PM PDT 24
Peak memory 206748 kb
Host smart-4c4ea130-63d5-4d04-8d59-17ef722a825c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27737
19052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_av_buffer.2773719052
Directory /workspace/42.usbdev_av_buffer/latest

Test location /workspace/coverage/default/42.usbdev_bitstuff_err.2764693977
Short name T534
Test name
Test status
Simulation time 149550348 ps
CPU time 0.75 seconds
Started Jul 22 06:02:37 PM PDT 24
Finished Jul 22 06:02:40 PM PDT 24
Peak memory 206732 kb
Host smart-bacf1773-fe29-4698-a8f7-9a61530a64f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27646
93977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_bitstuff_err.2764693977
Directory /workspace/42.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_clear.3373679903
Short name T108
Test name
Test status
Simulation time 518766235 ps
CPU time 1.54 seconds
Started Jul 22 06:02:45 PM PDT 24
Finished Jul 22 06:02:47 PM PDT 24
Peak memory 206872 kb
Host smart-4a861fea-36f1-467d-a5b8-6f361359573d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33736
79903 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_clear.3373679903
Directory /workspace/42.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/42.usbdev_data_toggle_restore.3599709828
Short name T1000
Test name
Test status
Simulation time 836698248 ps
CPU time 2.29 seconds
Started Jul 22 06:02:35 PM PDT 24
Finished Jul 22 06:02:38 PM PDT 24
Peak memory 206840 kb
Host smart-efcee2f5-c028-4def-95f5-cb00eee40061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35997
09828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_data_toggle_restore.3599709828
Directory /workspace/42.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/42.usbdev_device_address.155354828
Short name T1754
Test name
Test status
Simulation time 20618278569 ps
CPU time 38.42 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:03:31 PM PDT 24
Peak memory 206920 kb
Host smart-7d83b686-8573-4eda-84ec-9c5c7652d2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15535
4828 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_device_address.155354828
Directory /workspace/42.usbdev_device_address/latest

Test location /workspace/coverage/default/42.usbdev_disable_endpoint.73275802
Short name T1977
Test name
Test status
Simulation time 417124489 ps
CPU time 1.29 seconds
Started Jul 22 06:02:50 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206708 kb
Host smart-773c19a0-0a90-485a-adf4-d96cc2214caf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73275
802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disable_endpoint.73275802
Directory /workspace/42.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/42.usbdev_disconnected.1704479970
Short name T1998
Test name
Test status
Simulation time 161332557 ps
CPU time 0.78 seconds
Started Jul 22 06:02:49 PM PDT 24
Finished Jul 22 06:02:50 PM PDT 24
Peak memory 206724 kb
Host smart-628954b8-c72e-4be6-b966-ef15bde97dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17044
79970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_disconnected.1704479970
Directory /workspace/42.usbdev_disconnected/latest

Test location /workspace/coverage/default/42.usbdev_enable.894056100
Short name T1597
Test name
Test status
Simulation time 90110099 ps
CPU time 0.69 seconds
Started Jul 22 06:02:57 PM PDT 24
Finished Jul 22 06:02:58 PM PDT 24
Peak memory 206708 kb
Host smart-7f3d600d-cc75-40f5-aed1-39a2839fd3b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89405
6100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_enable.894056100
Directory /workspace/42.usbdev_enable/latest

Test location /workspace/coverage/default/42.usbdev_endpoint_access.3907168810
Short name T1889
Test name
Test status
Simulation time 902684969 ps
CPU time 2.52 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 206880 kb
Host smart-c15636ac-a7b6-4935-b3b7-1b8392de04c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39071
68810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_endpoint_access.3907168810
Directory /workspace/42.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/42.usbdev_fifo_rst.305222336
Short name T1897
Test name
Test status
Simulation time 356091957 ps
CPU time 2.18 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:02:58 PM PDT 24
Peak memory 206888 kb
Host smart-9016d158-8794-49a2-8dbc-bebd81fa4cbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30522
2336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_fifo_rst.305222336
Directory /workspace/42.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/42.usbdev_in_iso.3555129934
Short name T547
Test name
Test status
Simulation time 214617173 ps
CPU time 0.92 seconds
Started Jul 22 06:02:48 PM PDT 24
Finished Jul 22 06:02:49 PM PDT 24
Peak memory 206672 kb
Host smart-4b5ff2b4-7520-4475-a0bf-672e853710c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35551
29934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_iso.3555129934
Directory /workspace/42.usbdev_in_iso/latest

Test location /workspace/coverage/default/42.usbdev_in_stall.3668948352
Short name T2539
Test name
Test status
Simulation time 147727819 ps
CPU time 0.74 seconds
Started Jul 22 06:02:50 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206728 kb
Host smart-d98505a4-73a2-4618-bebc-578dfc46babb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36689
48352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_stall.3668948352
Directory /workspace/42.usbdev_in_stall/latest

Test location /workspace/coverage/default/42.usbdev_in_trans.3451546535
Short name T1328
Test name
Test status
Simulation time 176599818 ps
CPU time 0.82 seconds
Started Jul 22 06:02:54 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206780 kb
Host smart-5ce25318-564e-4872-82d1-3ee73f5cfa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34515
46535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_in_trans.3451546535
Directory /workspace/42.usbdev_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_iso_retraction.3923674243
Short name T1625
Test name
Test status
Simulation time 9094355791 ps
CPU time 32.74 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:03:29 PM PDT 24
Peak memory 207000 kb
Host smart-35ed296c-f16a-4ae9-89f0-2c14485eef2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39236
74243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_iso_retraction.3923674243
Directory /workspace/42.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/42.usbdev_link_in_err.4054345376
Short name T1520
Test name
Test status
Simulation time 209718114 ps
CPU time 0.93 seconds
Started Jul 22 06:02:54 PM PDT 24
Finished Jul 22 06:02:55 PM PDT 24
Peak memory 206704 kb
Host smart-93edcb97-514a-4c33-81c1-8b3d1a7ac084
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40543
45376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_in_err.4054345376
Directory /workspace/42.usbdev_link_in_err/latest

Test location /workspace/coverage/default/42.usbdev_link_resume.3074693201
Short name T378
Test name
Test status
Simulation time 23313523499 ps
CPU time 23.2 seconds
Started Jul 22 06:02:53 PM PDT 24
Finished Jul 22 06:03:17 PM PDT 24
Peak memory 206816 kb
Host smart-140f9955-67a4-45bc-9652-f1d16939ac4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30746
93201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_resume.3074693201
Directory /workspace/42.usbdev_link_resume/latest

Test location /workspace/coverage/default/42.usbdev_link_suspend.2689678840
Short name T999
Test name
Test status
Simulation time 3368440719 ps
CPU time 3.83 seconds
Started Jul 22 06:02:52 PM PDT 24
Finished Jul 22 06:02:57 PM PDT 24
Peak memory 206816 kb
Host smart-59e804f0-01be-4108-94f3-83ee8ccea23e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26896
78840 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_link_suspend.2689678840
Directory /workspace/42.usbdev_link_suspend/latest

Test location /workspace/coverage/default/42.usbdev_low_speed_traffic.3129198361
Short name T1473
Test name
Test status
Simulation time 8032204070 ps
CPU time 61.97 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206944 kb
Host smart-92b213ea-0919-45d5-a1df-4a0d46b68087
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31291
98361 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_low_speed_traffic.3129198361
Directory /workspace/42.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/42.usbdev_max_inter_pkt_delay.3575977621
Short name T1742
Test name
Test status
Simulation time 6359827349 ps
CPU time 169.13 seconds
Started Jul 22 06:02:50 PM PDT 24
Finished Jul 22 06:05:39 PM PDT 24
Peak memory 206848 kb
Host smart-aaec2555-d38c-4c0f-85b8-bb0ec854ca0d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3575977621 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_inter_pkt_delay.3575977621
Directory /workspace/42.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_max_length_in_transaction.1177854629
Short name T691
Test name
Test status
Simulation time 243055972 ps
CPU time 0.91 seconds
Started Jul 22 06:02:49 PM PDT 24
Finished Jul 22 06:02:50 PM PDT 24
Peak memory 206668 kb
Host smart-f134d19c-3ddd-4364-8eaf-9f85f53ed415
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1177854629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_in_transaction.1177854629
Directory /workspace/42.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_length_out_transaction.1385654662
Short name T451
Test name
Test status
Simulation time 232264726 ps
CPU time 0.86 seconds
Started Jul 22 06:02:49 PM PDT 24
Finished Jul 22 06:02:50 PM PDT 24
Peak memory 206736 kb
Host smart-566d4b91-b11c-4724-a4df-943055bf2294
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13856
54662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_length_out_transaction.1385654662
Directory /workspace/42.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_max_usb_traffic.2246198733
Short name T2639
Test name
Test status
Simulation time 3865324667 ps
CPU time 33.2 seconds
Started Jul 22 06:02:54 PM PDT 24
Finished Jul 22 06:03:27 PM PDT 24
Peak memory 206860 kb
Host smart-9927d9b3-f9be-4166-a854-9c915bce2095
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22461
98733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_max_usb_traffic.2246198733
Directory /workspace/42.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/42.usbdev_min_inter_pkt_delay.1858919481
Short name T2006
Test name
Test status
Simulation time 3699571779 ps
CPU time 106.11 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:04:38 PM PDT 24
Peak memory 206920 kb
Host smart-bee555cd-b7e1-4671-80a7-49ee4aa9512f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1858919481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_inter_pkt_delay.1858919481
Directory /workspace/42.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/42.usbdev_min_length_in_transaction.2541456723
Short name T2171
Test name
Test status
Simulation time 157544220 ps
CPU time 0.79 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206784 kb
Host smart-f0393045-beb2-40ef-8422-b138c89aba62
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2541456723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_in_transaction.2541456723
Directory /workspace/42.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_min_length_out_transaction.3608514756
Short name T1969
Test name
Test status
Simulation time 146906261 ps
CPU time 0.74 seconds
Started Jul 22 06:02:48 PM PDT 24
Finished Jul 22 06:02:49 PM PDT 24
Peak memory 206748 kb
Host smart-8395c4ee-d7ca-4b78-979d-4308be436e39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36085
14756 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_min_length_out_transaction.3608514756
Directory /workspace/42.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_nak_trans.4006049867
Short name T114
Test name
Test status
Simulation time 221733312 ps
CPU time 0.88 seconds
Started Jul 22 06:02:58 PM PDT 24
Finished Jul 22 06:02:59 PM PDT 24
Peak memory 206736 kb
Host smart-8e3576ed-d330-450b-85df-faeffac05cdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40060
49867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_nak_trans.4006049867
Directory /workspace/42.usbdev_nak_trans/latest

Test location /workspace/coverage/default/42.usbdev_out_iso.3149100483
Short name T2484
Test name
Test status
Simulation time 184834014 ps
CPU time 0.85 seconds
Started Jul 22 06:02:54 PM PDT 24
Finished Jul 22 06:02:55 PM PDT 24
Peak memory 206720 kb
Host smart-f0c54cb4-8836-4f00-8cf8-a82f8f8fe3a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31491
00483 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_iso.3149100483
Directory /workspace/42.usbdev_out_iso/latest

Test location /workspace/coverage/default/42.usbdev_out_stall.2775602616
Short name T1458
Test name
Test status
Simulation time 170661369 ps
CPU time 0.8 seconds
Started Jul 22 06:02:53 PM PDT 24
Finished Jul 22 06:02:54 PM PDT 24
Peak memory 206756 kb
Host smart-8ea34560-fdcd-4064-acd7-a166784a09f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27756
02616 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_stall.2775602616
Directory /workspace/42.usbdev_out_stall/latest

Test location /workspace/coverage/default/42.usbdev_out_trans_nak.3067062892
Short name T585
Test name
Test status
Simulation time 148315062 ps
CPU time 0.78 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206748 kb
Host smart-256553a0-af97-41f8-b9b9-cf2414422b72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30670
62892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_out_trans_nak.3067062892
Directory /workspace/42.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/42.usbdev_pending_in_trans.3733694386
Short name T456
Test name
Test status
Simulation time 145494165 ps
CPU time 0.72 seconds
Started Jul 22 06:02:54 PM PDT 24
Finished Jul 22 06:02:55 PM PDT 24
Peak memory 206724 kb
Host smart-ff56641b-0280-4d1e-ba88-ab7374839c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37336
94386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pending_in_trans.3733694386
Directory /workspace/42.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_pinflip.3541839584
Short name T1024
Test name
Test status
Simulation time 234088128 ps
CPU time 0.94 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206724 kb
Host smart-3cbb1b6c-b42a-4e44-a903-b61dd66ff00b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3541839584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_pinflip.3541839584
Directory /workspace/42.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/42.usbdev_phy_config_usb_ref_disable.1622146446
Short name T883
Test name
Test status
Simulation time 147307147 ps
CPU time 0.79 seconds
Started Jul 22 06:02:47 PM PDT 24
Finished Jul 22 06:02:48 PM PDT 24
Peak memory 206912 kb
Host smart-603d01fc-9403-4d0c-9328-8a2ca286e06b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16221
46446 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_config_usb_ref_disable.1622146446
Directory /workspace/42.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/42.usbdev_phy_pins_sense.2213355385
Short name T1940
Test name
Test status
Simulation time 38169856 ps
CPU time 0.65 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206704 kb
Host smart-fc30456f-5759-44be-904d-d64543f22d6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22133
55385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_phy_pins_sense.2213355385
Directory /workspace/42.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/42.usbdev_pkt_buffer.971536491
Short name T1611
Test name
Test status
Simulation time 11239379010 ps
CPU time 26.45 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:03:19 PM PDT 24
Peak memory 206968 kb
Host smart-75dbbea1-b175-45b8-9a0c-2aa90f64d8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97153
6491 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_buffer.971536491
Directory /workspace/42.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/42.usbdev_pkt_received.1157780328
Short name T2152
Test name
Test status
Simulation time 214526048 ps
CPU time 0.89 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:02:57 PM PDT 24
Peak memory 206712 kb
Host smart-875ef561-aa4d-42bd-969d-e9d27dca82a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11577
80328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_received.1157780328
Directory /workspace/42.usbdev_pkt_received/latest

Test location /workspace/coverage/default/42.usbdev_pkt_sent.126072073
Short name T438
Test name
Test status
Simulation time 237835415 ps
CPU time 0.93 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206720 kb
Host smart-5f9534d8-1e79-40a7-9b77-f37921f93da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12607
2073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_pkt_sent.126072073
Directory /workspace/42.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/42.usbdev_random_length_in_transaction.4277404789
Short name T1436
Test name
Test status
Simulation time 243818920 ps
CPU time 0.87 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206748 kb
Host smart-e2a701fd-5178-40b0-8571-178d57f2be77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42774
04789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_in_transaction.4277404789
Directory /workspace/42.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/42.usbdev_random_length_out_transaction.1521598200
Short name T810
Test name
Test status
Simulation time 175929952 ps
CPU time 0.85 seconds
Started Jul 22 06:02:47 PM PDT 24
Finished Jul 22 06:02:49 PM PDT 24
Peak memory 206728 kb
Host smart-22b62654-8e2e-40c7-b627-196627c008bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15215
98200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_random_length_out_transaction.1521598200
Directory /workspace/42.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/42.usbdev_rx_crc_err.1195113475
Short name T1768
Test name
Test status
Simulation time 145928224 ps
CPU time 0.75 seconds
Started Jul 22 06:02:46 PM PDT 24
Finished Jul 22 06:02:48 PM PDT 24
Peak memory 206656 kb
Host smart-d09a8079-4e49-4b16-877b-b4bfc4dc6041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11951
13475 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_rx_crc_err.1195113475
Directory /workspace/42.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/42.usbdev_setup_stage.741272065
Short name T587
Test name
Test status
Simulation time 169404351 ps
CPU time 0.83 seconds
Started Jul 22 06:02:49 PM PDT 24
Finished Jul 22 06:02:51 PM PDT 24
Peak memory 206732 kb
Host smart-4d503294-6f4d-4e24-bee7-535090af831f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74127
2065 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_stage.741272065
Directory /workspace/42.usbdev_setup_stage/latest

Test location /workspace/coverage/default/42.usbdev_setup_trans_ignored.1021039289
Short name T569
Test name
Test status
Simulation time 159396953 ps
CPU time 0.82 seconds
Started Jul 22 06:02:54 PM PDT 24
Finished Jul 22 06:02:55 PM PDT 24
Peak memory 206748 kb
Host smart-edc01f2a-0da8-496b-a576-a2728b9a9bf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10210
39289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_setup_trans_ignored.1021039289
Directory /workspace/42.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/42.usbdev_smoke.2643383745
Short name T2210
Test name
Test status
Simulation time 228267577 ps
CPU time 0.94 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206716 kb
Host smart-92ef3284-310f-4293-97b2-3970a2ddb349
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26433
83745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_smoke.2643383745
Directory /workspace/42.usbdev_smoke/latest

Test location /workspace/coverage/default/42.usbdev_spurious_pids_ignored.1668949073
Short name T154
Test name
Test status
Simulation time 5579293123 ps
CPU time 50.89 seconds
Started Jul 22 06:02:50 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206772 kb
Host smart-9e292d01-5e7e-4c85-b5cc-0bc9c989a7fe
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=1668949073 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_spurious_pids_ignored.1668949073
Directory /workspace/42.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/42.usbdev_stall_priority_over_nak.4136789641
Short name T1617
Test name
Test status
Simulation time 166977449 ps
CPU time 0.79 seconds
Started Jul 22 06:02:52 PM PDT 24
Finished Jul 22 06:02:54 PM PDT 24
Peak memory 206736 kb
Host smart-459e7df5-6b55-43fc-b712-0217d56caa2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41367
89641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_priority_over_nak.4136789641
Directory /workspace/42.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/42.usbdev_stall_trans.3423618064
Short name T1380
Test name
Test status
Simulation time 154394961 ps
CPU time 0.8 seconds
Started Jul 22 06:04:01 PM PDT 24
Finished Jul 22 06:04:02 PM PDT 24
Peak memory 206744 kb
Host smart-3ff02106-9d65-41b2-8c71-874b5f057d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34236
18064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stall_trans.3423618064
Directory /workspace/42.usbdev_stall_trans/latest

Test location /workspace/coverage/default/42.usbdev_stream_len_max.357743751
Short name T2086
Test name
Test status
Simulation time 343795010 ps
CPU time 1.13 seconds
Started Jul 22 06:02:50 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206688 kb
Host smart-769458fc-b712-47c6-a3a7-e2ee3a28aa6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35774
3751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_stream_len_max.357743751
Directory /workspace/42.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/42.usbdev_streaming_out.2346306298
Short name T1878
Test name
Test status
Simulation time 4156220355 ps
CPU time 38.34 seconds
Started Jul 22 06:03:30 PM PDT 24
Finished Jul 22 06:04:08 PM PDT 24
Peak memory 206900 kb
Host smart-d717f7cf-8e92-4c4e-9e01-2f3c2f527d5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23463
06298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.usbdev_streaming_out.2346306298
Directory /workspace/42.usbdev_streaming_out/latest

Test location /workspace/coverage/default/43.usbdev_alert_test.3796004557
Short name T545
Test name
Test status
Simulation time 79274666 ps
CPU time 0.74 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206696 kb
Host smart-7080511a-9b1e-4209-b96a-16e4d2229daa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3796004557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_alert_test.3796004557
Directory /workspace/43.usbdev_alert_test/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_disconnect.731208094
Short name T1731
Test name
Test status
Simulation time 3606775644 ps
CPU time 4.59 seconds
Started Jul 22 06:02:53 PM PDT 24
Finished Jul 22 06:02:58 PM PDT 24
Peak memory 206964 kb
Host smart-482d5aab-0118-4107-a3f8-b1f4a7430ad2
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=731208094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_disconnect.731208094
Directory /workspace/43.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_reset.2514353015
Short name T11
Test name
Test status
Simulation time 13381703243 ps
CPU time 13.79 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206964 kb
Host smart-4fb7b1da-8281-47e6-9112-d9607cec7bc2
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2514353015 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_reset.2514353015
Directory /workspace/43.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/43.usbdev_aon_wake_resume.3009897568
Short name T920
Test name
Test status
Simulation time 23413902193 ps
CPU time 22.83 seconds
Started Jul 22 06:02:48 PM PDT 24
Finished Jul 22 06:03:12 PM PDT 24
Peak memory 206956 kb
Host smart-5ffcff32-84cc-480e-85db-834736073ce6
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3009897568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_aon_wake_resume.3009897568
Directory /workspace/43.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/43.usbdev_av_buffer.2808359774
Short name T1615
Test name
Test status
Simulation time 177955432 ps
CPU time 0.87 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:02:56 PM PDT 24
Peak memory 206712 kb
Host smart-ffa9e633-6f8d-4106-9646-e9b0c112a50a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28083
59774 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_av_buffer.2808359774
Directory /workspace/43.usbdev_av_buffer/latest

Test location /workspace/coverage/default/43.usbdev_bitstuff_err.1149085977
Short name T1631
Test name
Test status
Simulation time 209617107 ps
CPU time 0.92 seconds
Started Jul 22 06:04:02 PM PDT 24
Finished Jul 22 06:04:04 PM PDT 24
Peak memory 206752 kb
Host smart-f6bcb197-476c-4b11-b71d-b64da3845c67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11490
85977 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_bitstuff_err.1149085977
Directory /workspace/43.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_clear.4294374972
Short name T2214
Test name
Test status
Simulation time 403011763 ps
CPU time 1.44 seconds
Started Jul 22 06:02:46 PM PDT 24
Finished Jul 22 06:02:48 PM PDT 24
Peak memory 206736 kb
Host smart-3587ce69-b3f0-446a-9d82-2fc8001721ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42943
74972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_clear.4294374972
Directory /workspace/43.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/43.usbdev_data_toggle_restore.1218200690
Short name T2357
Test name
Test status
Simulation time 367685344 ps
CPU time 1.04 seconds
Started Jul 22 06:02:58 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206708 kb
Host smart-8ef115be-f62f-4f5f-8ec8-3b3e35b46060
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12182
00690 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_data_toggle_restore.1218200690
Directory /workspace/43.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/43.usbdev_device_address.699582477
Short name T1070
Test name
Test status
Simulation time 11776611272 ps
CPU time 22.46 seconds
Started Jul 22 06:02:54 PM PDT 24
Finished Jul 22 06:03:17 PM PDT 24
Peak memory 206936 kb
Host smart-bf2176d2-9a6f-45e2-aae3-8e350f856df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69958
2477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_device_address.699582477
Directory /workspace/43.usbdev_device_address/latest

Test location /workspace/coverage/default/43.usbdev_disable_endpoint.4231769328
Short name T1535
Test name
Test status
Simulation time 423451943 ps
CPU time 1.33 seconds
Started Jul 22 06:02:55 PM PDT 24
Finished Jul 22 06:02:57 PM PDT 24
Peak memory 206748 kb
Host smart-95fa6fd5-e6d3-4438-aea9-bcbebba89fa3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42317
69328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disable_endpoint.4231769328
Directory /workspace/43.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/43.usbdev_disconnected.3819416481
Short name T1941
Test name
Test status
Simulation time 149135316 ps
CPU time 0.77 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:53 PM PDT 24
Peak memory 206744 kb
Host smart-23cdef4f-3329-4640-8a45-70951d9fcae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38194
16481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_disconnected.3819416481
Directory /workspace/43.usbdev_disconnected/latest

Test location /workspace/coverage/default/43.usbdev_enable.1957233105
Short name T1910
Test name
Test status
Simulation time 61050035 ps
CPU time 0.68 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206740 kb
Host smart-916a2dd6-1b79-400f-b0ff-48f0fc41a034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19572
33105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_enable.1957233105
Directory /workspace/43.usbdev_enable/latest

Test location /workspace/coverage/default/43.usbdev_endpoint_access.957720160
Short name T900
Test name
Test status
Simulation time 1009853132 ps
CPU time 2.19 seconds
Started Jul 22 06:02:51 PM PDT 24
Finished Jul 22 06:02:54 PM PDT 24
Peak memory 206796 kb
Host smart-4fd74be7-9375-479b-900f-8bbaad89b23d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95772
0160 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_endpoint_access.957720160
Directory /workspace/43.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/43.usbdev_fifo_rst.3827853296
Short name T1118
Test name
Test status
Simulation time 248814731 ps
CPU time 1.54 seconds
Started Jul 22 06:02:49 PM PDT 24
Finished Jul 22 06:02:52 PM PDT 24
Peak memory 206880 kb
Host smart-ca3491ca-8fae-45fe-a592-9e62d974f4d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38278
53296 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_fifo_rst.3827853296
Directory /workspace/43.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/43.usbdev_in_iso.2452536328
Short name T2173
Test name
Test status
Simulation time 217910212 ps
CPU time 0.86 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 206744 kb
Host smart-608b3693-eaf7-4571-9859-cb99767d72fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24525
36328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_iso.2452536328
Directory /workspace/43.usbdev_in_iso/latest

Test location /workspace/coverage/default/43.usbdev_in_stall.2311883696
Short name T2414
Test name
Test status
Simulation time 146438570 ps
CPU time 0.89 seconds
Started Jul 22 06:02:57 PM PDT 24
Finished Jul 22 06:02:59 PM PDT 24
Peak memory 206740 kb
Host smart-89a8cd8c-a0b0-4383-9651-75165450e42f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23118
83696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_stall.2311883696
Directory /workspace/43.usbdev_in_stall/latest

Test location /workspace/coverage/default/43.usbdev_in_trans.42064220
Short name T2002
Test name
Test status
Simulation time 227885451 ps
CPU time 1.03 seconds
Started Jul 22 06:02:58 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206748 kb
Host smart-04c61140-f5e7-4bda-a170-071effc483d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42064
220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_in_trans.42064220
Directory /workspace/43.usbdev_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_invalid_sync.1767516891
Short name T1265
Test name
Test status
Simulation time 5459767885 ps
CPU time 50.14 seconds
Started Jul 22 06:02:58 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206876 kb
Host smart-92df07e3-e927-4104-9f00-1336593c6d22
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1767516891 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_invalid_sync.1767516891
Directory /workspace/43.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/43.usbdev_iso_retraction.3299303633
Short name T90
Test name
Test status
Simulation time 10568881828 ps
CPU time 31.48 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:36 PM PDT 24
Peak memory 206884 kb
Host smart-a100bddf-b5d2-4f30-84fe-532229bbef25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32993
03633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_iso_retraction.3299303633
Directory /workspace/43.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/43.usbdev_link_in_err.2333841109
Short name T1692
Test name
Test status
Simulation time 208924600 ps
CPU time 0.84 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206784 kb
Host smart-a1bd258a-eb5b-4f2f-a86e-d439c81b61d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23338
41109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_in_err.2333841109
Directory /workspace/43.usbdev_link_in_err/latest

Test location /workspace/coverage/default/43.usbdev_link_resume.1014482349
Short name T405
Test name
Test status
Simulation time 23363571710 ps
CPU time 20.98 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:29 PM PDT 24
Peak memory 206804 kb
Host smart-0a7c9dd8-f9d4-4b34-9970-243e26569e17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10144
82349 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_resume.1014482349
Directory /workspace/43.usbdev_link_resume/latest

Test location /workspace/coverage/default/43.usbdev_link_suspend.3120125217
Short name T353
Test name
Test status
Simulation time 3314187904 ps
CPU time 3.38 seconds
Started Jul 22 06:03:29 PM PDT 24
Finished Jul 22 06:03:33 PM PDT 24
Peak memory 206816 kb
Host smart-06bfb3f0-5c88-40c4-9528-a54ceb0e2ef3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31201
25217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_link_suspend.3120125217
Directory /workspace/43.usbdev_link_suspend/latest

Test location /workspace/coverage/default/43.usbdev_low_speed_traffic.1211591521
Short name T612
Test name
Test status
Simulation time 7390127872 ps
CPU time 71.37 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:04:14 PM PDT 24
Peak memory 206956 kb
Host smart-574f04b3-c95b-4f1b-9cd1-c60c4958a379
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12115
91521 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_low_speed_traffic.1211591521
Directory /workspace/43.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/43.usbdev_max_inter_pkt_delay.258338720
Short name T1430
Test name
Test status
Simulation time 5430401339 ps
CPU time 52.29 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:59 PM PDT 24
Peak memory 206824 kb
Host smart-edff41d9-a269-465d-9aaa-14a5173ab6cb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=258338720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_inter_pkt_delay.258338720
Directory /workspace/43.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_max_length_in_transaction.1876210002
Short name T1445
Test name
Test status
Simulation time 268224108 ps
CPU time 0.99 seconds
Started Jul 22 06:03:00 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206748 kb
Host smart-56e7ac5c-b3a3-4efb-b911-33c8c40d1f03
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1876210002 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_in_transaction.1876210002
Directory /workspace/43.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_length_out_transaction.4283524336
Short name T2033
Test name
Test status
Simulation time 193258515 ps
CPU time 0.92 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206596 kb
Host smart-e8a18497-b54d-4d71-bba0-6650ad5410ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42835
24336 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_length_out_transaction.4283524336
Directory /workspace/43.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_max_usb_traffic.2541945499
Short name T1373
Test name
Test status
Simulation time 7521993935 ps
CPU time 53.03 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206904 kb
Host smart-76354ac8-77ae-4356-8e28-a59691222f8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25419
45499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_max_usb_traffic.2541945499
Directory /workspace/43.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/43.usbdev_min_inter_pkt_delay.4038472522
Short name T2057
Test name
Test status
Simulation time 4843231854 ps
CPU time 130.88 seconds
Started Jul 22 06:03:08 PM PDT 24
Finished Jul 22 06:05:21 PM PDT 24
Peak memory 206920 kb
Host smart-3faffff2-20ca-4338-898f-97eefe5fb862
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4038472522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_inter_pkt_delay.4038472522
Directory /workspace/43.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/43.usbdev_min_length_in_transaction.567369431
Short name T1533
Test name
Test status
Simulation time 193251587 ps
CPU time 0.82 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206684 kb
Host smart-829a7371-0b8d-4be2-b8e7-89b8b3eea9ad
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=567369431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_in_transaction.567369431
Directory /workspace/43.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_min_length_out_transaction.2923336471
Short name T2115
Test name
Test status
Simulation time 140502834 ps
CPU time 0.77 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206704 kb
Host smart-0afa15d7-8e29-4419-8b63-4a6f0cd395f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29233
36471 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_min_length_out_transaction.2923336471
Directory /workspace/43.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_nak_trans.1610318500
Short name T111
Test name
Test status
Simulation time 234252659 ps
CPU time 0.93 seconds
Started Jul 22 06:02:59 PM PDT 24
Finished Jul 22 06:03:02 PM PDT 24
Peak memory 206756 kb
Host smart-5eac4aaf-7549-4011-a02d-748cd6303288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16103
18500 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_nak_trans.1610318500
Directory /workspace/43.usbdev_nak_trans/latest

Test location /workspace/coverage/default/43.usbdev_out_iso.790617777
Short name T727
Test name
Test status
Simulation time 142724277 ps
CPU time 0.79 seconds
Started Jul 22 06:02:57 PM PDT 24
Finished Jul 22 06:02:58 PM PDT 24
Peak memory 206804 kb
Host smart-12b6a2fa-627e-42b8-8f70-2d592ea62959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79061
7777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_iso.790617777
Directory /workspace/43.usbdev_out_iso/latest

Test location /workspace/coverage/default/43.usbdev_out_stall.2928525896
Short name T1192
Test name
Test status
Simulation time 157165918 ps
CPU time 0.79 seconds
Started Jul 22 06:02:59 PM PDT 24
Finished Jul 22 06:03:01 PM PDT 24
Peak memory 206656 kb
Host smart-1ddc2457-0580-42b2-8642-7befba023340
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29285
25896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_stall.2928525896
Directory /workspace/43.usbdev_out_stall/latest

Test location /workspace/coverage/default/43.usbdev_out_trans_nak.4230634696
Short name T1894
Test name
Test status
Simulation time 175889944 ps
CPU time 0.86 seconds
Started Jul 22 06:03:02 PM PDT 24
Finished Jul 22 06:03:05 PM PDT 24
Peak memory 206672 kb
Host smart-0970334d-1959-4350-a6b1-e3fea4d0cb59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42306
34696 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_out_trans_nak.4230634696
Directory /workspace/43.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/43.usbdev_pending_in_trans.1321839101
Short name T2610
Test name
Test status
Simulation time 152617240 ps
CPU time 0.81 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206740 kb
Host smart-8f40f30f-b32d-49cf-81de-9b488058a0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13218
39101 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pending_in_trans.1321839101
Directory /workspace/43.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_pinflip.2839113159
Short name T2576
Test name
Test status
Simulation time 202969848 ps
CPU time 0.94 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206736 kb
Host smart-faa2e8f9-b1bb-455f-958f-12ea29c00365
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2839113159 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_pinflip.2839113159
Directory /workspace/43.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/43.usbdev_phy_config_usb_ref_disable.426006141
Short name T1376
Test name
Test status
Simulation time 138229928 ps
CPU time 0.8 seconds
Started Jul 22 06:03:02 PM PDT 24
Finished Jul 22 06:03:04 PM PDT 24
Peak memory 206708 kb
Host smart-3a5f8468-1837-4c69-98d9-046fa21f9600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42600
6141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_phy_config_usb_ref_disable.426006141
Directory /workspace/43.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/43.usbdev_pkt_buffer.163622464
Short name T1452
Test name
Test status
Simulation time 13032698997 ps
CPU time 28.36 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:34 PM PDT 24
Peak memory 215128 kb
Host smart-eb97012e-546f-40f1-bf13-e71859fc8939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16362
2464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_buffer.163622464
Directory /workspace/43.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/43.usbdev_pkt_received.4273541131
Short name T1581
Test name
Test status
Simulation time 187236583 ps
CPU time 0.89 seconds
Started Jul 22 06:02:59 PM PDT 24
Finished Jul 22 06:03:01 PM PDT 24
Peak memory 206632 kb
Host smart-a93775fd-cde5-4439-89a9-c77f262408b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42735
41131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_received.4273541131
Directory /workspace/43.usbdev_pkt_received/latest

Test location /workspace/coverage/default/43.usbdev_pkt_sent.3885521629
Short name T447
Test name
Test status
Simulation time 182228308 ps
CPU time 0.88 seconds
Started Jul 22 06:03:05 PM PDT 24
Finished Jul 22 06:03:09 PM PDT 24
Peak memory 206752 kb
Host smart-827ebdf1-2630-4810-9e4b-dba40f976e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38855
21629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_pkt_sent.3885521629
Directory /workspace/43.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/43.usbdev_random_length_in_transaction.2362071693
Short name T2240
Test name
Test status
Simulation time 179004058 ps
CPU time 0.82 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206748 kb
Host smart-dca78f2c-2385-4e8a-845c-5eacfdb35cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23620
71693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_in_transaction.2362071693
Directory /workspace/43.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/43.usbdev_random_length_out_transaction.2689784986
Short name T373
Test name
Test status
Simulation time 181917971 ps
CPU time 0.83 seconds
Started Jul 22 06:03:02 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206744 kb
Host smart-49668f5c-1c2e-4913-8fad-90b7aab69aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26897
84986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_random_length_out_transaction.2689784986
Directory /workspace/43.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/43.usbdev_rx_crc_err.662637012
Short name T2275
Test name
Test status
Simulation time 167770667 ps
CPU time 0.78 seconds
Started Jul 22 06:03:02 PM PDT 24
Finished Jul 22 06:03:05 PM PDT 24
Peak memory 206788 kb
Host smart-8bf89358-894f-4ca5-b22b-059330b34129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66263
7012 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_rx_crc_err.662637012
Directory /workspace/43.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/43.usbdev_setup_stage.3136716352
Short name T2536
Test name
Test status
Simulation time 155754211 ps
CPU time 0.78 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206688 kb
Host smart-99bf8d1c-a330-438d-a998-9fbca1f4371f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31367
16352 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_stage.3136716352
Directory /workspace/43.usbdev_setup_stage/latest

Test location /workspace/coverage/default/43.usbdev_setup_trans_ignored.2355705106
Short name T2326
Test name
Test status
Simulation time 145585168 ps
CPU time 0.86 seconds
Started Jul 22 06:02:58 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206744 kb
Host smart-9e9d8a60-3627-461e-872f-676beaa090f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23557
05106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_setup_trans_ignored.2355705106
Directory /workspace/43.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/43.usbdev_smoke.19852991
Short name T1097
Test name
Test status
Simulation time 244020646 ps
CPU time 0.92 seconds
Started Jul 22 06:05:12 PM PDT 24
Finished Jul 22 06:05:14 PM PDT 24
Peak memory 206676 kb
Host smart-208b9031-096f-464e-ac8e-765fb4bc0a09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19852
991 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_smoke.19852991
Directory /workspace/43.usbdev_smoke/latest

Test location /workspace/coverage/default/43.usbdev_spurious_pids_ignored.964291484
Short name T472
Test name
Test status
Simulation time 5482827431 ps
CPU time 40.48 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:48 PM PDT 24
Peak memory 206900 kb
Host smart-373a73b8-6ddb-47b5-b9bc-9cc4bb1ff926
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=964291484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_spurious_pids_ignored.964291484
Directory /workspace/43.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/43.usbdev_stall_priority_over_nak.3767933376
Short name T2452
Test name
Test status
Simulation time 149323868 ps
CPU time 0.74 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206748 kb
Host smart-6ccdbdaa-188d-41ff-a84d-936acd6e7dcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37679
33376 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_priority_over_nak.3767933376
Directory /workspace/43.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/43.usbdev_stall_trans.760779972
Short name T2540
Test name
Test status
Simulation time 197866560 ps
CPU time 0.81 seconds
Started Jul 22 06:03:13 PM PDT 24
Finished Jul 22 06:03:14 PM PDT 24
Peak memory 206688 kb
Host smart-fa49b11f-52de-4e36-809b-37965adb076c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76077
9972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stall_trans.760779972
Directory /workspace/43.usbdev_stall_trans/latest

Test location /workspace/coverage/default/43.usbdev_stream_len_max.25623155
Short name T1732
Test name
Test status
Simulation time 564879067 ps
CPU time 1.55 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:04 PM PDT 24
Peak memory 206712 kb
Host smart-82980ea0-02da-41b4-bca4-2a8308470ab2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25623
155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_stream_len_max.25623155
Directory /workspace/43.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/43.usbdev_streaming_out.3783190860
Short name T2163
Test name
Test status
Simulation time 3939199495 ps
CPU time 36.99 seconds
Started Jul 22 06:03:08 PM PDT 24
Finished Jul 22 06:03:47 PM PDT 24
Peak memory 206956 kb
Host smart-4af8fb6c-9587-4095-853c-57c0406205f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37831
90860 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.usbdev_streaming_out.3783190860
Directory /workspace/43.usbdev_streaming_out/latest

Test location /workspace/coverage/default/44.usbdev_alert_test.3835003638
Short name T387
Test name
Test status
Simulation time 41122778 ps
CPU time 0.68 seconds
Started Jul 22 06:03:22 PM PDT 24
Finished Jul 22 06:03:24 PM PDT 24
Peak memory 206736 kb
Host smart-c03551b2-064b-4651-bd0d-6aa91609b7cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3835003638 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_alert_test.3835003638
Directory /workspace/44.usbdev_alert_test/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_disconnect.1399204224
Short name T1364
Test name
Test status
Simulation time 3856725873 ps
CPU time 4.43 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:12 PM PDT 24
Peak memory 206816 kb
Host smart-6d96dc56-ab14-40dc-8c8b-98df91575439
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1399204224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_disconnect.1399204224
Directory /workspace/44.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_reset.2410928540
Short name T698
Test name
Test status
Simulation time 13417535126 ps
CPU time 12.39 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:19 PM PDT 24
Peak memory 206844 kb
Host smart-c6eb716a-cf11-496b-8978-64459a25d4f0
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2410928540 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_reset.2410928540
Directory /workspace/44.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/44.usbdev_aon_wake_resume.1201085940
Short name T1138
Test name
Test status
Simulation time 23352866231 ps
CPU time 25.01 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:34 PM PDT 24
Peak memory 206800 kb
Host smart-502caa4d-0ae7-40ca-b846-52a3c7f3fa46
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1201085940 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_aon_wake_resume.1201085940
Directory /workspace/44.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/44.usbdev_av_buffer.900332531
Short name T506
Test name
Test status
Simulation time 165274813 ps
CPU time 0.8 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206752 kb
Host smart-dd00a6ee-2829-4408-8243-0f43a0b47924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90033
2531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_av_buffer.900332531
Directory /workspace/44.usbdev_av_buffer/latest

Test location /workspace/coverage/default/44.usbdev_bitstuff_err.3808455153
Short name T2742
Test name
Test status
Simulation time 177169062 ps
CPU time 0.8 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206772 kb
Host smart-b691f6ae-f6db-48b3-8ff3-d4aba1bf987b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38084
55153 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_bitstuff_err.3808455153
Directory /workspace/44.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_clear.2374242172
Short name T1336
Test name
Test status
Simulation time 403691420 ps
CPU time 1.29 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206700 kb
Host smart-a17db026-9d83-40b3-88e2-1d5ab757d5b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23742
42172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_clear.2374242172
Directory /workspace/44.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/44.usbdev_data_toggle_restore.889634861
Short name T2677
Test name
Test status
Simulation time 1341368028 ps
CPU time 3.08 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:13 PM PDT 24
Peak memory 206840 kb
Host smart-3b250857-ec10-4ba3-b9ea-3cc00ed34f22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88963
4861 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_data_toggle_restore.889634861
Directory /workspace/44.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/44.usbdev_device_address.3180650151
Short name T2580
Test name
Test status
Simulation time 21241698938 ps
CPU time 42.53 seconds
Started Jul 22 06:03:02 PM PDT 24
Finished Jul 22 06:03:47 PM PDT 24
Peak memory 206960 kb
Host smart-57410569-e9ce-4a32-b728-addc8a4b9cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31806
50151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_device_address.3180650151
Directory /workspace/44.usbdev_device_address/latest

Test location /workspace/coverage/default/44.usbdev_disable_endpoint.3076600388
Short name T1528
Test name
Test status
Simulation time 451491076 ps
CPU time 1.38 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:11 PM PDT 24
Peak memory 206756 kb
Host smart-c9630d3a-9d3b-477d-ba6a-034bfd1bfea5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30766
00388 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disable_endpoint.3076600388
Directory /workspace/44.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/44.usbdev_disconnected.1757648823
Short name T208
Test name
Test status
Simulation time 162047660 ps
CPU time 0.77 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206708 kb
Host smart-46b67892-249d-418d-bd27-3d61beda9cd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17576
48823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_disconnected.1757648823
Directory /workspace/44.usbdev_disconnected/latest

Test location /workspace/coverage/default/44.usbdev_enable.2544851844
Short name T363
Test name
Test status
Simulation time 82924271 ps
CPU time 0.72 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206692 kb
Host smart-37999c13-7bc0-4c0d-9ea0-d5e5d03335e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25448
51844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_enable.2544851844
Directory /workspace/44.usbdev_enable/latest

Test location /workspace/coverage/default/44.usbdev_endpoint_access.2883218945
Short name T2076
Test name
Test status
Simulation time 878274082 ps
CPU time 2.09 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:12 PM PDT 24
Peak memory 206880 kb
Host smart-d73f3f43-4d07-4742-a1fa-a34faacd29a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28832
18945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_endpoint_access.2883218945
Directory /workspace/44.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/44.usbdev_fifo_rst.4080955301
Short name T1437
Test name
Test status
Simulation time 213676815 ps
CPU time 1.3 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:04 PM PDT 24
Peak memory 206840 kb
Host smart-a435fdaa-ad22-44e0-a578-72ec2d8a070f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40809
55301 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_fifo_rst.4080955301
Directory /workspace/44.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/44.usbdev_in_iso.2037821236
Short name T978
Test name
Test status
Simulation time 208964372 ps
CPU time 0.9 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:08 PM PDT 24
Peak memory 206784 kb
Host smart-894beb1b-6a81-443d-a943-897674653737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20378
21236 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_iso.2037821236
Directory /workspace/44.usbdev_in_iso/latest

Test location /workspace/coverage/default/44.usbdev_in_stall.742004443
Short name T324
Test name
Test status
Simulation time 152726144 ps
CPU time 0.82 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206748 kb
Host smart-d61939f1-dc93-4c27-8d1a-89ca6be08ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74200
4443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_stall.742004443
Directory /workspace/44.usbdev_in_stall/latest

Test location /workspace/coverage/default/44.usbdev_in_trans.930796131
Short name T775
Test name
Test status
Simulation time 229248673 ps
CPU time 0.94 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206728 kb
Host smart-a61c36c5-0dc9-4b90-9612-ce3985eb5345
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93079
6131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_in_trans.930796131
Directory /workspace/44.usbdev_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_iso_retraction.1177781939
Short name T806
Test name
Test status
Simulation time 3682696699 ps
CPU time 31.34 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:33 PM PDT 24
Peak memory 206888 kb
Host smart-ffd0beb1-f30f-4698-af03-39b92180e5a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11777
81939 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_iso_retraction.1177781939
Directory /workspace/44.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/44.usbdev_link_in_err.2264437542
Short name T2441
Test name
Test status
Simulation time 184716497 ps
CPU time 0.84 seconds
Started Jul 22 06:03:02 PM PDT 24
Finished Jul 22 06:03:05 PM PDT 24
Peak memory 206752 kb
Host smart-4182b502-41b1-40a6-9aa1-e4ef4cdf3975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22644
37542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_in_err.2264437542
Directory /workspace/44.usbdev_link_in_err/latest

Test location /workspace/coverage/default/44.usbdev_link_resume.638740084
Short name T1314
Test name
Test status
Simulation time 23286544407 ps
CPU time 26.25 seconds
Started Jul 22 06:03:05 PM PDT 24
Finished Jul 22 06:03:35 PM PDT 24
Peak memory 206804 kb
Host smart-15ccd9ed-2030-4b83-a192-cfa56d240732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63874
0084 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_resume.638740084
Directory /workspace/44.usbdev_link_resume/latest

Test location /workspace/coverage/default/44.usbdev_link_suspend.4167293533
Short name T2073
Test name
Test status
Simulation time 3347932247 ps
CPU time 4.33 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206808 kb
Host smart-f93c489a-352b-4df0-b8ec-fcac3ffa6b0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41672
93533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_link_suspend.4167293533
Directory /workspace/44.usbdev_link_suspend/latest

Test location /workspace/coverage/default/44.usbdev_low_speed_traffic.1636089645
Short name T1626
Test name
Test status
Simulation time 9581564044 ps
CPU time 84 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:04:29 PM PDT 24
Peak memory 206884 kb
Host smart-a0721167-7df2-4492-8963-b4339a296d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16360
89645 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_low_speed_traffic.1636089645
Directory /workspace/44.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/44.usbdev_max_inter_pkt_delay.1548204273
Short name T2398
Test name
Test status
Simulation time 4583025888 ps
CPU time 31.01 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:33 PM PDT 24
Peak memory 206892 kb
Host smart-f53e6ac4-4d95-4ee2-a7bc-145ea61d423f
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1548204273 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_inter_pkt_delay.1548204273
Directory /workspace/44.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_max_length_in_transaction.1366103855
Short name T2622
Test name
Test status
Simulation time 271261764 ps
CPU time 0.95 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206700 kb
Host smart-d09ca0fa-d9fc-4c22-9453-5457a9fdc61a
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1366103855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_in_transaction.1366103855
Directory /workspace/44.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_length_out_transaction.847635955
Short name T1907
Test name
Test status
Simulation time 184453397 ps
CPU time 0.84 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206792 kb
Host smart-2879a7dd-ec1b-4f96-8af4-a669015b1d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84763
5955 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_length_out_transaction.847635955
Directory /workspace/44.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_max_usb_traffic.3065102767
Short name T1988
Test name
Test status
Simulation time 6698046046 ps
CPU time 173.13 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:05:59 PM PDT 24
Peak memory 206856 kb
Host smart-393778f6-620a-417a-8f54-13c800e9201f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30651
02767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_max_usb_traffic.3065102767
Directory /workspace/44.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/44.usbdev_min_inter_pkt_delay.2757598078
Short name T2481
Test name
Test status
Simulation time 6369635730 ps
CPU time 43.91 seconds
Started Jul 22 06:03:02 PM PDT 24
Finished Jul 22 06:03:48 PM PDT 24
Peak memory 206948 kb
Host smart-d3c5bf02-9a57-4ee3-a341-39560fa4c59c
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2757598078 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_inter_pkt_delay.2757598078
Directory /workspace/44.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/44.usbdev_min_length_in_transaction.1396261790
Short name T546
Test name
Test status
Simulation time 211045353 ps
CPU time 0.85 seconds
Started Jul 22 06:02:59 PM PDT 24
Finished Jul 22 06:03:01 PM PDT 24
Peak memory 206740 kb
Host smart-b818d436-28e9-4f96-9818-c294b4a509dd
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1396261790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_in_transaction.1396261790
Directory /workspace/44.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_min_length_out_transaction.597772587
Short name T340
Test name
Test status
Simulation time 155778593 ps
CPU time 0.89 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206684 kb
Host smart-2f2aac1d-766a-4efe-9fc8-28e2502405cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59777
2587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_min_length_out_transaction.597772587
Directory /workspace/44.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_nak_trans.55491011
Short name T123
Test name
Test status
Simulation time 184177981 ps
CPU time 0.86 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206788 kb
Host smart-d0ca0af5-8ce4-433e-a843-eb3ea8e737df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55491
011 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_nak_trans.55491011
Directory /workspace/44.usbdev_nak_trans/latest

Test location /workspace/coverage/default/44.usbdev_out_iso.3437937959
Short name T1114
Test name
Test status
Simulation time 157246817 ps
CPU time 0.78 seconds
Started Jul 22 06:03:08 PM PDT 24
Finished Jul 22 06:03:11 PM PDT 24
Peak memory 206744 kb
Host smart-cb827b36-6cbb-466f-a550-ff07aaf59190
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
37959 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_iso.3437937959
Directory /workspace/44.usbdev_out_iso/latest

Test location /workspace/coverage/default/44.usbdev_out_stall.3325279542
Short name T1470
Test name
Test status
Simulation time 174794517 ps
CPU time 0.8 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206752 kb
Host smart-39f4dbbd-3a2b-4230-b4f1-201dae90d057
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33252
79542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_stall.3325279542
Directory /workspace/44.usbdev_out_stall/latest

Test location /workspace/coverage/default/44.usbdev_out_trans_nak.3968863040
Short name T2738
Test name
Test status
Simulation time 220922046 ps
CPU time 0.91 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:09 PM PDT 24
Peak memory 206748 kb
Host smart-3abe1ff5-7492-46eb-aa1c-39b898b348d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39688
63040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_out_trans_nak.3968863040
Directory /workspace/44.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/44.usbdev_pending_in_trans.3384183867
Short name T2498
Test name
Test status
Simulation time 148725490 ps
CPU time 0.78 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206752 kb
Host smart-681786bd-4dec-45e4-8d6e-f9eaab0449a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33841
83867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pending_in_trans.3384183867
Directory /workspace/44.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_pinflip.545099648
Short name T1799
Test name
Test status
Simulation time 219495632 ps
CPU time 0.96 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:08 PM PDT 24
Peak memory 206756 kb
Host smart-e23e22ff-c7c7-437b-b4bb-6f68a0f42a99
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=545099648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_pinflip.545099648
Directory /workspace/44.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/44.usbdev_phy_config_usb_ref_disable.1243861898
Short name T2299
Test name
Test status
Simulation time 139302383 ps
CPU time 0.79 seconds
Started Jul 22 06:03:01 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206732 kb
Host smart-f5482a08-02c1-4071-a833-4471999f8972
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12438
61898 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_config_usb_ref_disable.1243861898
Directory /workspace/44.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/44.usbdev_phy_pins_sense.3932656412
Short name T24
Test name
Test status
Simulation time 39914437 ps
CPU time 0.66 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206748 kb
Host smart-f548ceee-f6c6-436a-b615-3f16a3e1c2e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39326
56412 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_phy_pins_sense.3932656412
Directory /workspace/44.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/44.usbdev_pkt_buffer.2425996715
Short name T617
Test name
Test status
Simulation time 15926617406 ps
CPU time 37.78 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:47 PM PDT 24
Peak memory 215120 kb
Host smart-99384613-f912-43de-835c-58fdd48366de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24259
96715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_buffer.2425996715
Directory /workspace/44.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/44.usbdev_pkt_received.3030187720
Short name T1951
Test name
Test status
Simulation time 166348730 ps
CPU time 0.85 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206756 kb
Host smart-a7c7c41d-e73b-4941-acf8-aaa86834ce37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30301
87720 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_received.3030187720
Directory /workspace/44.usbdev_pkt_received/latest

Test location /workspace/coverage/default/44.usbdev_pkt_sent.1308871581
Short name T1062
Test name
Test status
Simulation time 188785166 ps
CPU time 0.87 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206752 kb
Host smart-4993580d-d183-48dc-8dec-ebcf4a51f870
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13088
71581 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_pkt_sent.1308871581
Directory /workspace/44.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/44.usbdev_random_length_in_transaction.920585260
Short name T1064
Test name
Test status
Simulation time 159705602 ps
CPU time 0.86 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206752 kb
Host smart-aff35f26-e607-4902-9fbd-b8aa9b6d6968
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92058
5260 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_in_transaction.920585260
Directory /workspace/44.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/44.usbdev_random_length_out_transaction.1780040863
Short name T590
Test name
Test status
Simulation time 188895247 ps
CPU time 0.88 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:06 PM PDT 24
Peak memory 206704 kb
Host smart-5f819c39-0644-4b3d-aac4-f22f134a9ff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17800
40863 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_random_length_out_transaction.1780040863
Directory /workspace/44.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/44.usbdev_rx_crc_err.2013485915
Short name T2101
Test name
Test status
Simulation time 228145587 ps
CPU time 0.89 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:08 PM PDT 24
Peak memory 206732 kb
Host smart-2e5b28b3-e2b2-42a2-9f32-ca3a10410d7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20134
85915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_rx_crc_err.2013485915
Directory /workspace/44.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/44.usbdev_setup_stage.1073731288
Short name T1135
Test name
Test status
Simulation time 176077858 ps
CPU time 0.86 seconds
Started Jul 22 06:03:06 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206732 kb
Host smart-70b0d8ae-3491-45f3-99f7-bfead675710d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10737
31288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_stage.1073731288
Directory /workspace/44.usbdev_setup_stage/latest

Test location /workspace/coverage/default/44.usbdev_setup_trans_ignored.3154444658
Short name T1115
Test name
Test status
Simulation time 148394992 ps
CPU time 0.79 seconds
Started Jul 22 06:03:07 PM PDT 24
Finished Jul 22 06:03:10 PM PDT 24
Peak memory 206756 kb
Host smart-8767c7f4-076d-4021-889d-608378cd04ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31544
44658 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_setup_trans_ignored.3154444658
Directory /workspace/44.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/44.usbdev_smoke.4273982741
Short name T561
Test name
Test status
Simulation time 239607222 ps
CPU time 0.91 seconds
Started Jul 22 06:03:00 PM PDT 24
Finished Jul 22 06:03:02 PM PDT 24
Peak memory 206492 kb
Host smart-e06454b2-3af7-4769-b94c-6e7acfc378ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42739
82741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_smoke.4273982741
Directory /workspace/44.usbdev_smoke/latest

Test location /workspace/coverage/default/44.usbdev_spurious_pids_ignored.3580053114
Short name T1199
Test name
Test status
Simulation time 3393202935 ps
CPU time 23.73 seconds
Started Jul 22 06:03:04 PM PDT 24
Finished Jul 22 06:03:31 PM PDT 24
Peak memory 206956 kb
Host smart-2ccaf28d-aa7f-496c-bbe0-965451b3f428
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3580053114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_spurious_pids_ignored.3580053114
Directory /workspace/44.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/44.usbdev_stall_priority_over_nak.845521968
Short name T980
Test name
Test status
Simulation time 188930035 ps
CPU time 0.88 seconds
Started Jul 22 06:03:03 PM PDT 24
Finished Jul 22 06:03:07 PM PDT 24
Peak memory 206756 kb
Host smart-5b7e9c19-7df7-4697-8eab-bcbbf080438d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84552
1968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_priority_over_nak.845521968
Directory /workspace/44.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/44.usbdev_stall_trans.2097073008
Short name T2418
Test name
Test status
Simulation time 220375696 ps
CPU time 0.9 seconds
Started Jul 22 06:02:58 PM PDT 24
Finished Jul 22 06:03:00 PM PDT 24
Peak memory 206860 kb
Host smart-4d20b799-55f2-4ad1-8af9-6364ff2ccde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20970
73008 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stall_trans.2097073008
Directory /workspace/44.usbdev_stall_trans/latest

Test location /workspace/coverage/default/44.usbdev_stream_len_max.2287716871
Short name T2401
Test name
Test status
Simulation time 1146121383 ps
CPU time 2.64 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206884 kb
Host smart-91897f84-3b2a-49ed-abfd-5126a0026b8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22877
16871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_stream_len_max.2287716871
Directory /workspace/44.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/44.usbdev_streaming_out.1769354317
Short name T1682
Test name
Test status
Simulation time 7967817921 ps
CPU time 213.61 seconds
Started Jul 22 06:02:59 PM PDT 24
Finished Jul 22 06:06:34 PM PDT 24
Peak memory 206932 kb
Host smart-3cfdd212-4a83-4356-bac2-0ce3a7dbf742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17693
54317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.usbdev_streaming_out.1769354317
Directory /workspace/44.usbdev_streaming_out/latest

Test location /workspace/coverage/default/45.usbdev_alert_test.3470408765
Short name T2142
Test name
Test status
Simulation time 39452751 ps
CPU time 0.69 seconds
Started Jul 22 06:03:21 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206696 kb
Host smart-467ea54e-33e9-4a2c-934c-143ef2786315
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3470408765 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_alert_test.3470408765
Directory /workspace/45.usbdev_alert_test/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_disconnect.3360876979
Short name T2278
Test name
Test status
Simulation time 3717102105 ps
CPU time 4.63 seconds
Started Jul 22 06:03:20 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206952 kb
Host smart-af9588b7-dc4f-4392-8773-afb4b474ab02
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3360876979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_disconnect.3360876979
Directory /workspace/45.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/45.usbdev_aon_wake_resume.3782707130
Short name T9
Test name
Test status
Simulation time 23397616901 ps
CPU time 24.79 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206816 kb
Host smart-3fae40e2-8c16-46d0-b491-bd9393999894
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3782707130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_aon_wake_resume.3782707130
Directory /workspace/45.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/45.usbdev_av_buffer.3631137255
Short name T2177
Test name
Test status
Simulation time 175781211 ps
CPU time 0.79 seconds
Started Jul 22 06:04:26 PM PDT 24
Finished Jul 22 06:04:27 PM PDT 24
Peak memory 206720 kb
Host smart-c7228599-bacb-4794-929b-76a559bb70a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36311
37255 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_av_buffer.3631137255
Directory /workspace/45.usbdev_av_buffer/latest

Test location /workspace/coverage/default/45.usbdev_bitstuff_err.1864106172
Short name T562
Test name
Test status
Simulation time 145691433 ps
CPU time 0.76 seconds
Started Jul 22 06:03:13 PM PDT 24
Finished Jul 22 06:03:14 PM PDT 24
Peak memory 206756 kb
Host smart-57f03c9c-8a0d-4fd9-a682-c1b7782f30bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18641
06172 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_bitstuff_err.1864106172
Directory /workspace/45.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_clear.40745883
Short name T2096
Test name
Test status
Simulation time 299373247 ps
CPU time 1.15 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:25 PM PDT 24
Peak memory 206448 kb
Host smart-d6ea7993-2c96-48c6-a51a-a96cfdc996a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40745
883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_clear.40745883
Directory /workspace/45.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/45.usbdev_data_toggle_restore.4124938914
Short name T1996
Test name
Test status
Simulation time 1422380069 ps
CPU time 3.16 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:44 PM PDT 24
Peak memory 206840 kb
Host smart-3ddd8ff5-37a1-4183-b405-fa2c2929ef8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41249
38914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_data_toggle_restore.4124938914
Directory /workspace/45.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/45.usbdev_device_address.25989776
Short name T172
Test name
Test status
Simulation time 9833717595 ps
CPU time 19.51 seconds
Started Jul 22 06:03:26 PM PDT 24
Finished Jul 22 06:03:46 PM PDT 24
Peak memory 206948 kb
Host smart-5a241758-f61a-4b5e-a33f-8b8e306e0f9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25989
776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_device_address.25989776
Directory /workspace/45.usbdev_device_address/latest

Test location /workspace/coverage/default/45.usbdev_disable_endpoint.4153720185
Short name T1675
Test name
Test status
Simulation time 457209047 ps
CPU time 1.4 seconds
Started Jul 22 06:03:29 PM PDT 24
Finished Jul 22 06:03:30 PM PDT 24
Peak memory 206752 kb
Host smart-6306885f-5088-47f9-b3e7-0c71203e0705
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41537
20185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disable_endpoint.4153720185
Directory /workspace/45.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/45.usbdev_disconnected.985256439
Short name T2721
Test name
Test status
Simulation time 153240585 ps
CPU time 0.8 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206712 kb
Host smart-6ca3b75e-b58f-467f-bc55-e4ada35af565
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98525
6439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_disconnected.985256439
Directory /workspace/45.usbdev_disconnected/latest

Test location /workspace/coverage/default/45.usbdev_enable.3834327855
Short name T234
Test name
Test status
Simulation time 35770868 ps
CPU time 0.63 seconds
Started Jul 22 06:03:21 PM PDT 24
Finished Jul 22 06:03:23 PM PDT 24
Peak memory 206720 kb
Host smart-ec6554ae-8f39-4ff5-99d0-318b87366e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38343
27855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_enable.3834327855
Directory /workspace/45.usbdev_enable/latest

Test location /workspace/coverage/default/45.usbdev_endpoint_access.3147016279
Short name T2532
Test name
Test status
Simulation time 1126304037 ps
CPU time 2.44 seconds
Started Jul 22 06:03:14 PM PDT 24
Finished Jul 22 06:03:16 PM PDT 24
Peak memory 206936 kb
Host smart-0d74d4c6-308a-4748-9f61-0d968e4dfaf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31470
16279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_endpoint_access.3147016279
Directory /workspace/45.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/45.usbdev_fifo_rst.4081768501
Short name T2040
Test name
Test status
Simulation time 287971464 ps
CPU time 1.99 seconds
Started Jul 22 06:03:36 PM PDT 24
Finished Jul 22 06:03:38 PM PDT 24
Peak memory 206900 kb
Host smart-eeae3c20-c5aa-45d3-bd41-9e2c3dede5d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40817
68501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_fifo_rst.4081768501
Directory /workspace/45.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/45.usbdev_in_iso.2012815759
Short name T583
Test name
Test status
Simulation time 213698538 ps
CPU time 0.91 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206628 kb
Host smart-d7410ffd-9b41-4d0c-86c2-9585949f9e98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20128
15759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_iso.2012815759
Directory /workspace/45.usbdev_in_iso/latest

Test location /workspace/coverage/default/45.usbdev_in_stall.227977464
Short name T377
Test name
Test status
Simulation time 140495297 ps
CPU time 0.81 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206740 kb
Host smart-b3075463-6395-4c08-ac21-36caa4dd39c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22797
7464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_stall.227977464
Directory /workspace/45.usbdev_in_stall/latest

Test location /workspace/coverage/default/45.usbdev_in_trans.1301633615
Short name T1362
Test name
Test status
Simulation time 206357173 ps
CPU time 0.85 seconds
Started Jul 22 06:03:26 PM PDT 24
Finished Jul 22 06:03:27 PM PDT 24
Peak memory 206756 kb
Host smart-d3f7d010-fddf-46f0-a2f7-e7baf0b8ab82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13016
33615 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_in_trans.1301633615
Directory /workspace/45.usbdev_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_invalid_sync.3236338058
Short name T237
Test name
Test status
Simulation time 4589992716 ps
CPU time 119.51 seconds
Started Jul 22 06:05:20 PM PDT 24
Finished Jul 22 06:07:20 PM PDT 24
Peak memory 206880 kb
Host smart-dd921275-d787-44cb-9f65-ff6fe5e5d771
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3236338058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_invalid_sync.3236338058
Directory /workspace/45.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/45.usbdev_link_in_err.2030683385
Short name T1882
Test name
Test status
Simulation time 185338949 ps
CPU time 0.89 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:38 PM PDT 24
Peak memory 206716 kb
Host smart-acb25623-a9f3-45d6-ad76-5b9a0a2be069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20306
83385 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_in_err.2030683385
Directory /workspace/45.usbdev_link_in_err/latest

Test location /workspace/coverage/default/45.usbdev_link_resume.1321374447
Short name T395
Test name
Test status
Simulation time 23309897361 ps
CPU time 27.19 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:51 PM PDT 24
Peak memory 206816 kb
Host smart-80f601e4-bd73-43a4-8980-a2fc5188652f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13213
74447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_resume.1321374447
Directory /workspace/45.usbdev_link_resume/latest

Test location /workspace/coverage/default/45.usbdev_link_suspend.3452951642
Short name T368
Test name
Test status
Simulation time 3345612775 ps
CPU time 3.71 seconds
Started Jul 22 06:04:11 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 206800 kb
Host smart-31f83c83-5b6a-4d9b-a3a4-068aa49795fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34529
51642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_link_suspend.3452951642
Directory /workspace/45.usbdev_link_suspend/latest

Test location /workspace/coverage/default/45.usbdev_low_speed_traffic.2462669233
Short name T6
Test name
Test status
Simulation time 8321966278 ps
CPU time 78.22 seconds
Started Jul 22 06:03:33 PM PDT 24
Finished Jul 22 06:04:52 PM PDT 24
Peak memory 206908 kb
Host smart-e6f5b730-cb68-48b2-83c9-2f5c639afa87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24626
69233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_low_speed_traffic.2462669233
Directory /workspace/45.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/45.usbdev_max_inter_pkt_delay.3346681669
Short name T2631
Test name
Test status
Simulation time 5398662161 ps
CPU time 36.54 seconds
Started Jul 22 06:03:18 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 206904 kb
Host smart-8189b70e-56cc-44a1-a9d5-f7e128fe06e2
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=3346681669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_inter_pkt_delay.3346681669
Directory /workspace/45.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_max_length_in_transaction.3409982808
Short name T2114
Test name
Test status
Simulation time 251683360 ps
CPU time 0.97 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206628 kb
Host smart-3ea5000a-a06a-4ed7-b474-d6ef5e35728c
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3409982808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_in_transaction.3409982808
Directory /workspace/45.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_max_length_out_transaction.1901610270
Short name T2067
Test name
Test status
Simulation time 220180155 ps
CPU time 0.89 seconds
Started Jul 22 06:03:20 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206720 kb
Host smart-5ccc1e49-89bb-4729-b0ba-c1cfc307ba02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19016
10270 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_max_length_out_transaction.1901610270
Directory /workspace/45.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_inter_pkt_delay.232907596
Short name T994
Test name
Test status
Simulation time 4865801001 ps
CPU time 135.16 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:05:40 PM PDT 24
Peak memory 206892 kb
Host smart-ef746d6f-497e-4327-8aac-1353f4cd4e17
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=232907596 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_inter_pkt_delay.232907596
Directory /workspace/45.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/45.usbdev_min_length_in_transaction.2991407790
Short name T1790
Test name
Test status
Simulation time 146593630 ps
CPU time 0.81 seconds
Started Jul 22 06:04:03 PM PDT 24
Finished Jul 22 06:04:05 PM PDT 24
Peak memory 206748 kb
Host smart-a3100f0c-7bbf-4c9e-96f6-8c809a4a9f3e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2991407790 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_in_transaction.2991407790
Directory /workspace/45.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_min_length_out_transaction.3291863064
Short name T448
Test name
Test status
Simulation time 152514530 ps
CPU time 0.81 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:25 PM PDT 24
Peak memory 206332 kb
Host smart-9a86ec8f-da1b-464c-b4cf-159642ab0c46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32918
63064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_min_length_out_transaction.3291863064
Directory /workspace/45.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_nak_trans.2931136597
Short name T131
Test name
Test status
Simulation time 157593227 ps
CPU time 0.8 seconds
Started Jul 22 06:03:21 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206668 kb
Host smart-919d1c0c-1f1e-4919-a3c5-22d33b3e4620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29311
36597 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_nak_trans.2931136597
Directory /workspace/45.usbdev_nak_trans/latest

Test location /workspace/coverage/default/45.usbdev_out_stall.2833686286
Short name T1999
Test name
Test status
Simulation time 240776467 ps
CPU time 0.89 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:25 PM PDT 24
Peak memory 206744 kb
Host smart-7030dd75-01e2-4a68-9f5f-1095bba961dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28336
86286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_stall.2833686286
Directory /workspace/45.usbdev_out_stall/latest

Test location /workspace/coverage/default/45.usbdev_out_trans_nak.4037675106
Short name T1793
Test name
Test status
Simulation time 156139800 ps
CPU time 0.79 seconds
Started Jul 22 06:03:19 PM PDT 24
Finished Jul 22 06:03:21 PM PDT 24
Peak memory 206684 kb
Host smart-e96f1009-eb04-46af-b07e-e25c7b4fe76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40376
75106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_out_trans_nak.4037675106
Directory /workspace/45.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/45.usbdev_pending_in_trans.2172882704
Short name T880
Test name
Test status
Simulation time 193268203 ps
CPU time 0.86 seconds
Started Jul 22 06:03:25 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206744 kb
Host smart-cec5fa15-e652-4f6a-af76-ac171babada6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21728
82704 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pending_in_trans.2172882704
Directory /workspace/45.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_pinflip.280156697
Short name T678
Test name
Test status
Simulation time 200446008 ps
CPU time 0.86 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 206700 kb
Host smart-5fbfefd6-8639-4994-a478-04f3735473e1
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=280156697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_pinflip.280156697
Directory /workspace/45.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/45.usbdev_phy_config_usb_ref_disable.2767355404
Short name T714
Test name
Test status
Simulation time 143338744 ps
CPU time 0.84 seconds
Started Jul 22 06:04:19 PM PDT 24
Finished Jul 22 06:04:20 PM PDT 24
Peak memory 206768 kb
Host smart-f66a5470-fac8-4c2e-90c4-5835fe6681ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27673
55404 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_config_usb_ref_disable.2767355404
Directory /workspace/45.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/45.usbdev_phy_pins_sense.3630496735
Short name T2673
Test name
Test status
Simulation time 57924413 ps
CPU time 0.68 seconds
Started Jul 22 06:03:22 PM PDT 24
Finished Jul 22 06:03:23 PM PDT 24
Peak memory 206784 kb
Host smart-14974901-b268-416d-961b-30203c02f70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36304
96735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_phy_pins_sense.3630496735
Directory /workspace/45.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/45.usbdev_pkt_buffer.3728589348
Short name T1830
Test name
Test status
Simulation time 13784476796 ps
CPU time 29.48 seconds
Started Jul 22 06:03:12 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206924 kb
Host smart-4d9c7ad3-0350-44ce-83a1-2b01bc72ebfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37285
89348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_buffer.3728589348
Directory /workspace/45.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/45.usbdev_pkt_received.3760274781
Short name T1523
Test name
Test status
Simulation time 154961466 ps
CPU time 0.76 seconds
Started Jul 22 06:05:19 PM PDT 24
Finished Jul 22 06:05:21 PM PDT 24
Peak memory 206752 kb
Host smart-a28e46a9-6e55-4a0e-aeae-bfb9100b2f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37602
74781 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_received.3760274781
Directory /workspace/45.usbdev_pkt_received/latest

Test location /workspace/coverage/default/45.usbdev_pkt_sent.1083006439
Short name T1026
Test name
Test status
Simulation time 213793617 ps
CPU time 0.88 seconds
Started Jul 22 06:03:21 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206660 kb
Host smart-5be39314-c203-4205-a683-a2536f55da45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10830
06439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_pkt_sent.1083006439
Directory /workspace/45.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/45.usbdev_random_length_in_transaction.1598985736
Short name T2000
Test name
Test status
Simulation time 214047791 ps
CPU time 0.92 seconds
Started Jul 22 06:03:20 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206712 kb
Host smart-87bf5ce3-f3d2-4e81-983b-17fffb12a5a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15989
85736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_in_transaction.1598985736
Directory /workspace/45.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/45.usbdev_random_length_out_transaction.1832076455
Short name T717
Test name
Test status
Simulation time 168475396 ps
CPU time 0.88 seconds
Started Jul 22 06:03:20 PM PDT 24
Finished Jul 22 06:03:21 PM PDT 24
Peak memory 206684 kb
Host smart-dfdf7530-9fa7-42e8-b585-83e8c7c449da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18320
76455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_random_length_out_transaction.1832076455
Directory /workspace/45.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/45.usbdev_rx_crc_err.959213723
Short name T671
Test name
Test status
Simulation time 168098646 ps
CPU time 0.79 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:39 PM PDT 24
Peak memory 206732 kb
Host smart-0bfcee2b-15fc-475d-8e8b-e27fd6f6672f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95921
3723 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_rx_crc_err.959213723
Directory /workspace/45.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/45.usbdev_setup_stage.1060939776
Short name T1756
Test name
Test status
Simulation time 153377469 ps
CPU time 0.82 seconds
Started Jul 22 06:03:35 PM PDT 24
Finished Jul 22 06:03:36 PM PDT 24
Peak memory 206796 kb
Host smart-34ec3241-258b-4caa-b8b3-582c292501d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10609
39776 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_stage.1060939776
Directory /workspace/45.usbdev_setup_stage/latest

Test location /workspace/coverage/default/45.usbdev_setup_trans_ignored.662590982
Short name T1983
Test name
Test status
Simulation time 165213856 ps
CPU time 0.87 seconds
Started Jul 22 06:05:19 PM PDT 24
Finished Jul 22 06:05:21 PM PDT 24
Peak memory 206752 kb
Host smart-ef990100-68b7-4f99-88d5-fc0830fd8350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66259
0982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_setup_trans_ignored.662590982
Directory /workspace/45.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/45.usbdev_smoke.1719030428
Short name T1796
Test name
Test status
Simulation time 259707996 ps
CPU time 1 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:24 PM PDT 24
Peak memory 206744 kb
Host smart-c3343abf-dbd7-479b-9f46-f1a96962687f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17190
30428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_smoke.1719030428
Directory /workspace/45.usbdev_smoke/latest

Test location /workspace/coverage/default/45.usbdev_spurious_pids_ignored.2143842257
Short name T2403
Test name
Test status
Simulation time 4166777904 ps
CPU time 38.93 seconds
Started Jul 22 06:03:21 PM PDT 24
Finished Jul 22 06:04:00 PM PDT 24
Peak memory 206868 kb
Host smart-14ce8e27-a737-4473-821d-ca75b947243d
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2143842257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_spurious_pids_ignored.2143842257
Directory /workspace/45.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/45.usbdev_stall_priority_over_nak.3467091028
Short name T1390
Test name
Test status
Simulation time 188216398 ps
CPU time 0.95 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206732 kb
Host smart-7daad8b9-61c9-4952-8183-557eda07c869
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34670
91028 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_priority_over_nak.3467091028
Directory /workspace/45.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/45.usbdev_stall_trans.170106821
Short name T1868
Test name
Test status
Simulation time 209639650 ps
CPU time 0.84 seconds
Started Jul 22 06:03:16 PM PDT 24
Finished Jul 22 06:03:17 PM PDT 24
Peak memory 206736 kb
Host smart-533756ba-b630-425c-ac72-af0835cf3787
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17010
6821 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stall_trans.170106821
Directory /workspace/45.usbdev_stall_trans/latest

Test location /workspace/coverage/default/45.usbdev_stream_len_max.1583227592
Short name T2205
Test name
Test status
Simulation time 221672133 ps
CPU time 0.9 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206748 kb
Host smart-a462d580-c02e-459a-98dd-ae9c659f4e22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15832
27592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_stream_len_max.1583227592
Directory /workspace/45.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/45.usbdev_streaming_out.2385592713
Short name T2372
Test name
Test status
Simulation time 3950806967 ps
CPU time 111.69 seconds
Started Jul 22 06:03:25 PM PDT 24
Finished Jul 22 06:05:17 PM PDT 24
Peak memory 206896 kb
Host smart-3a855cb9-10f9-4afe-9927-949b7092f27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23855
92713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.usbdev_streaming_out.2385592713
Directory /workspace/45.usbdev_streaming_out/latest

Test location /workspace/coverage/default/46.usbdev_alert_test.385782979
Short name T2634
Test name
Test status
Simulation time 46974226 ps
CPU time 0.7 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206792 kb
Host smart-1af87302-d8d4-4bab-8b6d-54c0b26cd407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=385782979 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_alert_test.385782979
Directory /workspace/46.usbdev_alert_test/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_disconnect.60445274
Short name T2069
Test name
Test status
Simulation time 3669892198 ps
CPU time 4.52 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:30 PM PDT 24
Peak memory 206764 kb
Host smart-d626573c-7aba-48f7-9094-da4cc8e02c08
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=60445274 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_disconnect.60445274
Directory /workspace/46.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_reset.555170174
Short name T633
Test name
Test status
Simulation time 13423917998 ps
CPU time 13.51 seconds
Started Jul 22 06:03:35 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206832 kb
Host smart-9f586f2b-ccf5-40a9-b1ca-8213fff065b4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=555170174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_reset.555170174
Directory /workspace/46.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/46.usbdev_aon_wake_resume.2307767288
Short name T1235
Test name
Test status
Simulation time 23311576028 ps
CPU time 26.66 seconds
Started Jul 22 06:03:22 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206820 kb
Host smart-a42a2a52-a309-4945-83de-aeea5da72b54
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2307767288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_aon_wake_resume.2307767288
Directory /workspace/46.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/46.usbdev_av_buffer.3233763477
Short name T1384
Test name
Test status
Simulation time 159426698 ps
CPU time 0.83 seconds
Started Jul 22 06:03:20 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206740 kb
Host smart-03f57bce-59ce-425d-9711-013da4167e0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32337
63477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_av_buffer.3233763477
Directory /workspace/46.usbdev_av_buffer/latest

Test location /workspace/coverage/default/46.usbdev_bitstuff_err.3079668403
Short name T482
Test name
Test status
Simulation time 192587477 ps
CPU time 0.86 seconds
Started Jul 22 06:03:19 PM PDT 24
Finished Jul 22 06:03:20 PM PDT 24
Peak memory 206740 kb
Host smart-d3431537-8d02-4e40-b02b-9fb2cef0e11a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30796
68403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_bitstuff_err.3079668403
Directory /workspace/46.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/46.usbdev_data_toggle_clear.1454195100
Short name T1289
Test name
Test status
Simulation time 468526345 ps
CPU time 1.45 seconds
Started Jul 22 06:03:20 PM PDT 24
Finished Jul 22 06:03:22 PM PDT 24
Peak memory 206736 kb
Host smart-b1d5f551-9fc6-4cd9-9ee4-db831f47889f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14541
95100 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_data_toggle_clear.1454195100
Directory /workspace/46.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/46.usbdev_device_address.2533450377
Short name T2570
Test name
Test status
Simulation time 18473237792 ps
CPU time 33.06 seconds
Started Jul 22 06:03:42 PM PDT 24
Finished Jul 22 06:04:16 PM PDT 24
Peak memory 206748 kb
Host smart-966514b8-11ab-4a3d-9d3b-4b01f3b6a9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25334
50377 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_device_address.2533450377
Directory /workspace/46.usbdev_device_address/latest

Test location /workspace/coverage/default/46.usbdev_disable_endpoint.1703233838
Short name T1406
Test name
Test status
Simulation time 367236610 ps
CPU time 1.28 seconds
Started Jul 22 06:03:39 PM PDT 24
Finished Jul 22 06:03:41 PM PDT 24
Peak memory 206712 kb
Host smart-b5ab6499-2463-426d-9ece-d31554c13cb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17032
33838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disable_endpoint.1703233838
Directory /workspace/46.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/46.usbdev_disconnected.779715875
Short name T49
Test name
Test status
Simulation time 145769474 ps
CPU time 0.73 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206748 kb
Host smart-e7854e14-0644-487e-b845-19fc197c14ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77971
5875 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_disconnected.779715875
Directory /workspace/46.usbdev_disconnected/latest

Test location /workspace/coverage/default/46.usbdev_enable.2122918662
Short name T1039
Test name
Test status
Simulation time 33142408 ps
CPU time 0.64 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:39 PM PDT 24
Peak memory 206716 kb
Host smart-cdd9e657-3bf0-4843-9ac7-eebf0618c1fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21229
18662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_enable.2122918662
Directory /workspace/46.usbdev_enable/latest

Test location /workspace/coverage/default/46.usbdev_endpoint_access.3802427198
Short name T2642
Test name
Test status
Simulation time 944404919 ps
CPU time 2.38 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:41 PM PDT 24
Peak memory 206824 kb
Host smart-9a7e3cd0-75e2-41e7-a9c0-2d938d7ced88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38024
27198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_endpoint_access.3802427198
Directory /workspace/46.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/46.usbdev_fifo_rst.2930005469
Short name T738
Test name
Test status
Simulation time 359936153 ps
CPU time 2.23 seconds
Started Jul 22 06:03:32 PM PDT 24
Finished Jul 22 06:03:35 PM PDT 24
Peak memory 206864 kb
Host smart-9ea11b4c-e048-4ce2-a1c0-12e6f5ac784f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29300
05469 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_fifo_rst.2930005469
Directory /workspace/46.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/46.usbdev_in_iso.871816622
Short name T1149
Test name
Test status
Simulation time 211582874 ps
CPU time 0.88 seconds
Started Jul 22 06:03:10 PM PDT 24
Finished Jul 22 06:03:13 PM PDT 24
Peak memory 206740 kb
Host smart-546b28a6-d559-42fd-96ff-f7cffd84e75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87181
6622 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_iso.871816622
Directory /workspace/46.usbdev_in_iso/latest

Test location /workspace/coverage/default/46.usbdev_in_stall.3358665504
Short name T2503
Test name
Test status
Simulation time 155105681 ps
CPU time 0.8 seconds
Started Jul 22 06:03:34 PM PDT 24
Finished Jul 22 06:03:35 PM PDT 24
Peak memory 206752 kb
Host smart-2b3fed99-bff8-4e32-ad37-78b58c0846c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33586
65504 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_stall.3358665504
Directory /workspace/46.usbdev_in_stall/latest

Test location /workspace/coverage/default/46.usbdev_in_trans.531559499
Short name T1385
Test name
Test status
Simulation time 180883571 ps
CPU time 0.83 seconds
Started Jul 22 06:03:34 PM PDT 24
Finished Jul 22 06:03:35 PM PDT 24
Peak memory 206728 kb
Host smart-b1315930-91d0-4f9d-b68a-fd299f44a97d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53155
9499 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_in_trans.531559499
Directory /workspace/46.usbdev_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_link_in_err.1427075201
Short name T2456
Test name
Test status
Simulation time 209367902 ps
CPU time 0.91 seconds
Started Jul 22 06:03:42 PM PDT 24
Finished Jul 22 06:03:44 PM PDT 24
Peak memory 206544 kb
Host smart-7f52f4b8-a30d-4212-8fa2-f9a5ca53ce0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14270
75201 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_in_err.1427075201
Directory /workspace/46.usbdev_link_in_err/latest

Test location /workspace/coverage/default/46.usbdev_link_resume.1056732691
Short name T1934
Test name
Test status
Simulation time 23344332769 ps
CPU time 28.85 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:43 PM PDT 24
Peak memory 206760 kb
Host smart-bf4328ca-8414-4dac-8a0f-0cf52df8d433
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10567
32691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_resume.1056732691
Directory /workspace/46.usbdev_link_resume/latest

Test location /workspace/coverage/default/46.usbdev_link_suspend.2765601105
Short name T574
Test name
Test status
Simulation time 3287272495 ps
CPU time 3.86 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:04:47 PM PDT 24
Peak memory 206796 kb
Host smart-1a906818-1b90-4f68-972f-d48a638e8e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27656
01105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_link_suspend.2765601105
Directory /workspace/46.usbdev_link_suspend/latest

Test location /workspace/coverage/default/46.usbdev_low_speed_traffic.2148031925
Short name T19
Test name
Test status
Simulation time 13581529020 ps
CPU time 121.24 seconds
Started Jul 22 06:03:43 PM PDT 24
Finished Jul 22 06:05:45 PM PDT 24
Peak memory 206960 kb
Host smart-fa9b6a4e-1d14-44d9-99e1-f63a52f1c3ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21480
31925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_low_speed_traffic.2148031925
Directory /workspace/46.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/46.usbdev_max_inter_pkt_delay.4131893067
Short name T1164
Test name
Test status
Simulation time 6836164795 ps
CPU time 177.21 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:06:34 PM PDT 24
Peak memory 206928 kb
Host smart-889ec817-264a-4a4f-9bd1-9d48df02f2e6
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4131893067 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_inter_pkt_delay.4131893067
Directory /workspace/46.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_max_length_in_transaction.1365853887
Short name T1141
Test name
Test status
Simulation time 244214695 ps
CPU time 0.9 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:41 PM PDT 24
Peak memory 206740 kb
Host smart-5d34f1e5-e43f-4823-b05b-28286e589e50
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=1365853887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_in_transaction.1365853887
Directory /workspace/46.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_length_out_transaction.4013461242
Short name T2273
Test name
Test status
Simulation time 205100930 ps
CPU time 0.91 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206744 kb
Host smart-a538b545-1295-4424-a3ba-f56d0073918e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40134
61242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_length_out_transaction.4013461242
Directory /workspace/46.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_max_usb_traffic.2576198335
Short name T2083
Test name
Test status
Simulation time 4634762698 ps
CPU time 33.07 seconds
Started Jul 22 06:03:28 PM PDT 24
Finished Jul 22 06:04:02 PM PDT 24
Peak memory 206808 kb
Host smart-fe2f8953-6d17-4380-882f-a7cb7cde9942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25761
98335 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_max_usb_traffic.2576198335
Directory /workspace/46.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/46.usbdev_min_inter_pkt_delay.3052694498
Short name T2135
Test name
Test status
Simulation time 4368300065 ps
CPU time 40.6 seconds
Started Jul 22 06:03:31 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 206904 kb
Host smart-3e3bc483-63d8-46a8-bbc3-766e9bd3adc7
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3052694498 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_inter_pkt_delay.3052694498
Directory /workspace/46.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/46.usbdev_min_length_in_transaction.1083333948
Short name T1025
Test name
Test status
Simulation time 177237703 ps
CPU time 0.79 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:41 PM PDT 24
Peak memory 206748 kb
Host smart-fa52538b-37fd-41a3-9ccb-68f04a02aa62
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1083333948 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_in_transaction.1083333948
Directory /workspace/46.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_min_length_out_transaction.70976242
Short name T1982
Test name
Test status
Simulation time 139867962 ps
CPU time 0.75 seconds
Started Jul 22 06:03:32 PM PDT 24
Finished Jul 22 06:03:33 PM PDT 24
Peak memory 206756 kb
Host smart-902552ba-2c79-4c5c-916c-6549da48d0e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70976
242 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_min_length_out_transaction.70976242
Directory /workspace/46.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_nak_trans.3957603268
Short name T122
Test name
Test status
Simulation time 167307584 ps
CPU time 0.81 seconds
Started Jul 22 06:03:31 PM PDT 24
Finished Jul 22 06:03:33 PM PDT 24
Peak memory 206764 kb
Host smart-71c1dce5-0b79-4a01-97bb-db8ae0c1e088
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39576
03268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_nak_trans.3957603268
Directory /workspace/46.usbdev_nak_trans/latest

Test location /workspace/coverage/default/46.usbdev_out_iso.197389594
Short name T726
Test name
Test status
Simulation time 163891484 ps
CPU time 0.82 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:40 PM PDT 24
Peak memory 206752 kb
Host smart-ade37cee-8d4d-4600-b0e4-9e4826dc66b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19738
9594 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_iso.197389594
Directory /workspace/46.usbdev_out_iso/latest

Test location /workspace/coverage/default/46.usbdev_out_stall.167025046
Short name T543
Test name
Test status
Simulation time 199376874 ps
CPU time 0.83 seconds
Started Jul 22 06:03:34 PM PDT 24
Finished Jul 22 06:03:36 PM PDT 24
Peak memory 206712 kb
Host smart-dfcefd14-4b0b-4896-a0cc-c71d10e4ac4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16702
5046 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_stall.167025046
Directory /workspace/46.usbdev_out_stall/latest

Test location /workspace/coverage/default/46.usbdev_out_trans_nak.3129319730
Short name T2376
Test name
Test status
Simulation time 147966622 ps
CPU time 0.77 seconds
Started Jul 22 06:04:43 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 206720 kb
Host smart-a011b689-ce0f-443e-8f67-cae16c8945cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31293
19730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_out_trans_nak.3129319730
Directory /workspace/46.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/46.usbdev_pending_in_trans.1216754183
Short name T1641
Test name
Test status
Simulation time 167892360 ps
CPU time 0.82 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:39 PM PDT 24
Peak memory 206752 kb
Host smart-098bb3bf-f765-4368-8bb1-6ca3718f1f0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12167
54183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pending_in_trans.1216754183
Directory /workspace/46.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_pinflip.3798234770
Short name T837
Test name
Test status
Simulation time 260650252 ps
CPU time 1.05 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:39 PM PDT 24
Peak memory 206756 kb
Host smart-77131a24-b083-4bec-b33b-abca493e3b48
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3798234770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_pinflip.3798234770
Directory /workspace/46.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/46.usbdev_phy_config_usb_ref_disable.750413474
Short name T1917
Test name
Test status
Simulation time 144514676 ps
CPU time 0.75 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206672 kb
Host smart-61260f9a-01f7-4f33-9ad2-9d2591f496a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75041
3474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_config_usb_ref_disable.750413474
Directory /workspace/46.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/46.usbdev_phy_pins_sense.1653707496
Short name T1098
Test name
Test status
Simulation time 32424875 ps
CPU time 0.63 seconds
Started Jul 22 06:03:31 PM PDT 24
Finished Jul 22 06:03:32 PM PDT 24
Peak memory 206760 kb
Host smart-faa8f82f-2852-48ee-9075-fb396e820947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16537
07496 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_phy_pins_sense.1653707496
Directory /workspace/46.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/46.usbdev_pkt_buffer.3632948836
Short name T275
Test name
Test status
Simulation time 8836158159 ps
CPU time 18.83 seconds
Started Jul 22 06:03:42 PM PDT 24
Finished Jul 22 06:04:02 PM PDT 24
Peak memory 206980 kb
Host smart-467df912-076f-4d8d-87fe-9e1a53400a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36329
48836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_buffer.3632948836
Directory /workspace/46.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/46.usbdev_pkt_received.1576083165
Short name T311
Test name
Test status
Simulation time 154709545 ps
CPU time 0.84 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:40 PM PDT 24
Peak memory 206756 kb
Host smart-003d3f3d-b291-4756-a7ee-14b527a86217
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15760
83165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_received.1576083165
Directory /workspace/46.usbdev_pkt_received/latest

Test location /workspace/coverage/default/46.usbdev_pkt_sent.1982930279
Short name T1372
Test name
Test status
Simulation time 156181654 ps
CPU time 0.79 seconds
Started Jul 22 06:03:36 PM PDT 24
Finished Jul 22 06:03:38 PM PDT 24
Peak memory 206744 kb
Host smart-5f0e35ad-3bab-4b89-8ca1-7ae63bdde82c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19829
30279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_pkt_sent.1982930279
Directory /workspace/46.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/46.usbdev_random_length_in_transaction.324127036
Short name T2714
Test name
Test status
Simulation time 224237867 ps
CPU time 0.93 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:40 PM PDT 24
Peak memory 206724 kb
Host smart-d638b981-cc76-43cd-9275-428d14ca8ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32412
7036 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_in_transaction.324127036
Directory /workspace/46.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/46.usbdev_random_length_out_transaction.1948269671
Short name T2491
Test name
Test status
Simulation time 259851627 ps
CPU time 0.87 seconds
Started Jul 22 06:03:28 PM PDT 24
Finished Jul 22 06:03:29 PM PDT 24
Peak memory 206728 kb
Host smart-4c48d5e8-a47b-42dc-9e80-57445b1e68bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19482
69671 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_random_length_out_transaction.1948269671
Directory /workspace/46.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/46.usbdev_rx_crc_err.2984473650
Short name T1249
Test name
Test status
Simulation time 205674890 ps
CPU time 0.78 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:25 PM PDT 24
Peak memory 206656 kb
Host smart-4f80887e-4842-411d-9ac3-e1c8ad4e4a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29844
73650 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_rx_crc_err.2984473650
Directory /workspace/46.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/46.usbdev_setup_stage.2552220836
Short name T1042
Test name
Test status
Simulation time 176961055 ps
CPU time 0.84 seconds
Started Jul 22 06:03:24 PM PDT 24
Finished Jul 22 06:03:25 PM PDT 24
Peak memory 206860 kb
Host smart-8084febe-1d64-4cff-914e-58eda51fcf11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25522
20836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_stage.2552220836
Directory /workspace/46.usbdev_setup_stage/latest

Test location /workspace/coverage/default/46.usbdev_setup_trans_ignored.924076601
Short name T972
Test name
Test status
Simulation time 149630913 ps
CPU time 0.79 seconds
Started Jul 22 06:03:45 PM PDT 24
Finished Jul 22 06:03:46 PM PDT 24
Peak memory 206736 kb
Host smart-3ea3772d-aee6-425c-aeaf-88645fbb3a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92407
6601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_setup_trans_ignored.924076601
Directory /workspace/46.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/46.usbdev_smoke.1572409390
Short name T1312
Test name
Test status
Simulation time 199118287 ps
CPU time 0.9 seconds
Started Jul 22 06:03:35 PM PDT 24
Finished Jul 22 06:03:37 PM PDT 24
Peak memory 206800 kb
Host smart-9ed15fa0-7934-4760-bd24-45ae0afd0b42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15724
09390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_smoke.1572409390
Directory /workspace/46.usbdev_smoke/latest

Test location /workspace/coverage/default/46.usbdev_spurious_pids_ignored.4225040230
Short name T1500
Test name
Test status
Simulation time 6106048662 ps
CPU time 54.09 seconds
Started Jul 22 06:03:41 PM PDT 24
Finished Jul 22 06:04:37 PM PDT 24
Peak memory 206900 kb
Host smart-3d80419a-5f52-4d14-a473-03b268e4f441
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4225040230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_spurious_pids_ignored.4225040230
Directory /workspace/46.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/46.usbdev_stall_priority_over_nak.3443968257
Short name T1661
Test name
Test status
Simulation time 216924859 ps
CPU time 0.84 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:25 PM PDT 24
Peak memory 206740 kb
Host smart-6114a830-4c26-40b4-bb69-43da47e317ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34439
68257 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_priority_over_nak.3443968257
Directory /workspace/46.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/46.usbdev_stall_trans.2130961768
Short name T891
Test name
Test status
Simulation time 175665926 ps
CPU time 0.83 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:40 PM PDT 24
Peak memory 206748 kb
Host smart-0c5566e0-fd4f-46b1-a600-8db8d48026c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21309
61768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stall_trans.2130961768
Directory /workspace/46.usbdev_stall_trans/latest

Test location /workspace/coverage/default/46.usbdev_stream_len_max.2628797207
Short name T2467
Test name
Test status
Simulation time 201087901 ps
CPU time 0.88 seconds
Started Jul 22 06:04:13 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 206680 kb
Host smart-2e317a72-9817-414d-803a-c59eb293c527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26287
97207 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_stream_len_max.2628797207
Directory /workspace/46.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/46.usbdev_streaming_out.3880909271
Short name T2630
Test name
Test status
Simulation time 7432164669 ps
CPU time 68.57 seconds
Started Jul 22 06:03:33 PM PDT 24
Finished Jul 22 06:04:42 PM PDT 24
Peak memory 206904 kb
Host smart-ecee4f89-7c87-4236-b740-17431b72a62b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38809
09271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.usbdev_streaming_out.3880909271
Directory /workspace/46.usbdev_streaming_out/latest

Test location /workspace/coverage/default/47.usbdev_alert_test.4175351583
Short name T979
Test name
Test status
Simulation time 39432792 ps
CPU time 0.68 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206704 kb
Host smart-1a49f39a-e076-440b-b9cb-59324431f307
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=4175351583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_alert_test.4175351583
Directory /workspace/47.usbdev_alert_test/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_disconnect.52929428
Short name T1763
Test name
Test status
Simulation time 4286596175 ps
CPU time 5.12 seconds
Started Jul 22 06:03:28 PM PDT 24
Finished Jul 22 06:03:33 PM PDT 24
Peak memory 206776 kb
Host smart-59377ad9-e661-49fe-aa2a-9d7548472b1b
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=52929428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_disconnect.52929428
Directory /workspace/47.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_reset.1706594808
Short name T2719
Test name
Test status
Simulation time 13380559730 ps
CPU time 11.8 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:51 PM PDT 24
Peak memory 206932 kb
Host smart-b73b5ee2-ea5a-43f2-9852-77af0a7683bf
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1706594808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_reset.1706594808
Directory /workspace/47.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/47.usbdev_aon_wake_resume.1916532969
Short name T1739
Test name
Test status
Simulation time 23304889827 ps
CPU time 22.68 seconds
Started Jul 22 06:03:36 PM PDT 24
Finished Jul 22 06:03:59 PM PDT 24
Peak memory 206820 kb
Host smart-d5328fe6-5db0-4053-91b7-1e03b6cddc98
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1916532969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_aon_wake_resume.1916532969
Directory /workspace/47.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/47.usbdev_av_buffer.1970260945
Short name T774
Test name
Test status
Simulation time 177626937 ps
CPU time 0.87 seconds
Started Jul 22 06:03:44 PM PDT 24
Finished Jul 22 06:03:45 PM PDT 24
Peak memory 206732 kb
Host smart-f28a9e89-0d57-4ae2-b50e-035f960ebc94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19702
60945 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_av_buffer.1970260945
Directory /workspace/47.usbdev_av_buffer/latest

Test location /workspace/coverage/default/47.usbdev_bitstuff_err.1073179215
Short name T2409
Test name
Test status
Simulation time 149236369 ps
CPU time 0.82 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:40 PM PDT 24
Peak memory 206748 kb
Host smart-5a7c3fcf-5f57-4c6a-8593-9ac6a4384380
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10731
79215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_bitstuff_err.1073179215
Directory /workspace/47.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_clear.669795730
Short name T1346
Test name
Test status
Simulation time 420167398 ps
CPU time 1.33 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:39 PM PDT 24
Peak memory 206756 kb
Host smart-04ac2e83-481e-42c6-b363-2112e5744ffd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66979
5730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_clear.669795730
Directory /workspace/47.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/47.usbdev_data_toggle_restore.201937748
Short name T1647
Test name
Test status
Simulation time 932356706 ps
CPU time 2.09 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206816 kb
Host smart-ddeb6141-2b27-4cd3-bd67-71943528d2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20193
7748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_data_toggle_restore.201937748
Directory /workspace/47.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/47.usbdev_device_address.3179869971
Short name T640
Test name
Test status
Simulation time 7903263845 ps
CPU time 14.5 seconds
Started Jul 22 06:03:43 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 206860 kb
Host smart-3e3dc6e9-74b8-4e30-b720-1fdfb23fe958
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31798
69971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_device_address.3179869971
Directory /workspace/47.usbdev_device_address/latest

Test location /workspace/coverage/default/47.usbdev_disable_endpoint.4027232287
Short name T2371
Test name
Test status
Simulation time 365517296 ps
CPU time 1.2 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:38 PM PDT 24
Peak memory 206744 kb
Host smart-78336cb3-fbcf-4f95-93ec-6bb2f003a10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40272
32287 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disable_endpoint.4027232287
Directory /workspace/47.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/47.usbdev_disconnected.888384769
Short name T1547
Test name
Test status
Simulation time 142048803 ps
CPU time 0.76 seconds
Started Jul 22 06:03:42 PM PDT 24
Finished Jul 22 06:03:43 PM PDT 24
Peak memory 206668 kb
Host smart-faa7aeec-315b-4ba0-9320-59d9a4a74128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88838
4769 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_disconnected.888384769
Directory /workspace/47.usbdev_disconnected/latest

Test location /workspace/coverage/default/47.usbdev_enable.123971426
Short name T1214
Test name
Test status
Simulation time 80103728 ps
CPU time 0.69 seconds
Started Jul 22 06:03:31 PM PDT 24
Finished Jul 22 06:03:32 PM PDT 24
Peak memory 206748 kb
Host smart-1710c534-7cc8-4fc9-b04e-1354ce8270f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12397
1426 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_enable.123971426
Directory /workspace/47.usbdev_enable/latest

Test location /workspace/coverage/default/47.usbdev_endpoint_access.702175072
Short name T1207
Test name
Test status
Simulation time 814452389 ps
CPU time 1.92 seconds
Started Jul 22 06:03:23 PM PDT 24
Finished Jul 22 06:03:26 PM PDT 24
Peak memory 206808 kb
Host smart-1dcb3dc0-8157-488f-92c0-50018235186c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70217
5072 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_endpoint_access.702175072
Directory /workspace/47.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/47.usbdev_fifo_rst.333597328
Short name T924
Test name
Test status
Simulation time 209764201 ps
CPU time 2.01 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:39 PM PDT 24
Peak memory 206840 kb
Host smart-85e5f1bb-2e45-4f47-98d7-8de585b660b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33359
7328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_fifo_rst.333597328
Directory /workspace/47.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/47.usbdev_in_iso.3035528762
Short name T908
Test name
Test status
Simulation time 155739618 ps
CPU time 0.79 seconds
Started Jul 22 06:03:32 PM PDT 24
Finished Jul 22 06:03:33 PM PDT 24
Peak memory 206752 kb
Host smart-88e7dfd0-8d64-479e-b91f-495f7f5da838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30355
28762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_iso.3035528762
Directory /workspace/47.usbdev_in_iso/latest

Test location /workspace/coverage/default/47.usbdev_in_stall.4264501969
Short name T1349
Test name
Test status
Simulation time 153627253 ps
CPU time 0.82 seconds
Started Jul 22 06:03:42 PM PDT 24
Finished Jul 22 06:03:43 PM PDT 24
Peak memory 206736 kb
Host smart-86fa2be4-86e3-46ed-9d65-ac3c87a9df37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42645
01969 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_stall.4264501969
Directory /workspace/47.usbdev_in_stall/latest

Test location /workspace/coverage/default/47.usbdev_in_trans.1386697454
Short name T667
Test name
Test status
Simulation time 189478167 ps
CPU time 0.85 seconds
Started Jul 22 06:03:22 PM PDT 24
Finished Jul 22 06:03:24 PM PDT 24
Peak memory 206860 kb
Host smart-9a5ad7d1-97b3-4c4c-9dd7-2af8945d711d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13866
97454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_in_trans.1386697454
Directory /workspace/47.usbdev_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_invalid_sync.171746788
Short name T1836
Test name
Test status
Simulation time 9335866663 ps
CPU time 89.38 seconds
Started Jul 22 06:03:41 PM PDT 24
Finished Jul 22 06:05:12 PM PDT 24
Peak memory 206900 kb
Host smart-b045bb2a-de58-4952-9fa1-574bd7edcd08
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=171746788 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_invalid_sync.171746788
Directory /workspace/47.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/47.usbdev_iso_retraction.1356412534
Short name T1766
Test name
Test status
Simulation time 6755048718 ps
CPU time 58.04 seconds
Started Jul 22 06:03:43 PM PDT 24
Finished Jul 22 06:04:42 PM PDT 24
Peak memory 206956 kb
Host smart-cd39912d-0f27-48c9-a64c-34f351305bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13564
12534 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_iso_retraction.1356412534
Directory /workspace/47.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/47.usbdev_link_in_err.644940669
Short name T2010
Test name
Test status
Simulation time 221493628 ps
CPU time 0.98 seconds
Started Jul 22 06:03:42 PM PDT 24
Finished Jul 22 06:03:44 PM PDT 24
Peak memory 206712 kb
Host smart-31794f00-b8f7-425b-8577-60ea4ad12854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64494
0669 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_in_err.644940669
Directory /workspace/47.usbdev_link_in_err/latest

Test location /workspace/coverage/default/47.usbdev_link_resume.615627166
Short name T2740
Test name
Test status
Simulation time 23275847633 ps
CPU time 23.01 seconds
Started Jul 22 06:03:31 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206788 kb
Host smart-f7a30d73-aca8-4ae1-a6e2-8a779f6caf2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61562
7166 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_resume.615627166
Directory /workspace/47.usbdev_link_resume/latest

Test location /workspace/coverage/default/47.usbdev_link_suspend.3718961975
Short name T778
Test name
Test status
Simulation time 3285079145 ps
CPU time 3.78 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:45 PM PDT 24
Peak memory 206788 kb
Host smart-395f4b2b-5bab-4603-83a4-350a031d7aff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37189
61975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_link_suspend.3718961975
Directory /workspace/47.usbdev_link_suspend/latest

Test location /workspace/coverage/default/47.usbdev_low_speed_traffic.2565802402
Short name T2047
Test name
Test status
Simulation time 12388274002 ps
CPU time 83.45 seconds
Started Jul 22 06:03:36 PM PDT 24
Finished Jul 22 06:04:59 PM PDT 24
Peak memory 206864 kb
Host smart-97278da5-6732-45f3-9b73-4e9d736db46c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25658
02402 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_low_speed_traffic.2565802402
Directory /workspace/47.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/47.usbdev_max_inter_pkt_delay.2531374325
Short name T169
Test name
Test status
Simulation time 7333218735 ps
CPU time 64.63 seconds
Started Jul 22 06:03:39 PM PDT 24
Finished Jul 22 06:04:45 PM PDT 24
Peak memory 206952 kb
Host smart-e7fb3808-ba11-40cb-99b0-24ad54b85e9d
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2531374325 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_inter_pkt_delay.2531374325
Directory /workspace/47.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_max_length_in_transaction.70893161
Short name T938
Test name
Test status
Simulation time 235851069 ps
CPU time 0.94 seconds
Started Jul 22 06:04:37 PM PDT 24
Finished Jul 22 06:04:38 PM PDT 24
Peak memory 206216 kb
Host smart-0819cf42-2373-4e3c-bd0c-c8c4d8480636
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=70893161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_in_transaction.70893161
Directory /workspace/47.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_length_out_transaction.869497451
Short name T932
Test name
Test status
Simulation time 230731088 ps
CPU time 0.91 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206704 kb
Host smart-625d1d79-63eb-4240-b456-38dd411ff506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86949
7451 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_length_out_transaction.869497451
Directory /workspace/47.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_max_usb_traffic.2271770814
Short name T925
Test name
Test status
Simulation time 5406080136 ps
CPU time 143.09 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:06:01 PM PDT 24
Peak memory 206780 kb
Host smart-8c12263d-0ef9-4c10-9c2d-c37be811cc31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22717
70814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_max_usb_traffic.2271770814
Directory /workspace/47.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/47.usbdev_min_inter_pkt_delay.1781127109
Short name T1450
Test name
Test status
Simulation time 7439840233 ps
CPU time 70.28 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:04:49 PM PDT 24
Peak memory 206944 kb
Host smart-54fc151f-c868-4a41-93ad-4ad504e7488f
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1781127109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_inter_pkt_delay.1781127109
Directory /workspace/47.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/47.usbdev_min_length_in_transaction.1054447279
Short name T697
Test name
Test status
Simulation time 188643728 ps
CPU time 0.81 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:41 PM PDT 24
Peak memory 206728 kb
Host smart-06775485-02b5-4a55-bb65-c887c5df5d49
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1054447279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_in_transaction.1054447279
Directory /workspace/47.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_min_length_out_transaction.563118129
Short name T1930
Test name
Test status
Simulation time 139823314 ps
CPU time 0.78 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 206716 kb
Host smart-8f19125a-1dc3-4ebb-80f5-6a4fcffdd283
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56311
8129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_min_length_out_transaction.563118129
Directory /workspace/47.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_nak_trans.1002769538
Short name T1665
Test name
Test status
Simulation time 195499174 ps
CPU time 0.91 seconds
Started Jul 22 06:04:43 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 206736 kb
Host smart-3d7fc032-43f1-4599-86b1-afe8cfd732a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10027
69538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_nak_trans.1002769538
Directory /workspace/47.usbdev_nak_trans/latest

Test location /workspace/coverage/default/47.usbdev_out_iso.3351307877
Short name T1179
Test name
Test status
Simulation time 200893175 ps
CPU time 0.84 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:40 PM PDT 24
Peak memory 206716 kb
Host smart-0281b8ba-c94a-4201-b788-8147f7188566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33513
07877 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_iso.3351307877
Directory /workspace/47.usbdev_out_iso/latest

Test location /workspace/coverage/default/47.usbdev_out_stall.209096413
Short name T638
Test name
Test status
Simulation time 181677430 ps
CPU time 0.82 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206724 kb
Host smart-b8849fe3-343a-4cf5-8057-3194978a6fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20909
6413 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_stall.209096413
Directory /workspace/47.usbdev_out_stall/latest

Test location /workspace/coverage/default/47.usbdev_out_trans_nak.4252780643
Short name T1475
Test name
Test status
Simulation time 175534257 ps
CPU time 0.93 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 206676 kb
Host smart-31ba3162-fed2-46b3-aadf-3b9d231158c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42527
80643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_out_trans_nak.4252780643
Directory /workspace/47.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/47.usbdev_pending_in_trans.4103908929
Short name T178
Test name
Test status
Simulation time 153347989 ps
CPU time 0.8 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 206752 kb
Host smart-7726517b-a509-4b8b-b99d-7d77c844c1fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41039
08929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pending_in_trans.4103908929
Directory /workspace/47.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_pinflip.892422147
Short name T2729
Test name
Test status
Simulation time 254132411 ps
CPU time 0.97 seconds
Started Jul 22 06:03:45 PM PDT 24
Finished Jul 22 06:03:46 PM PDT 24
Peak memory 206740 kb
Host smart-6baba852-1adc-4070-83f4-b3142aa89297
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=892422147 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_pinflip.892422147
Directory /workspace/47.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/47.usbdev_phy_config_usb_ref_disable.2414129514
Short name T2013
Test name
Test status
Simulation time 146777707 ps
CPU time 0.79 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206720 kb
Host smart-452d7478-eeda-48a9-a92e-1e6625a01fe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24141
29514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_config_usb_ref_disable.2414129514
Directory /workspace/47.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/47.usbdev_phy_pins_sense.2960333389
Short name T40
Test name
Test status
Simulation time 42462557 ps
CPU time 0.65 seconds
Started Jul 22 06:03:46 PM PDT 24
Finished Jul 22 06:03:48 PM PDT 24
Peak memory 206696 kb
Host smart-973cc18d-ed6d-4352-9386-44ee87dcffeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29603
33389 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_phy_pins_sense.2960333389
Directory /workspace/47.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/47.usbdev_pkt_buffer.812265535
Short name T1805
Test name
Test status
Simulation time 12983159919 ps
CPU time 29.34 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:04:09 PM PDT 24
Peak memory 206964 kb
Host smart-25bbee64-4a51-403e-a2c4-95d35098a604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81226
5535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_buffer.812265535
Directory /workspace/47.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/47.usbdev_pkt_received.2821699532
Short name T2511
Test name
Test status
Simulation time 144226489 ps
CPU time 0.77 seconds
Started Jul 22 06:03:28 PM PDT 24
Finished Jul 22 06:03:30 PM PDT 24
Peak memory 206748 kb
Host smart-2f73fd8d-a556-47da-81ec-6029422479ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28216
99532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_received.2821699532
Directory /workspace/47.usbdev_pkt_received/latest

Test location /workspace/coverage/default/47.usbdev_pkt_sent.2135023878
Short name T498
Test name
Test status
Simulation time 283671531 ps
CPU time 0.95 seconds
Started Jul 22 06:03:25 PM PDT 24
Finished Jul 22 06:03:27 PM PDT 24
Peak memory 206696 kb
Host smart-dfc64b71-e5c1-49b6-b3d4-240a8bcc904a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21350
23878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_pkt_sent.2135023878
Directory /workspace/47.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/47.usbdev_random_length_in_transaction.660620984
Short name T1792
Test name
Test status
Simulation time 229373680 ps
CPU time 0.96 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 206752 kb
Host smart-207f4331-9850-41d2-aa8b-755c6578ea0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66062
0984 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_in_transaction.660620984
Directory /workspace/47.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/47.usbdev_random_length_out_transaction.3018715642
Short name T1821
Test name
Test status
Simulation time 192233790 ps
CPU time 0.87 seconds
Started Jul 22 06:04:37 PM PDT 24
Finished Jul 22 06:04:38 PM PDT 24
Peak memory 206196 kb
Host smart-b2dd256c-2f54-4523-862e-3206bfc22dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30187
15642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_random_length_out_transaction.3018715642
Directory /workspace/47.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/47.usbdev_rx_crc_err.2660735745
Short name T2496
Test name
Test status
Simulation time 135616910 ps
CPU time 0.73 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206724 kb
Host smart-4192ba6e-5d13-4310-bc81-9d0136e921c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26607
35745 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_rx_crc_err.2660735745
Directory /workspace/47.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/47.usbdev_setup_stage.3407816230
Short name T1073
Test name
Test status
Simulation time 152134859 ps
CPU time 0.81 seconds
Started Jul 22 06:03:26 PM PDT 24
Finished Jul 22 06:03:27 PM PDT 24
Peak memory 206680 kb
Host smart-0c008869-093c-46b9-81bd-e67faf2fb371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34078
16230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_stage.3407816230
Directory /workspace/47.usbdev_setup_stage/latest

Test location /workspace/coverage/default/47.usbdev_setup_trans_ignored.2011796077
Short name T552
Test name
Test status
Simulation time 175767712 ps
CPU time 0.8 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 206752 kb
Host smart-45457693-2f62-4166-b7eb-52820049539e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20117
96077 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_setup_trans_ignored.2011796077
Directory /workspace/47.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/47.usbdev_smoke.1339301623
Short name T1689
Test name
Test status
Simulation time 246410294 ps
CPU time 0.92 seconds
Started Jul 22 06:03:39 PM PDT 24
Finished Jul 22 06:03:41 PM PDT 24
Peak memory 206720 kb
Host smart-542a8216-b40e-4a9d-b380-6e9d2e210111
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13393
01623 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_smoke.1339301623
Directory /workspace/47.usbdev_smoke/latest

Test location /workspace/coverage/default/47.usbdev_spurious_pids_ignored.45811239
Short name T1721
Test name
Test status
Simulation time 5374484178 ps
CPU time 48.53 seconds
Started Jul 22 06:03:41 PM PDT 24
Finished Jul 22 06:04:31 PM PDT 24
Peak memory 206940 kb
Host smart-e3d5d5a5-60b6-4eee-aa51-deeb1e95e280
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=45811239 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_spurious_pids_ignored.45811239
Directory /workspace/47.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/47.usbdev_stall_priority_over_nak.3514995647
Short name T2172
Test name
Test status
Simulation time 151339621 ps
CPU time 0.79 seconds
Started Jul 22 06:03:26 PM PDT 24
Finished Jul 22 06:03:28 PM PDT 24
Peak memory 206736 kb
Host smart-245b2b8b-dc7f-48da-a250-0811c42422d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35149
95647 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_priority_over_nak.3514995647
Directory /workspace/47.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/47.usbdev_stall_trans.3827112502
Short name T736
Test name
Test status
Simulation time 175364603 ps
CPU time 0.89 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 206748 kb
Host smart-72d5f8b8-d004-42d7-b722-a0535e762224
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38271
12502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stall_trans.3827112502
Directory /workspace/47.usbdev_stall_trans/latest

Test location /workspace/coverage/default/47.usbdev_stream_len_max.583591232
Short name T1618
Test name
Test status
Simulation time 869095420 ps
CPU time 1.86 seconds
Started Jul 22 06:03:30 PM PDT 24
Finished Jul 22 06:03:32 PM PDT 24
Peak memory 206852 kb
Host smart-16a3daf1-a9b2-4283-9a50-5484306c9e56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58359
1232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_stream_len_max.583591232
Directory /workspace/47.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/47.usbdev_streaming_out.4194612542
Short name T735
Test name
Test status
Simulation time 3822859354 ps
CPU time 28.53 seconds
Started Jul 22 06:03:46 PM PDT 24
Finished Jul 22 06:04:15 PM PDT 24
Peak memory 206960 kb
Host smart-e5403013-3687-4864-9d88-1ea71e1618f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41946
12542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.usbdev_streaming_out.4194612542
Directory /workspace/47.usbdev_streaming_out/latest

Test location /workspace/coverage/default/48.usbdev_alert_test.3206787943
Short name T2138
Test name
Test status
Simulation time 95937346 ps
CPU time 0.74 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206712 kb
Host smart-e75b61b3-da1c-4efd-830b-92a45403ef7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3206787943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_alert_test.3206787943
Directory /workspace/48.usbdev_alert_test/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_disconnect.3527403148
Short name T1150
Test name
Test status
Simulation time 4302149118 ps
CPU time 5.33 seconds
Started Jul 22 06:03:42 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206912 kb
Host smart-f38b76f1-5b81-465f-b62c-58f2c8696eaa
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3527403148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_disconnect.3527403148
Directory /workspace/48.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_reset.3660160466
Short name T2720
Test name
Test status
Simulation time 13366165390 ps
CPU time 13.31 seconds
Started Jul 22 06:03:39 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206780 kb
Host smart-e81df7d1-bc15-49e3-a4b6-3b9985e01c02
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3660160466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_reset.3660160466
Directory /workspace/48.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/48.usbdev_aon_wake_resume.2152871699
Short name T838
Test name
Test status
Simulation time 23346722413 ps
CPU time 24.85 seconds
Started Jul 22 06:03:30 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 206888 kb
Host smart-3c51c67c-4782-4754-801c-a417ef8d4a1c
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2152871699 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_aon_wake_resume.2152871699
Directory /workspace/48.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/48.usbdev_av_buffer.3524552108
Short name T426
Test name
Test status
Simulation time 145966495 ps
CPU time 0.86 seconds
Started Jul 22 06:03:31 PM PDT 24
Finished Jul 22 06:03:32 PM PDT 24
Peak memory 206732 kb
Host smart-1d261c0c-87c4-4a1d-94f5-3ebf90b88902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35245
52108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_av_buffer.3524552108
Directory /workspace/48.usbdev_av_buffer/latest

Test location /workspace/coverage/default/48.usbdev_bitstuff_err.462222021
Short name T716
Test name
Test status
Simulation time 174570956 ps
CPU time 0.83 seconds
Started Jul 22 06:03:33 PM PDT 24
Finished Jul 22 06:03:35 PM PDT 24
Peak memory 206748 kb
Host smart-c6218c0e-d3ef-437f-b255-bcb55e476ad8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46222
2021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_bitstuff_err.462222021
Directory /workspace/48.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_clear.4170373680
Short name T17
Test name
Test status
Simulation time 598780302 ps
CPU time 1.65 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206880 kb
Host smart-2ce08748-1baa-4c23-8c42-63fbd465442d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41703
73680 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_clear.4170373680
Directory /workspace/48.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/48.usbdev_data_toggle_restore.3177103390
Short name T589
Test name
Test status
Simulation time 537871191 ps
CPU time 1.45 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:39 PM PDT 24
Peak memory 206732 kb
Host smart-8f10363b-2373-443e-8a69-4168d0f849dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31771
03390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_data_toggle_restore.3177103390
Directory /workspace/48.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/48.usbdev_device_address.852006068
Short name T1662
Test name
Test status
Simulation time 15104798405 ps
CPU time 29.14 seconds
Started Jul 22 06:03:49 PM PDT 24
Finished Jul 22 06:04:20 PM PDT 24
Peak memory 206932 kb
Host smart-691bbaf2-1d0b-45a0-899f-e0a6f11eaffa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85200
6068 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_device_address.852006068
Directory /workspace/48.usbdev_device_address/latest

Test location /workspace/coverage/default/48.usbdev_disable_endpoint.2456069780
Short name T1258
Test name
Test status
Simulation time 390485551 ps
CPU time 1.2 seconds
Started Jul 22 06:05:33 PM PDT 24
Finished Jul 22 06:05:35 PM PDT 24
Peak memory 206684 kb
Host smart-6665153e-4ecc-4bca-b0ce-15b52c5ebaf9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24560
69780 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disable_endpoint.2456069780
Directory /workspace/48.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/48.usbdev_disconnected.1357336170
Short name T776
Test name
Test status
Simulation time 141248512 ps
CPU time 0.76 seconds
Started Jul 22 06:03:41 PM PDT 24
Finished Jul 22 06:03:43 PM PDT 24
Peak memory 206748 kb
Host smart-0719e9f0-8fbe-43c3-b9c3-c43e5521b537
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13573
36170 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_disconnected.1357336170
Directory /workspace/48.usbdev_disconnected/latest

Test location /workspace/coverage/default/48.usbdev_enable.1141078226
Short name T2270
Test name
Test status
Simulation time 59751658 ps
CPU time 0.74 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 206668 kb
Host smart-f4469080-1e25-4a5d-8394-e3a43429de2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11410
78226 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_enable.1141078226
Directory /workspace/48.usbdev_enable/latest

Test location /workspace/coverage/default/48.usbdev_endpoint_access.3716295076
Short name T1248
Test name
Test status
Simulation time 1224246262 ps
CPU time 2.65 seconds
Started Jul 22 06:03:59 PM PDT 24
Finished Jul 22 06:04:03 PM PDT 24
Peak memory 206852 kb
Host smart-a31eae29-0c31-4952-948d-32f79d4b2c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37162
95076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_endpoint_access.3716295076
Directory /workspace/48.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/48.usbdev_fifo_rst.1493158428
Short name T987
Test name
Test status
Simulation time 165414076 ps
CPU time 1.38 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206812 kb
Host smart-748ea8ce-8d38-43ef-91a7-e9ac7bad29b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14931
58428 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_fifo_rst.1493158428
Directory /workspace/48.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/48.usbdev_in_iso.946586997
Short name T343
Test name
Test status
Simulation time 195890174 ps
CPU time 0.8 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206700 kb
Host smart-f6a7014c-004b-4bb0-8cc4-b49d53ddb096
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94658
6997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_iso.946586997
Directory /workspace/48.usbdev_in_iso/latest

Test location /workspace/coverage/default/48.usbdev_in_stall.3417000535
Short name T2259
Test name
Test status
Simulation time 150761969 ps
CPU time 0.78 seconds
Started Jul 22 06:05:32 PM PDT 24
Finished Jul 22 06:05:34 PM PDT 24
Peak memory 206752 kb
Host smart-276cea78-ec0e-449f-b800-84b7769271b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34170
00535 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_stall.3417000535
Directory /workspace/48.usbdev_in_stall/latest

Test location /workspace/coverage/default/48.usbdev_in_trans.2865215454
Short name T1246
Test name
Test status
Simulation time 169583316 ps
CPU time 0.82 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:51 PM PDT 24
Peak memory 206748 kb
Host smart-5616a19c-abc4-4688-bde1-2f55eceeca28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28652
15454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_in_trans.2865215454
Directory /workspace/48.usbdev_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_invalid_sync.3490092595
Short name T100
Test name
Test status
Simulation time 5940491582 ps
CPU time 55.87 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:04:50 PM PDT 24
Peak memory 206960 kb
Host smart-d812bd57-2268-4ea6-acfc-e817e4a32f6b
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3490092595 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_invalid_sync.3490092595
Directory /workspace/48.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/48.usbdev_link_in_err.3105623976
Short name T992
Test name
Test status
Simulation time 241910648 ps
CPU time 0.94 seconds
Started Jul 22 06:03:33 PM PDT 24
Finished Jul 22 06:03:34 PM PDT 24
Peak memory 206736 kb
Host smart-b3f950ef-cda9-4375-930e-4200dc614c4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31056
23976 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_in_err.3105623976
Directory /workspace/48.usbdev_link_in_err/latest

Test location /workspace/coverage/default/48.usbdev_link_resume.2384688834
Short name T1825
Test name
Test status
Simulation time 23329889180 ps
CPU time 21.53 seconds
Started Jul 22 06:03:36 PM PDT 24
Finished Jul 22 06:03:58 PM PDT 24
Peak memory 206808 kb
Host smart-645e9f45-c3bc-4b75-bfa6-53c4bb7bef91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23846
88834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_resume.2384688834
Directory /workspace/48.usbdev_link_resume/latest

Test location /workspace/coverage/default/48.usbdev_link_suspend.16815762
Short name T541
Test name
Test status
Simulation time 3340723840 ps
CPU time 3.86 seconds
Started Jul 22 06:03:46 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206816 kb
Host smart-e11eeecf-e164-451e-8a3e-ce4c7c4569a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16815
762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_link_suspend.16815762
Directory /workspace/48.usbdev_link_suspend/latest

Test location /workspace/coverage/default/48.usbdev_low_speed_traffic.1341790103
Short name T623
Test name
Test status
Simulation time 11243622876 ps
CPU time 84.13 seconds
Started Jul 22 06:03:50 PM PDT 24
Finished Jul 22 06:05:16 PM PDT 24
Peak memory 206984 kb
Host smart-fd829114-ac4a-4ce6-a16c-ec947ccfee81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13417
90103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_low_speed_traffic.1341790103
Directory /workspace/48.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/48.usbdev_max_inter_pkt_delay.439643853
Short name T725
Test name
Test status
Simulation time 4086622774 ps
CPU time 105.42 seconds
Started Jul 22 06:03:41 PM PDT 24
Finished Jul 22 06:05:28 PM PDT 24
Peak memory 206888 kb
Host smart-685bf7a9-0dcc-4a27-9e4f-d3969489d8e0
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=439643853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_inter_pkt_delay.439643853
Directory /workspace/48.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_max_length_in_transaction.2202179666
Short name T2277
Test name
Test status
Simulation time 240531602 ps
CPU time 0.95 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206720 kb
Host smart-2584cbbf-3034-4877-9659-db936e307e2d
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=2202179666 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_in_transaction.2202179666
Directory /workspace/48.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_length_out_transaction.2205853234
Short name T564
Test name
Test status
Simulation time 189099304 ps
CPU time 0.88 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206744 kb
Host smart-5bcba9bf-5b5d-4d6d-922f-7e8272c31c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22058
53234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_length_out_transaction.2205853234
Directory /workspace/48.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_max_usb_traffic.3636671121
Short name T1616
Test name
Test status
Simulation time 5746442137 ps
CPU time 161.29 seconds
Started Jul 22 06:03:41 PM PDT 24
Finished Jul 22 06:06:23 PM PDT 24
Peak memory 206864 kb
Host smart-53fc7294-53f9-4b98-8c97-bf35f87dc7cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36366
71121 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_max_usb_traffic.3636671121
Directory /workspace/48.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/48.usbdev_min_inter_pkt_delay.2111927513
Short name T1270
Test name
Test status
Simulation time 4825677340 ps
CPU time 35.33 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:04:23 PM PDT 24
Peak memory 206868 kb
Host smart-a17e2961-e1a9-473e-a699-7eaf929b6b33
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2111927513 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_inter_pkt_delay.2111927513
Directory /workspace/48.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/48.usbdev_min_length_in_transaction.814721941
Short name T519
Test name
Test status
Simulation time 149261350 ps
CPU time 0.78 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206756 kb
Host smart-11085f51-bbb7-473c-ae1c-d6c4544b70ee
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=814721941 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_in_transaction.814721941
Directory /workspace/48.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_min_length_out_transaction.931401994
Short name T1007
Test name
Test status
Simulation time 151216956 ps
CPU time 0.86 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206700 kb
Host smart-146e120d-bcfb-4f39-8cee-84de1d780ae2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93140
1994 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_min_length_out_transaction.931401994
Directory /workspace/48.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_nak_trans.1618027482
Short name T127
Test name
Test status
Simulation time 167800709 ps
CPU time 0.82 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206736 kb
Host smart-ac22a865-2a1a-49ec-af23-f675399a7585
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16180
27482 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_nak_trans.1618027482
Directory /workspace/48.usbdev_nak_trans/latest

Test location /workspace/coverage/default/48.usbdev_out_iso.3699280304
Short name T1568
Test name
Test status
Simulation time 184391537 ps
CPU time 0.92 seconds
Started Jul 22 06:03:36 PM PDT 24
Finished Jul 22 06:03:38 PM PDT 24
Peak memory 206696 kb
Host smart-55e9e52c-e1ac-4ad1-818e-0dd185733538
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36992
80304 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_iso.3699280304
Directory /workspace/48.usbdev_out_iso/latest

Test location /workspace/coverage/default/48.usbdev_out_stall.631330561
Short name T2281
Test name
Test status
Simulation time 155509950 ps
CPU time 0.8 seconds
Started Jul 22 06:03:35 PM PDT 24
Finished Jul 22 06:03:36 PM PDT 24
Peak memory 206756 kb
Host smart-846372a4-7301-42c6-9f66-1298004e5e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63133
0561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_stall.631330561
Directory /workspace/48.usbdev_out_stall/latest

Test location /workspace/coverage/default/48.usbdev_out_trans_nak.3040309719
Short name T836
Test name
Test status
Simulation time 206223916 ps
CPU time 0.88 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206736 kb
Host smart-940c1918-7b30-47b3-80c1-c7b52d03cac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30403
09719 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_out_trans_nak.3040309719
Directory /workspace/48.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/48.usbdev_pending_in_trans.2050602793
Short name T680
Test name
Test status
Simulation time 155620571 ps
CPU time 0.79 seconds
Started Jul 22 06:03:43 PM PDT 24
Finished Jul 22 06:03:44 PM PDT 24
Peak memory 206752 kb
Host smart-7728e275-2216-4d5e-88bf-415c68d8d39d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20506
02793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pending_in_trans.2050602793
Directory /workspace/48.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_pinflip.1142908452
Short name T518
Test name
Test status
Simulation time 236444798 ps
CPU time 0.99 seconds
Started Jul 22 06:03:50 PM PDT 24
Finished Jul 22 06:03:52 PM PDT 24
Peak memory 206780 kb
Host smart-2b55ed34-ca5f-4f91-b95d-a6ece655e022
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1142908452 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_pinflip.1142908452
Directory /workspace/48.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/48.usbdev_phy_config_usb_ref_disable.3998446403
Short name T479
Test name
Test status
Simulation time 155087108 ps
CPU time 0.77 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206720 kb
Host smart-5d500e0e-38d4-4953-b7f3-79bc9f69a109
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39984
46403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_config_usb_ref_disable.3998446403
Directory /workspace/48.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/48.usbdev_phy_pins_sense.3342262502
Short name T1341
Test name
Test status
Simulation time 39961431 ps
CPU time 0.65 seconds
Started Jul 22 06:03:46 PM PDT 24
Finished Jul 22 06:03:47 PM PDT 24
Peak memory 206796 kb
Host smart-a616769c-0273-4bdf-ac4b-dc0803786042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33422
62502 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_phy_pins_sense.3342262502
Directory /workspace/48.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/48.usbdev_pkt_buffer.3887329374
Short name T2426
Test name
Test status
Simulation time 8226840934 ps
CPU time 16.73 seconds
Started Jul 22 06:03:38 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206964 kb
Host smart-4bc4fef7-325f-43e2-a023-40f18adc0d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38873
29374 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_buffer.3887329374
Directory /workspace/48.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/48.usbdev_pkt_received.71561366
Short name T1319
Test name
Test status
Simulation time 177449917 ps
CPU time 0.84 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206740 kb
Host smart-5f402a61-63e9-49aa-b622-519ab4ea5221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71561
366 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_received.71561366
Directory /workspace/48.usbdev_pkt_received/latest

Test location /workspace/coverage/default/48.usbdev_pkt_sent.1978171108
Short name T2244
Test name
Test status
Simulation time 210297082 ps
CPU time 0.92 seconds
Started Jul 22 06:03:36 PM PDT 24
Finished Jul 22 06:03:37 PM PDT 24
Peak memory 206864 kb
Host smart-b099a5b7-0943-43cb-9d7f-5d8ce59a7989
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19781
71108 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_pkt_sent.1978171108
Directory /workspace/48.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/48.usbdev_random_length_in_transaction.1018777252
Short name T2587
Test name
Test status
Simulation time 197825178 ps
CPU time 0.8 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:04:49 PM PDT 24
Peak memory 206696 kb
Host smart-99308614-07fb-418e-a0e7-e5279b7a5d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10187
77252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_in_transaction.1018777252
Directory /workspace/48.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/48.usbdev_random_length_out_transaction.3964288279
Short name T2741
Test name
Test status
Simulation time 170604605 ps
CPU time 0.81 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206684 kb
Host smart-a7aaeeb8-ba60-4f9d-a822-968720a0c3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39642
88279 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_random_length_out_transaction.3964288279
Directory /workspace/48.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/48.usbdev_rx_crc_err.458078859
Short name T1832
Test name
Test status
Simulation time 204667988 ps
CPU time 0.82 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206700 kb
Host smart-6f8ceb86-3313-440c-b5ba-c02f7eb2f004
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45807
8859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_rx_crc_err.458078859
Directory /workspace/48.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/48.usbdev_setup_stage.3284220784
Short name T1794
Test name
Test status
Simulation time 192284604 ps
CPU time 0.92 seconds
Started Jul 22 06:03:40 PM PDT 24
Finished Jul 22 06:03:42 PM PDT 24
Peak memory 206704 kb
Host smart-9e70f574-bcf4-4eed-a6aa-e88ef43ddd08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32842
20784 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_stage.3284220784
Directory /workspace/48.usbdev_setup_stage/latest

Test location /workspace/coverage/default/48.usbdev_setup_trans_ignored.2175459832
Short name T975
Test name
Test status
Simulation time 177386183 ps
CPU time 0.84 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206700 kb
Host smart-79b60593-2166-435b-bbb2-128a2b398528
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21754
59832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_setup_trans_ignored.2175459832
Directory /workspace/48.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/48.usbdev_smoke.2398863544
Short name T1638
Test name
Test status
Simulation time 245347382 ps
CPU time 0.94 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:51 PM PDT 24
Peak memory 206704 kb
Host smart-2bcff66e-f4f9-483d-8b45-a0860279e0fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23988
63544 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_smoke.2398863544
Directory /workspace/48.usbdev_smoke/latest

Test location /workspace/coverage/default/48.usbdev_spurious_pids_ignored.267820936
Short name T1488
Test name
Test status
Simulation time 6597116181 ps
CPU time 170.35 seconds
Started Jul 22 06:03:44 PM PDT 24
Finished Jul 22 06:06:35 PM PDT 24
Peak memory 206872 kb
Host smart-e88f5818-a0b8-4b3c-a3d7-133ebeb6526b
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=267820936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_spurious_pids_ignored.267820936
Directory /workspace/48.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/48.usbdev_stall_priority_over_nak.3976494929
Short name T274
Test name
Test status
Simulation time 172801562 ps
CPU time 0.84 seconds
Started Jul 22 06:03:50 PM PDT 24
Finished Jul 22 06:03:52 PM PDT 24
Peak memory 206700 kb
Host smart-fcef7398-a967-4cf2-9c64-f8f85274b12f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39764
94929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_priority_over_nak.3976494929
Directory /workspace/48.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/48.usbdev_stall_trans.4075463110
Short name T1975
Test name
Test status
Simulation time 175095197 ps
CPU time 0.84 seconds
Started Jul 22 06:03:37 PM PDT 24
Finished Jul 22 06:03:38 PM PDT 24
Peak memory 206736 kb
Host smart-4d34c05e-9829-4386-9e64-2a7d8a08ebff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40754
63110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stall_trans.4075463110
Directory /workspace/48.usbdev_stall_trans/latest

Test location /workspace/coverage/default/48.usbdev_stream_len_max.2550799848
Short name T332
Test name
Test status
Simulation time 482346669 ps
CPU time 1.21 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206736 kb
Host smart-6e4414a3-d47a-411a-9de0-5d7252db2eb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25507
99848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_stream_len_max.2550799848
Directory /workspace/48.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/48.usbdev_streaming_out.544586709
Short name T1755
Test name
Test status
Simulation time 5359326790 ps
CPU time 139.14 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:06:09 PM PDT 24
Peak memory 206884 kb
Host smart-b06e2da5-ec8a-476c-a67a-1db1105a1e28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54458
6709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.usbdev_streaming_out.544586709
Directory /workspace/48.usbdev_streaming_out/latest

Test location /workspace/coverage/default/49.usbdev_alert_test.3532693134
Short name T1872
Test name
Test status
Simulation time 43993941 ps
CPU time 0.67 seconds
Started Jul 22 06:03:58 PM PDT 24
Finished Jul 22 06:03:59 PM PDT 24
Peak memory 206612 kb
Host smart-7a62b254-1324-4a7a-bcc4-696101dd8dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3532693134 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_alert_test.3532693134
Directory /workspace/49.usbdev_alert_test/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_disconnect.1711579265
Short name T222
Test name
Test status
Simulation time 4222969579 ps
CPU time 5.76 seconds
Started Jul 22 06:03:49 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206896 kb
Host smart-212ad155-ae74-4106-b40d-7046a6ae0a48
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1711579265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_disconnect.1711579265
Directory /workspace/49.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_reset.1249430024
Short name T2705
Test name
Test status
Simulation time 13380177374 ps
CPU time 12.24 seconds
Started Jul 22 06:03:49 PM PDT 24
Finished Jul 22 06:04:02 PM PDT 24
Peak memory 206840 kb
Host smart-fc48cd03-d6c5-467c-ad07-13ead292ff19
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1249430024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_reset.1249430024
Directory /workspace/49.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/49.usbdev_aon_wake_resume.1627028867
Short name T1260
Test name
Test status
Simulation time 23361184531 ps
CPU time 24.29 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 206804 kb
Host smart-2f4d204d-b13c-4c70-b7b7-3c1a8fefa6f4
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1627028867 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_aon_wake_resume.1627028867
Directory /workspace/49.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/49.usbdev_av_buffer.1418017463
Short name T2483
Test name
Test status
Simulation time 157364302 ps
CPU time 0.8 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206732 kb
Host smart-5eec6de4-7f7f-48a4-9a7a-99c8f0003c21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14180
17463 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_av_buffer.1418017463
Directory /workspace/49.usbdev_av_buffer/latest

Test location /workspace/coverage/default/49.usbdev_bitstuff_err.1500298748
Short name T1829
Test name
Test status
Simulation time 153758425 ps
CPU time 0.76 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:03:48 PM PDT 24
Peak memory 206700 kb
Host smart-0e40b300-e96a-40a6-974d-d7a3b864b882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15002
98748 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_bitstuff_err.1500298748
Directory /workspace/49.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_clear.4217580289
Short name T1831
Test name
Test status
Simulation time 444504127 ps
CPU time 1.33 seconds
Started Jul 22 06:04:48 PM PDT 24
Finished Jul 22 06:04:50 PM PDT 24
Peak memory 206640 kb
Host smart-8b685fc4-ebd2-428d-ab77-d5d4ff731e77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42175
80289 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_clear.4217580289
Directory /workspace/49.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/49.usbdev_data_toggle_restore.246735751
Short name T1408
Test name
Test status
Simulation time 1087406687 ps
CPU time 2.39 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206804 kb
Host smart-0a4c9806-181f-4154-af3e-146315acbc2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24673
5751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_data_toggle_restore.246735751
Directory /workspace/49.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/49.usbdev_device_address.968317235
Short name T2125
Test name
Test status
Simulation time 13232382770 ps
CPU time 24.45 seconds
Started Jul 22 06:03:47 PM PDT 24
Finished Jul 22 06:04:12 PM PDT 24
Peak memory 206936 kb
Host smart-2fb6da7e-b806-4eff-bf9e-bb08d2aa367c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96831
7235 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_device_address.968317235
Directory /workspace/49.usbdev_device_address/latest

Test location /workspace/coverage/default/49.usbdev_disable_endpoint.3935956041
Short name T2727
Test name
Test status
Simulation time 368011525 ps
CPU time 1.26 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 206724 kb
Host smart-12528a9c-c090-441d-a471-0af896608352
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39359
56041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disable_endpoint.3935956041
Directory /workspace/49.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/49.usbdev_disconnected.1209921125
Short name T553
Test name
Test status
Simulation time 147783275 ps
CPU time 0.81 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:49 PM PDT 24
Peak memory 206736 kb
Host smart-450cbf93-ab7a-4ecd-955e-ca2b5e14fc05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12099
21125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_disconnected.1209921125
Directory /workspace/49.usbdev_disconnected/latest

Test location /workspace/coverage/default/49.usbdev_enable.2025209636
Short name T1257
Test name
Test status
Simulation time 68613917 ps
CPU time 0.7 seconds
Started Jul 22 06:03:48 PM PDT 24
Finished Jul 22 06:03:50 PM PDT 24
Peak memory 206692 kb
Host smart-c3218037-54c6-4637-80fd-639e7c7eb91b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20252
09636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_enable.2025209636
Directory /workspace/49.usbdev_enable/latest

Test location /workspace/coverage/default/49.usbdev_endpoint_access.647001717
Short name T971
Test name
Test status
Simulation time 909042206 ps
CPU time 1.98 seconds
Started Jul 22 06:03:49 PM PDT 24
Finished Jul 22 06:03:52 PM PDT 24
Peak memory 206796 kb
Host smart-b680f93e-e57d-4ef0-b46f-7e30feb06804
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64700
1717 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_endpoint_access.647001717
Directory /workspace/49.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/49.usbdev_fifo_rst.1691678360
Short name T2382
Test name
Test status
Simulation time 307164387 ps
CPU time 1.66 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206836 kb
Host smart-f30c21fe-c19f-4a29-bf72-70fc0e353f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16916
78360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_fifo_rst.1691678360
Directory /workspace/49.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/49.usbdev_in_iso.2587480087
Short name T2112
Test name
Test status
Simulation time 164533301 ps
CPU time 0.84 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206748 kb
Host smart-bb4857f9-a74b-4912-98e5-89a91d057dcd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25874
80087 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_iso.2587480087
Directory /workspace/49.usbdev_in_iso/latest

Test location /workspace/coverage/default/49.usbdev_in_stall.1738666904
Short name T444
Test name
Test status
Simulation time 154702182 ps
CPU time 0.77 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206740 kb
Host smart-99798445-6f77-4085-889e-2bf2c3ffd7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17386
66904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_stall.1738666904
Directory /workspace/49.usbdev_in_stall/latest

Test location /workspace/coverage/default/49.usbdev_in_trans.750084379
Short name T1429
Test name
Test status
Simulation time 198753066 ps
CPU time 0.82 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206752 kb
Host smart-78b3bfb5-7d23-4dd6-b9d5-6b102bd6dc5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75008
4379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_in_trans.750084379
Directory /workspace/49.usbdev_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_iso_retraction.1549213593
Short name T2164
Test name
Test status
Simulation time 3431164748 ps
CPU time 27.97 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:04:20 PM PDT 24
Peak memory 207000 kb
Host smart-a4f4f9ae-b683-4ee8-9783-1eb779902e1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15492
13593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_iso_retraction.1549213593
Directory /workspace/49.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/49.usbdev_link_in_err.1984977156
Short name T33
Test name
Test status
Simulation time 190598715 ps
CPU time 0.82 seconds
Started Jul 22 06:04:22 PM PDT 24
Finished Jul 22 06:04:23 PM PDT 24
Peak memory 206744 kb
Host smart-bb519a48-4d59-42b8-bc14-3c49702c62df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19849
77156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_in_err.1984977156
Directory /workspace/49.usbdev_link_in_err/latest

Test location /workspace/coverage/default/49.usbdev_link_resume.4174794178
Short name T187
Test name
Test status
Simulation time 23351804961 ps
CPU time 29.47 seconds
Started Jul 22 06:04:17 PM PDT 24
Finished Jul 22 06:04:48 PM PDT 24
Peak memory 206772 kb
Host smart-96109675-cb44-4158-ae85-bd858143452d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41747
94178 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_resume.4174794178
Directory /workspace/49.usbdev_link_resume/latest

Test location /workspace/coverage/default/49.usbdev_link_suspend.273630200
Short name T1802
Test name
Test status
Simulation time 3361098675 ps
CPU time 3.85 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206784 kb
Host smart-a48cac80-9785-4b08-9659-6cf525f1eb0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27363
0200 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_link_suspend.273630200
Directory /workspace/49.usbdev_link_suspend/latest

Test location /workspace/coverage/default/49.usbdev_low_speed_traffic.3679433679
Short name T1828
Test name
Test status
Simulation time 10211899326 ps
CPU time 278.42 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:08:31 PM PDT 24
Peak memory 206912 kb
Host smart-22c73026-3683-4374-9f07-a5a067d82e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36794
33679 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_low_speed_traffic.3679433679
Directory /workspace/49.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/49.usbdev_max_inter_pkt_delay.4240503503
Short name T1891
Test name
Test status
Simulation time 5042429142 ps
CPU time 136.9 seconds
Started Jul 22 06:03:49 PM PDT 24
Finished Jul 22 06:06:07 PM PDT 24
Peak memory 206800 kb
Host smart-c38cf846-7315-4627-a190-d8fea65484cb
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4240503503 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_inter_pkt_delay.4240503503
Directory /workspace/49.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_max_length_in_transaction.3898722240
Short name T2078
Test name
Test status
Simulation time 257890700 ps
CPU time 0.9 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206736 kb
Host smart-04d56ec1-f212-46b2-96b0-31f92b7f64a0
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3898722240 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_in_transaction.3898722240
Directory /workspace/49.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_length_out_transaction.3026130342
Short name T763
Test name
Test status
Simulation time 209790068 ps
CPU time 0.9 seconds
Started Jul 22 06:04:28 PM PDT 24
Finished Jul 22 06:04:29 PM PDT 24
Peak memory 206728 kb
Host smart-ccfb4460-1517-464d-a797-f733bac6ad1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30261
30342 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_length_out_transaction.3026130342
Directory /workspace/49.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_max_usb_traffic.2674152459
Short name T2711
Test name
Test status
Simulation time 4154469397 ps
CPU time 109.68 seconds
Started Jul 22 06:04:28 PM PDT 24
Finished Jul 22 06:06:18 PM PDT 24
Peak memory 206844 kb
Host smart-58407818-6371-48f7-8fd8-c780cf992b59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26741
52459 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_max_usb_traffic.2674152459
Directory /workspace/49.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/49.usbdev_min_inter_pkt_delay.963518152
Short name T1933
Test name
Test status
Simulation time 5428615408 ps
CPU time 51.31 seconds
Started Jul 22 06:03:56 PM PDT 24
Finished Jul 22 06:04:48 PM PDT 24
Peak memory 206940 kb
Host smart-a8fbfdb6-0423-491a-b1a0-acde3dd9f113
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=963518152 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_inter_pkt_delay.963518152
Directory /workspace/49.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/49.usbdev_min_length_in_transaction.1588700968
Short name T2208
Test name
Test status
Simulation time 171907201 ps
CPU time 0.8 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206752 kb
Host smart-a19e6725-b98c-449b-a239-02951ce1680e
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1588700968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_in_transaction.1588700968
Directory /workspace/49.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_min_length_out_transaction.1391081353
Short name T2130
Test name
Test status
Simulation time 143428179 ps
CPU time 0.76 seconds
Started Jul 22 06:03:53 PM PDT 24
Finished Jul 22 06:03:55 PM PDT 24
Peak memory 206668 kb
Host smart-2f960977-25a7-437f-8d39-420d151eddac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13910
81353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_min_length_out_transaction.1391081353
Directory /workspace/49.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_nak_trans.4237595612
Short name T136
Test name
Test status
Simulation time 195405970 ps
CPU time 0.86 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206736 kb
Host smart-f0ff2bb6-ee51-4e36-aace-bb18937be73b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42375
95612 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_nak_trans.4237595612
Directory /workspace/49.usbdev_nak_trans/latest

Test location /workspace/coverage/default/49.usbdev_out_iso.2367682453
Short name T532
Test name
Test status
Simulation time 236942558 ps
CPU time 0.88 seconds
Started Jul 22 06:03:50 PM PDT 24
Finished Jul 22 06:03:52 PM PDT 24
Peak memory 206740 kb
Host smart-6610d46f-be19-4b86-b61b-3fd54ea279c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23676
82453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_iso.2367682453
Directory /workspace/49.usbdev_out_iso/latest

Test location /workspace/coverage/default/49.usbdev_out_stall.1691042729
Short name T1454
Test name
Test status
Simulation time 150514266 ps
CPU time 0.86 seconds
Started Jul 22 06:03:58 PM PDT 24
Finished Jul 22 06:03:59 PM PDT 24
Peak memory 206756 kb
Host smart-204d04cd-d287-462e-812a-4d57e6b4df94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16910
42729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_stall.1691042729
Directory /workspace/49.usbdev_out_stall/latest

Test location /workspace/coverage/default/49.usbdev_out_trans_nak.3487161120
Short name T2518
Test name
Test status
Simulation time 155805029 ps
CPU time 0.84 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206736 kb
Host smart-a39ab501-b3b2-4ef9-8863-9d465e94d59f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34871
61120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_out_trans_nak.3487161120
Directory /workspace/49.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/49.usbdev_pending_in_trans.2433934113
Short name T1563
Test name
Test status
Simulation time 153595689 ps
CPU time 0.76 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206788 kb
Host smart-b96f4ecd-c6d9-451a-a4db-36103dda7e90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24339
34113 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pending_in_trans.2433934113
Directory /workspace/49.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_pinflip.3451254677
Short name T523
Test name
Test status
Simulation time 182389291 ps
CPU time 0.9 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 206772 kb
Host smart-284a31bc-bf19-4d94-9261-fd64bd37b54b
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3451254677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_pinflip.3451254677
Directory /workspace/49.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/49.usbdev_phy_config_usb_ref_disable.2980669630
Short name T1031
Test name
Test status
Simulation time 152516361 ps
CPU time 0.77 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:04:44 PM PDT 24
Peak memory 206732 kb
Host smart-bae3f5a5-e6e2-482e-83bb-117cabba31e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29806
69630 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_config_usb_ref_disable.2980669630
Directory /workspace/49.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/49.usbdev_phy_pins_sense.3692167735
Short name T839
Test name
Test status
Simulation time 38433899 ps
CPU time 0.66 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206628 kb
Host smart-7d3ff8fa-7ab8-4ebe-8431-8ed0a4c8e30f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36921
67735 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_phy_pins_sense.3692167735
Directory /workspace/49.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/49.usbdev_pkt_buffer.695990663
Short name T1827
Test name
Test status
Simulation time 17359698981 ps
CPU time 41.23 seconds
Started Jul 22 06:04:42 PM PDT 24
Finished Jul 22 06:05:24 PM PDT 24
Peak memory 206988 kb
Host smart-f9eb919f-d151-43fc-845d-292da07aae27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69599
0663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_buffer.695990663
Directory /workspace/49.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/49.usbdev_pkt_received.4051096431
Short name T1922
Test name
Test status
Simulation time 196020174 ps
CPU time 0.86 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206712 kb
Host smart-5b3d62a1-f235-4e32-89a9-1a13be4aca35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40510
96431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_received.4051096431
Directory /workspace/49.usbdev_pkt_received/latest

Test location /workspace/coverage/default/49.usbdev_pkt_sent.1408229661
Short name T557
Test name
Test status
Simulation time 200943451 ps
CPU time 0.82 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206740 kb
Host smart-b163d204-5016-462e-81f5-141795ad7f96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14082
29661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_pkt_sent.1408229661
Directory /workspace/49.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/49.usbdev_random_length_in_transaction.3162904082
Short name T1789
Test name
Test status
Simulation time 234382610 ps
CPU time 0.85 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206724 kb
Host smart-2b1c0bf0-4386-4f30-8f39-e615f82ceafd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31629
04082 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_in_transaction.3162904082
Directory /workspace/49.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/49.usbdev_random_length_out_transaction.712594026
Short name T1398
Test name
Test status
Simulation time 193612866 ps
CPU time 0.81 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206756 kb
Host smart-718cf9c2-108b-4ebe-a3e1-24d40c0cda3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71259
4026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_random_length_out_transaction.712594026
Directory /workspace/49.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/49.usbdev_rx_crc_err.312992529
Short name T960
Test name
Test status
Simulation time 146953078 ps
CPU time 0.76 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206736 kb
Host smart-c9976ac0-eea1-43f8-a477-244718da4276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31299
2529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_rx_crc_err.312992529
Directory /workspace/49.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/49.usbdev_setup_stage.2607731873
Short name T2044
Test name
Test status
Simulation time 146807542 ps
CPU time 0.75 seconds
Started Jul 22 06:03:52 PM PDT 24
Finished Jul 22 06:03:54 PM PDT 24
Peak memory 206752 kb
Host smart-f220e4b9-a1a3-4f63-b0f9-6cd6937ae1ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26077
31873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_stage.2607731873
Directory /workspace/49.usbdev_setup_stage/latest

Test location /workspace/coverage/default/49.usbdev_setup_trans_ignored.462084798
Short name T2134
Test name
Test status
Simulation time 150955986 ps
CPU time 0.77 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:52 PM PDT 24
Peak memory 206732 kb
Host smart-e6d3d14b-d810-4a84-8ee7-52c4e5562f1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46208
4798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_setup_trans_ignored.462084798
Directory /workspace/49.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/49.usbdev_smoke.4021008286
Short name T2257
Test name
Test status
Simulation time 191906823 ps
CPU time 0.9 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:03:57 PM PDT 24
Peak memory 206716 kb
Host smart-8648ece7-c5d8-4bd2-bd99-f1843abb1b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40210
08286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_smoke.4021008286
Directory /workspace/49.usbdev_smoke/latest

Test location /workspace/coverage/default/49.usbdev_spurious_pids_ignored.2250165432
Short name T2305
Test name
Test status
Simulation time 5517469800 ps
CPU time 154.15 seconds
Started Jul 22 06:03:55 PM PDT 24
Finished Jul 22 06:06:31 PM PDT 24
Peak memory 206856 kb
Host smart-5a7518af-0eb8-40af-acb7-6486708f9553
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2250165432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_spurious_pids_ignored.2250165432
Directory /workspace/49.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/49.usbdev_stall_priority_over_nak.795344705
Short name T1059
Test name
Test status
Simulation time 154724093 ps
CPU time 0.81 seconds
Started Jul 22 06:03:51 PM PDT 24
Finished Jul 22 06:03:53 PM PDT 24
Peak memory 206740 kb
Host smart-49259211-4a61-4278-a02e-a15e3bc32a8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79534
4705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_priority_over_nak.795344705
Directory /workspace/49.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/49.usbdev_stall_trans.1603637746
Short name T1482
Test name
Test status
Simulation time 202218973 ps
CPU time 0.9 seconds
Started Jul 22 06:03:54 PM PDT 24
Finished Jul 22 06:03:56 PM PDT 24
Peak memory 206740 kb
Host smart-5b6476c7-7623-4c81-8e9a-90aa9857fbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16036
37746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stall_trans.1603637746
Directory /workspace/49.usbdev_stall_trans/latest

Test location /workspace/coverage/default/49.usbdev_stream_len_max.3537675372
Short name T603
Test name
Test status
Simulation time 1402871427 ps
CPU time 3.16 seconds
Started Jul 22 06:04:16 PM PDT 24
Finished Jul 22 06:04:21 PM PDT 24
Peak memory 206880 kb
Host smart-90652300-5c63-4263-8613-9acb6a65bf99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35376
75372 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_stream_len_max.3537675372
Directory /workspace/49.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/49.usbdev_streaming_out.2107596234
Short name T756
Test name
Test status
Simulation time 5876174466 ps
CPU time 54.04 seconds
Started Jul 22 06:03:58 PM PDT 24
Finished Jul 22 06:04:52 PM PDT 24
Peak memory 206796 kb
Host smart-ec49c0f5-8729-406a-9de7-67fcc803dff8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21075
96234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.usbdev_streaming_out.2107596234
Directory /workspace/49.usbdev_streaming_out/latest

Test location /workspace/coverage/default/5.usbdev_alert_test.3195841324
Short name T1561
Test name
Test status
Simulation time 49132959 ps
CPU time 0.67 seconds
Started Jul 22 05:57:11 PM PDT 24
Finished Jul 22 05:57:12 PM PDT 24
Peak memory 206680 kb
Host smart-63fa6d89-5762-4710-ae35-860664f48de4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3195841324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_alert_test.3195841324
Directory /workspace/5.usbdev_alert_test/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_disconnect.3129348449
Short name T706
Test name
Test status
Simulation time 3975976830 ps
CPU time 4.8 seconds
Started Jul 22 05:56:56 PM PDT 24
Finished Jul 22 05:57:02 PM PDT 24
Peak memory 206896 kb
Host smart-022499af-7ead-4318-8f2c-81d0e87683a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3129348449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_disconnect.3129348449
Directory /workspace/5.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_reset.1234543826
Short name T1569
Test name
Test status
Simulation time 13286099511 ps
CPU time 16.32 seconds
Started Jul 22 05:57:01 PM PDT 24
Finished Jul 22 05:57:18 PM PDT 24
Peak memory 206908 kb
Host smart-305d3900-8661-48c8-98a6-c1d2a961b5b9
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1234543826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_reset.1234543826
Directory /workspace/5.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/5.usbdev_aon_wake_resume.3812528746
Short name T2085
Test name
Test status
Simulation time 23477762592 ps
CPU time 23.77 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 206772 kb
Host smart-2abf8c1e-3cda-4c08-ab6c-19c43f35564f
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3812528746 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_aon_wake_resume.3812528746
Directory /workspace/5.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/5.usbdev_av_buffer.3685604010
Short name T1663
Test name
Test status
Simulation time 156843458 ps
CPU time 0.9 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206752 kb
Host smart-6a1bdf23-9503-45dd-82ce-28523985807b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36856
04010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_av_buffer.3685604010
Directory /workspace/5.usbdev_av_buffer/latest

Test location /workspace/coverage/default/5.usbdev_bitstuff_err.947694408
Short name T1881
Test name
Test status
Simulation time 213424295 ps
CPU time 0.84 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206736 kb
Host smart-1c6b329f-9bc7-466a-9431-c2f6e3d7838c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94769
4408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_bitstuff_err.947694408
Directory /workspace/5.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_clear.3220360584
Short name T1609
Test name
Test status
Simulation time 143479483 ps
CPU time 0.79 seconds
Started Jul 22 05:57:05 PM PDT 24
Finished Jul 22 05:57:07 PM PDT 24
Peak memory 206740 kb
Host smart-4fd1fc9b-e966-4cd0-9911-ed68db3fada0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32203
60584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_clear.3220360584
Directory /workspace/5.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/5.usbdev_data_toggle_restore.494790106
Short name T366
Test name
Test status
Simulation time 333821753 ps
CPU time 1.09 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:05 PM PDT 24
Peak memory 206392 kb
Host smart-6f477fae-b7bd-49ba-9c85-09f97959821b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49479
0106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_data_toggle_restore.494790106
Directory /workspace/5.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/5.usbdev_device_address.3365926356
Short name T94
Test name
Test status
Simulation time 19711802776 ps
CPU time 36.49 seconds
Started Jul 22 05:57:01 PM PDT 24
Finished Jul 22 05:57:38 PM PDT 24
Peak memory 206904 kb
Host smart-3250d222-538d-4cad-959a-8711abdbfd26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33659
26356 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_device_address.3365926356
Directory /workspace/5.usbdev_device_address/latest

Test location /workspace/coverage/default/5.usbdev_disable_endpoint.1026649041
Short name T1122
Test name
Test status
Simulation time 393249493 ps
CPU time 1.3 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:12 PM PDT 24
Peak memory 206736 kb
Host smart-d926661b-bc92-4b8c-9537-9f28ada53373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10266
49041 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disable_endpoint.1026649041
Directory /workspace/5.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/5.usbdev_disconnected.1243449132
Short name T529
Test name
Test status
Simulation time 148537603 ps
CPU time 0.78 seconds
Started Jul 22 05:57:01 PM PDT 24
Finished Jul 22 05:57:02 PM PDT 24
Peak memory 206664 kb
Host smart-5e824bbd-538b-4669-a053-129ea524bb01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12434
49132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_disconnected.1243449132
Directory /workspace/5.usbdev_disconnected/latest

Test location /workspace/coverage/default/5.usbdev_enable.2941768222
Short name T2469
Test name
Test status
Simulation time 44536901 ps
CPU time 0.67 seconds
Started Jul 22 05:57:07 PM PDT 24
Finished Jul 22 05:57:08 PM PDT 24
Peak memory 206712 kb
Host smart-6741f27f-6b67-45cb-a59d-5523841cb876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417
68222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_enable.2941768222
Directory /workspace/5.usbdev_enable/latest

Test location /workspace/coverage/default/5.usbdev_endpoint_access.1651453025
Short name T1686
Test name
Test status
Simulation time 1023777610 ps
CPU time 2.43 seconds
Started Jul 22 05:57:05 PM PDT 24
Finished Jul 22 05:57:09 PM PDT 24
Peak memory 206896 kb
Host smart-37b98207-3ea4-420b-819a-10680eb02b13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16514
53025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_endpoint_access.1651453025
Directory /workspace/5.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/5.usbdev_fifo_rst.1546183820
Short name T2446
Test name
Test status
Simulation time 387010978 ps
CPU time 2.28 seconds
Started Jul 22 05:57:00 PM PDT 24
Finished Jul 22 05:57:03 PM PDT 24
Peak memory 206852 kb
Host smart-48863691-3242-4adf-870b-8665a09a8f2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15461
83820 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_fifo_rst.1546183820
Directory /workspace/5.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/5.usbdev_in_iso.3371382654
Short name T1477
Test name
Test status
Simulation time 228542725 ps
CPU time 0.88 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:04 PM PDT 24
Peak memory 206740 kb
Host smart-aeca1744-715f-429a-bcc1-cfcf4a601129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33713
82654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_iso.3371382654
Directory /workspace/5.usbdev_in_iso/latest

Test location /workspace/coverage/default/5.usbdev_in_stall.351858813
Short name T2209
Test name
Test status
Simulation time 153113407 ps
CPU time 0.77 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:07 PM PDT 24
Peak memory 206668 kb
Host smart-a5364d4f-2c8c-4291-befc-31c3f4a3f892
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35185
8813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_stall.351858813
Directory /workspace/5.usbdev_in_stall/latest

Test location /workspace/coverage/default/5.usbdev_in_trans.3253897466
Short name T629
Test name
Test status
Simulation time 170274711 ps
CPU time 0.89 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:04 PM PDT 24
Peak memory 206752 kb
Host smart-0a1bb6fb-b208-4b50-8253-452e201aae3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32538
97466 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_in_trans.3253897466
Directory /workspace/5.usbdev_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_invalid_sync.1011038920
Short name T1720
Test name
Test status
Simulation time 5870865938 ps
CPU time 55.29 seconds
Started Jul 22 05:57:01 PM PDT 24
Finished Jul 22 05:57:57 PM PDT 24
Peak memory 206840 kb
Host smart-87378ad9-6a9c-469e-983b-b139027ec222
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1011038920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_invalid_sync.1011038920
Directory /workspace/5.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/5.usbdev_iso_retraction.3830787454
Short name T1984
Test name
Test status
Simulation time 11375538193 ps
CPU time 89.66 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206848 kb
Host smart-1690c185-6283-4c5b-8ee0-68332f096813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38307
87454 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_iso_retraction.3830787454
Directory /workspace/5.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/5.usbdev_link_in_err.1867650079
Short name T2200
Test name
Test status
Simulation time 199093400 ps
CPU time 0.9 seconds
Started Jul 22 05:57:07 PM PDT 24
Finished Jul 22 05:57:08 PM PDT 24
Peak memory 206724 kb
Host smart-cdf82ff4-3399-480e-9573-a8bdaf5437b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18676
50079 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_in_err.1867650079
Directory /workspace/5.usbdev_link_in_err/latest

Test location /workspace/coverage/default/5.usbdev_link_resume.1642981524
Short name T1562
Test name
Test status
Simulation time 23304132923 ps
CPU time 22.46 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:27 PM PDT 24
Peak memory 206796 kb
Host smart-f1f813ad-5b41-413c-8e1a-0ad14de0e973
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16429
81524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_resume.1642981524
Directory /workspace/5.usbdev_link_resume/latest

Test location /workspace/coverage/default/5.usbdev_link_suspend.1747540265
Short name T1817
Test name
Test status
Simulation time 3284478709 ps
CPU time 3.75 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:10 PM PDT 24
Peak memory 206772 kb
Host smart-8fce38ed-53ed-4ca1-894f-0a9f8c33a303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17475
40265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_link_suspend.1747540265
Directory /workspace/5.usbdev_link_suspend/latest

Test location /workspace/coverage/default/5.usbdev_low_speed_traffic.1971555110
Short name T2050
Test name
Test status
Simulation time 5514962017 ps
CPU time 156.37 seconds
Started Jul 22 05:57:05 PM PDT 24
Finished Jul 22 05:59:43 PM PDT 24
Peak memory 206940 kb
Host smart-2390b09e-6612-42fd-ba3e-e1cac2f934db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19715
55110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_low_speed_traffic.1971555110
Directory /workspace/5.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/5.usbdev_max_inter_pkt_delay.2396352663
Short name T2127
Test name
Test status
Simulation time 5577814635 ps
CPU time 166.99 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:59:51 PM PDT 24
Peak memory 206928 kb
Host smart-381854ff-d1c8-4296-8915-3b2d14d9d041
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2396352663 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_inter_pkt_delay.2396352663
Directory /workspace/5.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_max_length_in_transaction.3756718843
Short name T2522
Test name
Test status
Simulation time 244026522 ps
CPU time 0.88 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:03 PM PDT 24
Peak memory 206752 kb
Host smart-37cf48c8-58a9-4daa-9456-912cf945eb8b
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3756718843 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_in_transaction.3756718843
Directory /workspace/5.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_length_out_transaction.1444057709
Short name T1723
Test name
Test status
Simulation time 193546451 ps
CPU time 0.93 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206748 kb
Host smart-03880650-d7a7-4053-86f7-c56ef394b6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14440
57709 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_length_out_transaction.1444057709
Directory /workspace/5.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_max_usb_traffic.565652237
Short name T1152
Test name
Test status
Simulation time 4374081013 ps
CPU time 40.41 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206872 kb
Host smart-5d826ca2-60f9-423e-9456-db0792ae2e99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56565
2237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_max_usb_traffic.565652237
Directory /workspace/5.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/5.usbdev_min_inter_pkt_delay.1262190179
Short name T1224
Test name
Test status
Simulation time 5658342354 ps
CPU time 49.35 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:55 PM PDT 24
Peak memory 206792 kb
Host smart-77095ae3-ea9a-4893-ba2a-a842db7f7221
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=1262190179 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_inter_pkt_delay.1262190179
Directory /workspace/5.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/5.usbdev_min_length_in_transaction.2717219619
Short name T848
Test name
Test status
Simulation time 176157385 ps
CPU time 0.95 seconds
Started Jul 22 05:57:01 PM PDT 24
Finished Jul 22 05:57:03 PM PDT 24
Peak memory 206708 kb
Host smart-a9dddca4-b2ce-45f8-8c14-2b1b86251ca9
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2717219619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_in_transaction.2717219619
Directory /workspace/5.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_min_length_out_transaction.1395888759
Short name T1712
Test name
Test status
Simulation time 141580986 ps
CPU time 0.79 seconds
Started Jul 22 05:57:03 PM PDT 24
Finished Jul 22 05:57:05 PM PDT 24
Peak memory 206512 kb
Host smart-a4f7bfd3-cedf-4bb2-9105-123ddaf92e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13958
88759 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_min_length_out_transaction.1395888759
Directory /workspace/5.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_nak_trans.686118859
Short name T137
Test name
Test status
Simulation time 188738550 ps
CPU time 0.86 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:06 PM PDT 24
Peak memory 206736 kb
Host smart-d68c3d26-c682-40e8-903a-5f9291ce4b28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68611
8859 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_nak_trans.686118859
Directory /workspace/5.usbdev_nak_trans/latest

Test location /workspace/coverage/default/5.usbdev_out_iso.3367029195
Short name T554
Test name
Test status
Simulation time 178739969 ps
CPU time 0.88 seconds
Started Jul 22 05:57:07 PM PDT 24
Finished Jul 22 05:57:08 PM PDT 24
Peak memory 206744 kb
Host smart-e35de985-12db-4bb7-bcee-bd9e580fcd24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33670
29195 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_iso.3367029195
Directory /workspace/5.usbdev_out_iso/latest

Test location /workspace/coverage/default/5.usbdev_out_stall.2536129582
Short name T2353
Test name
Test status
Simulation time 182711038 ps
CPU time 0.8 seconds
Started Jul 22 05:57:06 PM PDT 24
Finished Jul 22 05:57:08 PM PDT 24
Peak memory 206712 kb
Host smart-d8f329db-e334-490d-9510-13e311fe5196
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25361
29582 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_stall.2536129582
Directory /workspace/5.usbdev_out_stall/latest

Test location /workspace/coverage/default/5.usbdev_out_trans_nak.3174420494
Short name T2715
Test name
Test status
Simulation time 208968751 ps
CPU time 0.81 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:04 PM PDT 24
Peak memory 206708 kb
Host smart-d02a3f49-b51a-430c-9134-fbb9dd28deec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31744
20494 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_out_trans_nak.3174420494
Directory /workspace/5.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/5.usbdev_pending_in_trans.1403480184
Short name T1621
Test name
Test status
Simulation time 148288060 ps
CPU time 0.76 seconds
Started Jul 22 05:57:05 PM PDT 24
Finished Jul 22 05:57:07 PM PDT 24
Peak memory 206752 kb
Host smart-bf328ce8-3f11-4ce9-ba91-537d376a3022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034
80184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pending_in_trans.1403480184
Directory /workspace/5.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_pinflip.3633705094
Short name T1589
Test name
Test status
Simulation time 248838229 ps
CPU time 1.04 seconds
Started Jul 22 05:57:05 PM PDT 24
Finished Jul 22 05:57:07 PM PDT 24
Peak memory 206704 kb
Host smart-22ffa23e-7e1b-4d14-b93f-520d912d913a
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3633705094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_pinflip.3633705094
Directory /workspace/5.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/5.usbdev_phy_config_usb_ref_disable.295225899
Short name T1724
Test name
Test status
Simulation time 143367659 ps
CPU time 0.75 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:03 PM PDT 24
Peak memory 206752 kb
Host smart-1863c0da-3ac7-40c6-9657-c9201349a70a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29522
5899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_config_usb_ref_disable.295225899
Directory /workspace/5.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/5.usbdev_phy_pins_sense.980487947
Short name T2370
Test name
Test status
Simulation time 40702335 ps
CPU time 0.67 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:04 PM PDT 24
Peak memory 206684 kb
Host smart-93020806-e5e9-44a2-a69e-a411bd61677e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98048
7947 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_phy_pins_sense.980487947
Directory /workspace/5.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/5.usbdev_pkt_buffer.3943547129
Short name T2117
Test name
Test status
Simulation time 16211105930 ps
CPU time 34.4 seconds
Started Jul 22 05:57:07 PM PDT 24
Finished Jul 22 05:57:42 PM PDT 24
Peak memory 206904 kb
Host smart-027f014c-eb39-4b14-adc8-3d6c4943a050
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39435
47129 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_buffer.3943547129
Directory /workspace/5.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/5.usbdev_pkt_received.2158136740
Short name T2289
Test name
Test status
Simulation time 163500718 ps
CPU time 0.84 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 206772 kb
Host smart-56dff2c5-1212-4700-a2bb-c68d1f5b40e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21581
36740 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_received.2158136740
Directory /workspace/5.usbdev_pkt_received/latest

Test location /workspace/coverage/default/5.usbdev_pkt_sent.3272133757
Short name T419
Test name
Test status
Simulation time 199709881 ps
CPU time 0.9 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:08 PM PDT 24
Peak memory 206772 kb
Host smart-e8ef4701-ffd2-4531-a639-3e288041a72f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32721
33757 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_pkt_sent.3272133757
Directory /workspace/5.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_disconnects.1770791148
Short name T209
Test name
Test status
Simulation time 11768086352 ps
CPU time 218.73 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 06:00:43 PM PDT 24
Peak memory 206912 kb
Host smart-4b080354-863c-4ce3-9382-23eb4e7c62a3
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1770791148 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_disconnects.1770791148
Directory /workspace/5.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/5.usbdev_rand_bus_resets.4016180799
Short name T567
Test name
Test status
Simulation time 5098248144 ps
CPU time 41.73 seconds
Started Jul 22 05:57:05 PM PDT 24
Finished Jul 22 05:57:49 PM PDT 24
Peak memory 206908 kb
Host smart-a3ec0ae4-5120-4eb2-a274-20c737b32fb7
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4016180799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_bus_resets.4016180799
Directory /workspace/5.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/5.usbdev_rand_suspends.3592268929
Short name T1016
Test name
Test status
Simulation time 13765269929 ps
CPU time 72.76 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206820 kb
Host smart-b7817b66-4e06-4940-9e05-4325e072e610
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3592268929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rand_suspends.3592268929
Directory /workspace/5.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/5.usbdev_random_length_in_transaction.3751221928
Short name T732
Test name
Test status
Simulation time 153465571 ps
CPU time 0.79 seconds
Started Jul 22 05:57:02 PM PDT 24
Finished Jul 22 05:57:04 PM PDT 24
Peak memory 206752 kb
Host smart-f29e50f1-995c-40be-aaad-05dc4f945ff9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37512
21928 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_in_transaction.3751221928
Directory /workspace/5.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/5.usbdev_random_length_out_transaction.4223322190
Short name T788
Test name
Test status
Simulation time 228492141 ps
CPU time 0.9 seconds
Started Jul 22 05:57:04 PM PDT 24
Finished Jul 22 05:57:07 PM PDT 24
Peak memory 206736 kb
Host smart-6b6cc986-ecac-43f1-9db8-66112e324d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42233
22190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_random_length_out_transaction.4223322190
Directory /workspace/5.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/5.usbdev_rx_crc_err.4267250049
Short name T772
Test name
Test status
Simulation time 222793457 ps
CPU time 0.84 seconds
Started Jul 22 05:57:06 PM PDT 24
Finished Jul 22 05:57:08 PM PDT 24
Peak memory 206748 kb
Host smart-a899b494-bf34-4b9c-af8a-be33e9553e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42672
50049 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_rx_crc_err.4267250049
Directory /workspace/5.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/5.usbdev_setup_stage.2957683934
Short name T673
Test name
Test status
Simulation time 201843373 ps
CPU time 0.83 seconds
Started Jul 22 05:57:11 PM PDT 24
Finished Jul 22 05:57:12 PM PDT 24
Peak memory 206736 kb
Host smart-fd44c950-6593-41da-a885-01470781a468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29576
83934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_stage.2957683934
Directory /workspace/5.usbdev_setup_stage/latest

Test location /workspace/coverage/default/5.usbdev_setup_trans_ignored.1518095882
Short name T2549
Test name
Test status
Simulation time 152976330 ps
CPU time 0.83 seconds
Started Jul 22 05:57:09 PM PDT 24
Finished Jul 22 05:57:11 PM PDT 24
Peak memory 206860 kb
Host smart-013ea616-cee6-4894-8ef5-4caa1618efa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15180
95882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_setup_trans_ignored.1518095882
Directory /workspace/5.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/5.usbdev_smoke.3876298283
Short name T2218
Test name
Test status
Simulation time 246358549 ps
CPU time 0.97 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:11 PM PDT 24
Peak memory 206624 kb
Host smart-8fff1f34-7720-40c5-8a00-6ceca4fb9f10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38762
98283 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_smoke.3876298283
Directory /workspace/5.usbdev_smoke/latest

Test location /workspace/coverage/default/5.usbdev_spurious_pids_ignored.672688958
Short name T2131
Test name
Test status
Simulation time 5667116298 ps
CPU time 52.7 seconds
Started Jul 22 05:57:13 PM PDT 24
Finished Jul 22 05:58:06 PM PDT 24
Peak memory 206912 kb
Host smart-67b4a76f-665d-4b4e-99f3-a18e795e8acd
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=672688958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_spurious_pids_ignored.672688958
Directory /workspace/5.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/5.usbdev_stall_priority_over_nak.3935962871
Short name T1421
Test name
Test status
Simulation time 164358507 ps
CPU time 0.79 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:11 PM PDT 24
Peak memory 206736 kb
Host smart-d08460d3-dd74-4c37-8283-a69ce6c8cd5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39359
62871 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_priority_over_nak.3935962871
Directory /workspace/5.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/5.usbdev_stall_trans.1771885403
Short name T1801
Test name
Test status
Simulation time 202012133 ps
CPU time 0.84 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:12 PM PDT 24
Peak memory 206724 kb
Host smart-371f0c5b-28ce-438f-926c-b645f162ea91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17718
85403 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stall_trans.1771885403
Directory /workspace/5.usbdev_stall_trans/latest

Test location /workspace/coverage/default/5.usbdev_stream_len_max.2001340435
Short name T1858
Test name
Test status
Simulation time 306469860 ps
CPU time 0.97 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:12 PM PDT 24
Peak memory 206680 kb
Host smart-dcff18de-3a7f-473f-be5f-0c54506b7c5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20013
40435 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_stream_len_max.2001340435
Directory /workspace/5.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/5.usbdev_streaming_out.84352960
Short name T1342
Test name
Test status
Simulation time 4572979340 ps
CPU time 34.08 seconds
Started Jul 22 05:57:09 PM PDT 24
Finished Jul 22 05:57:43 PM PDT 24
Peak memory 206888 kb
Host smart-ee2e10fa-1b84-4714-9ba3-dff61bf0ed6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84352
960 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.usbdev_streaming_out.84352960
Directory /workspace/5.usbdev_streaming_out/latest

Test location /workspace/coverage/default/6.usbdev_alert_test.1379575999
Short name T1883
Test name
Test status
Simulation time 53262081 ps
CPU time 0.66 seconds
Started Jul 22 05:57:17 PM PDT 24
Finished Jul 22 05:57:18 PM PDT 24
Peak memory 206768 kb
Host smart-f1b36cac-050a-4054-a182-c84914de46d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1379575999 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_alert_test.1379575999
Directory /workspace/6.usbdev_alert_test/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_disconnect.3570116010
Short name T2154
Test name
Test status
Simulation time 4126216574 ps
CPU time 5.61 seconds
Started Jul 22 05:57:12 PM PDT 24
Finished Jul 22 05:57:19 PM PDT 24
Peak memory 206796 kb
Host smart-e3d187e1-6f31-4a1d-9e32-955529379633
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3570116010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_disconnect.3570116010
Directory /workspace/6.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_reset.692656722
Short name T2230
Test name
Test status
Simulation time 13313958924 ps
CPU time 12.26 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:23 PM PDT 24
Peak memory 206720 kb
Host smart-ab9aa53c-6804-4776-a468-bc65ded88a87
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=692656722 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_reset.692656722
Directory /workspace/6.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/6.usbdev_aon_wake_resume.3121848117
Short name T2648
Test name
Test status
Simulation time 23387647029 ps
CPU time 23.95 seconds
Started Jul 22 05:57:08 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206796 kb
Host smart-e482ebb3-92bd-44f9-b9b6-1e04ee8ed193
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3121848117 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_aon_wake_resume.3121848117
Directory /workspace/6.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/6.usbdev_av_buffer.3801058392
Short name T1107
Test name
Test status
Simulation time 155475336 ps
CPU time 0.79 seconds
Started Jul 22 05:57:13 PM PDT 24
Finished Jul 22 05:57:14 PM PDT 24
Peak memory 206704 kb
Host smart-480d4ce0-7e30-4ded-8976-0d14e093e317
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38010
58392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_av_buffer.3801058392
Directory /workspace/6.usbdev_av_buffer/latest

Test location /workspace/coverage/default/6.usbdev_bitstuff_err.4215321392
Short name T2119
Test name
Test status
Simulation time 160834300 ps
CPU time 0.79 seconds
Started Jul 22 05:57:14 PM PDT 24
Finished Jul 22 05:57:15 PM PDT 24
Peak memory 206748 kb
Host smart-52e15ec2-336c-4609-9318-eb164c0a0444
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42153
21392 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_bitstuff_err.4215321392
Directory /workspace/6.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_clear.1588933184
Short name T2453
Test name
Test status
Simulation time 205634726 ps
CPU time 0.94 seconds
Started Jul 22 05:57:13 PM PDT 24
Finished Jul 22 05:57:15 PM PDT 24
Peak memory 206752 kb
Host smart-73b29d91-ab39-436b-bfb7-083c328d2d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15889
33184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_clear.1588933184
Directory /workspace/6.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/6.usbdev_data_toggle_restore.2450822156
Short name T724
Test name
Test status
Simulation time 985624954 ps
CPU time 2.28 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:13 PM PDT 24
Peak memory 206888 kb
Host smart-92efabc1-0314-4102-afdf-3652c0aca8f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24508
22156 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_data_toggle_restore.2450822156
Directory /workspace/6.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/6.usbdev_device_address.1762969986
Short name T664
Test name
Test status
Simulation time 12784230607 ps
CPU time 22.35 seconds
Started Jul 22 05:57:09 PM PDT 24
Finished Jul 22 05:57:32 PM PDT 24
Peak memory 206968 kb
Host smart-029f91a2-3ac8-4484-a46e-67b2589e231a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17629
69986 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_device_address.1762969986
Directory /workspace/6.usbdev_device_address/latest

Test location /workspace/coverage/default/6.usbdev_disable_endpoint.2006502202
Short name T2605
Test name
Test status
Simulation time 450870151 ps
CPU time 1.38 seconds
Started Jul 22 05:57:12 PM PDT 24
Finished Jul 22 05:57:14 PM PDT 24
Peak memory 206748 kb
Host smart-d667c9c4-6a43-40e0-94d7-a1a107a07e8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20065
02202 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disable_endpoint.2006502202
Directory /workspace/6.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/6.usbdev_disconnected.4164979292
Short name T1537
Test name
Test status
Simulation time 153633694 ps
CPU time 0.79 seconds
Started Jul 22 05:57:13 PM PDT 24
Finished Jul 22 05:57:14 PM PDT 24
Peak memory 206704 kb
Host smart-c331e7cd-cc26-4ac6-81ef-f510c7371082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41649
79292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_disconnected.4164979292
Directory /workspace/6.usbdev_disconnected/latest

Test location /workspace/coverage/default/6.usbdev_enable.38222716
Short name T2017
Test name
Test status
Simulation time 44172817 ps
CPU time 0.67 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:11 PM PDT 24
Peak memory 206672 kb
Host smart-da8d2e6d-6c59-4572-99bf-7259d13d27b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38222
716 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_enable.38222716
Directory /workspace/6.usbdev_enable/latest

Test location /workspace/coverage/default/6.usbdev_endpoint_access.36561408
Short name T1824
Test name
Test status
Simulation time 930506514 ps
CPU time 2.33 seconds
Started Jul 22 05:57:09 PM PDT 24
Finished Jul 22 05:57:12 PM PDT 24
Peak memory 206824 kb
Host smart-59e191c0-3aa8-41b6-9611-a8a1ac95d423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36561
408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_endpoint_access.36561408
Directory /workspace/6.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/6.usbdev_fifo_rst.4211868804
Short name T2271
Test name
Test status
Simulation time 332867802 ps
CPU time 2.39 seconds
Started Jul 22 05:57:13 PM PDT 24
Finished Jul 22 05:57:16 PM PDT 24
Peak memory 206844 kb
Host smart-0a52fee1-f262-45d3-920b-7abcfd81436f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42118
68804 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_fifo_rst.4211868804
Directory /workspace/6.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/6.usbdev_in_iso.3679178490
Short name T1003
Test name
Test status
Simulation time 156152281 ps
CPU time 0.8 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:20 PM PDT 24
Peak memory 206748 kb
Host smart-7033dfc1-1c8f-444d-ad3e-cb748dad1697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36791
78490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_iso.3679178490
Directory /workspace/6.usbdev_in_iso/latest

Test location /workspace/coverage/default/6.usbdev_in_stall.4252957524
Short name T1943
Test name
Test status
Simulation time 150067954 ps
CPU time 0.77 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206708 kb
Host smart-2b7d0fac-5256-45bc-89c5-98c66e1abf1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42529
57524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_stall.4252957524
Directory /workspace/6.usbdev_in_stall/latest

Test location /workspace/coverage/default/6.usbdev_in_trans.3869196021
Short name T375
Test name
Test status
Simulation time 196683801 ps
CPU time 0.85 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:21 PM PDT 24
Peak memory 206756 kb
Host smart-e1b839c9-df83-42d5-8b72-32971e17953a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38691
96021 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_in_trans.3869196021
Directory /workspace/6.usbdev_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_invalid_sync.1283799312
Short name T817
Test name
Test status
Simulation time 5259422792 ps
CPU time 36.56 seconds
Started Jul 22 05:57:10 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206944 kb
Host smart-07a5ef59-6c98-46cd-a028-68b9760436b8
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1283799312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_invalid_sync.1283799312
Directory /workspace/6.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/6.usbdev_iso_retraction.2827738691
Short name T1508
Test name
Test status
Simulation time 7605723621 ps
CPU time 62.68 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206852 kb
Host smart-efd0c9df-b231-4f6b-b053-be1a36a51b0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
38691 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_iso_retraction.2827738691
Directory /workspace/6.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/6.usbdev_link_in_err.2783691583
Short name T2324
Test name
Test status
Simulation time 240105843 ps
CPU time 0.89 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206720 kb
Host smart-08237d81-930e-4641-b585-f6649f43019f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27836
91583 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_in_err.2783691583
Directory /workspace/6.usbdev_link_in_err/latest

Test location /workspace/coverage/default/6.usbdev_link_resume.2352107944
Short name T47
Test name
Test status
Simulation time 23300563575 ps
CPU time 23.88 seconds
Started Jul 22 05:57:21 PM PDT 24
Finished Jul 22 05:57:46 PM PDT 24
Peak memory 206752 kb
Host smart-45f9e0ed-d160-4fe0-96fe-4fb8adc80f47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23521
07944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_resume.2352107944
Directory /workspace/6.usbdev_link_resume/latest

Test location /workspace/coverage/default/6.usbdev_link_suspend.1440840443
Short name T2235
Test name
Test status
Simulation time 3331604160 ps
CPU time 3.86 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:23 PM PDT 24
Peak memory 206804 kb
Host smart-43c9358b-fcf3-4f1c-b4a2-41c965e4cae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14408
40443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_link_suspend.1440840443
Directory /workspace/6.usbdev_link_suspend/latest

Test location /workspace/coverage/default/6.usbdev_low_speed_traffic.671747444
Short name T1583
Test name
Test status
Simulation time 5090747094 ps
CPU time 34.53 seconds
Started Jul 22 05:57:18 PM PDT 24
Finished Jul 22 05:57:53 PM PDT 24
Peak memory 206924 kb
Host smart-4dbd0909-3135-4718-bbe1-4746e85ffb10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67174
7444 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_low_speed_traffic.671747444
Directory /workspace/6.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/6.usbdev_max_inter_pkt_delay.449772652
Short name T906
Test name
Test status
Simulation time 3583738578 ps
CPU time 101.36 seconds
Started Jul 22 05:57:18 PM PDT 24
Finished Jul 22 05:59:00 PM PDT 24
Peak memory 207072 kb
Host smart-c8fb21ff-cca4-45ec-8460-fac426e9b9a1
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=449772652 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_inter_pkt_delay.449772652
Directory /workspace/6.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_max_length_in_transaction.3131235329
Short name T2377
Test name
Test status
Simulation time 240400338 ps
CPU time 0.91 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206780 kb
Host smart-b86ce4a0-e028-4bc4-a992-fbb14ea6ab1e
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=3131235329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_in_transaction.3131235329
Directory /workspace/6.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_length_out_transaction.2810533003
Short name T2340
Test name
Test status
Simulation time 215748246 ps
CPU time 0.86 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206708 kb
Host smart-d27000b3-de2f-4bb9-8e0d-79fd304e822d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28105
33003 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_length_out_transaction.2810533003
Directory /workspace/6.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_max_usb_traffic.242302363
Short name T2307
Test name
Test status
Simulation time 5577074680 ps
CPU time 147.52 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:59:49 PM PDT 24
Peak memory 206892 kb
Host smart-7ce7b57b-f273-4a89-a6ad-815f6d089c97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24230
2363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_max_usb_traffic.242302363
Directory /workspace/6.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/6.usbdev_min_inter_pkt_delay.4209895457
Short name T1750
Test name
Test status
Simulation time 6321539658 ps
CPU time 60.54 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:58:21 PM PDT 24
Peak memory 206956 kb
Host smart-666fb7d0-6c66-4e48-8d91-7d3432b88af2
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=4209895457 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_inter_pkt_delay.4209895457
Directory /workspace/6.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/6.usbdev_min_length_in_transaction.1898970920
Short name T2036
Test name
Test status
Simulation time 152620587 ps
CPU time 0.79 seconds
Started Jul 22 05:57:22 PM PDT 24
Finished Jul 22 05:57:24 PM PDT 24
Peak memory 206700 kb
Host smart-e4bcc0d4-0c4e-4a4e-bd69-f4aafbe7b433
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1898970920 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_in_transaction.1898970920
Directory /workspace/6.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_min_length_out_transaction.3657853684
Short name T309
Test name
Test status
Simulation time 149930058 ps
CPU time 0.76 seconds
Started Jul 22 05:57:17 PM PDT 24
Finished Jul 22 05:57:18 PM PDT 24
Peak memory 206752 kb
Host smart-5b4eb64b-ee91-4fd6-b354-2d4e624e1378
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36578
53684 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_min_length_out_transaction.3657853684
Directory /workspace/6.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_nak_trans.1482199726
Short name T138
Test name
Test status
Simulation time 198297491 ps
CPU time 0.88 seconds
Started Jul 22 05:57:17 PM PDT 24
Finished Jul 22 05:57:18 PM PDT 24
Peak memory 206748 kb
Host smart-76a9c955-85d8-41fc-bef2-e01c6c7de5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14821
99726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_nak_trans.1482199726
Directory /workspace/6.usbdev_nak_trans/latest

Test location /workspace/coverage/default/6.usbdev_out_iso.2704991637
Short name T1471
Test name
Test status
Simulation time 159430133 ps
CPU time 0.81 seconds
Started Jul 22 05:57:22 PM PDT 24
Finished Jul 22 05:57:24 PM PDT 24
Peak memory 206704 kb
Host smart-cf4c8c04-251d-4dae-8a83-6af99bac9662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27049
91637 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_iso.2704991637
Directory /workspace/6.usbdev_out_iso/latest

Test location /workspace/coverage/default/6.usbdev_out_stall.1891424561
Short name T1929
Test name
Test status
Simulation time 191320813 ps
CPU time 0.8 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206712 kb
Host smart-db491ca8-9691-485c-ad8e-a4930e80302a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18914
24561 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_stall.1891424561
Directory /workspace/6.usbdev_out_stall/latest

Test location /workspace/coverage/default/6.usbdev_out_trans_nak.2675477485
Short name T832
Test name
Test status
Simulation time 192888300 ps
CPU time 0.88 seconds
Started Jul 22 05:57:23 PM PDT 24
Finished Jul 22 05:57:25 PM PDT 24
Peak memory 206704 kb
Host smart-2cf0c229-0d61-4165-a415-ea48fb18819a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754
77485 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_out_trans_nak.2675477485
Directory /workspace/6.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/6.usbdev_pending_in_trans.1706117591
Short name T1728
Test name
Test status
Simulation time 162737085 ps
CPU time 0.76 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206756 kb
Host smart-dfe74c6e-3f3f-4665-9632-7b837b3e4123
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17061
17591 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pending_in_trans.1706117591
Directory /workspace/6.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_pinflip.590685044
Short name T2129
Test name
Test status
Simulation time 201610102 ps
CPU time 0.92 seconds
Started Jul 22 05:57:21 PM PDT 24
Finished Jul 22 05:57:23 PM PDT 24
Peak memory 206684 kb
Host smart-bbdcb042-cb6f-4d9e-bfa6-728d2957a784
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=590685044 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_pinflip.590685044
Directory /workspace/6.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/6.usbdev_phy_config_usb_ref_disable.2340024406
Short name T2698
Test name
Test status
Simulation time 178637564 ps
CPU time 0.8 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:20 PM PDT 24
Peak memory 206720 kb
Host smart-10203b37-90bb-409a-99e3-0455ce93ef94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23400
24406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_config_usb_ref_disable.2340024406
Directory /workspace/6.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/6.usbdev_phy_pins_sense.1164936187
Short name T2730
Test name
Test status
Simulation time 51431727 ps
CPU time 0.69 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:22 PM PDT 24
Peak memory 206736 kb
Host smart-e7fbd581-0ac7-44ce-8dc9-5324f762de2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11649
36187 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_phy_pins_sense.1164936187
Directory /workspace/6.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/6.usbdev_pkt_buffer.899133215
Short name T2537
Test name
Test status
Simulation time 21123372684 ps
CPU time 42.93 seconds
Started Jul 22 05:57:18 PM PDT 24
Finished Jul 22 05:58:02 PM PDT 24
Peak memory 215196 kb
Host smart-bdb36151-d56c-45cb-a91e-cfc618496c6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89913
3215 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_buffer.899133215
Directory /workspace/6.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/6.usbdev_pkt_sent.2807195915
Short name T1668
Test name
Test status
Simulation time 263731322 ps
CPU time 0.92 seconds
Started Jul 22 05:57:18 PM PDT 24
Finished Jul 22 05:57:19 PM PDT 24
Peak memory 206784 kb
Host smart-3091d226-2f42-4400-bd31-6ab764a9c534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28071
95915 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_pkt_sent.2807195915
Directory /workspace/6.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_disconnects.1009915448
Short name T1091
Test name
Test status
Simulation time 9271105456 ps
CPU time 78.65 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:58:40 PM PDT 24
Peak memory 206880 kb
Host smart-daecc16e-dac7-4fba-a312-a2c56270d1a1
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1009915448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_disconnects.1009915448
Directory /workspace/6.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/6.usbdev_rand_bus_resets.800849137
Short name T157
Test name
Test status
Simulation time 21515923751 ps
CPU time 124.43 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206944 kb
Host smart-28279317-f426-4670-ae37-a1479f627e13
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=800849137 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_bus_resets.800849137
Directory /workspace/6.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/6.usbdev_rand_suspends.3128880677
Short name T1718
Test name
Test status
Simulation time 15869050070 ps
CPU time 340.11 seconds
Started Jul 22 05:57:22 PM PDT 24
Finished Jul 22 06:03:03 PM PDT 24
Peak memory 206908 kb
Host smart-82eeeea6-0c24-4bc4-bd7c-fa4f6b18f635
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3128880677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rand_suspends.3128880677
Directory /workspace/6.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/6.usbdev_random_length_in_transaction.3748046511
Short name T417
Test name
Test status
Simulation time 184562363 ps
CPU time 0.87 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:21 PM PDT 24
Peak memory 206736 kb
Host smart-d4651447-7394-4f33-8031-6f9027ee83f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37480
46511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_in_transaction.3748046511
Directory /workspace/6.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/6.usbdev_random_length_out_transaction.1283810228
Short name T2181
Test name
Test status
Simulation time 169155512 ps
CPU time 0.8 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:21 PM PDT 24
Peak memory 206752 kb
Host smart-1df3ef88-986a-4f70-a2e3-4d3010770373
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12838
10228 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_random_length_out_transaction.1283810228
Directory /workspace/6.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/6.usbdev_rx_crc_err.3266303826
Short name T1155
Test name
Test status
Simulation time 141734080 ps
CPU time 0.76 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:20 PM PDT 24
Peak memory 206748 kb
Host smart-3e878561-7e03-455d-93cb-3393ca3bf560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32663
03826 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_rx_crc_err.3266303826
Directory /workspace/6.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/6.usbdev_setup_stage.3058101338
Short name T1587
Test name
Test status
Simulation time 172049212 ps
CPU time 0.77 seconds
Started Jul 22 05:57:21 PM PDT 24
Finished Jul 22 05:57:23 PM PDT 24
Peak memory 206668 kb
Host smart-da65c74e-1e01-4be7-af2a-6ed183b3d477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30581
01338 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_stage.3058101338
Directory /workspace/6.usbdev_setup_stage/latest

Test location /workspace/coverage/default/6.usbdev_setup_trans_ignored.454434711
Short name T2084
Test name
Test status
Simulation time 167781290 ps
CPU time 0.79 seconds
Started Jul 22 05:57:23 PM PDT 24
Finished Jul 22 05:57:24 PM PDT 24
Peak memory 206692 kb
Host smart-aaa6d306-8be1-4833-b279-cb6cbf6a45f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45443
4711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_setup_trans_ignored.454434711
Directory /workspace/6.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/6.usbdev_smoke.3960682698
Short name T1955
Test name
Test status
Simulation time 213959433 ps
CPU time 0.92 seconds
Started Jul 22 05:57:19 PM PDT 24
Finished Jul 22 05:57:20 PM PDT 24
Peak memory 206716 kb
Host smart-ad8f4c82-6fd4-48cc-b320-ab82f068c357
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39606
82698 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_smoke.3960682698
Directory /workspace/6.usbdev_smoke/latest

Test location /workspace/coverage/default/6.usbdev_spurious_pids_ignored.4134613317
Short name T1245
Test name
Test status
Simulation time 4010371382 ps
CPU time 29.28 seconds
Started Jul 22 05:57:22 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206908 kb
Host smart-5bd1d268-a093-48e3-9263-6b70e47eb7db
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4134613317 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_spurious_pids_ignored.4134613317
Directory /workspace/6.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/6.usbdev_stall_priority_over_nak.547712252
Short name T740
Test name
Test status
Simulation time 180752989 ps
CPU time 0.86 seconds
Started Jul 22 05:57:59 PM PDT 24
Finished Jul 22 05:58:01 PM PDT 24
Peak memory 206712 kb
Host smart-b435abfc-eeea-437a-8cef-d6ee80159f0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54771
2252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_priority_over_nak.547712252
Directory /workspace/6.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/6.usbdev_stall_trans.3802066764
Short name T1964
Test name
Test status
Simulation time 189682052 ps
CPU time 0.85 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:21 PM PDT 24
Peak memory 206772 kb
Host smart-0e975d5e-0d62-4730-8cd9-7967422fd556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38020
66764 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stall_trans.3802066764
Directory /workspace/6.usbdev_stall_trans/latest

Test location /workspace/coverage/default/6.usbdev_stream_len_max.412114127
Short name T1111
Test name
Test status
Simulation time 755465543 ps
CPU time 1.75 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:23 PM PDT 24
Peak memory 206840 kb
Host smart-91f8c01d-997c-4424-984e-e69dab1d119e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41211
4127 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_stream_len_max.412114127
Directory /workspace/6.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/6.usbdev_streaming_out.2708561346
Short name T594
Test name
Test status
Simulation time 4043770284 ps
CPU time 27.92 seconds
Started Jul 22 05:57:20 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206868 kb
Host smart-14deb75d-ce2b-44d2-acfc-0adada8dad39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27085
61346 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.usbdev_streaming_out.2708561346
Directory /workspace/6.usbdev_streaming_out/latest

Test location /workspace/coverage/default/7.usbdev_alert_test.3195671448
Short name T1783
Test name
Test status
Simulation time 41255901 ps
CPU time 0.67 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206736 kb
Host smart-1dbd0f93-ff22-40cd-a0e0-93e59d580ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=3195671448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_alert_test.3195671448
Directory /workspace/7.usbdev_alert_test/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_disconnect.1435750906
Short name T941
Test name
Test status
Simulation time 3698061813 ps
CPU time 4.45 seconds
Started Jul 22 05:57:18 PM PDT 24
Finished Jul 22 05:57:24 PM PDT 24
Peak memory 206808 kb
Host smart-a6827032-3028-4cdb-8053-6db8d7f39025
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1435750906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_disconnect.1435750906
Directory /workspace/7.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_reset.1274686889
Short name T1693
Test name
Test status
Simulation time 13368944568 ps
CPU time 14.52 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:57:43 PM PDT 24
Peak memory 206788 kb
Host smart-195abba4-06bc-42af-abf9-140da8677df4
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1274686889 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_reset.1274686889
Directory /workspace/7.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/7.usbdev_aon_wake_resume.3811021171
Short name T428
Test name
Test status
Simulation time 23304627383 ps
CPU time 21.37 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:56 PM PDT 24
Peak memory 206888 kb
Host smart-f4b7125d-54df-4134-8883-6eba3e51d266
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3811021171 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_aon_wake_resume.3811021171
Directory /workspace/7.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/7.usbdev_av_buffer.1267061905
Short name T461
Test name
Test status
Simulation time 156869557 ps
CPU time 0.83 seconds
Started Jul 22 05:58:16 PM PDT 24
Finished Jul 22 05:58:18 PM PDT 24
Peak memory 206748 kb
Host smart-d498dadb-0111-4e33-b954-6a9ceac26081
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12670
61905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_av_buffer.1267061905
Directory /workspace/7.usbdev_av_buffer/latest

Test location /workspace/coverage/default/7.usbdev_bitstuff_err.750600111
Short name T2162
Test name
Test status
Simulation time 158563579 ps
CPU time 0.78 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:57:31 PM PDT 24
Peak memory 206752 kb
Host smart-d7b06cc5-2ebb-4ec4-a89b-8ee7b6e6fa91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75060
0111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_bitstuff_err.750600111
Directory /workspace/7.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_clear.3102675318
Short name T1229
Test name
Test status
Simulation time 524846462 ps
CPU time 1.55 seconds
Started Jul 22 05:57:30 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206836 kb
Host smart-ab910fd3-566f-444a-80e1-aec8c221497c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31026
75318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_clear.3102675318
Directory /workspace/7.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/7.usbdev_data_toggle_restore.753036064
Short name T1879
Test name
Test status
Simulation time 507626299 ps
CPU time 1.31 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206684 kb
Host smart-65441cad-ee4f-45eb-906a-d8cffdfa7655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75303
6064 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_data_toggle_restore.753036064
Directory /workspace/7.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/7.usbdev_device_address.4153687662
Short name T2612
Test name
Test status
Simulation time 17675692782 ps
CPU time 31.83 seconds
Started Jul 22 05:57:33 PM PDT 24
Finished Jul 22 05:58:06 PM PDT 24
Peak memory 206940 kb
Host smart-77d273f5-e506-4d01-b2f2-ba45ac184180
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41536
87662 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_device_address.4153687662
Directory /workspace/7.usbdev_device_address/latest

Test location /workspace/coverage/default/7.usbdev_disable_endpoint.722066480
Short name T1197
Test name
Test status
Simulation time 469568374 ps
CPU time 1.39 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:57:32 PM PDT 24
Peak memory 206748 kb
Host smart-4defbc46-7798-40c2-a640-2477e330a924
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72206
6480 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disable_endpoint.722066480
Directory /workspace/7.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/7.usbdev_disconnected.1507453532
Short name T501
Test name
Test status
Simulation time 139948606 ps
CPU time 0.74 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:57:29 PM PDT 24
Peak memory 206704 kb
Host smart-061cbdd3-19d3-4c9a-bd58-1fc4d2a94037
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15074
53532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_disconnected.1507453532
Directory /workspace/7.usbdev_disconnected/latest

Test location /workspace/coverage/default/7.usbdev_enable.2175573089
Short name T934
Test name
Test status
Simulation time 40404757 ps
CPU time 0.69 seconds
Started Jul 22 05:57:33 PM PDT 24
Finished Jul 22 05:57:34 PM PDT 24
Peak memory 206720 kb
Host smart-3bcf7ba5-a0cb-4bfc-aa6b-8072439c49c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21755
73089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_enable.2175573089
Directory /workspace/7.usbdev_enable/latest

Test location /workspace/coverage/default/7.usbdev_endpoint_access.1899576951
Short name T2495
Test name
Test status
Simulation time 1028599058 ps
CPU time 2.21 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:57:32 PM PDT 24
Peak memory 206900 kb
Host smart-90529a9c-61a1-423a-b6a9-0c444d6cfda0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18995
76951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_endpoint_access.1899576951
Directory /workspace/7.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/7.usbdev_fifo_rst.222033224
Short name T558
Test name
Test status
Simulation time 213508456 ps
CPU time 1.29 seconds
Started Jul 22 05:57:33 PM PDT 24
Finished Jul 22 05:57:35 PM PDT 24
Peak memory 206384 kb
Host smart-07a5d5fc-53dc-4302-b656-33f05e50bac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22203
3224 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_fifo_rst.222033224
Directory /workspace/7.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/7.usbdev_in_iso.471379741
Short name T2564
Test name
Test status
Simulation time 231252442 ps
CPU time 0.87 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:57:31 PM PDT 24
Peak memory 206744 kb
Host smart-cc987d1b-15b3-4935-ad6e-e4b982ec5076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47137
9741 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_iso.471379741
Directory /workspace/7.usbdev_in_iso/latest

Test location /workspace/coverage/default/7.usbdev_in_stall.3206500607
Short name T654
Test name
Test status
Simulation time 160355491 ps
CPU time 0.83 seconds
Started Jul 22 05:57:32 PM PDT 24
Finished Jul 22 05:57:34 PM PDT 24
Peak memory 206752 kb
Host smart-af095d3f-23bc-48cb-82b3-3faab9828061
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32065
00607 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_stall.3206500607
Directory /workspace/7.usbdev_in_stall/latest

Test location /workspace/coverage/default/7.usbdev_in_trans.2767286964
Short name T1857
Test name
Test status
Simulation time 251313797 ps
CPU time 0.98 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:57:30 PM PDT 24
Peak memory 206740 kb
Host smart-75994d5f-7c9d-45b9-b012-5ee9d86bf947
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27672
86964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_in_trans.2767286964
Directory /workspace/7.usbdev_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_invalid_sync.3668300111
Short name T1056
Test name
Test status
Simulation time 4703530416 ps
CPU time 143.02 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:59:53 PM PDT 24
Peak memory 206924 kb
Host smart-ed58634a-b06f-46c8-8c04-2c6f4f6846a2
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3668300111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_invalid_sync.3668300111
Directory /workspace/7.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/7.usbdev_iso_retraction.2252655323
Short name T1144
Test name
Test status
Simulation time 9766601505 ps
CPU time 31.22 seconds
Started Jul 22 05:58:04 PM PDT 24
Finished Jul 22 05:58:35 PM PDT 24
Peak memory 206904 kb
Host smart-100c569b-fffe-42c5-8195-161caa92fb66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22526
55323 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_iso_retraction.2252655323
Directory /workspace/7.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/7.usbdev_link_in_err.2971971185
Short name T1181
Test name
Test status
Simulation time 211304739 ps
CPU time 0.88 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206732 kb
Host smart-08344bdc-a724-44e5-ae98-fd9b6b126501
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29719
71185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_in_err.2971971185
Directory /workspace/7.usbdev_link_in_err/latest

Test location /workspace/coverage/default/7.usbdev_link_resume.1514112506
Short name T1285
Test name
Test status
Simulation time 23361484373 ps
CPU time 23.42 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:57:54 PM PDT 24
Peak memory 206796 kb
Host smart-b016891f-a398-48d7-b058-abaafaf0ab39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15141
12506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_resume.1514112506
Directory /workspace/7.usbdev_link_resume/latest

Test location /workspace/coverage/default/7.usbdev_link_suspend.1240442917
Short name T937
Test name
Test status
Simulation time 3293480749 ps
CPU time 3.67 seconds
Started Jul 22 05:57:30 PM PDT 24
Finished Jul 22 05:57:35 PM PDT 24
Peak memory 206996 kb
Host smart-e1a1bf7a-12e2-4ad9-9a48-625c69e71836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12404
42917 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_link_suspend.1240442917
Directory /workspace/7.usbdev_link_suspend/latest

Test location /workspace/coverage/default/7.usbdev_low_speed_traffic.332789726
Short name T1036
Test name
Test status
Simulation time 13576269513 ps
CPU time 125.3 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:59:38 PM PDT 24
Peak memory 206996 kb
Host smart-de8a43fa-710b-454c-9e0c-0b2f2b56412a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33278
9726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_low_speed_traffic.332789726
Directory /workspace/7.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/7.usbdev_max_inter_pkt_delay.1471725220
Short name T2709
Test name
Test status
Simulation time 7533498310 ps
CPU time 217.01 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 06:01:06 PM PDT 24
Peak memory 206904 kb
Host smart-0597e783-84f7-4858-8df1-d444dad3e618
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=1471725220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_inter_pkt_delay.1471725220
Directory /workspace/7.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_max_length_in_transaction.558648892
Short name T2685
Test name
Test status
Simulation time 237668904 ps
CPU time 0.88 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206712 kb
Host smart-8cb266b8-4e14-415b-859c-e77000b2a042
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=558648892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_in_transaction.558648892
Directory /workspace/7.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_length_out_transaction.727674399
Short name T1920
Test name
Test status
Simulation time 205185014 ps
CPU time 0.85 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206692 kb
Host smart-b2007ae7-038c-4c53-bf49-1d9098433551
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72767
4399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_length_out_transaction.727674399
Directory /workspace/7.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_max_usb_traffic.1291903364
Short name T645
Test name
Test status
Simulation time 4763426519 ps
CPU time 43.72 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:58:13 PM PDT 24
Peak memory 206892 kb
Host smart-ec5d1627-cb27-43d3-a595-5f83f437dd25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12919
03364 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_max_usb_traffic.1291903364
Directory /workspace/7.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/7.usbdev_min_inter_pkt_delay.934424896
Short name T2665
Test name
Test status
Simulation time 4965447577 ps
CPU time 135.95 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:59:48 PM PDT 24
Peak memory 206912 kb
Host smart-aa9d7444-e5a2-4f35-a9de-2b7a048ab3a5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=934424896 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_inter_pkt_delay.934424896
Directory /workspace/7.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/7.usbdev_min_length_in_transaction.6762676
Short name T2308
Test name
Test status
Simulation time 162570723 ps
CPU time 0.82 seconds
Started Jul 22 05:57:30 PM PDT 24
Finished Jul 22 05:57:32 PM PDT 24
Peak memory 206728 kb
Host smart-84d435d3-8313-4484-9d10-4bf11e1f0ef4
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=6762676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_in_transaction.6762676
Directory /workspace/7.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_min_length_out_transaction.2277082823
Short name T2104
Test name
Test status
Simulation time 183225101 ps
CPU time 0.86 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:34 PM PDT 24
Peak memory 206736 kb
Host smart-6fe89e1a-f7c3-415a-8c10-646ba5534f2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22770
82823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_min_length_out_transaction.2277082823
Directory /workspace/7.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_nak_trans.3650867657
Short name T2011
Test name
Test status
Simulation time 250650478 ps
CPU time 0.9 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206688 kb
Host smart-d81c8e6e-0b0f-456b-a9bf-1ebc1d057ad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36508
67657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_nak_trans.3650867657
Directory /workspace/7.usbdev_nak_trans/latest

Test location /workspace/coverage/default/7.usbdev_out_iso.1877809080
Short name T1264
Test name
Test status
Simulation time 160487577 ps
CPU time 0.77 seconds
Started Jul 22 05:57:27 PM PDT 24
Finished Jul 22 05:57:28 PM PDT 24
Peak memory 206748 kb
Host smart-820c9254-3744-4459-af4c-bca35bc645a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18778
09080 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_iso.1877809080
Directory /workspace/7.usbdev_out_iso/latest

Test location /workspace/coverage/default/7.usbdev_out_stall.2431467827
Short name T1407
Test name
Test status
Simulation time 171935609 ps
CPU time 0.79 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:34 PM PDT 24
Peak memory 206704 kb
Host smart-6711b227-6f4d-466f-9297-cbe94d81573e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24314
67827 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_stall.2431467827
Directory /workspace/7.usbdev_out_stall/latest

Test location /workspace/coverage/default/7.usbdev_out_trans_nak.812433190
Short name T1937
Test name
Test status
Simulation time 171111394 ps
CPU time 0.78 seconds
Started Jul 22 05:57:30 PM PDT 24
Finished Jul 22 05:57:32 PM PDT 24
Peak memory 206724 kb
Host smart-e00ea0da-42ca-48c0-bfcf-dbbd2b3cefe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81243
3190 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_out_trans_nak.812433190
Directory /workspace/7.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/7.usbdev_pending_in_trans.1154789802
Short name T2223
Test name
Test status
Simulation time 150895723 ps
CPU time 0.83 seconds
Started Jul 22 05:57:57 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206756 kb
Host smart-7ffd7717-0135-45fa-9869-6045a784fc24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11547
89802 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pending_in_trans.1154789802
Directory /workspace/7.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_pinflip.3552002767
Short name T1034
Test name
Test status
Simulation time 227892781 ps
CPU time 0.99 seconds
Started Jul 22 05:57:30 PM PDT 24
Finished Jul 22 05:57:32 PM PDT 24
Peak memory 206752 kb
Host smart-f9b1cb32-da4a-4049-88bc-0b1fb4aeafcc
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3552002767 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_pinflip.3552002767
Directory /workspace/7.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/7.usbdev_phy_config_usb_ref_disable.890132933
Short name T874
Test name
Test status
Simulation time 144582462 ps
CPU time 0.78 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:57:30 PM PDT 24
Peak memory 206748 kb
Host smart-1fbdd10d-ea3e-436a-b8bc-5039ef5156fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89013
2933 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_config_usb_ref_disable.890132933
Directory /workspace/7.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/7.usbdev_phy_pins_sense.3954146801
Short name T1846
Test name
Test status
Simulation time 58163286 ps
CPU time 0.72 seconds
Started Jul 22 05:57:35 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206728 kb
Host smart-7504e129-2bb5-413d-92ce-e114b3bc7ddb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39541
46801 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_phy_pins_sense.3954146801
Directory /workspace/7.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/7.usbdev_pkt_buffer.609609105
Short name T1165
Test name
Test status
Simulation time 20238584441 ps
CPU time 42.53 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:58:15 PM PDT 24
Peak memory 206976 kb
Host smart-1cb7bdb0-f2fa-4e5f-8a6a-0246b901714f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60960
9105 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_buffer.609609105
Directory /workspace/7.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/7.usbdev_pkt_received.1916568835
Short name T1237
Test name
Test status
Simulation time 171007923 ps
CPU time 0.88 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:57:31 PM PDT 24
Peak memory 206748 kb
Host smart-60fd68d4-104c-4725-8378-6476be01ca69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19165
68835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_received.1916568835
Directory /workspace/7.usbdev_pkt_received/latest

Test location /workspace/coverage/default/7.usbdev_pkt_sent.1628330832
Short name T2411
Test name
Test status
Simulation time 202431922 ps
CPU time 0.89 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:57:30 PM PDT 24
Peak memory 206728 kb
Host smart-a2816883-3047-4f2d-993b-e43f465ff40b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16283
30832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_pkt_sent.1628330832
Directory /workspace/7.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/7.usbdev_rand_bus_disconnects.3896557931
Short name T1166
Test name
Test status
Simulation time 12180259539 ps
CPU time 80.83 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:59:27 PM PDT 24
Peak memory 206924 kb
Host smart-68d2a9c3-eb54-45e0-a8bc-25b7bc04b71d
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3896557931 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_bus_disconnects.3896557931
Directory /workspace/7.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/7.usbdev_rand_suspends.2097586837
Short name T2710
Test name
Test status
Simulation time 14933333711 ps
CPU time 102.02 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:59:15 PM PDT 24
Peak memory 206924 kb
Host smart-f3b0cc78-fad7-4756-8ba0-eedb5469c657
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2097586837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rand_suspends.2097586837
Directory /workspace/7.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/7.usbdev_random_length_in_transaction.3062049872
Short name T2628
Test name
Test status
Simulation time 239549242 ps
CPU time 0.93 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206728 kb
Host smart-8d93f58b-4a1b-4dcc-ae69-cff160413b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30620
49872 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_in_transaction.3062049872
Directory /workspace/7.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/7.usbdev_random_length_out_transaction.4071862157
Short name T408
Test name
Test status
Simulation time 185597817 ps
CPU time 0.84 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206656 kb
Host smart-da074f77-2c49-4822-90c4-8c7d2524a41f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40718
62157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_random_length_out_transaction.4071862157
Directory /workspace/7.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/7.usbdev_rx_crc_err.1093726958
Short name T2502
Test name
Test status
Simulation time 197164499 ps
CPU time 0.81 seconds
Started Jul 22 05:57:30 PM PDT 24
Finished Jul 22 05:57:32 PM PDT 24
Peak memory 206912 kb
Host smart-195bb423-2609-410a-802a-7a12daa154f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10937
26958 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_rx_crc_err.1093726958
Directory /workspace/7.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/7.usbdev_setup_stage.1611239906
Short name T2406
Test name
Test status
Simulation time 195176497 ps
CPU time 0.8 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206744 kb
Host smart-4fc8abe1-f00e-454d-96e3-8eb27fac27cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16112
39906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_stage.1611239906
Directory /workspace/7.usbdev_setup_stage/latest

Test location /workspace/coverage/default/7.usbdev_setup_trans_ignored.3541710549
Short name T2394
Test name
Test status
Simulation time 150343377 ps
CPU time 0.78 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:57:30 PM PDT 24
Peak memory 206676 kb
Host smart-c89153f5-4c73-4f6f-9f3b-674a7a4cad23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417
10549 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_setup_trans_ignored.3541710549
Directory /workspace/7.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/7.usbdev_smoke.2774766793
Short name T2247
Test name
Test status
Simulation time 255820815 ps
CPU time 0.93 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206740 kb
Host smart-74142c81-48a3-45f1-baf9-cc6a45b29acc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27747
66793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_smoke.2774766793
Directory /workspace/7.usbdev_smoke/latest

Test location /workspace/coverage/default/7.usbdev_spurious_pids_ignored.2964744533
Short name T1315
Test name
Test status
Simulation time 6681890098 ps
CPU time 179.74 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 06:00:30 PM PDT 24
Peak memory 206868 kb
Host smart-7ec8ebdc-0129-4290-b51c-1fe5b42a4c49
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=2964744533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_spurious_pids_ignored.2964744533
Directory /workspace/7.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/7.usbdev_stall_priority_over_nak.2122732888
Short name T1311
Test name
Test status
Simulation time 183288607 ps
CPU time 0.83 seconds
Started Jul 22 05:57:28 PM PDT 24
Finished Jul 22 05:57:30 PM PDT 24
Peak memory 206732 kb
Host smart-125553c5-d149-4b29-9c61-64bcad6f0dbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
32888 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_priority_over_nak.2122732888
Directory /workspace/7.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/7.usbdev_stall_trans.703789825
Short name T2116
Test name
Test status
Simulation time 175188360 ps
CPU time 0.79 seconds
Started Jul 22 05:57:29 PM PDT 24
Finished Jul 22 05:57:31 PM PDT 24
Peak memory 206760 kb
Host smart-08594e74-a4ba-4582-bd28-8892aaf90477
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70378
9825 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stall_trans.703789825
Directory /workspace/7.usbdev_stall_trans/latest

Test location /workspace/coverage/default/7.usbdev_stream_len_max.1033217176
Short name T2493
Test name
Test status
Simulation time 1079189296 ps
CPU time 2.53 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:35 PM PDT 24
Peak memory 206840 kb
Host smart-87dd48c7-601a-41c1-818a-6ef2acb7b506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10332
17176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_stream_len_max.1033217176
Directory /workspace/7.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/7.usbdev_streaming_out.930462906
Short name T2745
Test name
Test status
Simulation time 5349140757 ps
CPU time 47.92 seconds
Started Jul 22 05:57:30 PM PDT 24
Finished Jul 22 05:58:19 PM PDT 24
Peak memory 206892 kb
Host smart-e3d7c707-b57f-435b-9134-0aa819e991f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93046
2906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.usbdev_streaming_out.930462906
Directory /workspace/7.usbdev_streaming_out/latest

Test location /workspace/coverage/default/8.usbdev_alert_test.1957028120
Short name T687
Test name
Test status
Simulation time 36518893 ps
CPU time 0.7 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206416 kb
Host smart-90a370b2-70d4-41ee-9871-08fbc6073645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=1957028120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_alert_test.1957028120
Directory /workspace/8.usbdev_alert_test/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_disconnect.2268643321
Short name T2430
Test name
Test status
Simulation time 3484858028 ps
CPU time 4.55 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:39 PM PDT 24
Peak memory 206832 kb
Host smart-a4c6026b-1294-4eaf-b6eb-85a7d1665780
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2268643321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_disconnect.2268643321
Directory /workspace/8.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_reset.441336736
Short name T794
Test name
Test status
Simulation time 13337202443 ps
CPU time 13.01 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:46 PM PDT 24
Peak memory 206800 kb
Host smart-8d82d517-83eb-4a77-ad5a-ae33fcaf473d
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=441336736 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_reset.441336736
Directory /workspace/8.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/8.usbdev_aon_wake_resume.269384232
Short name T933
Test name
Test status
Simulation time 23345898637 ps
CPU time 22.67 seconds
Started Jul 22 05:57:32 PM PDT 24
Finished Jul 22 05:57:56 PM PDT 24
Peak memory 206948 kb
Host smart-c755c97a-8059-4c26-8f6e-8b4a5bfed166
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=269384232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_aon_wake_resume.269384232
Directory /workspace/8.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/8.usbdev_av_buffer.2346670705
Short name T1139
Test name
Test status
Simulation time 145272659 ps
CPU time 0.8 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206772 kb
Host smart-b113edea-e231-4d7b-bdc0-8660101f1a2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23466
70705 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_av_buffer.2346670705
Directory /workspace/8.usbdev_av_buffer/latest

Test location /workspace/coverage/default/8.usbdev_bitstuff_err.3330438587
Short name T1965
Test name
Test status
Simulation time 183519672 ps
CPU time 0.86 seconds
Started Jul 22 05:57:34 PM PDT 24
Finished Jul 22 05:57:36 PM PDT 24
Peak memory 206692 kb
Host smart-497bfb17-a15a-457f-ab91-33e99aab0052
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33304
38587 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_bitstuff_err.3330438587
Directory /workspace/8.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_clear.2048624882
Short name T2063
Test name
Test status
Simulation time 342443368 ps
CPU time 1.16 seconds
Started Jul 22 05:57:31 PM PDT 24
Finished Jul 22 05:57:33 PM PDT 24
Peak memory 206740 kb
Host smart-e0abc618-0c43-44bc-95c7-f239b2122587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20486
24882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_clear.2048624882
Directory /workspace/8.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/8.usbdev_data_toggle_restore.77735515
Short name T1944
Test name
Test status
Simulation time 604609280 ps
CPU time 1.58 seconds
Started Jul 22 05:57:33 PM PDT 24
Finished Jul 22 05:57:35 PM PDT 24
Peak memory 206736 kb
Host smart-186c10cf-02ad-4108-b2c8-a2d9e291bb0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77735
515 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_data_toggle_restore.77735515
Directory /workspace/8.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/8.usbdev_device_address.1158456569
Short name T2555
Test name
Test status
Simulation time 17916176832 ps
CPU time 31.98 seconds
Started Jul 22 05:57:57 PM PDT 24
Finished Jul 22 05:58:30 PM PDT 24
Peak memory 206948 kb
Host smart-158df8f9-a882-4882-94b1-653597e40d9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11584
56569 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_device_address.1158456569
Directory /workspace/8.usbdev_device_address/latest

Test location /workspace/coverage/default/8.usbdev_disable_endpoint.3967114095
Short name T2424
Test name
Test status
Simulation time 463434828 ps
CPU time 1.41 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206752 kb
Host smart-7bd209e5-ade2-4899-86a1-ee844f263e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39671
14095 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disable_endpoint.3967114095
Directory /workspace/8.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/8.usbdev_disconnected.3897548677
Short name T2603
Test name
Test status
Simulation time 155450479 ps
CPU time 0.79 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206760 kb
Host smart-0093c109-a5b4-4f38-81db-a971803f0b55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38975
48677 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_disconnected.3897548677
Directory /workspace/8.usbdev_disconnected/latest

Test location /workspace/coverage/default/8.usbdev_enable.856911873
Short name T1558
Test name
Test status
Simulation time 39101819 ps
CPU time 0.68 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206664 kb
Host smart-336e65d2-aace-4544-afb9-f5b5359fff16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85691
1873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_enable.856911873
Directory /workspace/8.usbdev_enable/latest

Test location /workspace/coverage/default/8.usbdev_endpoint_access.3497088272
Short name T2392
Test name
Test status
Simulation time 973390511 ps
CPU time 2.19 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:41 PM PDT 24
Peak memory 206828 kb
Host smart-aca28472-1173-4437-92b2-ecb4e1fed2ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34970
88272 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_endpoint_access.3497088272
Directory /workspace/8.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/8.usbdev_fifo_rst.78706992
Short name T852
Test name
Test status
Simulation time 366309726 ps
CPU time 2.41 seconds
Started Jul 22 05:58:20 PM PDT 24
Finished Jul 22 05:58:23 PM PDT 24
Peak memory 206912 kb
Host smart-80623e43-5eaa-4f16-96b1-06e33373750d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78706
992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_fifo_rst.78706992
Directory /workspace/8.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/8.usbdev_in_iso.191288565
Short name T747
Test name
Test status
Simulation time 245613549 ps
CPU time 0.98 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:57:43 PM PDT 24
Peak memory 206740 kb
Host smart-ceb83978-20d6-49c5-aeae-b26e0636d1b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19128
8565 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_iso.191288565
Directory /workspace/8.usbdev_in_iso/latest

Test location /workspace/coverage/default/8.usbdev_in_stall.662726747
Short name T2553
Test name
Test status
Simulation time 180090330 ps
CPU time 0.78 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:57:43 PM PDT 24
Peak memory 206744 kb
Host smart-48d5fb06-9c10-431e-a44b-d63885e1207a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66272
6747 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_stall.662726747
Directory /workspace/8.usbdev_in_stall/latest

Test location /workspace/coverage/default/8.usbdev_in_trans.3880665617
Short name T1358
Test name
Test status
Simulation time 207232935 ps
CPU time 0.9 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 05:57:42 PM PDT 24
Peak memory 206712 kb
Host smart-5214ea98-7eb8-4cdb-ac7f-2d83f8c3e5e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38806
65617 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_in_trans.3880665617
Directory /workspace/8.usbdev_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_invalid_sync.344882189
Short name T722
Test name
Test status
Simulation time 9267816055 ps
CPU time 62.95 seconds
Started Jul 22 05:57:38 PM PDT 24
Finished Jul 22 05:58:41 PM PDT 24
Peak memory 206840 kb
Host smart-0f148e33-e280-4293-b86b-e60469215862
User root
Command /workspace/default/simv +wt_bad_syncs=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=344882189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_invalid_sync.344882189
Directory /workspace/8.usbdev_invalid_sync/latest

Test location /workspace/coverage/default/8.usbdev_link_in_err.644116795
Short name T1041
Test name
Test status
Simulation time 192034529 ps
CPU time 0.8 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:41 PM PDT 24
Peak memory 206732 kb
Host smart-d48ad1ff-72eb-4162-91c8-603e86900e1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64411
6795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_in_err.644116795
Directory /workspace/8.usbdev_link_in_err/latest

Test location /workspace/coverage/default/8.usbdev_link_resume.2500431455
Short name T330
Test name
Test status
Simulation time 23313041688 ps
CPU time 22.14 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:58:09 PM PDT 24
Peak memory 206780 kb
Host smart-0368ba62-5779-4c97-9c21-e157ce65702e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25004
31455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_resume.2500431455
Directory /workspace/8.usbdev_link_resume/latest

Test location /workspace/coverage/default/8.usbdev_link_suspend.2970657271
Short name T1279
Test name
Test status
Simulation time 3341668970 ps
CPU time 4.1 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:57:49 PM PDT 24
Peak memory 206812 kb
Host smart-163a60d5-4aed-4e4b-b309-035afe6f7e16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29706
57271 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_link_suspend.2970657271
Directory /workspace/8.usbdev_link_suspend/latest

Test location /workspace/coverage/default/8.usbdev_low_speed_traffic.3351773373
Short name T1628
Test name
Test status
Simulation time 6293801381 ps
CPU time 173.14 seconds
Started Jul 22 05:58:20 PM PDT 24
Finished Jul 22 06:01:14 PM PDT 24
Peak memory 206980 kb
Host smart-3d879440-64cf-4810-a580-e8deea8e3998
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33517
73373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_low_speed_traffic.3351773373
Directory /workspace/8.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/8.usbdev_max_inter_pkt_delay.2616199479
Short name T572
Test name
Test status
Simulation time 5698873203 ps
CPU time 159.62 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 06:00:20 PM PDT 24
Peak memory 206848 kb
Host smart-1f6f73b8-9a94-4cec-92ea-6c6136d05ce8
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2616199479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_inter_pkt_delay.2616199479
Directory /workspace/8.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_max_length_in_transaction.4058322880
Short name T450
Test name
Test status
Simulation time 274790678 ps
CPU time 0.91 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206744 kb
Host smart-65837b1c-f5cc-4a05-8f0b-307ea58ce1ba
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=4058322880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_in_transaction.4058322880
Directory /workspace/8.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_length_out_transaction.3853866479
Short name T1771
Test name
Test status
Simulation time 188893888 ps
CPU time 0.84 seconds
Started Jul 22 05:58:06 PM PDT 24
Finished Jul 22 05:58:07 PM PDT 24
Peak memory 206704 kb
Host smart-36cbc30f-4a80-4652-80ae-a669e9e422fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38538
66479 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_length_out_transaction.3853866479
Directory /workspace/8.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_max_usb_traffic.2552549266
Short name T2020
Test name
Test status
Simulation time 6723099506 ps
CPU time 179.21 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 06:00:40 PM PDT 24
Peak memory 206876 kb
Host smart-06e770f5-8238-4ff7-a2f2-ba432169b3e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25525
49266 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_max_usb_traffic.2552549266
Directory /workspace/8.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/8.usbdev_min_inter_pkt_delay.2673956710
Short name T1651
Test name
Test status
Simulation time 3613911008 ps
CPU time 101.07 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:59:23 PM PDT 24
Peak memory 206932 kb
Host smart-a4c48f58-a7be-4acf-9935-40f4275796ea
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=2673956710 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_inter_pkt_delay.2673956710
Directory /workspace/8.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/8.usbdev_min_length_in_transaction.3363241387
Short name T815
Test name
Test status
Simulation time 205467919 ps
CPU time 0.84 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206748 kb
Host smart-938302c6-4853-424b-8b94-699606640d37
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3363241387 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_in_transaction.3363241387
Directory /workspace/8.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_min_length_out_transaction.3338628942
Short name T1992
Test name
Test status
Simulation time 161046162 ps
CPU time 0.8 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:41 PM PDT 24
Peak memory 206748 kb
Host smart-d07ef073-7d0f-41fb-9917-36ad13a67820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33386
28942 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_min_length_out_transaction.3338628942
Directory /workspace/8.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_nak_trans.3611036429
Short name T2563
Test name
Test status
Simulation time 199638329 ps
CPU time 0.82 seconds
Started Jul 22 05:57:38 PM PDT 24
Finished Jul 22 05:57:39 PM PDT 24
Peak memory 206732 kb
Host smart-8e39a23f-eafd-4748-8677-8152ae69f6d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36110
36429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_nak_trans.3611036429
Directory /workspace/8.usbdev_nak_trans/latest

Test location /workspace/coverage/default/8.usbdev_out_iso.3543404453
Short name T2207
Test name
Test status
Simulation time 189520790 ps
CPU time 0.84 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 05:57:41 PM PDT 24
Peak memory 206744 kb
Host smart-1f98a359-15ea-4a2a-89d2-0d97ed2683d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35434
04453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_iso.3543404453
Directory /workspace/8.usbdev_out_iso/latest

Test location /workspace/coverage/default/8.usbdev_out_stall.1834821800
Short name T1274
Test name
Test status
Simulation time 184510568 ps
CPU time 0.82 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:57:45 PM PDT 24
Peak memory 206752 kb
Host smart-6fbdf88b-a573-4698-abff-67f5cfa720f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18348
21800 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_stall.1834821800
Directory /workspace/8.usbdev_out_stall/latest

Test location /workspace/coverage/default/8.usbdev_out_trans_nak.3757961755
Short name T854
Test name
Test status
Simulation time 190148925 ps
CPU time 0.8 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 05:57:45 PM PDT 24
Peak memory 206756 kb
Host smart-f1d963c3-9f46-4acf-9c29-b22084c100ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37579
61755 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_out_trans_nak.3757961755
Directory /workspace/8.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/8.usbdev_pending_in_trans.542398427
Short name T1632
Test name
Test status
Simulation time 155590378 ps
CPU time 0.83 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:57:43 PM PDT 24
Peak memory 206736 kb
Host smart-29d878c6-7da8-46d9-954c-9e0ab80b6028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54239
8427 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pending_in_trans.542398427
Directory /workspace/8.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_pinflip.342340846
Short name T2091
Test name
Test status
Simulation time 289316693 ps
CPU time 1.04 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:41 PM PDT 24
Peak memory 206712 kb
Host smart-2fbccd18-168f-4695-8471-079db4ae20ec
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=342340846 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_pinflip.342340846
Directory /workspace/8.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/8.usbdev_phy_config_usb_ref_disable.2501223904
Short name T702
Test name
Test status
Simulation time 137967132 ps
CPU time 0.8 seconds
Started Jul 22 05:57:46 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206788 kb
Host smart-6d8343e7-decd-4e4b-a1bb-d4017e32a90c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25012
23904 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_config_usb_ref_disable.2501223904
Directory /workspace/8.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/8.usbdev_phy_pins_sense.1084629103
Short name T1760
Test name
Test status
Simulation time 41789231 ps
CPU time 0.67 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206588 kb
Host smart-e7033c72-2daf-4691-ba25-c20da511ef2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10846
29103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_phy_pins_sense.1084629103
Directory /workspace/8.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/8.usbdev_pkt_buffer.2316676715
Short name T1317
Test name
Test status
Simulation time 18206085673 ps
CPU time 39.92 seconds
Started Jul 22 05:57:41 PM PDT 24
Finished Jul 22 05:58:22 PM PDT 24
Peak memory 206936 kb
Host smart-c3bb1f06-f221-411e-951b-90378093910a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23166
76715 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_buffer.2316676715
Directory /workspace/8.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/8.usbdev_pkt_received.1095774472
Short name T245
Test name
Test status
Simulation time 207306376 ps
CPU time 0.9 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 05:57:42 PM PDT 24
Peak memory 206732 kb
Host smart-cbd4cbbf-0413-40d2-bd3d-e1aff7311252
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10957
74472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_received.1095774472
Directory /workspace/8.usbdev_pkt_received/latest

Test location /workspace/coverage/default/8.usbdev_pkt_sent.4039470835
Short name T700
Test name
Test status
Simulation time 205154269 ps
CPU time 0.87 seconds
Started Jul 22 05:57:44 PM PDT 24
Finished Jul 22 05:57:47 PM PDT 24
Peak memory 206748 kb
Host smart-d0421cbe-b71c-4a82-91e3-6652822b15cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40394
70835 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_pkt_sent.4039470835
Directory /workspace/8.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_disconnects.1735350519
Short name T177
Test name
Test status
Simulation time 11772210667 ps
CPU time 76.73 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:59:02 PM PDT 24
Peak memory 206976 kb
Host smart-e823c49a-d084-49bb-a9e9-b5ed56754e18
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=1735350519 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_disconnects.1735350519
Directory /workspace/8.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/8.usbdev_rand_bus_resets.36718971
Short name T161
Test name
Test status
Simulation time 13968931410 ps
CPU time 98.86 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:59:24 PM PDT 24
Peak memory 206880 kb
Host smart-4b3918fa-82df-4594-a30a-ccf8981e0736
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=36718971 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_bus_resets.36718971
Directory /workspace/8.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/8.usbdev_rand_suspends.4282947533
Short name T895
Test name
Test status
Simulation time 24309031525 ps
CPU time 187.16 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 06:00:50 PM PDT 24
Peak memory 206832 kb
Host smart-1a416c77-6f72-455a-9acd-14667a70dedd
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=4282947533 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rand_suspends.4282947533
Directory /workspace/8.usbdev_rand_suspends/latest

Test location /workspace/coverage/default/8.usbdev_random_length_in_transaction.293817687
Short name T476
Test name
Test status
Simulation time 209587539 ps
CPU time 0.83 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:57:47 PM PDT 24
Peak memory 206752 kb
Host smart-26ca3024-cf2f-4da0-8328-6f3f88d304ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
7687 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_in_transaction.293817687
Directory /workspace/8.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/8.usbdev_random_length_out_transaction.2389264974
Short name T833
Test name
Test status
Simulation time 187061107 ps
CPU time 0.84 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:40 PM PDT 24
Peak memory 206624 kb
Host smart-ba49c450-f36e-4593-9cfd-391e79c4020b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23892
64974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_random_length_out_transaction.2389264974
Directory /workspace/8.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/8.usbdev_rx_crc_err.4229862553
Short name T79
Test name
Test status
Simulation time 171064407 ps
CPU time 0.82 seconds
Started Jul 22 05:57:46 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206764 kb
Host smart-d90178b3-24ed-422c-9997-67b86ef3177b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42298
62553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_rx_crc_err.4229862553
Directory /workspace/8.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/8.usbdev_setup_stage.416488199
Short name T1691
Test name
Test status
Simulation time 147317920 ps
CPU time 0.74 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206740 kb
Host smart-6730d101-6824-4bad-aafe-2fa693aae907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41648
8199 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_stage.416488199
Directory /workspace/8.usbdev_setup_stage/latest

Test location /workspace/coverage/default/8.usbdev_setup_trans_ignored.130853927
Short name T520
Test name
Test status
Simulation time 168768445 ps
CPU time 0.85 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:40 PM PDT 24
Peak memory 206676 kb
Host smart-86c20042-e884-4a75-a55e-f1636fc54cc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13085
3927 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_setup_trans_ignored.130853927
Directory /workspace/8.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/8.usbdev_smoke.841560762
Short name T2702
Test name
Test status
Simulation time 208917206 ps
CPU time 0.95 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:40 PM PDT 24
Peak memory 206696 kb
Host smart-7932460a-4622-439e-a6e1-973117fbcf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84156
0762 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
space/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_smoke.841560762
Directory /workspace/8.usbdev_smoke/latest

Test location /workspace/coverage/default/8.usbdev_spurious_pids_ignored.3965229111
Short name T1206
Test name
Test status
Simulation time 4057007954 ps
CPU time 108.47 seconds
Started Jul 22 05:57:46 PM PDT 24
Finished Jul 22 05:59:36 PM PDT 24
Peak memory 206864 kb
Host smart-faeb8fbe-5e34-47af-b132-eb071734aed3
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=3965229111 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_spurious_pids_ignored.3965229111
Directory /workspace/8.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/8.usbdev_stall_priority_over_nak.195991792
Short name T2433
Test name
Test status
Simulation time 177414078 ps
CPU time 0.82 seconds
Started Jul 22 05:57:39 PM PDT 24
Finished Jul 22 05:57:40 PM PDT 24
Peak memory 206756 kb
Host smart-c6d01faa-ca17-483d-851d-ef2b5e34e4d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19599
1792 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_priority_over_nak.195991792
Directory /workspace/8.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/8.usbdev_stall_trans.1339556949
Short name T364
Test name
Test status
Simulation time 172841060 ps
CPU time 0.8 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:57:45 PM PDT 24
Peak memory 206728 kb
Host smart-eeecbe59-b023-4d2c-b810-42ccfb2e7873
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13395
56949 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stall_trans.1339556949
Directory /workspace/8.usbdev_stall_trans/latest

Test location /workspace/coverage/default/8.usbdev_stream_len_max.3243716857
Short name T2276
Test name
Test status
Simulation time 269449879 ps
CPU time 1.03 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206476 kb
Host smart-b0745eca-9ad2-40c1-8bc0-18c35b3cc71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32437
16857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_stream_len_max.3243716857
Directory /workspace/8.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/8.usbdev_streaming_out.4187912659
Short name T2509
Test name
Test status
Simulation time 7285200769 ps
CPU time 50.68 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:58:36 PM PDT 24
Peak memory 206956 kb
Host smart-7099d2e4-5818-4000-83c4-05004ec4aab5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41879
12659 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.usbdev_streaming_out.4187912659
Directory /workspace/8.usbdev_streaming_out/latest

Test location /workspace/coverage/default/9.usbdev_alert_test.2481272962
Short name T2066
Test name
Test status
Simulation time 50371612 ps
CPU time 0.66 seconds
Started Jul 22 05:57:47 PM PDT 24
Finished Jul 22 05:57:49 PM PDT 24
Peak memory 206672 kb
Host smart-15451059-40aa-4465-b0c3-d2504fc32802
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.
tcl +ntb_random_seed=2481272962 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_alert_test.2481272962
Directory /workspace/9.usbdev_alert_test/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_disconnect.3609127453
Short name T1226
Test name
Test status
Simulation time 3448905728 ps
CPU time 5.39 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 05:57:46 PM PDT 24
Peak memory 206896 kb
Host smart-8645890c-170a-40cf-96f4-48c90a14e39f
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=3609127453 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_disconnect.3609127453
Directory /workspace/9.usbdev_aon_wake_disconnect/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_reset.316496968
Short name T1519
Test name
Test status
Simulation time 13356936185 ps
CPU time 16.34 seconds
Started Jul 22 05:57:46 PM PDT 24
Finished Jul 22 05:58:04 PM PDT 24
Peak memory 206920 kb
Host smart-fa80b446-1c48-47a8-9f97-26cf73bcaa17
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=316496968 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_reset.316496968
Directory /workspace/9.usbdev_aon_wake_reset/latest

Test location /workspace/coverage/default/9.usbdev_aon_wake_resume.859743281
Short name T1392
Test name
Test status
Simulation time 23417611901 ps
CPU time 23.63 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 05:58:04 PM PDT 24
Peak memory 206800 kb
Host smart-09452d45-f2e2-45dd-b810-f9e1c2259954
User root
Command /workspace/default/simv +do_resume_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=859743281 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_aon_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_aon_wake_resume.859743281
Directory /workspace/9.usbdev_aon_wake_resume/latest

Test location /workspace/coverage/default/9.usbdev_av_buffer.4117494905
Short name T946
Test name
Test status
Simulation time 188571872 ps
CPU time 0.82 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:57:45 PM PDT 24
Peak memory 206756 kb
Host smart-0f3c98bf-ec96-4f5e-8286-ff9e056e2475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41174
94905 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_av_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_av_buffer.4117494905
Directory /workspace/9.usbdev_av_buffer/latest

Test location /workspace/coverage/default/9.usbdev_bitstuff_err.2565089173
Short name T964
Test name
Test status
Simulation time 174308290 ps
CPU time 0.79 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 05:57:41 PM PDT 24
Peak memory 206752 kb
Host smart-1a68330a-a344-44b5-a9e4-d87c765be2de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25650
89173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bitstuff_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_bitstuff_err.2565089173
Directory /workspace/9.usbdev_bitstuff_err/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_clear.2104996810
Short name T635
Test name
Test status
Simulation time 383278867 ps
CPU time 1.31 seconds
Started Jul 22 05:57:37 PM PDT 24
Finished Jul 22 05:57:39 PM PDT 24
Peak memory 206744 kb
Host smart-16eb8574-39df-4d92-b04f-9533ce5f06e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21049
96810 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_clear_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_clear.2104996810
Directory /workspace/9.usbdev_data_toggle_clear/latest

Test location /workspace/coverage/default/9.usbdev_data_toggle_restore.1688692982
Short name T1061
Test name
Test status
Simulation time 896348290 ps
CPU time 1.94 seconds
Started Jul 22 05:57:44 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206812 kb
Host smart-0b04698c-4683-4c09-bf02-08814363d0a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16886
92982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_data_toggle_restore_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_data_toggle_restore.1688692982
Directory /workspace/9.usbdev_data_toggle_restore/latest

Test location /workspace/coverage/default/9.usbdev_device_address.249221445
Short name T1075
Test name
Test status
Simulation time 6910152119 ps
CPU time 13.61 seconds
Started Jul 22 05:57:44 PM PDT 24
Finished Jul 22 05:58:00 PM PDT 24
Peak memory 206888 kb
Host smart-01fd5ba6-300d-4132-875f-862e72293daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24922
1445 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_device_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_device_address.249221445
Directory /workspace/9.usbdev_device_address/latest

Test location /workspace/coverage/default/9.usbdev_disable_endpoint.1804434797
Short name T2348
Test name
Test status
Simulation time 440080216 ps
CPU time 1.36 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 05:57:45 PM PDT 24
Peak memory 206756 kb
Host smart-5efb36f4-a76a-43dc-bbc0-7654048858d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18044
34797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disable_endpoint_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disable_endpoint.1804434797
Directory /workspace/9.usbdev_disable_endpoint/latest

Test location /workspace/coverage/default/9.usbdev_disconnected.2450879880
Short name T1798
Test name
Test status
Simulation time 171289643 ps
CPU time 0.81 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:57:46 PM PDT 24
Peak memory 206768 kb
Host smart-356c0ae6-c670-466f-a8d3-1e12e8cf8b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24508
79880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_disconnected_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_disconnected.2450879880
Directory /workspace/9.usbdev_disconnected/latest

Test location /workspace/coverage/default/9.usbdev_enable.1947267183
Short name T1105
Test name
Test status
Simulation time 34045768 ps
CPU time 0.65 seconds
Started Jul 22 05:57:42 PM PDT 24
Finished Jul 22 05:57:45 PM PDT 24
Peak memory 206688 kb
Host smart-befa8bd7-a521-4412-813d-49a37334081a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19472
67183 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_enable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_enable.1947267183
Directory /workspace/9.usbdev_enable/latest

Test location /workspace/coverage/default/9.usbdev_endpoint_access.1651292253
Short name T141
Test name
Test status
Simulation time 927838911 ps
CPU time 2.49 seconds
Started Jul 22 05:57:40 PM PDT 24
Finished Jul 22 05:57:44 PM PDT 24
Peak memory 206880 kb
Host smart-02eb0b92-d43c-4372-9999-b5ccaa68db11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16512
92253 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_endpoint_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_endpoint_access.1651292253
Directory /workspace/9.usbdev_endpoint_access/latest

Test location /workspace/coverage/default/9.usbdev_fifo_rst.1275434140
Short name T1468
Test name
Test status
Simulation time 187534217 ps
CPU time 2 seconds
Started Jul 22 05:57:46 PM PDT 24
Finished Jul 22 05:57:50 PM PDT 24
Peak memory 206828 kb
Host smart-c3bcc22c-0278-49db-91bb-8838b2d032ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12754
34140 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_fifo_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_fifo_rst.1275434140
Directory /workspace/9.usbdev_fifo_rst/latest

Test location /workspace/coverage/default/9.usbdev_in_iso.2128648267
Short name T2229
Test name
Test status
Simulation time 198760226 ps
CPU time 0.89 seconds
Started Jul 22 05:57:44 PM PDT 24
Finished Jul 22 05:57:47 PM PDT 24
Peak memory 206740 kb
Host smart-0a6075ce-abfc-4f33-8ae3-2d7e3ba58b63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21286
48267 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_iso.2128648267
Directory /workspace/9.usbdev_in_iso/latest

Test location /workspace/coverage/default/9.usbdev_in_stall.652875045
Short name T1077
Test name
Test status
Simulation time 199527774 ps
CPU time 0.78 seconds
Started Jul 22 05:57:43 PM PDT 24
Finished Jul 22 05:57:46 PM PDT 24
Peak memory 206760 kb
Host smart-178b21df-c423-43c1-bbf5-c3abae27bd0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65287
5045 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_stall.652875045
Directory /workspace/9.usbdev_in_stall/latest

Test location /workspace/coverage/default/9.usbdev_in_trans.3425070501
Short name T1826
Test name
Test status
Simulation time 244274418 ps
CPU time 0.92 seconds
Started Jul 22 05:57:51 PM PDT 24
Finished Jul 22 05:57:53 PM PDT 24
Peak memory 206752 kb
Host smart-6e62aecd-d3c0-44e7-84a4-2beada92bb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34250
70501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_in_trans.3425070501
Directory /workspace/9.usbdev_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_iso_retraction.2889404258
Short name T872
Test name
Test status
Simulation time 3897927823 ps
CPU time 13.94 seconds
Started Jul 22 05:57:47 PM PDT 24
Finished Jul 22 05:58:02 PM PDT 24
Peak memory 206892 kb
Host smart-61f4877a-ab4c-4193-b714-65761e54f76e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28894
04258 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_iso_retraction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_iso_retraction.2889404258
Directory /workspace/9.usbdev_iso_retraction/latest

Test location /workspace/coverage/default/9.usbdev_link_in_err.2680784899
Short name T2358
Test name
Test status
Simulation time 223214319 ps
CPU time 0.84 seconds
Started Jul 22 05:57:48 PM PDT 24
Finished Jul 22 05:57:50 PM PDT 24
Peak memory 206740 kb
Host smart-b6962c7d-a3c3-4275-827c-d6e8938adc3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26807
84899 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_in_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_in_err.2680784899
Directory /workspace/9.usbdev_link_in_err/latest

Test location /workspace/coverage/default/9.usbdev_link_resume.3318351180
Short name T2103
Test name
Test status
Simulation time 23329925229 ps
CPU time 24.11 seconds
Started Jul 22 05:57:50 PM PDT 24
Finished Jul 22 05:58:16 PM PDT 24
Peak memory 206788 kb
Host smart-f7eabd2d-4898-42d8-8620-4a37aee33036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33183
51180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_resume_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_resume.3318351180
Directory /workspace/9.usbdev_link_resume/latest

Test location /workspace/coverage/default/9.usbdev_link_suspend.2404893577
Short name T1361
Test name
Test status
Simulation time 3328140456 ps
CPU time 4.04 seconds
Started Jul 22 05:57:48 PM PDT 24
Finished Jul 22 05:57:53 PM PDT 24
Peak memory 206860 kb
Host smart-b2ab5d1a-18d2-4f33-9d01-09caab30b3ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24048
93577 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_link_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_link_suspend.2404893577
Directory /workspace/9.usbdev_link_suspend/latest

Test location /workspace/coverage/default/9.usbdev_low_speed_traffic.1215546819
Short name T458
Test name
Test status
Simulation time 6178348039 ps
CPU time 166.02 seconds
Started Jul 22 05:57:52 PM PDT 24
Finished Jul 22 06:00:39 PM PDT 24
Peak memory 206908 kb
Host smart-133778f5-1ea0-4ad2-abf7-e4cd7fd9d2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12155
46819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_low_speed_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_low_speed_traffic.1215546819
Directory /workspace/9.usbdev_low_speed_traffic/latest

Test location /workspace/coverage/default/9.usbdev_max_inter_pkt_delay.178931259
Short name T1195
Test name
Test status
Simulation time 6546967748 ps
CPU time 64.14 seconds
Started Jul 22 05:57:47 PM PDT 24
Finished Jul 22 05:58:53 PM PDT 24
Peak memory 206952 kb
Host smart-555c4c21-0d99-480f-8eab-50b689d14319
User root
Command /workspace/default/simv +setup_data_delay=26 +out_data_delay=26 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=178931259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_inter_pkt_delay.178931259
Directory /workspace/9.usbdev_max_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_max_length_in_transaction.953270524
Short name T1784
Test name
Test status
Simulation time 244120204 ps
CPU time 0.89 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206724 kb
Host smart-9cf83236-eedc-4885-bfd3-a2f1ea6d17ab
User root
Command /workspace/default/simv +num_of_bytes=64 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_
random_seed=953270524 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_in_transaction.953270524
Directory /workspace/9.usbdev_max_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_length_out_transaction.3223279733
Short name T396
Test name
Test status
Simulation time 200325382 ps
CPU time 0.84 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:57:51 PM PDT 24
Peak memory 206748 kb
Host smart-ab8c1142-4d0e-497b-b9b0-8441508bcbeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32232
79733 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_length_out_transaction.3223279733
Directory /workspace/9.usbdev_max_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_max_usb_traffic.3285445675
Short name T2490
Test name
Test status
Simulation time 5364781960 ps
CPU time 151.49 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 06:00:22 PM PDT 24
Peak memory 206880 kb
Host smart-0d8b5769-dcdf-4afd-a81b-30d0f708e0bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32854
45675 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_max_usb_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_max_usb_traffic.3285445675
Directory /workspace/9.usbdev_max_usb_traffic/latest

Test location /workspace/coverage/default/9.usbdev_min_inter_pkt_delay.3519525250
Short name T1040
Test name
Test status
Simulation time 7990906373 ps
CPU time 62.55 seconds
Started Jul 22 05:57:47 PM PDT 24
Finished Jul 22 05:58:51 PM PDT 24
Peak memory 206976 kb
Host smart-52211b9b-aa3c-4e0d-9b27-5b5b808e4fc5
User root
Command /workspace/default/simv +setup_data_delay=8 +out_data_delay=8 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d
v/tools/sim.tcl +ntb_random_seed=3519525250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_inter_pkt_delay.3519525250
Directory /workspace/9.usbdev_min_inter_pkt_delay/latest

Test location /workspace/coverage/default/9.usbdev_min_length_in_transaction.542778396
Short name T1434
Test name
Test status
Simulation time 154598265 ps
CPU time 0.77 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206724 kb
Host smart-5d32ce92-05dd-4511-abad-45aaf7dec597
User root
Command /workspace/default/simv +num_of_bytes=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r
andom_seed=542778396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_in_transaction.542778396
Directory /workspace/9.usbdev_min_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_min_length_out_transaction.3088123951
Short name T750
Test name
Test status
Simulation time 141522043 ps
CPU time 0.76 seconds
Started Jul 22 05:57:52 PM PDT 24
Finished Jul 22 05:57:54 PM PDT 24
Peak memory 206696 kb
Host smart-0407d91d-fe96-445e-b8cb-634cad521e23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30881
23951 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_min_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_min_length_out_transaction.3088123951
Directory /workspace/9.usbdev_min_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_nak_trans.1109022547
Short name T2627
Test name
Test status
Simulation time 269588860 ps
CPU time 0.96 seconds
Started Jul 22 05:57:45 PM PDT 24
Finished Jul 22 05:57:48 PM PDT 24
Peak memory 206912 kb
Host smart-ff4dcbc6-6647-45df-b7ce-c272d7947423
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11090
22547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_nak_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_nak_trans.1109022547
Directory /workspace/9.usbdev_nak_trans/latest

Test location /workspace/coverage/default/9.usbdev_out_iso.4141455169
Short name T970
Test name
Test status
Simulation time 175020495 ps
CPU time 0.91 seconds
Started Jul 22 05:59:00 PM PDT 24
Finished Jul 22 05:59:01 PM PDT 24
Peak memory 206744 kb
Host smart-0dc89801-320a-43ad-8c19-2339d0a80d8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41414
55169 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_iso_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_iso.4141455169
Directory /workspace/9.usbdev_out_iso/latest

Test location /workspace/coverage/default/9.usbdev_out_stall.2852967408
Short name T1870
Test name
Test status
Simulation time 203123532 ps
CPU time 0.85 seconds
Started Jul 22 05:57:46 PM PDT 24
Finished Jul 22 05:57:49 PM PDT 24
Peak memory 206732 kb
Host smart-b0970f03-8c8f-4310-ae6d-7772411fc4db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28529
67408 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_stall_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_stall.2852967408
Directory /workspace/9.usbdev_out_stall/latest

Test location /workspace/coverage/default/9.usbdev_out_trans_nak.1931659592
Short name T2225
Test name
Test status
Simulation time 230604099 ps
CPU time 0.84 seconds
Started Jul 22 05:57:48 PM PDT 24
Finished Jul 22 05:57:50 PM PDT 24
Peak memory 206692 kb
Host smart-6b254b0c-d996-4270-9501-6bb8a16c8535
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19316
59592 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_out_trans_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_out_trans_nak.1931659592
Directory /workspace/9.usbdev_out_trans_nak/latest

Test location /workspace/coverage/default/9.usbdev_pending_in_trans.2857339399
Short name T2018
Test name
Test status
Simulation time 150714255 ps
CPU time 0.77 seconds
Started Jul 22 05:57:56 PM PDT 24
Finished Jul 22 05:57:58 PM PDT 24
Peak memory 206672 kb
Host smart-33d6ae19-5d5f-4474-83ff-1c570995e805
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28573
39399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pending_in_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pending_in_trans.2857339399
Directory /workspace/9.usbdev_pending_in_trans/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_pinflip.3449514997
Short name T551
Test name
Test status
Simulation time 217015553 ps
CPU time 0.95 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206760 kb
Host smart-42f06446-f6a5-4f34-ae4f-8ff0395ca45d
User root
Command /workspace/default/simv +pin_flip=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3449514997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_pinflip_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_pinflip.3449514997
Directory /workspace/9.usbdev_phy_config_pinflip/latest

Test location /workspace/coverage/default/9.usbdev_phy_config_usb_ref_disable.900425560
Short name T2250
Test name
Test status
Simulation time 157080555 ps
CPU time 0.8 seconds
Started Jul 22 05:57:44 PM PDT 24
Finished Jul 22 05:57:46 PM PDT 24
Peak memory 206748 kb
Host smart-8c9f3d8a-602c-4115-bc2a-86d6f0d6d8a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90042
5560 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_config_usb_ref_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_config_usb_ref_disable.900425560
Directory /workspace/9.usbdev_phy_config_usb_ref_disable/latest

Test location /workspace/coverage/default/9.usbdev_phy_pins_sense.1399528373
Short name T1877
Test name
Test status
Simulation time 44733394 ps
CPU time 0.69 seconds
Started Jul 22 05:57:48 PM PDT 24
Finished Jul 22 05:57:50 PM PDT 24
Peak memory 206732 kb
Host smart-3142e9d3-c767-4ea0-b8ca-2bf9a374dec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13995
28373 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_phy_pins_sense_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_phy_pins_sense.1399528373
Directory /workspace/9.usbdev_phy_pins_sense/latest

Test location /workspace/coverage/default/9.usbdev_pkt_buffer.2178389173
Short name T276
Test name
Test status
Simulation time 12630615794 ps
CPU time 26.84 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:58:24 PM PDT 24
Peak memory 206948 kb
Host smart-8cee0c29-d3dd-44ba-b6d6-7f510c616ee2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21783
89173 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_buffer_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_buffer.2178389173
Directory /workspace/9.usbdev_pkt_buffer/latest

Test location /workspace/coverage/default/9.usbdev_pkt_received.1119692109
Short name T2400
Test name
Test status
Simulation time 172870002 ps
CPU time 0.82 seconds
Started Jul 22 05:57:52 PM PDT 24
Finished Jul 22 05:57:54 PM PDT 24
Peak memory 206748 kb
Host smart-faea1f45-0f5b-48de-9160-3842a03ade2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11196
92109 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_received_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_received.1119692109
Directory /workspace/9.usbdev_pkt_received/latest

Test location /workspace/coverage/default/9.usbdev_pkt_sent.2262042892
Short name T1853
Test name
Test status
Simulation time 223852921 ps
CPU time 0.87 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:57:51 PM PDT 24
Peak memory 206688 kb
Host smart-e70ad1a0-8d82-4ddc-8503-83f70c9f33cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22620
42892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_pkt_sent_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_pkt_sent.2262042892
Directory /workspace/9.usbdev_pkt_sent/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_disconnects.2703417474
Short name T406
Test name
Test status
Simulation time 7579007939 ps
CPU time 28.14 seconds
Started Jul 22 05:57:51 PM PDT 24
Finished Jul 22 05:58:20 PM PDT 24
Peak memory 206908 kb
Host smart-cbe1e6c8-219a-427e-9977-d705b190721c
User root
Command /workspace/default/simv +do_vbus_disconnects=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2703417474 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_disconnects.2703417474
Directory /workspace/9.usbdev_rand_bus_disconnects/latest

Test location /workspace/coverage/default/9.usbdev_rand_bus_resets.2419268433
Short name T2598
Test name
Test status
Simulation time 7222788599 ps
CPU time 100.64 seconds
Started Jul 22 05:57:51 PM PDT 24
Finished Jul 22 05:59:33 PM PDT 24
Peak memory 206908 kb
Host smart-04fdfbac-52eb-42ee-965d-cfb0c2338b6f
User root
Command /workspace/default/simv +do_reset_signaling=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl
+ntb_random_seed=2419268433 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bus_rand_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rand_bus_resets.2419268433
Directory /workspace/9.usbdev_rand_bus_resets/latest

Test location /workspace/coverage/default/9.usbdev_random_length_in_transaction.1939493382
Short name T990
Test name
Test status
Simulation time 250330062 ps
CPU time 0.91 seconds
Started Jul 22 05:57:53 PM PDT 24
Finished Jul 22 05:57:55 PM PDT 24
Peak memory 206660 kb
Host smart-eafb223c-8340-437f-9edb-b7569535e17c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19394
93382 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_in_rand_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_in_transaction.1939493382
Directory /workspace/9.usbdev_random_length_in_transaction/latest

Test location /workspace/coverage/default/9.usbdev_random_length_out_transaction.370487797
Short name T1653
Test name
Test status
Simulation time 173213818 ps
CPU time 0.86 seconds
Started Jul 22 05:57:52 PM PDT 24
Finished Jul 22 05:57:54 PM PDT 24
Peak memory 206740 kb
Host smart-241bccc0-0bb8-4cfa-ad7a-88382d2cdcef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37048
7797 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_random_length_out_transaction_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_random_length_out_transaction.370487797
Directory /workspace/9.usbdev_random_length_out_transaction/latest

Test location /workspace/coverage/default/9.usbdev_rx_crc_err.566094900
Short name T621
Test name
Test status
Simulation time 140582808 ps
CPU time 0.75 seconds
Started Jul 22 05:57:48 PM PDT 24
Finished Jul 22 05:57:50 PM PDT 24
Peak memory 206740 kb
Host smart-0a92cc0a-5d90-4aab-94b2-da45074cb485
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56609
4900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_rx_crc_err_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_rx_crc_err.566094900
Directory /workspace/9.usbdev_rx_crc_err/latest

Test location /workspace/coverage/default/9.usbdev_setup_stage.3850840125
Short name T2459
Test name
Test status
Simulation time 163493317 ps
CPU time 0.79 seconds
Started Jul 22 05:57:53 PM PDT 24
Finished Jul 22 05:57:55 PM PDT 24
Peak memory 206728 kb
Host smart-f07dffe2-74a3-403f-b008-17219ab1f682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38508
40125 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_stage_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_stage.3850840125
Directory /workspace/9.usbdev_setup_stage/latest

Test location /workspace/coverage/default/9.usbdev_setup_trans_ignored.3852667973
Short name T2260
Test name
Test status
Simulation time 155199907 ps
CPU time 0.83 seconds
Started Jul 22 05:57:48 PM PDT 24
Finished Jul 22 05:57:50 PM PDT 24
Peak memory 206740 kb
Host smart-29fb5e64-24ee-4b33-989c-7a4759f4afc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38526
67973 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_setup_trans_ignored_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_setup_trans_ignored.3852667973
Directory /workspace/9.usbdev_setup_trans_ignored/latest

Test location /workspace/coverage/default/9.usbdev_smoke.3813670321
Short name T1161
Test name
Test status
Simulation time 270723137 ps
CPU time 1 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:57 PM PDT 24
Peak memory 206716 kb
Host smart-4ef509f4-a704-402a-9bd9-bbbb4c26fea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38136
70321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_smoke.3813670321
Directory /workspace/9.usbdev_smoke/latest

Test location /workspace/coverage/default/9.usbdev_spurious_pids_ignored.4007373584
Short name T2689
Test name
Test status
Simulation time 4057728555 ps
CPU time 39.6 seconds
Started Jul 22 05:57:50 PM PDT 24
Finished Jul 22 05:58:31 PM PDT 24
Peak memory 206976 kb
Host smart-df62629d-eddf-49d9-bbc4-c2cec6085355
User root
Command /workspace/default/simv +wt_spurious_pids=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n
tb_random_seed=4007373584 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_bad_traffic_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_spurious_pids_ignored.4007373584
Directory /workspace/9.usbdev_spurious_pids_ignored/latest

Test location /workspace/coverage/default/9.usbdev_stall_priority_over_nak.2217596286
Short name T1815
Test name
Test status
Simulation time 204247765 ps
CPU time 0.84 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:57:51 PM PDT 24
Peak memory 206732 kb
Host smart-c5d33547-5dd9-4941-ba26-a3e826d7313d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22175
96286 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_priority_over_nak_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_priority_over_nak.2217596286
Directory /workspace/9.usbdev_stall_priority_over_nak/latest

Test location /workspace/coverage/default/9.usbdev_stall_trans.4043618010
Short name T2245
Test name
Test status
Simulation time 146222801 ps
CPU time 0.74 seconds
Started Jul 22 05:57:49 PM PDT 24
Finished Jul 22 05:57:52 PM PDT 24
Peak memory 206736 kb
Host smart-1fb2b925-1319-4c43-86fe-0677f6c074be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
18010 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stall_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stall_trans.4043618010
Directory /workspace/9.usbdev_stall_trans/latest

Test location /workspace/coverage/default/9.usbdev_stream_len_max.2771174930
Short name T228
Test name
Test status
Simulation time 1211991716 ps
CPU time 2.39 seconds
Started Jul 22 05:57:55 PM PDT 24
Finished Jul 22 05:57:59 PM PDT 24
Peak memory 206852 kb
Host smart-fb17dd83-9c7d-4e85-8bfa-e639e90fd2a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27711
74930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_stream_len_max_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_stream_len_max.2771174930
Directory /workspace/9.usbdev_stream_len_max/latest

Test location /workspace/coverage/default/9.usbdev_streaming_out.1761537353
Short name T2538
Test name
Test status
Simulation time 5495356809 ps
CPU time 155.51 seconds
Started Jul 22 05:58:20 PM PDT 24
Finished Jul 22 06:00:56 PM PDT 24
Peak memory 206924 kb
Host smart-1326736c-aba4-48cb-8fc9-ceff5ffc49d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17615
37353 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_streaming_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.usbdev_streaming_out.1761537353
Directory /workspace/9.usbdev_streaming_out/latest
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