Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	86560	1		T1	2		T2	3		T3	2
all_values[1]	86560	1		T1	2		T2	3		T3	2
all_values[2]	86560	1		T1	2		T2	3		T3	2
all_values[3]	86560	1		T1	2		T2	3		T3	2
all_values[4]	86560	1		T1	2		T2	3		T3	2
all_values[5]	86560	1		T1	2		T2	3		T3	2
all_values[6]	86560	1		T1	2		T2	3		T3	2
all_values[7]	86560	1		T1	2		T2	3		T3	2
all_values[8]	86560	1		T1	2		T2	3		T3	2
all_values[9]	86560	1		T1	2		T2	3		T3	2
all_values[10]	86560	1		T1	2		T2	3		T3	2
all_values[11]	86560	1		T1	2		T2	3		T3	2
all_values[12]	86560	1		T1	2		T2	3		T3	2
all_values[13]	86560	1		T1	2		T2	3		T3	2
all_values[14]	86560	1		T1	2		T2	3		T3	2
all_values[15]	86560	1		T1	2		T2	3		T3	2
all_values[16]	86560	1		T1	2		T2	3		T3	2
all_values[17]	86560	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1551233	1		T1	36		T2	54		T3	34
auto[1]	6847	1		T3	2		T7	2		T19	2

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1553220	1		T1	36		T2	54		T3	36
auto[1]	4860	1		T204	121		T201	67		T202	124

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	85583	1		T1	2		T2	3		T3	2
all_values[0]	auto[0]	auto[1]	137	1		T204	2		T201	4		T202	5
all_values[0]	auto[1]	auto[0]	706	1		T48	3		T49	4		T50	4
all_values[0]	auto[1]	auto[1]	134	1		T204	5		T201	1		T202	2
all_values[1]	auto[0]	auto[0]	84756	1		T1	2		T2	3		T3	2
all_values[1]	auto[0]	auto[1]	133	1		T204	5		T202	1		T206	1
all_values[1]	auto[1]	auto[0]	1536	1		T7	2		T8	2		T20	2
all_values[1]	auto[1]	auto[1]	135	1		T204	3		T201	4		T202	5
all_values[2]	auto[0]	auto[0]	86165	1		T1	2		T2	3		T3	2
all_values[2]	auto[0]	auto[1]	125	1		T204	1		T201	1		T202	2
all_values[2]	auto[1]	auto[0]	140	1		T38	2		T39	2		T43	2
all_values[2]	auto[1]	auto[1]	130	1		T204	7		T201	3		T202	5
all_values[3]	auto[0]	auto[0]	84780	1		T1	2		T2	3		T3	2
all_values[3]	auto[0]	auto[1]	139	1		T204	5		T201	1		T202	4
all_values[3]	auto[1]	auto[0]	1508	1		T68	1484		T206	1		T273	1
all_values[3]	auto[1]	auto[1]	133	1		T204	3		T201	3		T202	4
all_values[4]	auto[0]	auto[0]	86274	1		T1	2		T2	3		T3	2
all_values[4]	auto[0]	auto[1]	119	1		T204	5		T201	4		T202	2
all_values[4]	auto[1]	auto[0]	33	1		T69	2		T202	1		T205	1
all_values[4]	auto[1]	auto[1]	134	1		T201	1		T202	4		T205	3
all_values[5]	auto[0]	auto[0]	86265	1		T1	2		T2	3		T3	2
all_values[5]	auto[0]	auto[1]	146	1		T204	1		T201	4		T202	3
all_values[5]	auto[1]	auto[0]	36	1		T204	1		T202	1		T203	2
all_values[5]	auto[1]	auto[1]	113	1		T204	5		T201	1		T202	4
all_values[6]	auto[0]	auto[0]	86260	1		T1	2		T2	3		T3	2
all_values[6]	auto[0]	auto[1]	133	1		T204	5		T201	1		T202	4
all_values[6]	auto[1]	auto[0]	29	1		T203	4		T206	1		T274	1
all_values[6]	auto[1]	auto[1]	138	1		T204	3		T201	4		T202	4
all_values[7]	auto[0]	auto[0]	86256	1		T1	2		T2	3		T3	2
all_values[7]	auto[0]	auto[1]	146	1		T204	1		T201	4		T202	5
all_values[7]	auto[1]	auto[0]	20	1		T52	2		T53	2		T54	2
all_values[7]	auto[1]	auto[1]	138	1		T204	6		T201	1		T202	3
all_values[8]	auto[0]	auto[0]	86259	1		T1	2		T2	3		T3	2
all_values[8]	auto[0]	auto[1]	125	1		T204	2		T202	4		T203	4
all_values[8]	auto[1]	auto[0]	45	1		T58	11		T201	4		T270	3
all_values[8]	auto[1]	auto[1]	131	1		T204	6		T202	4		T203	1
all_values[9]	auto[0]	auto[0]	86236	1		T1	2		T2	3		T3	2
all_values[9]	auto[0]	auto[1]	135	1		T204	6		T201	4		T205	4
all_values[9]	auto[1]	auto[0]	59	1		T65	5		T66	5		T67	5
all_values[9]	auto[1]	auto[1]	130	1		T204	2		T202	4		T205	1
all_values[10]	auto[0]	auto[0]	86261	1		T1	2		T2	3		T3	2
all_values[10]	auto[0]	auto[1]	142	1		T204	4		T201	4		T202	7
all_values[10]	auto[1]	auto[0]	24	1		T271	1		T275	2		T276	1
all_values[10]	auto[1]	auto[1]	133	1		T204	1		T202	1		T205	5
all_values[11]	auto[0]	auto[0]	86169	1		T1	2		T2	3		T30	2
all_values[11]	auto[0]	auto[1]	134	1		T201	3		T202	5		T205	3
all_values[11]	auto[1]	auto[0]	123	1		T3	2		T19	2		T73	2
all_values[11]	auto[1]	auto[1]	134	1		T201	2		T202	3		T203	4
all_values[12]	auto[0]	auto[0]	86239	1		T1	2		T2	3		T3	2
all_values[12]	auto[0]	auto[1]	159	1		T204	5		T202	1		T205	3
all_values[12]	auto[1]	auto[0]	38	1		T74	3		T77	3		T78	3
all_values[12]	auto[1]	auto[1]	124	1		T204	2		T201	4		T202	4
all_values[13]	auto[0]	auto[0]	86249	1		T1	2		T2	3		T3	2
all_values[13]	auto[0]	auto[1]	139	1		T204	4		T202	2		T205	1
all_values[13]	auto[1]	auto[0]	27	1		T201	4		T205	1		T203	1
all_values[13]	auto[1]	auto[1]	145	1		T204	4		T202	5		T205	3
all_values[14]	auto[0]	auto[0]	86261	1		T1	2		T2	3		T3	2
all_values[14]	auto[0]	auto[1]	152	1		T204	6		T202	3		T205	3
all_values[14]	auto[1]	auto[0]	32	1		T203	4		T206	1		T277	1
all_values[14]	auto[1]	auto[1]	115	1		T204	1		T201	4		T202	5
all_values[15]	auto[0]	auto[0]	86261	1		T1	2		T2	3		T3	2
all_values[15]	auto[0]	auto[1]	140	1		T204	6		T201	1		T205	3
all_values[15]	auto[1]	auto[0]	30	1		T204	2		T202	3		T205	1
all_values[15]	auto[1]	auto[1]	129	1		T201	4		T202	4		T203	4
all_values[16]	auto[0]	auto[0]	86233	1		T1	2		T2	3		T3	2
all_values[16]	auto[0]	auto[1]	134	1		T204	5		T201	4		T202	7
all_values[16]	auto[1]	auto[0]	46	1		T70	8		T71	8		T72	8
all_values[16]	auto[1]	auto[1]	147	1		T204	3		T202	1		T205	3
all_values[17]	auto[0]	auto[0]	86252	1		T1	2		T2	3		T3	2
all_values[17]	auto[0]	auto[1]	136	1		T204	2		T202	5		T205	1
all_values[17]	auto[1]	auto[0]	29	1		T59	2		T60	2		T204	1
all_values[17]	auto[1]	auto[1]	143	1		T204	5		T202	2		T205	4