Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	86560	1		T1	2		T2	3		T3	2
all_pins[1]	86560	1		T1	2		T2	3		T3	2
all_pins[2]	86560	1		T1	2		T2	3		T3	2
all_pins[3]	86560	1		T1	2		T2	3		T3	2
all_pins[4]	86560	1		T1	2		T2	3		T3	2
all_pins[5]	86560	1		T1	2		T2	3		T3	2
all_pins[6]	86560	1		T1	2		T2	3		T3	2
all_pins[7]	86560	1		T1	2		T2	3		T3	2
all_pins[8]	86560	1		T1	2		T2	3		T3	2
all_pins[9]	86560	1		T1	2		T2	3		T3	2
all_pins[10]	86560	1		T1	2		T2	3		T3	2
all_pins[11]	86560	1		T1	2		T2	3		T3	2
all_pins[12]	86560	1		T1	2		T2	3		T3	2
all_pins[13]	86560	1		T1	2		T2	3		T3	2
all_pins[14]	86560	1		T1	2		T2	3		T3	2
all_pins[15]	86560	1		T1	2		T2	3		T3	2
all_pins[16]	86560	1		T1	2		T2	3		T3	2
all_pins[17]	86560	1		T1	2		T2	3		T3	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1555868	1		T1	36		T2	54		T3	35
values[0x1]	2212	1		T3	1		T7	1		T19	1
transitions[0x0=>0x1]	1965	1		T3	1		T7	1		T19	1
transitions[0x1=>0x0]	1976	1		T3	1		T7	1		T19	1

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	86454	1		T1	2		T2	3		T3	2
all_pins[0]	values[0x1]	106	1		T49	1		T50	1		T278	1
all_pins[0]	transitions[0x0=>0x1]	87	1		T49	1		T50	1		T278	1
all_pins[0]	transitions[0x1=>0x0]	995	1		T7	1		T8	1		T20	1
all_pins[1]	values[0x0]	85546	1		T1	2		T2	3		T3	2
all_pins[1]	values[0x1]	1014	1		T7	1		T8	1		T20	1
all_pins[1]	transitions[0x0=>0x1]	998	1		T7	1		T8	1		T20	1
all_pins[1]	transitions[0x1=>0x0]	97	1		T38	1		T39	1		T43	1
all_pins[2]	values[0x0]	86447	1		T1	2		T2	3		T3	2
all_pins[2]	values[0x1]	113	1		T38	1		T39	1		T43	1
all_pins[2]	transitions[0x0=>0x1]	96	1		T38	1		T39	1		T43	1
all_pins[2]	transitions[0x1=>0x0]	47	1		T68	1		T204	2		T202	2
all_pins[3]	values[0x0]	86496	1		T1	2		T2	3		T3	2
all_pins[3]	values[0x1]	64	1		T68	1		T204	2		T202	3
all_pins[3]	transitions[0x0=>0x1]	56	1		T68	1		T204	2		T202	2
all_pins[3]	transitions[0x1=>0x0]	53	1		T69	1		T201	1		T203	2
all_pins[4]	values[0x0]	86499	1		T1	2		T2	3		T3	2
all_pins[4]	values[0x1]	61	1		T69	1		T201	1		T202	1
all_pins[4]	transitions[0x0=>0x1]	48	1		T69	1		T201	1		T202	1
all_pins[4]	transitions[0x1=>0x0]	34	1		T204	2		T205	1		T206	1
all_pins[5]	values[0x0]	86513	1		T1	2		T2	3		T3	2
all_pins[5]	values[0x1]	47	1		T204	2		T205	1		T203	2
all_pins[5]	transitions[0x0=>0x1]	32	1		T204	2		T205	1		T203	2
all_pins[5]	transitions[0x1=>0x0]	56	1		T201	3		T202	4		T277	2
all_pins[6]	values[0x0]	86489	1		T1	2		T2	3		T3	2
all_pins[6]	values[0x1]	71	1		T201	3		T202	4		T277	2
all_pins[6]	transitions[0x0=>0x1]	59	1		T201	2		T202	3		T277	1
all_pins[6]	transitions[0x1=>0x0]	54	1		T52	1		T53	1		T54	1
all_pins[7]	values[0x0]	86494	1		T1	2		T2	3		T3	2
all_pins[7]	values[0x1]	66	1		T52	1		T53	1		T54	1
all_pins[7]	transitions[0x0=>0x1]	54	1		T52	1		T53	1		T54	1
all_pins[7]	transitions[0x1=>0x0]	38	1		T58	1		T204	1		T202	3
all_pins[8]	values[0x0]	86510	1		T1	2		T2	3		T3	2
all_pins[8]	values[0x1]	50	1		T58	1		T204	1		T202	4
all_pins[8]	transitions[0x0=>0x1]	41	1		T58	1		T204	1		T202	3
all_pins[8]	transitions[0x1=>0x0]	64	1		T65	2		T66	2		T67	2
all_pins[9]	values[0x0]	86487	1		T1	2		T2	3		T3	2
all_pins[9]	values[0x1]	73	1		T65	2		T66	2		T67	2
all_pins[9]	transitions[0x0=>0x1]	65	1		T65	2		T66	2		T67	2
all_pins[9]	transitions[0x1=>0x0]	51	1		T204	1		T205	4		T203	1
all_pins[10]	values[0x0]	86501	1		T1	2		T2	3		T3	2
all_pins[10]	values[0x1]	59	1		T204	1		T205	4		T203	1
all_pins[10]	transitions[0x0=>0x1]	44	1		T204	1		T205	4		T206	1
all_pins[10]	transitions[0x1=>0x0]	97	1		T3	1		T19	1		T73	1
all_pins[11]	values[0x0]	86448	1		T1	2		T2	3		T3	1
all_pins[11]	values[0x1]	112	1		T3	1		T19	1		T73	1
all_pins[11]	transitions[0x0=>0x1]	94	1		T3	1		T19	1		T73	1
all_pins[11]	transitions[0x1=>0x0]	42	1		T74	1		T77	1		T78	1
all_pins[12]	values[0x0]	86500	1		T1	2		T2	3		T3	2
all_pins[12]	values[0x1]	60	1		T74	1		T77	1		T78	1
all_pins[12]	transitions[0x0=>0x1]	50	1		T74	1		T77	1		T78	1
all_pins[12]	transitions[0x1=>0x0]	47	1		T204	2		T202	1		T205	2
all_pins[13]	values[0x0]	86503	1		T1	2		T2	3		T3	2
all_pins[13]	values[0x1]	57	1		T204	2		T202	1		T205	2
all_pins[13]	transitions[0x0=>0x1]	45	1		T204	2		T202	1		T205	2
all_pins[13]	transitions[0x1=>0x0]	43	1		T204	1		T201	3		T202	2
all_pins[14]	values[0x0]	86505	1		T1	2		T2	3		T3	2
all_pins[14]	values[0x1]	55	1		T204	1		T201	3		T202	2
all_pins[14]	transitions[0x0=>0x1]	40	1		T204	1		T202	2		T205	1
all_pins[14]	transitions[0x1=>0x0]	48	1		T202	3		T203	3		T206	1
all_pins[15]	values[0x0]	86497	1		T1	2		T2	3		T3	2
all_pins[15]	values[0x1]	63	1		T201	3		T202	3		T203	3
all_pins[15]	transitions[0x0=>0x1]	50	1		T201	3		T202	3		T203	3
all_pins[15]	transitions[0x1=>0x0]	70	1		T70	4		T71	4		T72	4
all_pins[16]	values[0x0]	86477	1		T1	2		T2	3		T3	2
all_pins[16]	values[0x1]	83	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x0=>0x1]	69	1		T70	4		T71	4		T72	4
all_pins[16]	transitions[0x1=>0x0]	44	1		T59	1		T60	1		T204	1
all_pins[17]	values[0x0]	86502	1		T1	2		T2	3		T3	2
all_pins[17]	values[0x1]	58	1		T59	1		T60	1		T204	2
all_pins[17]	transitions[0x0=>0x1]	37	1		T59	1		T60	1		T204	2
all_pins[17]	transitions[0x1=>0x0]	96	1		T49	1		T50	1		T278	1