Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1		T204	7		T201	4		T202	7
all_values[1]	278	1		T204	7		T201	4		T202	7
all_values[2]	278	1		T204	7		T201	4		T202	7
all_values[3]	278	1		T204	7		T201	4		T202	7
all_values[4]	278	1		T204	7		T201	4		T202	7
all_values[5]	278	1		T204	7		T201	4		T202	7
all_values[6]	278	1		T204	7		T201	4		T202	7
all_values[7]	278	1		T204	7		T201	4		T202	7
all_values[8]	278	1		T204	7		T201	4		T202	7
all_values[9]	278	1		T204	7		T201	4		T202	7
all_values[10]	278	1		T204	7		T201	4		T202	7
all_values[11]	278	1		T204	7		T201	4		T202	7
all_values[12]	278	1		T204	7		T201	4		T202	7
all_values[13]	278	1		T204	7		T201	4		T202	7
all_values[14]	278	1		T204	7		T201	4		T202	7
all_values[15]	278	1		T204	7		T201	4		T202	7
all_values[16]	278	1		T204	7		T201	4		T202	7
all_values[17]	278	1		T204	7		T201	4		T202	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2720	1		T204	70		T201	44		T202	62
auto[1]	2284	1		T204	56		T201	28		T202	64

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	970	1		T204	22		T201	20		T202	20
auto[1]	4034	1		T204	104		T201	52		T202	106

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2985	1		T204	85		T201	46		T202	72
auto[1]	2019	1		T204	41		T201	26		T202	54

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	28	1		T202	1		T270	1		T276	2
all_values[0]	auto[0]	auto[0]	auto[1]	60	1		T204	1		T201	2		T202	1
all_values[0]	auto[0]	auto[1]	auto[0]	26	1		T204	1		T277	1		T271	2
all_values[0]	auto[0]	auto[1]	auto[1]	50	1		T204	3		T201	1		T205	3
all_values[0]	auto[1]	auto[0]	auto[1]	63	1		T204	1		T201	1		T202	4
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T204	1		T202	1		T205	1
all_values[1]	auto[0]	auto[0]	auto[0]	29	1		T201	1		T203	3		T206	1
all_values[1]	auto[0]	auto[0]	auto[1]	57	1		T204	2		T206	1		T277	3
all_values[1]	auto[0]	auto[1]	auto[0]	28	1		T202	2		T203	1		T206	1
all_values[1]	auto[0]	auto[1]	auto[1]	48	1		T204	1		T201	1		T202	3
all_values[1]	auto[1]	auto[0]	auto[1]	56	1		T204	3		T206	1		T277	3
all_values[1]	auto[1]	auto[1]	auto[1]	60	1		T204	1		T201	2		T202	2
all_values[2]	auto[0]	auto[0]	auto[0]	37	1		T201	1		T203	1		T279	1
all_values[2]	auto[0]	auto[0]	auto[1]	52	1		T204	1		T206	1		T277	3
all_values[2]	auto[0]	auto[1]	auto[0]	30	1		T202	1		T271	1		T279	2
all_values[2]	auto[0]	auto[1]	auto[1]	52	1		T204	4		T201	2		T202	3
all_values[2]	auto[1]	auto[0]	auto[1]	50	1		T204	1		T201	1		T202	1
all_values[2]	auto[1]	auto[1]	auto[1]	57	1		T204	1		T202	2		T205	2
all_values[3]	auto[0]	auto[0]	auto[0]	36	1		T201	1		T206	5		T274	1
all_values[3]	auto[0]	auto[0]	auto[1]	55	1		T204	2		T202	3		T203	3
all_values[3]	auto[0]	auto[1]	auto[0]	16	1		T280	2		T281	1		T282	1
all_values[3]	auto[0]	auto[1]	auto[1]	59	1		T204	4		T201	2		T202	1
all_values[3]	auto[1]	auto[0]	auto[1]	56	1		T201	1		T203	1		T206	1
all_values[3]	auto[1]	auto[1]	auto[1]	56	1		T204	1		T202	3		T205	2
all_values[4]	auto[0]	auto[0]	auto[0]	43	1		T204	3		T202	1		T203	2
all_values[4]	auto[0]	auto[0]	auto[1]	52	1		T204	3		T201	2		T202	2
all_values[4]	auto[0]	auto[1]	auto[0]	25	1		T202	1		T205	2		T270	1
all_values[4]	auto[0]	auto[1]	auto[1]	58	1		T202	2		T205	1		T203	1
all_values[4]	auto[1]	auto[0]	auto[1]	64	1		T204	1		T201	1		T203	1
all_values[4]	auto[1]	auto[1]	auto[1]	36	1		T201	1		T202	1		T205	1
all_values[5]	auto[0]	auto[0]	auto[0]	31	1		T205	1		T203	1		T274	1
all_values[5]	auto[0]	auto[0]	auto[1]	66	1		T204	1		T201	3		T202	1
all_values[5]	auto[0]	auto[1]	auto[0]	33	1		T204	2		T202	1		T203	1
all_values[5]	auto[0]	auto[1]	auto[1]	49	1		T204	3		T202	2		T203	1
all_values[5]	auto[1]	auto[0]	auto[1]	51	1		T201	1		T202	2		T205	2
all_values[5]	auto[1]	auto[1]	auto[1]	48	1		T204	1		T202	1		T203	1
all_values[6]	auto[0]	auto[0]	auto[0]	33	1		T203	1		T206	2		T277	1
all_values[6]	auto[0]	auto[0]	auto[1]	54	1		T204	3		T202	2		T205	3
all_values[6]	auto[0]	auto[1]	auto[0]	20	1		T203	3		T274	1		T279	1
all_values[6]	auto[0]	auto[1]	auto[1]	55	1		T204	2		T201	2		T202	1
all_values[6]	auto[1]	auto[0]	auto[1]	55	1		T204	2		T201	1		T202	1
all_values[6]	auto[1]	auto[1]	auto[1]	61	1		T201	1		T202	3		T206	1
all_values[7]	auto[0]	auto[0]	auto[0]	31	1		T277	1		T270	1		T274	3
all_values[7]	auto[0]	auto[0]	auto[1]	67	1		T204	2		T201	2		T202	3
all_values[7]	auto[0]	auto[1]	auto[0]	11	1		T204	1		T274	1		T271	1
all_values[7]	auto[0]	auto[1]	auto[1]	52	1		T204	1		T202	1		T205	1
all_values[7]	auto[1]	auto[0]	auto[1]	65	1		T201	1		T202	1		T205	1
all_values[7]	auto[1]	auto[1]	auto[1]	52	1		T204	3		T201	1		T202	2
all_values[8]	auto[0]	auto[0]	auto[0]	37	1		T201	1		T205	4		T277	1
all_values[8]	auto[0]	auto[0]	auto[1]	46	1		T204	1		T202	1		T203	1
all_values[8]	auto[0]	auto[1]	auto[0]	27	1		T201	3		T270	2		T275	2
all_values[8]	auto[0]	auto[1]	auto[1]	65	1		T204	5		T203	2		T270	2
all_values[8]	auto[1]	auto[0]	auto[1]	54	1		T202	2		T203	1		T206	4
all_values[8]	auto[1]	auto[1]	auto[1]	49	1		T204	1		T202	4		T206	2
all_values[9]	auto[0]	auto[0]	auto[0]	30	1		T201	1		T202	1		T203	1
all_values[9]	auto[0]	auto[0]	auto[1]	63	1		T204	3		T201	2		T205	2
all_values[9]	auto[0]	auto[1]	auto[0]	28	1		T202	3		T271	2		T279	4
all_values[9]	auto[0]	auto[1]	auto[1]	51	1		T204	2		T202	1		T203	1
all_values[9]	auto[1]	auto[0]	auto[1]	62	1		T204	2		T201	1		T205	2
all_values[9]	auto[1]	auto[1]	auto[1]	44	1		T202	2		T206	1		T277	1
all_values[10]	auto[0]	auto[0]	auto[0]	27	1		T204	3		T201	1		T279	1
all_values[10]	auto[0]	auto[0]	auto[1]	61	1		T204	2		T201	1		T202	5
all_values[10]	auto[0]	auto[1]	auto[0]	21	1		T271	1		T275	3		T276	2
all_values[10]	auto[0]	auto[1]	auto[1]	60	1		T205	2		T203	1		T206	3
all_values[10]	auto[1]	auto[0]	auto[1]	64	1		T204	1		T201	2		T202	2
all_values[10]	auto[1]	auto[1]	auto[1]	45	1		T204	1		T205	2		T203	1
all_values[11]	auto[0]	auto[0]	auto[0]	35	1		T204	3		T205	2		T206	1
all_values[11]	auto[0]	auto[0]	auto[1]	61	1		T201	1		T202	1		T205	1
all_values[11]	auto[0]	auto[1]	auto[0]	21	1		T204	4		T274	1		T280	2
all_values[11]	auto[0]	auto[1]	auto[1]	52	1		T201	1		T202	2		T203	1
all_values[11]	auto[1]	auto[0]	auto[1]	61	1		T201	2		T202	2		T205	1
all_values[11]	auto[1]	auto[1]	auto[1]	48	1		T202	2		T270	3		T274	1
all_values[12]	auto[0]	auto[0]	auto[0]	26	1		T204	1		T201	1		T202	3
all_values[12]	auto[0]	auto[0]	auto[1]	61	1		T204	2		T205	1		T203	1
all_values[12]	auto[0]	auto[1]	auto[0]	18	1		T270	1		T279	2		T280	5
all_values[12]	auto[0]	auto[1]	auto[1]	58	1		T204	1		T201	1		T202	1
all_values[12]	auto[1]	auto[0]	auto[1]	70	1		T204	2		T202	2		T205	2
all_values[12]	auto[1]	auto[1]	auto[1]	45	1		T204	1		T201	2		T202	1
all_values[13]	auto[0]	auto[0]	auto[0]	22	1		T201	2		T202	1		T203	1
all_values[13]	auto[0]	auto[0]	auto[1]	61	1		T202	1		T270	4		T271	1
all_values[13]	auto[0]	auto[1]	auto[0]	18	1		T201	2		T205	1		T277	4
all_values[13]	auto[0]	auto[1]	auto[1]	52	1		T204	2		T202	3		T205	1
all_values[13]	auto[1]	auto[0]	auto[1]	71	1		T204	4		T202	2		T203	2
all_values[13]	auto[1]	auto[1]	auto[1]	54	1		T204	1		T205	2		T206	1
all_values[14]	auto[0]	auto[0]	auto[0]	37	1		T204	1		T201	1		T203	1
all_values[14]	auto[0]	auto[0]	auto[1]	59	1		T204	3		T202	1		T205	2
all_values[14]	auto[0]	auto[1]	auto[0]	20	1		T203	3		T277	1		T271	1
all_values[14]	auto[0]	auto[1]	auto[1]	42	1		T201	1		T202	2		T206	1
all_values[14]	auto[1]	auto[0]	auto[1]	71	1		T204	3		T202	2		T206	3
all_values[14]	auto[1]	auto[1]	auto[1]	49	1		T201	2		T202	2		T205	2
all_values[15]	auto[0]	auto[0]	auto[0]	32	1		T202	1		T205	2		T203	1
all_values[15]	auto[0]	auto[0]	auto[1]	53	1		T204	2		T205	1		T206	3
all_values[15]	auto[0]	auto[1]	auto[0]	25	1		T204	2		T202	3		T277	1
all_values[15]	auto[0]	auto[1]	auto[1]	48	1		T201	1		T202	1		T203	1
all_values[15]	auto[1]	auto[0]	auto[1]	70	1		T204	3		T201	1		T205	1
all_values[15]	auto[1]	auto[1]	auto[1]	50	1		T201	2		T202	2		T203	2
all_values[16]	auto[0]	auto[0]	auto[0]	33	1		T201	1		T205	1		T203	1
all_values[16]	auto[0]	auto[0]	auto[1]	64	1		T204	5		T201	1		T202	4
all_values[16]	auto[0]	auto[1]	auto[0]	12	1		T270	1		T275	1		T283	2
all_values[16]	auto[0]	auto[1]	auto[1]	56	1		T202	1		T205	1		T203	1
all_values[16]	auto[1]	auto[0]	auto[1]	50	1		T204	1		T201	2		T202	2
all_values[16]	auto[1]	auto[1]	auto[1]	63	1		T204	1		T205	1		T206	2
all_values[17]	auto[0]	auto[0]	auto[0]	27	1		T201	4		T202	1		T203	1
all_values[17]	auto[0]	auto[0]	auto[1]	63	1		T202	3		T203	2		T206	1
all_values[17]	auto[0]	auto[1]	auto[0]	17	1		T204	1		T270	2		T271	1
all_values[17]	auto[0]	auto[1]	auto[1]	53	1		T204	2		T205	2		T206	1
all_values[17]	auto[1]	auto[0]	auto[1]	58	1		T204	2		T202	2		T203	1
all_values[17]	auto[1]	auto[1]	auto[1]	60	1		T204	2		T202	1		T205	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal